1 | /* |
2 | * Copyright 2022 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | #ifndef _mmhub_1_8_0_SH_MASK_HEADER |
24 | #define |
25 | |
26 | |
27 | // addressBlock: aid_mmhub_dagb_dagbdec0 |
28 | //DAGB0_RDCLI0 |
29 | #define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0 |
30 | #define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 |
31 | #define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4 |
32 | #define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8 |
33 | #define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc |
34 | #define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd |
35 | #define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 |
36 | #define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16 |
37 | #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 |
38 | #define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a |
39 | #define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L |
40 | #define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L |
41 | #define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L |
42 | #define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L |
43 | #define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L |
44 | #define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L |
45 | #define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L |
46 | #define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L |
47 | #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L |
48 | #define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L |
49 | //DAGB0_RDCLI1 |
50 | #define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0 |
51 | #define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 |
52 | #define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4 |
53 | #define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8 |
54 | #define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc |
55 | #define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd |
56 | #define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 |
57 | #define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16 |
58 | #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 |
59 | #define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a |
60 | #define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L |
61 | #define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L |
62 | #define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L |
63 | #define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L |
64 | #define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L |
65 | #define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L |
66 | #define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L |
67 | #define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L |
68 | #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L |
69 | #define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L |
70 | //DAGB0_RDCLI2 |
71 | #define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0 |
72 | #define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 |
73 | #define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4 |
74 | #define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8 |
75 | #define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc |
76 | #define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd |
77 | #define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 |
78 | #define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16 |
79 | #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 |
80 | #define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a |
81 | #define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L |
82 | #define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L |
83 | #define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L |
84 | #define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L |
85 | #define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L |
86 | #define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L |
87 | #define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L |
88 | #define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L |
89 | #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L |
90 | #define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L |
91 | //DAGB0_RDCLI3 |
92 | #define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0 |
93 | #define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 |
94 | #define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4 |
95 | #define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8 |
96 | #define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc |
97 | #define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd |
98 | #define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 |
99 | #define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16 |
100 | #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 |
101 | #define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a |
102 | #define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L |
103 | #define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L |
104 | #define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L |
105 | #define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L |
106 | #define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L |
107 | #define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L |
108 | #define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L |
109 | #define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L |
110 | #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L |
111 | #define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L |
112 | //DAGB0_RDCLI4 |
113 | #define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0 |
114 | #define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 |
115 | #define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4 |
116 | #define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8 |
117 | #define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc |
118 | #define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd |
119 | #define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 |
120 | #define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16 |
121 | #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 |
122 | #define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a |
123 | #define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L |
124 | #define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L |
125 | #define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L |
126 | #define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L |
127 | #define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L |
128 | #define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L |
129 | #define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L |
130 | #define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L |
131 | #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L |
132 | #define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L |
133 | //DAGB0_RDCLI5 |
134 | #define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0 |
135 | #define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 |
136 | #define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4 |
137 | #define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8 |
138 | #define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc |
139 | #define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd |
140 | #define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 |
141 | #define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16 |
142 | #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 |
143 | #define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a |
144 | #define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L |
145 | #define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L |
146 | #define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L |
147 | #define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L |
148 | #define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L |
149 | #define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L |
150 | #define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L |
151 | #define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L |
152 | #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L |
153 | #define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L |
154 | //DAGB0_RDCLI6 |
155 | #define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0 |
156 | #define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 |
157 | #define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4 |
158 | #define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8 |
159 | #define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc |
160 | #define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd |
161 | #define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 |
162 | #define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16 |
163 | #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 |
164 | #define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a |
165 | #define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L |
166 | #define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L |
167 | #define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L |
168 | #define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L |
169 | #define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L |
170 | #define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L |
171 | #define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L |
172 | #define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L |
173 | #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L |
174 | #define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L |
175 | //DAGB0_RDCLI7 |
176 | #define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0 |
177 | #define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 |
178 | #define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4 |
179 | #define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8 |
180 | #define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc |
181 | #define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd |
182 | #define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 |
183 | #define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16 |
184 | #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 |
185 | #define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a |
186 | #define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L |
187 | #define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L |
188 | #define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L |
189 | #define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L |
190 | #define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L |
191 | #define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L |
192 | #define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L |
193 | #define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L |
194 | #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L |
195 | #define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L |
196 | //DAGB0_RDCLI8 |
197 | #define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0 |
198 | #define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 |
199 | #define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4 |
200 | #define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8 |
201 | #define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc |
202 | #define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd |
203 | #define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 |
204 | #define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16 |
205 | #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 |
206 | #define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a |
207 | #define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L |
208 | #define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L |
209 | #define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L |
210 | #define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L |
211 | #define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L |
212 | #define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L |
213 | #define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L |
214 | #define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L |
215 | #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L |
216 | #define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L |
217 | //DAGB0_RDCLI9 |
218 | #define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0 |
219 | #define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 |
220 | #define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4 |
221 | #define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8 |
222 | #define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc |
223 | #define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd |
224 | #define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 |
225 | #define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16 |
226 | #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 |
227 | #define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a |
228 | #define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L |
229 | #define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L |
230 | #define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L |
231 | #define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L |
232 | #define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L |
233 | #define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L |
234 | #define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L |
235 | #define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L |
236 | #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L |
237 | #define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L |
238 | //DAGB0_RDCLI10 |
239 | #define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0 |
240 | #define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 |
241 | #define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4 |
242 | #define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8 |
243 | #define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc |
244 | #define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd |
245 | #define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 |
246 | #define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16 |
247 | #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 |
248 | #define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a |
249 | #define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L |
250 | #define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L |
251 | #define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L |
252 | #define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L |
253 | #define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L |
254 | #define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L |
255 | #define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L |
256 | #define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L |
257 | #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L |
258 | #define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L |
259 | //DAGB0_RDCLI11 |
260 | #define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0 |
261 | #define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 |
262 | #define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4 |
263 | #define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8 |
264 | #define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc |
265 | #define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd |
266 | #define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 |
267 | #define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16 |
268 | #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 |
269 | #define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a |
270 | #define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L |
271 | #define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L |
272 | #define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L |
273 | #define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L |
274 | #define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L |
275 | #define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L |
276 | #define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L |
277 | #define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L |
278 | #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L |
279 | #define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L |
280 | //DAGB0_RDCLI12 |
281 | #define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0 |
282 | #define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 |
283 | #define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4 |
284 | #define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8 |
285 | #define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc |
286 | #define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd |
287 | #define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 |
288 | #define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16 |
289 | #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 |
290 | #define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a |
291 | #define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L |
292 | #define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L |
293 | #define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L |
294 | #define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L |
295 | #define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L |
296 | #define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L |
297 | #define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L |
298 | #define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L |
299 | #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L |
300 | #define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L |
301 | //DAGB0_RDCLI13 |
302 | #define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0 |
303 | #define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 |
304 | #define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4 |
305 | #define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8 |
306 | #define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc |
307 | #define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd |
308 | #define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 |
309 | #define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16 |
310 | #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 |
311 | #define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a |
312 | #define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L |
313 | #define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L |
314 | #define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L |
315 | #define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L |
316 | #define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L |
317 | #define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L |
318 | #define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L |
319 | #define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L |
320 | #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L |
321 | #define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L |
322 | //DAGB0_RDCLI14 |
323 | #define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0 |
324 | #define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 |
325 | #define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4 |
326 | #define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8 |
327 | #define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc |
328 | #define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd |
329 | #define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 |
330 | #define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16 |
331 | #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 |
332 | #define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a |
333 | #define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L |
334 | #define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L |
335 | #define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L |
336 | #define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L |
337 | #define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L |
338 | #define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L |
339 | #define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L |
340 | #define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L |
341 | #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L |
342 | #define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L |
343 | //DAGB0_RDCLI15 |
344 | #define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0 |
345 | #define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 |
346 | #define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4 |
347 | #define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8 |
348 | #define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc |
349 | #define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd |
350 | #define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 |
351 | #define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16 |
352 | #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 |
353 | #define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a |
354 | #define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L |
355 | #define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L |
356 | #define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L |
357 | #define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L |
358 | #define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L |
359 | #define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L |
360 | #define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L |
361 | #define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L |
362 | #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L |
363 | #define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L |
364 | //DAGB0_RD_CNTL |
365 | #define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT 0x0 |
366 | #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 |
367 | #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa |
368 | #define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 |
369 | #define DAGB0_RD_CNTL__IO_LEVEL__SHIFT 0x11 |
370 | #define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 |
371 | #define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 |
372 | #define DAGB0_RD_CNTL__FIX_JUMP__SHIFT 0x1a |
373 | #define DAGB0_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL |
374 | #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L |
375 | #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L |
376 | #define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L |
377 | #define DAGB0_RD_CNTL__IO_LEVEL_MASK 0x000E0000L |
378 | #define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L |
379 | #define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L |
380 | #define DAGB0_RD_CNTL__FIX_JUMP_MASK 0x04000000L |
381 | //DAGB0_RD_GMI_CNTL |
382 | #define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 |
383 | #define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT 0x6 |
384 | #define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 |
385 | #define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd |
386 | #define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL |
387 | #define DAGB0_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L |
388 | #define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L |
389 | #define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L |
390 | //DAGB0_RD_ADDR_DAGB |
391 | #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 |
392 | #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 |
393 | #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 |
394 | #define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 |
395 | #define DAGB0_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd |
396 | #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L |
397 | #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L |
398 | #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L |
399 | #define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L |
400 | #define DAGB0_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L |
401 | //DAGB0_RD_OUTPUT_DAGB_MAX_BURST |
402 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 |
403 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 |
404 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 |
405 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc |
406 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 |
407 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 |
408 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 |
409 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c |
410 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL |
411 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L |
412 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L |
413 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L |
414 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L |
415 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L |
416 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L |
417 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L |
418 | //DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER |
419 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 |
420 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 |
421 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 |
422 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc |
423 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 |
424 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 |
425 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 |
426 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c |
427 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL |
428 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L |
429 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L |
430 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L |
431 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L |
432 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L |
433 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L |
434 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L |
435 | //DAGB0_RD_CGTT_CLK_CTRL |
436 | #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
437 | #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
438 | #define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
439 | #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
440 | #define DAGB0_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
441 | #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
442 | #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
443 | #define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
444 | #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
445 | #define DAGB0_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
446 | //DAGB0_L1TLB_RD_CGTT_CLK_CTRL |
447 | #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
448 | #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
449 | #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
450 | #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
451 | #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
452 | #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
453 | #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
454 | #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
455 | #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
456 | #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
457 | //DAGB0_ATCVM_RD_CGTT_CLK_CTRL |
458 | #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
459 | #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
460 | #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
461 | #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
462 | #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
463 | #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
464 | #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
465 | #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
466 | #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
467 | #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
468 | //DAGB0_RD_ADDR_DAGB_MAX_BURST0 |
469 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 |
470 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 |
471 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 |
472 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc |
473 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 |
474 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 |
475 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 |
476 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c |
477 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL |
478 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L |
479 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L |
480 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L |
481 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L |
482 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L |
483 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L |
484 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L |
485 | //DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 |
486 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 |
487 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 |
488 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 |
489 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc |
490 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 |
491 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 |
492 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 |
493 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c |
494 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL |
495 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L |
496 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L |
497 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L |
498 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L |
499 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L |
500 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L |
501 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L |
502 | //DAGB0_RD_ADDR_DAGB_MAX_BURST1 |
503 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 |
504 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 |
505 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 |
506 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc |
507 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 |
508 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 |
509 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 |
510 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c |
511 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL |
512 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L |
513 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L |
514 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L |
515 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L |
516 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L |
517 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L |
518 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L |
519 | //DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 |
520 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 |
521 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 |
522 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 |
523 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc |
524 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 |
525 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 |
526 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 |
527 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c |
528 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL |
529 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L |
530 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L |
531 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L |
532 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L |
533 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L |
534 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L |
535 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L |
536 | //DAGB0_RD_VC0_CNTL |
537 | #define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 |
538 | #define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 |
539 | #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
540 | #define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc |
541 | #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
542 | #define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 |
543 | #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
544 | #define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 |
545 | #define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL |
546 | #define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L |
547 | #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
548 | #define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L |
549 | #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
550 | #define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L |
551 | #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
552 | #define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L |
553 | //DAGB0_RD_VC1_CNTL |
554 | #define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 |
555 | #define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 |
556 | #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
557 | #define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc |
558 | #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
559 | #define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 |
560 | #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
561 | #define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 |
562 | #define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL |
563 | #define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L |
564 | #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
565 | #define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L |
566 | #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
567 | #define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L |
568 | #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
569 | #define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L |
570 | //DAGB0_RD_VC2_CNTL |
571 | #define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 |
572 | #define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 |
573 | #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
574 | #define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc |
575 | #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
576 | #define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 |
577 | #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
578 | #define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 |
579 | #define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL |
580 | #define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L |
581 | #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
582 | #define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L |
583 | #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
584 | #define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L |
585 | #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
586 | #define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L |
587 | //DAGB0_RD_VC3_CNTL |
588 | #define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 |
589 | #define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 |
590 | #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
591 | #define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc |
592 | #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
593 | #define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 |
594 | #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
595 | #define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 |
596 | #define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL |
597 | #define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L |
598 | #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
599 | #define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L |
600 | #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
601 | #define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L |
602 | #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
603 | #define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L |
604 | //DAGB0_RD_VC4_CNTL |
605 | #define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 |
606 | #define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 |
607 | #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
608 | #define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc |
609 | #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
610 | #define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 |
611 | #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
612 | #define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 |
613 | #define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL |
614 | #define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L |
615 | #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
616 | #define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L |
617 | #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
618 | #define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L |
619 | #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
620 | #define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L |
621 | //DAGB0_RD_VC5_CNTL |
622 | #define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 |
623 | #define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 |
624 | #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
625 | #define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc |
626 | #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
627 | #define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 |
628 | #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
629 | #define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 |
630 | #define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL |
631 | #define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L |
632 | #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
633 | #define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L |
634 | #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
635 | #define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L |
636 | #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
637 | #define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L |
638 | //DAGB0_RD_VC6_CNTL |
639 | #define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 |
640 | #define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 |
641 | #define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
642 | #define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT 0xc |
643 | #define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
644 | #define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 |
645 | #define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
646 | #define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 |
647 | #define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL |
648 | #define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L |
649 | #define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
650 | #define DAGB0_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L |
651 | #define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
652 | #define DAGB0_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L |
653 | #define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
654 | #define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L |
655 | //DAGB0_RD_VC7_CNTL |
656 | #define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 |
657 | #define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 |
658 | #define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
659 | #define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT 0xc |
660 | #define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
661 | #define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 |
662 | #define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
663 | #define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 |
664 | #define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL |
665 | #define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L |
666 | #define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
667 | #define DAGB0_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L |
668 | #define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
669 | #define DAGB0_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L |
670 | #define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
671 | #define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L |
672 | //DAGB0_RD_CNTL_MISC |
673 | #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 |
674 | #define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 |
675 | #define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd |
676 | #define DAGB0_RD_CNTL_MISC__STOR_CC_NEW_MODE__SHIFT 0x13 |
677 | #define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 |
678 | #define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 |
679 | #define DAGB0_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a |
680 | #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL |
681 | #define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L |
682 | #define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L |
683 | #define DAGB0_RD_CNTL_MISC__STOR_CC_NEW_MODE_MASK 0x00080000L |
684 | #define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L |
685 | #define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L |
686 | #define DAGB0_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L |
687 | //DAGB0_RD_TLB_CREDIT |
688 | #define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0 |
689 | #define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5 |
690 | #define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa |
691 | #define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf |
692 | #define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14 |
693 | #define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19 |
694 | #define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL |
695 | #define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L |
696 | #define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L |
697 | #define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L |
698 | #define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L |
699 | #define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L |
700 | //DAGB0_RD_RDRET_CREDIT_CNTL |
701 | #define DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0 |
702 | #define DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x6 |
703 | #define DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xc |
704 | #define DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0x12 |
705 | #define DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x18 |
706 | #define DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e |
707 | #define DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f |
708 | #define DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000003FL |
709 | #define DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x00000FC0L |
710 | #define DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x0003F000L |
711 | #define DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x00FC0000L |
712 | #define DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x3F000000L |
713 | #define DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L |
714 | #define DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L |
715 | //DAGB0_RD_RDRET_CREDIT_CNTL2 |
716 | #define DAGB0_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT 0x0 |
717 | #define DAGB0_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT 0x6 |
718 | #define DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0xc |
719 | #define DAGB0_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK 0x0000003FL |
720 | #define DAGB0_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK 0x00000FC0L |
721 | #define DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0007F000L |
722 | //DAGB0_RDCLI_ASK_PENDING |
723 | #define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 |
724 | #define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL |
725 | //DAGB0_RDCLI_GO_PENDING |
726 | #define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 |
727 | #define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL |
728 | //DAGB0_RDCLI_GBLSEND_PENDING |
729 | #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 |
730 | #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL |
731 | //DAGB0_RDCLI_TLB_PENDING |
732 | #define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 |
733 | #define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL |
734 | //DAGB0_RDCLI_OARB_PENDING |
735 | #define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 |
736 | #define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL |
737 | //DAGB0_RDCLI_OSD_PENDING |
738 | #define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 |
739 | #define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL |
740 | //DAGB0_RDCLI_NOALLOC_OVERRIDE |
741 | #define DAGB0_RDCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT 0x0 |
742 | #define DAGB0_RDCLI_NOALLOC_OVERRIDE__ENABLE_MASK 0x0000FFFFL |
743 | //DAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE |
744 | #define DAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT 0x0 |
745 | #define DAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK 0x0000FFFFL |
746 | //DAGB0_WRCLI0 |
747 | #define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0 |
748 | #define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 |
749 | #define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4 |
750 | #define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8 |
751 | #define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc |
752 | #define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd |
753 | #define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 |
754 | #define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16 |
755 | #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 |
756 | #define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a |
757 | #define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L |
758 | #define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L |
759 | #define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L |
760 | #define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L |
761 | #define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L |
762 | #define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L |
763 | #define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L |
764 | #define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L |
765 | #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L |
766 | #define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L |
767 | //DAGB0_WRCLI1 |
768 | #define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0 |
769 | #define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 |
770 | #define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4 |
771 | #define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8 |
772 | #define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc |
773 | #define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd |
774 | #define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 |
775 | #define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16 |
776 | #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 |
777 | #define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a |
778 | #define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L |
779 | #define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L |
780 | #define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L |
781 | #define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L |
782 | #define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L |
783 | #define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L |
784 | #define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L |
785 | #define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L |
786 | #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L |
787 | #define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L |
788 | //DAGB0_WRCLI2 |
789 | #define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0 |
790 | #define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 |
791 | #define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4 |
792 | #define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8 |
793 | #define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc |
794 | #define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd |
795 | #define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 |
796 | #define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16 |
797 | #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 |
798 | #define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a |
799 | #define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L |
800 | #define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L |
801 | #define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L |
802 | #define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L |
803 | #define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L |
804 | #define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L |
805 | #define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L |
806 | #define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L |
807 | #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L |
808 | #define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L |
809 | //DAGB0_WRCLI3 |
810 | #define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0 |
811 | #define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 |
812 | #define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4 |
813 | #define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8 |
814 | #define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc |
815 | #define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd |
816 | #define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 |
817 | #define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16 |
818 | #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 |
819 | #define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a |
820 | #define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L |
821 | #define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L |
822 | #define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L |
823 | #define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L |
824 | #define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L |
825 | #define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L |
826 | #define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L |
827 | #define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L |
828 | #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L |
829 | #define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L |
830 | //DAGB0_WRCLI4 |
831 | #define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0 |
832 | #define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 |
833 | #define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4 |
834 | #define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8 |
835 | #define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc |
836 | #define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd |
837 | #define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 |
838 | #define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16 |
839 | #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 |
840 | #define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a |
841 | #define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L |
842 | #define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L |
843 | #define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L |
844 | #define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L |
845 | #define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L |
846 | #define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L |
847 | #define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L |
848 | #define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L |
849 | #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L |
850 | #define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L |
851 | //DAGB0_WRCLI5 |
852 | #define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0 |
853 | #define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 |
854 | #define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4 |
855 | #define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8 |
856 | #define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc |
857 | #define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd |
858 | #define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 |
859 | #define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16 |
860 | #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 |
861 | #define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a |
862 | #define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L |
863 | #define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L |
864 | #define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L |
865 | #define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L |
866 | #define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L |
867 | #define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L |
868 | #define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L |
869 | #define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L |
870 | #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L |
871 | #define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L |
872 | //DAGB0_WRCLI6 |
873 | #define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0 |
874 | #define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 |
875 | #define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4 |
876 | #define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8 |
877 | #define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc |
878 | #define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd |
879 | #define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 |
880 | #define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16 |
881 | #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 |
882 | #define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a |
883 | #define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L |
884 | #define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L |
885 | #define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L |
886 | #define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L |
887 | #define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L |
888 | #define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L |
889 | #define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L |
890 | #define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L |
891 | #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L |
892 | #define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L |
893 | //DAGB0_WRCLI7 |
894 | #define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0 |
895 | #define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 |
896 | #define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4 |
897 | #define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8 |
898 | #define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc |
899 | #define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd |
900 | #define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 |
901 | #define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16 |
902 | #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 |
903 | #define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a |
904 | #define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L |
905 | #define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L |
906 | #define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L |
907 | #define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L |
908 | #define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L |
909 | #define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L |
910 | #define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L |
911 | #define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L |
912 | #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L |
913 | #define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L |
914 | //DAGB0_WRCLI8 |
915 | #define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0 |
916 | #define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 |
917 | #define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4 |
918 | #define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8 |
919 | #define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc |
920 | #define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd |
921 | #define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 |
922 | #define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16 |
923 | #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 |
924 | #define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a |
925 | #define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L |
926 | #define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L |
927 | #define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L |
928 | #define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L |
929 | #define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L |
930 | #define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L |
931 | #define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L |
932 | #define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L |
933 | #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L |
934 | #define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L |
935 | //DAGB0_WRCLI9 |
936 | #define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0 |
937 | #define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 |
938 | #define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4 |
939 | #define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8 |
940 | #define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc |
941 | #define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd |
942 | #define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 |
943 | #define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16 |
944 | #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 |
945 | #define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a |
946 | #define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L |
947 | #define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L |
948 | #define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L |
949 | #define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L |
950 | #define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L |
951 | #define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L |
952 | #define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L |
953 | #define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L |
954 | #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L |
955 | #define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L |
956 | //DAGB0_WRCLI10 |
957 | #define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0 |
958 | #define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 |
959 | #define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4 |
960 | #define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8 |
961 | #define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc |
962 | #define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd |
963 | #define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 |
964 | #define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16 |
965 | #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 |
966 | #define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a |
967 | #define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L |
968 | #define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L |
969 | #define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L |
970 | #define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L |
971 | #define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L |
972 | #define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L |
973 | #define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L |
974 | #define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L |
975 | #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L |
976 | #define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L |
977 | //DAGB0_WRCLI11 |
978 | #define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0 |
979 | #define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 |
980 | #define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4 |
981 | #define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8 |
982 | #define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc |
983 | #define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd |
984 | #define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 |
985 | #define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16 |
986 | #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 |
987 | #define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a |
988 | #define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L |
989 | #define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L |
990 | #define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L |
991 | #define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L |
992 | #define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L |
993 | #define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L |
994 | #define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L |
995 | #define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L |
996 | #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L |
997 | #define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L |
998 | //DAGB0_WRCLI12 |
999 | #define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0 |
1000 | #define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 |
1001 | #define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4 |
1002 | #define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8 |
1003 | #define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc |
1004 | #define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd |
1005 | #define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 |
1006 | #define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16 |
1007 | #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 |
1008 | #define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a |
1009 | #define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L |
1010 | #define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L |
1011 | #define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L |
1012 | #define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L |
1013 | #define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L |
1014 | #define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L |
1015 | #define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L |
1016 | #define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L |
1017 | #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L |
1018 | #define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L |
1019 | //DAGB0_WRCLI13 |
1020 | #define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0 |
1021 | #define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 |
1022 | #define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4 |
1023 | #define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8 |
1024 | #define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc |
1025 | #define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd |
1026 | #define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 |
1027 | #define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16 |
1028 | #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 |
1029 | #define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a |
1030 | #define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L |
1031 | #define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L |
1032 | #define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L |
1033 | #define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L |
1034 | #define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L |
1035 | #define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L |
1036 | #define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L |
1037 | #define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L |
1038 | #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L |
1039 | #define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L |
1040 | //DAGB0_WRCLI14 |
1041 | #define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0 |
1042 | #define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 |
1043 | #define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4 |
1044 | #define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8 |
1045 | #define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc |
1046 | #define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd |
1047 | #define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 |
1048 | #define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16 |
1049 | #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 |
1050 | #define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a |
1051 | #define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L |
1052 | #define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L |
1053 | #define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L |
1054 | #define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L |
1055 | #define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L |
1056 | #define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L |
1057 | #define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L |
1058 | #define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L |
1059 | #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L |
1060 | #define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L |
1061 | //DAGB0_WRCLI15 |
1062 | #define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0 |
1063 | #define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 |
1064 | #define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4 |
1065 | #define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8 |
1066 | #define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc |
1067 | #define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd |
1068 | #define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 |
1069 | #define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16 |
1070 | #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 |
1071 | #define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a |
1072 | #define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L |
1073 | #define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L |
1074 | #define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L |
1075 | #define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L |
1076 | #define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L |
1077 | #define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L |
1078 | #define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L |
1079 | #define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L |
1080 | #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L |
1081 | #define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L |
1082 | //DAGB0_WR_CNTL |
1083 | #define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT 0x0 |
1084 | #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 |
1085 | #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa |
1086 | #define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 |
1087 | #define DAGB0_WR_CNTL__IO_LEVEL__SHIFT 0x11 |
1088 | #define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 |
1089 | #define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 |
1090 | #define DAGB0_WR_CNTL__FIX_JUMP__SHIFT 0x1a |
1091 | #define DAGB0_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL |
1092 | #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L |
1093 | #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L |
1094 | #define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L |
1095 | #define DAGB0_WR_CNTL__IO_LEVEL_MASK 0x000E0000L |
1096 | #define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L |
1097 | #define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L |
1098 | #define DAGB0_WR_CNTL__FIX_JUMP_MASK 0x04000000L |
1099 | //DAGB0_WR_GMI_CNTL |
1100 | #define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 |
1101 | #define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT 0x6 |
1102 | #define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 |
1103 | #define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd |
1104 | #define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL |
1105 | #define DAGB0_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L |
1106 | #define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L |
1107 | #define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L |
1108 | //DAGB0_WR_ADDR_DAGB |
1109 | #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 |
1110 | #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 |
1111 | #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 |
1112 | #define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 |
1113 | #define DAGB0_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd |
1114 | #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L |
1115 | #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L |
1116 | #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L |
1117 | #define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L |
1118 | #define DAGB0_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L |
1119 | //DAGB0_WR_OUTPUT_DAGB_MAX_BURST |
1120 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 |
1121 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 |
1122 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 |
1123 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc |
1124 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 |
1125 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 |
1126 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 |
1127 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c |
1128 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL |
1129 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L |
1130 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L |
1131 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L |
1132 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L |
1133 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L |
1134 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L |
1135 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L |
1136 | //DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER |
1137 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 |
1138 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 |
1139 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 |
1140 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc |
1141 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 |
1142 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 |
1143 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 |
1144 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c |
1145 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL |
1146 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L |
1147 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L |
1148 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L |
1149 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L |
1150 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L |
1151 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L |
1152 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L |
1153 | //DAGB0_WR_CGTT_CLK_CTRL |
1154 | #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
1155 | #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
1156 | #define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
1157 | #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
1158 | #define DAGB0_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
1159 | #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
1160 | #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
1161 | #define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
1162 | #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
1163 | #define DAGB0_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
1164 | //DAGB0_L1TLB_WR_CGTT_CLK_CTRL |
1165 | #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
1166 | #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
1167 | #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
1168 | #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
1169 | #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
1170 | #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
1171 | #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
1172 | #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
1173 | #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
1174 | #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
1175 | //DAGB0_ATCVM_WR_CGTT_CLK_CTRL |
1176 | #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
1177 | #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
1178 | #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
1179 | #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
1180 | #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
1181 | #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
1182 | #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
1183 | #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
1184 | #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
1185 | #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
1186 | //DAGB0_WR_ADDR_DAGB_MAX_BURST0 |
1187 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 |
1188 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 |
1189 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 |
1190 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc |
1191 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 |
1192 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 |
1193 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 |
1194 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c |
1195 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL |
1196 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L |
1197 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L |
1198 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L |
1199 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L |
1200 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L |
1201 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L |
1202 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L |
1203 | //DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 |
1204 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 |
1205 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 |
1206 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 |
1207 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc |
1208 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 |
1209 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 |
1210 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 |
1211 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c |
1212 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL |
1213 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L |
1214 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L |
1215 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L |
1216 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L |
1217 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L |
1218 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L |
1219 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L |
1220 | //DAGB0_WR_ADDR_DAGB_MAX_BURST1 |
1221 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 |
1222 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 |
1223 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 |
1224 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc |
1225 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 |
1226 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 |
1227 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 |
1228 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c |
1229 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL |
1230 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L |
1231 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L |
1232 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L |
1233 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L |
1234 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L |
1235 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L |
1236 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L |
1237 | //DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 |
1238 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 |
1239 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 |
1240 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 |
1241 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc |
1242 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 |
1243 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 |
1244 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 |
1245 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c |
1246 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL |
1247 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L |
1248 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L |
1249 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L |
1250 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L |
1251 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L |
1252 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L |
1253 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L |
1254 | //DAGB0_WR_DATA_DAGB |
1255 | #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 |
1256 | #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 |
1257 | #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 |
1258 | #define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 |
1259 | #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L |
1260 | #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L |
1261 | #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L |
1262 | #define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L |
1263 | //DAGB0_WR_DATA_DAGB_MAX_BURST0 |
1264 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 |
1265 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 |
1266 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 |
1267 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc |
1268 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 |
1269 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 |
1270 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 |
1271 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c |
1272 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL |
1273 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L |
1274 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L |
1275 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L |
1276 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L |
1277 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L |
1278 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L |
1279 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L |
1280 | //DAGB0_WR_DATA_DAGB_LAZY_TIMER0 |
1281 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 |
1282 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 |
1283 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 |
1284 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc |
1285 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 |
1286 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 |
1287 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 |
1288 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c |
1289 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL |
1290 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L |
1291 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L |
1292 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L |
1293 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L |
1294 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L |
1295 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L |
1296 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L |
1297 | //DAGB0_WR_DATA_DAGB_MAX_BURST1 |
1298 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 |
1299 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 |
1300 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 |
1301 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc |
1302 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 |
1303 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 |
1304 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 |
1305 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c |
1306 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL |
1307 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L |
1308 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L |
1309 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L |
1310 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L |
1311 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L |
1312 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L |
1313 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L |
1314 | //DAGB0_WR_DATA_DAGB_LAZY_TIMER1 |
1315 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 |
1316 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 |
1317 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 |
1318 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc |
1319 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 |
1320 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 |
1321 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 |
1322 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c |
1323 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL |
1324 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L |
1325 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L |
1326 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L |
1327 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L |
1328 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L |
1329 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L |
1330 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L |
1331 | //DAGB0_WR_VC0_CNTL |
1332 | #define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 |
1333 | #define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 |
1334 | #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
1335 | #define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc |
1336 | #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
1337 | #define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 |
1338 | #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
1339 | #define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 |
1340 | #define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL |
1341 | #define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L |
1342 | #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
1343 | #define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L |
1344 | #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
1345 | #define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L |
1346 | #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
1347 | #define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L |
1348 | //DAGB0_WR_VC1_CNTL |
1349 | #define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 |
1350 | #define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 |
1351 | #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
1352 | #define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc |
1353 | #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
1354 | #define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 |
1355 | #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
1356 | #define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 |
1357 | #define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL |
1358 | #define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L |
1359 | #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
1360 | #define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L |
1361 | #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
1362 | #define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L |
1363 | #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
1364 | #define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L |
1365 | //DAGB0_WR_VC2_CNTL |
1366 | #define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 |
1367 | #define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 |
1368 | #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
1369 | #define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc |
1370 | #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
1371 | #define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 |
1372 | #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
1373 | #define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 |
1374 | #define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL |
1375 | #define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L |
1376 | #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
1377 | #define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L |
1378 | #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
1379 | #define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L |
1380 | #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
1381 | #define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L |
1382 | //DAGB0_WR_VC3_CNTL |
1383 | #define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 |
1384 | #define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 |
1385 | #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
1386 | #define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc |
1387 | #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
1388 | #define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 |
1389 | #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
1390 | #define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 |
1391 | #define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL |
1392 | #define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L |
1393 | #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
1394 | #define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L |
1395 | #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
1396 | #define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L |
1397 | #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
1398 | #define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L |
1399 | //DAGB0_WR_VC4_CNTL |
1400 | #define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 |
1401 | #define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 |
1402 | #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
1403 | #define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc |
1404 | #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
1405 | #define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 |
1406 | #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
1407 | #define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 |
1408 | #define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL |
1409 | #define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L |
1410 | #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
1411 | #define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L |
1412 | #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
1413 | #define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L |
1414 | #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
1415 | #define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L |
1416 | //DAGB0_WR_VC5_CNTL |
1417 | #define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 |
1418 | #define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 |
1419 | #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
1420 | #define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc |
1421 | #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
1422 | #define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 |
1423 | #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
1424 | #define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 |
1425 | #define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL |
1426 | #define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L |
1427 | #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
1428 | #define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L |
1429 | #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
1430 | #define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L |
1431 | #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
1432 | #define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L |
1433 | //DAGB0_WR_VC6_CNTL |
1434 | #define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 |
1435 | #define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 |
1436 | #define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
1437 | #define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT 0xc |
1438 | #define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
1439 | #define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 |
1440 | #define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
1441 | #define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 |
1442 | #define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL |
1443 | #define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L |
1444 | #define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
1445 | #define DAGB0_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L |
1446 | #define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
1447 | #define DAGB0_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L |
1448 | #define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
1449 | #define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L |
1450 | //DAGB0_WR_VC7_CNTL |
1451 | #define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 |
1452 | #define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 |
1453 | #define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
1454 | #define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT 0xc |
1455 | #define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
1456 | #define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 |
1457 | #define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
1458 | #define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 |
1459 | #define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL |
1460 | #define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L |
1461 | #define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
1462 | #define DAGB0_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L |
1463 | #define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
1464 | #define DAGB0_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L |
1465 | #define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
1466 | #define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L |
1467 | //DAGB0_WR_CNTL_MISC |
1468 | #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 |
1469 | #define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 |
1470 | #define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd |
1471 | #define DAGB0_WR_CNTL_MISC__STOR_CC_NEW_MODE__SHIFT 0x13 |
1472 | #define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 |
1473 | #define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 |
1474 | #define DAGB0_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a |
1475 | #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL |
1476 | #define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L |
1477 | #define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L |
1478 | #define DAGB0_WR_CNTL_MISC__STOR_CC_NEW_MODE_MASK 0x00080000L |
1479 | #define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L |
1480 | #define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L |
1481 | #define DAGB0_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L |
1482 | //DAGB0_WR_TLB_CREDIT |
1483 | #define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0 |
1484 | #define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5 |
1485 | #define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa |
1486 | #define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf |
1487 | #define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14 |
1488 | #define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19 |
1489 | #define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL |
1490 | #define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L |
1491 | #define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L |
1492 | #define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L |
1493 | #define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L |
1494 | #define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L |
1495 | //DAGB0_WR_DATA_CREDIT |
1496 | #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 |
1497 | #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 |
1498 | #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 |
1499 | #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 |
1500 | #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL |
1501 | #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L |
1502 | #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L |
1503 | #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L |
1504 | //DAGB0_WR_MISC_CREDIT |
1505 | #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 |
1506 | #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 |
1507 | #define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 |
1508 | #define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 |
1509 | #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL |
1510 | #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L |
1511 | #define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L |
1512 | #define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L |
1513 | //DAGB0_WR_OSD_CREDIT_CNTL1 |
1514 | #define DAGB0_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 |
1515 | #define DAGB0_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x4 |
1516 | #define DAGB0_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0x8 |
1517 | #define DAGB0_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xc |
1518 | #define DAGB0_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT 0x10 |
1519 | #define DAGB0_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT 0x14 |
1520 | #define DAGB0_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x18 |
1521 | #define DAGB0_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000000FL |
1522 | #define DAGB0_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000000F0L |
1523 | #define DAGB0_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00000F00L |
1524 | #define DAGB0_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK 0x0000F000L |
1525 | #define DAGB0_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK 0x000F0000L |
1526 | #define DAGB0_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK 0x00F00000L |
1527 | #define DAGB0_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK 0x3F000000L |
1528 | //DAGB0_WR_OSD_CREDIT_CNTL2 |
1529 | #define DAGB0_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT 0x0 |
1530 | #define DAGB0_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT 0x4 |
1531 | #define DAGB0_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK 0x0000000FL |
1532 | #define DAGB0_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK 0x00000010L |
1533 | //DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 |
1534 | #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 |
1535 | #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 |
1536 | #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa |
1537 | #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf |
1538 | #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 |
1539 | #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19 |
1540 | #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a |
1541 | #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b |
1542 | #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT 0x1c |
1543 | #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT 0x1d |
1544 | #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL |
1545 | #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L |
1546 | #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L |
1547 | #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L |
1548 | #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L |
1549 | #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L |
1550 | #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L |
1551 | #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L |
1552 | #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK 0x10000000L |
1553 | #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK 0x20000000L |
1554 | //DAGB0_WRCLI_GPU_SNOOP_OVERRIDE |
1555 | #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 |
1556 | #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0x0000FFFFL |
1557 | //DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE |
1558 | #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 |
1559 | #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0x0000FFFFL |
1560 | //DAGB0_WRCLI_ASK_PENDING |
1561 | #define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 |
1562 | #define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL |
1563 | //DAGB0_WRCLI_GO_PENDING |
1564 | #define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 |
1565 | #define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL |
1566 | //DAGB0_WRCLI_GBLSEND_PENDING |
1567 | #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 |
1568 | #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL |
1569 | //DAGB0_WRCLI_TLB_PENDING |
1570 | #define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 |
1571 | #define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL |
1572 | //DAGB0_WRCLI_OARB_PENDING |
1573 | #define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 |
1574 | #define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL |
1575 | //DAGB0_WRCLI_OSD_PENDING |
1576 | #define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 |
1577 | #define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL |
1578 | //DAGB0_WRCLI_DBUS_ASK_PENDING |
1579 | #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 |
1580 | #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL |
1581 | //DAGB0_WRCLI_DBUS_GO_PENDING |
1582 | #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 |
1583 | #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL |
1584 | //DAGB0_WRCLI_NOALLOC_OVERRIDE |
1585 | #define DAGB0_WRCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT 0x0 |
1586 | #define DAGB0_WRCLI_NOALLOC_OVERRIDE__ENABLE_MASK 0x0000FFFFL |
1587 | //DAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE |
1588 | #define DAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT 0x0 |
1589 | #define DAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK 0x0000FFFFL |
1590 | //DAGB0_DAGB_DLY |
1591 | #define DAGB0_DAGB_DLY__DLY__SHIFT 0x0 |
1592 | #define DAGB0_DAGB_DLY__CLI__SHIFT 0x8 |
1593 | #define DAGB0_DAGB_DLY__POS__SHIFT 0x10 |
1594 | #define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL |
1595 | #define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L |
1596 | #define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L |
1597 | //DAGB0_CNTL_MISC |
1598 | #define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 |
1599 | #define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 |
1600 | #define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 |
1601 | #define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 |
1602 | #define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc |
1603 | #define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf |
1604 | #define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 |
1605 | #define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 |
1606 | #define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 |
1607 | #define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e |
1608 | #define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L |
1609 | #define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L |
1610 | #define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L |
1611 | #define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L |
1612 | #define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L |
1613 | #define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L |
1614 | #define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L |
1615 | #define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L |
1616 | #define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L |
1617 | #define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L |
1618 | //DAGB0_CNTL_MISC2 |
1619 | #define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 |
1620 | #define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 |
1621 | #define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 |
1622 | #define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 |
1623 | #define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 |
1624 | #define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 |
1625 | #define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 |
1626 | #define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 |
1627 | #define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 |
1628 | #define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 |
1629 | #define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa |
1630 | #define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb |
1631 | #define DAGB0_CNTL_MISC2__HDP_CID__SHIFT 0xc |
1632 | #define DAGB0_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x10 |
1633 | #define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L |
1634 | #define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L |
1635 | #define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L |
1636 | #define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L |
1637 | #define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L |
1638 | #define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L |
1639 | #define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L |
1640 | #define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L |
1641 | #define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L |
1642 | #define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L |
1643 | #define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L |
1644 | #define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L |
1645 | #define DAGB0_CNTL_MISC2__HDP_CID_MASK 0x0000F000L |
1646 | #define DAGB0_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x003F0000L |
1647 | //DAGB0_FATAL_ERROR_CNTL |
1648 | #define DAGB0_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0 |
1649 | #define DAGB0_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL |
1650 | //DAGB0_FATAL_ERROR_CLEAR |
1651 | #define DAGB0_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0 |
1652 | #define DAGB0_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L |
1653 | //DAGB0_FATAL_ERROR_STATUS0 |
1654 | #define DAGB0_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0 |
1655 | #define DAGB0_FATAL_ERROR_STATUS0__CID__SHIFT 0x1 |
1656 | #define DAGB0_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6 |
1657 | #define DAGB0_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L |
1658 | #define DAGB0_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL |
1659 | #define DAGB0_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L |
1660 | //DAGB0_FATAL_ERROR_STATUS1 |
1661 | #define DAGB0_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0 |
1662 | #define DAGB0_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL |
1663 | //DAGB0_FATAL_ERROR_STATUS2 |
1664 | #define DAGB0_FATAL_ERROR_STATUS2__TAG__SHIFT 0x0 |
1665 | #define DAGB0_FATAL_ERROR_STATUS2__VFID__SHIFT 0x10 |
1666 | #define DAGB0_FATAL_ERROR_STATUS2__VF__SHIFT 0x14 |
1667 | #define DAGB0_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x15 |
1668 | #define DAGB0_FATAL_ERROR_STATUS2__IO__SHIFT 0x16 |
1669 | #define DAGB0_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x17 |
1670 | #define DAGB0_FATAL_ERROR_STATUS2__DBGMSK__SHIFT 0x18 |
1671 | #define DAGB0_FATAL_ERROR_STATUS2__FED__SHIFT 0x19 |
1672 | #define DAGB0_FATAL_ERROR_STATUS2__TAG_MASK 0x0000FFFFL |
1673 | #define DAGB0_FATAL_ERROR_STATUS2__VFID_MASK 0x000F0000L |
1674 | #define DAGB0_FATAL_ERROR_STATUS2__VF_MASK 0x00100000L |
1675 | #define DAGB0_FATAL_ERROR_STATUS2__SPACE_MASK 0x00200000L |
1676 | #define DAGB0_FATAL_ERROR_STATUS2__IO_MASK 0x00400000L |
1677 | #define DAGB0_FATAL_ERROR_STATUS2__SIZE_MASK 0x00800000L |
1678 | #define DAGB0_FATAL_ERROR_STATUS2__DBGMSK_MASK 0x01000000L |
1679 | #define DAGB0_FATAL_ERROR_STATUS2__FED_MASK 0x02000000L |
1680 | //DAGB0_FATAL_ERROR_STATUS3 |
1681 | #define DAGB0_FATAL_ERROR_STATUS3__NOALLOC__SHIFT 0x0 |
1682 | #define DAGB0_FATAL_ERROR_STATUS3__UNITID__SHIFT 0x1 |
1683 | #define DAGB0_FATAL_ERROR_STATUS3__OP__SHIFT 0x7 |
1684 | #define DAGB0_FATAL_ERROR_STATUS3__SECLEVEL__SHIFT 0xe |
1685 | #define DAGB0_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x11 |
1686 | #define DAGB0_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x12 |
1687 | #define DAGB0_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x13 |
1688 | #define DAGB0_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x14 |
1689 | #define DAGB0_FATAL_ERROR_STATUS3__NACK__SHIFT 0x15 |
1690 | #define DAGB0_FATAL_ERROR_STATUS3__RO__SHIFT 0x17 |
1691 | #define DAGB0_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x18 |
1692 | #define DAGB0_FATAL_ERROR_STATUS3__EOP__SHIFT 0x19 |
1693 | #define DAGB0_FATAL_ERROR_STATUS3__NOALLOC_MASK 0x00000001L |
1694 | #define DAGB0_FATAL_ERROR_STATUS3__UNITID_MASK 0x0000007EL |
1695 | #define DAGB0_FATAL_ERROR_STATUS3__OP_MASK 0x00003F80L |
1696 | #define DAGB0_FATAL_ERROR_STATUS3__SECLEVEL_MASK 0x0001C000L |
1697 | #define DAGB0_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00020000L |
1698 | #define DAGB0_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00040000L |
1699 | #define DAGB0_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00080000L |
1700 | #define DAGB0_FATAL_ERROR_STATUS3__INVAL_MASK 0x00100000L |
1701 | #define DAGB0_FATAL_ERROR_STATUS3__NACK_MASK 0x00600000L |
1702 | #define DAGB0_FATAL_ERROR_STATUS3__RO_MASK 0x00800000L |
1703 | #define DAGB0_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x01000000L |
1704 | #define DAGB0_FATAL_ERROR_STATUS3__EOP_MASK 0x02000000L |
1705 | //DAGB0_FIFO_EMPTY |
1706 | #define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0 |
1707 | #define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL |
1708 | //DAGB0_FIFO_FULL |
1709 | #define DAGB0_FIFO_FULL__FULL__SHIFT 0x0 |
1710 | #define DAGB0_FIFO_FULL__FULL_MASK 0x007FFFFFL |
1711 | //DAGB0_WR_CREDITS_FULL |
1712 | #define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0 |
1713 | #define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL |
1714 | //DAGB0_RD_CREDITS_FULL |
1715 | #define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0 |
1716 | #define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL |
1717 | //DAGB0_PERFCOUNTER_LO |
1718 | #define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
1719 | #define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
1720 | //DAGB0_PERFCOUNTER_HI |
1721 | #define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
1722 | #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
1723 | #define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
1724 | #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
1725 | //DAGB0_PERFCOUNTER0_CFG |
1726 | #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
1727 | #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
1728 | #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
1729 | #define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
1730 | #define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
1731 | #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
1732 | #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
1733 | #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
1734 | #define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
1735 | #define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
1736 | //DAGB0_PERFCOUNTER1_CFG |
1737 | #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
1738 | #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
1739 | #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
1740 | #define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
1741 | #define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
1742 | #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
1743 | #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
1744 | #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
1745 | #define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
1746 | #define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
1747 | //DAGB0_PERFCOUNTER2_CFG |
1748 | #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 |
1749 | #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 |
1750 | #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 |
1751 | #define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c |
1752 | #define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d |
1753 | #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL |
1754 | #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L |
1755 | #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L |
1756 | #define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L |
1757 | #define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L |
1758 | //DAGB0_PERFCOUNTER_RSLT_CNTL |
1759 | #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
1760 | #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
1761 | #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
1762 | #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
1763 | #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
1764 | #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
1765 | #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
1766 | #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
1767 | #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
1768 | #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
1769 | #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
1770 | #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
1771 | //DAGB0_L1TLB_REG_RW |
1772 | #define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 |
1773 | #define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 |
1774 | #define DAGB0_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT 0x2 |
1775 | #define DAGB0_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT 0x4 |
1776 | #define DAGB0_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT 0x5 |
1777 | #define DAGB0_L1TLB_REG_RW__RESERVE__SHIFT 0x6 |
1778 | #define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L |
1779 | #define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L |
1780 | #define DAGB0_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK 0x00000004L |
1781 | #define DAGB0_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK 0x00000010L |
1782 | #define DAGB0_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK 0x00000020L |
1783 | #define DAGB0_L1TLB_REG_RW__RESERVE_MASK 0xFFFFFFC0L |
1784 | |
1785 | |
1786 | // addressBlock: aid_mmhub_dagb_dagbdec1 |
1787 | //DAGB1_RDCLI0 |
1788 | #define DAGB1_RDCLI0__VIRT_CHAN__SHIFT 0x0 |
1789 | #define DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 |
1790 | #define DAGB1_RDCLI0__URG_HIGH__SHIFT 0x4 |
1791 | #define DAGB1_RDCLI0__URG_LOW__SHIFT 0x8 |
1792 | #define DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc |
1793 | #define DAGB1_RDCLI0__MAX_BW__SHIFT 0xd |
1794 | #define DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 |
1795 | #define DAGB1_RDCLI0__MIN_BW__SHIFT 0x16 |
1796 | #define DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 |
1797 | #define DAGB1_RDCLI0__MAX_OSD__SHIFT 0x1a |
1798 | #define DAGB1_RDCLI0__VIRT_CHAN_MASK 0x00000007L |
1799 | #define DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L |
1800 | #define DAGB1_RDCLI0__URG_HIGH_MASK 0x000000F0L |
1801 | #define DAGB1_RDCLI0__URG_LOW_MASK 0x00000F00L |
1802 | #define DAGB1_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L |
1803 | #define DAGB1_RDCLI0__MAX_BW_MASK 0x001FE000L |
1804 | #define DAGB1_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L |
1805 | #define DAGB1_RDCLI0__MIN_BW_MASK 0x01C00000L |
1806 | #define DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L |
1807 | #define DAGB1_RDCLI0__MAX_OSD_MASK 0xFC000000L |
1808 | //DAGB1_RDCLI1 |
1809 | #define DAGB1_RDCLI1__VIRT_CHAN__SHIFT 0x0 |
1810 | #define DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 |
1811 | #define DAGB1_RDCLI1__URG_HIGH__SHIFT 0x4 |
1812 | #define DAGB1_RDCLI1__URG_LOW__SHIFT 0x8 |
1813 | #define DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc |
1814 | #define DAGB1_RDCLI1__MAX_BW__SHIFT 0xd |
1815 | #define DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 |
1816 | #define DAGB1_RDCLI1__MIN_BW__SHIFT 0x16 |
1817 | #define DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 |
1818 | #define DAGB1_RDCLI1__MAX_OSD__SHIFT 0x1a |
1819 | #define DAGB1_RDCLI1__VIRT_CHAN_MASK 0x00000007L |
1820 | #define DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L |
1821 | #define DAGB1_RDCLI1__URG_HIGH_MASK 0x000000F0L |
1822 | #define DAGB1_RDCLI1__URG_LOW_MASK 0x00000F00L |
1823 | #define DAGB1_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L |
1824 | #define DAGB1_RDCLI1__MAX_BW_MASK 0x001FE000L |
1825 | #define DAGB1_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L |
1826 | #define DAGB1_RDCLI1__MIN_BW_MASK 0x01C00000L |
1827 | #define DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L |
1828 | #define DAGB1_RDCLI1__MAX_OSD_MASK 0xFC000000L |
1829 | //DAGB1_RDCLI2 |
1830 | #define DAGB1_RDCLI2__VIRT_CHAN__SHIFT 0x0 |
1831 | #define DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 |
1832 | #define DAGB1_RDCLI2__URG_HIGH__SHIFT 0x4 |
1833 | #define DAGB1_RDCLI2__URG_LOW__SHIFT 0x8 |
1834 | #define DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc |
1835 | #define DAGB1_RDCLI2__MAX_BW__SHIFT 0xd |
1836 | #define DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 |
1837 | #define DAGB1_RDCLI2__MIN_BW__SHIFT 0x16 |
1838 | #define DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 |
1839 | #define DAGB1_RDCLI2__MAX_OSD__SHIFT 0x1a |
1840 | #define DAGB1_RDCLI2__VIRT_CHAN_MASK 0x00000007L |
1841 | #define DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L |
1842 | #define DAGB1_RDCLI2__URG_HIGH_MASK 0x000000F0L |
1843 | #define DAGB1_RDCLI2__URG_LOW_MASK 0x00000F00L |
1844 | #define DAGB1_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L |
1845 | #define DAGB1_RDCLI2__MAX_BW_MASK 0x001FE000L |
1846 | #define DAGB1_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L |
1847 | #define DAGB1_RDCLI2__MIN_BW_MASK 0x01C00000L |
1848 | #define DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L |
1849 | #define DAGB1_RDCLI2__MAX_OSD_MASK 0xFC000000L |
1850 | //DAGB1_RDCLI3 |
1851 | #define DAGB1_RDCLI3__VIRT_CHAN__SHIFT 0x0 |
1852 | #define DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 |
1853 | #define DAGB1_RDCLI3__URG_HIGH__SHIFT 0x4 |
1854 | #define DAGB1_RDCLI3__URG_LOW__SHIFT 0x8 |
1855 | #define DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc |
1856 | #define DAGB1_RDCLI3__MAX_BW__SHIFT 0xd |
1857 | #define DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 |
1858 | #define DAGB1_RDCLI3__MIN_BW__SHIFT 0x16 |
1859 | #define DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 |
1860 | #define DAGB1_RDCLI3__MAX_OSD__SHIFT 0x1a |
1861 | #define DAGB1_RDCLI3__VIRT_CHAN_MASK 0x00000007L |
1862 | #define DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L |
1863 | #define DAGB1_RDCLI3__URG_HIGH_MASK 0x000000F0L |
1864 | #define DAGB1_RDCLI3__URG_LOW_MASK 0x00000F00L |
1865 | #define DAGB1_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L |
1866 | #define DAGB1_RDCLI3__MAX_BW_MASK 0x001FE000L |
1867 | #define DAGB1_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L |
1868 | #define DAGB1_RDCLI3__MIN_BW_MASK 0x01C00000L |
1869 | #define DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L |
1870 | #define DAGB1_RDCLI3__MAX_OSD_MASK 0xFC000000L |
1871 | //DAGB1_RDCLI4 |
1872 | #define DAGB1_RDCLI4__VIRT_CHAN__SHIFT 0x0 |
1873 | #define DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 |
1874 | #define DAGB1_RDCLI4__URG_HIGH__SHIFT 0x4 |
1875 | #define DAGB1_RDCLI4__URG_LOW__SHIFT 0x8 |
1876 | #define DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc |
1877 | #define DAGB1_RDCLI4__MAX_BW__SHIFT 0xd |
1878 | #define DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 |
1879 | #define DAGB1_RDCLI4__MIN_BW__SHIFT 0x16 |
1880 | #define DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 |
1881 | #define DAGB1_RDCLI4__MAX_OSD__SHIFT 0x1a |
1882 | #define DAGB1_RDCLI4__VIRT_CHAN_MASK 0x00000007L |
1883 | #define DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L |
1884 | #define DAGB1_RDCLI4__URG_HIGH_MASK 0x000000F0L |
1885 | #define DAGB1_RDCLI4__URG_LOW_MASK 0x00000F00L |
1886 | #define DAGB1_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L |
1887 | #define DAGB1_RDCLI4__MAX_BW_MASK 0x001FE000L |
1888 | #define DAGB1_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L |
1889 | #define DAGB1_RDCLI4__MIN_BW_MASK 0x01C00000L |
1890 | #define DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L |
1891 | #define DAGB1_RDCLI4__MAX_OSD_MASK 0xFC000000L |
1892 | //DAGB1_RDCLI5 |
1893 | #define DAGB1_RDCLI5__VIRT_CHAN__SHIFT 0x0 |
1894 | #define DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 |
1895 | #define DAGB1_RDCLI5__URG_HIGH__SHIFT 0x4 |
1896 | #define DAGB1_RDCLI5__URG_LOW__SHIFT 0x8 |
1897 | #define DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc |
1898 | #define DAGB1_RDCLI5__MAX_BW__SHIFT 0xd |
1899 | #define DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 |
1900 | #define DAGB1_RDCLI5__MIN_BW__SHIFT 0x16 |
1901 | #define DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 |
1902 | #define DAGB1_RDCLI5__MAX_OSD__SHIFT 0x1a |
1903 | #define DAGB1_RDCLI5__VIRT_CHAN_MASK 0x00000007L |
1904 | #define DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L |
1905 | #define DAGB1_RDCLI5__URG_HIGH_MASK 0x000000F0L |
1906 | #define DAGB1_RDCLI5__URG_LOW_MASK 0x00000F00L |
1907 | #define DAGB1_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L |
1908 | #define DAGB1_RDCLI5__MAX_BW_MASK 0x001FE000L |
1909 | #define DAGB1_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L |
1910 | #define DAGB1_RDCLI5__MIN_BW_MASK 0x01C00000L |
1911 | #define DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L |
1912 | #define DAGB1_RDCLI5__MAX_OSD_MASK 0xFC000000L |
1913 | //DAGB1_RDCLI6 |
1914 | #define DAGB1_RDCLI6__VIRT_CHAN__SHIFT 0x0 |
1915 | #define DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 |
1916 | #define DAGB1_RDCLI6__URG_HIGH__SHIFT 0x4 |
1917 | #define DAGB1_RDCLI6__URG_LOW__SHIFT 0x8 |
1918 | #define DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc |
1919 | #define DAGB1_RDCLI6__MAX_BW__SHIFT 0xd |
1920 | #define DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 |
1921 | #define DAGB1_RDCLI6__MIN_BW__SHIFT 0x16 |
1922 | #define DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 |
1923 | #define DAGB1_RDCLI6__MAX_OSD__SHIFT 0x1a |
1924 | #define DAGB1_RDCLI6__VIRT_CHAN_MASK 0x00000007L |
1925 | #define DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L |
1926 | #define DAGB1_RDCLI6__URG_HIGH_MASK 0x000000F0L |
1927 | #define DAGB1_RDCLI6__URG_LOW_MASK 0x00000F00L |
1928 | #define DAGB1_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L |
1929 | #define DAGB1_RDCLI6__MAX_BW_MASK 0x001FE000L |
1930 | #define DAGB1_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L |
1931 | #define DAGB1_RDCLI6__MIN_BW_MASK 0x01C00000L |
1932 | #define DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L |
1933 | #define DAGB1_RDCLI6__MAX_OSD_MASK 0xFC000000L |
1934 | //DAGB1_RDCLI7 |
1935 | #define DAGB1_RDCLI7__VIRT_CHAN__SHIFT 0x0 |
1936 | #define DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 |
1937 | #define DAGB1_RDCLI7__URG_HIGH__SHIFT 0x4 |
1938 | #define DAGB1_RDCLI7__URG_LOW__SHIFT 0x8 |
1939 | #define DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc |
1940 | #define DAGB1_RDCLI7__MAX_BW__SHIFT 0xd |
1941 | #define DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 |
1942 | #define DAGB1_RDCLI7__MIN_BW__SHIFT 0x16 |
1943 | #define DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 |
1944 | #define DAGB1_RDCLI7__MAX_OSD__SHIFT 0x1a |
1945 | #define DAGB1_RDCLI7__VIRT_CHAN_MASK 0x00000007L |
1946 | #define DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L |
1947 | #define DAGB1_RDCLI7__URG_HIGH_MASK 0x000000F0L |
1948 | #define DAGB1_RDCLI7__URG_LOW_MASK 0x00000F00L |
1949 | #define DAGB1_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L |
1950 | #define DAGB1_RDCLI7__MAX_BW_MASK 0x001FE000L |
1951 | #define DAGB1_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L |
1952 | #define DAGB1_RDCLI7__MIN_BW_MASK 0x01C00000L |
1953 | #define DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L |
1954 | #define DAGB1_RDCLI7__MAX_OSD_MASK 0xFC000000L |
1955 | //DAGB1_RDCLI8 |
1956 | #define DAGB1_RDCLI8__VIRT_CHAN__SHIFT 0x0 |
1957 | #define DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 |
1958 | #define DAGB1_RDCLI8__URG_HIGH__SHIFT 0x4 |
1959 | #define DAGB1_RDCLI8__URG_LOW__SHIFT 0x8 |
1960 | #define DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc |
1961 | #define DAGB1_RDCLI8__MAX_BW__SHIFT 0xd |
1962 | #define DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 |
1963 | #define DAGB1_RDCLI8__MIN_BW__SHIFT 0x16 |
1964 | #define DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 |
1965 | #define DAGB1_RDCLI8__MAX_OSD__SHIFT 0x1a |
1966 | #define DAGB1_RDCLI8__VIRT_CHAN_MASK 0x00000007L |
1967 | #define DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L |
1968 | #define DAGB1_RDCLI8__URG_HIGH_MASK 0x000000F0L |
1969 | #define DAGB1_RDCLI8__URG_LOW_MASK 0x00000F00L |
1970 | #define DAGB1_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L |
1971 | #define DAGB1_RDCLI8__MAX_BW_MASK 0x001FE000L |
1972 | #define DAGB1_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L |
1973 | #define DAGB1_RDCLI8__MIN_BW_MASK 0x01C00000L |
1974 | #define DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L |
1975 | #define DAGB1_RDCLI8__MAX_OSD_MASK 0xFC000000L |
1976 | //DAGB1_RDCLI9 |
1977 | #define DAGB1_RDCLI9__VIRT_CHAN__SHIFT 0x0 |
1978 | #define DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 |
1979 | #define DAGB1_RDCLI9__URG_HIGH__SHIFT 0x4 |
1980 | #define DAGB1_RDCLI9__URG_LOW__SHIFT 0x8 |
1981 | #define DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc |
1982 | #define DAGB1_RDCLI9__MAX_BW__SHIFT 0xd |
1983 | #define DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 |
1984 | #define DAGB1_RDCLI9__MIN_BW__SHIFT 0x16 |
1985 | #define DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 |
1986 | #define DAGB1_RDCLI9__MAX_OSD__SHIFT 0x1a |
1987 | #define DAGB1_RDCLI9__VIRT_CHAN_MASK 0x00000007L |
1988 | #define DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L |
1989 | #define DAGB1_RDCLI9__URG_HIGH_MASK 0x000000F0L |
1990 | #define DAGB1_RDCLI9__URG_LOW_MASK 0x00000F00L |
1991 | #define DAGB1_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L |
1992 | #define DAGB1_RDCLI9__MAX_BW_MASK 0x001FE000L |
1993 | #define DAGB1_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L |
1994 | #define DAGB1_RDCLI9__MIN_BW_MASK 0x01C00000L |
1995 | #define DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L |
1996 | #define DAGB1_RDCLI9__MAX_OSD_MASK 0xFC000000L |
1997 | //DAGB1_RDCLI10 |
1998 | #define DAGB1_RDCLI10__VIRT_CHAN__SHIFT 0x0 |
1999 | #define DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 |
2000 | #define DAGB1_RDCLI10__URG_HIGH__SHIFT 0x4 |
2001 | #define DAGB1_RDCLI10__URG_LOW__SHIFT 0x8 |
2002 | #define DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc |
2003 | #define DAGB1_RDCLI10__MAX_BW__SHIFT 0xd |
2004 | #define DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 |
2005 | #define DAGB1_RDCLI10__MIN_BW__SHIFT 0x16 |
2006 | #define DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 |
2007 | #define DAGB1_RDCLI10__MAX_OSD__SHIFT 0x1a |
2008 | #define DAGB1_RDCLI10__VIRT_CHAN_MASK 0x00000007L |
2009 | #define DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L |
2010 | #define DAGB1_RDCLI10__URG_HIGH_MASK 0x000000F0L |
2011 | #define DAGB1_RDCLI10__URG_LOW_MASK 0x00000F00L |
2012 | #define DAGB1_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L |
2013 | #define DAGB1_RDCLI10__MAX_BW_MASK 0x001FE000L |
2014 | #define DAGB1_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L |
2015 | #define DAGB1_RDCLI10__MIN_BW_MASK 0x01C00000L |
2016 | #define DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L |
2017 | #define DAGB1_RDCLI10__MAX_OSD_MASK 0xFC000000L |
2018 | //DAGB1_RDCLI11 |
2019 | #define DAGB1_RDCLI11__VIRT_CHAN__SHIFT 0x0 |
2020 | #define DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 |
2021 | #define DAGB1_RDCLI11__URG_HIGH__SHIFT 0x4 |
2022 | #define DAGB1_RDCLI11__URG_LOW__SHIFT 0x8 |
2023 | #define DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc |
2024 | #define DAGB1_RDCLI11__MAX_BW__SHIFT 0xd |
2025 | #define DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 |
2026 | #define DAGB1_RDCLI11__MIN_BW__SHIFT 0x16 |
2027 | #define DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 |
2028 | #define DAGB1_RDCLI11__MAX_OSD__SHIFT 0x1a |
2029 | #define DAGB1_RDCLI11__VIRT_CHAN_MASK 0x00000007L |
2030 | #define DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L |
2031 | #define DAGB1_RDCLI11__URG_HIGH_MASK 0x000000F0L |
2032 | #define DAGB1_RDCLI11__URG_LOW_MASK 0x00000F00L |
2033 | #define DAGB1_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L |
2034 | #define DAGB1_RDCLI11__MAX_BW_MASK 0x001FE000L |
2035 | #define DAGB1_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L |
2036 | #define DAGB1_RDCLI11__MIN_BW_MASK 0x01C00000L |
2037 | #define DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L |
2038 | #define DAGB1_RDCLI11__MAX_OSD_MASK 0xFC000000L |
2039 | //DAGB1_RDCLI12 |
2040 | #define DAGB1_RDCLI12__VIRT_CHAN__SHIFT 0x0 |
2041 | #define DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 |
2042 | #define DAGB1_RDCLI12__URG_HIGH__SHIFT 0x4 |
2043 | #define DAGB1_RDCLI12__URG_LOW__SHIFT 0x8 |
2044 | #define DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc |
2045 | #define DAGB1_RDCLI12__MAX_BW__SHIFT 0xd |
2046 | #define DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 |
2047 | #define DAGB1_RDCLI12__MIN_BW__SHIFT 0x16 |
2048 | #define DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 |
2049 | #define DAGB1_RDCLI12__MAX_OSD__SHIFT 0x1a |
2050 | #define DAGB1_RDCLI12__VIRT_CHAN_MASK 0x00000007L |
2051 | #define DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L |
2052 | #define DAGB1_RDCLI12__URG_HIGH_MASK 0x000000F0L |
2053 | #define DAGB1_RDCLI12__URG_LOW_MASK 0x00000F00L |
2054 | #define DAGB1_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L |
2055 | #define DAGB1_RDCLI12__MAX_BW_MASK 0x001FE000L |
2056 | #define DAGB1_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L |
2057 | #define DAGB1_RDCLI12__MIN_BW_MASK 0x01C00000L |
2058 | #define DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L |
2059 | #define DAGB1_RDCLI12__MAX_OSD_MASK 0xFC000000L |
2060 | //DAGB1_RDCLI13 |
2061 | #define DAGB1_RDCLI13__VIRT_CHAN__SHIFT 0x0 |
2062 | #define DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 |
2063 | #define DAGB1_RDCLI13__URG_HIGH__SHIFT 0x4 |
2064 | #define DAGB1_RDCLI13__URG_LOW__SHIFT 0x8 |
2065 | #define DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc |
2066 | #define DAGB1_RDCLI13__MAX_BW__SHIFT 0xd |
2067 | #define DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 |
2068 | #define DAGB1_RDCLI13__MIN_BW__SHIFT 0x16 |
2069 | #define DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 |
2070 | #define DAGB1_RDCLI13__MAX_OSD__SHIFT 0x1a |
2071 | #define DAGB1_RDCLI13__VIRT_CHAN_MASK 0x00000007L |
2072 | #define DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L |
2073 | #define DAGB1_RDCLI13__URG_HIGH_MASK 0x000000F0L |
2074 | #define DAGB1_RDCLI13__URG_LOW_MASK 0x00000F00L |
2075 | #define DAGB1_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L |
2076 | #define DAGB1_RDCLI13__MAX_BW_MASK 0x001FE000L |
2077 | #define DAGB1_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L |
2078 | #define DAGB1_RDCLI13__MIN_BW_MASK 0x01C00000L |
2079 | #define DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L |
2080 | #define DAGB1_RDCLI13__MAX_OSD_MASK 0xFC000000L |
2081 | //DAGB1_RDCLI14 |
2082 | #define DAGB1_RDCLI14__VIRT_CHAN__SHIFT 0x0 |
2083 | #define DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 |
2084 | #define DAGB1_RDCLI14__URG_HIGH__SHIFT 0x4 |
2085 | #define DAGB1_RDCLI14__URG_LOW__SHIFT 0x8 |
2086 | #define DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc |
2087 | #define DAGB1_RDCLI14__MAX_BW__SHIFT 0xd |
2088 | #define DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 |
2089 | #define DAGB1_RDCLI14__MIN_BW__SHIFT 0x16 |
2090 | #define DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 |
2091 | #define DAGB1_RDCLI14__MAX_OSD__SHIFT 0x1a |
2092 | #define DAGB1_RDCLI14__VIRT_CHAN_MASK 0x00000007L |
2093 | #define DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L |
2094 | #define DAGB1_RDCLI14__URG_HIGH_MASK 0x000000F0L |
2095 | #define DAGB1_RDCLI14__URG_LOW_MASK 0x00000F00L |
2096 | #define DAGB1_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L |
2097 | #define DAGB1_RDCLI14__MAX_BW_MASK 0x001FE000L |
2098 | #define DAGB1_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L |
2099 | #define DAGB1_RDCLI14__MIN_BW_MASK 0x01C00000L |
2100 | #define DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L |
2101 | #define DAGB1_RDCLI14__MAX_OSD_MASK 0xFC000000L |
2102 | //DAGB1_RDCLI15 |
2103 | #define DAGB1_RDCLI15__VIRT_CHAN__SHIFT 0x0 |
2104 | #define DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 |
2105 | #define DAGB1_RDCLI15__URG_HIGH__SHIFT 0x4 |
2106 | #define DAGB1_RDCLI15__URG_LOW__SHIFT 0x8 |
2107 | #define DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc |
2108 | #define DAGB1_RDCLI15__MAX_BW__SHIFT 0xd |
2109 | #define DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 |
2110 | #define DAGB1_RDCLI15__MIN_BW__SHIFT 0x16 |
2111 | #define DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 |
2112 | #define DAGB1_RDCLI15__MAX_OSD__SHIFT 0x1a |
2113 | #define DAGB1_RDCLI15__VIRT_CHAN_MASK 0x00000007L |
2114 | #define DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L |
2115 | #define DAGB1_RDCLI15__URG_HIGH_MASK 0x000000F0L |
2116 | #define DAGB1_RDCLI15__URG_LOW_MASK 0x00000F00L |
2117 | #define DAGB1_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L |
2118 | #define DAGB1_RDCLI15__MAX_BW_MASK 0x001FE000L |
2119 | #define DAGB1_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L |
2120 | #define DAGB1_RDCLI15__MIN_BW_MASK 0x01C00000L |
2121 | #define DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L |
2122 | #define DAGB1_RDCLI15__MAX_OSD_MASK 0xFC000000L |
2123 | //DAGB1_RD_CNTL |
2124 | #define DAGB1_RD_CNTL__SCLK_FREQ__SHIFT 0x0 |
2125 | #define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 |
2126 | #define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa |
2127 | #define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 |
2128 | #define DAGB1_RD_CNTL__IO_LEVEL__SHIFT 0x11 |
2129 | #define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 |
2130 | #define DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 |
2131 | #define DAGB1_RD_CNTL__FIX_JUMP__SHIFT 0x1a |
2132 | #define DAGB1_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL |
2133 | #define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L |
2134 | #define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L |
2135 | #define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L |
2136 | #define DAGB1_RD_CNTL__IO_LEVEL_MASK 0x000E0000L |
2137 | #define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L |
2138 | #define DAGB1_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L |
2139 | #define DAGB1_RD_CNTL__FIX_JUMP_MASK 0x04000000L |
2140 | //DAGB1_RD_GMI_CNTL |
2141 | #define DAGB1_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 |
2142 | #define DAGB1_RD_GMI_CNTL__LEVEL__SHIFT 0x6 |
2143 | #define DAGB1_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 |
2144 | #define DAGB1_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd |
2145 | #define DAGB1_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL |
2146 | #define DAGB1_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L |
2147 | #define DAGB1_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L |
2148 | #define DAGB1_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L |
2149 | //DAGB1_RD_ADDR_DAGB |
2150 | #define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 |
2151 | #define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 |
2152 | #define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 |
2153 | #define DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 |
2154 | #define DAGB1_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd |
2155 | #define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L |
2156 | #define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L |
2157 | #define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L |
2158 | #define DAGB1_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L |
2159 | #define DAGB1_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L |
2160 | //DAGB1_RD_OUTPUT_DAGB_MAX_BURST |
2161 | #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 |
2162 | #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 |
2163 | #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 |
2164 | #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc |
2165 | #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 |
2166 | #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 |
2167 | #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 |
2168 | #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c |
2169 | #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL |
2170 | #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L |
2171 | #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L |
2172 | #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L |
2173 | #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L |
2174 | #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L |
2175 | #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L |
2176 | #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L |
2177 | //DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER |
2178 | #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 |
2179 | #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 |
2180 | #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 |
2181 | #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc |
2182 | #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 |
2183 | #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 |
2184 | #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 |
2185 | #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c |
2186 | #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL |
2187 | #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L |
2188 | #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L |
2189 | #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L |
2190 | #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L |
2191 | #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L |
2192 | #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L |
2193 | #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L |
2194 | //DAGB1_RD_CGTT_CLK_CTRL |
2195 | #define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
2196 | #define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
2197 | #define DAGB1_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
2198 | #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
2199 | #define DAGB1_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
2200 | #define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
2201 | #define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
2202 | #define DAGB1_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
2203 | #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
2204 | #define DAGB1_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
2205 | //DAGB1_L1TLB_RD_CGTT_CLK_CTRL |
2206 | #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
2207 | #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
2208 | #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
2209 | #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
2210 | #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
2211 | #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
2212 | #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
2213 | #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
2214 | #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
2215 | #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
2216 | //DAGB1_ATCVM_RD_CGTT_CLK_CTRL |
2217 | #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
2218 | #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
2219 | #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
2220 | #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
2221 | #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
2222 | #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
2223 | #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
2224 | #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
2225 | #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
2226 | #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
2227 | //DAGB1_RD_ADDR_DAGB_MAX_BURST0 |
2228 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 |
2229 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 |
2230 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 |
2231 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc |
2232 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 |
2233 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 |
2234 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 |
2235 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c |
2236 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL |
2237 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L |
2238 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L |
2239 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L |
2240 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L |
2241 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L |
2242 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L |
2243 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L |
2244 | //DAGB1_RD_ADDR_DAGB_LAZY_TIMER0 |
2245 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 |
2246 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 |
2247 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 |
2248 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc |
2249 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 |
2250 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 |
2251 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 |
2252 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c |
2253 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL |
2254 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L |
2255 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L |
2256 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L |
2257 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L |
2258 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L |
2259 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L |
2260 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L |
2261 | //DAGB1_RD_ADDR_DAGB_MAX_BURST1 |
2262 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 |
2263 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 |
2264 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 |
2265 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc |
2266 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 |
2267 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 |
2268 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 |
2269 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c |
2270 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL |
2271 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L |
2272 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L |
2273 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L |
2274 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L |
2275 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L |
2276 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L |
2277 | #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L |
2278 | //DAGB1_RD_ADDR_DAGB_LAZY_TIMER1 |
2279 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 |
2280 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 |
2281 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 |
2282 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc |
2283 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 |
2284 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 |
2285 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 |
2286 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c |
2287 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL |
2288 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L |
2289 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L |
2290 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L |
2291 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L |
2292 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L |
2293 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L |
2294 | #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L |
2295 | //DAGB1_RD_VC0_CNTL |
2296 | #define DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 |
2297 | #define DAGB1_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 |
2298 | #define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
2299 | #define DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT 0xc |
2300 | #define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
2301 | #define DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 |
2302 | #define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
2303 | #define DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 |
2304 | #define DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL |
2305 | #define DAGB1_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L |
2306 | #define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
2307 | #define DAGB1_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L |
2308 | #define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
2309 | #define DAGB1_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L |
2310 | #define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
2311 | #define DAGB1_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L |
2312 | //DAGB1_RD_VC1_CNTL |
2313 | #define DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 |
2314 | #define DAGB1_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 |
2315 | #define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
2316 | #define DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT 0xc |
2317 | #define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
2318 | #define DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 |
2319 | #define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
2320 | #define DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 |
2321 | #define DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL |
2322 | #define DAGB1_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L |
2323 | #define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
2324 | #define DAGB1_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L |
2325 | #define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
2326 | #define DAGB1_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L |
2327 | #define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
2328 | #define DAGB1_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L |
2329 | //DAGB1_RD_VC2_CNTL |
2330 | #define DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 |
2331 | #define DAGB1_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 |
2332 | #define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
2333 | #define DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT 0xc |
2334 | #define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
2335 | #define DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 |
2336 | #define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
2337 | #define DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 |
2338 | #define DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL |
2339 | #define DAGB1_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L |
2340 | #define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
2341 | #define DAGB1_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L |
2342 | #define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
2343 | #define DAGB1_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L |
2344 | #define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
2345 | #define DAGB1_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L |
2346 | //DAGB1_RD_VC3_CNTL |
2347 | #define DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 |
2348 | #define DAGB1_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 |
2349 | #define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
2350 | #define DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT 0xc |
2351 | #define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
2352 | #define DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 |
2353 | #define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
2354 | #define DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 |
2355 | #define DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL |
2356 | #define DAGB1_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L |
2357 | #define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
2358 | #define DAGB1_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L |
2359 | #define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
2360 | #define DAGB1_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L |
2361 | #define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
2362 | #define DAGB1_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L |
2363 | //DAGB1_RD_VC4_CNTL |
2364 | #define DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 |
2365 | #define DAGB1_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 |
2366 | #define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
2367 | #define DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT 0xc |
2368 | #define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
2369 | #define DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 |
2370 | #define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
2371 | #define DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 |
2372 | #define DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL |
2373 | #define DAGB1_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L |
2374 | #define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
2375 | #define DAGB1_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L |
2376 | #define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
2377 | #define DAGB1_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L |
2378 | #define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
2379 | #define DAGB1_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L |
2380 | //DAGB1_RD_VC5_CNTL |
2381 | #define DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 |
2382 | #define DAGB1_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 |
2383 | #define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
2384 | #define DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT 0xc |
2385 | #define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
2386 | #define DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 |
2387 | #define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
2388 | #define DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 |
2389 | #define DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL |
2390 | #define DAGB1_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L |
2391 | #define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
2392 | #define DAGB1_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L |
2393 | #define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
2394 | #define DAGB1_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L |
2395 | #define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
2396 | #define DAGB1_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L |
2397 | //DAGB1_RD_VC6_CNTL |
2398 | #define DAGB1_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 |
2399 | #define DAGB1_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 |
2400 | #define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
2401 | #define DAGB1_RD_VC6_CNTL__MAX_BW__SHIFT 0xc |
2402 | #define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
2403 | #define DAGB1_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 |
2404 | #define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
2405 | #define DAGB1_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 |
2406 | #define DAGB1_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL |
2407 | #define DAGB1_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L |
2408 | #define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
2409 | #define DAGB1_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L |
2410 | #define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
2411 | #define DAGB1_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L |
2412 | #define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
2413 | #define DAGB1_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L |
2414 | //DAGB1_RD_VC7_CNTL |
2415 | #define DAGB1_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 |
2416 | #define DAGB1_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 |
2417 | #define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
2418 | #define DAGB1_RD_VC7_CNTL__MAX_BW__SHIFT 0xc |
2419 | #define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
2420 | #define DAGB1_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 |
2421 | #define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
2422 | #define DAGB1_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 |
2423 | #define DAGB1_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL |
2424 | #define DAGB1_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L |
2425 | #define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
2426 | #define DAGB1_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L |
2427 | #define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
2428 | #define DAGB1_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L |
2429 | #define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
2430 | #define DAGB1_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L |
2431 | //DAGB1_RD_CNTL_MISC |
2432 | #define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 |
2433 | #define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 |
2434 | #define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd |
2435 | #define DAGB1_RD_CNTL_MISC__STOR_CC_NEW_MODE__SHIFT 0x13 |
2436 | #define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 |
2437 | #define DAGB1_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 |
2438 | #define DAGB1_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a |
2439 | #define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL |
2440 | #define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L |
2441 | #define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L |
2442 | #define DAGB1_RD_CNTL_MISC__STOR_CC_NEW_MODE_MASK 0x00080000L |
2443 | #define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L |
2444 | #define DAGB1_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L |
2445 | #define DAGB1_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L |
2446 | //DAGB1_RD_TLB_CREDIT |
2447 | #define DAGB1_RD_TLB_CREDIT__TLB0__SHIFT 0x0 |
2448 | #define DAGB1_RD_TLB_CREDIT__TLB1__SHIFT 0x5 |
2449 | #define DAGB1_RD_TLB_CREDIT__TLB2__SHIFT 0xa |
2450 | #define DAGB1_RD_TLB_CREDIT__TLB3__SHIFT 0xf |
2451 | #define DAGB1_RD_TLB_CREDIT__TLB4__SHIFT 0x14 |
2452 | #define DAGB1_RD_TLB_CREDIT__TLB5__SHIFT 0x19 |
2453 | #define DAGB1_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL |
2454 | #define DAGB1_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L |
2455 | #define DAGB1_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L |
2456 | #define DAGB1_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L |
2457 | #define DAGB1_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L |
2458 | #define DAGB1_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L |
2459 | //DAGB1_RD_RDRET_CREDIT_CNTL |
2460 | #define DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0 |
2461 | #define DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x6 |
2462 | #define DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xc |
2463 | #define DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0x12 |
2464 | #define DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x18 |
2465 | #define DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e |
2466 | #define DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f |
2467 | #define DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000003FL |
2468 | #define DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x00000FC0L |
2469 | #define DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x0003F000L |
2470 | #define DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x00FC0000L |
2471 | #define DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x3F000000L |
2472 | #define DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L |
2473 | #define DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L |
2474 | //DAGB1_RD_RDRET_CREDIT_CNTL2 |
2475 | #define DAGB1_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT 0x0 |
2476 | #define DAGB1_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT 0x6 |
2477 | #define DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0xc |
2478 | #define DAGB1_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK 0x0000003FL |
2479 | #define DAGB1_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK 0x00000FC0L |
2480 | #define DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0007F000L |
2481 | //DAGB1_RDCLI_ASK_PENDING |
2482 | #define DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 |
2483 | #define DAGB1_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL |
2484 | //DAGB1_RDCLI_GO_PENDING |
2485 | #define DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 |
2486 | #define DAGB1_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL |
2487 | //DAGB1_RDCLI_GBLSEND_PENDING |
2488 | #define DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 |
2489 | #define DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL |
2490 | //DAGB1_RDCLI_TLB_PENDING |
2491 | #define DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 |
2492 | #define DAGB1_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL |
2493 | //DAGB1_RDCLI_OARB_PENDING |
2494 | #define DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 |
2495 | #define DAGB1_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL |
2496 | //DAGB1_RDCLI_OSD_PENDING |
2497 | #define DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 |
2498 | #define DAGB1_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL |
2499 | //DAGB1_RDCLI_NOALLOC_OVERRIDE |
2500 | #define DAGB1_RDCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT 0x0 |
2501 | #define DAGB1_RDCLI_NOALLOC_OVERRIDE__ENABLE_MASK 0x0000FFFFL |
2502 | //DAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE |
2503 | #define DAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT 0x0 |
2504 | #define DAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK 0x0000FFFFL |
2505 | //DAGB1_WRCLI0 |
2506 | #define DAGB1_WRCLI0__VIRT_CHAN__SHIFT 0x0 |
2507 | #define DAGB1_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 |
2508 | #define DAGB1_WRCLI0__URG_HIGH__SHIFT 0x4 |
2509 | #define DAGB1_WRCLI0__URG_LOW__SHIFT 0x8 |
2510 | #define DAGB1_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc |
2511 | #define DAGB1_WRCLI0__MAX_BW__SHIFT 0xd |
2512 | #define DAGB1_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 |
2513 | #define DAGB1_WRCLI0__MIN_BW__SHIFT 0x16 |
2514 | #define DAGB1_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 |
2515 | #define DAGB1_WRCLI0__MAX_OSD__SHIFT 0x1a |
2516 | #define DAGB1_WRCLI0__VIRT_CHAN_MASK 0x00000007L |
2517 | #define DAGB1_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L |
2518 | #define DAGB1_WRCLI0__URG_HIGH_MASK 0x000000F0L |
2519 | #define DAGB1_WRCLI0__URG_LOW_MASK 0x00000F00L |
2520 | #define DAGB1_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L |
2521 | #define DAGB1_WRCLI0__MAX_BW_MASK 0x001FE000L |
2522 | #define DAGB1_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L |
2523 | #define DAGB1_WRCLI0__MIN_BW_MASK 0x01C00000L |
2524 | #define DAGB1_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L |
2525 | #define DAGB1_WRCLI0__MAX_OSD_MASK 0xFC000000L |
2526 | //DAGB1_WRCLI1 |
2527 | #define DAGB1_WRCLI1__VIRT_CHAN__SHIFT 0x0 |
2528 | #define DAGB1_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 |
2529 | #define DAGB1_WRCLI1__URG_HIGH__SHIFT 0x4 |
2530 | #define DAGB1_WRCLI1__URG_LOW__SHIFT 0x8 |
2531 | #define DAGB1_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc |
2532 | #define DAGB1_WRCLI1__MAX_BW__SHIFT 0xd |
2533 | #define DAGB1_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 |
2534 | #define DAGB1_WRCLI1__MIN_BW__SHIFT 0x16 |
2535 | #define DAGB1_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 |
2536 | #define DAGB1_WRCLI1__MAX_OSD__SHIFT 0x1a |
2537 | #define DAGB1_WRCLI1__VIRT_CHAN_MASK 0x00000007L |
2538 | #define DAGB1_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L |
2539 | #define DAGB1_WRCLI1__URG_HIGH_MASK 0x000000F0L |
2540 | #define DAGB1_WRCLI1__URG_LOW_MASK 0x00000F00L |
2541 | #define DAGB1_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L |
2542 | #define DAGB1_WRCLI1__MAX_BW_MASK 0x001FE000L |
2543 | #define DAGB1_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L |
2544 | #define DAGB1_WRCLI1__MIN_BW_MASK 0x01C00000L |
2545 | #define DAGB1_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L |
2546 | #define DAGB1_WRCLI1__MAX_OSD_MASK 0xFC000000L |
2547 | //DAGB1_WRCLI2 |
2548 | #define DAGB1_WRCLI2__VIRT_CHAN__SHIFT 0x0 |
2549 | #define DAGB1_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 |
2550 | #define DAGB1_WRCLI2__URG_HIGH__SHIFT 0x4 |
2551 | #define DAGB1_WRCLI2__URG_LOW__SHIFT 0x8 |
2552 | #define DAGB1_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc |
2553 | #define DAGB1_WRCLI2__MAX_BW__SHIFT 0xd |
2554 | #define DAGB1_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 |
2555 | #define DAGB1_WRCLI2__MIN_BW__SHIFT 0x16 |
2556 | #define DAGB1_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 |
2557 | #define DAGB1_WRCLI2__MAX_OSD__SHIFT 0x1a |
2558 | #define DAGB1_WRCLI2__VIRT_CHAN_MASK 0x00000007L |
2559 | #define DAGB1_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L |
2560 | #define DAGB1_WRCLI2__URG_HIGH_MASK 0x000000F0L |
2561 | #define DAGB1_WRCLI2__URG_LOW_MASK 0x00000F00L |
2562 | #define DAGB1_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L |
2563 | #define DAGB1_WRCLI2__MAX_BW_MASK 0x001FE000L |
2564 | #define DAGB1_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L |
2565 | #define DAGB1_WRCLI2__MIN_BW_MASK 0x01C00000L |
2566 | #define DAGB1_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L |
2567 | #define DAGB1_WRCLI2__MAX_OSD_MASK 0xFC000000L |
2568 | //DAGB1_WRCLI3 |
2569 | #define DAGB1_WRCLI3__VIRT_CHAN__SHIFT 0x0 |
2570 | #define DAGB1_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 |
2571 | #define DAGB1_WRCLI3__URG_HIGH__SHIFT 0x4 |
2572 | #define DAGB1_WRCLI3__URG_LOW__SHIFT 0x8 |
2573 | #define DAGB1_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc |
2574 | #define DAGB1_WRCLI3__MAX_BW__SHIFT 0xd |
2575 | #define DAGB1_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 |
2576 | #define DAGB1_WRCLI3__MIN_BW__SHIFT 0x16 |
2577 | #define DAGB1_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 |
2578 | #define DAGB1_WRCLI3__MAX_OSD__SHIFT 0x1a |
2579 | #define DAGB1_WRCLI3__VIRT_CHAN_MASK 0x00000007L |
2580 | #define DAGB1_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L |
2581 | #define DAGB1_WRCLI3__URG_HIGH_MASK 0x000000F0L |
2582 | #define DAGB1_WRCLI3__URG_LOW_MASK 0x00000F00L |
2583 | #define DAGB1_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L |
2584 | #define DAGB1_WRCLI3__MAX_BW_MASK 0x001FE000L |
2585 | #define DAGB1_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L |
2586 | #define DAGB1_WRCLI3__MIN_BW_MASK 0x01C00000L |
2587 | #define DAGB1_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L |
2588 | #define DAGB1_WRCLI3__MAX_OSD_MASK 0xFC000000L |
2589 | //DAGB1_WRCLI4 |
2590 | #define DAGB1_WRCLI4__VIRT_CHAN__SHIFT 0x0 |
2591 | #define DAGB1_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 |
2592 | #define DAGB1_WRCLI4__URG_HIGH__SHIFT 0x4 |
2593 | #define DAGB1_WRCLI4__URG_LOW__SHIFT 0x8 |
2594 | #define DAGB1_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc |
2595 | #define DAGB1_WRCLI4__MAX_BW__SHIFT 0xd |
2596 | #define DAGB1_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 |
2597 | #define DAGB1_WRCLI4__MIN_BW__SHIFT 0x16 |
2598 | #define DAGB1_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 |
2599 | #define DAGB1_WRCLI4__MAX_OSD__SHIFT 0x1a |
2600 | #define DAGB1_WRCLI4__VIRT_CHAN_MASK 0x00000007L |
2601 | #define DAGB1_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L |
2602 | #define DAGB1_WRCLI4__URG_HIGH_MASK 0x000000F0L |
2603 | #define DAGB1_WRCLI4__URG_LOW_MASK 0x00000F00L |
2604 | #define DAGB1_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L |
2605 | #define DAGB1_WRCLI4__MAX_BW_MASK 0x001FE000L |
2606 | #define DAGB1_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L |
2607 | #define DAGB1_WRCLI4__MIN_BW_MASK 0x01C00000L |
2608 | #define DAGB1_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L |
2609 | #define DAGB1_WRCLI4__MAX_OSD_MASK 0xFC000000L |
2610 | //DAGB1_WRCLI5 |
2611 | #define DAGB1_WRCLI5__VIRT_CHAN__SHIFT 0x0 |
2612 | #define DAGB1_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 |
2613 | #define DAGB1_WRCLI5__URG_HIGH__SHIFT 0x4 |
2614 | #define DAGB1_WRCLI5__URG_LOW__SHIFT 0x8 |
2615 | #define DAGB1_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc |
2616 | #define DAGB1_WRCLI5__MAX_BW__SHIFT 0xd |
2617 | #define DAGB1_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 |
2618 | #define DAGB1_WRCLI5__MIN_BW__SHIFT 0x16 |
2619 | #define DAGB1_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 |
2620 | #define DAGB1_WRCLI5__MAX_OSD__SHIFT 0x1a |
2621 | #define DAGB1_WRCLI5__VIRT_CHAN_MASK 0x00000007L |
2622 | #define DAGB1_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L |
2623 | #define DAGB1_WRCLI5__URG_HIGH_MASK 0x000000F0L |
2624 | #define DAGB1_WRCLI5__URG_LOW_MASK 0x00000F00L |
2625 | #define DAGB1_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L |
2626 | #define DAGB1_WRCLI5__MAX_BW_MASK 0x001FE000L |
2627 | #define DAGB1_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L |
2628 | #define DAGB1_WRCLI5__MIN_BW_MASK 0x01C00000L |
2629 | #define DAGB1_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L |
2630 | #define DAGB1_WRCLI5__MAX_OSD_MASK 0xFC000000L |
2631 | //DAGB1_WRCLI6 |
2632 | #define DAGB1_WRCLI6__VIRT_CHAN__SHIFT 0x0 |
2633 | #define DAGB1_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 |
2634 | #define DAGB1_WRCLI6__URG_HIGH__SHIFT 0x4 |
2635 | #define DAGB1_WRCLI6__URG_LOW__SHIFT 0x8 |
2636 | #define DAGB1_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc |
2637 | #define DAGB1_WRCLI6__MAX_BW__SHIFT 0xd |
2638 | #define DAGB1_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 |
2639 | #define DAGB1_WRCLI6__MIN_BW__SHIFT 0x16 |
2640 | #define DAGB1_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 |
2641 | #define DAGB1_WRCLI6__MAX_OSD__SHIFT 0x1a |
2642 | #define DAGB1_WRCLI6__VIRT_CHAN_MASK 0x00000007L |
2643 | #define DAGB1_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L |
2644 | #define DAGB1_WRCLI6__URG_HIGH_MASK 0x000000F0L |
2645 | #define DAGB1_WRCLI6__URG_LOW_MASK 0x00000F00L |
2646 | #define DAGB1_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L |
2647 | #define DAGB1_WRCLI6__MAX_BW_MASK 0x001FE000L |
2648 | #define DAGB1_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L |
2649 | #define DAGB1_WRCLI6__MIN_BW_MASK 0x01C00000L |
2650 | #define DAGB1_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L |
2651 | #define DAGB1_WRCLI6__MAX_OSD_MASK 0xFC000000L |
2652 | //DAGB1_WRCLI7 |
2653 | #define DAGB1_WRCLI7__VIRT_CHAN__SHIFT 0x0 |
2654 | #define DAGB1_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 |
2655 | #define DAGB1_WRCLI7__URG_HIGH__SHIFT 0x4 |
2656 | #define DAGB1_WRCLI7__URG_LOW__SHIFT 0x8 |
2657 | #define DAGB1_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc |
2658 | #define DAGB1_WRCLI7__MAX_BW__SHIFT 0xd |
2659 | #define DAGB1_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 |
2660 | #define DAGB1_WRCLI7__MIN_BW__SHIFT 0x16 |
2661 | #define DAGB1_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 |
2662 | #define DAGB1_WRCLI7__MAX_OSD__SHIFT 0x1a |
2663 | #define DAGB1_WRCLI7__VIRT_CHAN_MASK 0x00000007L |
2664 | #define DAGB1_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L |
2665 | #define DAGB1_WRCLI7__URG_HIGH_MASK 0x000000F0L |
2666 | #define DAGB1_WRCLI7__URG_LOW_MASK 0x00000F00L |
2667 | #define DAGB1_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L |
2668 | #define DAGB1_WRCLI7__MAX_BW_MASK 0x001FE000L |
2669 | #define DAGB1_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L |
2670 | #define DAGB1_WRCLI7__MIN_BW_MASK 0x01C00000L |
2671 | #define DAGB1_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L |
2672 | #define DAGB1_WRCLI7__MAX_OSD_MASK 0xFC000000L |
2673 | //DAGB1_WRCLI8 |
2674 | #define DAGB1_WRCLI8__VIRT_CHAN__SHIFT 0x0 |
2675 | #define DAGB1_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 |
2676 | #define DAGB1_WRCLI8__URG_HIGH__SHIFT 0x4 |
2677 | #define DAGB1_WRCLI8__URG_LOW__SHIFT 0x8 |
2678 | #define DAGB1_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc |
2679 | #define DAGB1_WRCLI8__MAX_BW__SHIFT 0xd |
2680 | #define DAGB1_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 |
2681 | #define DAGB1_WRCLI8__MIN_BW__SHIFT 0x16 |
2682 | #define DAGB1_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 |
2683 | #define DAGB1_WRCLI8__MAX_OSD__SHIFT 0x1a |
2684 | #define DAGB1_WRCLI8__VIRT_CHAN_MASK 0x00000007L |
2685 | #define DAGB1_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L |
2686 | #define DAGB1_WRCLI8__URG_HIGH_MASK 0x000000F0L |
2687 | #define DAGB1_WRCLI8__URG_LOW_MASK 0x00000F00L |
2688 | #define DAGB1_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L |
2689 | #define DAGB1_WRCLI8__MAX_BW_MASK 0x001FE000L |
2690 | #define DAGB1_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L |
2691 | #define DAGB1_WRCLI8__MIN_BW_MASK 0x01C00000L |
2692 | #define DAGB1_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L |
2693 | #define DAGB1_WRCLI8__MAX_OSD_MASK 0xFC000000L |
2694 | //DAGB1_WRCLI9 |
2695 | #define DAGB1_WRCLI9__VIRT_CHAN__SHIFT 0x0 |
2696 | #define DAGB1_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 |
2697 | #define DAGB1_WRCLI9__URG_HIGH__SHIFT 0x4 |
2698 | #define DAGB1_WRCLI9__URG_LOW__SHIFT 0x8 |
2699 | #define DAGB1_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc |
2700 | #define DAGB1_WRCLI9__MAX_BW__SHIFT 0xd |
2701 | #define DAGB1_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 |
2702 | #define DAGB1_WRCLI9__MIN_BW__SHIFT 0x16 |
2703 | #define DAGB1_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 |
2704 | #define DAGB1_WRCLI9__MAX_OSD__SHIFT 0x1a |
2705 | #define DAGB1_WRCLI9__VIRT_CHAN_MASK 0x00000007L |
2706 | #define DAGB1_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L |
2707 | #define DAGB1_WRCLI9__URG_HIGH_MASK 0x000000F0L |
2708 | #define DAGB1_WRCLI9__URG_LOW_MASK 0x00000F00L |
2709 | #define DAGB1_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L |
2710 | #define DAGB1_WRCLI9__MAX_BW_MASK 0x001FE000L |
2711 | #define DAGB1_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L |
2712 | #define DAGB1_WRCLI9__MIN_BW_MASK 0x01C00000L |
2713 | #define DAGB1_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L |
2714 | #define DAGB1_WRCLI9__MAX_OSD_MASK 0xFC000000L |
2715 | //DAGB1_WRCLI10 |
2716 | #define DAGB1_WRCLI10__VIRT_CHAN__SHIFT 0x0 |
2717 | #define DAGB1_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 |
2718 | #define DAGB1_WRCLI10__URG_HIGH__SHIFT 0x4 |
2719 | #define DAGB1_WRCLI10__URG_LOW__SHIFT 0x8 |
2720 | #define DAGB1_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc |
2721 | #define DAGB1_WRCLI10__MAX_BW__SHIFT 0xd |
2722 | #define DAGB1_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 |
2723 | #define DAGB1_WRCLI10__MIN_BW__SHIFT 0x16 |
2724 | #define DAGB1_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 |
2725 | #define DAGB1_WRCLI10__MAX_OSD__SHIFT 0x1a |
2726 | #define DAGB1_WRCLI10__VIRT_CHAN_MASK 0x00000007L |
2727 | #define DAGB1_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L |
2728 | #define DAGB1_WRCLI10__URG_HIGH_MASK 0x000000F0L |
2729 | #define DAGB1_WRCLI10__URG_LOW_MASK 0x00000F00L |
2730 | #define DAGB1_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L |
2731 | #define DAGB1_WRCLI10__MAX_BW_MASK 0x001FE000L |
2732 | #define DAGB1_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L |
2733 | #define DAGB1_WRCLI10__MIN_BW_MASK 0x01C00000L |
2734 | #define DAGB1_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L |
2735 | #define DAGB1_WRCLI10__MAX_OSD_MASK 0xFC000000L |
2736 | //DAGB1_WRCLI11 |
2737 | #define DAGB1_WRCLI11__VIRT_CHAN__SHIFT 0x0 |
2738 | #define DAGB1_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 |
2739 | #define DAGB1_WRCLI11__URG_HIGH__SHIFT 0x4 |
2740 | #define DAGB1_WRCLI11__URG_LOW__SHIFT 0x8 |
2741 | #define DAGB1_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc |
2742 | #define DAGB1_WRCLI11__MAX_BW__SHIFT 0xd |
2743 | #define DAGB1_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 |
2744 | #define DAGB1_WRCLI11__MIN_BW__SHIFT 0x16 |
2745 | #define DAGB1_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 |
2746 | #define DAGB1_WRCLI11__MAX_OSD__SHIFT 0x1a |
2747 | #define DAGB1_WRCLI11__VIRT_CHAN_MASK 0x00000007L |
2748 | #define DAGB1_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L |
2749 | #define DAGB1_WRCLI11__URG_HIGH_MASK 0x000000F0L |
2750 | #define DAGB1_WRCLI11__URG_LOW_MASK 0x00000F00L |
2751 | #define DAGB1_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L |
2752 | #define DAGB1_WRCLI11__MAX_BW_MASK 0x001FE000L |
2753 | #define DAGB1_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L |
2754 | #define DAGB1_WRCLI11__MIN_BW_MASK 0x01C00000L |
2755 | #define DAGB1_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L |
2756 | #define DAGB1_WRCLI11__MAX_OSD_MASK 0xFC000000L |
2757 | //DAGB1_WRCLI12 |
2758 | #define DAGB1_WRCLI12__VIRT_CHAN__SHIFT 0x0 |
2759 | #define DAGB1_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 |
2760 | #define DAGB1_WRCLI12__URG_HIGH__SHIFT 0x4 |
2761 | #define DAGB1_WRCLI12__URG_LOW__SHIFT 0x8 |
2762 | #define DAGB1_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc |
2763 | #define DAGB1_WRCLI12__MAX_BW__SHIFT 0xd |
2764 | #define DAGB1_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 |
2765 | #define DAGB1_WRCLI12__MIN_BW__SHIFT 0x16 |
2766 | #define DAGB1_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 |
2767 | #define DAGB1_WRCLI12__MAX_OSD__SHIFT 0x1a |
2768 | #define DAGB1_WRCLI12__VIRT_CHAN_MASK 0x00000007L |
2769 | #define DAGB1_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L |
2770 | #define DAGB1_WRCLI12__URG_HIGH_MASK 0x000000F0L |
2771 | #define DAGB1_WRCLI12__URG_LOW_MASK 0x00000F00L |
2772 | #define DAGB1_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L |
2773 | #define DAGB1_WRCLI12__MAX_BW_MASK 0x001FE000L |
2774 | #define DAGB1_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L |
2775 | #define DAGB1_WRCLI12__MIN_BW_MASK 0x01C00000L |
2776 | #define DAGB1_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L |
2777 | #define DAGB1_WRCLI12__MAX_OSD_MASK 0xFC000000L |
2778 | //DAGB1_WRCLI13 |
2779 | #define DAGB1_WRCLI13__VIRT_CHAN__SHIFT 0x0 |
2780 | #define DAGB1_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 |
2781 | #define DAGB1_WRCLI13__URG_HIGH__SHIFT 0x4 |
2782 | #define DAGB1_WRCLI13__URG_LOW__SHIFT 0x8 |
2783 | #define DAGB1_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc |
2784 | #define DAGB1_WRCLI13__MAX_BW__SHIFT 0xd |
2785 | #define DAGB1_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 |
2786 | #define DAGB1_WRCLI13__MIN_BW__SHIFT 0x16 |
2787 | #define DAGB1_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 |
2788 | #define DAGB1_WRCLI13__MAX_OSD__SHIFT 0x1a |
2789 | #define DAGB1_WRCLI13__VIRT_CHAN_MASK 0x00000007L |
2790 | #define DAGB1_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L |
2791 | #define DAGB1_WRCLI13__URG_HIGH_MASK 0x000000F0L |
2792 | #define DAGB1_WRCLI13__URG_LOW_MASK 0x00000F00L |
2793 | #define DAGB1_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L |
2794 | #define DAGB1_WRCLI13__MAX_BW_MASK 0x001FE000L |
2795 | #define DAGB1_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L |
2796 | #define DAGB1_WRCLI13__MIN_BW_MASK 0x01C00000L |
2797 | #define DAGB1_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L |
2798 | #define DAGB1_WRCLI13__MAX_OSD_MASK 0xFC000000L |
2799 | //DAGB1_WRCLI14 |
2800 | #define DAGB1_WRCLI14__VIRT_CHAN__SHIFT 0x0 |
2801 | #define DAGB1_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 |
2802 | #define DAGB1_WRCLI14__URG_HIGH__SHIFT 0x4 |
2803 | #define DAGB1_WRCLI14__URG_LOW__SHIFT 0x8 |
2804 | #define DAGB1_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc |
2805 | #define DAGB1_WRCLI14__MAX_BW__SHIFT 0xd |
2806 | #define DAGB1_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 |
2807 | #define DAGB1_WRCLI14__MIN_BW__SHIFT 0x16 |
2808 | #define DAGB1_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 |
2809 | #define DAGB1_WRCLI14__MAX_OSD__SHIFT 0x1a |
2810 | #define DAGB1_WRCLI14__VIRT_CHAN_MASK 0x00000007L |
2811 | #define DAGB1_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L |
2812 | #define DAGB1_WRCLI14__URG_HIGH_MASK 0x000000F0L |
2813 | #define DAGB1_WRCLI14__URG_LOW_MASK 0x00000F00L |
2814 | #define DAGB1_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L |
2815 | #define DAGB1_WRCLI14__MAX_BW_MASK 0x001FE000L |
2816 | #define DAGB1_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L |
2817 | #define DAGB1_WRCLI14__MIN_BW_MASK 0x01C00000L |
2818 | #define DAGB1_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L |
2819 | #define DAGB1_WRCLI14__MAX_OSD_MASK 0xFC000000L |
2820 | //DAGB1_WRCLI15 |
2821 | #define DAGB1_WRCLI15__VIRT_CHAN__SHIFT 0x0 |
2822 | #define DAGB1_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 |
2823 | #define DAGB1_WRCLI15__URG_HIGH__SHIFT 0x4 |
2824 | #define DAGB1_WRCLI15__URG_LOW__SHIFT 0x8 |
2825 | #define DAGB1_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc |
2826 | #define DAGB1_WRCLI15__MAX_BW__SHIFT 0xd |
2827 | #define DAGB1_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 |
2828 | #define DAGB1_WRCLI15__MIN_BW__SHIFT 0x16 |
2829 | #define DAGB1_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 |
2830 | #define DAGB1_WRCLI15__MAX_OSD__SHIFT 0x1a |
2831 | #define DAGB1_WRCLI15__VIRT_CHAN_MASK 0x00000007L |
2832 | #define DAGB1_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L |
2833 | #define DAGB1_WRCLI15__URG_HIGH_MASK 0x000000F0L |
2834 | #define DAGB1_WRCLI15__URG_LOW_MASK 0x00000F00L |
2835 | #define DAGB1_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L |
2836 | #define DAGB1_WRCLI15__MAX_BW_MASK 0x001FE000L |
2837 | #define DAGB1_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L |
2838 | #define DAGB1_WRCLI15__MIN_BW_MASK 0x01C00000L |
2839 | #define DAGB1_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L |
2840 | #define DAGB1_WRCLI15__MAX_OSD_MASK 0xFC000000L |
2841 | //DAGB1_WR_CNTL |
2842 | #define DAGB1_WR_CNTL__SCLK_FREQ__SHIFT 0x0 |
2843 | #define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 |
2844 | #define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa |
2845 | #define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 |
2846 | #define DAGB1_WR_CNTL__IO_LEVEL__SHIFT 0x11 |
2847 | #define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 |
2848 | #define DAGB1_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 |
2849 | #define DAGB1_WR_CNTL__FIX_JUMP__SHIFT 0x1a |
2850 | #define DAGB1_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL |
2851 | #define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L |
2852 | #define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L |
2853 | #define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L |
2854 | #define DAGB1_WR_CNTL__IO_LEVEL_MASK 0x000E0000L |
2855 | #define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L |
2856 | #define DAGB1_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L |
2857 | #define DAGB1_WR_CNTL__FIX_JUMP_MASK 0x04000000L |
2858 | //DAGB1_WR_GMI_CNTL |
2859 | #define DAGB1_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 |
2860 | #define DAGB1_WR_GMI_CNTL__LEVEL__SHIFT 0x6 |
2861 | #define DAGB1_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 |
2862 | #define DAGB1_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd |
2863 | #define DAGB1_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL |
2864 | #define DAGB1_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L |
2865 | #define DAGB1_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L |
2866 | #define DAGB1_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L |
2867 | //DAGB1_WR_ADDR_DAGB |
2868 | #define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 |
2869 | #define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 |
2870 | #define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 |
2871 | #define DAGB1_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 |
2872 | #define DAGB1_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd |
2873 | #define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L |
2874 | #define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L |
2875 | #define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L |
2876 | #define DAGB1_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L |
2877 | #define DAGB1_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L |
2878 | //DAGB1_WR_OUTPUT_DAGB_MAX_BURST |
2879 | #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 |
2880 | #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 |
2881 | #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 |
2882 | #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc |
2883 | #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 |
2884 | #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 |
2885 | #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 |
2886 | #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c |
2887 | #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL |
2888 | #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L |
2889 | #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L |
2890 | #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L |
2891 | #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L |
2892 | #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L |
2893 | #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L |
2894 | #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L |
2895 | //DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER |
2896 | #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 |
2897 | #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 |
2898 | #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 |
2899 | #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc |
2900 | #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 |
2901 | #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 |
2902 | #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 |
2903 | #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c |
2904 | #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL |
2905 | #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L |
2906 | #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L |
2907 | #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L |
2908 | #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L |
2909 | #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L |
2910 | #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L |
2911 | #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L |
2912 | //DAGB1_WR_CGTT_CLK_CTRL |
2913 | #define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
2914 | #define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
2915 | #define DAGB1_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
2916 | #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
2917 | #define DAGB1_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
2918 | #define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
2919 | #define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
2920 | #define DAGB1_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
2921 | #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
2922 | #define DAGB1_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
2923 | //DAGB1_L1TLB_WR_CGTT_CLK_CTRL |
2924 | #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
2925 | #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
2926 | #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
2927 | #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
2928 | #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
2929 | #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
2930 | #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
2931 | #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
2932 | #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
2933 | #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
2934 | //DAGB1_ATCVM_WR_CGTT_CLK_CTRL |
2935 | #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
2936 | #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
2937 | #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
2938 | #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
2939 | #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
2940 | #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
2941 | #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
2942 | #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
2943 | #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
2944 | #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
2945 | //DAGB1_WR_ADDR_DAGB_MAX_BURST0 |
2946 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 |
2947 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 |
2948 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 |
2949 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc |
2950 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 |
2951 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 |
2952 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 |
2953 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c |
2954 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL |
2955 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L |
2956 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L |
2957 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L |
2958 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L |
2959 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L |
2960 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L |
2961 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L |
2962 | //DAGB1_WR_ADDR_DAGB_LAZY_TIMER0 |
2963 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 |
2964 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 |
2965 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 |
2966 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc |
2967 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 |
2968 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 |
2969 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 |
2970 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c |
2971 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL |
2972 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L |
2973 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L |
2974 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L |
2975 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L |
2976 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L |
2977 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L |
2978 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L |
2979 | //DAGB1_WR_ADDR_DAGB_MAX_BURST1 |
2980 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 |
2981 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 |
2982 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 |
2983 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc |
2984 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 |
2985 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 |
2986 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 |
2987 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c |
2988 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL |
2989 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L |
2990 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L |
2991 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L |
2992 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L |
2993 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L |
2994 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L |
2995 | #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L |
2996 | //DAGB1_WR_ADDR_DAGB_LAZY_TIMER1 |
2997 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 |
2998 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 |
2999 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 |
3000 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc |
3001 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 |
3002 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 |
3003 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 |
3004 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c |
3005 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL |
3006 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L |
3007 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L |
3008 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L |
3009 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L |
3010 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L |
3011 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L |
3012 | #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L |
3013 | //DAGB1_WR_DATA_DAGB |
3014 | #define DAGB1_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 |
3015 | #define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 |
3016 | #define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 |
3017 | #define DAGB1_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 |
3018 | #define DAGB1_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L |
3019 | #define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L |
3020 | #define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L |
3021 | #define DAGB1_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L |
3022 | //DAGB1_WR_DATA_DAGB_MAX_BURST0 |
3023 | #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 |
3024 | #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 |
3025 | #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 |
3026 | #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc |
3027 | #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 |
3028 | #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 |
3029 | #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 |
3030 | #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c |
3031 | #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL |
3032 | #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L |
3033 | #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L |
3034 | #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L |
3035 | #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L |
3036 | #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L |
3037 | #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L |
3038 | #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L |
3039 | //DAGB1_WR_DATA_DAGB_LAZY_TIMER0 |
3040 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 |
3041 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 |
3042 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 |
3043 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc |
3044 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 |
3045 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 |
3046 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 |
3047 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c |
3048 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL |
3049 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L |
3050 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L |
3051 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L |
3052 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L |
3053 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L |
3054 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L |
3055 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L |
3056 | //DAGB1_WR_DATA_DAGB_MAX_BURST1 |
3057 | #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 |
3058 | #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 |
3059 | #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 |
3060 | #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc |
3061 | #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 |
3062 | #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 |
3063 | #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 |
3064 | #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c |
3065 | #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL |
3066 | #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L |
3067 | #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L |
3068 | #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L |
3069 | #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L |
3070 | #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L |
3071 | #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L |
3072 | #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L |
3073 | //DAGB1_WR_DATA_DAGB_LAZY_TIMER1 |
3074 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 |
3075 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 |
3076 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 |
3077 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc |
3078 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 |
3079 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 |
3080 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 |
3081 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c |
3082 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL |
3083 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L |
3084 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L |
3085 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L |
3086 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L |
3087 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L |
3088 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L |
3089 | #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L |
3090 | //DAGB1_WR_VC0_CNTL |
3091 | #define DAGB1_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 |
3092 | #define DAGB1_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 |
3093 | #define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
3094 | #define DAGB1_WR_VC0_CNTL__MAX_BW__SHIFT 0xc |
3095 | #define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
3096 | #define DAGB1_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 |
3097 | #define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
3098 | #define DAGB1_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 |
3099 | #define DAGB1_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL |
3100 | #define DAGB1_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L |
3101 | #define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
3102 | #define DAGB1_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L |
3103 | #define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
3104 | #define DAGB1_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L |
3105 | #define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
3106 | #define DAGB1_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L |
3107 | //DAGB1_WR_VC1_CNTL |
3108 | #define DAGB1_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 |
3109 | #define DAGB1_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 |
3110 | #define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
3111 | #define DAGB1_WR_VC1_CNTL__MAX_BW__SHIFT 0xc |
3112 | #define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
3113 | #define DAGB1_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 |
3114 | #define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
3115 | #define DAGB1_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 |
3116 | #define DAGB1_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL |
3117 | #define DAGB1_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L |
3118 | #define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
3119 | #define DAGB1_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L |
3120 | #define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
3121 | #define DAGB1_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L |
3122 | #define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
3123 | #define DAGB1_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L |
3124 | //DAGB1_WR_VC2_CNTL |
3125 | #define DAGB1_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 |
3126 | #define DAGB1_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 |
3127 | #define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
3128 | #define DAGB1_WR_VC2_CNTL__MAX_BW__SHIFT 0xc |
3129 | #define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
3130 | #define DAGB1_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 |
3131 | #define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
3132 | #define DAGB1_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 |
3133 | #define DAGB1_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL |
3134 | #define DAGB1_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L |
3135 | #define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
3136 | #define DAGB1_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L |
3137 | #define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
3138 | #define DAGB1_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L |
3139 | #define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
3140 | #define DAGB1_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L |
3141 | //DAGB1_WR_VC3_CNTL |
3142 | #define DAGB1_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 |
3143 | #define DAGB1_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 |
3144 | #define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
3145 | #define DAGB1_WR_VC3_CNTL__MAX_BW__SHIFT 0xc |
3146 | #define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
3147 | #define DAGB1_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 |
3148 | #define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
3149 | #define DAGB1_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 |
3150 | #define DAGB1_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL |
3151 | #define DAGB1_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L |
3152 | #define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
3153 | #define DAGB1_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L |
3154 | #define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
3155 | #define DAGB1_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L |
3156 | #define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
3157 | #define DAGB1_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L |
3158 | //DAGB1_WR_VC4_CNTL |
3159 | #define DAGB1_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 |
3160 | #define DAGB1_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 |
3161 | #define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
3162 | #define DAGB1_WR_VC4_CNTL__MAX_BW__SHIFT 0xc |
3163 | #define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
3164 | #define DAGB1_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 |
3165 | #define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
3166 | #define DAGB1_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 |
3167 | #define DAGB1_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL |
3168 | #define DAGB1_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L |
3169 | #define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
3170 | #define DAGB1_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L |
3171 | #define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
3172 | #define DAGB1_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L |
3173 | #define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
3174 | #define DAGB1_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L |
3175 | //DAGB1_WR_VC5_CNTL |
3176 | #define DAGB1_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 |
3177 | #define DAGB1_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 |
3178 | #define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
3179 | #define DAGB1_WR_VC5_CNTL__MAX_BW__SHIFT 0xc |
3180 | #define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
3181 | #define DAGB1_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 |
3182 | #define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
3183 | #define DAGB1_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 |
3184 | #define DAGB1_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL |
3185 | #define DAGB1_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L |
3186 | #define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
3187 | #define DAGB1_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L |
3188 | #define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
3189 | #define DAGB1_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L |
3190 | #define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
3191 | #define DAGB1_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L |
3192 | //DAGB1_WR_VC6_CNTL |
3193 | #define DAGB1_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 |
3194 | #define DAGB1_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 |
3195 | #define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
3196 | #define DAGB1_WR_VC6_CNTL__MAX_BW__SHIFT 0xc |
3197 | #define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
3198 | #define DAGB1_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 |
3199 | #define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
3200 | #define DAGB1_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 |
3201 | #define DAGB1_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL |
3202 | #define DAGB1_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L |
3203 | #define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
3204 | #define DAGB1_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L |
3205 | #define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
3206 | #define DAGB1_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L |
3207 | #define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
3208 | #define DAGB1_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L |
3209 | //DAGB1_WR_VC7_CNTL |
3210 | #define DAGB1_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 |
3211 | #define DAGB1_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 |
3212 | #define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
3213 | #define DAGB1_WR_VC7_CNTL__MAX_BW__SHIFT 0xc |
3214 | #define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
3215 | #define DAGB1_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 |
3216 | #define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
3217 | #define DAGB1_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 |
3218 | #define DAGB1_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL |
3219 | #define DAGB1_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L |
3220 | #define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
3221 | #define DAGB1_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L |
3222 | #define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
3223 | #define DAGB1_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L |
3224 | #define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
3225 | #define DAGB1_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L |
3226 | //DAGB1_WR_CNTL_MISC |
3227 | #define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 |
3228 | #define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 |
3229 | #define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd |
3230 | #define DAGB1_WR_CNTL_MISC__STOR_CC_NEW_MODE__SHIFT 0x13 |
3231 | #define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 |
3232 | #define DAGB1_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 |
3233 | #define DAGB1_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a |
3234 | #define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL |
3235 | #define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L |
3236 | #define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L |
3237 | #define DAGB1_WR_CNTL_MISC__STOR_CC_NEW_MODE_MASK 0x00080000L |
3238 | #define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L |
3239 | #define DAGB1_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L |
3240 | #define DAGB1_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L |
3241 | //DAGB1_WR_TLB_CREDIT |
3242 | #define DAGB1_WR_TLB_CREDIT__TLB0__SHIFT 0x0 |
3243 | #define DAGB1_WR_TLB_CREDIT__TLB1__SHIFT 0x5 |
3244 | #define DAGB1_WR_TLB_CREDIT__TLB2__SHIFT 0xa |
3245 | #define DAGB1_WR_TLB_CREDIT__TLB3__SHIFT 0xf |
3246 | #define DAGB1_WR_TLB_CREDIT__TLB4__SHIFT 0x14 |
3247 | #define DAGB1_WR_TLB_CREDIT__TLB5__SHIFT 0x19 |
3248 | #define DAGB1_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL |
3249 | #define DAGB1_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L |
3250 | #define DAGB1_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L |
3251 | #define DAGB1_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L |
3252 | #define DAGB1_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L |
3253 | #define DAGB1_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L |
3254 | //DAGB1_WR_DATA_CREDIT |
3255 | #define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 |
3256 | #define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 |
3257 | #define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 |
3258 | #define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 |
3259 | #define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL |
3260 | #define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L |
3261 | #define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L |
3262 | #define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L |
3263 | //DAGB1_WR_MISC_CREDIT |
3264 | #define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 |
3265 | #define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 |
3266 | #define DAGB1_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 |
3267 | #define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 |
3268 | #define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL |
3269 | #define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L |
3270 | #define DAGB1_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L |
3271 | #define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L |
3272 | //DAGB1_WR_OSD_CREDIT_CNTL1 |
3273 | #define DAGB1_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 |
3274 | #define DAGB1_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x4 |
3275 | #define DAGB1_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0x8 |
3276 | #define DAGB1_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xc |
3277 | #define DAGB1_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT 0x10 |
3278 | #define DAGB1_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT 0x14 |
3279 | #define DAGB1_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x18 |
3280 | #define DAGB1_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000000FL |
3281 | #define DAGB1_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000000F0L |
3282 | #define DAGB1_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00000F00L |
3283 | #define DAGB1_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK 0x0000F000L |
3284 | #define DAGB1_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK 0x000F0000L |
3285 | #define DAGB1_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK 0x00F00000L |
3286 | #define DAGB1_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK 0x3F000000L |
3287 | //DAGB1_WR_OSD_CREDIT_CNTL2 |
3288 | #define DAGB1_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT 0x0 |
3289 | #define DAGB1_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT 0x4 |
3290 | #define DAGB1_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK 0x0000000FL |
3291 | #define DAGB1_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK 0x00000010L |
3292 | //DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1 |
3293 | #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 |
3294 | #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 |
3295 | #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa |
3296 | #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf |
3297 | #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 |
3298 | #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19 |
3299 | #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a |
3300 | #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b |
3301 | #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT 0x1c |
3302 | #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT 0x1d |
3303 | #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL |
3304 | #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L |
3305 | #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L |
3306 | #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L |
3307 | #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L |
3308 | #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L |
3309 | #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L |
3310 | #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L |
3311 | #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK 0x10000000L |
3312 | #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK 0x20000000L |
3313 | //DAGB1_WRCLI_GPU_SNOOP_OVERRIDE |
3314 | #define DAGB1_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 |
3315 | #define DAGB1_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0x0000FFFFL |
3316 | //DAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE |
3317 | #define DAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 |
3318 | #define DAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0x0000FFFFL |
3319 | //DAGB1_WRCLI_ASK_PENDING |
3320 | #define DAGB1_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 |
3321 | #define DAGB1_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL |
3322 | //DAGB1_WRCLI_GO_PENDING |
3323 | #define DAGB1_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 |
3324 | #define DAGB1_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL |
3325 | //DAGB1_WRCLI_GBLSEND_PENDING |
3326 | #define DAGB1_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 |
3327 | #define DAGB1_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL |
3328 | //DAGB1_WRCLI_TLB_PENDING |
3329 | #define DAGB1_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 |
3330 | #define DAGB1_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL |
3331 | //DAGB1_WRCLI_OARB_PENDING |
3332 | #define DAGB1_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 |
3333 | #define DAGB1_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL |
3334 | //DAGB1_WRCLI_OSD_PENDING |
3335 | #define DAGB1_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 |
3336 | #define DAGB1_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL |
3337 | //DAGB1_WRCLI_DBUS_ASK_PENDING |
3338 | #define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 |
3339 | #define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL |
3340 | //DAGB1_WRCLI_DBUS_GO_PENDING |
3341 | #define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 |
3342 | #define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL |
3343 | //DAGB1_DAGB_DLY |
3344 | #define DAGB1_DAGB_DLY__DLY__SHIFT 0x0 |
3345 | #define DAGB1_DAGB_DLY__CLI__SHIFT 0x8 |
3346 | #define DAGB1_DAGB_DLY__POS__SHIFT 0x10 |
3347 | #define DAGB1_DAGB_DLY__DLY_MASK 0x000000FFL |
3348 | #define DAGB1_DAGB_DLY__CLI_MASK 0x0000FF00L |
3349 | #define DAGB1_DAGB_DLY__POS_MASK 0x000F0000L |
3350 | //DAGB1_CNTL_MISC |
3351 | #define DAGB1_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 |
3352 | #define DAGB1_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 |
3353 | #define DAGB1_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 |
3354 | #define DAGB1_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 |
3355 | #define DAGB1_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc |
3356 | #define DAGB1_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf |
3357 | #define DAGB1_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 |
3358 | #define DAGB1_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 |
3359 | #define DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 |
3360 | #define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e |
3361 | #define DAGB1_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L |
3362 | #define DAGB1_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L |
3363 | #define DAGB1_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L |
3364 | #define DAGB1_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L |
3365 | #define DAGB1_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L |
3366 | #define DAGB1_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L |
3367 | #define DAGB1_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L |
3368 | #define DAGB1_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L |
3369 | #define DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L |
3370 | #define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L |
3371 | //DAGB1_CNTL_MISC2 |
3372 | #define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 |
3373 | #define DAGB1_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 |
3374 | #define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 |
3375 | #define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 |
3376 | #define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 |
3377 | #define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 |
3378 | #define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 |
3379 | #define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 |
3380 | #define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 |
3381 | #define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 |
3382 | #define DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT 0xa |
3383 | #define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb |
3384 | #define DAGB1_CNTL_MISC2__HDP_CID__SHIFT 0xc |
3385 | #define DAGB1_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x10 |
3386 | #define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L |
3387 | #define DAGB1_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L |
3388 | #define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L |
3389 | #define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L |
3390 | #define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L |
3391 | #define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L |
3392 | #define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L |
3393 | #define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L |
3394 | #define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L |
3395 | #define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L |
3396 | #define DAGB1_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L |
3397 | #define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L |
3398 | #define DAGB1_CNTL_MISC2__HDP_CID_MASK 0x0000F000L |
3399 | #define DAGB1_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x003F0000L |
3400 | //DAGB1_FATAL_ERROR_CNTL |
3401 | #define DAGB1_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0 |
3402 | #define DAGB1_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL |
3403 | //DAGB1_FATAL_ERROR_CLEAR |
3404 | #define DAGB1_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0 |
3405 | #define DAGB1_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L |
3406 | //DAGB1_FATAL_ERROR_STATUS0 |
3407 | #define DAGB1_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0 |
3408 | #define DAGB1_FATAL_ERROR_STATUS0__CID__SHIFT 0x1 |
3409 | #define DAGB1_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6 |
3410 | #define DAGB1_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L |
3411 | #define DAGB1_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL |
3412 | #define DAGB1_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L |
3413 | //DAGB1_FATAL_ERROR_STATUS1 |
3414 | #define DAGB1_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0 |
3415 | #define DAGB1_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL |
3416 | //DAGB1_FATAL_ERROR_STATUS2 |
3417 | #define DAGB1_FATAL_ERROR_STATUS2__TAG__SHIFT 0x0 |
3418 | #define DAGB1_FATAL_ERROR_STATUS2__VFID__SHIFT 0x10 |
3419 | #define DAGB1_FATAL_ERROR_STATUS2__VF__SHIFT 0x14 |
3420 | #define DAGB1_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x15 |
3421 | #define DAGB1_FATAL_ERROR_STATUS2__IO__SHIFT 0x16 |
3422 | #define DAGB1_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x17 |
3423 | #define DAGB1_FATAL_ERROR_STATUS2__DBGMSK__SHIFT 0x18 |
3424 | #define DAGB1_FATAL_ERROR_STATUS2__FED__SHIFT 0x19 |
3425 | #define DAGB1_FATAL_ERROR_STATUS2__TAG_MASK 0x0000FFFFL |
3426 | #define DAGB1_FATAL_ERROR_STATUS2__VFID_MASK 0x000F0000L |
3427 | #define DAGB1_FATAL_ERROR_STATUS2__VF_MASK 0x00100000L |
3428 | #define DAGB1_FATAL_ERROR_STATUS2__SPACE_MASK 0x00200000L |
3429 | #define DAGB1_FATAL_ERROR_STATUS2__IO_MASK 0x00400000L |
3430 | #define DAGB1_FATAL_ERROR_STATUS2__SIZE_MASK 0x00800000L |
3431 | #define DAGB1_FATAL_ERROR_STATUS2__DBGMSK_MASK 0x01000000L |
3432 | #define DAGB1_FATAL_ERROR_STATUS2__FED_MASK 0x02000000L |
3433 | //DAGB1_FATAL_ERROR_STATUS3 |
3434 | #define DAGB1_FATAL_ERROR_STATUS3__NOALLOC__SHIFT 0x0 |
3435 | #define DAGB1_FATAL_ERROR_STATUS3__UNITID__SHIFT 0x1 |
3436 | #define DAGB1_FATAL_ERROR_STATUS3__OP__SHIFT 0x7 |
3437 | #define DAGB1_FATAL_ERROR_STATUS3__SECLEVEL__SHIFT 0xe |
3438 | #define DAGB1_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x11 |
3439 | #define DAGB1_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x12 |
3440 | #define DAGB1_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x13 |
3441 | #define DAGB1_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x14 |
3442 | #define DAGB1_FATAL_ERROR_STATUS3__NACK__SHIFT 0x15 |
3443 | #define DAGB1_FATAL_ERROR_STATUS3__RO__SHIFT 0x17 |
3444 | #define DAGB1_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x18 |
3445 | #define DAGB1_FATAL_ERROR_STATUS3__EOP__SHIFT 0x19 |
3446 | #define DAGB1_FATAL_ERROR_STATUS3__NOALLOC_MASK 0x00000001L |
3447 | #define DAGB1_FATAL_ERROR_STATUS3__UNITID_MASK 0x0000007EL |
3448 | #define DAGB1_FATAL_ERROR_STATUS3__OP_MASK 0x00003F80L |
3449 | #define DAGB1_FATAL_ERROR_STATUS3__SECLEVEL_MASK 0x0001C000L |
3450 | #define DAGB1_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00020000L |
3451 | #define DAGB1_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00040000L |
3452 | #define DAGB1_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00080000L |
3453 | #define DAGB1_FATAL_ERROR_STATUS3__INVAL_MASK 0x00100000L |
3454 | #define DAGB1_FATAL_ERROR_STATUS3__NACK_MASK 0x00600000L |
3455 | #define DAGB1_FATAL_ERROR_STATUS3__RO_MASK 0x00800000L |
3456 | #define DAGB1_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x01000000L |
3457 | #define DAGB1_FATAL_ERROR_STATUS3__EOP_MASK 0x02000000L |
3458 | //DAGB1_FIFO_EMPTY |
3459 | #define DAGB1_FIFO_EMPTY__EMPTY__SHIFT 0x0 |
3460 | #define DAGB1_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL |
3461 | //DAGB1_FIFO_FULL |
3462 | #define DAGB1_FIFO_FULL__FULL__SHIFT 0x0 |
3463 | #define DAGB1_FIFO_FULL__FULL_MASK 0x007FFFFFL |
3464 | //DAGB1_WR_CREDITS_FULL |
3465 | #define DAGB1_WR_CREDITS_FULL__FULL__SHIFT 0x0 |
3466 | #define DAGB1_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL |
3467 | //DAGB1_RD_CREDITS_FULL |
3468 | #define DAGB1_RD_CREDITS_FULL__FULL__SHIFT 0x0 |
3469 | #define DAGB1_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL |
3470 | //DAGB1_PERFCOUNTER_LO |
3471 | #define DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
3472 | #define DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
3473 | //DAGB1_PERFCOUNTER_HI |
3474 | #define DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
3475 | #define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
3476 | #define DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
3477 | #define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
3478 | //DAGB1_PERFCOUNTER0_CFG |
3479 | #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
3480 | #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
3481 | #define DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
3482 | #define DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
3483 | #define DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
3484 | #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
3485 | #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
3486 | #define DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
3487 | #define DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
3488 | #define DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
3489 | //DAGB1_PERFCOUNTER1_CFG |
3490 | #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
3491 | #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
3492 | #define DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
3493 | #define DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
3494 | #define DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
3495 | #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
3496 | #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
3497 | #define DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
3498 | #define DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
3499 | #define DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
3500 | //DAGB1_PERFCOUNTER2_CFG |
3501 | #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 |
3502 | #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 |
3503 | #define DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 |
3504 | #define DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c |
3505 | #define DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d |
3506 | #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL |
3507 | #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L |
3508 | #define DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L |
3509 | #define DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L |
3510 | #define DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L |
3511 | //DAGB1_PERFCOUNTER_RSLT_CNTL |
3512 | #define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
3513 | #define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
3514 | #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
3515 | #define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
3516 | #define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
3517 | #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
3518 | #define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
3519 | #define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
3520 | #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
3521 | #define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
3522 | #define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
3523 | #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
3524 | //DAGB1_L1TLB_REG_RW |
3525 | #define DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 |
3526 | #define DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 |
3527 | #define DAGB1_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT 0x2 |
3528 | #define DAGB1_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT 0x4 |
3529 | #define DAGB1_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT 0x5 |
3530 | #define DAGB1_L1TLB_REG_RW__RESERVE__SHIFT 0x6 |
3531 | #define DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L |
3532 | #define DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L |
3533 | #define DAGB1_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK 0x00000004L |
3534 | #define DAGB1_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK 0x00000010L |
3535 | #define DAGB1_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK 0x00000020L |
3536 | #define DAGB1_L1TLB_REG_RW__RESERVE_MASK 0xFFFFFFC0L |
3537 | |
3538 | |
3539 | // addressBlock: aid_mmhub_dagb_dagbdec2 |
3540 | //DAGB2_RDCLI0 |
3541 | #define DAGB2_RDCLI0__VIRT_CHAN__SHIFT 0x0 |
3542 | #define DAGB2_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 |
3543 | #define DAGB2_RDCLI0__URG_HIGH__SHIFT 0x4 |
3544 | #define DAGB2_RDCLI0__URG_LOW__SHIFT 0x8 |
3545 | #define DAGB2_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc |
3546 | #define DAGB2_RDCLI0__MAX_BW__SHIFT 0xd |
3547 | #define DAGB2_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 |
3548 | #define DAGB2_RDCLI0__MIN_BW__SHIFT 0x16 |
3549 | #define DAGB2_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 |
3550 | #define DAGB2_RDCLI0__MAX_OSD__SHIFT 0x1a |
3551 | #define DAGB2_RDCLI0__VIRT_CHAN_MASK 0x00000007L |
3552 | #define DAGB2_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L |
3553 | #define DAGB2_RDCLI0__URG_HIGH_MASK 0x000000F0L |
3554 | #define DAGB2_RDCLI0__URG_LOW_MASK 0x00000F00L |
3555 | #define DAGB2_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L |
3556 | #define DAGB2_RDCLI0__MAX_BW_MASK 0x001FE000L |
3557 | #define DAGB2_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L |
3558 | #define DAGB2_RDCLI0__MIN_BW_MASK 0x01C00000L |
3559 | #define DAGB2_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L |
3560 | #define DAGB2_RDCLI0__MAX_OSD_MASK 0xFC000000L |
3561 | //DAGB2_RDCLI1 |
3562 | #define DAGB2_RDCLI1__VIRT_CHAN__SHIFT 0x0 |
3563 | #define DAGB2_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 |
3564 | #define DAGB2_RDCLI1__URG_HIGH__SHIFT 0x4 |
3565 | #define DAGB2_RDCLI1__URG_LOW__SHIFT 0x8 |
3566 | #define DAGB2_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc |
3567 | #define DAGB2_RDCLI1__MAX_BW__SHIFT 0xd |
3568 | #define DAGB2_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 |
3569 | #define DAGB2_RDCLI1__MIN_BW__SHIFT 0x16 |
3570 | #define DAGB2_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 |
3571 | #define DAGB2_RDCLI1__MAX_OSD__SHIFT 0x1a |
3572 | #define DAGB2_RDCLI1__VIRT_CHAN_MASK 0x00000007L |
3573 | #define DAGB2_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L |
3574 | #define DAGB2_RDCLI1__URG_HIGH_MASK 0x000000F0L |
3575 | #define DAGB2_RDCLI1__URG_LOW_MASK 0x00000F00L |
3576 | #define DAGB2_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L |
3577 | #define DAGB2_RDCLI1__MAX_BW_MASK 0x001FE000L |
3578 | #define DAGB2_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L |
3579 | #define DAGB2_RDCLI1__MIN_BW_MASK 0x01C00000L |
3580 | #define DAGB2_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L |
3581 | #define DAGB2_RDCLI1__MAX_OSD_MASK 0xFC000000L |
3582 | //DAGB2_RDCLI2 |
3583 | #define DAGB2_RDCLI2__VIRT_CHAN__SHIFT 0x0 |
3584 | #define DAGB2_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 |
3585 | #define DAGB2_RDCLI2__URG_HIGH__SHIFT 0x4 |
3586 | #define DAGB2_RDCLI2__URG_LOW__SHIFT 0x8 |
3587 | #define DAGB2_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc |
3588 | #define DAGB2_RDCLI2__MAX_BW__SHIFT 0xd |
3589 | #define DAGB2_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 |
3590 | #define DAGB2_RDCLI2__MIN_BW__SHIFT 0x16 |
3591 | #define DAGB2_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 |
3592 | #define DAGB2_RDCLI2__MAX_OSD__SHIFT 0x1a |
3593 | #define DAGB2_RDCLI2__VIRT_CHAN_MASK 0x00000007L |
3594 | #define DAGB2_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L |
3595 | #define DAGB2_RDCLI2__URG_HIGH_MASK 0x000000F0L |
3596 | #define DAGB2_RDCLI2__URG_LOW_MASK 0x00000F00L |
3597 | #define DAGB2_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L |
3598 | #define DAGB2_RDCLI2__MAX_BW_MASK 0x001FE000L |
3599 | #define DAGB2_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L |
3600 | #define DAGB2_RDCLI2__MIN_BW_MASK 0x01C00000L |
3601 | #define DAGB2_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L |
3602 | #define DAGB2_RDCLI2__MAX_OSD_MASK 0xFC000000L |
3603 | //DAGB2_RDCLI3 |
3604 | #define DAGB2_RDCLI3__VIRT_CHAN__SHIFT 0x0 |
3605 | #define DAGB2_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 |
3606 | #define DAGB2_RDCLI3__URG_HIGH__SHIFT 0x4 |
3607 | #define DAGB2_RDCLI3__URG_LOW__SHIFT 0x8 |
3608 | #define DAGB2_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc |
3609 | #define DAGB2_RDCLI3__MAX_BW__SHIFT 0xd |
3610 | #define DAGB2_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 |
3611 | #define DAGB2_RDCLI3__MIN_BW__SHIFT 0x16 |
3612 | #define DAGB2_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 |
3613 | #define DAGB2_RDCLI3__MAX_OSD__SHIFT 0x1a |
3614 | #define DAGB2_RDCLI3__VIRT_CHAN_MASK 0x00000007L |
3615 | #define DAGB2_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L |
3616 | #define DAGB2_RDCLI3__URG_HIGH_MASK 0x000000F0L |
3617 | #define DAGB2_RDCLI3__URG_LOW_MASK 0x00000F00L |
3618 | #define DAGB2_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L |
3619 | #define DAGB2_RDCLI3__MAX_BW_MASK 0x001FE000L |
3620 | #define DAGB2_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L |
3621 | #define DAGB2_RDCLI3__MIN_BW_MASK 0x01C00000L |
3622 | #define DAGB2_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L |
3623 | #define DAGB2_RDCLI3__MAX_OSD_MASK 0xFC000000L |
3624 | //DAGB2_RDCLI4 |
3625 | #define DAGB2_RDCLI4__VIRT_CHAN__SHIFT 0x0 |
3626 | #define DAGB2_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 |
3627 | #define DAGB2_RDCLI4__URG_HIGH__SHIFT 0x4 |
3628 | #define DAGB2_RDCLI4__URG_LOW__SHIFT 0x8 |
3629 | #define DAGB2_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc |
3630 | #define DAGB2_RDCLI4__MAX_BW__SHIFT 0xd |
3631 | #define DAGB2_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 |
3632 | #define DAGB2_RDCLI4__MIN_BW__SHIFT 0x16 |
3633 | #define DAGB2_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 |
3634 | #define DAGB2_RDCLI4__MAX_OSD__SHIFT 0x1a |
3635 | #define DAGB2_RDCLI4__VIRT_CHAN_MASK 0x00000007L |
3636 | #define DAGB2_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L |
3637 | #define DAGB2_RDCLI4__URG_HIGH_MASK 0x000000F0L |
3638 | #define DAGB2_RDCLI4__URG_LOW_MASK 0x00000F00L |
3639 | #define DAGB2_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L |
3640 | #define DAGB2_RDCLI4__MAX_BW_MASK 0x001FE000L |
3641 | #define DAGB2_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L |
3642 | #define DAGB2_RDCLI4__MIN_BW_MASK 0x01C00000L |
3643 | #define DAGB2_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L |
3644 | #define DAGB2_RDCLI4__MAX_OSD_MASK 0xFC000000L |
3645 | //DAGB2_RDCLI5 |
3646 | #define DAGB2_RDCLI5__VIRT_CHAN__SHIFT 0x0 |
3647 | #define DAGB2_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 |
3648 | #define DAGB2_RDCLI5__URG_HIGH__SHIFT 0x4 |
3649 | #define DAGB2_RDCLI5__URG_LOW__SHIFT 0x8 |
3650 | #define DAGB2_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc |
3651 | #define DAGB2_RDCLI5__MAX_BW__SHIFT 0xd |
3652 | #define DAGB2_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 |
3653 | #define DAGB2_RDCLI5__MIN_BW__SHIFT 0x16 |
3654 | #define DAGB2_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 |
3655 | #define DAGB2_RDCLI5__MAX_OSD__SHIFT 0x1a |
3656 | #define DAGB2_RDCLI5__VIRT_CHAN_MASK 0x00000007L |
3657 | #define DAGB2_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L |
3658 | #define DAGB2_RDCLI5__URG_HIGH_MASK 0x000000F0L |
3659 | #define DAGB2_RDCLI5__URG_LOW_MASK 0x00000F00L |
3660 | #define DAGB2_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L |
3661 | #define DAGB2_RDCLI5__MAX_BW_MASK 0x001FE000L |
3662 | #define DAGB2_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L |
3663 | #define DAGB2_RDCLI5__MIN_BW_MASK 0x01C00000L |
3664 | #define DAGB2_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L |
3665 | #define DAGB2_RDCLI5__MAX_OSD_MASK 0xFC000000L |
3666 | //DAGB2_RDCLI6 |
3667 | #define DAGB2_RDCLI6__VIRT_CHAN__SHIFT 0x0 |
3668 | #define DAGB2_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 |
3669 | #define DAGB2_RDCLI6__URG_HIGH__SHIFT 0x4 |
3670 | #define DAGB2_RDCLI6__URG_LOW__SHIFT 0x8 |
3671 | #define DAGB2_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc |
3672 | #define DAGB2_RDCLI6__MAX_BW__SHIFT 0xd |
3673 | #define DAGB2_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 |
3674 | #define DAGB2_RDCLI6__MIN_BW__SHIFT 0x16 |
3675 | #define DAGB2_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 |
3676 | #define DAGB2_RDCLI6__MAX_OSD__SHIFT 0x1a |
3677 | #define DAGB2_RDCLI6__VIRT_CHAN_MASK 0x00000007L |
3678 | #define DAGB2_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L |
3679 | #define DAGB2_RDCLI6__URG_HIGH_MASK 0x000000F0L |
3680 | #define DAGB2_RDCLI6__URG_LOW_MASK 0x00000F00L |
3681 | #define DAGB2_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L |
3682 | #define DAGB2_RDCLI6__MAX_BW_MASK 0x001FE000L |
3683 | #define DAGB2_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L |
3684 | #define DAGB2_RDCLI6__MIN_BW_MASK 0x01C00000L |
3685 | #define DAGB2_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L |
3686 | #define DAGB2_RDCLI6__MAX_OSD_MASK 0xFC000000L |
3687 | //DAGB2_RDCLI7 |
3688 | #define DAGB2_RDCLI7__VIRT_CHAN__SHIFT 0x0 |
3689 | #define DAGB2_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 |
3690 | #define DAGB2_RDCLI7__URG_HIGH__SHIFT 0x4 |
3691 | #define DAGB2_RDCLI7__URG_LOW__SHIFT 0x8 |
3692 | #define DAGB2_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc |
3693 | #define DAGB2_RDCLI7__MAX_BW__SHIFT 0xd |
3694 | #define DAGB2_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 |
3695 | #define DAGB2_RDCLI7__MIN_BW__SHIFT 0x16 |
3696 | #define DAGB2_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 |
3697 | #define DAGB2_RDCLI7__MAX_OSD__SHIFT 0x1a |
3698 | #define DAGB2_RDCLI7__VIRT_CHAN_MASK 0x00000007L |
3699 | #define DAGB2_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L |
3700 | #define DAGB2_RDCLI7__URG_HIGH_MASK 0x000000F0L |
3701 | #define DAGB2_RDCLI7__URG_LOW_MASK 0x00000F00L |
3702 | #define DAGB2_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L |
3703 | #define DAGB2_RDCLI7__MAX_BW_MASK 0x001FE000L |
3704 | #define DAGB2_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L |
3705 | #define DAGB2_RDCLI7__MIN_BW_MASK 0x01C00000L |
3706 | #define DAGB2_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L |
3707 | #define DAGB2_RDCLI7__MAX_OSD_MASK 0xFC000000L |
3708 | //DAGB2_RDCLI8 |
3709 | #define DAGB2_RDCLI8__VIRT_CHAN__SHIFT 0x0 |
3710 | #define DAGB2_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 |
3711 | #define DAGB2_RDCLI8__URG_HIGH__SHIFT 0x4 |
3712 | #define DAGB2_RDCLI8__URG_LOW__SHIFT 0x8 |
3713 | #define DAGB2_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc |
3714 | #define DAGB2_RDCLI8__MAX_BW__SHIFT 0xd |
3715 | #define DAGB2_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 |
3716 | #define DAGB2_RDCLI8__MIN_BW__SHIFT 0x16 |
3717 | #define DAGB2_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 |
3718 | #define DAGB2_RDCLI8__MAX_OSD__SHIFT 0x1a |
3719 | #define DAGB2_RDCLI8__VIRT_CHAN_MASK 0x00000007L |
3720 | #define DAGB2_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L |
3721 | #define DAGB2_RDCLI8__URG_HIGH_MASK 0x000000F0L |
3722 | #define DAGB2_RDCLI8__URG_LOW_MASK 0x00000F00L |
3723 | #define DAGB2_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L |
3724 | #define DAGB2_RDCLI8__MAX_BW_MASK 0x001FE000L |
3725 | #define DAGB2_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L |
3726 | #define DAGB2_RDCLI8__MIN_BW_MASK 0x01C00000L |
3727 | #define DAGB2_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L |
3728 | #define DAGB2_RDCLI8__MAX_OSD_MASK 0xFC000000L |
3729 | //DAGB2_RDCLI9 |
3730 | #define DAGB2_RDCLI9__VIRT_CHAN__SHIFT 0x0 |
3731 | #define DAGB2_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 |
3732 | #define DAGB2_RDCLI9__URG_HIGH__SHIFT 0x4 |
3733 | #define DAGB2_RDCLI9__URG_LOW__SHIFT 0x8 |
3734 | #define DAGB2_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc |
3735 | #define DAGB2_RDCLI9__MAX_BW__SHIFT 0xd |
3736 | #define DAGB2_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 |
3737 | #define DAGB2_RDCLI9__MIN_BW__SHIFT 0x16 |
3738 | #define DAGB2_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 |
3739 | #define DAGB2_RDCLI9__MAX_OSD__SHIFT 0x1a |
3740 | #define DAGB2_RDCLI9__VIRT_CHAN_MASK 0x00000007L |
3741 | #define DAGB2_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L |
3742 | #define DAGB2_RDCLI9__URG_HIGH_MASK 0x000000F0L |
3743 | #define DAGB2_RDCLI9__URG_LOW_MASK 0x00000F00L |
3744 | #define DAGB2_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L |
3745 | #define DAGB2_RDCLI9__MAX_BW_MASK 0x001FE000L |
3746 | #define DAGB2_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L |
3747 | #define DAGB2_RDCLI9__MIN_BW_MASK 0x01C00000L |
3748 | #define DAGB2_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L |
3749 | #define DAGB2_RDCLI9__MAX_OSD_MASK 0xFC000000L |
3750 | //DAGB2_RDCLI10 |
3751 | #define DAGB2_RDCLI10__VIRT_CHAN__SHIFT 0x0 |
3752 | #define DAGB2_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 |
3753 | #define DAGB2_RDCLI10__URG_HIGH__SHIFT 0x4 |
3754 | #define DAGB2_RDCLI10__URG_LOW__SHIFT 0x8 |
3755 | #define DAGB2_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc |
3756 | #define DAGB2_RDCLI10__MAX_BW__SHIFT 0xd |
3757 | #define DAGB2_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 |
3758 | #define DAGB2_RDCLI10__MIN_BW__SHIFT 0x16 |
3759 | #define DAGB2_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 |
3760 | #define DAGB2_RDCLI10__MAX_OSD__SHIFT 0x1a |
3761 | #define DAGB2_RDCLI10__VIRT_CHAN_MASK 0x00000007L |
3762 | #define DAGB2_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L |
3763 | #define DAGB2_RDCLI10__URG_HIGH_MASK 0x000000F0L |
3764 | #define DAGB2_RDCLI10__URG_LOW_MASK 0x00000F00L |
3765 | #define DAGB2_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L |
3766 | #define DAGB2_RDCLI10__MAX_BW_MASK 0x001FE000L |
3767 | #define DAGB2_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L |
3768 | #define DAGB2_RDCLI10__MIN_BW_MASK 0x01C00000L |
3769 | #define DAGB2_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L |
3770 | #define DAGB2_RDCLI10__MAX_OSD_MASK 0xFC000000L |
3771 | //DAGB2_RDCLI11 |
3772 | #define DAGB2_RDCLI11__VIRT_CHAN__SHIFT 0x0 |
3773 | #define DAGB2_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 |
3774 | #define DAGB2_RDCLI11__URG_HIGH__SHIFT 0x4 |
3775 | #define DAGB2_RDCLI11__URG_LOW__SHIFT 0x8 |
3776 | #define DAGB2_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc |
3777 | #define DAGB2_RDCLI11__MAX_BW__SHIFT 0xd |
3778 | #define DAGB2_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 |
3779 | #define DAGB2_RDCLI11__MIN_BW__SHIFT 0x16 |
3780 | #define DAGB2_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 |
3781 | #define DAGB2_RDCLI11__MAX_OSD__SHIFT 0x1a |
3782 | #define DAGB2_RDCLI11__VIRT_CHAN_MASK 0x00000007L |
3783 | #define DAGB2_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L |
3784 | #define DAGB2_RDCLI11__URG_HIGH_MASK 0x000000F0L |
3785 | #define DAGB2_RDCLI11__URG_LOW_MASK 0x00000F00L |
3786 | #define DAGB2_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L |
3787 | #define DAGB2_RDCLI11__MAX_BW_MASK 0x001FE000L |
3788 | #define DAGB2_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L |
3789 | #define DAGB2_RDCLI11__MIN_BW_MASK 0x01C00000L |
3790 | #define DAGB2_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L |
3791 | #define DAGB2_RDCLI11__MAX_OSD_MASK 0xFC000000L |
3792 | //DAGB2_RDCLI12 |
3793 | #define DAGB2_RDCLI12__VIRT_CHAN__SHIFT 0x0 |
3794 | #define DAGB2_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 |
3795 | #define DAGB2_RDCLI12__URG_HIGH__SHIFT 0x4 |
3796 | #define DAGB2_RDCLI12__URG_LOW__SHIFT 0x8 |
3797 | #define DAGB2_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc |
3798 | #define DAGB2_RDCLI12__MAX_BW__SHIFT 0xd |
3799 | #define DAGB2_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 |
3800 | #define DAGB2_RDCLI12__MIN_BW__SHIFT 0x16 |
3801 | #define DAGB2_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 |
3802 | #define DAGB2_RDCLI12__MAX_OSD__SHIFT 0x1a |
3803 | #define DAGB2_RDCLI12__VIRT_CHAN_MASK 0x00000007L |
3804 | #define DAGB2_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L |
3805 | #define DAGB2_RDCLI12__URG_HIGH_MASK 0x000000F0L |
3806 | #define DAGB2_RDCLI12__URG_LOW_MASK 0x00000F00L |
3807 | #define DAGB2_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L |
3808 | #define DAGB2_RDCLI12__MAX_BW_MASK 0x001FE000L |
3809 | #define DAGB2_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L |
3810 | #define DAGB2_RDCLI12__MIN_BW_MASK 0x01C00000L |
3811 | #define DAGB2_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L |
3812 | #define DAGB2_RDCLI12__MAX_OSD_MASK 0xFC000000L |
3813 | //DAGB2_RDCLI13 |
3814 | #define DAGB2_RDCLI13__VIRT_CHAN__SHIFT 0x0 |
3815 | #define DAGB2_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 |
3816 | #define DAGB2_RDCLI13__URG_HIGH__SHIFT 0x4 |
3817 | #define DAGB2_RDCLI13__URG_LOW__SHIFT 0x8 |
3818 | #define DAGB2_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc |
3819 | #define DAGB2_RDCLI13__MAX_BW__SHIFT 0xd |
3820 | #define DAGB2_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 |
3821 | #define DAGB2_RDCLI13__MIN_BW__SHIFT 0x16 |
3822 | #define DAGB2_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 |
3823 | #define DAGB2_RDCLI13__MAX_OSD__SHIFT 0x1a |
3824 | #define DAGB2_RDCLI13__VIRT_CHAN_MASK 0x00000007L |
3825 | #define DAGB2_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L |
3826 | #define DAGB2_RDCLI13__URG_HIGH_MASK 0x000000F0L |
3827 | #define DAGB2_RDCLI13__URG_LOW_MASK 0x00000F00L |
3828 | #define DAGB2_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L |
3829 | #define DAGB2_RDCLI13__MAX_BW_MASK 0x001FE000L |
3830 | #define DAGB2_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L |
3831 | #define DAGB2_RDCLI13__MIN_BW_MASK 0x01C00000L |
3832 | #define DAGB2_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L |
3833 | #define DAGB2_RDCLI13__MAX_OSD_MASK 0xFC000000L |
3834 | //DAGB2_RDCLI14 |
3835 | #define DAGB2_RDCLI14__VIRT_CHAN__SHIFT 0x0 |
3836 | #define DAGB2_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 |
3837 | #define DAGB2_RDCLI14__URG_HIGH__SHIFT 0x4 |
3838 | #define DAGB2_RDCLI14__URG_LOW__SHIFT 0x8 |
3839 | #define DAGB2_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc |
3840 | #define DAGB2_RDCLI14__MAX_BW__SHIFT 0xd |
3841 | #define DAGB2_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 |
3842 | #define DAGB2_RDCLI14__MIN_BW__SHIFT 0x16 |
3843 | #define DAGB2_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 |
3844 | #define DAGB2_RDCLI14__MAX_OSD__SHIFT 0x1a |
3845 | #define DAGB2_RDCLI14__VIRT_CHAN_MASK 0x00000007L |
3846 | #define DAGB2_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L |
3847 | #define DAGB2_RDCLI14__URG_HIGH_MASK 0x000000F0L |
3848 | #define DAGB2_RDCLI14__URG_LOW_MASK 0x00000F00L |
3849 | #define DAGB2_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L |
3850 | #define DAGB2_RDCLI14__MAX_BW_MASK 0x001FE000L |
3851 | #define DAGB2_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L |
3852 | #define DAGB2_RDCLI14__MIN_BW_MASK 0x01C00000L |
3853 | #define DAGB2_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L |
3854 | #define DAGB2_RDCLI14__MAX_OSD_MASK 0xFC000000L |
3855 | //DAGB2_RDCLI15 |
3856 | #define DAGB2_RDCLI15__VIRT_CHAN__SHIFT 0x0 |
3857 | #define DAGB2_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 |
3858 | #define DAGB2_RDCLI15__URG_HIGH__SHIFT 0x4 |
3859 | #define DAGB2_RDCLI15__URG_LOW__SHIFT 0x8 |
3860 | #define DAGB2_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc |
3861 | #define DAGB2_RDCLI15__MAX_BW__SHIFT 0xd |
3862 | #define DAGB2_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 |
3863 | #define DAGB2_RDCLI15__MIN_BW__SHIFT 0x16 |
3864 | #define DAGB2_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 |
3865 | #define DAGB2_RDCLI15__MAX_OSD__SHIFT 0x1a |
3866 | #define DAGB2_RDCLI15__VIRT_CHAN_MASK 0x00000007L |
3867 | #define DAGB2_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L |
3868 | #define DAGB2_RDCLI15__URG_HIGH_MASK 0x000000F0L |
3869 | #define DAGB2_RDCLI15__URG_LOW_MASK 0x00000F00L |
3870 | #define DAGB2_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L |
3871 | #define DAGB2_RDCLI15__MAX_BW_MASK 0x001FE000L |
3872 | #define DAGB2_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L |
3873 | #define DAGB2_RDCLI15__MIN_BW_MASK 0x01C00000L |
3874 | #define DAGB2_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L |
3875 | #define DAGB2_RDCLI15__MAX_OSD_MASK 0xFC000000L |
3876 | //DAGB2_RD_CNTL |
3877 | #define DAGB2_RD_CNTL__SCLK_FREQ__SHIFT 0x0 |
3878 | #define DAGB2_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 |
3879 | #define DAGB2_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa |
3880 | #define DAGB2_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 |
3881 | #define DAGB2_RD_CNTL__IO_LEVEL__SHIFT 0x11 |
3882 | #define DAGB2_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 |
3883 | #define DAGB2_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 |
3884 | #define DAGB2_RD_CNTL__FIX_JUMP__SHIFT 0x1a |
3885 | #define DAGB2_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL |
3886 | #define DAGB2_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L |
3887 | #define DAGB2_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L |
3888 | #define DAGB2_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L |
3889 | #define DAGB2_RD_CNTL__IO_LEVEL_MASK 0x000E0000L |
3890 | #define DAGB2_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L |
3891 | #define DAGB2_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L |
3892 | #define DAGB2_RD_CNTL__FIX_JUMP_MASK 0x04000000L |
3893 | //DAGB2_RD_GMI_CNTL |
3894 | #define DAGB2_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 |
3895 | #define DAGB2_RD_GMI_CNTL__LEVEL__SHIFT 0x6 |
3896 | #define DAGB2_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 |
3897 | #define DAGB2_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd |
3898 | #define DAGB2_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL |
3899 | #define DAGB2_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L |
3900 | #define DAGB2_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L |
3901 | #define DAGB2_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L |
3902 | //DAGB2_RD_ADDR_DAGB |
3903 | #define DAGB2_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 |
3904 | #define DAGB2_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 |
3905 | #define DAGB2_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 |
3906 | #define DAGB2_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 |
3907 | #define DAGB2_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd |
3908 | #define DAGB2_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L |
3909 | #define DAGB2_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L |
3910 | #define DAGB2_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L |
3911 | #define DAGB2_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L |
3912 | #define DAGB2_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L |
3913 | //DAGB2_RD_OUTPUT_DAGB_MAX_BURST |
3914 | #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 |
3915 | #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 |
3916 | #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 |
3917 | #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc |
3918 | #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 |
3919 | #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 |
3920 | #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 |
3921 | #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c |
3922 | #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL |
3923 | #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L |
3924 | #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L |
3925 | #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L |
3926 | #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L |
3927 | #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L |
3928 | #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L |
3929 | #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L |
3930 | //DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER |
3931 | #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 |
3932 | #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 |
3933 | #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 |
3934 | #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc |
3935 | #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 |
3936 | #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 |
3937 | #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 |
3938 | #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c |
3939 | #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL |
3940 | #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L |
3941 | #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L |
3942 | #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L |
3943 | #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L |
3944 | #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L |
3945 | #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L |
3946 | #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L |
3947 | //DAGB2_RD_CGTT_CLK_CTRL |
3948 | #define DAGB2_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
3949 | #define DAGB2_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
3950 | #define DAGB2_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
3951 | #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
3952 | #define DAGB2_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
3953 | #define DAGB2_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
3954 | #define DAGB2_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
3955 | #define DAGB2_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
3956 | #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
3957 | #define DAGB2_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
3958 | //DAGB2_L1TLB_RD_CGTT_CLK_CTRL |
3959 | #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
3960 | #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
3961 | #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
3962 | #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
3963 | #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
3964 | #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
3965 | #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
3966 | #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
3967 | #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
3968 | #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
3969 | //DAGB2_ATCVM_RD_CGTT_CLK_CTRL |
3970 | #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
3971 | #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
3972 | #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
3973 | #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
3974 | #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
3975 | #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
3976 | #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
3977 | #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
3978 | #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
3979 | #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
3980 | //DAGB2_RD_ADDR_DAGB_MAX_BURST0 |
3981 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 |
3982 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 |
3983 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 |
3984 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc |
3985 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 |
3986 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 |
3987 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 |
3988 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c |
3989 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL |
3990 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L |
3991 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L |
3992 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L |
3993 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L |
3994 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L |
3995 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L |
3996 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L |
3997 | //DAGB2_RD_ADDR_DAGB_LAZY_TIMER0 |
3998 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 |
3999 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 |
4000 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 |
4001 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc |
4002 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 |
4003 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 |
4004 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 |
4005 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c |
4006 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL |
4007 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L |
4008 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L |
4009 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L |
4010 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L |
4011 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L |
4012 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L |
4013 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L |
4014 | //DAGB2_RD_ADDR_DAGB_MAX_BURST1 |
4015 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 |
4016 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 |
4017 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 |
4018 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc |
4019 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 |
4020 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 |
4021 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 |
4022 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c |
4023 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL |
4024 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L |
4025 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L |
4026 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L |
4027 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L |
4028 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L |
4029 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L |
4030 | #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L |
4031 | //DAGB2_RD_ADDR_DAGB_LAZY_TIMER1 |
4032 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 |
4033 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 |
4034 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 |
4035 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc |
4036 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 |
4037 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 |
4038 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 |
4039 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c |
4040 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL |
4041 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L |
4042 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L |
4043 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L |
4044 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L |
4045 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L |
4046 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L |
4047 | #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L |
4048 | //DAGB2_RD_VC0_CNTL |
4049 | #define DAGB2_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 |
4050 | #define DAGB2_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 |
4051 | #define DAGB2_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
4052 | #define DAGB2_RD_VC0_CNTL__MAX_BW__SHIFT 0xc |
4053 | #define DAGB2_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
4054 | #define DAGB2_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 |
4055 | #define DAGB2_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
4056 | #define DAGB2_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 |
4057 | #define DAGB2_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL |
4058 | #define DAGB2_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L |
4059 | #define DAGB2_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
4060 | #define DAGB2_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L |
4061 | #define DAGB2_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
4062 | #define DAGB2_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L |
4063 | #define DAGB2_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
4064 | #define DAGB2_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L |
4065 | //DAGB2_RD_VC1_CNTL |
4066 | #define DAGB2_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 |
4067 | #define DAGB2_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 |
4068 | #define DAGB2_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
4069 | #define DAGB2_RD_VC1_CNTL__MAX_BW__SHIFT 0xc |
4070 | #define DAGB2_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
4071 | #define DAGB2_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 |
4072 | #define DAGB2_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
4073 | #define DAGB2_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 |
4074 | #define DAGB2_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL |
4075 | #define DAGB2_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L |
4076 | #define DAGB2_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
4077 | #define DAGB2_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L |
4078 | #define DAGB2_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
4079 | #define DAGB2_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L |
4080 | #define DAGB2_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
4081 | #define DAGB2_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L |
4082 | //DAGB2_RD_VC2_CNTL |
4083 | #define DAGB2_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 |
4084 | #define DAGB2_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 |
4085 | #define DAGB2_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
4086 | #define DAGB2_RD_VC2_CNTL__MAX_BW__SHIFT 0xc |
4087 | #define DAGB2_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
4088 | #define DAGB2_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 |
4089 | #define DAGB2_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
4090 | #define DAGB2_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 |
4091 | #define DAGB2_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL |
4092 | #define DAGB2_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L |
4093 | #define DAGB2_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
4094 | #define DAGB2_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L |
4095 | #define DAGB2_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
4096 | #define DAGB2_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L |
4097 | #define DAGB2_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
4098 | #define DAGB2_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L |
4099 | //DAGB2_RD_VC3_CNTL |
4100 | #define DAGB2_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 |
4101 | #define DAGB2_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 |
4102 | #define DAGB2_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
4103 | #define DAGB2_RD_VC3_CNTL__MAX_BW__SHIFT 0xc |
4104 | #define DAGB2_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
4105 | #define DAGB2_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 |
4106 | #define DAGB2_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
4107 | #define DAGB2_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 |
4108 | #define DAGB2_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL |
4109 | #define DAGB2_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L |
4110 | #define DAGB2_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
4111 | #define DAGB2_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L |
4112 | #define DAGB2_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
4113 | #define DAGB2_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L |
4114 | #define DAGB2_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
4115 | #define DAGB2_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L |
4116 | //DAGB2_RD_VC4_CNTL |
4117 | #define DAGB2_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 |
4118 | #define DAGB2_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 |
4119 | #define DAGB2_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
4120 | #define DAGB2_RD_VC4_CNTL__MAX_BW__SHIFT 0xc |
4121 | #define DAGB2_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
4122 | #define DAGB2_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 |
4123 | #define DAGB2_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
4124 | #define DAGB2_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 |
4125 | #define DAGB2_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL |
4126 | #define DAGB2_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L |
4127 | #define DAGB2_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
4128 | #define DAGB2_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L |
4129 | #define DAGB2_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
4130 | #define DAGB2_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L |
4131 | #define DAGB2_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
4132 | #define DAGB2_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L |
4133 | //DAGB2_RD_VC5_CNTL |
4134 | #define DAGB2_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 |
4135 | #define DAGB2_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 |
4136 | #define DAGB2_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
4137 | #define DAGB2_RD_VC5_CNTL__MAX_BW__SHIFT 0xc |
4138 | #define DAGB2_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
4139 | #define DAGB2_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 |
4140 | #define DAGB2_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
4141 | #define DAGB2_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 |
4142 | #define DAGB2_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL |
4143 | #define DAGB2_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L |
4144 | #define DAGB2_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
4145 | #define DAGB2_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L |
4146 | #define DAGB2_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
4147 | #define DAGB2_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L |
4148 | #define DAGB2_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
4149 | #define DAGB2_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L |
4150 | //DAGB2_RD_VC6_CNTL |
4151 | #define DAGB2_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 |
4152 | #define DAGB2_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 |
4153 | #define DAGB2_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
4154 | #define DAGB2_RD_VC6_CNTL__MAX_BW__SHIFT 0xc |
4155 | #define DAGB2_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
4156 | #define DAGB2_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 |
4157 | #define DAGB2_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
4158 | #define DAGB2_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 |
4159 | #define DAGB2_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL |
4160 | #define DAGB2_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L |
4161 | #define DAGB2_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
4162 | #define DAGB2_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L |
4163 | #define DAGB2_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
4164 | #define DAGB2_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L |
4165 | #define DAGB2_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
4166 | #define DAGB2_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L |
4167 | //DAGB2_RD_VC7_CNTL |
4168 | #define DAGB2_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 |
4169 | #define DAGB2_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 |
4170 | #define DAGB2_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
4171 | #define DAGB2_RD_VC7_CNTL__MAX_BW__SHIFT 0xc |
4172 | #define DAGB2_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
4173 | #define DAGB2_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 |
4174 | #define DAGB2_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
4175 | #define DAGB2_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 |
4176 | #define DAGB2_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL |
4177 | #define DAGB2_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L |
4178 | #define DAGB2_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
4179 | #define DAGB2_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L |
4180 | #define DAGB2_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
4181 | #define DAGB2_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L |
4182 | #define DAGB2_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
4183 | #define DAGB2_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L |
4184 | //DAGB2_RD_CNTL_MISC |
4185 | #define DAGB2_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 |
4186 | #define DAGB2_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 |
4187 | #define DAGB2_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd |
4188 | #define DAGB2_RD_CNTL_MISC__STOR_CC_NEW_MODE__SHIFT 0x13 |
4189 | #define DAGB2_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 |
4190 | #define DAGB2_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 |
4191 | #define DAGB2_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a |
4192 | #define DAGB2_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL |
4193 | #define DAGB2_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L |
4194 | #define DAGB2_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L |
4195 | #define DAGB2_RD_CNTL_MISC__STOR_CC_NEW_MODE_MASK 0x00080000L |
4196 | #define DAGB2_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L |
4197 | #define DAGB2_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L |
4198 | #define DAGB2_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L |
4199 | //DAGB2_RD_TLB_CREDIT |
4200 | #define DAGB2_RD_TLB_CREDIT__TLB0__SHIFT 0x0 |
4201 | #define DAGB2_RD_TLB_CREDIT__TLB1__SHIFT 0x5 |
4202 | #define DAGB2_RD_TLB_CREDIT__TLB2__SHIFT 0xa |
4203 | #define DAGB2_RD_TLB_CREDIT__TLB3__SHIFT 0xf |
4204 | #define DAGB2_RD_TLB_CREDIT__TLB4__SHIFT 0x14 |
4205 | #define DAGB2_RD_TLB_CREDIT__TLB5__SHIFT 0x19 |
4206 | #define DAGB2_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL |
4207 | #define DAGB2_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L |
4208 | #define DAGB2_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L |
4209 | #define DAGB2_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L |
4210 | #define DAGB2_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L |
4211 | #define DAGB2_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L |
4212 | //DAGB2_RD_RDRET_CREDIT_CNTL |
4213 | #define DAGB2_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0 |
4214 | #define DAGB2_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x6 |
4215 | #define DAGB2_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xc |
4216 | #define DAGB2_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0x12 |
4217 | #define DAGB2_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x18 |
4218 | #define DAGB2_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e |
4219 | #define DAGB2_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f |
4220 | #define DAGB2_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000003FL |
4221 | #define DAGB2_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x00000FC0L |
4222 | #define DAGB2_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x0003F000L |
4223 | #define DAGB2_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x00FC0000L |
4224 | #define DAGB2_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x3F000000L |
4225 | #define DAGB2_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L |
4226 | #define DAGB2_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L |
4227 | //DAGB2_RD_RDRET_CREDIT_CNTL2 |
4228 | #define DAGB2_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT 0x0 |
4229 | #define DAGB2_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT 0x6 |
4230 | #define DAGB2_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0xc |
4231 | #define DAGB2_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK 0x0000003FL |
4232 | #define DAGB2_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK 0x00000FC0L |
4233 | #define DAGB2_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0007F000L |
4234 | //DAGB2_RDCLI_ASK_PENDING |
4235 | #define DAGB2_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 |
4236 | #define DAGB2_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL |
4237 | //DAGB2_RDCLI_GO_PENDING |
4238 | #define DAGB2_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 |
4239 | #define DAGB2_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL |
4240 | //DAGB2_RDCLI_GBLSEND_PENDING |
4241 | #define DAGB2_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 |
4242 | #define DAGB2_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL |
4243 | //DAGB2_RDCLI_TLB_PENDING |
4244 | #define DAGB2_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 |
4245 | #define DAGB2_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL |
4246 | //DAGB2_RDCLI_OARB_PENDING |
4247 | #define DAGB2_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 |
4248 | #define DAGB2_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL |
4249 | //DAGB2_RDCLI_OSD_PENDING |
4250 | #define DAGB2_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 |
4251 | #define DAGB2_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL |
4252 | //DAGB2_WRCLI0 |
4253 | #define DAGB2_WRCLI0__VIRT_CHAN__SHIFT 0x0 |
4254 | #define DAGB2_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 |
4255 | #define DAGB2_WRCLI0__URG_HIGH__SHIFT 0x4 |
4256 | #define DAGB2_WRCLI0__URG_LOW__SHIFT 0x8 |
4257 | #define DAGB2_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc |
4258 | #define DAGB2_WRCLI0__MAX_BW__SHIFT 0xd |
4259 | #define DAGB2_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 |
4260 | #define DAGB2_WRCLI0__MIN_BW__SHIFT 0x16 |
4261 | #define DAGB2_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 |
4262 | #define DAGB2_WRCLI0__MAX_OSD__SHIFT 0x1a |
4263 | #define DAGB2_WRCLI0__VIRT_CHAN_MASK 0x00000007L |
4264 | #define DAGB2_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L |
4265 | #define DAGB2_WRCLI0__URG_HIGH_MASK 0x000000F0L |
4266 | #define DAGB2_WRCLI0__URG_LOW_MASK 0x00000F00L |
4267 | #define DAGB2_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L |
4268 | #define DAGB2_WRCLI0__MAX_BW_MASK 0x001FE000L |
4269 | #define DAGB2_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L |
4270 | #define DAGB2_WRCLI0__MIN_BW_MASK 0x01C00000L |
4271 | #define DAGB2_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L |
4272 | #define DAGB2_WRCLI0__MAX_OSD_MASK 0xFC000000L |
4273 | //DAGB2_WRCLI1 |
4274 | #define DAGB2_WRCLI1__VIRT_CHAN__SHIFT 0x0 |
4275 | #define DAGB2_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 |
4276 | #define DAGB2_WRCLI1__URG_HIGH__SHIFT 0x4 |
4277 | #define DAGB2_WRCLI1__URG_LOW__SHIFT 0x8 |
4278 | #define DAGB2_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc |
4279 | #define DAGB2_WRCLI1__MAX_BW__SHIFT 0xd |
4280 | #define DAGB2_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 |
4281 | #define DAGB2_WRCLI1__MIN_BW__SHIFT 0x16 |
4282 | #define DAGB2_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 |
4283 | #define DAGB2_WRCLI1__MAX_OSD__SHIFT 0x1a |
4284 | #define DAGB2_WRCLI1__VIRT_CHAN_MASK 0x00000007L |
4285 | #define DAGB2_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L |
4286 | #define DAGB2_WRCLI1__URG_HIGH_MASK 0x000000F0L |
4287 | #define DAGB2_WRCLI1__URG_LOW_MASK 0x00000F00L |
4288 | #define DAGB2_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L |
4289 | #define DAGB2_WRCLI1__MAX_BW_MASK 0x001FE000L |
4290 | #define DAGB2_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L |
4291 | #define DAGB2_WRCLI1__MIN_BW_MASK 0x01C00000L |
4292 | #define DAGB2_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L |
4293 | #define DAGB2_WRCLI1__MAX_OSD_MASK 0xFC000000L |
4294 | //DAGB2_WRCLI2 |
4295 | #define DAGB2_WRCLI2__VIRT_CHAN__SHIFT 0x0 |
4296 | #define DAGB2_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 |
4297 | #define DAGB2_WRCLI2__URG_HIGH__SHIFT 0x4 |
4298 | #define DAGB2_WRCLI2__URG_LOW__SHIFT 0x8 |
4299 | #define DAGB2_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc |
4300 | #define DAGB2_WRCLI2__MAX_BW__SHIFT 0xd |
4301 | #define DAGB2_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 |
4302 | #define DAGB2_WRCLI2__MIN_BW__SHIFT 0x16 |
4303 | #define DAGB2_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 |
4304 | #define DAGB2_WRCLI2__MAX_OSD__SHIFT 0x1a |
4305 | #define DAGB2_WRCLI2__VIRT_CHAN_MASK 0x00000007L |
4306 | #define DAGB2_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L |
4307 | #define DAGB2_WRCLI2__URG_HIGH_MASK 0x000000F0L |
4308 | #define DAGB2_WRCLI2__URG_LOW_MASK 0x00000F00L |
4309 | #define DAGB2_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L |
4310 | #define DAGB2_WRCLI2__MAX_BW_MASK 0x001FE000L |
4311 | #define DAGB2_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L |
4312 | #define DAGB2_WRCLI2__MIN_BW_MASK 0x01C00000L |
4313 | #define DAGB2_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L |
4314 | #define DAGB2_WRCLI2__MAX_OSD_MASK 0xFC000000L |
4315 | //DAGB2_WRCLI3 |
4316 | #define DAGB2_WRCLI3__VIRT_CHAN__SHIFT 0x0 |
4317 | #define DAGB2_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 |
4318 | #define DAGB2_WRCLI3__URG_HIGH__SHIFT 0x4 |
4319 | #define DAGB2_WRCLI3__URG_LOW__SHIFT 0x8 |
4320 | #define DAGB2_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc |
4321 | #define DAGB2_WRCLI3__MAX_BW__SHIFT 0xd |
4322 | #define DAGB2_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 |
4323 | #define DAGB2_WRCLI3__MIN_BW__SHIFT 0x16 |
4324 | #define DAGB2_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 |
4325 | #define DAGB2_WRCLI3__MAX_OSD__SHIFT 0x1a |
4326 | #define DAGB2_WRCLI3__VIRT_CHAN_MASK 0x00000007L |
4327 | #define DAGB2_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L |
4328 | #define DAGB2_WRCLI3__URG_HIGH_MASK 0x000000F0L |
4329 | #define DAGB2_WRCLI3__URG_LOW_MASK 0x00000F00L |
4330 | #define DAGB2_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L |
4331 | #define DAGB2_WRCLI3__MAX_BW_MASK 0x001FE000L |
4332 | #define DAGB2_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L |
4333 | #define DAGB2_WRCLI3__MIN_BW_MASK 0x01C00000L |
4334 | #define DAGB2_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L |
4335 | #define DAGB2_WRCLI3__MAX_OSD_MASK 0xFC000000L |
4336 | //DAGB2_WRCLI4 |
4337 | #define DAGB2_WRCLI4__VIRT_CHAN__SHIFT 0x0 |
4338 | #define DAGB2_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 |
4339 | #define DAGB2_WRCLI4__URG_HIGH__SHIFT 0x4 |
4340 | #define DAGB2_WRCLI4__URG_LOW__SHIFT 0x8 |
4341 | #define DAGB2_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc |
4342 | #define DAGB2_WRCLI4__MAX_BW__SHIFT 0xd |
4343 | #define DAGB2_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 |
4344 | #define DAGB2_WRCLI4__MIN_BW__SHIFT 0x16 |
4345 | #define DAGB2_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 |
4346 | #define DAGB2_WRCLI4__MAX_OSD__SHIFT 0x1a |
4347 | #define DAGB2_WRCLI4__VIRT_CHAN_MASK 0x00000007L |
4348 | #define DAGB2_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L |
4349 | #define DAGB2_WRCLI4__URG_HIGH_MASK 0x000000F0L |
4350 | #define DAGB2_WRCLI4__URG_LOW_MASK 0x00000F00L |
4351 | #define DAGB2_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L |
4352 | #define DAGB2_WRCLI4__MAX_BW_MASK 0x001FE000L |
4353 | #define DAGB2_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L |
4354 | #define DAGB2_WRCLI4__MIN_BW_MASK 0x01C00000L |
4355 | #define DAGB2_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L |
4356 | #define DAGB2_WRCLI4__MAX_OSD_MASK 0xFC000000L |
4357 | //DAGB2_WRCLI5 |
4358 | #define DAGB2_WRCLI5__VIRT_CHAN__SHIFT 0x0 |
4359 | #define DAGB2_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 |
4360 | #define DAGB2_WRCLI5__URG_HIGH__SHIFT 0x4 |
4361 | #define DAGB2_WRCLI5__URG_LOW__SHIFT 0x8 |
4362 | #define DAGB2_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc |
4363 | #define DAGB2_WRCLI5__MAX_BW__SHIFT 0xd |
4364 | #define DAGB2_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 |
4365 | #define DAGB2_WRCLI5__MIN_BW__SHIFT 0x16 |
4366 | #define DAGB2_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 |
4367 | #define DAGB2_WRCLI5__MAX_OSD__SHIFT 0x1a |
4368 | #define DAGB2_WRCLI5__VIRT_CHAN_MASK 0x00000007L |
4369 | #define DAGB2_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L |
4370 | #define DAGB2_WRCLI5__URG_HIGH_MASK 0x000000F0L |
4371 | #define DAGB2_WRCLI5__URG_LOW_MASK 0x00000F00L |
4372 | #define DAGB2_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L |
4373 | #define DAGB2_WRCLI5__MAX_BW_MASK 0x001FE000L |
4374 | #define DAGB2_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L |
4375 | #define DAGB2_WRCLI5__MIN_BW_MASK 0x01C00000L |
4376 | #define DAGB2_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L |
4377 | #define DAGB2_WRCLI5__MAX_OSD_MASK 0xFC000000L |
4378 | //DAGB2_WRCLI6 |
4379 | #define DAGB2_WRCLI6__VIRT_CHAN__SHIFT 0x0 |
4380 | #define DAGB2_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 |
4381 | #define DAGB2_WRCLI6__URG_HIGH__SHIFT 0x4 |
4382 | #define DAGB2_WRCLI6__URG_LOW__SHIFT 0x8 |
4383 | #define DAGB2_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc |
4384 | #define DAGB2_WRCLI6__MAX_BW__SHIFT 0xd |
4385 | #define DAGB2_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 |
4386 | #define DAGB2_WRCLI6__MIN_BW__SHIFT 0x16 |
4387 | #define DAGB2_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 |
4388 | #define DAGB2_WRCLI6__MAX_OSD__SHIFT 0x1a |
4389 | #define DAGB2_WRCLI6__VIRT_CHAN_MASK 0x00000007L |
4390 | #define DAGB2_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L |
4391 | #define DAGB2_WRCLI6__URG_HIGH_MASK 0x000000F0L |
4392 | #define DAGB2_WRCLI6__URG_LOW_MASK 0x00000F00L |
4393 | #define DAGB2_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L |
4394 | #define DAGB2_WRCLI6__MAX_BW_MASK 0x001FE000L |
4395 | #define DAGB2_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L |
4396 | #define DAGB2_WRCLI6__MIN_BW_MASK 0x01C00000L |
4397 | #define DAGB2_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L |
4398 | #define DAGB2_WRCLI6__MAX_OSD_MASK 0xFC000000L |
4399 | //DAGB2_WRCLI7 |
4400 | #define DAGB2_WRCLI7__VIRT_CHAN__SHIFT 0x0 |
4401 | #define DAGB2_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 |
4402 | #define DAGB2_WRCLI7__URG_HIGH__SHIFT 0x4 |
4403 | #define DAGB2_WRCLI7__URG_LOW__SHIFT 0x8 |
4404 | #define DAGB2_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc |
4405 | #define DAGB2_WRCLI7__MAX_BW__SHIFT 0xd |
4406 | #define DAGB2_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 |
4407 | #define DAGB2_WRCLI7__MIN_BW__SHIFT 0x16 |
4408 | #define DAGB2_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 |
4409 | #define DAGB2_WRCLI7__MAX_OSD__SHIFT 0x1a |
4410 | #define DAGB2_WRCLI7__VIRT_CHAN_MASK 0x00000007L |
4411 | #define DAGB2_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L |
4412 | #define DAGB2_WRCLI7__URG_HIGH_MASK 0x000000F0L |
4413 | #define DAGB2_WRCLI7__URG_LOW_MASK 0x00000F00L |
4414 | #define DAGB2_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L |
4415 | #define DAGB2_WRCLI7__MAX_BW_MASK 0x001FE000L |
4416 | #define DAGB2_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L |
4417 | #define DAGB2_WRCLI7__MIN_BW_MASK 0x01C00000L |
4418 | #define DAGB2_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L |
4419 | #define DAGB2_WRCLI7__MAX_OSD_MASK 0xFC000000L |
4420 | //DAGB2_WRCLI8 |
4421 | #define DAGB2_WRCLI8__VIRT_CHAN__SHIFT 0x0 |
4422 | #define DAGB2_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 |
4423 | #define DAGB2_WRCLI8__URG_HIGH__SHIFT 0x4 |
4424 | #define DAGB2_WRCLI8__URG_LOW__SHIFT 0x8 |
4425 | #define DAGB2_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc |
4426 | #define DAGB2_WRCLI8__MAX_BW__SHIFT 0xd |
4427 | #define DAGB2_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 |
4428 | #define DAGB2_WRCLI8__MIN_BW__SHIFT 0x16 |
4429 | #define DAGB2_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 |
4430 | #define DAGB2_WRCLI8__MAX_OSD__SHIFT 0x1a |
4431 | #define DAGB2_WRCLI8__VIRT_CHAN_MASK 0x00000007L |
4432 | #define DAGB2_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L |
4433 | #define DAGB2_WRCLI8__URG_HIGH_MASK 0x000000F0L |
4434 | #define DAGB2_WRCLI8__URG_LOW_MASK 0x00000F00L |
4435 | #define DAGB2_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L |
4436 | #define DAGB2_WRCLI8__MAX_BW_MASK 0x001FE000L |
4437 | #define DAGB2_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L |
4438 | #define DAGB2_WRCLI8__MIN_BW_MASK 0x01C00000L |
4439 | #define DAGB2_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L |
4440 | #define DAGB2_WRCLI8__MAX_OSD_MASK 0xFC000000L |
4441 | //DAGB2_WRCLI9 |
4442 | #define DAGB2_WRCLI9__VIRT_CHAN__SHIFT 0x0 |
4443 | #define DAGB2_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 |
4444 | #define DAGB2_WRCLI9__URG_HIGH__SHIFT 0x4 |
4445 | #define DAGB2_WRCLI9__URG_LOW__SHIFT 0x8 |
4446 | #define DAGB2_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc |
4447 | #define DAGB2_WRCLI9__MAX_BW__SHIFT 0xd |
4448 | #define DAGB2_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 |
4449 | #define DAGB2_WRCLI9__MIN_BW__SHIFT 0x16 |
4450 | #define DAGB2_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 |
4451 | #define DAGB2_WRCLI9__MAX_OSD__SHIFT 0x1a |
4452 | #define DAGB2_WRCLI9__VIRT_CHAN_MASK 0x00000007L |
4453 | #define DAGB2_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L |
4454 | #define DAGB2_WRCLI9__URG_HIGH_MASK 0x000000F0L |
4455 | #define DAGB2_WRCLI9__URG_LOW_MASK 0x00000F00L |
4456 | #define DAGB2_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L |
4457 | #define DAGB2_WRCLI9__MAX_BW_MASK 0x001FE000L |
4458 | #define DAGB2_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L |
4459 | #define DAGB2_WRCLI9__MIN_BW_MASK 0x01C00000L |
4460 | #define DAGB2_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L |
4461 | #define DAGB2_WRCLI9__MAX_OSD_MASK 0xFC000000L |
4462 | //DAGB2_WRCLI10 |
4463 | #define DAGB2_WRCLI10__VIRT_CHAN__SHIFT 0x0 |
4464 | #define DAGB2_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 |
4465 | #define DAGB2_WRCLI10__URG_HIGH__SHIFT 0x4 |
4466 | #define DAGB2_WRCLI10__URG_LOW__SHIFT 0x8 |
4467 | #define DAGB2_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc |
4468 | #define DAGB2_WRCLI10__MAX_BW__SHIFT 0xd |
4469 | #define DAGB2_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 |
4470 | #define DAGB2_WRCLI10__MIN_BW__SHIFT 0x16 |
4471 | #define DAGB2_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 |
4472 | #define DAGB2_WRCLI10__MAX_OSD__SHIFT 0x1a |
4473 | #define DAGB2_WRCLI10__VIRT_CHAN_MASK 0x00000007L |
4474 | #define DAGB2_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L |
4475 | #define DAGB2_WRCLI10__URG_HIGH_MASK 0x000000F0L |
4476 | #define DAGB2_WRCLI10__URG_LOW_MASK 0x00000F00L |
4477 | #define DAGB2_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L |
4478 | #define DAGB2_WRCLI10__MAX_BW_MASK 0x001FE000L |
4479 | #define DAGB2_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L |
4480 | #define DAGB2_WRCLI10__MIN_BW_MASK 0x01C00000L |
4481 | #define DAGB2_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L |
4482 | #define DAGB2_WRCLI10__MAX_OSD_MASK 0xFC000000L |
4483 | //DAGB2_WRCLI11 |
4484 | #define DAGB2_WRCLI11__VIRT_CHAN__SHIFT 0x0 |
4485 | #define DAGB2_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 |
4486 | #define DAGB2_WRCLI11__URG_HIGH__SHIFT 0x4 |
4487 | #define DAGB2_WRCLI11__URG_LOW__SHIFT 0x8 |
4488 | #define DAGB2_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc |
4489 | #define DAGB2_WRCLI11__MAX_BW__SHIFT 0xd |
4490 | #define DAGB2_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 |
4491 | #define DAGB2_WRCLI11__MIN_BW__SHIFT 0x16 |
4492 | #define DAGB2_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 |
4493 | #define DAGB2_WRCLI11__MAX_OSD__SHIFT 0x1a |
4494 | #define DAGB2_WRCLI11__VIRT_CHAN_MASK 0x00000007L |
4495 | #define DAGB2_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L |
4496 | #define DAGB2_WRCLI11__URG_HIGH_MASK 0x000000F0L |
4497 | #define DAGB2_WRCLI11__URG_LOW_MASK 0x00000F00L |
4498 | #define DAGB2_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L |
4499 | #define DAGB2_WRCLI11__MAX_BW_MASK 0x001FE000L |
4500 | #define DAGB2_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L |
4501 | #define DAGB2_WRCLI11__MIN_BW_MASK 0x01C00000L |
4502 | #define DAGB2_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L |
4503 | #define DAGB2_WRCLI11__MAX_OSD_MASK 0xFC000000L |
4504 | //DAGB2_WRCLI12 |
4505 | #define DAGB2_WRCLI12__VIRT_CHAN__SHIFT 0x0 |
4506 | #define DAGB2_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 |
4507 | #define DAGB2_WRCLI12__URG_HIGH__SHIFT 0x4 |
4508 | #define DAGB2_WRCLI12__URG_LOW__SHIFT 0x8 |
4509 | #define DAGB2_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc |
4510 | #define DAGB2_WRCLI12__MAX_BW__SHIFT 0xd |
4511 | #define DAGB2_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 |
4512 | #define DAGB2_WRCLI12__MIN_BW__SHIFT 0x16 |
4513 | #define DAGB2_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 |
4514 | #define DAGB2_WRCLI12__MAX_OSD__SHIFT 0x1a |
4515 | #define DAGB2_WRCLI12__VIRT_CHAN_MASK 0x00000007L |
4516 | #define DAGB2_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L |
4517 | #define DAGB2_WRCLI12__URG_HIGH_MASK 0x000000F0L |
4518 | #define DAGB2_WRCLI12__URG_LOW_MASK 0x00000F00L |
4519 | #define DAGB2_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L |
4520 | #define DAGB2_WRCLI12__MAX_BW_MASK 0x001FE000L |
4521 | #define DAGB2_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L |
4522 | #define DAGB2_WRCLI12__MIN_BW_MASK 0x01C00000L |
4523 | #define DAGB2_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L |
4524 | #define DAGB2_WRCLI12__MAX_OSD_MASK 0xFC000000L |
4525 | //DAGB2_WRCLI13 |
4526 | #define DAGB2_WRCLI13__VIRT_CHAN__SHIFT 0x0 |
4527 | #define DAGB2_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 |
4528 | #define DAGB2_WRCLI13__URG_HIGH__SHIFT 0x4 |
4529 | #define DAGB2_WRCLI13__URG_LOW__SHIFT 0x8 |
4530 | #define DAGB2_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc |
4531 | #define DAGB2_WRCLI13__MAX_BW__SHIFT 0xd |
4532 | #define DAGB2_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 |
4533 | #define DAGB2_WRCLI13__MIN_BW__SHIFT 0x16 |
4534 | #define DAGB2_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 |
4535 | #define DAGB2_WRCLI13__MAX_OSD__SHIFT 0x1a |
4536 | #define DAGB2_WRCLI13__VIRT_CHAN_MASK 0x00000007L |
4537 | #define DAGB2_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L |
4538 | #define DAGB2_WRCLI13__URG_HIGH_MASK 0x000000F0L |
4539 | #define DAGB2_WRCLI13__URG_LOW_MASK 0x00000F00L |
4540 | #define DAGB2_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L |
4541 | #define DAGB2_WRCLI13__MAX_BW_MASK 0x001FE000L |
4542 | #define DAGB2_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L |
4543 | #define DAGB2_WRCLI13__MIN_BW_MASK 0x01C00000L |
4544 | #define DAGB2_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L |
4545 | #define DAGB2_WRCLI13__MAX_OSD_MASK 0xFC000000L |
4546 | //DAGB2_WRCLI14 |
4547 | #define DAGB2_WRCLI14__VIRT_CHAN__SHIFT 0x0 |
4548 | #define DAGB2_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 |
4549 | #define DAGB2_WRCLI14__URG_HIGH__SHIFT 0x4 |
4550 | #define DAGB2_WRCLI14__URG_LOW__SHIFT 0x8 |
4551 | #define DAGB2_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc |
4552 | #define DAGB2_WRCLI14__MAX_BW__SHIFT 0xd |
4553 | #define DAGB2_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 |
4554 | #define DAGB2_WRCLI14__MIN_BW__SHIFT 0x16 |
4555 | #define DAGB2_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 |
4556 | #define DAGB2_WRCLI14__MAX_OSD__SHIFT 0x1a |
4557 | #define DAGB2_WRCLI14__VIRT_CHAN_MASK 0x00000007L |
4558 | #define DAGB2_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L |
4559 | #define DAGB2_WRCLI14__URG_HIGH_MASK 0x000000F0L |
4560 | #define DAGB2_WRCLI14__URG_LOW_MASK 0x00000F00L |
4561 | #define DAGB2_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L |
4562 | #define DAGB2_WRCLI14__MAX_BW_MASK 0x001FE000L |
4563 | #define DAGB2_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L |
4564 | #define DAGB2_WRCLI14__MIN_BW_MASK 0x01C00000L |
4565 | #define DAGB2_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L |
4566 | #define DAGB2_WRCLI14__MAX_OSD_MASK 0xFC000000L |
4567 | //DAGB2_WRCLI15 |
4568 | #define DAGB2_WRCLI15__VIRT_CHAN__SHIFT 0x0 |
4569 | #define DAGB2_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 |
4570 | #define DAGB2_WRCLI15__URG_HIGH__SHIFT 0x4 |
4571 | #define DAGB2_WRCLI15__URG_LOW__SHIFT 0x8 |
4572 | #define DAGB2_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc |
4573 | #define DAGB2_WRCLI15__MAX_BW__SHIFT 0xd |
4574 | #define DAGB2_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 |
4575 | #define DAGB2_WRCLI15__MIN_BW__SHIFT 0x16 |
4576 | #define DAGB2_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 |
4577 | #define DAGB2_WRCLI15__MAX_OSD__SHIFT 0x1a |
4578 | #define DAGB2_WRCLI15__VIRT_CHAN_MASK 0x00000007L |
4579 | #define DAGB2_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L |
4580 | #define DAGB2_WRCLI15__URG_HIGH_MASK 0x000000F0L |
4581 | #define DAGB2_WRCLI15__URG_LOW_MASK 0x00000F00L |
4582 | #define DAGB2_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L |
4583 | #define DAGB2_WRCLI15__MAX_BW_MASK 0x001FE000L |
4584 | #define DAGB2_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L |
4585 | #define DAGB2_WRCLI15__MIN_BW_MASK 0x01C00000L |
4586 | #define DAGB2_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L |
4587 | #define DAGB2_WRCLI15__MAX_OSD_MASK 0xFC000000L |
4588 | //DAGB2_WR_CNTL |
4589 | #define DAGB2_WR_CNTL__SCLK_FREQ__SHIFT 0x0 |
4590 | #define DAGB2_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 |
4591 | #define DAGB2_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa |
4592 | #define DAGB2_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 |
4593 | #define DAGB2_WR_CNTL__IO_LEVEL__SHIFT 0x11 |
4594 | #define DAGB2_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 |
4595 | #define DAGB2_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 |
4596 | #define DAGB2_WR_CNTL__FIX_JUMP__SHIFT 0x1a |
4597 | #define DAGB2_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL |
4598 | #define DAGB2_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L |
4599 | #define DAGB2_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L |
4600 | #define DAGB2_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L |
4601 | #define DAGB2_WR_CNTL__IO_LEVEL_MASK 0x000E0000L |
4602 | #define DAGB2_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L |
4603 | #define DAGB2_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L |
4604 | #define DAGB2_WR_CNTL__FIX_JUMP_MASK 0x04000000L |
4605 | //DAGB2_WR_GMI_CNTL |
4606 | #define DAGB2_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 |
4607 | #define DAGB2_WR_GMI_CNTL__LEVEL__SHIFT 0x6 |
4608 | #define DAGB2_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 |
4609 | #define DAGB2_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd |
4610 | #define DAGB2_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL |
4611 | #define DAGB2_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L |
4612 | #define DAGB2_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L |
4613 | #define DAGB2_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L |
4614 | //DAGB2_WR_ADDR_DAGB |
4615 | #define DAGB2_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 |
4616 | #define DAGB2_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 |
4617 | #define DAGB2_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 |
4618 | #define DAGB2_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 |
4619 | #define DAGB2_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd |
4620 | #define DAGB2_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L |
4621 | #define DAGB2_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L |
4622 | #define DAGB2_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L |
4623 | #define DAGB2_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L |
4624 | #define DAGB2_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L |
4625 | //DAGB2_WR_OUTPUT_DAGB_MAX_BURST |
4626 | #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 |
4627 | #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 |
4628 | #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 |
4629 | #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc |
4630 | #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 |
4631 | #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 |
4632 | #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 |
4633 | #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c |
4634 | #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL |
4635 | #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L |
4636 | #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L |
4637 | #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L |
4638 | #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L |
4639 | #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L |
4640 | #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L |
4641 | #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L |
4642 | //DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER |
4643 | #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 |
4644 | #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 |
4645 | #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 |
4646 | #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc |
4647 | #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 |
4648 | #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 |
4649 | #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 |
4650 | #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c |
4651 | #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL |
4652 | #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L |
4653 | #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L |
4654 | #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L |
4655 | #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L |
4656 | #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L |
4657 | #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L |
4658 | #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L |
4659 | //DAGB2_WR_CGTT_CLK_CTRL |
4660 | #define DAGB2_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
4661 | #define DAGB2_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
4662 | #define DAGB2_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
4663 | #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
4664 | #define DAGB2_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
4665 | #define DAGB2_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
4666 | #define DAGB2_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
4667 | #define DAGB2_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
4668 | #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
4669 | #define DAGB2_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
4670 | //DAGB2_L1TLB_WR_CGTT_CLK_CTRL |
4671 | #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
4672 | #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
4673 | #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
4674 | #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
4675 | #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
4676 | #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
4677 | #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
4678 | #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
4679 | #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
4680 | #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
4681 | //DAGB2_ATCVM_WR_CGTT_CLK_CTRL |
4682 | #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
4683 | #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
4684 | #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
4685 | #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
4686 | #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
4687 | #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
4688 | #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
4689 | #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
4690 | #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
4691 | #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
4692 | //DAGB2_WR_ADDR_DAGB_MAX_BURST0 |
4693 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 |
4694 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 |
4695 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 |
4696 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc |
4697 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 |
4698 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 |
4699 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 |
4700 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c |
4701 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL |
4702 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L |
4703 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L |
4704 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L |
4705 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L |
4706 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L |
4707 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L |
4708 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L |
4709 | //DAGB2_WR_ADDR_DAGB_LAZY_TIMER0 |
4710 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 |
4711 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 |
4712 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 |
4713 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc |
4714 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 |
4715 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 |
4716 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 |
4717 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c |
4718 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL |
4719 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L |
4720 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L |
4721 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L |
4722 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L |
4723 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L |
4724 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L |
4725 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L |
4726 | //DAGB2_WR_ADDR_DAGB_MAX_BURST1 |
4727 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 |
4728 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 |
4729 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 |
4730 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc |
4731 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 |
4732 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 |
4733 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 |
4734 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c |
4735 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL |
4736 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L |
4737 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L |
4738 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L |
4739 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L |
4740 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L |
4741 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L |
4742 | #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L |
4743 | //DAGB2_WR_ADDR_DAGB_LAZY_TIMER1 |
4744 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 |
4745 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 |
4746 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 |
4747 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc |
4748 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 |
4749 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 |
4750 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 |
4751 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c |
4752 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL |
4753 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L |
4754 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L |
4755 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L |
4756 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L |
4757 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L |
4758 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L |
4759 | #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L |
4760 | //DAGB2_WR_DATA_DAGB |
4761 | #define DAGB2_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 |
4762 | #define DAGB2_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 |
4763 | #define DAGB2_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 |
4764 | #define DAGB2_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 |
4765 | #define DAGB2_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L |
4766 | #define DAGB2_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L |
4767 | #define DAGB2_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L |
4768 | #define DAGB2_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L |
4769 | //DAGB2_WR_DATA_DAGB_MAX_BURST0 |
4770 | #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 |
4771 | #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 |
4772 | #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 |
4773 | #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc |
4774 | #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 |
4775 | #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 |
4776 | #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 |
4777 | #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c |
4778 | #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL |
4779 | #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L |
4780 | #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L |
4781 | #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L |
4782 | #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L |
4783 | #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L |
4784 | #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L |
4785 | #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L |
4786 | //DAGB2_WR_DATA_DAGB_LAZY_TIMER0 |
4787 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 |
4788 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 |
4789 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 |
4790 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc |
4791 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 |
4792 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 |
4793 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 |
4794 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c |
4795 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL |
4796 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L |
4797 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L |
4798 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L |
4799 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L |
4800 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L |
4801 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L |
4802 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L |
4803 | //DAGB2_WR_DATA_DAGB_MAX_BURST1 |
4804 | #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 |
4805 | #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 |
4806 | #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 |
4807 | #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc |
4808 | #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 |
4809 | #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 |
4810 | #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 |
4811 | #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c |
4812 | #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL |
4813 | #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L |
4814 | #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L |
4815 | #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L |
4816 | #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L |
4817 | #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L |
4818 | #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L |
4819 | #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L |
4820 | //DAGB2_WR_DATA_DAGB_LAZY_TIMER1 |
4821 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 |
4822 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 |
4823 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 |
4824 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc |
4825 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 |
4826 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 |
4827 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 |
4828 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c |
4829 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL |
4830 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L |
4831 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L |
4832 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L |
4833 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L |
4834 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L |
4835 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L |
4836 | #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L |
4837 | //DAGB2_WR_VC0_CNTL |
4838 | #define DAGB2_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 |
4839 | #define DAGB2_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 |
4840 | #define DAGB2_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
4841 | #define DAGB2_WR_VC0_CNTL__MAX_BW__SHIFT 0xc |
4842 | #define DAGB2_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
4843 | #define DAGB2_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 |
4844 | #define DAGB2_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
4845 | #define DAGB2_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 |
4846 | #define DAGB2_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL |
4847 | #define DAGB2_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L |
4848 | #define DAGB2_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
4849 | #define DAGB2_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L |
4850 | #define DAGB2_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
4851 | #define DAGB2_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L |
4852 | #define DAGB2_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
4853 | #define DAGB2_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L |
4854 | //DAGB2_WR_VC1_CNTL |
4855 | #define DAGB2_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 |
4856 | #define DAGB2_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 |
4857 | #define DAGB2_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
4858 | #define DAGB2_WR_VC1_CNTL__MAX_BW__SHIFT 0xc |
4859 | #define DAGB2_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
4860 | #define DAGB2_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 |
4861 | #define DAGB2_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
4862 | #define DAGB2_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 |
4863 | #define DAGB2_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL |
4864 | #define DAGB2_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L |
4865 | #define DAGB2_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
4866 | #define DAGB2_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L |
4867 | #define DAGB2_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
4868 | #define DAGB2_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L |
4869 | #define DAGB2_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
4870 | #define DAGB2_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L |
4871 | //DAGB2_WR_VC2_CNTL |
4872 | #define DAGB2_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 |
4873 | #define DAGB2_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 |
4874 | #define DAGB2_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
4875 | #define DAGB2_WR_VC2_CNTL__MAX_BW__SHIFT 0xc |
4876 | #define DAGB2_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
4877 | #define DAGB2_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 |
4878 | #define DAGB2_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
4879 | #define DAGB2_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 |
4880 | #define DAGB2_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL |
4881 | #define DAGB2_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L |
4882 | #define DAGB2_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
4883 | #define DAGB2_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L |
4884 | #define DAGB2_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
4885 | #define DAGB2_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L |
4886 | #define DAGB2_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
4887 | #define DAGB2_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L |
4888 | //DAGB2_WR_VC3_CNTL |
4889 | #define DAGB2_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 |
4890 | #define DAGB2_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 |
4891 | #define DAGB2_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
4892 | #define DAGB2_WR_VC3_CNTL__MAX_BW__SHIFT 0xc |
4893 | #define DAGB2_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
4894 | #define DAGB2_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 |
4895 | #define DAGB2_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
4896 | #define DAGB2_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 |
4897 | #define DAGB2_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL |
4898 | #define DAGB2_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L |
4899 | #define DAGB2_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
4900 | #define DAGB2_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L |
4901 | #define DAGB2_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
4902 | #define DAGB2_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L |
4903 | #define DAGB2_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
4904 | #define DAGB2_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L |
4905 | //DAGB2_WR_VC4_CNTL |
4906 | #define DAGB2_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 |
4907 | #define DAGB2_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 |
4908 | #define DAGB2_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
4909 | #define DAGB2_WR_VC4_CNTL__MAX_BW__SHIFT 0xc |
4910 | #define DAGB2_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
4911 | #define DAGB2_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 |
4912 | #define DAGB2_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
4913 | #define DAGB2_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 |
4914 | #define DAGB2_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL |
4915 | #define DAGB2_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L |
4916 | #define DAGB2_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
4917 | #define DAGB2_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L |
4918 | #define DAGB2_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
4919 | #define DAGB2_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L |
4920 | #define DAGB2_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
4921 | #define DAGB2_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L |
4922 | //DAGB2_WR_VC5_CNTL |
4923 | #define DAGB2_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 |
4924 | #define DAGB2_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 |
4925 | #define DAGB2_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
4926 | #define DAGB2_WR_VC5_CNTL__MAX_BW__SHIFT 0xc |
4927 | #define DAGB2_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
4928 | #define DAGB2_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 |
4929 | #define DAGB2_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
4930 | #define DAGB2_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 |
4931 | #define DAGB2_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL |
4932 | #define DAGB2_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L |
4933 | #define DAGB2_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
4934 | #define DAGB2_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L |
4935 | #define DAGB2_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
4936 | #define DAGB2_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L |
4937 | #define DAGB2_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
4938 | #define DAGB2_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L |
4939 | //DAGB2_WR_VC6_CNTL |
4940 | #define DAGB2_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 |
4941 | #define DAGB2_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 |
4942 | #define DAGB2_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
4943 | #define DAGB2_WR_VC6_CNTL__MAX_BW__SHIFT 0xc |
4944 | #define DAGB2_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
4945 | #define DAGB2_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 |
4946 | #define DAGB2_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
4947 | #define DAGB2_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 |
4948 | #define DAGB2_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL |
4949 | #define DAGB2_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L |
4950 | #define DAGB2_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
4951 | #define DAGB2_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L |
4952 | #define DAGB2_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
4953 | #define DAGB2_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L |
4954 | #define DAGB2_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
4955 | #define DAGB2_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L |
4956 | //DAGB2_WR_VC7_CNTL |
4957 | #define DAGB2_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 |
4958 | #define DAGB2_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 |
4959 | #define DAGB2_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
4960 | #define DAGB2_WR_VC7_CNTL__MAX_BW__SHIFT 0xc |
4961 | #define DAGB2_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
4962 | #define DAGB2_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 |
4963 | #define DAGB2_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
4964 | #define DAGB2_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 |
4965 | #define DAGB2_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL |
4966 | #define DAGB2_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L |
4967 | #define DAGB2_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
4968 | #define DAGB2_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L |
4969 | #define DAGB2_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
4970 | #define DAGB2_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L |
4971 | #define DAGB2_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
4972 | #define DAGB2_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L |
4973 | //DAGB2_WR_CNTL_MISC |
4974 | #define DAGB2_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 |
4975 | #define DAGB2_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 |
4976 | #define DAGB2_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd |
4977 | #define DAGB2_WR_CNTL_MISC__STOR_CC_NEW_MODE__SHIFT 0x13 |
4978 | #define DAGB2_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 |
4979 | #define DAGB2_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 |
4980 | #define DAGB2_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a |
4981 | #define DAGB2_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL |
4982 | #define DAGB2_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L |
4983 | #define DAGB2_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L |
4984 | #define DAGB2_WR_CNTL_MISC__STOR_CC_NEW_MODE_MASK 0x00080000L |
4985 | #define DAGB2_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L |
4986 | #define DAGB2_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L |
4987 | #define DAGB2_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L |
4988 | //DAGB2_WR_TLB_CREDIT |
4989 | #define DAGB2_WR_TLB_CREDIT__TLB0__SHIFT 0x0 |
4990 | #define DAGB2_WR_TLB_CREDIT__TLB1__SHIFT 0x5 |
4991 | #define DAGB2_WR_TLB_CREDIT__TLB2__SHIFT 0xa |
4992 | #define DAGB2_WR_TLB_CREDIT__TLB3__SHIFT 0xf |
4993 | #define DAGB2_WR_TLB_CREDIT__TLB4__SHIFT 0x14 |
4994 | #define DAGB2_WR_TLB_CREDIT__TLB5__SHIFT 0x19 |
4995 | #define DAGB2_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL |
4996 | #define DAGB2_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L |
4997 | #define DAGB2_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L |
4998 | #define DAGB2_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L |
4999 | #define DAGB2_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L |
5000 | #define DAGB2_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L |
5001 | //DAGB2_WR_DATA_CREDIT |
5002 | #define DAGB2_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 |
5003 | #define DAGB2_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 |
5004 | #define DAGB2_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 |
5005 | #define DAGB2_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 |
5006 | #define DAGB2_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL |
5007 | #define DAGB2_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L |
5008 | #define DAGB2_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L |
5009 | #define DAGB2_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L |
5010 | //DAGB2_WR_MISC_CREDIT |
5011 | #define DAGB2_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 |
5012 | #define DAGB2_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 |
5013 | #define DAGB2_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 |
5014 | #define DAGB2_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 |
5015 | #define DAGB2_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL |
5016 | #define DAGB2_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L |
5017 | #define DAGB2_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L |
5018 | #define DAGB2_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L |
5019 | //DAGB2_WR_OSD_CREDIT_CNTL1 |
5020 | #define DAGB2_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 |
5021 | #define DAGB2_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x4 |
5022 | #define DAGB2_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0x8 |
5023 | #define DAGB2_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xc |
5024 | #define DAGB2_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT 0x10 |
5025 | #define DAGB2_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT 0x14 |
5026 | #define DAGB2_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x18 |
5027 | #define DAGB2_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000000FL |
5028 | #define DAGB2_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000000F0L |
5029 | #define DAGB2_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00000F00L |
5030 | #define DAGB2_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK 0x0000F000L |
5031 | #define DAGB2_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK 0x000F0000L |
5032 | #define DAGB2_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK 0x00F00000L |
5033 | #define DAGB2_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK 0x3F000000L |
5034 | //DAGB2_WR_OSD_CREDIT_CNTL2 |
5035 | #define DAGB2_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT 0x0 |
5036 | #define DAGB2_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT 0x4 |
5037 | #define DAGB2_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK 0x0000000FL |
5038 | #define DAGB2_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK 0x00000010L |
5039 | //DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1 |
5040 | #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 |
5041 | #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 |
5042 | #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa |
5043 | #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf |
5044 | #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 |
5045 | #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19 |
5046 | #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a |
5047 | #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b |
5048 | #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT 0x1c |
5049 | #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT 0x1d |
5050 | #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL |
5051 | #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L |
5052 | #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L |
5053 | #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L |
5054 | #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L |
5055 | #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L |
5056 | #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L |
5057 | #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L |
5058 | #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK 0x10000000L |
5059 | #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK 0x20000000L |
5060 | //DAGB2_WRCLI_GPU_SNOOP_OVERRIDE |
5061 | #define DAGB2_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 |
5062 | #define DAGB2_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0x0000FFFFL |
5063 | //DAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE |
5064 | #define DAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 |
5065 | #define DAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0x0000FFFFL |
5066 | //DAGB2_WRCLI_ASK_PENDING |
5067 | #define DAGB2_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 |
5068 | #define DAGB2_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL |
5069 | //DAGB2_WRCLI_GO_PENDING |
5070 | #define DAGB2_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 |
5071 | #define DAGB2_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL |
5072 | //DAGB2_WRCLI_GBLSEND_PENDING |
5073 | #define DAGB2_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 |
5074 | #define DAGB2_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL |
5075 | //DAGB2_WRCLI_TLB_PENDING |
5076 | #define DAGB2_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 |
5077 | #define DAGB2_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL |
5078 | //DAGB2_WRCLI_OARB_PENDING |
5079 | #define DAGB2_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 |
5080 | #define DAGB2_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL |
5081 | //DAGB2_WRCLI_OSD_PENDING |
5082 | #define DAGB2_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 |
5083 | #define DAGB2_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL |
5084 | //DAGB2_WRCLI_DBUS_ASK_PENDING |
5085 | #define DAGB2_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 |
5086 | #define DAGB2_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL |
5087 | //DAGB2_WRCLI_DBUS_GO_PENDING |
5088 | #define DAGB2_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 |
5089 | #define DAGB2_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL |
5090 | //DAGB2_DAGB_DLY |
5091 | #define DAGB2_DAGB_DLY__DLY__SHIFT 0x0 |
5092 | #define DAGB2_DAGB_DLY__CLI__SHIFT 0x8 |
5093 | #define DAGB2_DAGB_DLY__POS__SHIFT 0x10 |
5094 | #define DAGB2_DAGB_DLY__DLY_MASK 0x000000FFL |
5095 | #define DAGB2_DAGB_DLY__CLI_MASK 0x0000FF00L |
5096 | #define DAGB2_DAGB_DLY__POS_MASK 0x000F0000L |
5097 | //DAGB2_CNTL_MISC |
5098 | #define DAGB2_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 |
5099 | #define DAGB2_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 |
5100 | #define DAGB2_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 |
5101 | #define DAGB2_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 |
5102 | #define DAGB2_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc |
5103 | #define DAGB2_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf |
5104 | #define DAGB2_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 |
5105 | #define DAGB2_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 |
5106 | #define DAGB2_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 |
5107 | #define DAGB2_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e |
5108 | #define DAGB2_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L |
5109 | #define DAGB2_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L |
5110 | #define DAGB2_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L |
5111 | #define DAGB2_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L |
5112 | #define DAGB2_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L |
5113 | #define DAGB2_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L |
5114 | #define DAGB2_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L |
5115 | #define DAGB2_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L |
5116 | #define DAGB2_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L |
5117 | #define DAGB2_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L |
5118 | //DAGB2_CNTL_MISC2 |
5119 | #define DAGB2_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 |
5120 | #define DAGB2_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 |
5121 | #define DAGB2_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 |
5122 | #define DAGB2_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 |
5123 | #define DAGB2_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 |
5124 | #define DAGB2_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 |
5125 | #define DAGB2_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 |
5126 | #define DAGB2_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 |
5127 | #define DAGB2_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 |
5128 | #define DAGB2_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 |
5129 | #define DAGB2_CNTL_MISC2__SWAP_CTL__SHIFT 0xa |
5130 | #define DAGB2_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb |
5131 | #define DAGB2_CNTL_MISC2__HDP_CID__SHIFT 0xc |
5132 | #define DAGB2_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x10 |
5133 | #define DAGB2_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L |
5134 | #define DAGB2_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L |
5135 | #define DAGB2_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L |
5136 | #define DAGB2_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L |
5137 | #define DAGB2_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L |
5138 | #define DAGB2_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L |
5139 | #define DAGB2_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L |
5140 | #define DAGB2_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L |
5141 | #define DAGB2_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L |
5142 | #define DAGB2_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L |
5143 | #define DAGB2_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L |
5144 | #define DAGB2_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L |
5145 | #define DAGB2_CNTL_MISC2__HDP_CID_MASK 0x0000F000L |
5146 | #define DAGB2_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x003F0000L |
5147 | //DAGB2_FATAL_ERROR_CNTL |
5148 | #define DAGB2_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0 |
5149 | #define DAGB2_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL |
5150 | //DAGB2_FATAL_ERROR_CLEAR |
5151 | #define DAGB2_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0 |
5152 | #define DAGB2_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L |
5153 | //DAGB2_FATAL_ERROR_STATUS0 |
5154 | #define DAGB2_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0 |
5155 | #define DAGB2_FATAL_ERROR_STATUS0__CID__SHIFT 0x1 |
5156 | #define DAGB2_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6 |
5157 | #define DAGB2_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L |
5158 | #define DAGB2_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL |
5159 | #define DAGB2_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L |
5160 | //DAGB2_FATAL_ERROR_STATUS1 |
5161 | #define DAGB2_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0 |
5162 | #define DAGB2_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL |
5163 | //DAGB2_FATAL_ERROR_STATUS2 |
5164 | #define DAGB2_FATAL_ERROR_STATUS2__TAG__SHIFT 0x0 |
5165 | #define DAGB2_FATAL_ERROR_STATUS2__VFID__SHIFT 0x10 |
5166 | #define DAGB2_FATAL_ERROR_STATUS2__VF__SHIFT 0x14 |
5167 | #define DAGB2_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x15 |
5168 | #define DAGB2_FATAL_ERROR_STATUS2__IO__SHIFT 0x16 |
5169 | #define DAGB2_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x17 |
5170 | #define DAGB2_FATAL_ERROR_STATUS2__DBGMSK__SHIFT 0x18 |
5171 | #define DAGB2_FATAL_ERROR_STATUS2__FED__SHIFT 0x19 |
5172 | #define DAGB2_FATAL_ERROR_STATUS2__TAG_MASK 0x0000FFFFL |
5173 | #define DAGB2_FATAL_ERROR_STATUS2__VFID_MASK 0x000F0000L |
5174 | #define DAGB2_FATAL_ERROR_STATUS2__VF_MASK 0x00100000L |
5175 | #define DAGB2_FATAL_ERROR_STATUS2__SPACE_MASK 0x00200000L |
5176 | #define DAGB2_FATAL_ERROR_STATUS2__IO_MASK 0x00400000L |
5177 | #define DAGB2_FATAL_ERROR_STATUS2__SIZE_MASK 0x00800000L |
5178 | #define DAGB2_FATAL_ERROR_STATUS2__DBGMSK_MASK 0x01000000L |
5179 | #define DAGB2_FATAL_ERROR_STATUS2__FED_MASK 0x02000000L |
5180 | //DAGB2_FATAL_ERROR_STATUS3 |
5181 | #define DAGB2_FATAL_ERROR_STATUS3__NOALLOC__SHIFT 0x0 |
5182 | #define DAGB2_FATAL_ERROR_STATUS3__UNITID__SHIFT 0x1 |
5183 | #define DAGB2_FATAL_ERROR_STATUS3__OP__SHIFT 0x7 |
5184 | #define DAGB2_FATAL_ERROR_STATUS3__SECLEVEL__SHIFT 0xe |
5185 | #define DAGB2_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x11 |
5186 | #define DAGB2_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x12 |
5187 | #define DAGB2_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x13 |
5188 | #define DAGB2_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x14 |
5189 | #define DAGB2_FATAL_ERROR_STATUS3__NACK__SHIFT 0x15 |
5190 | #define DAGB2_FATAL_ERROR_STATUS3__RO__SHIFT 0x17 |
5191 | #define DAGB2_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x18 |
5192 | #define DAGB2_FATAL_ERROR_STATUS3__EOP__SHIFT 0x19 |
5193 | #define DAGB2_FATAL_ERROR_STATUS3__NOALLOC_MASK 0x00000001L |
5194 | #define DAGB2_FATAL_ERROR_STATUS3__UNITID_MASK 0x0000007EL |
5195 | #define DAGB2_FATAL_ERROR_STATUS3__OP_MASK 0x00003F80L |
5196 | #define DAGB2_FATAL_ERROR_STATUS3__SECLEVEL_MASK 0x0001C000L |
5197 | #define DAGB2_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00020000L |
5198 | #define DAGB2_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00040000L |
5199 | #define DAGB2_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00080000L |
5200 | #define DAGB2_FATAL_ERROR_STATUS3__INVAL_MASK 0x00100000L |
5201 | #define DAGB2_FATAL_ERROR_STATUS3__NACK_MASK 0x00600000L |
5202 | #define DAGB2_FATAL_ERROR_STATUS3__RO_MASK 0x00800000L |
5203 | #define DAGB2_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x01000000L |
5204 | #define DAGB2_FATAL_ERROR_STATUS3__EOP_MASK 0x02000000L |
5205 | //DAGB2_FIFO_EMPTY |
5206 | #define DAGB2_FIFO_EMPTY__EMPTY__SHIFT 0x0 |
5207 | #define DAGB2_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL |
5208 | //DAGB2_FIFO_FULL |
5209 | #define DAGB2_FIFO_FULL__FULL__SHIFT 0x0 |
5210 | #define DAGB2_FIFO_FULL__FULL_MASK 0x007FFFFFL |
5211 | //DAGB2_WR_CREDITS_FULL |
5212 | #define DAGB2_WR_CREDITS_FULL__FULL__SHIFT 0x0 |
5213 | #define DAGB2_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL |
5214 | //DAGB2_RD_CREDITS_FULL |
5215 | #define DAGB2_RD_CREDITS_FULL__FULL__SHIFT 0x0 |
5216 | #define DAGB2_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL |
5217 | //DAGB2_PERFCOUNTER_LO |
5218 | #define DAGB2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
5219 | #define DAGB2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
5220 | //DAGB2_PERFCOUNTER_HI |
5221 | #define DAGB2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
5222 | #define DAGB2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
5223 | #define DAGB2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
5224 | #define DAGB2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
5225 | //DAGB2_PERFCOUNTER0_CFG |
5226 | #define DAGB2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
5227 | #define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
5228 | #define DAGB2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
5229 | #define DAGB2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
5230 | #define DAGB2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
5231 | #define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
5232 | #define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
5233 | #define DAGB2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
5234 | #define DAGB2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
5235 | #define DAGB2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
5236 | //DAGB2_PERFCOUNTER1_CFG |
5237 | #define DAGB2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
5238 | #define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
5239 | #define DAGB2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
5240 | #define DAGB2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
5241 | #define DAGB2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
5242 | #define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
5243 | #define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
5244 | #define DAGB2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
5245 | #define DAGB2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
5246 | #define DAGB2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
5247 | //DAGB2_PERFCOUNTER2_CFG |
5248 | #define DAGB2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 |
5249 | #define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 |
5250 | #define DAGB2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 |
5251 | #define DAGB2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c |
5252 | #define DAGB2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d |
5253 | #define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL |
5254 | #define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L |
5255 | #define DAGB2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L |
5256 | #define DAGB2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L |
5257 | #define DAGB2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L |
5258 | //DAGB2_PERFCOUNTER_RSLT_CNTL |
5259 | #define DAGB2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
5260 | #define DAGB2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
5261 | #define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
5262 | #define DAGB2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
5263 | #define DAGB2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
5264 | #define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
5265 | #define DAGB2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
5266 | #define DAGB2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
5267 | #define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
5268 | #define DAGB2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
5269 | #define DAGB2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
5270 | #define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
5271 | //DAGB2_L1TLB_REG_RW |
5272 | #define DAGB2_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 |
5273 | #define DAGB2_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 |
5274 | #define DAGB2_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT 0x2 |
5275 | #define DAGB2_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT 0x4 |
5276 | #define DAGB2_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT 0x5 |
5277 | #define DAGB2_L1TLB_REG_RW__RESERVE__SHIFT 0x6 |
5278 | #define DAGB2_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L |
5279 | #define DAGB2_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L |
5280 | #define DAGB2_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK 0x00000004L |
5281 | #define DAGB2_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK 0x00000010L |
5282 | #define DAGB2_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK 0x00000020L |
5283 | #define DAGB2_L1TLB_REG_RW__RESERVE_MASK 0xFFFFFFC0L |
5284 | |
5285 | |
5286 | // addressBlock: aid_mmhub_dagb_dagbdec3 |
5287 | //DAGB3_RDCLI0 |
5288 | #define DAGB3_RDCLI0__VIRT_CHAN__SHIFT 0x0 |
5289 | #define DAGB3_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 |
5290 | #define DAGB3_RDCLI0__URG_HIGH__SHIFT 0x4 |
5291 | #define DAGB3_RDCLI0__URG_LOW__SHIFT 0x8 |
5292 | #define DAGB3_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc |
5293 | #define DAGB3_RDCLI0__MAX_BW__SHIFT 0xd |
5294 | #define DAGB3_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 |
5295 | #define DAGB3_RDCLI0__MIN_BW__SHIFT 0x16 |
5296 | #define DAGB3_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 |
5297 | #define DAGB3_RDCLI0__MAX_OSD__SHIFT 0x1a |
5298 | #define DAGB3_RDCLI0__VIRT_CHAN_MASK 0x00000007L |
5299 | #define DAGB3_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L |
5300 | #define DAGB3_RDCLI0__URG_HIGH_MASK 0x000000F0L |
5301 | #define DAGB3_RDCLI0__URG_LOW_MASK 0x00000F00L |
5302 | #define DAGB3_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L |
5303 | #define DAGB3_RDCLI0__MAX_BW_MASK 0x001FE000L |
5304 | #define DAGB3_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L |
5305 | #define DAGB3_RDCLI0__MIN_BW_MASK 0x01C00000L |
5306 | #define DAGB3_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L |
5307 | #define DAGB3_RDCLI0__MAX_OSD_MASK 0xFC000000L |
5308 | //DAGB3_RDCLI1 |
5309 | #define DAGB3_RDCLI1__VIRT_CHAN__SHIFT 0x0 |
5310 | #define DAGB3_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 |
5311 | #define DAGB3_RDCLI1__URG_HIGH__SHIFT 0x4 |
5312 | #define DAGB3_RDCLI1__URG_LOW__SHIFT 0x8 |
5313 | #define DAGB3_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc |
5314 | #define DAGB3_RDCLI1__MAX_BW__SHIFT 0xd |
5315 | #define DAGB3_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 |
5316 | #define DAGB3_RDCLI1__MIN_BW__SHIFT 0x16 |
5317 | #define DAGB3_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 |
5318 | #define DAGB3_RDCLI1__MAX_OSD__SHIFT 0x1a |
5319 | #define DAGB3_RDCLI1__VIRT_CHAN_MASK 0x00000007L |
5320 | #define DAGB3_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L |
5321 | #define DAGB3_RDCLI1__URG_HIGH_MASK 0x000000F0L |
5322 | #define DAGB3_RDCLI1__URG_LOW_MASK 0x00000F00L |
5323 | #define DAGB3_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L |
5324 | #define DAGB3_RDCLI1__MAX_BW_MASK 0x001FE000L |
5325 | #define DAGB3_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L |
5326 | #define DAGB3_RDCLI1__MIN_BW_MASK 0x01C00000L |
5327 | #define DAGB3_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L |
5328 | #define DAGB3_RDCLI1__MAX_OSD_MASK 0xFC000000L |
5329 | //DAGB3_RDCLI2 |
5330 | #define DAGB3_RDCLI2__VIRT_CHAN__SHIFT 0x0 |
5331 | #define DAGB3_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 |
5332 | #define DAGB3_RDCLI2__URG_HIGH__SHIFT 0x4 |
5333 | #define DAGB3_RDCLI2__URG_LOW__SHIFT 0x8 |
5334 | #define DAGB3_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc |
5335 | #define DAGB3_RDCLI2__MAX_BW__SHIFT 0xd |
5336 | #define DAGB3_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 |
5337 | #define DAGB3_RDCLI2__MIN_BW__SHIFT 0x16 |
5338 | #define DAGB3_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 |
5339 | #define DAGB3_RDCLI2__MAX_OSD__SHIFT 0x1a |
5340 | #define DAGB3_RDCLI2__VIRT_CHAN_MASK 0x00000007L |
5341 | #define DAGB3_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L |
5342 | #define DAGB3_RDCLI2__URG_HIGH_MASK 0x000000F0L |
5343 | #define DAGB3_RDCLI2__URG_LOW_MASK 0x00000F00L |
5344 | #define DAGB3_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L |
5345 | #define DAGB3_RDCLI2__MAX_BW_MASK 0x001FE000L |
5346 | #define DAGB3_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L |
5347 | #define DAGB3_RDCLI2__MIN_BW_MASK 0x01C00000L |
5348 | #define DAGB3_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L |
5349 | #define DAGB3_RDCLI2__MAX_OSD_MASK 0xFC000000L |
5350 | //DAGB3_RDCLI3 |
5351 | #define DAGB3_RDCLI3__VIRT_CHAN__SHIFT 0x0 |
5352 | #define DAGB3_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 |
5353 | #define DAGB3_RDCLI3__URG_HIGH__SHIFT 0x4 |
5354 | #define DAGB3_RDCLI3__URG_LOW__SHIFT 0x8 |
5355 | #define DAGB3_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc |
5356 | #define DAGB3_RDCLI3__MAX_BW__SHIFT 0xd |
5357 | #define DAGB3_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 |
5358 | #define DAGB3_RDCLI3__MIN_BW__SHIFT 0x16 |
5359 | #define DAGB3_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 |
5360 | #define DAGB3_RDCLI3__MAX_OSD__SHIFT 0x1a |
5361 | #define DAGB3_RDCLI3__VIRT_CHAN_MASK 0x00000007L |
5362 | #define DAGB3_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L |
5363 | #define DAGB3_RDCLI3__URG_HIGH_MASK 0x000000F0L |
5364 | #define DAGB3_RDCLI3__URG_LOW_MASK 0x00000F00L |
5365 | #define DAGB3_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L |
5366 | #define DAGB3_RDCLI3__MAX_BW_MASK 0x001FE000L |
5367 | #define DAGB3_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L |
5368 | #define DAGB3_RDCLI3__MIN_BW_MASK 0x01C00000L |
5369 | #define DAGB3_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L |
5370 | #define DAGB3_RDCLI3__MAX_OSD_MASK 0xFC000000L |
5371 | //DAGB3_RDCLI4 |
5372 | #define DAGB3_RDCLI4__VIRT_CHAN__SHIFT 0x0 |
5373 | #define DAGB3_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 |
5374 | #define DAGB3_RDCLI4__URG_HIGH__SHIFT 0x4 |
5375 | #define DAGB3_RDCLI4__URG_LOW__SHIFT 0x8 |
5376 | #define DAGB3_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc |
5377 | #define DAGB3_RDCLI4__MAX_BW__SHIFT 0xd |
5378 | #define DAGB3_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 |
5379 | #define DAGB3_RDCLI4__MIN_BW__SHIFT 0x16 |
5380 | #define DAGB3_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 |
5381 | #define DAGB3_RDCLI4__MAX_OSD__SHIFT 0x1a |
5382 | #define DAGB3_RDCLI4__VIRT_CHAN_MASK 0x00000007L |
5383 | #define DAGB3_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L |
5384 | #define DAGB3_RDCLI4__URG_HIGH_MASK 0x000000F0L |
5385 | #define DAGB3_RDCLI4__URG_LOW_MASK 0x00000F00L |
5386 | #define DAGB3_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L |
5387 | #define DAGB3_RDCLI4__MAX_BW_MASK 0x001FE000L |
5388 | #define DAGB3_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L |
5389 | #define DAGB3_RDCLI4__MIN_BW_MASK 0x01C00000L |
5390 | #define DAGB3_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L |
5391 | #define DAGB3_RDCLI4__MAX_OSD_MASK 0xFC000000L |
5392 | //DAGB3_RDCLI5 |
5393 | #define DAGB3_RDCLI5__VIRT_CHAN__SHIFT 0x0 |
5394 | #define DAGB3_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 |
5395 | #define DAGB3_RDCLI5__URG_HIGH__SHIFT 0x4 |
5396 | #define DAGB3_RDCLI5__URG_LOW__SHIFT 0x8 |
5397 | #define DAGB3_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc |
5398 | #define DAGB3_RDCLI5__MAX_BW__SHIFT 0xd |
5399 | #define DAGB3_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 |
5400 | #define DAGB3_RDCLI5__MIN_BW__SHIFT 0x16 |
5401 | #define DAGB3_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 |
5402 | #define DAGB3_RDCLI5__MAX_OSD__SHIFT 0x1a |
5403 | #define DAGB3_RDCLI5__VIRT_CHAN_MASK 0x00000007L |
5404 | #define DAGB3_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L |
5405 | #define DAGB3_RDCLI5__URG_HIGH_MASK 0x000000F0L |
5406 | #define DAGB3_RDCLI5__URG_LOW_MASK 0x00000F00L |
5407 | #define DAGB3_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L |
5408 | #define DAGB3_RDCLI5__MAX_BW_MASK 0x001FE000L |
5409 | #define DAGB3_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L |
5410 | #define DAGB3_RDCLI5__MIN_BW_MASK 0x01C00000L |
5411 | #define DAGB3_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L |
5412 | #define DAGB3_RDCLI5__MAX_OSD_MASK 0xFC000000L |
5413 | //DAGB3_RDCLI6 |
5414 | #define DAGB3_RDCLI6__VIRT_CHAN__SHIFT 0x0 |
5415 | #define DAGB3_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 |
5416 | #define DAGB3_RDCLI6__URG_HIGH__SHIFT 0x4 |
5417 | #define DAGB3_RDCLI6__URG_LOW__SHIFT 0x8 |
5418 | #define DAGB3_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc |
5419 | #define DAGB3_RDCLI6__MAX_BW__SHIFT 0xd |
5420 | #define DAGB3_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 |
5421 | #define DAGB3_RDCLI6__MIN_BW__SHIFT 0x16 |
5422 | #define DAGB3_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 |
5423 | #define DAGB3_RDCLI6__MAX_OSD__SHIFT 0x1a |
5424 | #define DAGB3_RDCLI6__VIRT_CHAN_MASK 0x00000007L |
5425 | #define DAGB3_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L |
5426 | #define DAGB3_RDCLI6__URG_HIGH_MASK 0x000000F0L |
5427 | #define DAGB3_RDCLI6__URG_LOW_MASK 0x00000F00L |
5428 | #define DAGB3_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L |
5429 | #define DAGB3_RDCLI6__MAX_BW_MASK 0x001FE000L |
5430 | #define DAGB3_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L |
5431 | #define DAGB3_RDCLI6__MIN_BW_MASK 0x01C00000L |
5432 | #define DAGB3_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L |
5433 | #define DAGB3_RDCLI6__MAX_OSD_MASK 0xFC000000L |
5434 | //DAGB3_RDCLI7 |
5435 | #define DAGB3_RDCLI7__VIRT_CHAN__SHIFT 0x0 |
5436 | #define DAGB3_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 |
5437 | #define DAGB3_RDCLI7__URG_HIGH__SHIFT 0x4 |
5438 | #define DAGB3_RDCLI7__URG_LOW__SHIFT 0x8 |
5439 | #define DAGB3_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc |
5440 | #define DAGB3_RDCLI7__MAX_BW__SHIFT 0xd |
5441 | #define DAGB3_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 |
5442 | #define DAGB3_RDCLI7__MIN_BW__SHIFT 0x16 |
5443 | #define DAGB3_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 |
5444 | #define DAGB3_RDCLI7__MAX_OSD__SHIFT 0x1a |
5445 | #define DAGB3_RDCLI7__VIRT_CHAN_MASK 0x00000007L |
5446 | #define DAGB3_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L |
5447 | #define DAGB3_RDCLI7__URG_HIGH_MASK 0x000000F0L |
5448 | #define DAGB3_RDCLI7__URG_LOW_MASK 0x00000F00L |
5449 | #define DAGB3_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L |
5450 | #define DAGB3_RDCLI7__MAX_BW_MASK 0x001FE000L |
5451 | #define DAGB3_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L |
5452 | #define DAGB3_RDCLI7__MIN_BW_MASK 0x01C00000L |
5453 | #define DAGB3_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L |
5454 | #define DAGB3_RDCLI7__MAX_OSD_MASK 0xFC000000L |
5455 | //DAGB3_RDCLI8 |
5456 | #define DAGB3_RDCLI8__VIRT_CHAN__SHIFT 0x0 |
5457 | #define DAGB3_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 |
5458 | #define DAGB3_RDCLI8__URG_HIGH__SHIFT 0x4 |
5459 | #define DAGB3_RDCLI8__URG_LOW__SHIFT 0x8 |
5460 | #define DAGB3_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc |
5461 | #define DAGB3_RDCLI8__MAX_BW__SHIFT 0xd |
5462 | #define DAGB3_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 |
5463 | #define DAGB3_RDCLI8__MIN_BW__SHIFT 0x16 |
5464 | #define DAGB3_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 |
5465 | #define DAGB3_RDCLI8__MAX_OSD__SHIFT 0x1a |
5466 | #define DAGB3_RDCLI8__VIRT_CHAN_MASK 0x00000007L |
5467 | #define DAGB3_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L |
5468 | #define DAGB3_RDCLI8__URG_HIGH_MASK 0x000000F0L |
5469 | #define DAGB3_RDCLI8__URG_LOW_MASK 0x00000F00L |
5470 | #define DAGB3_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L |
5471 | #define DAGB3_RDCLI8__MAX_BW_MASK 0x001FE000L |
5472 | #define DAGB3_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L |
5473 | #define DAGB3_RDCLI8__MIN_BW_MASK 0x01C00000L |
5474 | #define DAGB3_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L |
5475 | #define DAGB3_RDCLI8__MAX_OSD_MASK 0xFC000000L |
5476 | //DAGB3_RDCLI9 |
5477 | #define DAGB3_RDCLI9__VIRT_CHAN__SHIFT 0x0 |
5478 | #define DAGB3_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 |
5479 | #define DAGB3_RDCLI9__URG_HIGH__SHIFT 0x4 |
5480 | #define DAGB3_RDCLI9__URG_LOW__SHIFT 0x8 |
5481 | #define DAGB3_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc |
5482 | #define DAGB3_RDCLI9__MAX_BW__SHIFT 0xd |
5483 | #define DAGB3_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 |
5484 | #define DAGB3_RDCLI9__MIN_BW__SHIFT 0x16 |
5485 | #define DAGB3_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 |
5486 | #define DAGB3_RDCLI9__MAX_OSD__SHIFT 0x1a |
5487 | #define DAGB3_RDCLI9__VIRT_CHAN_MASK 0x00000007L |
5488 | #define DAGB3_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L |
5489 | #define DAGB3_RDCLI9__URG_HIGH_MASK 0x000000F0L |
5490 | #define DAGB3_RDCLI9__URG_LOW_MASK 0x00000F00L |
5491 | #define DAGB3_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L |
5492 | #define DAGB3_RDCLI9__MAX_BW_MASK 0x001FE000L |
5493 | #define DAGB3_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L |
5494 | #define DAGB3_RDCLI9__MIN_BW_MASK 0x01C00000L |
5495 | #define DAGB3_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L |
5496 | #define DAGB3_RDCLI9__MAX_OSD_MASK 0xFC000000L |
5497 | //DAGB3_RDCLI10 |
5498 | #define DAGB3_RDCLI10__VIRT_CHAN__SHIFT 0x0 |
5499 | #define DAGB3_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 |
5500 | #define DAGB3_RDCLI10__URG_HIGH__SHIFT 0x4 |
5501 | #define DAGB3_RDCLI10__URG_LOW__SHIFT 0x8 |
5502 | #define DAGB3_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc |
5503 | #define DAGB3_RDCLI10__MAX_BW__SHIFT 0xd |
5504 | #define DAGB3_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 |
5505 | #define DAGB3_RDCLI10__MIN_BW__SHIFT 0x16 |
5506 | #define DAGB3_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 |
5507 | #define DAGB3_RDCLI10__MAX_OSD__SHIFT 0x1a |
5508 | #define DAGB3_RDCLI10__VIRT_CHAN_MASK 0x00000007L |
5509 | #define DAGB3_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L |
5510 | #define DAGB3_RDCLI10__URG_HIGH_MASK 0x000000F0L |
5511 | #define DAGB3_RDCLI10__URG_LOW_MASK 0x00000F00L |
5512 | #define DAGB3_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L |
5513 | #define DAGB3_RDCLI10__MAX_BW_MASK 0x001FE000L |
5514 | #define DAGB3_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L |
5515 | #define DAGB3_RDCLI10__MIN_BW_MASK 0x01C00000L |
5516 | #define DAGB3_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L |
5517 | #define DAGB3_RDCLI10__MAX_OSD_MASK 0xFC000000L |
5518 | //DAGB3_RDCLI11 |
5519 | #define DAGB3_RDCLI11__VIRT_CHAN__SHIFT 0x0 |
5520 | #define DAGB3_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 |
5521 | #define DAGB3_RDCLI11__URG_HIGH__SHIFT 0x4 |
5522 | #define DAGB3_RDCLI11__URG_LOW__SHIFT 0x8 |
5523 | #define DAGB3_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc |
5524 | #define DAGB3_RDCLI11__MAX_BW__SHIFT 0xd |
5525 | #define DAGB3_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 |
5526 | #define DAGB3_RDCLI11__MIN_BW__SHIFT 0x16 |
5527 | #define DAGB3_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 |
5528 | #define DAGB3_RDCLI11__MAX_OSD__SHIFT 0x1a |
5529 | #define DAGB3_RDCLI11__VIRT_CHAN_MASK 0x00000007L |
5530 | #define DAGB3_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L |
5531 | #define DAGB3_RDCLI11__URG_HIGH_MASK 0x000000F0L |
5532 | #define DAGB3_RDCLI11__URG_LOW_MASK 0x00000F00L |
5533 | #define DAGB3_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L |
5534 | #define DAGB3_RDCLI11__MAX_BW_MASK 0x001FE000L |
5535 | #define DAGB3_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L |
5536 | #define DAGB3_RDCLI11__MIN_BW_MASK 0x01C00000L |
5537 | #define DAGB3_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L |
5538 | #define DAGB3_RDCLI11__MAX_OSD_MASK 0xFC000000L |
5539 | //DAGB3_RDCLI12 |
5540 | #define DAGB3_RDCLI12__VIRT_CHAN__SHIFT 0x0 |
5541 | #define DAGB3_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 |
5542 | #define DAGB3_RDCLI12__URG_HIGH__SHIFT 0x4 |
5543 | #define DAGB3_RDCLI12__URG_LOW__SHIFT 0x8 |
5544 | #define DAGB3_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc |
5545 | #define DAGB3_RDCLI12__MAX_BW__SHIFT 0xd |
5546 | #define DAGB3_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 |
5547 | #define DAGB3_RDCLI12__MIN_BW__SHIFT 0x16 |
5548 | #define DAGB3_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 |
5549 | #define DAGB3_RDCLI12__MAX_OSD__SHIFT 0x1a |
5550 | #define DAGB3_RDCLI12__VIRT_CHAN_MASK 0x00000007L |
5551 | #define DAGB3_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L |
5552 | #define DAGB3_RDCLI12__URG_HIGH_MASK 0x000000F0L |
5553 | #define DAGB3_RDCLI12__URG_LOW_MASK 0x00000F00L |
5554 | #define DAGB3_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L |
5555 | #define DAGB3_RDCLI12__MAX_BW_MASK 0x001FE000L |
5556 | #define DAGB3_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L |
5557 | #define DAGB3_RDCLI12__MIN_BW_MASK 0x01C00000L |
5558 | #define DAGB3_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L |
5559 | #define DAGB3_RDCLI12__MAX_OSD_MASK 0xFC000000L |
5560 | //DAGB3_RDCLI13 |
5561 | #define DAGB3_RDCLI13__VIRT_CHAN__SHIFT 0x0 |
5562 | #define DAGB3_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 |
5563 | #define DAGB3_RDCLI13__URG_HIGH__SHIFT 0x4 |
5564 | #define DAGB3_RDCLI13__URG_LOW__SHIFT 0x8 |
5565 | #define DAGB3_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc |
5566 | #define DAGB3_RDCLI13__MAX_BW__SHIFT 0xd |
5567 | #define DAGB3_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 |
5568 | #define DAGB3_RDCLI13__MIN_BW__SHIFT 0x16 |
5569 | #define DAGB3_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 |
5570 | #define DAGB3_RDCLI13__MAX_OSD__SHIFT 0x1a |
5571 | #define DAGB3_RDCLI13__VIRT_CHAN_MASK 0x00000007L |
5572 | #define DAGB3_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L |
5573 | #define DAGB3_RDCLI13__URG_HIGH_MASK 0x000000F0L |
5574 | #define DAGB3_RDCLI13__URG_LOW_MASK 0x00000F00L |
5575 | #define DAGB3_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L |
5576 | #define DAGB3_RDCLI13__MAX_BW_MASK 0x001FE000L |
5577 | #define DAGB3_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L |
5578 | #define DAGB3_RDCLI13__MIN_BW_MASK 0x01C00000L |
5579 | #define DAGB3_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L |
5580 | #define DAGB3_RDCLI13__MAX_OSD_MASK 0xFC000000L |
5581 | //DAGB3_RDCLI14 |
5582 | #define DAGB3_RDCLI14__VIRT_CHAN__SHIFT 0x0 |
5583 | #define DAGB3_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 |
5584 | #define DAGB3_RDCLI14__URG_HIGH__SHIFT 0x4 |
5585 | #define DAGB3_RDCLI14__URG_LOW__SHIFT 0x8 |
5586 | #define DAGB3_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc |
5587 | #define DAGB3_RDCLI14__MAX_BW__SHIFT 0xd |
5588 | #define DAGB3_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 |
5589 | #define DAGB3_RDCLI14__MIN_BW__SHIFT 0x16 |
5590 | #define DAGB3_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 |
5591 | #define DAGB3_RDCLI14__MAX_OSD__SHIFT 0x1a |
5592 | #define DAGB3_RDCLI14__VIRT_CHAN_MASK 0x00000007L |
5593 | #define DAGB3_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L |
5594 | #define DAGB3_RDCLI14__URG_HIGH_MASK 0x000000F0L |
5595 | #define DAGB3_RDCLI14__URG_LOW_MASK 0x00000F00L |
5596 | #define DAGB3_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L |
5597 | #define DAGB3_RDCLI14__MAX_BW_MASK 0x001FE000L |
5598 | #define DAGB3_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L |
5599 | #define DAGB3_RDCLI14__MIN_BW_MASK 0x01C00000L |
5600 | #define DAGB3_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L |
5601 | #define DAGB3_RDCLI14__MAX_OSD_MASK 0xFC000000L |
5602 | //DAGB3_RDCLI15 |
5603 | #define DAGB3_RDCLI15__VIRT_CHAN__SHIFT 0x0 |
5604 | #define DAGB3_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 |
5605 | #define DAGB3_RDCLI15__URG_HIGH__SHIFT 0x4 |
5606 | #define DAGB3_RDCLI15__URG_LOW__SHIFT 0x8 |
5607 | #define DAGB3_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc |
5608 | #define DAGB3_RDCLI15__MAX_BW__SHIFT 0xd |
5609 | #define DAGB3_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 |
5610 | #define DAGB3_RDCLI15__MIN_BW__SHIFT 0x16 |
5611 | #define DAGB3_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 |
5612 | #define DAGB3_RDCLI15__MAX_OSD__SHIFT 0x1a |
5613 | #define DAGB3_RDCLI15__VIRT_CHAN_MASK 0x00000007L |
5614 | #define DAGB3_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L |
5615 | #define DAGB3_RDCLI15__URG_HIGH_MASK 0x000000F0L |
5616 | #define DAGB3_RDCLI15__URG_LOW_MASK 0x00000F00L |
5617 | #define DAGB3_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L |
5618 | #define DAGB3_RDCLI15__MAX_BW_MASK 0x001FE000L |
5619 | #define DAGB3_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L |
5620 | #define DAGB3_RDCLI15__MIN_BW_MASK 0x01C00000L |
5621 | #define DAGB3_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L |
5622 | #define DAGB3_RDCLI15__MAX_OSD_MASK 0xFC000000L |
5623 | //DAGB3_RD_CNTL |
5624 | #define DAGB3_RD_CNTL__SCLK_FREQ__SHIFT 0x0 |
5625 | #define DAGB3_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 |
5626 | #define DAGB3_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa |
5627 | #define DAGB3_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 |
5628 | #define DAGB3_RD_CNTL__IO_LEVEL__SHIFT 0x11 |
5629 | #define DAGB3_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 |
5630 | #define DAGB3_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 |
5631 | #define DAGB3_RD_CNTL__FIX_JUMP__SHIFT 0x1a |
5632 | #define DAGB3_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL |
5633 | #define DAGB3_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L |
5634 | #define DAGB3_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L |
5635 | #define DAGB3_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L |
5636 | #define DAGB3_RD_CNTL__IO_LEVEL_MASK 0x000E0000L |
5637 | #define DAGB3_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L |
5638 | #define DAGB3_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L |
5639 | #define DAGB3_RD_CNTL__FIX_JUMP_MASK 0x04000000L |
5640 | //DAGB3_RD_GMI_CNTL |
5641 | #define DAGB3_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 |
5642 | #define DAGB3_RD_GMI_CNTL__LEVEL__SHIFT 0x6 |
5643 | #define DAGB3_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 |
5644 | #define DAGB3_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd |
5645 | #define DAGB3_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL |
5646 | #define DAGB3_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L |
5647 | #define DAGB3_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L |
5648 | #define DAGB3_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L |
5649 | //DAGB3_RD_ADDR_DAGB |
5650 | #define DAGB3_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 |
5651 | #define DAGB3_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 |
5652 | #define DAGB3_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 |
5653 | #define DAGB3_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 |
5654 | #define DAGB3_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd |
5655 | #define DAGB3_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L |
5656 | #define DAGB3_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L |
5657 | #define DAGB3_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L |
5658 | #define DAGB3_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L |
5659 | #define DAGB3_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L |
5660 | //DAGB3_RD_OUTPUT_DAGB_MAX_BURST |
5661 | #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 |
5662 | #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 |
5663 | #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 |
5664 | #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc |
5665 | #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 |
5666 | #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 |
5667 | #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 |
5668 | #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c |
5669 | #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL |
5670 | #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L |
5671 | #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L |
5672 | #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L |
5673 | #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L |
5674 | #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L |
5675 | #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L |
5676 | #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L |
5677 | //DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER |
5678 | #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 |
5679 | #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 |
5680 | #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 |
5681 | #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc |
5682 | #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 |
5683 | #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 |
5684 | #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 |
5685 | #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c |
5686 | #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL |
5687 | #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L |
5688 | #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L |
5689 | #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L |
5690 | #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L |
5691 | #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L |
5692 | #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L |
5693 | #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L |
5694 | //DAGB3_RD_CGTT_CLK_CTRL |
5695 | #define DAGB3_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
5696 | #define DAGB3_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
5697 | #define DAGB3_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
5698 | #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
5699 | #define DAGB3_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
5700 | #define DAGB3_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
5701 | #define DAGB3_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
5702 | #define DAGB3_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
5703 | #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
5704 | #define DAGB3_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
5705 | //DAGB3_L1TLB_RD_CGTT_CLK_CTRL |
5706 | #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
5707 | #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
5708 | #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
5709 | #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
5710 | #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
5711 | #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
5712 | #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
5713 | #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
5714 | #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
5715 | #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
5716 | //DAGB3_ATCVM_RD_CGTT_CLK_CTRL |
5717 | #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
5718 | #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
5719 | #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
5720 | #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
5721 | #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
5722 | #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
5723 | #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
5724 | #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
5725 | #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
5726 | #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
5727 | //DAGB3_RD_ADDR_DAGB_MAX_BURST0 |
5728 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 |
5729 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 |
5730 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 |
5731 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc |
5732 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 |
5733 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 |
5734 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 |
5735 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c |
5736 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL |
5737 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L |
5738 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L |
5739 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L |
5740 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L |
5741 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L |
5742 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L |
5743 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L |
5744 | //DAGB3_RD_ADDR_DAGB_LAZY_TIMER0 |
5745 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 |
5746 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 |
5747 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 |
5748 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc |
5749 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 |
5750 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 |
5751 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 |
5752 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c |
5753 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL |
5754 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L |
5755 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L |
5756 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L |
5757 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L |
5758 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L |
5759 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L |
5760 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L |
5761 | //DAGB3_RD_ADDR_DAGB_MAX_BURST1 |
5762 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 |
5763 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 |
5764 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 |
5765 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc |
5766 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 |
5767 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 |
5768 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 |
5769 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c |
5770 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL |
5771 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L |
5772 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L |
5773 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L |
5774 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L |
5775 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L |
5776 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L |
5777 | #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L |
5778 | //DAGB3_RD_ADDR_DAGB_LAZY_TIMER1 |
5779 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 |
5780 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 |
5781 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 |
5782 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc |
5783 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 |
5784 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 |
5785 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 |
5786 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c |
5787 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL |
5788 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L |
5789 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L |
5790 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L |
5791 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L |
5792 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L |
5793 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L |
5794 | #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L |
5795 | //DAGB3_RD_VC0_CNTL |
5796 | #define DAGB3_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 |
5797 | #define DAGB3_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 |
5798 | #define DAGB3_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
5799 | #define DAGB3_RD_VC0_CNTL__MAX_BW__SHIFT 0xc |
5800 | #define DAGB3_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
5801 | #define DAGB3_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 |
5802 | #define DAGB3_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
5803 | #define DAGB3_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 |
5804 | #define DAGB3_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL |
5805 | #define DAGB3_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L |
5806 | #define DAGB3_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
5807 | #define DAGB3_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L |
5808 | #define DAGB3_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
5809 | #define DAGB3_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L |
5810 | #define DAGB3_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
5811 | #define DAGB3_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L |
5812 | //DAGB3_RD_VC1_CNTL |
5813 | #define DAGB3_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 |
5814 | #define DAGB3_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 |
5815 | #define DAGB3_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
5816 | #define DAGB3_RD_VC1_CNTL__MAX_BW__SHIFT 0xc |
5817 | #define DAGB3_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
5818 | #define DAGB3_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 |
5819 | #define DAGB3_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
5820 | #define DAGB3_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 |
5821 | #define DAGB3_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL |
5822 | #define DAGB3_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L |
5823 | #define DAGB3_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
5824 | #define DAGB3_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L |
5825 | #define DAGB3_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
5826 | #define DAGB3_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L |
5827 | #define DAGB3_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
5828 | #define DAGB3_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L |
5829 | //DAGB3_RD_VC2_CNTL |
5830 | #define DAGB3_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 |
5831 | #define DAGB3_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 |
5832 | #define DAGB3_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
5833 | #define DAGB3_RD_VC2_CNTL__MAX_BW__SHIFT 0xc |
5834 | #define DAGB3_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
5835 | #define DAGB3_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 |
5836 | #define DAGB3_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
5837 | #define DAGB3_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 |
5838 | #define DAGB3_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL |
5839 | #define DAGB3_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L |
5840 | #define DAGB3_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
5841 | #define DAGB3_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L |
5842 | #define DAGB3_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
5843 | #define DAGB3_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L |
5844 | #define DAGB3_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
5845 | #define DAGB3_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L |
5846 | //DAGB3_RD_VC3_CNTL |
5847 | #define DAGB3_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 |
5848 | #define DAGB3_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 |
5849 | #define DAGB3_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
5850 | #define DAGB3_RD_VC3_CNTL__MAX_BW__SHIFT 0xc |
5851 | #define DAGB3_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
5852 | #define DAGB3_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 |
5853 | #define DAGB3_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
5854 | #define DAGB3_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 |
5855 | #define DAGB3_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL |
5856 | #define DAGB3_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L |
5857 | #define DAGB3_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
5858 | #define DAGB3_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L |
5859 | #define DAGB3_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
5860 | #define DAGB3_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L |
5861 | #define DAGB3_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
5862 | #define DAGB3_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L |
5863 | //DAGB3_RD_VC4_CNTL |
5864 | #define DAGB3_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 |
5865 | #define DAGB3_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 |
5866 | #define DAGB3_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
5867 | #define DAGB3_RD_VC4_CNTL__MAX_BW__SHIFT 0xc |
5868 | #define DAGB3_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
5869 | #define DAGB3_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 |
5870 | #define DAGB3_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
5871 | #define DAGB3_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 |
5872 | #define DAGB3_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL |
5873 | #define DAGB3_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L |
5874 | #define DAGB3_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
5875 | #define DAGB3_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L |
5876 | #define DAGB3_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
5877 | #define DAGB3_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L |
5878 | #define DAGB3_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
5879 | #define DAGB3_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L |
5880 | //DAGB3_RD_VC5_CNTL |
5881 | #define DAGB3_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 |
5882 | #define DAGB3_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 |
5883 | #define DAGB3_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
5884 | #define DAGB3_RD_VC5_CNTL__MAX_BW__SHIFT 0xc |
5885 | #define DAGB3_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
5886 | #define DAGB3_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 |
5887 | #define DAGB3_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
5888 | #define DAGB3_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 |
5889 | #define DAGB3_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL |
5890 | #define DAGB3_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L |
5891 | #define DAGB3_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
5892 | #define DAGB3_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L |
5893 | #define DAGB3_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
5894 | #define DAGB3_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L |
5895 | #define DAGB3_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
5896 | #define DAGB3_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L |
5897 | //DAGB3_RD_VC6_CNTL |
5898 | #define DAGB3_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 |
5899 | #define DAGB3_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 |
5900 | #define DAGB3_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
5901 | #define DAGB3_RD_VC6_CNTL__MAX_BW__SHIFT 0xc |
5902 | #define DAGB3_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
5903 | #define DAGB3_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 |
5904 | #define DAGB3_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
5905 | #define DAGB3_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 |
5906 | #define DAGB3_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL |
5907 | #define DAGB3_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L |
5908 | #define DAGB3_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
5909 | #define DAGB3_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L |
5910 | #define DAGB3_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
5911 | #define DAGB3_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L |
5912 | #define DAGB3_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
5913 | #define DAGB3_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L |
5914 | //DAGB3_RD_VC7_CNTL |
5915 | #define DAGB3_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 |
5916 | #define DAGB3_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 |
5917 | #define DAGB3_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
5918 | #define DAGB3_RD_VC7_CNTL__MAX_BW__SHIFT 0xc |
5919 | #define DAGB3_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
5920 | #define DAGB3_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 |
5921 | #define DAGB3_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
5922 | #define DAGB3_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 |
5923 | #define DAGB3_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL |
5924 | #define DAGB3_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L |
5925 | #define DAGB3_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
5926 | #define DAGB3_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L |
5927 | #define DAGB3_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
5928 | #define DAGB3_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L |
5929 | #define DAGB3_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
5930 | #define DAGB3_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L |
5931 | //DAGB3_RD_CNTL_MISC |
5932 | #define DAGB3_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 |
5933 | #define DAGB3_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 |
5934 | #define DAGB3_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd |
5935 | #define DAGB3_RD_CNTL_MISC__STOR_CC_NEW_MODE__SHIFT 0x13 |
5936 | #define DAGB3_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 |
5937 | #define DAGB3_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 |
5938 | #define DAGB3_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a |
5939 | #define DAGB3_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL |
5940 | #define DAGB3_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L |
5941 | #define DAGB3_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L |
5942 | #define DAGB3_RD_CNTL_MISC__STOR_CC_NEW_MODE_MASK 0x00080000L |
5943 | #define DAGB3_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L |
5944 | #define DAGB3_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L |
5945 | #define DAGB3_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L |
5946 | //DAGB3_RD_TLB_CREDIT |
5947 | #define DAGB3_RD_TLB_CREDIT__TLB0__SHIFT 0x0 |
5948 | #define DAGB3_RD_TLB_CREDIT__TLB1__SHIFT 0x5 |
5949 | #define DAGB3_RD_TLB_CREDIT__TLB2__SHIFT 0xa |
5950 | #define DAGB3_RD_TLB_CREDIT__TLB3__SHIFT 0xf |
5951 | #define DAGB3_RD_TLB_CREDIT__TLB4__SHIFT 0x14 |
5952 | #define DAGB3_RD_TLB_CREDIT__TLB5__SHIFT 0x19 |
5953 | #define DAGB3_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL |
5954 | #define DAGB3_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L |
5955 | #define DAGB3_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L |
5956 | #define DAGB3_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L |
5957 | #define DAGB3_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L |
5958 | #define DAGB3_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L |
5959 | //DAGB3_RD_RDRET_CREDIT_CNTL |
5960 | #define DAGB3_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0 |
5961 | #define DAGB3_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x6 |
5962 | #define DAGB3_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xc |
5963 | #define DAGB3_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0x12 |
5964 | #define DAGB3_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x18 |
5965 | #define DAGB3_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e |
5966 | #define DAGB3_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f |
5967 | #define DAGB3_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000003FL |
5968 | #define DAGB3_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x00000FC0L |
5969 | #define DAGB3_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x0003F000L |
5970 | #define DAGB3_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x00FC0000L |
5971 | #define DAGB3_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x3F000000L |
5972 | #define DAGB3_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L |
5973 | #define DAGB3_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L |
5974 | //DAGB3_RD_RDRET_CREDIT_CNTL2 |
5975 | #define DAGB3_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT 0x0 |
5976 | #define DAGB3_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT 0x6 |
5977 | #define DAGB3_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0xc |
5978 | #define DAGB3_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK 0x0000003FL |
5979 | #define DAGB3_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK 0x00000FC0L |
5980 | #define DAGB3_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0007F000L |
5981 | //DAGB3_RDCLI_ASK_PENDING |
5982 | #define DAGB3_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 |
5983 | #define DAGB3_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL |
5984 | //DAGB3_RDCLI_GO_PENDING |
5985 | #define DAGB3_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 |
5986 | #define DAGB3_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL |
5987 | //DAGB3_RDCLI_GBLSEND_PENDING |
5988 | #define DAGB3_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 |
5989 | #define DAGB3_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL |
5990 | //DAGB3_RDCLI_TLB_PENDING |
5991 | #define DAGB3_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 |
5992 | #define DAGB3_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL |
5993 | //DAGB3_RDCLI_OARB_PENDING |
5994 | #define DAGB3_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 |
5995 | #define DAGB3_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL |
5996 | //DAGB3_RDCLI_OSD_PENDING |
5997 | #define DAGB3_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 |
5998 | #define DAGB3_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL |
5999 | //DAGB3_WRCLI0 |
6000 | #define DAGB3_WRCLI0__VIRT_CHAN__SHIFT 0x0 |
6001 | #define DAGB3_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 |
6002 | #define DAGB3_WRCLI0__URG_HIGH__SHIFT 0x4 |
6003 | #define DAGB3_WRCLI0__URG_LOW__SHIFT 0x8 |
6004 | #define DAGB3_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc |
6005 | #define DAGB3_WRCLI0__MAX_BW__SHIFT 0xd |
6006 | #define DAGB3_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 |
6007 | #define DAGB3_WRCLI0__MIN_BW__SHIFT 0x16 |
6008 | #define DAGB3_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 |
6009 | #define DAGB3_WRCLI0__MAX_OSD__SHIFT 0x1a |
6010 | #define DAGB3_WRCLI0__VIRT_CHAN_MASK 0x00000007L |
6011 | #define DAGB3_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L |
6012 | #define DAGB3_WRCLI0__URG_HIGH_MASK 0x000000F0L |
6013 | #define DAGB3_WRCLI0__URG_LOW_MASK 0x00000F00L |
6014 | #define DAGB3_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L |
6015 | #define DAGB3_WRCLI0__MAX_BW_MASK 0x001FE000L |
6016 | #define DAGB3_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L |
6017 | #define DAGB3_WRCLI0__MIN_BW_MASK 0x01C00000L |
6018 | #define DAGB3_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L |
6019 | #define DAGB3_WRCLI0__MAX_OSD_MASK 0xFC000000L |
6020 | //DAGB3_WRCLI1 |
6021 | #define DAGB3_WRCLI1__VIRT_CHAN__SHIFT 0x0 |
6022 | #define DAGB3_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 |
6023 | #define DAGB3_WRCLI1__URG_HIGH__SHIFT 0x4 |
6024 | #define DAGB3_WRCLI1__URG_LOW__SHIFT 0x8 |
6025 | #define DAGB3_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc |
6026 | #define DAGB3_WRCLI1__MAX_BW__SHIFT 0xd |
6027 | #define DAGB3_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 |
6028 | #define DAGB3_WRCLI1__MIN_BW__SHIFT 0x16 |
6029 | #define DAGB3_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 |
6030 | #define DAGB3_WRCLI1__MAX_OSD__SHIFT 0x1a |
6031 | #define DAGB3_WRCLI1__VIRT_CHAN_MASK 0x00000007L |
6032 | #define DAGB3_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L |
6033 | #define DAGB3_WRCLI1__URG_HIGH_MASK 0x000000F0L |
6034 | #define DAGB3_WRCLI1__URG_LOW_MASK 0x00000F00L |
6035 | #define DAGB3_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L |
6036 | #define DAGB3_WRCLI1__MAX_BW_MASK 0x001FE000L |
6037 | #define DAGB3_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L |
6038 | #define DAGB3_WRCLI1__MIN_BW_MASK 0x01C00000L |
6039 | #define DAGB3_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L |
6040 | #define DAGB3_WRCLI1__MAX_OSD_MASK 0xFC000000L |
6041 | //DAGB3_WRCLI2 |
6042 | #define DAGB3_WRCLI2__VIRT_CHAN__SHIFT 0x0 |
6043 | #define DAGB3_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 |
6044 | #define DAGB3_WRCLI2__URG_HIGH__SHIFT 0x4 |
6045 | #define DAGB3_WRCLI2__URG_LOW__SHIFT 0x8 |
6046 | #define DAGB3_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc |
6047 | #define DAGB3_WRCLI2__MAX_BW__SHIFT 0xd |
6048 | #define DAGB3_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 |
6049 | #define DAGB3_WRCLI2__MIN_BW__SHIFT 0x16 |
6050 | #define DAGB3_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 |
6051 | #define DAGB3_WRCLI2__MAX_OSD__SHIFT 0x1a |
6052 | #define DAGB3_WRCLI2__VIRT_CHAN_MASK 0x00000007L |
6053 | #define DAGB3_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L |
6054 | #define DAGB3_WRCLI2__URG_HIGH_MASK 0x000000F0L |
6055 | #define DAGB3_WRCLI2__URG_LOW_MASK 0x00000F00L |
6056 | #define DAGB3_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L |
6057 | #define DAGB3_WRCLI2__MAX_BW_MASK 0x001FE000L |
6058 | #define DAGB3_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L |
6059 | #define DAGB3_WRCLI2__MIN_BW_MASK 0x01C00000L |
6060 | #define DAGB3_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L |
6061 | #define DAGB3_WRCLI2__MAX_OSD_MASK 0xFC000000L |
6062 | //DAGB3_WRCLI3 |
6063 | #define DAGB3_WRCLI3__VIRT_CHAN__SHIFT 0x0 |
6064 | #define DAGB3_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 |
6065 | #define DAGB3_WRCLI3__URG_HIGH__SHIFT 0x4 |
6066 | #define DAGB3_WRCLI3__URG_LOW__SHIFT 0x8 |
6067 | #define DAGB3_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc |
6068 | #define DAGB3_WRCLI3__MAX_BW__SHIFT 0xd |
6069 | #define DAGB3_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 |
6070 | #define DAGB3_WRCLI3__MIN_BW__SHIFT 0x16 |
6071 | #define DAGB3_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 |
6072 | #define DAGB3_WRCLI3__MAX_OSD__SHIFT 0x1a |
6073 | #define DAGB3_WRCLI3__VIRT_CHAN_MASK 0x00000007L |
6074 | #define DAGB3_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L |
6075 | #define DAGB3_WRCLI3__URG_HIGH_MASK 0x000000F0L |
6076 | #define DAGB3_WRCLI3__URG_LOW_MASK 0x00000F00L |
6077 | #define DAGB3_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L |
6078 | #define DAGB3_WRCLI3__MAX_BW_MASK 0x001FE000L |
6079 | #define DAGB3_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L |
6080 | #define DAGB3_WRCLI3__MIN_BW_MASK 0x01C00000L |
6081 | #define DAGB3_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L |
6082 | #define DAGB3_WRCLI3__MAX_OSD_MASK 0xFC000000L |
6083 | //DAGB3_WRCLI4 |
6084 | #define DAGB3_WRCLI4__VIRT_CHAN__SHIFT 0x0 |
6085 | #define DAGB3_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 |
6086 | #define DAGB3_WRCLI4__URG_HIGH__SHIFT 0x4 |
6087 | #define DAGB3_WRCLI4__URG_LOW__SHIFT 0x8 |
6088 | #define DAGB3_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc |
6089 | #define DAGB3_WRCLI4__MAX_BW__SHIFT 0xd |
6090 | #define DAGB3_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 |
6091 | #define DAGB3_WRCLI4__MIN_BW__SHIFT 0x16 |
6092 | #define DAGB3_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 |
6093 | #define DAGB3_WRCLI4__MAX_OSD__SHIFT 0x1a |
6094 | #define DAGB3_WRCLI4__VIRT_CHAN_MASK 0x00000007L |
6095 | #define DAGB3_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L |
6096 | #define DAGB3_WRCLI4__URG_HIGH_MASK 0x000000F0L |
6097 | #define DAGB3_WRCLI4__URG_LOW_MASK 0x00000F00L |
6098 | #define DAGB3_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L |
6099 | #define DAGB3_WRCLI4__MAX_BW_MASK 0x001FE000L |
6100 | #define DAGB3_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L |
6101 | #define DAGB3_WRCLI4__MIN_BW_MASK 0x01C00000L |
6102 | #define DAGB3_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L |
6103 | #define DAGB3_WRCLI4__MAX_OSD_MASK 0xFC000000L |
6104 | //DAGB3_WRCLI5 |
6105 | #define DAGB3_WRCLI5__VIRT_CHAN__SHIFT 0x0 |
6106 | #define DAGB3_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 |
6107 | #define DAGB3_WRCLI5__URG_HIGH__SHIFT 0x4 |
6108 | #define DAGB3_WRCLI5__URG_LOW__SHIFT 0x8 |
6109 | #define DAGB3_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc |
6110 | #define DAGB3_WRCLI5__MAX_BW__SHIFT 0xd |
6111 | #define DAGB3_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 |
6112 | #define DAGB3_WRCLI5__MIN_BW__SHIFT 0x16 |
6113 | #define DAGB3_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 |
6114 | #define DAGB3_WRCLI5__MAX_OSD__SHIFT 0x1a |
6115 | #define DAGB3_WRCLI5__VIRT_CHAN_MASK 0x00000007L |
6116 | #define DAGB3_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L |
6117 | #define DAGB3_WRCLI5__URG_HIGH_MASK 0x000000F0L |
6118 | #define DAGB3_WRCLI5__URG_LOW_MASK 0x00000F00L |
6119 | #define DAGB3_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L |
6120 | #define DAGB3_WRCLI5__MAX_BW_MASK 0x001FE000L |
6121 | #define DAGB3_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L |
6122 | #define DAGB3_WRCLI5__MIN_BW_MASK 0x01C00000L |
6123 | #define DAGB3_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L |
6124 | #define DAGB3_WRCLI5__MAX_OSD_MASK 0xFC000000L |
6125 | //DAGB3_WRCLI6 |
6126 | #define DAGB3_WRCLI6__VIRT_CHAN__SHIFT 0x0 |
6127 | #define DAGB3_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 |
6128 | #define DAGB3_WRCLI6__URG_HIGH__SHIFT 0x4 |
6129 | #define DAGB3_WRCLI6__URG_LOW__SHIFT 0x8 |
6130 | #define DAGB3_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc |
6131 | #define DAGB3_WRCLI6__MAX_BW__SHIFT 0xd |
6132 | #define DAGB3_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 |
6133 | #define DAGB3_WRCLI6__MIN_BW__SHIFT 0x16 |
6134 | #define DAGB3_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 |
6135 | #define DAGB3_WRCLI6__MAX_OSD__SHIFT 0x1a |
6136 | #define DAGB3_WRCLI6__VIRT_CHAN_MASK 0x00000007L |
6137 | #define DAGB3_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L |
6138 | #define DAGB3_WRCLI6__URG_HIGH_MASK 0x000000F0L |
6139 | #define DAGB3_WRCLI6__URG_LOW_MASK 0x00000F00L |
6140 | #define DAGB3_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L |
6141 | #define DAGB3_WRCLI6__MAX_BW_MASK 0x001FE000L |
6142 | #define DAGB3_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L |
6143 | #define DAGB3_WRCLI6__MIN_BW_MASK 0x01C00000L |
6144 | #define DAGB3_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L |
6145 | #define DAGB3_WRCLI6__MAX_OSD_MASK 0xFC000000L |
6146 | //DAGB3_WRCLI7 |
6147 | #define DAGB3_WRCLI7__VIRT_CHAN__SHIFT 0x0 |
6148 | #define DAGB3_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 |
6149 | #define DAGB3_WRCLI7__URG_HIGH__SHIFT 0x4 |
6150 | #define DAGB3_WRCLI7__URG_LOW__SHIFT 0x8 |
6151 | #define DAGB3_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc |
6152 | #define DAGB3_WRCLI7__MAX_BW__SHIFT 0xd |
6153 | #define DAGB3_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 |
6154 | #define DAGB3_WRCLI7__MIN_BW__SHIFT 0x16 |
6155 | #define DAGB3_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 |
6156 | #define DAGB3_WRCLI7__MAX_OSD__SHIFT 0x1a |
6157 | #define DAGB3_WRCLI7__VIRT_CHAN_MASK 0x00000007L |
6158 | #define DAGB3_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L |
6159 | #define DAGB3_WRCLI7__URG_HIGH_MASK 0x000000F0L |
6160 | #define DAGB3_WRCLI7__URG_LOW_MASK 0x00000F00L |
6161 | #define DAGB3_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L |
6162 | #define DAGB3_WRCLI7__MAX_BW_MASK 0x001FE000L |
6163 | #define DAGB3_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L |
6164 | #define DAGB3_WRCLI7__MIN_BW_MASK 0x01C00000L |
6165 | #define DAGB3_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L |
6166 | #define DAGB3_WRCLI7__MAX_OSD_MASK 0xFC000000L |
6167 | //DAGB3_WRCLI8 |
6168 | #define DAGB3_WRCLI8__VIRT_CHAN__SHIFT 0x0 |
6169 | #define DAGB3_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 |
6170 | #define DAGB3_WRCLI8__URG_HIGH__SHIFT 0x4 |
6171 | #define DAGB3_WRCLI8__URG_LOW__SHIFT 0x8 |
6172 | #define DAGB3_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc |
6173 | #define DAGB3_WRCLI8__MAX_BW__SHIFT 0xd |
6174 | #define DAGB3_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 |
6175 | #define DAGB3_WRCLI8__MIN_BW__SHIFT 0x16 |
6176 | #define DAGB3_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 |
6177 | #define DAGB3_WRCLI8__MAX_OSD__SHIFT 0x1a |
6178 | #define DAGB3_WRCLI8__VIRT_CHAN_MASK 0x00000007L |
6179 | #define DAGB3_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L |
6180 | #define DAGB3_WRCLI8__URG_HIGH_MASK 0x000000F0L |
6181 | #define DAGB3_WRCLI8__URG_LOW_MASK 0x00000F00L |
6182 | #define DAGB3_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L |
6183 | #define DAGB3_WRCLI8__MAX_BW_MASK 0x001FE000L |
6184 | #define DAGB3_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L |
6185 | #define DAGB3_WRCLI8__MIN_BW_MASK 0x01C00000L |
6186 | #define DAGB3_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L |
6187 | #define DAGB3_WRCLI8__MAX_OSD_MASK 0xFC000000L |
6188 | //DAGB3_WRCLI9 |
6189 | #define DAGB3_WRCLI9__VIRT_CHAN__SHIFT 0x0 |
6190 | #define DAGB3_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 |
6191 | #define DAGB3_WRCLI9__URG_HIGH__SHIFT 0x4 |
6192 | #define DAGB3_WRCLI9__URG_LOW__SHIFT 0x8 |
6193 | #define DAGB3_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc |
6194 | #define DAGB3_WRCLI9__MAX_BW__SHIFT 0xd |
6195 | #define DAGB3_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 |
6196 | #define DAGB3_WRCLI9__MIN_BW__SHIFT 0x16 |
6197 | #define DAGB3_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 |
6198 | #define DAGB3_WRCLI9__MAX_OSD__SHIFT 0x1a |
6199 | #define DAGB3_WRCLI9__VIRT_CHAN_MASK 0x00000007L |
6200 | #define DAGB3_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L |
6201 | #define DAGB3_WRCLI9__URG_HIGH_MASK 0x000000F0L |
6202 | #define DAGB3_WRCLI9__URG_LOW_MASK 0x00000F00L |
6203 | #define DAGB3_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L |
6204 | #define DAGB3_WRCLI9__MAX_BW_MASK 0x001FE000L |
6205 | #define DAGB3_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L |
6206 | #define DAGB3_WRCLI9__MIN_BW_MASK 0x01C00000L |
6207 | #define DAGB3_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L |
6208 | #define DAGB3_WRCLI9__MAX_OSD_MASK 0xFC000000L |
6209 | //DAGB3_WRCLI10 |
6210 | #define DAGB3_WRCLI10__VIRT_CHAN__SHIFT 0x0 |
6211 | #define DAGB3_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 |
6212 | #define DAGB3_WRCLI10__URG_HIGH__SHIFT 0x4 |
6213 | #define DAGB3_WRCLI10__URG_LOW__SHIFT 0x8 |
6214 | #define DAGB3_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc |
6215 | #define DAGB3_WRCLI10__MAX_BW__SHIFT 0xd |
6216 | #define DAGB3_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 |
6217 | #define DAGB3_WRCLI10__MIN_BW__SHIFT 0x16 |
6218 | #define DAGB3_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 |
6219 | #define DAGB3_WRCLI10__MAX_OSD__SHIFT 0x1a |
6220 | #define DAGB3_WRCLI10__VIRT_CHAN_MASK 0x00000007L |
6221 | #define DAGB3_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L |
6222 | #define DAGB3_WRCLI10__URG_HIGH_MASK 0x000000F0L |
6223 | #define DAGB3_WRCLI10__URG_LOW_MASK 0x00000F00L |
6224 | #define DAGB3_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L |
6225 | #define DAGB3_WRCLI10__MAX_BW_MASK 0x001FE000L |
6226 | #define DAGB3_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L |
6227 | #define DAGB3_WRCLI10__MIN_BW_MASK 0x01C00000L |
6228 | #define DAGB3_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L |
6229 | #define DAGB3_WRCLI10__MAX_OSD_MASK 0xFC000000L |
6230 | //DAGB3_WRCLI11 |
6231 | #define DAGB3_WRCLI11__VIRT_CHAN__SHIFT 0x0 |
6232 | #define DAGB3_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 |
6233 | #define DAGB3_WRCLI11__URG_HIGH__SHIFT 0x4 |
6234 | #define DAGB3_WRCLI11__URG_LOW__SHIFT 0x8 |
6235 | #define DAGB3_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc |
6236 | #define DAGB3_WRCLI11__MAX_BW__SHIFT 0xd |
6237 | #define DAGB3_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 |
6238 | #define DAGB3_WRCLI11__MIN_BW__SHIFT 0x16 |
6239 | #define DAGB3_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 |
6240 | #define DAGB3_WRCLI11__MAX_OSD__SHIFT 0x1a |
6241 | #define DAGB3_WRCLI11__VIRT_CHAN_MASK 0x00000007L |
6242 | #define DAGB3_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L |
6243 | #define DAGB3_WRCLI11__URG_HIGH_MASK 0x000000F0L |
6244 | #define DAGB3_WRCLI11__URG_LOW_MASK 0x00000F00L |
6245 | #define DAGB3_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L |
6246 | #define DAGB3_WRCLI11__MAX_BW_MASK 0x001FE000L |
6247 | #define DAGB3_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L |
6248 | #define DAGB3_WRCLI11__MIN_BW_MASK 0x01C00000L |
6249 | #define DAGB3_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L |
6250 | #define DAGB3_WRCLI11__MAX_OSD_MASK 0xFC000000L |
6251 | //DAGB3_WRCLI12 |
6252 | #define DAGB3_WRCLI12__VIRT_CHAN__SHIFT 0x0 |
6253 | #define DAGB3_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 |
6254 | #define DAGB3_WRCLI12__URG_HIGH__SHIFT 0x4 |
6255 | #define DAGB3_WRCLI12__URG_LOW__SHIFT 0x8 |
6256 | #define DAGB3_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc |
6257 | #define DAGB3_WRCLI12__MAX_BW__SHIFT 0xd |
6258 | #define DAGB3_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 |
6259 | #define DAGB3_WRCLI12__MIN_BW__SHIFT 0x16 |
6260 | #define DAGB3_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 |
6261 | #define DAGB3_WRCLI12__MAX_OSD__SHIFT 0x1a |
6262 | #define DAGB3_WRCLI12__VIRT_CHAN_MASK 0x00000007L |
6263 | #define DAGB3_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L |
6264 | #define DAGB3_WRCLI12__URG_HIGH_MASK 0x000000F0L |
6265 | #define DAGB3_WRCLI12__URG_LOW_MASK 0x00000F00L |
6266 | #define DAGB3_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L |
6267 | #define DAGB3_WRCLI12__MAX_BW_MASK 0x001FE000L |
6268 | #define DAGB3_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L |
6269 | #define DAGB3_WRCLI12__MIN_BW_MASK 0x01C00000L |
6270 | #define DAGB3_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L |
6271 | #define DAGB3_WRCLI12__MAX_OSD_MASK 0xFC000000L |
6272 | //DAGB3_WRCLI13 |
6273 | #define DAGB3_WRCLI13__VIRT_CHAN__SHIFT 0x0 |
6274 | #define DAGB3_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 |
6275 | #define DAGB3_WRCLI13__URG_HIGH__SHIFT 0x4 |
6276 | #define DAGB3_WRCLI13__URG_LOW__SHIFT 0x8 |
6277 | #define DAGB3_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc |
6278 | #define DAGB3_WRCLI13__MAX_BW__SHIFT 0xd |
6279 | #define DAGB3_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 |
6280 | #define DAGB3_WRCLI13__MIN_BW__SHIFT 0x16 |
6281 | #define DAGB3_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 |
6282 | #define DAGB3_WRCLI13__MAX_OSD__SHIFT 0x1a |
6283 | #define DAGB3_WRCLI13__VIRT_CHAN_MASK 0x00000007L |
6284 | #define DAGB3_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L |
6285 | #define DAGB3_WRCLI13__URG_HIGH_MASK 0x000000F0L |
6286 | #define DAGB3_WRCLI13__URG_LOW_MASK 0x00000F00L |
6287 | #define DAGB3_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L |
6288 | #define DAGB3_WRCLI13__MAX_BW_MASK 0x001FE000L |
6289 | #define DAGB3_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L |
6290 | #define DAGB3_WRCLI13__MIN_BW_MASK 0x01C00000L |
6291 | #define DAGB3_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L |
6292 | #define DAGB3_WRCLI13__MAX_OSD_MASK 0xFC000000L |
6293 | //DAGB3_WRCLI14 |
6294 | #define DAGB3_WRCLI14__VIRT_CHAN__SHIFT 0x0 |
6295 | #define DAGB3_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 |
6296 | #define DAGB3_WRCLI14__URG_HIGH__SHIFT 0x4 |
6297 | #define DAGB3_WRCLI14__URG_LOW__SHIFT 0x8 |
6298 | #define DAGB3_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc |
6299 | #define DAGB3_WRCLI14__MAX_BW__SHIFT 0xd |
6300 | #define DAGB3_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 |
6301 | #define DAGB3_WRCLI14__MIN_BW__SHIFT 0x16 |
6302 | #define DAGB3_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 |
6303 | #define DAGB3_WRCLI14__MAX_OSD__SHIFT 0x1a |
6304 | #define DAGB3_WRCLI14__VIRT_CHAN_MASK 0x00000007L |
6305 | #define DAGB3_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L |
6306 | #define DAGB3_WRCLI14__URG_HIGH_MASK 0x000000F0L |
6307 | #define DAGB3_WRCLI14__URG_LOW_MASK 0x00000F00L |
6308 | #define DAGB3_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L |
6309 | #define DAGB3_WRCLI14__MAX_BW_MASK 0x001FE000L |
6310 | #define DAGB3_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L |
6311 | #define DAGB3_WRCLI14__MIN_BW_MASK 0x01C00000L |
6312 | #define DAGB3_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L |
6313 | #define DAGB3_WRCLI14__MAX_OSD_MASK 0xFC000000L |
6314 | //DAGB3_WRCLI15 |
6315 | #define DAGB3_WRCLI15__VIRT_CHAN__SHIFT 0x0 |
6316 | #define DAGB3_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 |
6317 | #define DAGB3_WRCLI15__URG_HIGH__SHIFT 0x4 |
6318 | #define DAGB3_WRCLI15__URG_LOW__SHIFT 0x8 |
6319 | #define DAGB3_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc |
6320 | #define DAGB3_WRCLI15__MAX_BW__SHIFT 0xd |
6321 | #define DAGB3_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 |
6322 | #define DAGB3_WRCLI15__MIN_BW__SHIFT 0x16 |
6323 | #define DAGB3_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 |
6324 | #define DAGB3_WRCLI15__MAX_OSD__SHIFT 0x1a |
6325 | #define DAGB3_WRCLI15__VIRT_CHAN_MASK 0x00000007L |
6326 | #define DAGB3_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L |
6327 | #define DAGB3_WRCLI15__URG_HIGH_MASK 0x000000F0L |
6328 | #define DAGB3_WRCLI15__URG_LOW_MASK 0x00000F00L |
6329 | #define DAGB3_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L |
6330 | #define DAGB3_WRCLI15__MAX_BW_MASK 0x001FE000L |
6331 | #define DAGB3_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L |
6332 | #define DAGB3_WRCLI15__MIN_BW_MASK 0x01C00000L |
6333 | #define DAGB3_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L |
6334 | #define DAGB3_WRCLI15__MAX_OSD_MASK 0xFC000000L |
6335 | //DAGB3_WR_CNTL |
6336 | #define DAGB3_WR_CNTL__SCLK_FREQ__SHIFT 0x0 |
6337 | #define DAGB3_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 |
6338 | #define DAGB3_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa |
6339 | #define DAGB3_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 |
6340 | #define DAGB3_WR_CNTL__IO_LEVEL__SHIFT 0x11 |
6341 | #define DAGB3_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 |
6342 | #define DAGB3_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 |
6343 | #define DAGB3_WR_CNTL__FIX_JUMP__SHIFT 0x1a |
6344 | #define DAGB3_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL |
6345 | #define DAGB3_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L |
6346 | #define DAGB3_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L |
6347 | #define DAGB3_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L |
6348 | #define DAGB3_WR_CNTL__IO_LEVEL_MASK 0x000E0000L |
6349 | #define DAGB3_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L |
6350 | #define DAGB3_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L |
6351 | #define DAGB3_WR_CNTL__FIX_JUMP_MASK 0x04000000L |
6352 | //DAGB3_WR_GMI_CNTL |
6353 | #define DAGB3_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 |
6354 | #define DAGB3_WR_GMI_CNTL__LEVEL__SHIFT 0x6 |
6355 | #define DAGB3_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 |
6356 | #define DAGB3_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd |
6357 | #define DAGB3_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL |
6358 | #define DAGB3_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L |
6359 | #define DAGB3_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L |
6360 | #define DAGB3_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L |
6361 | //DAGB3_WR_ADDR_DAGB |
6362 | #define DAGB3_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 |
6363 | #define DAGB3_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 |
6364 | #define DAGB3_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 |
6365 | #define DAGB3_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 |
6366 | #define DAGB3_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd |
6367 | #define DAGB3_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L |
6368 | #define DAGB3_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L |
6369 | #define DAGB3_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L |
6370 | #define DAGB3_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L |
6371 | #define DAGB3_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L |
6372 | //DAGB3_WR_OUTPUT_DAGB_MAX_BURST |
6373 | #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 |
6374 | #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 |
6375 | #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 |
6376 | #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc |
6377 | #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 |
6378 | #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 |
6379 | #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 |
6380 | #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c |
6381 | #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL |
6382 | #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L |
6383 | #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L |
6384 | #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L |
6385 | #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L |
6386 | #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L |
6387 | #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L |
6388 | #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L |
6389 | //DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER |
6390 | #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 |
6391 | #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 |
6392 | #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 |
6393 | #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc |
6394 | #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 |
6395 | #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 |
6396 | #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 |
6397 | #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c |
6398 | #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL |
6399 | #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L |
6400 | #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L |
6401 | #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L |
6402 | #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L |
6403 | #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L |
6404 | #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L |
6405 | #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L |
6406 | //DAGB3_WR_CGTT_CLK_CTRL |
6407 | #define DAGB3_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
6408 | #define DAGB3_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
6409 | #define DAGB3_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
6410 | #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
6411 | #define DAGB3_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
6412 | #define DAGB3_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
6413 | #define DAGB3_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
6414 | #define DAGB3_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
6415 | #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
6416 | #define DAGB3_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
6417 | //DAGB3_L1TLB_WR_CGTT_CLK_CTRL |
6418 | #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
6419 | #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
6420 | #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
6421 | #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
6422 | #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
6423 | #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
6424 | #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
6425 | #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
6426 | #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
6427 | #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
6428 | //DAGB3_ATCVM_WR_CGTT_CLK_CTRL |
6429 | #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
6430 | #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
6431 | #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
6432 | #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
6433 | #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
6434 | #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
6435 | #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
6436 | #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
6437 | #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
6438 | #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
6439 | //DAGB3_WR_ADDR_DAGB_MAX_BURST0 |
6440 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 |
6441 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 |
6442 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 |
6443 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc |
6444 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 |
6445 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 |
6446 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 |
6447 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c |
6448 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL |
6449 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L |
6450 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L |
6451 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L |
6452 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L |
6453 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L |
6454 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L |
6455 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L |
6456 | //DAGB3_WR_ADDR_DAGB_LAZY_TIMER0 |
6457 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 |
6458 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 |
6459 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 |
6460 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc |
6461 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 |
6462 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 |
6463 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 |
6464 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c |
6465 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL |
6466 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L |
6467 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L |
6468 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L |
6469 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L |
6470 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L |
6471 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L |
6472 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L |
6473 | //DAGB3_WR_ADDR_DAGB_MAX_BURST1 |
6474 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 |
6475 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 |
6476 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 |
6477 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc |
6478 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 |
6479 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 |
6480 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 |
6481 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c |
6482 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL |
6483 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L |
6484 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L |
6485 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L |
6486 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L |
6487 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L |
6488 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L |
6489 | #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L |
6490 | //DAGB3_WR_ADDR_DAGB_LAZY_TIMER1 |
6491 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 |
6492 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 |
6493 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 |
6494 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc |
6495 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 |
6496 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 |
6497 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 |
6498 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c |
6499 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL |
6500 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L |
6501 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L |
6502 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L |
6503 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L |
6504 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L |
6505 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L |
6506 | #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L |
6507 | //DAGB3_WR_DATA_DAGB |
6508 | #define DAGB3_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 |
6509 | #define DAGB3_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 |
6510 | #define DAGB3_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 |
6511 | #define DAGB3_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 |
6512 | #define DAGB3_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L |
6513 | #define DAGB3_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L |
6514 | #define DAGB3_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L |
6515 | #define DAGB3_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L |
6516 | //DAGB3_WR_DATA_DAGB_MAX_BURST0 |
6517 | #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 |
6518 | #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 |
6519 | #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 |
6520 | #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc |
6521 | #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 |
6522 | #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 |
6523 | #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 |
6524 | #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c |
6525 | #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL |
6526 | #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L |
6527 | #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L |
6528 | #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L |
6529 | #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L |
6530 | #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L |
6531 | #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L |
6532 | #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L |
6533 | //DAGB3_WR_DATA_DAGB_LAZY_TIMER0 |
6534 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 |
6535 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 |
6536 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 |
6537 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc |
6538 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 |
6539 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 |
6540 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 |
6541 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c |
6542 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL |
6543 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L |
6544 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L |
6545 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L |
6546 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L |
6547 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L |
6548 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L |
6549 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L |
6550 | //DAGB3_WR_DATA_DAGB_MAX_BURST1 |
6551 | #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 |
6552 | #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 |
6553 | #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 |
6554 | #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc |
6555 | #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 |
6556 | #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 |
6557 | #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 |
6558 | #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c |
6559 | #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL |
6560 | #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L |
6561 | #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L |
6562 | #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L |
6563 | #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L |
6564 | #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L |
6565 | #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L |
6566 | #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L |
6567 | //DAGB3_WR_DATA_DAGB_LAZY_TIMER1 |
6568 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 |
6569 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 |
6570 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 |
6571 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc |
6572 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 |
6573 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 |
6574 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 |
6575 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c |
6576 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL |
6577 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L |
6578 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L |
6579 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L |
6580 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L |
6581 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L |
6582 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L |
6583 | #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L |
6584 | //DAGB3_WR_VC0_CNTL |
6585 | #define DAGB3_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 |
6586 | #define DAGB3_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 |
6587 | #define DAGB3_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
6588 | #define DAGB3_WR_VC0_CNTL__MAX_BW__SHIFT 0xc |
6589 | #define DAGB3_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
6590 | #define DAGB3_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 |
6591 | #define DAGB3_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
6592 | #define DAGB3_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 |
6593 | #define DAGB3_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL |
6594 | #define DAGB3_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L |
6595 | #define DAGB3_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
6596 | #define DAGB3_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L |
6597 | #define DAGB3_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
6598 | #define DAGB3_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L |
6599 | #define DAGB3_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
6600 | #define DAGB3_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L |
6601 | //DAGB3_WR_VC1_CNTL |
6602 | #define DAGB3_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 |
6603 | #define DAGB3_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 |
6604 | #define DAGB3_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
6605 | #define DAGB3_WR_VC1_CNTL__MAX_BW__SHIFT 0xc |
6606 | #define DAGB3_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
6607 | #define DAGB3_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 |
6608 | #define DAGB3_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
6609 | #define DAGB3_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 |
6610 | #define DAGB3_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL |
6611 | #define DAGB3_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L |
6612 | #define DAGB3_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
6613 | #define DAGB3_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L |
6614 | #define DAGB3_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
6615 | #define DAGB3_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L |
6616 | #define DAGB3_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
6617 | #define DAGB3_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L |
6618 | //DAGB3_WR_VC2_CNTL |
6619 | #define DAGB3_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 |
6620 | #define DAGB3_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 |
6621 | #define DAGB3_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
6622 | #define DAGB3_WR_VC2_CNTL__MAX_BW__SHIFT 0xc |
6623 | #define DAGB3_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
6624 | #define DAGB3_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 |
6625 | #define DAGB3_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
6626 | #define DAGB3_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 |
6627 | #define DAGB3_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL |
6628 | #define DAGB3_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L |
6629 | #define DAGB3_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
6630 | #define DAGB3_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L |
6631 | #define DAGB3_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
6632 | #define DAGB3_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L |
6633 | #define DAGB3_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
6634 | #define DAGB3_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L |
6635 | //DAGB3_WR_VC3_CNTL |
6636 | #define DAGB3_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 |
6637 | #define DAGB3_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 |
6638 | #define DAGB3_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
6639 | #define DAGB3_WR_VC3_CNTL__MAX_BW__SHIFT 0xc |
6640 | #define DAGB3_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
6641 | #define DAGB3_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 |
6642 | #define DAGB3_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
6643 | #define DAGB3_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 |
6644 | #define DAGB3_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL |
6645 | #define DAGB3_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L |
6646 | #define DAGB3_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
6647 | #define DAGB3_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L |
6648 | #define DAGB3_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
6649 | #define DAGB3_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L |
6650 | #define DAGB3_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
6651 | #define DAGB3_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L |
6652 | //DAGB3_WR_VC4_CNTL |
6653 | #define DAGB3_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 |
6654 | #define DAGB3_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 |
6655 | #define DAGB3_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
6656 | #define DAGB3_WR_VC4_CNTL__MAX_BW__SHIFT 0xc |
6657 | #define DAGB3_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
6658 | #define DAGB3_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 |
6659 | #define DAGB3_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
6660 | #define DAGB3_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 |
6661 | #define DAGB3_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL |
6662 | #define DAGB3_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L |
6663 | #define DAGB3_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
6664 | #define DAGB3_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L |
6665 | #define DAGB3_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
6666 | #define DAGB3_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L |
6667 | #define DAGB3_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
6668 | #define DAGB3_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L |
6669 | //DAGB3_WR_VC5_CNTL |
6670 | #define DAGB3_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 |
6671 | #define DAGB3_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 |
6672 | #define DAGB3_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
6673 | #define DAGB3_WR_VC5_CNTL__MAX_BW__SHIFT 0xc |
6674 | #define DAGB3_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
6675 | #define DAGB3_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 |
6676 | #define DAGB3_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
6677 | #define DAGB3_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 |
6678 | #define DAGB3_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL |
6679 | #define DAGB3_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L |
6680 | #define DAGB3_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
6681 | #define DAGB3_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L |
6682 | #define DAGB3_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
6683 | #define DAGB3_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L |
6684 | #define DAGB3_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
6685 | #define DAGB3_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L |
6686 | //DAGB3_WR_VC6_CNTL |
6687 | #define DAGB3_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 |
6688 | #define DAGB3_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 |
6689 | #define DAGB3_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
6690 | #define DAGB3_WR_VC6_CNTL__MAX_BW__SHIFT 0xc |
6691 | #define DAGB3_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
6692 | #define DAGB3_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 |
6693 | #define DAGB3_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
6694 | #define DAGB3_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 |
6695 | #define DAGB3_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL |
6696 | #define DAGB3_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L |
6697 | #define DAGB3_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
6698 | #define DAGB3_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L |
6699 | #define DAGB3_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
6700 | #define DAGB3_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L |
6701 | #define DAGB3_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
6702 | #define DAGB3_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L |
6703 | //DAGB3_WR_VC7_CNTL |
6704 | #define DAGB3_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 |
6705 | #define DAGB3_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 |
6706 | #define DAGB3_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
6707 | #define DAGB3_WR_VC7_CNTL__MAX_BW__SHIFT 0xc |
6708 | #define DAGB3_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
6709 | #define DAGB3_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 |
6710 | #define DAGB3_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
6711 | #define DAGB3_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 |
6712 | #define DAGB3_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL |
6713 | #define DAGB3_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L |
6714 | #define DAGB3_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
6715 | #define DAGB3_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L |
6716 | #define DAGB3_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
6717 | #define DAGB3_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L |
6718 | #define DAGB3_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
6719 | #define DAGB3_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L |
6720 | //DAGB3_WR_CNTL_MISC |
6721 | #define DAGB3_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 |
6722 | #define DAGB3_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 |
6723 | #define DAGB3_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd |
6724 | #define DAGB3_WR_CNTL_MISC__STOR_CC_NEW_MODE__SHIFT 0x13 |
6725 | #define DAGB3_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 |
6726 | #define DAGB3_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 |
6727 | #define DAGB3_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a |
6728 | #define DAGB3_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL |
6729 | #define DAGB3_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L |
6730 | #define DAGB3_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L |
6731 | #define DAGB3_WR_CNTL_MISC__STOR_CC_NEW_MODE_MASK 0x00080000L |
6732 | #define DAGB3_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L |
6733 | #define DAGB3_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L |
6734 | #define DAGB3_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L |
6735 | //DAGB3_WR_TLB_CREDIT |
6736 | #define DAGB3_WR_TLB_CREDIT__TLB0__SHIFT 0x0 |
6737 | #define DAGB3_WR_TLB_CREDIT__TLB1__SHIFT 0x5 |
6738 | #define DAGB3_WR_TLB_CREDIT__TLB2__SHIFT 0xa |
6739 | #define DAGB3_WR_TLB_CREDIT__TLB3__SHIFT 0xf |
6740 | #define DAGB3_WR_TLB_CREDIT__TLB4__SHIFT 0x14 |
6741 | #define DAGB3_WR_TLB_CREDIT__TLB5__SHIFT 0x19 |
6742 | #define DAGB3_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL |
6743 | #define DAGB3_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L |
6744 | #define DAGB3_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L |
6745 | #define DAGB3_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L |
6746 | #define DAGB3_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L |
6747 | #define DAGB3_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L |
6748 | //DAGB3_WR_DATA_CREDIT |
6749 | #define DAGB3_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 |
6750 | #define DAGB3_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 |
6751 | #define DAGB3_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 |
6752 | #define DAGB3_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 |
6753 | #define DAGB3_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL |
6754 | #define DAGB3_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L |
6755 | #define DAGB3_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L |
6756 | #define DAGB3_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L |
6757 | //DAGB3_WR_MISC_CREDIT |
6758 | #define DAGB3_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 |
6759 | #define DAGB3_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 |
6760 | #define DAGB3_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 |
6761 | #define DAGB3_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 |
6762 | #define DAGB3_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL |
6763 | #define DAGB3_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L |
6764 | #define DAGB3_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L |
6765 | #define DAGB3_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L |
6766 | //DAGB3_WR_OSD_CREDIT_CNTL1 |
6767 | #define DAGB3_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 |
6768 | #define DAGB3_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x4 |
6769 | #define DAGB3_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0x8 |
6770 | #define DAGB3_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xc |
6771 | #define DAGB3_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT 0x10 |
6772 | #define DAGB3_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT 0x14 |
6773 | #define DAGB3_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x18 |
6774 | #define DAGB3_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000000FL |
6775 | #define DAGB3_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000000F0L |
6776 | #define DAGB3_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00000F00L |
6777 | #define DAGB3_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK 0x0000F000L |
6778 | #define DAGB3_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK 0x000F0000L |
6779 | #define DAGB3_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK 0x00F00000L |
6780 | #define DAGB3_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK 0x3F000000L |
6781 | //DAGB3_WR_OSD_CREDIT_CNTL2 |
6782 | #define DAGB3_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT 0x0 |
6783 | #define DAGB3_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT 0x4 |
6784 | #define DAGB3_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK 0x0000000FL |
6785 | #define DAGB3_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK 0x00000010L |
6786 | //DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1 |
6787 | #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 |
6788 | #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 |
6789 | #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa |
6790 | #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf |
6791 | #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 |
6792 | #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19 |
6793 | #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a |
6794 | #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b |
6795 | #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT 0x1c |
6796 | #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT 0x1d |
6797 | #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL |
6798 | #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L |
6799 | #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L |
6800 | #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L |
6801 | #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L |
6802 | #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L |
6803 | #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L |
6804 | #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L |
6805 | #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK 0x10000000L |
6806 | #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK 0x20000000L |
6807 | //DAGB3_WRCLI_GPU_SNOOP_OVERRIDE |
6808 | #define DAGB3_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 |
6809 | #define DAGB3_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0x0000FFFFL |
6810 | //DAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE |
6811 | #define DAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 |
6812 | #define DAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0x0000FFFFL |
6813 | //DAGB3_WRCLI_ASK_PENDING |
6814 | #define DAGB3_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 |
6815 | #define DAGB3_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL |
6816 | //DAGB3_WRCLI_GO_PENDING |
6817 | #define DAGB3_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 |
6818 | #define DAGB3_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL |
6819 | //DAGB3_WRCLI_GBLSEND_PENDING |
6820 | #define DAGB3_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 |
6821 | #define DAGB3_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL |
6822 | //DAGB3_WRCLI_TLB_PENDING |
6823 | #define DAGB3_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 |
6824 | #define DAGB3_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL |
6825 | //DAGB3_WRCLI_OARB_PENDING |
6826 | #define DAGB3_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 |
6827 | #define DAGB3_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL |
6828 | //DAGB3_WRCLI_OSD_PENDING |
6829 | #define DAGB3_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 |
6830 | #define DAGB3_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL |
6831 | //DAGB3_WRCLI_DBUS_ASK_PENDING |
6832 | #define DAGB3_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 |
6833 | #define DAGB3_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL |
6834 | //DAGB3_WRCLI_DBUS_GO_PENDING |
6835 | #define DAGB3_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 |
6836 | #define DAGB3_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL |
6837 | //DAGB3_DAGB_DLY |
6838 | #define DAGB3_DAGB_DLY__DLY__SHIFT 0x0 |
6839 | #define DAGB3_DAGB_DLY__CLI__SHIFT 0x8 |
6840 | #define DAGB3_DAGB_DLY__POS__SHIFT 0x10 |
6841 | #define DAGB3_DAGB_DLY__DLY_MASK 0x000000FFL |
6842 | #define DAGB3_DAGB_DLY__CLI_MASK 0x0000FF00L |
6843 | #define DAGB3_DAGB_DLY__POS_MASK 0x000F0000L |
6844 | //DAGB3_CNTL_MISC |
6845 | #define DAGB3_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 |
6846 | #define DAGB3_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 |
6847 | #define DAGB3_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 |
6848 | #define DAGB3_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 |
6849 | #define DAGB3_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc |
6850 | #define DAGB3_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf |
6851 | #define DAGB3_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 |
6852 | #define DAGB3_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 |
6853 | #define DAGB3_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 |
6854 | #define DAGB3_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e |
6855 | #define DAGB3_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L |
6856 | #define DAGB3_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L |
6857 | #define DAGB3_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L |
6858 | #define DAGB3_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L |
6859 | #define DAGB3_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L |
6860 | #define DAGB3_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L |
6861 | #define DAGB3_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L |
6862 | #define DAGB3_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L |
6863 | #define DAGB3_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L |
6864 | #define DAGB3_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L |
6865 | //DAGB3_CNTL_MISC2 |
6866 | #define DAGB3_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 |
6867 | #define DAGB3_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 |
6868 | #define DAGB3_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 |
6869 | #define DAGB3_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 |
6870 | #define DAGB3_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 |
6871 | #define DAGB3_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 |
6872 | #define DAGB3_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 |
6873 | #define DAGB3_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 |
6874 | #define DAGB3_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 |
6875 | #define DAGB3_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 |
6876 | #define DAGB3_CNTL_MISC2__SWAP_CTL__SHIFT 0xa |
6877 | #define DAGB3_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb |
6878 | #define DAGB3_CNTL_MISC2__HDP_CID__SHIFT 0xc |
6879 | #define DAGB3_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x10 |
6880 | #define DAGB3_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L |
6881 | #define DAGB3_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L |
6882 | #define DAGB3_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L |
6883 | #define DAGB3_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L |
6884 | #define DAGB3_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L |
6885 | #define DAGB3_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L |
6886 | #define DAGB3_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L |
6887 | #define DAGB3_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L |
6888 | #define DAGB3_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L |
6889 | #define DAGB3_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L |
6890 | #define DAGB3_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L |
6891 | #define DAGB3_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L |
6892 | #define DAGB3_CNTL_MISC2__HDP_CID_MASK 0x0000F000L |
6893 | #define DAGB3_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x003F0000L |
6894 | //DAGB3_FATAL_ERROR_CNTL |
6895 | #define DAGB3_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0 |
6896 | #define DAGB3_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL |
6897 | //DAGB3_FATAL_ERROR_CLEAR |
6898 | #define DAGB3_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0 |
6899 | #define DAGB3_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L |
6900 | //DAGB3_FATAL_ERROR_STATUS0 |
6901 | #define DAGB3_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0 |
6902 | #define DAGB3_FATAL_ERROR_STATUS0__CID__SHIFT 0x1 |
6903 | #define DAGB3_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6 |
6904 | #define DAGB3_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L |
6905 | #define DAGB3_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL |
6906 | #define DAGB3_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L |
6907 | //DAGB3_FATAL_ERROR_STATUS1 |
6908 | #define DAGB3_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0 |
6909 | #define DAGB3_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL |
6910 | //DAGB3_FATAL_ERROR_STATUS2 |
6911 | #define DAGB3_FATAL_ERROR_STATUS2__TAG__SHIFT 0x0 |
6912 | #define DAGB3_FATAL_ERROR_STATUS2__VFID__SHIFT 0x10 |
6913 | #define DAGB3_FATAL_ERROR_STATUS2__VF__SHIFT 0x14 |
6914 | #define DAGB3_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x15 |
6915 | #define DAGB3_FATAL_ERROR_STATUS2__IO__SHIFT 0x16 |
6916 | #define DAGB3_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x17 |
6917 | #define DAGB3_FATAL_ERROR_STATUS2__DBGMSK__SHIFT 0x18 |
6918 | #define DAGB3_FATAL_ERROR_STATUS2__FED__SHIFT 0x19 |
6919 | #define DAGB3_FATAL_ERROR_STATUS2__TAG_MASK 0x0000FFFFL |
6920 | #define DAGB3_FATAL_ERROR_STATUS2__VFID_MASK 0x000F0000L |
6921 | #define DAGB3_FATAL_ERROR_STATUS2__VF_MASK 0x00100000L |
6922 | #define DAGB3_FATAL_ERROR_STATUS2__SPACE_MASK 0x00200000L |
6923 | #define DAGB3_FATAL_ERROR_STATUS2__IO_MASK 0x00400000L |
6924 | #define DAGB3_FATAL_ERROR_STATUS2__SIZE_MASK 0x00800000L |
6925 | #define DAGB3_FATAL_ERROR_STATUS2__DBGMSK_MASK 0x01000000L |
6926 | #define DAGB3_FATAL_ERROR_STATUS2__FED_MASK 0x02000000L |
6927 | //DAGB3_FATAL_ERROR_STATUS3 |
6928 | #define DAGB3_FATAL_ERROR_STATUS3__NOALLOC__SHIFT 0x0 |
6929 | #define DAGB3_FATAL_ERROR_STATUS3__UNITID__SHIFT 0x1 |
6930 | #define DAGB3_FATAL_ERROR_STATUS3__OP__SHIFT 0x7 |
6931 | #define DAGB3_FATAL_ERROR_STATUS3__SECLEVEL__SHIFT 0xe |
6932 | #define DAGB3_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x11 |
6933 | #define DAGB3_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x12 |
6934 | #define DAGB3_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x13 |
6935 | #define DAGB3_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x14 |
6936 | #define DAGB3_FATAL_ERROR_STATUS3__NACK__SHIFT 0x15 |
6937 | #define DAGB3_FATAL_ERROR_STATUS3__RO__SHIFT 0x17 |
6938 | #define DAGB3_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x18 |
6939 | #define DAGB3_FATAL_ERROR_STATUS3__EOP__SHIFT 0x19 |
6940 | #define DAGB3_FATAL_ERROR_STATUS3__NOALLOC_MASK 0x00000001L |
6941 | #define DAGB3_FATAL_ERROR_STATUS3__UNITID_MASK 0x0000007EL |
6942 | #define DAGB3_FATAL_ERROR_STATUS3__OP_MASK 0x00003F80L |
6943 | #define DAGB3_FATAL_ERROR_STATUS3__SECLEVEL_MASK 0x0001C000L |
6944 | #define DAGB3_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00020000L |
6945 | #define DAGB3_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00040000L |
6946 | #define DAGB3_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00080000L |
6947 | #define DAGB3_FATAL_ERROR_STATUS3__INVAL_MASK 0x00100000L |
6948 | #define DAGB3_FATAL_ERROR_STATUS3__NACK_MASK 0x00600000L |
6949 | #define DAGB3_FATAL_ERROR_STATUS3__RO_MASK 0x00800000L |
6950 | #define DAGB3_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x01000000L |
6951 | #define DAGB3_FATAL_ERROR_STATUS3__EOP_MASK 0x02000000L |
6952 | //DAGB3_FIFO_EMPTY |
6953 | #define DAGB3_FIFO_EMPTY__EMPTY__SHIFT 0x0 |
6954 | #define DAGB3_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL |
6955 | //DAGB3_FIFO_FULL |
6956 | #define DAGB3_FIFO_FULL__FULL__SHIFT 0x0 |
6957 | #define DAGB3_FIFO_FULL__FULL_MASK 0x007FFFFFL |
6958 | //DAGB3_WR_CREDITS_FULL |
6959 | #define DAGB3_WR_CREDITS_FULL__FULL__SHIFT 0x0 |
6960 | #define DAGB3_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL |
6961 | //DAGB3_RD_CREDITS_FULL |
6962 | #define DAGB3_RD_CREDITS_FULL__FULL__SHIFT 0x0 |
6963 | #define DAGB3_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL |
6964 | //DAGB3_PERFCOUNTER_LO |
6965 | #define DAGB3_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
6966 | #define DAGB3_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
6967 | //DAGB3_PERFCOUNTER_HI |
6968 | #define DAGB3_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
6969 | #define DAGB3_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
6970 | #define DAGB3_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
6971 | #define DAGB3_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
6972 | //DAGB3_PERFCOUNTER0_CFG |
6973 | #define DAGB3_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
6974 | #define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
6975 | #define DAGB3_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
6976 | #define DAGB3_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
6977 | #define DAGB3_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
6978 | #define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
6979 | #define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
6980 | #define DAGB3_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
6981 | #define DAGB3_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
6982 | #define DAGB3_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
6983 | //DAGB3_PERFCOUNTER1_CFG |
6984 | #define DAGB3_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
6985 | #define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
6986 | #define DAGB3_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
6987 | #define DAGB3_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
6988 | #define DAGB3_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
6989 | #define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
6990 | #define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
6991 | #define DAGB3_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
6992 | #define DAGB3_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
6993 | #define DAGB3_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
6994 | //DAGB3_PERFCOUNTER2_CFG |
6995 | #define DAGB3_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 |
6996 | #define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 |
6997 | #define DAGB3_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 |
6998 | #define DAGB3_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c |
6999 | #define DAGB3_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d |
7000 | #define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL |
7001 | #define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L |
7002 | #define DAGB3_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L |
7003 | #define DAGB3_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L |
7004 | #define DAGB3_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L |
7005 | //DAGB3_PERFCOUNTER_RSLT_CNTL |
7006 | #define DAGB3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
7007 | #define DAGB3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
7008 | #define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
7009 | #define DAGB3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
7010 | #define DAGB3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
7011 | #define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
7012 | #define DAGB3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
7013 | #define DAGB3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
7014 | #define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
7015 | #define DAGB3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
7016 | #define DAGB3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
7017 | #define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
7018 | //DAGB3_L1TLB_REG_RW |
7019 | #define DAGB3_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 |
7020 | #define DAGB3_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 |
7021 | #define DAGB3_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT 0x2 |
7022 | #define DAGB3_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT 0x4 |
7023 | #define DAGB3_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT 0x5 |
7024 | #define DAGB3_L1TLB_REG_RW__RESERVE__SHIFT 0x6 |
7025 | #define DAGB3_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L |
7026 | #define DAGB3_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L |
7027 | #define DAGB3_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK 0x00000004L |
7028 | #define DAGB3_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK 0x00000010L |
7029 | #define DAGB3_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK 0x00000020L |
7030 | #define DAGB3_L1TLB_REG_RW__RESERVE_MASK 0xFFFFFFC0L |
7031 | |
7032 | |
7033 | // addressBlock: aid_mmhub_dagb_dagbdec4 |
7034 | //DAGB4_RDCLI0 |
7035 | #define DAGB4_RDCLI0__VIRT_CHAN__SHIFT 0x0 |
7036 | #define DAGB4_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 |
7037 | #define DAGB4_RDCLI0__URG_HIGH__SHIFT 0x4 |
7038 | #define DAGB4_RDCLI0__URG_LOW__SHIFT 0x8 |
7039 | #define DAGB4_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc |
7040 | #define DAGB4_RDCLI0__MAX_BW__SHIFT 0xd |
7041 | #define DAGB4_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 |
7042 | #define DAGB4_RDCLI0__MIN_BW__SHIFT 0x16 |
7043 | #define DAGB4_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7044 | #define DAGB4_RDCLI0__MAX_OSD__SHIFT 0x1a |
7045 | #define DAGB4_RDCLI0__VIRT_CHAN_MASK 0x00000007L |
7046 | #define DAGB4_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L |
7047 | #define DAGB4_RDCLI0__URG_HIGH_MASK 0x000000F0L |
7048 | #define DAGB4_RDCLI0__URG_LOW_MASK 0x00000F00L |
7049 | #define DAGB4_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L |
7050 | #define DAGB4_RDCLI0__MAX_BW_MASK 0x001FE000L |
7051 | #define DAGB4_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L |
7052 | #define DAGB4_RDCLI0__MIN_BW_MASK 0x01C00000L |
7053 | #define DAGB4_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7054 | #define DAGB4_RDCLI0__MAX_OSD_MASK 0xFC000000L |
7055 | //DAGB4_RDCLI1 |
7056 | #define DAGB4_RDCLI1__VIRT_CHAN__SHIFT 0x0 |
7057 | #define DAGB4_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 |
7058 | #define DAGB4_RDCLI1__URG_HIGH__SHIFT 0x4 |
7059 | #define DAGB4_RDCLI1__URG_LOW__SHIFT 0x8 |
7060 | #define DAGB4_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc |
7061 | #define DAGB4_RDCLI1__MAX_BW__SHIFT 0xd |
7062 | #define DAGB4_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 |
7063 | #define DAGB4_RDCLI1__MIN_BW__SHIFT 0x16 |
7064 | #define DAGB4_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7065 | #define DAGB4_RDCLI1__MAX_OSD__SHIFT 0x1a |
7066 | #define DAGB4_RDCLI1__VIRT_CHAN_MASK 0x00000007L |
7067 | #define DAGB4_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L |
7068 | #define DAGB4_RDCLI1__URG_HIGH_MASK 0x000000F0L |
7069 | #define DAGB4_RDCLI1__URG_LOW_MASK 0x00000F00L |
7070 | #define DAGB4_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L |
7071 | #define DAGB4_RDCLI1__MAX_BW_MASK 0x001FE000L |
7072 | #define DAGB4_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L |
7073 | #define DAGB4_RDCLI1__MIN_BW_MASK 0x01C00000L |
7074 | #define DAGB4_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7075 | #define DAGB4_RDCLI1__MAX_OSD_MASK 0xFC000000L |
7076 | //DAGB4_RDCLI2 |
7077 | #define DAGB4_RDCLI2__VIRT_CHAN__SHIFT 0x0 |
7078 | #define DAGB4_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 |
7079 | #define DAGB4_RDCLI2__URG_HIGH__SHIFT 0x4 |
7080 | #define DAGB4_RDCLI2__URG_LOW__SHIFT 0x8 |
7081 | #define DAGB4_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc |
7082 | #define DAGB4_RDCLI2__MAX_BW__SHIFT 0xd |
7083 | #define DAGB4_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 |
7084 | #define DAGB4_RDCLI2__MIN_BW__SHIFT 0x16 |
7085 | #define DAGB4_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7086 | #define DAGB4_RDCLI2__MAX_OSD__SHIFT 0x1a |
7087 | #define DAGB4_RDCLI2__VIRT_CHAN_MASK 0x00000007L |
7088 | #define DAGB4_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L |
7089 | #define DAGB4_RDCLI2__URG_HIGH_MASK 0x000000F0L |
7090 | #define DAGB4_RDCLI2__URG_LOW_MASK 0x00000F00L |
7091 | #define DAGB4_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L |
7092 | #define DAGB4_RDCLI2__MAX_BW_MASK 0x001FE000L |
7093 | #define DAGB4_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L |
7094 | #define DAGB4_RDCLI2__MIN_BW_MASK 0x01C00000L |
7095 | #define DAGB4_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7096 | #define DAGB4_RDCLI2__MAX_OSD_MASK 0xFC000000L |
7097 | //DAGB4_RDCLI3 |
7098 | #define DAGB4_RDCLI3__VIRT_CHAN__SHIFT 0x0 |
7099 | #define DAGB4_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 |
7100 | #define DAGB4_RDCLI3__URG_HIGH__SHIFT 0x4 |
7101 | #define DAGB4_RDCLI3__URG_LOW__SHIFT 0x8 |
7102 | #define DAGB4_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc |
7103 | #define DAGB4_RDCLI3__MAX_BW__SHIFT 0xd |
7104 | #define DAGB4_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 |
7105 | #define DAGB4_RDCLI3__MIN_BW__SHIFT 0x16 |
7106 | #define DAGB4_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7107 | #define DAGB4_RDCLI3__MAX_OSD__SHIFT 0x1a |
7108 | #define DAGB4_RDCLI3__VIRT_CHAN_MASK 0x00000007L |
7109 | #define DAGB4_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L |
7110 | #define DAGB4_RDCLI3__URG_HIGH_MASK 0x000000F0L |
7111 | #define DAGB4_RDCLI3__URG_LOW_MASK 0x00000F00L |
7112 | #define DAGB4_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L |
7113 | #define DAGB4_RDCLI3__MAX_BW_MASK 0x001FE000L |
7114 | #define DAGB4_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L |
7115 | #define DAGB4_RDCLI3__MIN_BW_MASK 0x01C00000L |
7116 | #define DAGB4_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7117 | #define DAGB4_RDCLI3__MAX_OSD_MASK 0xFC000000L |
7118 | //DAGB4_RDCLI4 |
7119 | #define DAGB4_RDCLI4__VIRT_CHAN__SHIFT 0x0 |
7120 | #define DAGB4_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 |
7121 | #define DAGB4_RDCLI4__URG_HIGH__SHIFT 0x4 |
7122 | #define DAGB4_RDCLI4__URG_LOW__SHIFT 0x8 |
7123 | #define DAGB4_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc |
7124 | #define DAGB4_RDCLI4__MAX_BW__SHIFT 0xd |
7125 | #define DAGB4_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 |
7126 | #define DAGB4_RDCLI4__MIN_BW__SHIFT 0x16 |
7127 | #define DAGB4_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7128 | #define DAGB4_RDCLI4__MAX_OSD__SHIFT 0x1a |
7129 | #define DAGB4_RDCLI4__VIRT_CHAN_MASK 0x00000007L |
7130 | #define DAGB4_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L |
7131 | #define DAGB4_RDCLI4__URG_HIGH_MASK 0x000000F0L |
7132 | #define DAGB4_RDCLI4__URG_LOW_MASK 0x00000F00L |
7133 | #define DAGB4_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L |
7134 | #define DAGB4_RDCLI4__MAX_BW_MASK 0x001FE000L |
7135 | #define DAGB4_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L |
7136 | #define DAGB4_RDCLI4__MIN_BW_MASK 0x01C00000L |
7137 | #define DAGB4_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7138 | #define DAGB4_RDCLI4__MAX_OSD_MASK 0xFC000000L |
7139 | //DAGB4_RDCLI5 |
7140 | #define DAGB4_RDCLI5__VIRT_CHAN__SHIFT 0x0 |
7141 | #define DAGB4_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 |
7142 | #define DAGB4_RDCLI5__URG_HIGH__SHIFT 0x4 |
7143 | #define DAGB4_RDCLI5__URG_LOW__SHIFT 0x8 |
7144 | #define DAGB4_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc |
7145 | #define DAGB4_RDCLI5__MAX_BW__SHIFT 0xd |
7146 | #define DAGB4_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 |
7147 | #define DAGB4_RDCLI5__MIN_BW__SHIFT 0x16 |
7148 | #define DAGB4_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7149 | #define DAGB4_RDCLI5__MAX_OSD__SHIFT 0x1a |
7150 | #define DAGB4_RDCLI5__VIRT_CHAN_MASK 0x00000007L |
7151 | #define DAGB4_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L |
7152 | #define DAGB4_RDCLI5__URG_HIGH_MASK 0x000000F0L |
7153 | #define DAGB4_RDCLI5__URG_LOW_MASK 0x00000F00L |
7154 | #define DAGB4_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L |
7155 | #define DAGB4_RDCLI5__MAX_BW_MASK 0x001FE000L |
7156 | #define DAGB4_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L |
7157 | #define DAGB4_RDCLI5__MIN_BW_MASK 0x01C00000L |
7158 | #define DAGB4_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7159 | #define DAGB4_RDCLI5__MAX_OSD_MASK 0xFC000000L |
7160 | //DAGB4_RDCLI6 |
7161 | #define DAGB4_RDCLI6__VIRT_CHAN__SHIFT 0x0 |
7162 | #define DAGB4_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 |
7163 | #define DAGB4_RDCLI6__URG_HIGH__SHIFT 0x4 |
7164 | #define DAGB4_RDCLI6__URG_LOW__SHIFT 0x8 |
7165 | #define DAGB4_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc |
7166 | #define DAGB4_RDCLI6__MAX_BW__SHIFT 0xd |
7167 | #define DAGB4_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 |
7168 | #define DAGB4_RDCLI6__MIN_BW__SHIFT 0x16 |
7169 | #define DAGB4_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7170 | #define DAGB4_RDCLI6__MAX_OSD__SHIFT 0x1a |
7171 | #define DAGB4_RDCLI6__VIRT_CHAN_MASK 0x00000007L |
7172 | #define DAGB4_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L |
7173 | #define DAGB4_RDCLI6__URG_HIGH_MASK 0x000000F0L |
7174 | #define DAGB4_RDCLI6__URG_LOW_MASK 0x00000F00L |
7175 | #define DAGB4_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L |
7176 | #define DAGB4_RDCLI6__MAX_BW_MASK 0x001FE000L |
7177 | #define DAGB4_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L |
7178 | #define DAGB4_RDCLI6__MIN_BW_MASK 0x01C00000L |
7179 | #define DAGB4_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7180 | #define DAGB4_RDCLI6__MAX_OSD_MASK 0xFC000000L |
7181 | //DAGB4_RDCLI7 |
7182 | #define DAGB4_RDCLI7__VIRT_CHAN__SHIFT 0x0 |
7183 | #define DAGB4_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 |
7184 | #define DAGB4_RDCLI7__URG_HIGH__SHIFT 0x4 |
7185 | #define DAGB4_RDCLI7__URG_LOW__SHIFT 0x8 |
7186 | #define DAGB4_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc |
7187 | #define DAGB4_RDCLI7__MAX_BW__SHIFT 0xd |
7188 | #define DAGB4_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 |
7189 | #define DAGB4_RDCLI7__MIN_BW__SHIFT 0x16 |
7190 | #define DAGB4_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7191 | #define DAGB4_RDCLI7__MAX_OSD__SHIFT 0x1a |
7192 | #define DAGB4_RDCLI7__VIRT_CHAN_MASK 0x00000007L |
7193 | #define DAGB4_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L |
7194 | #define DAGB4_RDCLI7__URG_HIGH_MASK 0x000000F0L |
7195 | #define DAGB4_RDCLI7__URG_LOW_MASK 0x00000F00L |
7196 | #define DAGB4_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L |
7197 | #define DAGB4_RDCLI7__MAX_BW_MASK 0x001FE000L |
7198 | #define DAGB4_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L |
7199 | #define DAGB4_RDCLI7__MIN_BW_MASK 0x01C00000L |
7200 | #define DAGB4_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7201 | #define DAGB4_RDCLI7__MAX_OSD_MASK 0xFC000000L |
7202 | //DAGB4_RDCLI8 |
7203 | #define DAGB4_RDCLI8__VIRT_CHAN__SHIFT 0x0 |
7204 | #define DAGB4_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 |
7205 | #define DAGB4_RDCLI8__URG_HIGH__SHIFT 0x4 |
7206 | #define DAGB4_RDCLI8__URG_LOW__SHIFT 0x8 |
7207 | #define DAGB4_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc |
7208 | #define DAGB4_RDCLI8__MAX_BW__SHIFT 0xd |
7209 | #define DAGB4_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 |
7210 | #define DAGB4_RDCLI8__MIN_BW__SHIFT 0x16 |
7211 | #define DAGB4_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7212 | #define DAGB4_RDCLI8__MAX_OSD__SHIFT 0x1a |
7213 | #define DAGB4_RDCLI8__VIRT_CHAN_MASK 0x00000007L |
7214 | #define DAGB4_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L |
7215 | #define DAGB4_RDCLI8__URG_HIGH_MASK 0x000000F0L |
7216 | #define DAGB4_RDCLI8__URG_LOW_MASK 0x00000F00L |
7217 | #define DAGB4_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L |
7218 | #define DAGB4_RDCLI8__MAX_BW_MASK 0x001FE000L |
7219 | #define DAGB4_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L |
7220 | #define DAGB4_RDCLI8__MIN_BW_MASK 0x01C00000L |
7221 | #define DAGB4_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7222 | #define DAGB4_RDCLI8__MAX_OSD_MASK 0xFC000000L |
7223 | //DAGB4_RDCLI9 |
7224 | #define DAGB4_RDCLI9__VIRT_CHAN__SHIFT 0x0 |
7225 | #define DAGB4_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 |
7226 | #define DAGB4_RDCLI9__URG_HIGH__SHIFT 0x4 |
7227 | #define DAGB4_RDCLI9__URG_LOW__SHIFT 0x8 |
7228 | #define DAGB4_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc |
7229 | #define DAGB4_RDCLI9__MAX_BW__SHIFT 0xd |
7230 | #define DAGB4_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 |
7231 | #define DAGB4_RDCLI9__MIN_BW__SHIFT 0x16 |
7232 | #define DAGB4_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7233 | #define DAGB4_RDCLI9__MAX_OSD__SHIFT 0x1a |
7234 | #define DAGB4_RDCLI9__VIRT_CHAN_MASK 0x00000007L |
7235 | #define DAGB4_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L |
7236 | #define DAGB4_RDCLI9__URG_HIGH_MASK 0x000000F0L |
7237 | #define DAGB4_RDCLI9__URG_LOW_MASK 0x00000F00L |
7238 | #define DAGB4_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L |
7239 | #define DAGB4_RDCLI9__MAX_BW_MASK 0x001FE000L |
7240 | #define DAGB4_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L |
7241 | #define DAGB4_RDCLI9__MIN_BW_MASK 0x01C00000L |
7242 | #define DAGB4_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7243 | #define DAGB4_RDCLI9__MAX_OSD_MASK 0xFC000000L |
7244 | //DAGB4_RDCLI10 |
7245 | #define DAGB4_RDCLI10__VIRT_CHAN__SHIFT 0x0 |
7246 | #define DAGB4_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 |
7247 | #define DAGB4_RDCLI10__URG_HIGH__SHIFT 0x4 |
7248 | #define DAGB4_RDCLI10__URG_LOW__SHIFT 0x8 |
7249 | #define DAGB4_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc |
7250 | #define DAGB4_RDCLI10__MAX_BW__SHIFT 0xd |
7251 | #define DAGB4_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 |
7252 | #define DAGB4_RDCLI10__MIN_BW__SHIFT 0x16 |
7253 | #define DAGB4_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7254 | #define DAGB4_RDCLI10__MAX_OSD__SHIFT 0x1a |
7255 | #define DAGB4_RDCLI10__VIRT_CHAN_MASK 0x00000007L |
7256 | #define DAGB4_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L |
7257 | #define DAGB4_RDCLI10__URG_HIGH_MASK 0x000000F0L |
7258 | #define DAGB4_RDCLI10__URG_LOW_MASK 0x00000F00L |
7259 | #define DAGB4_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L |
7260 | #define DAGB4_RDCLI10__MAX_BW_MASK 0x001FE000L |
7261 | #define DAGB4_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L |
7262 | #define DAGB4_RDCLI10__MIN_BW_MASK 0x01C00000L |
7263 | #define DAGB4_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7264 | #define DAGB4_RDCLI10__MAX_OSD_MASK 0xFC000000L |
7265 | //DAGB4_RDCLI11 |
7266 | #define DAGB4_RDCLI11__VIRT_CHAN__SHIFT 0x0 |
7267 | #define DAGB4_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 |
7268 | #define DAGB4_RDCLI11__URG_HIGH__SHIFT 0x4 |
7269 | #define DAGB4_RDCLI11__URG_LOW__SHIFT 0x8 |
7270 | #define DAGB4_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc |
7271 | #define DAGB4_RDCLI11__MAX_BW__SHIFT 0xd |
7272 | #define DAGB4_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 |
7273 | #define DAGB4_RDCLI11__MIN_BW__SHIFT 0x16 |
7274 | #define DAGB4_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7275 | #define DAGB4_RDCLI11__MAX_OSD__SHIFT 0x1a |
7276 | #define DAGB4_RDCLI11__VIRT_CHAN_MASK 0x00000007L |
7277 | #define DAGB4_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L |
7278 | #define DAGB4_RDCLI11__URG_HIGH_MASK 0x000000F0L |
7279 | #define DAGB4_RDCLI11__URG_LOW_MASK 0x00000F00L |
7280 | #define DAGB4_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L |
7281 | #define DAGB4_RDCLI11__MAX_BW_MASK 0x001FE000L |
7282 | #define DAGB4_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L |
7283 | #define DAGB4_RDCLI11__MIN_BW_MASK 0x01C00000L |
7284 | #define DAGB4_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7285 | #define DAGB4_RDCLI11__MAX_OSD_MASK 0xFC000000L |
7286 | //DAGB4_RDCLI12 |
7287 | #define DAGB4_RDCLI12__VIRT_CHAN__SHIFT 0x0 |
7288 | #define DAGB4_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 |
7289 | #define DAGB4_RDCLI12__URG_HIGH__SHIFT 0x4 |
7290 | #define DAGB4_RDCLI12__URG_LOW__SHIFT 0x8 |
7291 | #define DAGB4_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc |
7292 | #define DAGB4_RDCLI12__MAX_BW__SHIFT 0xd |
7293 | #define DAGB4_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 |
7294 | #define DAGB4_RDCLI12__MIN_BW__SHIFT 0x16 |
7295 | #define DAGB4_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7296 | #define DAGB4_RDCLI12__MAX_OSD__SHIFT 0x1a |
7297 | #define DAGB4_RDCLI12__VIRT_CHAN_MASK 0x00000007L |
7298 | #define DAGB4_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L |
7299 | #define DAGB4_RDCLI12__URG_HIGH_MASK 0x000000F0L |
7300 | #define DAGB4_RDCLI12__URG_LOW_MASK 0x00000F00L |
7301 | #define DAGB4_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L |
7302 | #define DAGB4_RDCLI12__MAX_BW_MASK 0x001FE000L |
7303 | #define DAGB4_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L |
7304 | #define DAGB4_RDCLI12__MIN_BW_MASK 0x01C00000L |
7305 | #define DAGB4_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7306 | #define DAGB4_RDCLI12__MAX_OSD_MASK 0xFC000000L |
7307 | //DAGB4_RDCLI13 |
7308 | #define DAGB4_RDCLI13__VIRT_CHAN__SHIFT 0x0 |
7309 | #define DAGB4_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 |
7310 | #define DAGB4_RDCLI13__URG_HIGH__SHIFT 0x4 |
7311 | #define DAGB4_RDCLI13__URG_LOW__SHIFT 0x8 |
7312 | #define DAGB4_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc |
7313 | #define DAGB4_RDCLI13__MAX_BW__SHIFT 0xd |
7314 | #define DAGB4_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 |
7315 | #define DAGB4_RDCLI13__MIN_BW__SHIFT 0x16 |
7316 | #define DAGB4_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7317 | #define DAGB4_RDCLI13__MAX_OSD__SHIFT 0x1a |
7318 | #define DAGB4_RDCLI13__VIRT_CHAN_MASK 0x00000007L |
7319 | #define DAGB4_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L |
7320 | #define DAGB4_RDCLI13__URG_HIGH_MASK 0x000000F0L |
7321 | #define DAGB4_RDCLI13__URG_LOW_MASK 0x00000F00L |
7322 | #define DAGB4_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L |
7323 | #define DAGB4_RDCLI13__MAX_BW_MASK 0x001FE000L |
7324 | #define DAGB4_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L |
7325 | #define DAGB4_RDCLI13__MIN_BW_MASK 0x01C00000L |
7326 | #define DAGB4_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7327 | #define DAGB4_RDCLI13__MAX_OSD_MASK 0xFC000000L |
7328 | //DAGB4_RDCLI14 |
7329 | #define DAGB4_RDCLI14__VIRT_CHAN__SHIFT 0x0 |
7330 | #define DAGB4_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 |
7331 | #define DAGB4_RDCLI14__URG_HIGH__SHIFT 0x4 |
7332 | #define DAGB4_RDCLI14__URG_LOW__SHIFT 0x8 |
7333 | #define DAGB4_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc |
7334 | #define DAGB4_RDCLI14__MAX_BW__SHIFT 0xd |
7335 | #define DAGB4_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 |
7336 | #define DAGB4_RDCLI14__MIN_BW__SHIFT 0x16 |
7337 | #define DAGB4_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7338 | #define DAGB4_RDCLI14__MAX_OSD__SHIFT 0x1a |
7339 | #define DAGB4_RDCLI14__VIRT_CHAN_MASK 0x00000007L |
7340 | #define DAGB4_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L |
7341 | #define DAGB4_RDCLI14__URG_HIGH_MASK 0x000000F0L |
7342 | #define DAGB4_RDCLI14__URG_LOW_MASK 0x00000F00L |
7343 | #define DAGB4_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L |
7344 | #define DAGB4_RDCLI14__MAX_BW_MASK 0x001FE000L |
7345 | #define DAGB4_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L |
7346 | #define DAGB4_RDCLI14__MIN_BW_MASK 0x01C00000L |
7347 | #define DAGB4_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7348 | #define DAGB4_RDCLI14__MAX_OSD_MASK 0xFC000000L |
7349 | //DAGB4_RDCLI15 |
7350 | #define DAGB4_RDCLI15__VIRT_CHAN__SHIFT 0x0 |
7351 | #define DAGB4_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 |
7352 | #define DAGB4_RDCLI15__URG_HIGH__SHIFT 0x4 |
7353 | #define DAGB4_RDCLI15__URG_LOW__SHIFT 0x8 |
7354 | #define DAGB4_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc |
7355 | #define DAGB4_RDCLI15__MAX_BW__SHIFT 0xd |
7356 | #define DAGB4_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 |
7357 | #define DAGB4_RDCLI15__MIN_BW__SHIFT 0x16 |
7358 | #define DAGB4_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7359 | #define DAGB4_RDCLI15__MAX_OSD__SHIFT 0x1a |
7360 | #define DAGB4_RDCLI15__VIRT_CHAN_MASK 0x00000007L |
7361 | #define DAGB4_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L |
7362 | #define DAGB4_RDCLI15__URG_HIGH_MASK 0x000000F0L |
7363 | #define DAGB4_RDCLI15__URG_LOW_MASK 0x00000F00L |
7364 | #define DAGB4_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L |
7365 | #define DAGB4_RDCLI15__MAX_BW_MASK 0x001FE000L |
7366 | #define DAGB4_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L |
7367 | #define DAGB4_RDCLI15__MIN_BW_MASK 0x01C00000L |
7368 | #define DAGB4_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7369 | #define DAGB4_RDCLI15__MAX_OSD_MASK 0xFC000000L |
7370 | //DAGB4_RD_CNTL |
7371 | #define DAGB4_RD_CNTL__SCLK_FREQ__SHIFT 0x0 |
7372 | #define DAGB4_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 |
7373 | #define DAGB4_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa |
7374 | #define DAGB4_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 |
7375 | #define DAGB4_RD_CNTL__IO_LEVEL__SHIFT 0x11 |
7376 | #define DAGB4_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 |
7377 | #define DAGB4_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 |
7378 | #define DAGB4_RD_CNTL__FIX_JUMP__SHIFT 0x1a |
7379 | #define DAGB4_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL |
7380 | #define DAGB4_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L |
7381 | #define DAGB4_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L |
7382 | #define DAGB4_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L |
7383 | #define DAGB4_RD_CNTL__IO_LEVEL_MASK 0x000E0000L |
7384 | #define DAGB4_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L |
7385 | #define DAGB4_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L |
7386 | #define DAGB4_RD_CNTL__FIX_JUMP_MASK 0x04000000L |
7387 | //DAGB4_RD_GMI_CNTL |
7388 | #define DAGB4_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 |
7389 | #define DAGB4_RD_GMI_CNTL__LEVEL__SHIFT 0x6 |
7390 | #define DAGB4_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 |
7391 | #define DAGB4_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd |
7392 | #define DAGB4_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL |
7393 | #define DAGB4_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L |
7394 | #define DAGB4_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L |
7395 | #define DAGB4_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L |
7396 | //DAGB4_RD_ADDR_DAGB |
7397 | #define DAGB4_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 |
7398 | #define DAGB4_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 |
7399 | #define DAGB4_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 |
7400 | #define DAGB4_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 |
7401 | #define DAGB4_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd |
7402 | #define DAGB4_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L |
7403 | #define DAGB4_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L |
7404 | #define DAGB4_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L |
7405 | #define DAGB4_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L |
7406 | #define DAGB4_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L |
7407 | //DAGB4_RD_OUTPUT_DAGB_MAX_BURST |
7408 | #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 |
7409 | #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 |
7410 | #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 |
7411 | #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc |
7412 | #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 |
7413 | #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 |
7414 | #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 |
7415 | #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c |
7416 | #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL |
7417 | #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L |
7418 | #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L |
7419 | #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L |
7420 | #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L |
7421 | #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L |
7422 | #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L |
7423 | #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L |
7424 | //DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER |
7425 | #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 |
7426 | #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 |
7427 | #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 |
7428 | #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc |
7429 | #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 |
7430 | #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 |
7431 | #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 |
7432 | #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c |
7433 | #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL |
7434 | #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L |
7435 | #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L |
7436 | #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L |
7437 | #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L |
7438 | #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L |
7439 | #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L |
7440 | #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L |
7441 | //DAGB4_RD_CGTT_CLK_CTRL |
7442 | #define DAGB4_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
7443 | #define DAGB4_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
7444 | #define DAGB4_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
7445 | #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
7446 | #define DAGB4_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
7447 | #define DAGB4_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
7448 | #define DAGB4_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
7449 | #define DAGB4_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
7450 | #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
7451 | #define DAGB4_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
7452 | //DAGB4_L1TLB_RD_CGTT_CLK_CTRL |
7453 | #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
7454 | #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
7455 | #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
7456 | #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
7457 | #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
7458 | #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
7459 | #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
7460 | #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
7461 | #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
7462 | #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
7463 | //DAGB4_ATCVM_RD_CGTT_CLK_CTRL |
7464 | #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
7465 | #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
7466 | #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
7467 | #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
7468 | #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
7469 | #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
7470 | #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
7471 | #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
7472 | #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
7473 | #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
7474 | //DAGB4_RD_ADDR_DAGB_MAX_BURST0 |
7475 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 |
7476 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 |
7477 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 |
7478 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc |
7479 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 |
7480 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 |
7481 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 |
7482 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c |
7483 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL |
7484 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L |
7485 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L |
7486 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L |
7487 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L |
7488 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L |
7489 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L |
7490 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L |
7491 | //DAGB4_RD_ADDR_DAGB_LAZY_TIMER0 |
7492 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 |
7493 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 |
7494 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 |
7495 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc |
7496 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 |
7497 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 |
7498 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 |
7499 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c |
7500 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL |
7501 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L |
7502 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L |
7503 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L |
7504 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L |
7505 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L |
7506 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L |
7507 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L |
7508 | //DAGB4_RD_ADDR_DAGB_MAX_BURST1 |
7509 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 |
7510 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 |
7511 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 |
7512 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc |
7513 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 |
7514 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 |
7515 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 |
7516 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c |
7517 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL |
7518 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L |
7519 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L |
7520 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L |
7521 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L |
7522 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L |
7523 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L |
7524 | #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L |
7525 | //DAGB4_RD_ADDR_DAGB_LAZY_TIMER1 |
7526 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 |
7527 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 |
7528 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 |
7529 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc |
7530 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 |
7531 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 |
7532 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 |
7533 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c |
7534 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL |
7535 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L |
7536 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L |
7537 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L |
7538 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L |
7539 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L |
7540 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L |
7541 | #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L |
7542 | //DAGB4_RD_VC0_CNTL |
7543 | #define DAGB4_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 |
7544 | #define DAGB4_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 |
7545 | #define DAGB4_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
7546 | #define DAGB4_RD_VC0_CNTL__MAX_BW__SHIFT 0xc |
7547 | #define DAGB4_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
7548 | #define DAGB4_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 |
7549 | #define DAGB4_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
7550 | #define DAGB4_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 |
7551 | #define DAGB4_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL |
7552 | #define DAGB4_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L |
7553 | #define DAGB4_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
7554 | #define DAGB4_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L |
7555 | #define DAGB4_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
7556 | #define DAGB4_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L |
7557 | #define DAGB4_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
7558 | #define DAGB4_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L |
7559 | //DAGB4_RD_VC1_CNTL |
7560 | #define DAGB4_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 |
7561 | #define DAGB4_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 |
7562 | #define DAGB4_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
7563 | #define DAGB4_RD_VC1_CNTL__MAX_BW__SHIFT 0xc |
7564 | #define DAGB4_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
7565 | #define DAGB4_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 |
7566 | #define DAGB4_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
7567 | #define DAGB4_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 |
7568 | #define DAGB4_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL |
7569 | #define DAGB4_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L |
7570 | #define DAGB4_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
7571 | #define DAGB4_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L |
7572 | #define DAGB4_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
7573 | #define DAGB4_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L |
7574 | #define DAGB4_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
7575 | #define DAGB4_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L |
7576 | //DAGB4_RD_VC2_CNTL |
7577 | #define DAGB4_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 |
7578 | #define DAGB4_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 |
7579 | #define DAGB4_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
7580 | #define DAGB4_RD_VC2_CNTL__MAX_BW__SHIFT 0xc |
7581 | #define DAGB4_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
7582 | #define DAGB4_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 |
7583 | #define DAGB4_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
7584 | #define DAGB4_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 |
7585 | #define DAGB4_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL |
7586 | #define DAGB4_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L |
7587 | #define DAGB4_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
7588 | #define DAGB4_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L |
7589 | #define DAGB4_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
7590 | #define DAGB4_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L |
7591 | #define DAGB4_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
7592 | #define DAGB4_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L |
7593 | //DAGB4_RD_VC3_CNTL |
7594 | #define DAGB4_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 |
7595 | #define DAGB4_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 |
7596 | #define DAGB4_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
7597 | #define DAGB4_RD_VC3_CNTL__MAX_BW__SHIFT 0xc |
7598 | #define DAGB4_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
7599 | #define DAGB4_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 |
7600 | #define DAGB4_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
7601 | #define DAGB4_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 |
7602 | #define DAGB4_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL |
7603 | #define DAGB4_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L |
7604 | #define DAGB4_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
7605 | #define DAGB4_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L |
7606 | #define DAGB4_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
7607 | #define DAGB4_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L |
7608 | #define DAGB4_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
7609 | #define DAGB4_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L |
7610 | //DAGB4_RD_VC4_CNTL |
7611 | #define DAGB4_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 |
7612 | #define DAGB4_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 |
7613 | #define DAGB4_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
7614 | #define DAGB4_RD_VC4_CNTL__MAX_BW__SHIFT 0xc |
7615 | #define DAGB4_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
7616 | #define DAGB4_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 |
7617 | #define DAGB4_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
7618 | #define DAGB4_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 |
7619 | #define DAGB4_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL |
7620 | #define DAGB4_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L |
7621 | #define DAGB4_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
7622 | #define DAGB4_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L |
7623 | #define DAGB4_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
7624 | #define DAGB4_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L |
7625 | #define DAGB4_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
7626 | #define DAGB4_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L |
7627 | //DAGB4_RD_VC5_CNTL |
7628 | #define DAGB4_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 |
7629 | #define DAGB4_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 |
7630 | #define DAGB4_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
7631 | #define DAGB4_RD_VC5_CNTL__MAX_BW__SHIFT 0xc |
7632 | #define DAGB4_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
7633 | #define DAGB4_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 |
7634 | #define DAGB4_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
7635 | #define DAGB4_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 |
7636 | #define DAGB4_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL |
7637 | #define DAGB4_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L |
7638 | #define DAGB4_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
7639 | #define DAGB4_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L |
7640 | #define DAGB4_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
7641 | #define DAGB4_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L |
7642 | #define DAGB4_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
7643 | #define DAGB4_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L |
7644 | //DAGB4_RD_VC6_CNTL |
7645 | #define DAGB4_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 |
7646 | #define DAGB4_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 |
7647 | #define DAGB4_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
7648 | #define DAGB4_RD_VC6_CNTL__MAX_BW__SHIFT 0xc |
7649 | #define DAGB4_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
7650 | #define DAGB4_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 |
7651 | #define DAGB4_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
7652 | #define DAGB4_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 |
7653 | #define DAGB4_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL |
7654 | #define DAGB4_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L |
7655 | #define DAGB4_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
7656 | #define DAGB4_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L |
7657 | #define DAGB4_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
7658 | #define DAGB4_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L |
7659 | #define DAGB4_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
7660 | #define DAGB4_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L |
7661 | //DAGB4_RD_VC7_CNTL |
7662 | #define DAGB4_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 |
7663 | #define DAGB4_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 |
7664 | #define DAGB4_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
7665 | #define DAGB4_RD_VC7_CNTL__MAX_BW__SHIFT 0xc |
7666 | #define DAGB4_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
7667 | #define DAGB4_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 |
7668 | #define DAGB4_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
7669 | #define DAGB4_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 |
7670 | #define DAGB4_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL |
7671 | #define DAGB4_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L |
7672 | #define DAGB4_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
7673 | #define DAGB4_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L |
7674 | #define DAGB4_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
7675 | #define DAGB4_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L |
7676 | #define DAGB4_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
7677 | #define DAGB4_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L |
7678 | //DAGB4_RD_CNTL_MISC |
7679 | #define DAGB4_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 |
7680 | #define DAGB4_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 |
7681 | #define DAGB4_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd |
7682 | #define DAGB4_RD_CNTL_MISC__STOR_CC_NEW_MODE__SHIFT 0x13 |
7683 | #define DAGB4_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 |
7684 | #define DAGB4_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 |
7685 | #define DAGB4_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a |
7686 | #define DAGB4_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL |
7687 | #define DAGB4_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L |
7688 | #define DAGB4_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L |
7689 | #define DAGB4_RD_CNTL_MISC__STOR_CC_NEW_MODE_MASK 0x00080000L |
7690 | #define DAGB4_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L |
7691 | #define DAGB4_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L |
7692 | #define DAGB4_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L |
7693 | //DAGB4_RD_TLB_CREDIT |
7694 | #define DAGB4_RD_TLB_CREDIT__TLB0__SHIFT 0x0 |
7695 | #define DAGB4_RD_TLB_CREDIT__TLB1__SHIFT 0x5 |
7696 | #define DAGB4_RD_TLB_CREDIT__TLB2__SHIFT 0xa |
7697 | #define DAGB4_RD_TLB_CREDIT__TLB3__SHIFT 0xf |
7698 | #define DAGB4_RD_TLB_CREDIT__TLB4__SHIFT 0x14 |
7699 | #define DAGB4_RD_TLB_CREDIT__TLB5__SHIFT 0x19 |
7700 | #define DAGB4_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL |
7701 | #define DAGB4_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L |
7702 | #define DAGB4_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L |
7703 | #define DAGB4_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L |
7704 | #define DAGB4_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L |
7705 | #define DAGB4_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L |
7706 | //DAGB4_RD_RDRET_CREDIT_CNTL |
7707 | #define DAGB4_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0 |
7708 | #define DAGB4_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x6 |
7709 | #define DAGB4_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xc |
7710 | #define DAGB4_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0x12 |
7711 | #define DAGB4_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x18 |
7712 | #define DAGB4_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e |
7713 | #define DAGB4_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f |
7714 | #define DAGB4_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000003FL |
7715 | #define DAGB4_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x00000FC0L |
7716 | #define DAGB4_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x0003F000L |
7717 | #define DAGB4_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x00FC0000L |
7718 | #define DAGB4_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x3F000000L |
7719 | #define DAGB4_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L |
7720 | #define DAGB4_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L |
7721 | //DAGB4_RD_RDRET_CREDIT_CNTL2 |
7722 | #define DAGB4_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT 0x0 |
7723 | #define DAGB4_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT 0x6 |
7724 | #define DAGB4_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0xc |
7725 | #define DAGB4_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK 0x0000003FL |
7726 | #define DAGB4_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK 0x00000FC0L |
7727 | #define DAGB4_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0007F000L |
7728 | //DAGB4_RDCLI_ASK_PENDING |
7729 | #define DAGB4_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 |
7730 | #define DAGB4_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL |
7731 | //DAGB4_RDCLI_GO_PENDING |
7732 | #define DAGB4_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 |
7733 | #define DAGB4_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL |
7734 | //DAGB4_RDCLI_GBLSEND_PENDING |
7735 | #define DAGB4_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 |
7736 | #define DAGB4_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL |
7737 | //DAGB4_RDCLI_TLB_PENDING |
7738 | #define DAGB4_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 |
7739 | #define DAGB4_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL |
7740 | //DAGB4_RDCLI_OARB_PENDING |
7741 | #define DAGB4_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 |
7742 | #define DAGB4_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL |
7743 | //DAGB4_RDCLI_OSD_PENDING |
7744 | #define DAGB4_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 |
7745 | #define DAGB4_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL |
7746 | //DAGB4_WRCLI0 |
7747 | #define DAGB4_WRCLI0__VIRT_CHAN__SHIFT 0x0 |
7748 | #define DAGB4_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 |
7749 | #define DAGB4_WRCLI0__URG_HIGH__SHIFT 0x4 |
7750 | #define DAGB4_WRCLI0__URG_LOW__SHIFT 0x8 |
7751 | #define DAGB4_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc |
7752 | #define DAGB4_WRCLI0__MAX_BW__SHIFT 0xd |
7753 | #define DAGB4_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 |
7754 | #define DAGB4_WRCLI0__MIN_BW__SHIFT 0x16 |
7755 | #define DAGB4_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7756 | #define DAGB4_WRCLI0__MAX_OSD__SHIFT 0x1a |
7757 | #define DAGB4_WRCLI0__VIRT_CHAN_MASK 0x00000007L |
7758 | #define DAGB4_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L |
7759 | #define DAGB4_WRCLI0__URG_HIGH_MASK 0x000000F0L |
7760 | #define DAGB4_WRCLI0__URG_LOW_MASK 0x00000F00L |
7761 | #define DAGB4_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L |
7762 | #define DAGB4_WRCLI0__MAX_BW_MASK 0x001FE000L |
7763 | #define DAGB4_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L |
7764 | #define DAGB4_WRCLI0__MIN_BW_MASK 0x01C00000L |
7765 | #define DAGB4_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7766 | #define DAGB4_WRCLI0__MAX_OSD_MASK 0xFC000000L |
7767 | //DAGB4_WRCLI1 |
7768 | #define DAGB4_WRCLI1__VIRT_CHAN__SHIFT 0x0 |
7769 | #define DAGB4_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 |
7770 | #define DAGB4_WRCLI1__URG_HIGH__SHIFT 0x4 |
7771 | #define DAGB4_WRCLI1__URG_LOW__SHIFT 0x8 |
7772 | #define DAGB4_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc |
7773 | #define DAGB4_WRCLI1__MAX_BW__SHIFT 0xd |
7774 | #define DAGB4_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 |
7775 | #define DAGB4_WRCLI1__MIN_BW__SHIFT 0x16 |
7776 | #define DAGB4_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7777 | #define DAGB4_WRCLI1__MAX_OSD__SHIFT 0x1a |
7778 | #define DAGB4_WRCLI1__VIRT_CHAN_MASK 0x00000007L |
7779 | #define DAGB4_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L |
7780 | #define DAGB4_WRCLI1__URG_HIGH_MASK 0x000000F0L |
7781 | #define DAGB4_WRCLI1__URG_LOW_MASK 0x00000F00L |
7782 | #define DAGB4_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L |
7783 | #define DAGB4_WRCLI1__MAX_BW_MASK 0x001FE000L |
7784 | #define DAGB4_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L |
7785 | #define DAGB4_WRCLI1__MIN_BW_MASK 0x01C00000L |
7786 | #define DAGB4_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7787 | #define DAGB4_WRCLI1__MAX_OSD_MASK 0xFC000000L |
7788 | //DAGB4_WRCLI2 |
7789 | #define DAGB4_WRCLI2__VIRT_CHAN__SHIFT 0x0 |
7790 | #define DAGB4_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 |
7791 | #define DAGB4_WRCLI2__URG_HIGH__SHIFT 0x4 |
7792 | #define DAGB4_WRCLI2__URG_LOW__SHIFT 0x8 |
7793 | #define DAGB4_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc |
7794 | #define DAGB4_WRCLI2__MAX_BW__SHIFT 0xd |
7795 | #define DAGB4_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 |
7796 | #define DAGB4_WRCLI2__MIN_BW__SHIFT 0x16 |
7797 | #define DAGB4_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7798 | #define DAGB4_WRCLI2__MAX_OSD__SHIFT 0x1a |
7799 | #define DAGB4_WRCLI2__VIRT_CHAN_MASK 0x00000007L |
7800 | #define DAGB4_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L |
7801 | #define DAGB4_WRCLI2__URG_HIGH_MASK 0x000000F0L |
7802 | #define DAGB4_WRCLI2__URG_LOW_MASK 0x00000F00L |
7803 | #define DAGB4_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L |
7804 | #define DAGB4_WRCLI2__MAX_BW_MASK 0x001FE000L |
7805 | #define DAGB4_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L |
7806 | #define DAGB4_WRCLI2__MIN_BW_MASK 0x01C00000L |
7807 | #define DAGB4_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7808 | #define DAGB4_WRCLI2__MAX_OSD_MASK 0xFC000000L |
7809 | //DAGB4_WRCLI3 |
7810 | #define DAGB4_WRCLI3__VIRT_CHAN__SHIFT 0x0 |
7811 | #define DAGB4_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 |
7812 | #define DAGB4_WRCLI3__URG_HIGH__SHIFT 0x4 |
7813 | #define DAGB4_WRCLI3__URG_LOW__SHIFT 0x8 |
7814 | #define DAGB4_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc |
7815 | #define DAGB4_WRCLI3__MAX_BW__SHIFT 0xd |
7816 | #define DAGB4_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 |
7817 | #define DAGB4_WRCLI3__MIN_BW__SHIFT 0x16 |
7818 | #define DAGB4_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7819 | #define DAGB4_WRCLI3__MAX_OSD__SHIFT 0x1a |
7820 | #define DAGB4_WRCLI3__VIRT_CHAN_MASK 0x00000007L |
7821 | #define DAGB4_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L |
7822 | #define DAGB4_WRCLI3__URG_HIGH_MASK 0x000000F0L |
7823 | #define DAGB4_WRCLI3__URG_LOW_MASK 0x00000F00L |
7824 | #define DAGB4_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L |
7825 | #define DAGB4_WRCLI3__MAX_BW_MASK 0x001FE000L |
7826 | #define DAGB4_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L |
7827 | #define DAGB4_WRCLI3__MIN_BW_MASK 0x01C00000L |
7828 | #define DAGB4_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7829 | #define DAGB4_WRCLI3__MAX_OSD_MASK 0xFC000000L |
7830 | //DAGB4_WRCLI4 |
7831 | #define DAGB4_WRCLI4__VIRT_CHAN__SHIFT 0x0 |
7832 | #define DAGB4_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 |
7833 | #define DAGB4_WRCLI4__URG_HIGH__SHIFT 0x4 |
7834 | #define DAGB4_WRCLI4__URG_LOW__SHIFT 0x8 |
7835 | #define DAGB4_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc |
7836 | #define DAGB4_WRCLI4__MAX_BW__SHIFT 0xd |
7837 | #define DAGB4_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 |
7838 | #define DAGB4_WRCLI4__MIN_BW__SHIFT 0x16 |
7839 | #define DAGB4_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7840 | #define DAGB4_WRCLI4__MAX_OSD__SHIFT 0x1a |
7841 | #define DAGB4_WRCLI4__VIRT_CHAN_MASK 0x00000007L |
7842 | #define DAGB4_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L |
7843 | #define DAGB4_WRCLI4__URG_HIGH_MASK 0x000000F0L |
7844 | #define DAGB4_WRCLI4__URG_LOW_MASK 0x00000F00L |
7845 | #define DAGB4_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L |
7846 | #define DAGB4_WRCLI4__MAX_BW_MASK 0x001FE000L |
7847 | #define DAGB4_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L |
7848 | #define DAGB4_WRCLI4__MIN_BW_MASK 0x01C00000L |
7849 | #define DAGB4_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7850 | #define DAGB4_WRCLI4__MAX_OSD_MASK 0xFC000000L |
7851 | //DAGB4_WRCLI5 |
7852 | #define DAGB4_WRCLI5__VIRT_CHAN__SHIFT 0x0 |
7853 | #define DAGB4_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 |
7854 | #define DAGB4_WRCLI5__URG_HIGH__SHIFT 0x4 |
7855 | #define DAGB4_WRCLI5__URG_LOW__SHIFT 0x8 |
7856 | #define DAGB4_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc |
7857 | #define DAGB4_WRCLI5__MAX_BW__SHIFT 0xd |
7858 | #define DAGB4_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 |
7859 | #define DAGB4_WRCLI5__MIN_BW__SHIFT 0x16 |
7860 | #define DAGB4_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7861 | #define DAGB4_WRCLI5__MAX_OSD__SHIFT 0x1a |
7862 | #define DAGB4_WRCLI5__VIRT_CHAN_MASK 0x00000007L |
7863 | #define DAGB4_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L |
7864 | #define DAGB4_WRCLI5__URG_HIGH_MASK 0x000000F0L |
7865 | #define DAGB4_WRCLI5__URG_LOW_MASK 0x00000F00L |
7866 | #define DAGB4_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L |
7867 | #define DAGB4_WRCLI5__MAX_BW_MASK 0x001FE000L |
7868 | #define DAGB4_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L |
7869 | #define DAGB4_WRCLI5__MIN_BW_MASK 0x01C00000L |
7870 | #define DAGB4_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7871 | #define DAGB4_WRCLI5__MAX_OSD_MASK 0xFC000000L |
7872 | //DAGB4_WRCLI6 |
7873 | #define DAGB4_WRCLI6__VIRT_CHAN__SHIFT 0x0 |
7874 | #define DAGB4_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 |
7875 | #define DAGB4_WRCLI6__URG_HIGH__SHIFT 0x4 |
7876 | #define DAGB4_WRCLI6__URG_LOW__SHIFT 0x8 |
7877 | #define DAGB4_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc |
7878 | #define DAGB4_WRCLI6__MAX_BW__SHIFT 0xd |
7879 | #define DAGB4_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 |
7880 | #define DAGB4_WRCLI6__MIN_BW__SHIFT 0x16 |
7881 | #define DAGB4_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7882 | #define DAGB4_WRCLI6__MAX_OSD__SHIFT 0x1a |
7883 | #define DAGB4_WRCLI6__VIRT_CHAN_MASK 0x00000007L |
7884 | #define DAGB4_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L |
7885 | #define DAGB4_WRCLI6__URG_HIGH_MASK 0x000000F0L |
7886 | #define DAGB4_WRCLI6__URG_LOW_MASK 0x00000F00L |
7887 | #define DAGB4_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L |
7888 | #define DAGB4_WRCLI6__MAX_BW_MASK 0x001FE000L |
7889 | #define DAGB4_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L |
7890 | #define DAGB4_WRCLI6__MIN_BW_MASK 0x01C00000L |
7891 | #define DAGB4_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7892 | #define DAGB4_WRCLI6__MAX_OSD_MASK 0xFC000000L |
7893 | //DAGB4_WRCLI7 |
7894 | #define DAGB4_WRCLI7__VIRT_CHAN__SHIFT 0x0 |
7895 | #define DAGB4_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 |
7896 | #define DAGB4_WRCLI7__URG_HIGH__SHIFT 0x4 |
7897 | #define DAGB4_WRCLI7__URG_LOW__SHIFT 0x8 |
7898 | #define DAGB4_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc |
7899 | #define DAGB4_WRCLI7__MAX_BW__SHIFT 0xd |
7900 | #define DAGB4_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 |
7901 | #define DAGB4_WRCLI7__MIN_BW__SHIFT 0x16 |
7902 | #define DAGB4_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7903 | #define DAGB4_WRCLI7__MAX_OSD__SHIFT 0x1a |
7904 | #define DAGB4_WRCLI7__VIRT_CHAN_MASK 0x00000007L |
7905 | #define DAGB4_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L |
7906 | #define DAGB4_WRCLI7__URG_HIGH_MASK 0x000000F0L |
7907 | #define DAGB4_WRCLI7__URG_LOW_MASK 0x00000F00L |
7908 | #define DAGB4_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L |
7909 | #define DAGB4_WRCLI7__MAX_BW_MASK 0x001FE000L |
7910 | #define DAGB4_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L |
7911 | #define DAGB4_WRCLI7__MIN_BW_MASK 0x01C00000L |
7912 | #define DAGB4_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7913 | #define DAGB4_WRCLI7__MAX_OSD_MASK 0xFC000000L |
7914 | //DAGB4_WRCLI8 |
7915 | #define DAGB4_WRCLI8__VIRT_CHAN__SHIFT 0x0 |
7916 | #define DAGB4_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 |
7917 | #define DAGB4_WRCLI8__URG_HIGH__SHIFT 0x4 |
7918 | #define DAGB4_WRCLI8__URG_LOW__SHIFT 0x8 |
7919 | #define DAGB4_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc |
7920 | #define DAGB4_WRCLI8__MAX_BW__SHIFT 0xd |
7921 | #define DAGB4_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 |
7922 | #define DAGB4_WRCLI8__MIN_BW__SHIFT 0x16 |
7923 | #define DAGB4_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7924 | #define DAGB4_WRCLI8__MAX_OSD__SHIFT 0x1a |
7925 | #define DAGB4_WRCLI8__VIRT_CHAN_MASK 0x00000007L |
7926 | #define DAGB4_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L |
7927 | #define DAGB4_WRCLI8__URG_HIGH_MASK 0x000000F0L |
7928 | #define DAGB4_WRCLI8__URG_LOW_MASK 0x00000F00L |
7929 | #define DAGB4_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L |
7930 | #define DAGB4_WRCLI8__MAX_BW_MASK 0x001FE000L |
7931 | #define DAGB4_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L |
7932 | #define DAGB4_WRCLI8__MIN_BW_MASK 0x01C00000L |
7933 | #define DAGB4_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7934 | #define DAGB4_WRCLI8__MAX_OSD_MASK 0xFC000000L |
7935 | //DAGB4_WRCLI9 |
7936 | #define DAGB4_WRCLI9__VIRT_CHAN__SHIFT 0x0 |
7937 | #define DAGB4_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 |
7938 | #define DAGB4_WRCLI9__URG_HIGH__SHIFT 0x4 |
7939 | #define DAGB4_WRCLI9__URG_LOW__SHIFT 0x8 |
7940 | #define DAGB4_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc |
7941 | #define DAGB4_WRCLI9__MAX_BW__SHIFT 0xd |
7942 | #define DAGB4_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 |
7943 | #define DAGB4_WRCLI9__MIN_BW__SHIFT 0x16 |
7944 | #define DAGB4_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7945 | #define DAGB4_WRCLI9__MAX_OSD__SHIFT 0x1a |
7946 | #define DAGB4_WRCLI9__VIRT_CHAN_MASK 0x00000007L |
7947 | #define DAGB4_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L |
7948 | #define DAGB4_WRCLI9__URG_HIGH_MASK 0x000000F0L |
7949 | #define DAGB4_WRCLI9__URG_LOW_MASK 0x00000F00L |
7950 | #define DAGB4_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L |
7951 | #define DAGB4_WRCLI9__MAX_BW_MASK 0x001FE000L |
7952 | #define DAGB4_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L |
7953 | #define DAGB4_WRCLI9__MIN_BW_MASK 0x01C00000L |
7954 | #define DAGB4_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7955 | #define DAGB4_WRCLI9__MAX_OSD_MASK 0xFC000000L |
7956 | //DAGB4_WRCLI10 |
7957 | #define DAGB4_WRCLI10__VIRT_CHAN__SHIFT 0x0 |
7958 | #define DAGB4_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 |
7959 | #define DAGB4_WRCLI10__URG_HIGH__SHIFT 0x4 |
7960 | #define DAGB4_WRCLI10__URG_LOW__SHIFT 0x8 |
7961 | #define DAGB4_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc |
7962 | #define DAGB4_WRCLI10__MAX_BW__SHIFT 0xd |
7963 | #define DAGB4_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 |
7964 | #define DAGB4_WRCLI10__MIN_BW__SHIFT 0x16 |
7965 | #define DAGB4_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7966 | #define DAGB4_WRCLI10__MAX_OSD__SHIFT 0x1a |
7967 | #define DAGB4_WRCLI10__VIRT_CHAN_MASK 0x00000007L |
7968 | #define DAGB4_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L |
7969 | #define DAGB4_WRCLI10__URG_HIGH_MASK 0x000000F0L |
7970 | #define DAGB4_WRCLI10__URG_LOW_MASK 0x00000F00L |
7971 | #define DAGB4_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L |
7972 | #define DAGB4_WRCLI10__MAX_BW_MASK 0x001FE000L |
7973 | #define DAGB4_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L |
7974 | #define DAGB4_WRCLI10__MIN_BW_MASK 0x01C00000L |
7975 | #define DAGB4_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7976 | #define DAGB4_WRCLI10__MAX_OSD_MASK 0xFC000000L |
7977 | //DAGB4_WRCLI11 |
7978 | #define DAGB4_WRCLI11__VIRT_CHAN__SHIFT 0x0 |
7979 | #define DAGB4_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 |
7980 | #define DAGB4_WRCLI11__URG_HIGH__SHIFT 0x4 |
7981 | #define DAGB4_WRCLI11__URG_LOW__SHIFT 0x8 |
7982 | #define DAGB4_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc |
7983 | #define DAGB4_WRCLI11__MAX_BW__SHIFT 0xd |
7984 | #define DAGB4_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 |
7985 | #define DAGB4_WRCLI11__MIN_BW__SHIFT 0x16 |
7986 | #define DAGB4_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 |
7987 | #define DAGB4_WRCLI11__MAX_OSD__SHIFT 0x1a |
7988 | #define DAGB4_WRCLI11__VIRT_CHAN_MASK 0x00000007L |
7989 | #define DAGB4_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L |
7990 | #define DAGB4_WRCLI11__URG_HIGH_MASK 0x000000F0L |
7991 | #define DAGB4_WRCLI11__URG_LOW_MASK 0x00000F00L |
7992 | #define DAGB4_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L |
7993 | #define DAGB4_WRCLI11__MAX_BW_MASK 0x001FE000L |
7994 | #define DAGB4_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L |
7995 | #define DAGB4_WRCLI11__MIN_BW_MASK 0x01C00000L |
7996 | #define DAGB4_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L |
7997 | #define DAGB4_WRCLI11__MAX_OSD_MASK 0xFC000000L |
7998 | //DAGB4_WRCLI12 |
7999 | #define DAGB4_WRCLI12__VIRT_CHAN__SHIFT 0x0 |
8000 | #define DAGB4_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 |
8001 | #define DAGB4_WRCLI12__URG_HIGH__SHIFT 0x4 |
8002 | #define DAGB4_WRCLI12__URG_LOW__SHIFT 0x8 |
8003 | #define DAGB4_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc |
8004 | #define DAGB4_WRCLI12__MAX_BW__SHIFT 0xd |
8005 | #define DAGB4_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 |
8006 | #define DAGB4_WRCLI12__MIN_BW__SHIFT 0x16 |
8007 | #define DAGB4_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 |
8008 | #define DAGB4_WRCLI12__MAX_OSD__SHIFT 0x1a |
8009 | #define DAGB4_WRCLI12__VIRT_CHAN_MASK 0x00000007L |
8010 | #define DAGB4_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L |
8011 | #define DAGB4_WRCLI12__URG_HIGH_MASK 0x000000F0L |
8012 | #define DAGB4_WRCLI12__URG_LOW_MASK 0x00000F00L |
8013 | #define DAGB4_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L |
8014 | #define DAGB4_WRCLI12__MAX_BW_MASK 0x001FE000L |
8015 | #define DAGB4_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L |
8016 | #define DAGB4_WRCLI12__MIN_BW_MASK 0x01C00000L |
8017 | #define DAGB4_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L |
8018 | #define DAGB4_WRCLI12__MAX_OSD_MASK 0xFC000000L |
8019 | //DAGB4_WRCLI13 |
8020 | #define DAGB4_WRCLI13__VIRT_CHAN__SHIFT 0x0 |
8021 | #define DAGB4_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 |
8022 | #define DAGB4_WRCLI13__URG_HIGH__SHIFT 0x4 |
8023 | #define DAGB4_WRCLI13__URG_LOW__SHIFT 0x8 |
8024 | #define DAGB4_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc |
8025 | #define DAGB4_WRCLI13__MAX_BW__SHIFT 0xd |
8026 | #define DAGB4_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 |
8027 | #define DAGB4_WRCLI13__MIN_BW__SHIFT 0x16 |
8028 | #define DAGB4_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 |
8029 | #define DAGB4_WRCLI13__MAX_OSD__SHIFT 0x1a |
8030 | #define DAGB4_WRCLI13__VIRT_CHAN_MASK 0x00000007L |
8031 | #define DAGB4_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L |
8032 | #define DAGB4_WRCLI13__URG_HIGH_MASK 0x000000F0L |
8033 | #define DAGB4_WRCLI13__URG_LOW_MASK 0x00000F00L |
8034 | #define DAGB4_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L |
8035 | #define DAGB4_WRCLI13__MAX_BW_MASK 0x001FE000L |
8036 | #define DAGB4_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L |
8037 | #define DAGB4_WRCLI13__MIN_BW_MASK 0x01C00000L |
8038 | #define DAGB4_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L |
8039 | #define DAGB4_WRCLI13__MAX_OSD_MASK 0xFC000000L |
8040 | //DAGB4_WRCLI14 |
8041 | #define DAGB4_WRCLI14__VIRT_CHAN__SHIFT 0x0 |
8042 | #define DAGB4_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 |
8043 | #define DAGB4_WRCLI14__URG_HIGH__SHIFT 0x4 |
8044 | #define DAGB4_WRCLI14__URG_LOW__SHIFT 0x8 |
8045 | #define DAGB4_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc |
8046 | #define DAGB4_WRCLI14__MAX_BW__SHIFT 0xd |
8047 | #define DAGB4_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 |
8048 | #define DAGB4_WRCLI14__MIN_BW__SHIFT 0x16 |
8049 | #define DAGB4_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 |
8050 | #define DAGB4_WRCLI14__MAX_OSD__SHIFT 0x1a |
8051 | #define DAGB4_WRCLI14__VIRT_CHAN_MASK 0x00000007L |
8052 | #define DAGB4_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L |
8053 | #define DAGB4_WRCLI14__URG_HIGH_MASK 0x000000F0L |
8054 | #define DAGB4_WRCLI14__URG_LOW_MASK 0x00000F00L |
8055 | #define DAGB4_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L |
8056 | #define DAGB4_WRCLI14__MAX_BW_MASK 0x001FE000L |
8057 | #define DAGB4_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L |
8058 | #define DAGB4_WRCLI14__MIN_BW_MASK 0x01C00000L |
8059 | #define DAGB4_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L |
8060 | #define DAGB4_WRCLI14__MAX_OSD_MASK 0xFC000000L |
8061 | //DAGB4_WRCLI15 |
8062 | #define DAGB4_WRCLI15__VIRT_CHAN__SHIFT 0x0 |
8063 | #define DAGB4_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 |
8064 | #define DAGB4_WRCLI15__URG_HIGH__SHIFT 0x4 |
8065 | #define DAGB4_WRCLI15__URG_LOW__SHIFT 0x8 |
8066 | #define DAGB4_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc |
8067 | #define DAGB4_WRCLI15__MAX_BW__SHIFT 0xd |
8068 | #define DAGB4_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 |
8069 | #define DAGB4_WRCLI15__MIN_BW__SHIFT 0x16 |
8070 | #define DAGB4_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 |
8071 | #define DAGB4_WRCLI15__MAX_OSD__SHIFT 0x1a |
8072 | #define DAGB4_WRCLI15__VIRT_CHAN_MASK 0x00000007L |
8073 | #define DAGB4_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L |
8074 | #define DAGB4_WRCLI15__URG_HIGH_MASK 0x000000F0L |
8075 | #define DAGB4_WRCLI15__URG_LOW_MASK 0x00000F00L |
8076 | #define DAGB4_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L |
8077 | #define DAGB4_WRCLI15__MAX_BW_MASK 0x001FE000L |
8078 | #define DAGB4_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L |
8079 | #define DAGB4_WRCLI15__MIN_BW_MASK 0x01C00000L |
8080 | #define DAGB4_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L |
8081 | #define DAGB4_WRCLI15__MAX_OSD_MASK 0xFC000000L |
8082 | //DAGB4_WR_CNTL |
8083 | #define DAGB4_WR_CNTL__SCLK_FREQ__SHIFT 0x0 |
8084 | #define DAGB4_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 |
8085 | #define DAGB4_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa |
8086 | #define DAGB4_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 |
8087 | #define DAGB4_WR_CNTL__IO_LEVEL__SHIFT 0x11 |
8088 | #define DAGB4_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 |
8089 | #define DAGB4_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 |
8090 | #define DAGB4_WR_CNTL__FIX_JUMP__SHIFT 0x1a |
8091 | #define DAGB4_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL |
8092 | #define DAGB4_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L |
8093 | #define DAGB4_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L |
8094 | #define DAGB4_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L |
8095 | #define DAGB4_WR_CNTL__IO_LEVEL_MASK 0x000E0000L |
8096 | #define DAGB4_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L |
8097 | #define DAGB4_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L |
8098 | #define DAGB4_WR_CNTL__FIX_JUMP_MASK 0x04000000L |
8099 | //DAGB4_WR_GMI_CNTL |
8100 | #define DAGB4_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 |
8101 | #define DAGB4_WR_GMI_CNTL__LEVEL__SHIFT 0x6 |
8102 | #define DAGB4_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 |
8103 | #define DAGB4_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd |
8104 | #define DAGB4_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL |
8105 | #define DAGB4_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L |
8106 | #define DAGB4_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L |
8107 | #define DAGB4_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L |
8108 | //DAGB4_WR_ADDR_DAGB |
8109 | #define DAGB4_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 |
8110 | #define DAGB4_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 |
8111 | #define DAGB4_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 |
8112 | #define DAGB4_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 |
8113 | #define DAGB4_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd |
8114 | #define DAGB4_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L |
8115 | #define DAGB4_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L |
8116 | #define DAGB4_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L |
8117 | #define DAGB4_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L |
8118 | #define DAGB4_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L |
8119 | //DAGB4_WR_OUTPUT_DAGB_MAX_BURST |
8120 | #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 |
8121 | #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 |
8122 | #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 |
8123 | #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc |
8124 | #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 |
8125 | #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 |
8126 | #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 |
8127 | #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c |
8128 | #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL |
8129 | #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L |
8130 | #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L |
8131 | #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L |
8132 | #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L |
8133 | #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L |
8134 | #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L |
8135 | #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L |
8136 | //DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER |
8137 | #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 |
8138 | #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 |
8139 | #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 |
8140 | #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc |
8141 | #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 |
8142 | #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 |
8143 | #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 |
8144 | #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c |
8145 | #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL |
8146 | #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L |
8147 | #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L |
8148 | #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L |
8149 | #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L |
8150 | #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L |
8151 | #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L |
8152 | #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L |
8153 | //DAGB4_WR_CGTT_CLK_CTRL |
8154 | #define DAGB4_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
8155 | #define DAGB4_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
8156 | #define DAGB4_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
8157 | #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
8158 | #define DAGB4_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
8159 | #define DAGB4_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
8160 | #define DAGB4_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
8161 | #define DAGB4_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
8162 | #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
8163 | #define DAGB4_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
8164 | //DAGB4_L1TLB_WR_CGTT_CLK_CTRL |
8165 | #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
8166 | #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
8167 | #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
8168 | #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
8169 | #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
8170 | #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
8171 | #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
8172 | #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
8173 | #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
8174 | #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
8175 | //DAGB4_ATCVM_WR_CGTT_CLK_CTRL |
8176 | #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
8177 | #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
8178 | #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xc |
8179 | #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1e |
8180 | #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x1f |
8181 | #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
8182 | #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
8183 | #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x0FFFF000L |
8184 | #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x40000000L |
8185 | #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0x80000000L |
8186 | //DAGB4_WR_ADDR_DAGB_MAX_BURST0 |
8187 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 |
8188 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 |
8189 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 |
8190 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc |
8191 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 |
8192 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 |
8193 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 |
8194 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c |
8195 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL |
8196 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L |
8197 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L |
8198 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L |
8199 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L |
8200 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L |
8201 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L |
8202 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L |
8203 | //DAGB4_WR_ADDR_DAGB_LAZY_TIMER0 |
8204 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 |
8205 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 |
8206 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 |
8207 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc |
8208 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 |
8209 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 |
8210 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 |
8211 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c |
8212 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL |
8213 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L |
8214 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L |
8215 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L |
8216 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L |
8217 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L |
8218 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L |
8219 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L |
8220 | //DAGB4_WR_ADDR_DAGB_MAX_BURST1 |
8221 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 |
8222 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 |
8223 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 |
8224 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc |
8225 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 |
8226 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 |
8227 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 |
8228 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c |
8229 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL |
8230 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L |
8231 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L |
8232 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L |
8233 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L |
8234 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L |
8235 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L |
8236 | #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L |
8237 | //DAGB4_WR_ADDR_DAGB_LAZY_TIMER1 |
8238 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 |
8239 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 |
8240 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 |
8241 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc |
8242 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 |
8243 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 |
8244 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 |
8245 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c |
8246 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL |
8247 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L |
8248 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L |
8249 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L |
8250 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L |
8251 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L |
8252 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L |
8253 | #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L |
8254 | //DAGB4_WR_DATA_DAGB |
8255 | #define DAGB4_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 |
8256 | #define DAGB4_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 |
8257 | #define DAGB4_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 |
8258 | #define DAGB4_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 |
8259 | #define DAGB4_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L |
8260 | #define DAGB4_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L |
8261 | #define DAGB4_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L |
8262 | #define DAGB4_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L |
8263 | //DAGB4_WR_DATA_DAGB_MAX_BURST0 |
8264 | #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 |
8265 | #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 |
8266 | #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 |
8267 | #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc |
8268 | #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 |
8269 | #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 |
8270 | #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 |
8271 | #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c |
8272 | #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL |
8273 | #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L |
8274 | #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L |
8275 | #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L |
8276 | #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L |
8277 | #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L |
8278 | #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L |
8279 | #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L |
8280 | //DAGB4_WR_DATA_DAGB_LAZY_TIMER0 |
8281 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 |
8282 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 |
8283 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 |
8284 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc |
8285 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 |
8286 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 |
8287 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 |
8288 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c |
8289 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL |
8290 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L |
8291 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L |
8292 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L |
8293 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L |
8294 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L |
8295 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L |
8296 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L |
8297 | //DAGB4_WR_DATA_DAGB_MAX_BURST1 |
8298 | #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 |
8299 | #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 |
8300 | #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 |
8301 | #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc |
8302 | #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 |
8303 | #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 |
8304 | #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 |
8305 | #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c |
8306 | #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL |
8307 | #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L |
8308 | #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L |
8309 | #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L |
8310 | #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L |
8311 | #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L |
8312 | #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L |
8313 | #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L |
8314 | //DAGB4_WR_DATA_DAGB_LAZY_TIMER1 |
8315 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 |
8316 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 |
8317 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 |
8318 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc |
8319 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 |
8320 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 |
8321 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 |
8322 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c |
8323 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL |
8324 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L |
8325 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L |
8326 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L |
8327 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L |
8328 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L |
8329 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L |
8330 | #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L |
8331 | //DAGB4_WR_VC0_CNTL |
8332 | #define DAGB4_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 |
8333 | #define DAGB4_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 |
8334 | #define DAGB4_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
8335 | #define DAGB4_WR_VC0_CNTL__MAX_BW__SHIFT 0xc |
8336 | #define DAGB4_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
8337 | #define DAGB4_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 |
8338 | #define DAGB4_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
8339 | #define DAGB4_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 |
8340 | #define DAGB4_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL |
8341 | #define DAGB4_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L |
8342 | #define DAGB4_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
8343 | #define DAGB4_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L |
8344 | #define DAGB4_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
8345 | #define DAGB4_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L |
8346 | #define DAGB4_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
8347 | #define DAGB4_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L |
8348 | //DAGB4_WR_VC1_CNTL |
8349 | #define DAGB4_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 |
8350 | #define DAGB4_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 |
8351 | #define DAGB4_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
8352 | #define DAGB4_WR_VC1_CNTL__MAX_BW__SHIFT 0xc |
8353 | #define DAGB4_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
8354 | #define DAGB4_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 |
8355 | #define DAGB4_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
8356 | #define DAGB4_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 |
8357 | #define DAGB4_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL |
8358 | #define DAGB4_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L |
8359 | #define DAGB4_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
8360 | #define DAGB4_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L |
8361 | #define DAGB4_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
8362 | #define DAGB4_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L |
8363 | #define DAGB4_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
8364 | #define DAGB4_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L |
8365 | //DAGB4_WR_VC2_CNTL |
8366 | #define DAGB4_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 |
8367 | #define DAGB4_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 |
8368 | #define DAGB4_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
8369 | #define DAGB4_WR_VC2_CNTL__MAX_BW__SHIFT 0xc |
8370 | #define DAGB4_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
8371 | #define DAGB4_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 |
8372 | #define DAGB4_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
8373 | #define DAGB4_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 |
8374 | #define DAGB4_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL |
8375 | #define DAGB4_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L |
8376 | #define DAGB4_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
8377 | #define DAGB4_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L |
8378 | #define DAGB4_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
8379 | #define DAGB4_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L |
8380 | #define DAGB4_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
8381 | #define DAGB4_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L |
8382 | //DAGB4_WR_VC3_CNTL |
8383 | #define DAGB4_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 |
8384 | #define DAGB4_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 |
8385 | #define DAGB4_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
8386 | #define DAGB4_WR_VC3_CNTL__MAX_BW__SHIFT 0xc |
8387 | #define DAGB4_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
8388 | #define DAGB4_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 |
8389 | #define DAGB4_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
8390 | #define DAGB4_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 |
8391 | #define DAGB4_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL |
8392 | #define DAGB4_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L |
8393 | #define DAGB4_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
8394 | #define DAGB4_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L |
8395 | #define DAGB4_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
8396 | #define DAGB4_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L |
8397 | #define DAGB4_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
8398 | #define DAGB4_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L |
8399 | //DAGB4_WR_VC4_CNTL |
8400 | #define DAGB4_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 |
8401 | #define DAGB4_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 |
8402 | #define DAGB4_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
8403 | #define DAGB4_WR_VC4_CNTL__MAX_BW__SHIFT 0xc |
8404 | #define DAGB4_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
8405 | #define DAGB4_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 |
8406 | #define DAGB4_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
8407 | #define DAGB4_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 |
8408 | #define DAGB4_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL |
8409 | #define DAGB4_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L |
8410 | #define DAGB4_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
8411 | #define DAGB4_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L |
8412 | #define DAGB4_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
8413 | #define DAGB4_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L |
8414 | #define DAGB4_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
8415 | #define DAGB4_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L |
8416 | //DAGB4_WR_VC5_CNTL |
8417 | #define DAGB4_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 |
8418 | #define DAGB4_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 |
8419 | #define DAGB4_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
8420 | #define DAGB4_WR_VC5_CNTL__MAX_BW__SHIFT 0xc |
8421 | #define DAGB4_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
8422 | #define DAGB4_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 |
8423 | #define DAGB4_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
8424 | #define DAGB4_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 |
8425 | #define DAGB4_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL |
8426 | #define DAGB4_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L |
8427 | #define DAGB4_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
8428 | #define DAGB4_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L |
8429 | #define DAGB4_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
8430 | #define DAGB4_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L |
8431 | #define DAGB4_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
8432 | #define DAGB4_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L |
8433 | //DAGB4_WR_VC6_CNTL |
8434 | #define DAGB4_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 |
8435 | #define DAGB4_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 |
8436 | #define DAGB4_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
8437 | #define DAGB4_WR_VC6_CNTL__MAX_BW__SHIFT 0xc |
8438 | #define DAGB4_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
8439 | #define DAGB4_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 |
8440 | #define DAGB4_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
8441 | #define DAGB4_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 |
8442 | #define DAGB4_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL |
8443 | #define DAGB4_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L |
8444 | #define DAGB4_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
8445 | #define DAGB4_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L |
8446 | #define DAGB4_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
8447 | #define DAGB4_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L |
8448 | #define DAGB4_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
8449 | #define DAGB4_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L |
8450 | //DAGB4_WR_VC7_CNTL |
8451 | #define DAGB4_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 |
8452 | #define DAGB4_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 |
8453 | #define DAGB4_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
8454 | #define DAGB4_WR_VC7_CNTL__MAX_BW__SHIFT 0xc |
8455 | #define DAGB4_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
8456 | #define DAGB4_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 |
8457 | #define DAGB4_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
8458 | #define DAGB4_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 |
8459 | #define DAGB4_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL |
8460 | #define DAGB4_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L |
8461 | #define DAGB4_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
8462 | #define DAGB4_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L |
8463 | #define DAGB4_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
8464 | #define DAGB4_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L |
8465 | #define DAGB4_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
8466 | #define DAGB4_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L |
8467 | //DAGB4_WR_CNTL_MISC |
8468 | #define DAGB4_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 |
8469 | #define DAGB4_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 |
8470 | #define DAGB4_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd |
8471 | #define DAGB4_WR_CNTL_MISC__STOR_CC_NEW_MODE__SHIFT 0x13 |
8472 | #define DAGB4_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 |
8473 | #define DAGB4_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 |
8474 | #define DAGB4_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a |
8475 | #define DAGB4_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL |
8476 | #define DAGB4_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L |
8477 | #define DAGB4_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L |
8478 | #define DAGB4_WR_CNTL_MISC__STOR_CC_NEW_MODE_MASK 0x00080000L |
8479 | #define DAGB4_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L |
8480 | #define DAGB4_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L |
8481 | #define DAGB4_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L |
8482 | //DAGB4_WR_TLB_CREDIT |
8483 | #define DAGB4_WR_TLB_CREDIT__TLB0__SHIFT 0x0 |
8484 | #define DAGB4_WR_TLB_CREDIT__TLB1__SHIFT 0x5 |
8485 | #define DAGB4_WR_TLB_CREDIT__TLB2__SHIFT 0xa |
8486 | #define DAGB4_WR_TLB_CREDIT__TLB3__SHIFT 0xf |
8487 | #define DAGB4_WR_TLB_CREDIT__TLB4__SHIFT 0x14 |
8488 | #define DAGB4_WR_TLB_CREDIT__TLB5__SHIFT 0x19 |
8489 | #define DAGB4_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL |
8490 | #define DAGB4_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L |
8491 | #define DAGB4_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L |
8492 | #define DAGB4_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L |
8493 | #define DAGB4_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L |
8494 | #define DAGB4_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L |
8495 | //DAGB4_WR_DATA_CREDIT |
8496 | #define DAGB4_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 |
8497 | #define DAGB4_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 |
8498 | #define DAGB4_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 |
8499 | #define DAGB4_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 |
8500 | #define DAGB4_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL |
8501 | #define DAGB4_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L |
8502 | #define DAGB4_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L |
8503 | #define DAGB4_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L |
8504 | //DAGB4_WR_MISC_CREDIT |
8505 | #define DAGB4_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 |
8506 | #define DAGB4_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 |
8507 | #define DAGB4_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 |
8508 | #define DAGB4_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 |
8509 | #define DAGB4_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL |
8510 | #define DAGB4_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L |
8511 | #define DAGB4_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L |
8512 | #define DAGB4_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L |
8513 | //DAGB4_WR_OSD_CREDIT_CNTL1 |
8514 | #define DAGB4_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 |
8515 | #define DAGB4_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x4 |
8516 | #define DAGB4_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0x8 |
8517 | #define DAGB4_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xc |
8518 | #define DAGB4_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT 0x10 |
8519 | #define DAGB4_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT 0x14 |
8520 | #define DAGB4_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x18 |
8521 | #define DAGB4_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000000FL |
8522 | #define DAGB4_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000000F0L |
8523 | #define DAGB4_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00000F00L |
8524 | #define DAGB4_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK 0x0000F000L |
8525 | #define DAGB4_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK 0x000F0000L |
8526 | #define DAGB4_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK 0x00F00000L |
8527 | #define DAGB4_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK 0x3F000000L |
8528 | //DAGB4_WR_OSD_CREDIT_CNTL2 |
8529 | #define DAGB4_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT 0x0 |
8530 | #define DAGB4_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT 0x4 |
8531 | #define DAGB4_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK 0x0000000FL |
8532 | #define DAGB4_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK 0x00000010L |
8533 | //DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1 |
8534 | #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 |
8535 | #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 |
8536 | #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa |
8537 | #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf |
8538 | #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 |
8539 | #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19 |
8540 | #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a |
8541 | #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b |
8542 | #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT 0x1c |
8543 | #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT 0x1d |
8544 | #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL |
8545 | #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L |
8546 | #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L |
8547 | #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L |
8548 | #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L |
8549 | #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L |
8550 | #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L |
8551 | #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L |
8552 | #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK 0x10000000L |
8553 | #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK 0x20000000L |
8554 | //DAGB4_WRCLI_GPU_SNOOP_OVERRIDE |
8555 | #define DAGB4_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 |
8556 | #define DAGB4_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0x0000FFFFL |
8557 | //DAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE |
8558 | #define DAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 |
8559 | #define DAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0x0000FFFFL |
8560 | //DAGB4_WRCLI_ASK_PENDING |
8561 | #define DAGB4_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 |
8562 | #define DAGB4_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL |
8563 | //DAGB4_WRCLI_GO_PENDING |
8564 | #define DAGB4_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 |
8565 | #define DAGB4_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL |
8566 | //DAGB4_WRCLI_GBLSEND_PENDING |
8567 | #define DAGB4_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 |
8568 | #define DAGB4_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL |
8569 | //DAGB4_WRCLI_TLB_PENDING |
8570 | #define DAGB4_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 |
8571 | #define DAGB4_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL |
8572 | //DAGB4_WRCLI_OARB_PENDING |
8573 | #define DAGB4_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 |
8574 | #define DAGB4_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL |
8575 | //DAGB4_WRCLI_OSD_PENDING |
8576 | #define DAGB4_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 |
8577 | #define DAGB4_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL |
8578 | //DAGB4_WRCLI_DBUS_ASK_PENDING |
8579 | #define DAGB4_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 |
8580 | #define DAGB4_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL |
8581 | //DAGB4_WRCLI_DBUS_GO_PENDING |
8582 | #define DAGB4_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 |
8583 | #define DAGB4_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL |
8584 | //DAGB4_DAGB_DLY |
8585 | #define DAGB4_DAGB_DLY__DLY__SHIFT 0x0 |
8586 | #define DAGB4_DAGB_DLY__CLI__SHIFT 0x8 |
8587 | #define DAGB4_DAGB_DLY__POS__SHIFT 0x10 |
8588 | #define DAGB4_DAGB_DLY__DLY_MASK 0x000000FFL |
8589 | #define DAGB4_DAGB_DLY__CLI_MASK 0x0000FF00L |
8590 | #define DAGB4_DAGB_DLY__POS_MASK 0x000F0000L |
8591 | //DAGB4_CNTL_MISC |
8592 | #define DAGB4_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 |
8593 | #define DAGB4_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 |
8594 | #define DAGB4_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 |
8595 | #define DAGB4_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 |
8596 | #define DAGB4_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc |
8597 | #define DAGB4_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf |
8598 | #define DAGB4_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 |
8599 | #define DAGB4_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 |
8600 | #define DAGB4_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 |
8601 | #define DAGB4_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e |
8602 | #define DAGB4_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L |
8603 | #define DAGB4_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L |
8604 | #define DAGB4_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L |
8605 | #define DAGB4_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L |
8606 | #define DAGB4_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L |
8607 | #define DAGB4_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L |
8608 | #define DAGB4_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L |
8609 | #define DAGB4_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L |
8610 | #define DAGB4_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L |
8611 | #define DAGB4_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L |
8612 | //DAGB4_CNTL_MISC2 |
8613 | #define DAGB4_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 |
8614 | #define DAGB4_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 |
8615 | #define DAGB4_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 |
8616 | #define DAGB4_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 |
8617 | #define DAGB4_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 |
8618 | #define DAGB4_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 |
8619 | #define DAGB4_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 |
8620 | #define DAGB4_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 |
8621 | #define DAGB4_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 |
8622 | #define DAGB4_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 |
8623 | #define DAGB4_CNTL_MISC2__SWAP_CTL__SHIFT 0xa |
8624 | #define DAGB4_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb |
8625 | #define DAGB4_CNTL_MISC2__HDP_CID__SHIFT 0xc |
8626 | #define DAGB4_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x10 |
8627 | #define DAGB4_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L |
8628 | #define DAGB4_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L |
8629 | #define DAGB4_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L |
8630 | #define DAGB4_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L |
8631 | #define DAGB4_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L |
8632 | #define DAGB4_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L |
8633 | #define DAGB4_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L |
8634 | #define DAGB4_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L |
8635 | #define DAGB4_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L |
8636 | #define DAGB4_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L |
8637 | #define DAGB4_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L |
8638 | #define DAGB4_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L |
8639 | #define DAGB4_CNTL_MISC2__HDP_CID_MASK 0x0000F000L |
8640 | #define DAGB4_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x003F0000L |
8641 | //DAGB4_FATAL_ERROR_CNTL |
8642 | #define DAGB4_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0 |
8643 | #define DAGB4_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL |
8644 | //DAGB4_FATAL_ERROR_CLEAR |
8645 | #define DAGB4_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0 |
8646 | #define DAGB4_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L |
8647 | //DAGB4_FATAL_ERROR_STATUS0 |
8648 | #define DAGB4_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0 |
8649 | #define DAGB4_FATAL_ERROR_STATUS0__CID__SHIFT 0x1 |
8650 | #define DAGB4_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6 |
8651 | #define DAGB4_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L |
8652 | #define DAGB4_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL |
8653 | #define DAGB4_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L |
8654 | //DAGB4_FATAL_ERROR_STATUS1 |
8655 | #define DAGB4_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0 |
8656 | #define DAGB4_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL |
8657 | //DAGB4_FATAL_ERROR_STATUS2 |
8658 | #define DAGB4_FATAL_ERROR_STATUS2__TAG__SHIFT 0x0 |
8659 | #define DAGB4_FATAL_ERROR_STATUS2__VFID__SHIFT 0x10 |
8660 | #define DAGB4_FATAL_ERROR_STATUS2__VF__SHIFT 0x14 |
8661 | #define DAGB4_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x15 |
8662 | #define DAGB4_FATAL_ERROR_STATUS2__IO__SHIFT 0x16 |
8663 | #define DAGB4_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x17 |
8664 | #define DAGB4_FATAL_ERROR_STATUS2__DBGMSK__SHIFT 0x18 |
8665 | #define DAGB4_FATAL_ERROR_STATUS2__FED__SHIFT 0x19 |
8666 | #define DAGB4_FATAL_ERROR_STATUS2__TAG_MASK 0x0000FFFFL |
8667 | #define DAGB4_FATAL_ERROR_STATUS2__VFID_MASK 0x000F0000L |
8668 | #define DAGB4_FATAL_ERROR_STATUS2__VF_MASK 0x00100000L |
8669 | #define DAGB4_FATAL_ERROR_STATUS2__SPACE_MASK 0x00200000L |
8670 | #define DAGB4_FATAL_ERROR_STATUS2__IO_MASK 0x00400000L |
8671 | #define DAGB4_FATAL_ERROR_STATUS2__SIZE_MASK 0x00800000L |
8672 | #define DAGB4_FATAL_ERROR_STATUS2__DBGMSK_MASK 0x01000000L |
8673 | #define DAGB4_FATAL_ERROR_STATUS2__FED_MASK 0x02000000L |
8674 | //DAGB4_FATAL_ERROR_STATUS3 |
8675 | #define DAGB4_FATAL_ERROR_STATUS3__NOALLOC__SHIFT 0x0 |
8676 | #define DAGB4_FATAL_ERROR_STATUS3__UNITID__SHIFT 0x1 |
8677 | #define DAGB4_FATAL_ERROR_STATUS3__OP__SHIFT 0x7 |
8678 | #define DAGB4_FATAL_ERROR_STATUS3__SECLEVEL__SHIFT 0xe |
8679 | #define DAGB4_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x11 |
8680 | #define DAGB4_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x12 |
8681 | #define DAGB4_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x13 |
8682 | #define DAGB4_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x14 |
8683 | #define DAGB4_FATAL_ERROR_STATUS3__NACK__SHIFT 0x15 |
8684 | #define DAGB4_FATAL_ERROR_STATUS3__RO__SHIFT 0x17 |
8685 | #define DAGB4_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x18 |
8686 | #define DAGB4_FATAL_ERROR_STATUS3__EOP__SHIFT 0x19 |
8687 | #define DAGB4_FATAL_ERROR_STATUS3__NOALLOC_MASK 0x00000001L |
8688 | #define DAGB4_FATAL_ERROR_STATUS3__UNITID_MASK 0x0000007EL |
8689 | #define DAGB4_FATAL_ERROR_STATUS3__OP_MASK 0x00003F80L |
8690 | #define DAGB4_FATAL_ERROR_STATUS3__SECLEVEL_MASK 0x0001C000L |
8691 | #define DAGB4_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00020000L |
8692 | #define DAGB4_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00040000L |
8693 | #define DAGB4_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00080000L |
8694 | #define DAGB4_FATAL_ERROR_STATUS3__INVAL_MASK 0x00100000L |
8695 | #define DAGB4_FATAL_ERROR_STATUS3__NACK_MASK 0x00600000L |
8696 | #define DAGB4_FATAL_ERROR_STATUS3__RO_MASK 0x00800000L |
8697 | #define DAGB4_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x01000000L |
8698 | #define DAGB4_FATAL_ERROR_STATUS3__EOP_MASK 0x02000000L |
8699 | //DAGB4_FIFO_EMPTY |
8700 | #define DAGB4_FIFO_EMPTY__EMPTY__SHIFT 0x0 |
8701 | #define DAGB4_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL |
8702 | //DAGB4_FIFO_FULL |
8703 | #define DAGB4_FIFO_FULL__FULL__SHIFT 0x0 |
8704 | #define DAGB4_FIFO_FULL__FULL_MASK 0x007FFFFFL |
8705 | //DAGB4_WR_CREDITS_FULL |
8706 | #define DAGB4_WR_CREDITS_FULL__FULL__SHIFT 0x0 |
8707 | #define DAGB4_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL |
8708 | //DAGB4_RD_CREDITS_FULL |
8709 | #define DAGB4_RD_CREDITS_FULL__FULL__SHIFT 0x0 |
8710 | #define DAGB4_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL |
8711 | //DAGB4_PERFCOUNTER_LO |
8712 | #define DAGB4_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
8713 | #define DAGB4_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
8714 | //DAGB4_PERFCOUNTER_HI |
8715 | #define DAGB4_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
8716 | #define DAGB4_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
8717 | #define DAGB4_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
8718 | #define DAGB4_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
8719 | //DAGB4_PERFCOUNTER0_CFG |
8720 | #define DAGB4_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
8721 | #define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
8722 | #define DAGB4_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
8723 | #define DAGB4_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
8724 | #define DAGB4_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
8725 | #define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
8726 | #define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
8727 | #define DAGB4_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
8728 | #define DAGB4_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
8729 | #define DAGB4_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
8730 | //DAGB4_PERFCOUNTER1_CFG |
8731 | #define DAGB4_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
8732 | #define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
8733 | #define DAGB4_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
8734 | #define DAGB4_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
8735 | #define DAGB4_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
8736 | #define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
8737 | #define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
8738 | #define DAGB4_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
8739 | #define DAGB4_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
8740 | #define DAGB4_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
8741 | //DAGB4_PERFCOUNTER2_CFG |
8742 | #define DAGB4_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 |
8743 | #define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 |
8744 | #define DAGB4_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 |
8745 | #define DAGB4_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c |
8746 | #define DAGB4_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d |
8747 | #define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL |
8748 | #define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L |
8749 | #define DAGB4_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L |
8750 | #define DAGB4_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L |
8751 | #define DAGB4_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L |
8752 | //DAGB4_PERFCOUNTER_RSLT_CNTL |
8753 | #define DAGB4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
8754 | #define DAGB4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
8755 | #define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
8756 | #define DAGB4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
8757 | #define DAGB4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
8758 | #define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
8759 | #define DAGB4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
8760 | #define DAGB4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
8761 | #define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
8762 | #define DAGB4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
8763 | #define DAGB4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
8764 | #define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
8765 | //DAGB4_L1TLB_REG_RW |
8766 | #define DAGB4_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 |
8767 | #define DAGB4_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 |
8768 | #define DAGB4_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT 0x2 |
8769 | #define DAGB4_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT 0x4 |
8770 | #define DAGB4_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT 0x5 |
8771 | #define DAGB4_L1TLB_REG_RW__RESERVE__SHIFT 0x6 |
8772 | #define DAGB4_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L |
8773 | #define DAGB4_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L |
8774 | #define DAGB4_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK 0x00000004L |
8775 | #define DAGB4_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK 0x00000010L |
8776 | #define DAGB4_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK 0x00000020L |
8777 | #define DAGB4_L1TLB_REG_RW__RESERVE_MASK 0xFFFFFFC0L |
8778 | |
8779 | |
8780 | // addressBlock: aid_mmhub_ea_mmeadec0 |
8781 | //MMEA0_DRAM_RD_CLI2GRP_MAP0 |
8782 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
8783 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
8784 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
8785 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
8786 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
8787 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
8788 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
8789 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
8790 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
8791 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
8792 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
8793 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
8794 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
8795 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
8796 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
8797 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
8798 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
8799 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
8800 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
8801 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
8802 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
8803 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
8804 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
8805 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
8806 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
8807 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
8808 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
8809 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
8810 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
8811 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
8812 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
8813 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
8814 | //MMEA0_DRAM_RD_CLI2GRP_MAP1 |
8815 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
8816 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
8817 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
8818 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
8819 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
8820 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
8821 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
8822 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
8823 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
8824 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
8825 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
8826 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
8827 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
8828 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
8829 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
8830 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
8831 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
8832 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
8833 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
8834 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
8835 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
8836 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
8837 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
8838 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
8839 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
8840 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
8841 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
8842 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
8843 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
8844 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
8845 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
8846 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
8847 | //MMEA0_DRAM_WR_CLI2GRP_MAP0 |
8848 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
8849 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
8850 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
8851 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
8852 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
8853 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
8854 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
8855 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
8856 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
8857 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
8858 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
8859 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
8860 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
8861 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
8862 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
8863 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
8864 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
8865 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
8866 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
8867 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
8868 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
8869 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
8870 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
8871 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
8872 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
8873 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
8874 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
8875 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
8876 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
8877 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
8878 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
8879 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
8880 | //MMEA0_DRAM_WR_CLI2GRP_MAP1 |
8881 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
8882 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
8883 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
8884 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
8885 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
8886 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
8887 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
8888 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
8889 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
8890 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
8891 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
8892 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
8893 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
8894 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
8895 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
8896 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
8897 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
8898 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
8899 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
8900 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
8901 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
8902 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
8903 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
8904 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
8905 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
8906 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
8907 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
8908 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
8909 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
8910 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
8911 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
8912 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
8913 | //MMEA0_DRAM_RD_GRP2VC_MAP |
8914 | #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
8915 | #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
8916 | #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
8917 | #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
8918 | #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
8919 | #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
8920 | #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
8921 | #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
8922 | //MMEA0_DRAM_WR_GRP2VC_MAP |
8923 | #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
8924 | #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
8925 | #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
8926 | #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
8927 | #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
8928 | #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
8929 | #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
8930 | #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
8931 | //MMEA0_DRAM_RD_LAZY |
8932 | #define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 |
8933 | #define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 |
8934 | #define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 |
8935 | #define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 |
8936 | #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
8937 | #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
8938 | #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
8939 | #define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L |
8940 | #define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L |
8941 | #define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
8942 | #define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
8943 | #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
8944 | #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
8945 | #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
8946 | //MMEA0_DRAM_WR_LAZY |
8947 | #define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 |
8948 | #define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 |
8949 | #define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 |
8950 | #define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 |
8951 | #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
8952 | #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
8953 | #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
8954 | #define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L |
8955 | #define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L |
8956 | #define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
8957 | #define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
8958 | #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
8959 | #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
8960 | #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
8961 | //MMEA0_DRAM_RD_CAM_CNTL |
8962 | #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
8963 | #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
8964 | #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
8965 | #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
8966 | #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
8967 | #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
8968 | #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
8969 | #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
8970 | #define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
8971 | #define MMEA0_DRAM_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d |
8972 | #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
8973 | #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
8974 | #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
8975 | #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
8976 | #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
8977 | #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
8978 | #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
8979 | #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
8980 | #define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
8981 | #define MMEA0_DRAM_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L |
8982 | //MMEA0_DRAM_WR_CAM_CNTL |
8983 | #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
8984 | #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
8985 | #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
8986 | #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
8987 | #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
8988 | #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
8989 | #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
8990 | #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
8991 | #define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
8992 | #define MMEA0_DRAM_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d |
8993 | #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
8994 | #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
8995 | #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
8996 | #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
8997 | #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
8998 | #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
8999 | #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
9000 | #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
9001 | #define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
9002 | #define MMEA0_DRAM_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L |
9003 | //MMEA0_DRAM_PAGE_BURST |
9004 | #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 |
9005 | #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 |
9006 | #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 |
9007 | #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 |
9008 | #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
9009 | #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
9010 | #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
9011 | #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
9012 | //MMEA0_DRAM_RD_PRI_AGE |
9013 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
9014 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
9015 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
9016 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
9017 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
9018 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
9019 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
9020 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
9021 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
9022 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
9023 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
9024 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
9025 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
9026 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
9027 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
9028 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
9029 | //MMEA0_DRAM_WR_PRI_AGE |
9030 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
9031 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
9032 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
9033 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
9034 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
9035 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
9036 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
9037 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
9038 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
9039 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
9040 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
9041 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
9042 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
9043 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
9044 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
9045 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
9046 | //MMEA0_DRAM_RD_PRI_QUEUING |
9047 | #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
9048 | #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
9049 | #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
9050 | #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
9051 | #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
9052 | #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
9053 | #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
9054 | #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
9055 | //MMEA0_DRAM_WR_PRI_QUEUING |
9056 | #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
9057 | #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
9058 | #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
9059 | #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
9060 | #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
9061 | #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
9062 | #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
9063 | #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
9064 | //MMEA0_DRAM_RD_PRI_FIXED |
9065 | #define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
9066 | #define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
9067 | #define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
9068 | #define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
9069 | #define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
9070 | #define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
9071 | #define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
9072 | #define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
9073 | //MMEA0_DRAM_WR_PRI_FIXED |
9074 | #define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
9075 | #define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
9076 | #define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
9077 | #define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
9078 | #define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
9079 | #define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
9080 | #define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
9081 | #define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
9082 | //MMEA0_DRAM_RD_PRI_URGENCY |
9083 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
9084 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
9085 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
9086 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
9087 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
9088 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
9089 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
9090 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
9091 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
9092 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
9093 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
9094 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
9095 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
9096 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
9097 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
9098 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
9099 | //MMEA0_DRAM_WR_PRI_URGENCY |
9100 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
9101 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
9102 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
9103 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
9104 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
9105 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
9106 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
9107 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
9108 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
9109 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
9110 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
9111 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
9112 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
9113 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
9114 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
9115 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
9116 | //MMEA0_DRAM_RD_PRI_QUANT_PRI1 |
9117 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
9118 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
9119 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
9120 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
9121 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
9122 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
9123 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
9124 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
9125 | //MMEA0_DRAM_RD_PRI_QUANT_PRI2 |
9126 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
9127 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
9128 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
9129 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
9130 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
9131 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
9132 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
9133 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
9134 | //MMEA0_DRAM_RD_PRI_QUANT_PRI3 |
9135 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
9136 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
9137 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
9138 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
9139 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
9140 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
9141 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
9142 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
9143 | //MMEA0_DRAM_WR_PRI_QUANT_PRI1 |
9144 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
9145 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
9146 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
9147 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
9148 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
9149 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
9150 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
9151 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
9152 | //MMEA0_DRAM_WR_PRI_QUANT_PRI2 |
9153 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
9154 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
9155 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
9156 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
9157 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
9158 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
9159 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
9160 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
9161 | //MMEA0_DRAM_WR_PRI_QUANT_PRI3 |
9162 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
9163 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
9164 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
9165 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
9166 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
9167 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
9168 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
9169 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
9170 | //MMEA0_GMI_RD_CLI2GRP_MAP0 |
9171 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
9172 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
9173 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
9174 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
9175 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
9176 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
9177 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
9178 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
9179 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
9180 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
9181 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
9182 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
9183 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
9184 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
9185 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
9186 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
9187 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
9188 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
9189 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
9190 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
9191 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
9192 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
9193 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
9194 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
9195 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
9196 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
9197 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
9198 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
9199 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
9200 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
9201 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
9202 | #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
9203 | //MMEA0_GMI_RD_CLI2GRP_MAP1 |
9204 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
9205 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
9206 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
9207 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
9208 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
9209 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
9210 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
9211 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
9212 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
9213 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
9214 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
9215 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
9216 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
9217 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
9218 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
9219 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
9220 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
9221 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
9222 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
9223 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
9224 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
9225 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
9226 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
9227 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
9228 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
9229 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
9230 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
9231 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
9232 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
9233 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
9234 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
9235 | #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
9236 | //MMEA0_GMI_WR_CLI2GRP_MAP0 |
9237 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
9238 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
9239 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
9240 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
9241 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
9242 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
9243 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
9244 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
9245 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
9246 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
9247 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
9248 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
9249 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
9250 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
9251 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
9252 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
9253 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
9254 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
9255 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
9256 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
9257 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
9258 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
9259 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
9260 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
9261 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
9262 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
9263 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
9264 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
9265 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
9266 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
9267 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
9268 | #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
9269 | //MMEA0_GMI_WR_CLI2GRP_MAP1 |
9270 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
9271 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
9272 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
9273 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
9274 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
9275 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
9276 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
9277 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
9278 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
9279 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
9280 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
9281 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
9282 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
9283 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
9284 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
9285 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
9286 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
9287 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
9288 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
9289 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
9290 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
9291 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
9292 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
9293 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
9294 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
9295 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
9296 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
9297 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
9298 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
9299 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
9300 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
9301 | #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
9302 | //MMEA0_GMI_RD_GRP2VC_MAP |
9303 | #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
9304 | #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
9305 | #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
9306 | #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
9307 | #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
9308 | #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
9309 | #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
9310 | #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
9311 | //MMEA0_GMI_WR_GRP2VC_MAP |
9312 | #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
9313 | #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
9314 | #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
9315 | #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
9316 | #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
9317 | #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
9318 | #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
9319 | #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
9320 | //MMEA0_GMI_RD_LAZY |
9321 | #define MMEA0_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 |
9322 | #define MMEA0_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 |
9323 | #define MMEA0_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 |
9324 | #define MMEA0_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 |
9325 | #define MMEA0_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
9326 | #define MMEA0_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
9327 | #define MMEA0_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
9328 | #define MMEA0_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L |
9329 | #define MMEA0_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L |
9330 | #define MMEA0_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
9331 | #define MMEA0_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
9332 | #define MMEA0_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
9333 | #define MMEA0_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
9334 | #define MMEA0_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
9335 | //MMEA0_GMI_WR_LAZY |
9336 | #define MMEA0_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 |
9337 | #define MMEA0_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 |
9338 | #define MMEA0_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 |
9339 | #define MMEA0_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 |
9340 | #define MMEA0_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
9341 | #define MMEA0_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
9342 | #define MMEA0_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
9343 | #define MMEA0_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L |
9344 | #define MMEA0_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L |
9345 | #define MMEA0_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
9346 | #define MMEA0_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
9347 | #define MMEA0_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
9348 | #define MMEA0_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
9349 | #define MMEA0_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
9350 | //MMEA0_GMI_RD_CAM_CNTL |
9351 | #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
9352 | #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
9353 | #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
9354 | #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
9355 | #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
9356 | #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
9357 | #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
9358 | #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
9359 | #define MMEA0_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
9360 | #define MMEA0_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d |
9361 | #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
9362 | #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
9363 | #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
9364 | #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
9365 | #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
9366 | #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
9367 | #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
9368 | #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
9369 | #define MMEA0_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
9370 | #define MMEA0_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L |
9371 | //MMEA0_GMI_WR_CAM_CNTL |
9372 | #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
9373 | #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
9374 | #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
9375 | #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
9376 | #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
9377 | #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
9378 | #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
9379 | #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
9380 | #define MMEA0_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
9381 | #define MMEA0_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d |
9382 | #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
9383 | #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
9384 | #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
9385 | #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
9386 | #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
9387 | #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
9388 | #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
9389 | #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
9390 | #define MMEA0_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
9391 | #define MMEA0_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L |
9392 | //MMEA0_GMI_PAGE_BURST |
9393 | #define MMEA0_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 |
9394 | #define MMEA0_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 |
9395 | #define MMEA0_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 |
9396 | #define MMEA0_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 |
9397 | #define MMEA0_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
9398 | #define MMEA0_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
9399 | #define MMEA0_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
9400 | #define MMEA0_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
9401 | //MMEA0_GMI_RD_PRI_AGE |
9402 | #define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
9403 | #define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
9404 | #define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
9405 | #define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
9406 | #define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
9407 | #define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
9408 | #define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
9409 | #define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
9410 | #define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
9411 | #define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
9412 | #define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
9413 | #define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
9414 | #define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
9415 | #define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
9416 | #define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
9417 | #define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
9418 | //MMEA0_GMI_WR_PRI_AGE |
9419 | #define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
9420 | #define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
9421 | #define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
9422 | #define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
9423 | #define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
9424 | #define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
9425 | #define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
9426 | #define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
9427 | #define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
9428 | #define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
9429 | #define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
9430 | #define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
9431 | #define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
9432 | #define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
9433 | #define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
9434 | #define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
9435 | //MMEA0_GMI_RD_PRI_QUEUING |
9436 | #define MMEA0_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
9437 | #define MMEA0_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
9438 | #define MMEA0_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
9439 | #define MMEA0_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
9440 | #define MMEA0_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
9441 | #define MMEA0_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
9442 | #define MMEA0_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
9443 | #define MMEA0_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
9444 | //MMEA0_GMI_WR_PRI_QUEUING |
9445 | #define MMEA0_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
9446 | #define MMEA0_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
9447 | #define MMEA0_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
9448 | #define MMEA0_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
9449 | #define MMEA0_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
9450 | #define MMEA0_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
9451 | #define MMEA0_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
9452 | #define MMEA0_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
9453 | //MMEA0_GMI_RD_PRI_FIXED |
9454 | #define MMEA0_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
9455 | #define MMEA0_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
9456 | #define MMEA0_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
9457 | #define MMEA0_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
9458 | #define MMEA0_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
9459 | #define MMEA0_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
9460 | #define MMEA0_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
9461 | #define MMEA0_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
9462 | //MMEA0_GMI_WR_PRI_FIXED |
9463 | #define MMEA0_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
9464 | #define MMEA0_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
9465 | #define MMEA0_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
9466 | #define MMEA0_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
9467 | #define MMEA0_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
9468 | #define MMEA0_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
9469 | #define MMEA0_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
9470 | #define MMEA0_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
9471 | //MMEA0_GMI_RD_PRI_URGENCY |
9472 | #define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
9473 | #define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
9474 | #define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
9475 | #define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
9476 | #define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
9477 | #define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
9478 | #define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
9479 | #define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
9480 | #define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
9481 | #define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
9482 | #define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
9483 | #define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
9484 | #define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
9485 | #define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
9486 | #define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
9487 | #define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
9488 | //MMEA0_GMI_WR_PRI_URGENCY |
9489 | #define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
9490 | #define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
9491 | #define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
9492 | #define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
9493 | #define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
9494 | #define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
9495 | #define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
9496 | #define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
9497 | #define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
9498 | #define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
9499 | #define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
9500 | #define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
9501 | #define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
9502 | #define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
9503 | #define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
9504 | #define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
9505 | //MMEA0_GMI_RD_PRI_URGENCY_MASKING |
9506 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
9507 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
9508 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
9509 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
9510 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
9511 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
9512 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
9513 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
9514 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
9515 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
9516 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
9517 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
9518 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
9519 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
9520 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
9521 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
9522 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
9523 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
9524 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
9525 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
9526 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
9527 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
9528 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
9529 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
9530 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
9531 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
9532 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
9533 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
9534 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
9535 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
9536 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
9537 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
9538 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
9539 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
9540 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
9541 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
9542 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
9543 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
9544 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
9545 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
9546 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
9547 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
9548 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
9549 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
9550 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
9551 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
9552 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
9553 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
9554 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
9555 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
9556 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
9557 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
9558 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
9559 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
9560 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
9561 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
9562 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
9563 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
9564 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
9565 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
9566 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
9567 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
9568 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
9569 | #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
9570 | //MMEA0_GMI_WR_PRI_URGENCY_MASKING |
9571 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
9572 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
9573 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
9574 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
9575 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
9576 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
9577 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
9578 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
9579 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
9580 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
9581 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
9582 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
9583 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
9584 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
9585 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
9586 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
9587 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
9588 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
9589 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
9590 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
9591 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
9592 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
9593 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
9594 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
9595 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
9596 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
9597 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
9598 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
9599 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
9600 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
9601 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
9602 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
9603 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
9604 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
9605 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
9606 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
9607 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
9608 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
9609 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
9610 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
9611 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
9612 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
9613 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
9614 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
9615 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
9616 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
9617 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
9618 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
9619 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
9620 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
9621 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
9622 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
9623 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
9624 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
9625 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
9626 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
9627 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
9628 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
9629 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
9630 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
9631 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
9632 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
9633 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
9634 | #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
9635 | //MMEA0_GMI_RD_PRI_QUANT_PRI1 |
9636 | #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
9637 | #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
9638 | #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
9639 | #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
9640 | #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
9641 | #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
9642 | #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
9643 | #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
9644 | //MMEA0_GMI_RD_PRI_QUANT_PRI2 |
9645 | #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
9646 | #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
9647 | #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
9648 | #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
9649 | #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
9650 | #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
9651 | #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
9652 | #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
9653 | //MMEA0_GMI_RD_PRI_QUANT_PRI3 |
9654 | #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
9655 | #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
9656 | #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
9657 | #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
9658 | #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
9659 | #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
9660 | #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
9661 | #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
9662 | //MMEA0_GMI_WR_PRI_QUANT_PRI1 |
9663 | #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
9664 | #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
9665 | #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
9666 | #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
9667 | #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
9668 | #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
9669 | #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
9670 | #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
9671 | //MMEA0_GMI_WR_PRI_QUANT_PRI2 |
9672 | #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
9673 | #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
9674 | #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
9675 | #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
9676 | #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
9677 | #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
9678 | #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
9679 | #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
9680 | //MMEA0_GMI_WR_PRI_QUANT_PRI3 |
9681 | #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
9682 | #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
9683 | #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
9684 | #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
9685 | #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
9686 | #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
9687 | #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
9688 | #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
9689 | //MMEA0_IO_RD_CLI2GRP_MAP0 |
9690 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
9691 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
9692 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
9693 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
9694 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
9695 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
9696 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
9697 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
9698 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
9699 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
9700 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
9701 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
9702 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
9703 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
9704 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
9705 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
9706 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
9707 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
9708 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
9709 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
9710 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
9711 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
9712 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
9713 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
9714 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
9715 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
9716 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
9717 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
9718 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
9719 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
9720 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
9721 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
9722 | //MMEA0_IO_RD_CLI2GRP_MAP1 |
9723 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
9724 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
9725 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
9726 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
9727 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
9728 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
9729 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
9730 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
9731 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
9732 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
9733 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
9734 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
9735 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
9736 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
9737 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
9738 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
9739 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
9740 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
9741 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
9742 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
9743 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
9744 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
9745 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
9746 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
9747 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
9748 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
9749 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
9750 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
9751 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
9752 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
9753 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
9754 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
9755 | //MMEA0_IO_WR_CLI2GRP_MAP0 |
9756 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
9757 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
9758 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
9759 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
9760 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
9761 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
9762 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
9763 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
9764 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
9765 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
9766 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
9767 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
9768 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
9769 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
9770 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
9771 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
9772 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
9773 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
9774 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
9775 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
9776 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
9777 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
9778 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
9779 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
9780 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
9781 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
9782 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
9783 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
9784 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
9785 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
9786 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
9787 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
9788 | //MMEA0_IO_WR_CLI2GRP_MAP1 |
9789 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
9790 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
9791 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
9792 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
9793 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
9794 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
9795 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
9796 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
9797 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
9798 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
9799 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
9800 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
9801 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
9802 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
9803 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
9804 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
9805 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
9806 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
9807 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
9808 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
9809 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
9810 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
9811 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
9812 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
9813 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
9814 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
9815 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
9816 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
9817 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
9818 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
9819 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
9820 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
9821 | //MMEA0_IO_RD_COMBINE_FLUSH |
9822 | #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
9823 | #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
9824 | #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
9825 | #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
9826 | #define MMEA0_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 |
9827 | #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
9828 | #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
9829 | #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
9830 | #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
9831 | #define MMEA0_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L |
9832 | //MMEA0_IO_WR_COMBINE_FLUSH |
9833 | #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
9834 | #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
9835 | #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
9836 | #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
9837 | #define MMEA0_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 |
9838 | #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
9839 | #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
9840 | #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
9841 | #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
9842 | #define MMEA0_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L |
9843 | //MMEA0_IO_GROUP_BURST |
9844 | #define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 |
9845 | #define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 |
9846 | #define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 |
9847 | #define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 |
9848 | #define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
9849 | #define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
9850 | #define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
9851 | #define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
9852 | //MMEA0_IO_RD_PRI_AGE |
9853 | #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
9854 | #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
9855 | #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
9856 | #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
9857 | #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
9858 | #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
9859 | #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
9860 | #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
9861 | #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
9862 | #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
9863 | #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
9864 | #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
9865 | #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
9866 | #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
9867 | #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
9868 | #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
9869 | //MMEA0_IO_WR_PRI_AGE |
9870 | #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
9871 | #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
9872 | #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
9873 | #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
9874 | #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
9875 | #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
9876 | #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
9877 | #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
9878 | #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
9879 | #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
9880 | #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
9881 | #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
9882 | #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
9883 | #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
9884 | #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
9885 | #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
9886 | //MMEA0_IO_RD_PRI_QUEUING |
9887 | #define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
9888 | #define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
9889 | #define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
9890 | #define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
9891 | #define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
9892 | #define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
9893 | #define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
9894 | #define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
9895 | //MMEA0_IO_WR_PRI_QUEUING |
9896 | #define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
9897 | #define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
9898 | #define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
9899 | #define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
9900 | #define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
9901 | #define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
9902 | #define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
9903 | #define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
9904 | //MMEA0_IO_RD_PRI_FIXED |
9905 | #define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
9906 | #define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
9907 | #define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
9908 | #define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
9909 | #define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
9910 | #define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
9911 | #define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
9912 | #define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
9913 | //MMEA0_IO_WR_PRI_FIXED |
9914 | #define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
9915 | #define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
9916 | #define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
9917 | #define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
9918 | #define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
9919 | #define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
9920 | #define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
9921 | #define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
9922 | //MMEA0_IO_RD_PRI_URGENCY |
9923 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
9924 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
9925 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
9926 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
9927 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
9928 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
9929 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
9930 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
9931 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
9932 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
9933 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
9934 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
9935 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
9936 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
9937 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
9938 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
9939 | //MMEA0_IO_WR_PRI_URGENCY |
9940 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
9941 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
9942 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
9943 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
9944 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
9945 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
9946 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
9947 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
9948 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
9949 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
9950 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
9951 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
9952 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
9953 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
9954 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
9955 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
9956 | //MMEA0_IO_RD_PRI_URGENCY_MASKING |
9957 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
9958 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
9959 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
9960 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
9961 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
9962 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
9963 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
9964 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
9965 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
9966 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
9967 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
9968 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
9969 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
9970 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
9971 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
9972 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
9973 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
9974 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
9975 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
9976 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
9977 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
9978 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
9979 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
9980 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
9981 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
9982 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
9983 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
9984 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
9985 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
9986 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
9987 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
9988 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
9989 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
9990 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
9991 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
9992 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
9993 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
9994 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
9995 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
9996 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
9997 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
9998 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
9999 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
10000 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
10001 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
10002 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
10003 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
10004 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
10005 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
10006 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
10007 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
10008 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
10009 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
10010 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
10011 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
10012 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
10013 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
10014 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
10015 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
10016 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
10017 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
10018 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
10019 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
10020 | #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
10021 | //MMEA0_IO_WR_PRI_URGENCY_MASKING |
10022 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
10023 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
10024 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
10025 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
10026 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
10027 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
10028 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
10029 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
10030 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
10031 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
10032 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
10033 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
10034 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
10035 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
10036 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
10037 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
10038 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
10039 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
10040 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
10041 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
10042 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
10043 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
10044 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
10045 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
10046 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
10047 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
10048 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
10049 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
10050 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
10051 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
10052 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
10053 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
10054 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
10055 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
10056 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
10057 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
10058 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
10059 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
10060 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
10061 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
10062 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
10063 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
10064 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
10065 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
10066 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
10067 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
10068 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
10069 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
10070 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
10071 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
10072 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
10073 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
10074 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
10075 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
10076 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
10077 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
10078 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
10079 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
10080 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
10081 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
10082 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
10083 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
10084 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
10085 | #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
10086 | //MMEA0_IO_RD_PRI_QUANT_PRI1 |
10087 | #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
10088 | #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
10089 | #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
10090 | #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
10091 | #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
10092 | #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
10093 | #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
10094 | #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
10095 | //MMEA0_IO_RD_PRI_QUANT_PRI2 |
10096 | #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
10097 | #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
10098 | #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
10099 | #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
10100 | #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
10101 | #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
10102 | #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
10103 | #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
10104 | //MMEA0_IO_RD_PRI_QUANT_PRI3 |
10105 | #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
10106 | #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
10107 | #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
10108 | #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
10109 | #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
10110 | #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
10111 | #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
10112 | #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
10113 | //MMEA0_IO_WR_PRI_QUANT_PRI1 |
10114 | #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
10115 | #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
10116 | #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
10117 | #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
10118 | #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
10119 | #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
10120 | #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
10121 | #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
10122 | //MMEA0_IO_WR_PRI_QUANT_PRI2 |
10123 | #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
10124 | #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
10125 | #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
10126 | #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
10127 | #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
10128 | #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
10129 | #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
10130 | #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
10131 | //MMEA0_IO_WR_PRI_QUANT_PRI3 |
10132 | #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
10133 | #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
10134 | #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
10135 | #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
10136 | #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
10137 | #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
10138 | #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
10139 | #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
10140 | //MMEA0_SDP_ARB_DRAM |
10141 | #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 |
10142 | #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 |
10143 | #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 |
10144 | #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 |
10145 | #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 |
10146 | #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 |
10147 | #define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 |
10148 | #define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 |
10149 | #define MMEA0_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING__SHIFT 0x16 |
10150 | #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL |
10151 | #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L |
10152 | #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L |
10153 | #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L |
10154 | #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L |
10155 | #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L |
10156 | #define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L |
10157 | #define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L |
10158 | #define MMEA0_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING_MASK 0x00400000L |
10159 | //MMEA0_SDP_ARB_GMI |
10160 | #define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 |
10161 | #define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 |
10162 | #define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 |
10163 | #define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 |
10164 | #define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 |
10165 | #define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 |
10166 | #define MMEA0_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 |
10167 | #define MMEA0_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 |
10168 | #define MMEA0_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 |
10169 | #define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL |
10170 | #define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L |
10171 | #define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L |
10172 | #define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L |
10173 | #define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L |
10174 | #define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L |
10175 | #define MMEA0_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L |
10176 | #define MMEA0_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L |
10177 | #define MMEA0_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L |
10178 | //MMEA0_SDP_ARB_FINAL |
10179 | #define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 |
10180 | #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 |
10181 | #define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa |
10182 | #define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf |
10183 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 |
10184 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 |
10185 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 |
10186 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 |
10187 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 |
10188 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 |
10189 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 |
10190 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 |
10191 | #define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 |
10192 | #define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a |
10193 | #define MMEA0_SDP_ARB_FINAL__DRAM_BURST_STRETCH__SHIFT 0x1b |
10194 | #define MMEA0_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1c |
10195 | #define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL |
10196 | #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L |
10197 | #define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L |
10198 | #define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L |
10199 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L |
10200 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L |
10201 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L |
10202 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L |
10203 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L |
10204 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L |
10205 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L |
10206 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L |
10207 | #define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L |
10208 | #define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L |
10209 | #define MMEA0_SDP_ARB_FINAL__DRAM_BURST_STRETCH_MASK 0x08000000L |
10210 | #define MMEA0_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x10000000L |
10211 | //MMEA0_SDP_DRAM_PRIORITY |
10212 | #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 |
10213 | #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 |
10214 | #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 |
10215 | #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc |
10216 | #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 |
10217 | #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 |
10218 | #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 |
10219 | #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c |
10220 | #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL |
10221 | #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L |
10222 | #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L |
10223 | #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L |
10224 | #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L |
10225 | #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L |
10226 | #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L |
10227 | #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L |
10228 | //MMEA0_SDP_GMI_PRIORITY |
10229 | #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 |
10230 | #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 |
10231 | #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 |
10232 | #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc |
10233 | #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 |
10234 | #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 |
10235 | #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 |
10236 | #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c |
10237 | #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL |
10238 | #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L |
10239 | #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L |
10240 | #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L |
10241 | #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L |
10242 | #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L |
10243 | #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L |
10244 | #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L |
10245 | //MMEA0_SDP_IO_PRIORITY |
10246 | #define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 |
10247 | #define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 |
10248 | #define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 |
10249 | #define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc |
10250 | #define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 |
10251 | #define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 |
10252 | #define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 |
10253 | #define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c |
10254 | #define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL |
10255 | #define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L |
10256 | #define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L |
10257 | #define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L |
10258 | #define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L |
10259 | #define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L |
10260 | #define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L |
10261 | #define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L |
10262 | //MMEA0_SDP_CREDITS |
10263 | #define MMEA0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 |
10264 | #define MMEA0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 |
10265 | #define MMEA0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 |
10266 | #define MMEA0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL |
10267 | #define MMEA0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L |
10268 | #define MMEA0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L |
10269 | //MMEA0_SDP_TAG_RESERVE0 |
10270 | #define MMEA0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 |
10271 | #define MMEA0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 |
10272 | #define MMEA0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 |
10273 | #define MMEA0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 |
10274 | #define MMEA0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL |
10275 | #define MMEA0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L |
10276 | #define MMEA0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L |
10277 | #define MMEA0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L |
10278 | //MMEA0_SDP_TAG_RESERVE1 |
10279 | #define MMEA0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 |
10280 | #define MMEA0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 |
10281 | #define MMEA0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 |
10282 | #define MMEA0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 |
10283 | #define MMEA0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL |
10284 | #define MMEA0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L |
10285 | #define MMEA0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L |
10286 | #define MMEA0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L |
10287 | //MMEA0_SDP_VCC_RESERVE0 |
10288 | #define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 |
10289 | #define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 |
10290 | #define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc |
10291 | #define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 |
10292 | #define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 |
10293 | #define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL |
10294 | #define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L |
10295 | #define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L |
10296 | #define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L |
10297 | #define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L |
10298 | //MMEA0_SDP_VCC_RESERVE1 |
10299 | #define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 |
10300 | #define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 |
10301 | #define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc |
10302 | #define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f |
10303 | #define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL |
10304 | #define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L |
10305 | #define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L |
10306 | #define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L |
10307 | //MMEA0_SDP_VCD_RESERVE0 |
10308 | #define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 |
10309 | #define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 |
10310 | #define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc |
10311 | #define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 |
10312 | #define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 |
10313 | #define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL |
10314 | #define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L |
10315 | #define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L |
10316 | #define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L |
10317 | #define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L |
10318 | //MMEA0_SDP_VCD_RESERVE1 |
10319 | #define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 |
10320 | #define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 |
10321 | #define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc |
10322 | #define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f |
10323 | #define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL |
10324 | #define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L |
10325 | #define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L |
10326 | #define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L |
10327 | //MMEA0_SDP_REQ_CNTL |
10328 | #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 |
10329 | #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 |
10330 | #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 |
10331 | #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 |
10332 | #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 |
10333 | #define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 |
10334 | #define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 |
10335 | #define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 |
10336 | #define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa |
10337 | #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L |
10338 | #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L |
10339 | #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L |
10340 | #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L |
10341 | #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L |
10342 | #define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L |
10343 | #define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L |
10344 | #define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L |
10345 | #define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L |
10346 | //MMEA0_MISC |
10347 | #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 |
10348 | #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 |
10349 | #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 |
10350 | #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 |
10351 | #define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 |
10352 | #define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 |
10353 | #define MMEA0_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 |
10354 | #define MMEA0_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 |
10355 | #define MMEA0_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 |
10356 | #define MMEA0_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 |
10357 | #define MMEA0_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa |
10358 | #define MMEA0_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb |
10359 | #define MMEA0_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc |
10360 | #define MMEA0_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd |
10361 | #define MMEA0_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe |
10362 | #define MMEA0_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf |
10363 | #define MMEA0_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 |
10364 | #define MMEA0_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 |
10365 | #define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 |
10366 | #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a |
10367 | #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b |
10368 | #define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c |
10369 | #define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d |
10370 | #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e |
10371 | #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f |
10372 | #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L |
10373 | #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L |
10374 | #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L |
10375 | #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L |
10376 | #define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L |
10377 | #define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L |
10378 | #define MMEA0_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L |
10379 | #define MMEA0_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L |
10380 | #define MMEA0_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L |
10381 | #define MMEA0_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L |
10382 | #define MMEA0_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L |
10383 | #define MMEA0_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L |
10384 | #define MMEA0_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L |
10385 | #define MMEA0_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L |
10386 | #define MMEA0_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L |
10387 | #define MMEA0_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L |
10388 | #define MMEA0_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L |
10389 | #define MMEA0_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L |
10390 | #define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L |
10391 | #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L |
10392 | #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L |
10393 | #define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L |
10394 | #define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L |
10395 | #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L |
10396 | #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L |
10397 | //MMEA0_LATENCY_SAMPLING |
10398 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 |
10399 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 |
10400 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 |
10401 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 |
10402 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 |
10403 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 |
10404 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 |
10405 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 |
10406 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 |
10407 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 |
10408 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa |
10409 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb |
10410 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc |
10411 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd |
10412 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe |
10413 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 |
10414 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L |
10415 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L |
10416 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L |
10417 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L |
10418 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L |
10419 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L |
10420 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L |
10421 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L |
10422 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L |
10423 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L |
10424 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L |
10425 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L |
10426 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L |
10427 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L |
10428 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L |
10429 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L |
10430 | //MMEA0_PERFCOUNTER_LO |
10431 | #define MMEA0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
10432 | #define MMEA0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
10433 | //MMEA0_PERFCOUNTER_HI |
10434 | #define MMEA0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
10435 | #define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
10436 | #define MMEA0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
10437 | #define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
10438 | //MMEA0_PERFCOUNTER0_CFG |
10439 | #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
10440 | #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
10441 | #define MMEA0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
10442 | #define MMEA0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
10443 | #define MMEA0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
10444 | #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
10445 | #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
10446 | #define MMEA0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
10447 | #define MMEA0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
10448 | #define MMEA0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
10449 | //MMEA0_PERFCOUNTER1_CFG |
10450 | #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
10451 | #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
10452 | #define MMEA0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
10453 | #define MMEA0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
10454 | #define MMEA0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
10455 | #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
10456 | #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
10457 | #define MMEA0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
10458 | #define MMEA0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
10459 | #define MMEA0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
10460 | //MMEA0_PERFCOUNTER_RSLT_CNTL |
10461 | #define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
10462 | #define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
10463 | #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
10464 | #define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
10465 | #define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
10466 | #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
10467 | #define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
10468 | #define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
10469 | #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
10470 | #define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
10471 | #define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
10472 | #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
10473 | //MMEA0_UE_ERR_STATUS_LO |
10474 | #define MMEA0_UE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT 0x0 |
10475 | #define MMEA0_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 |
10476 | #define MMEA0_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 |
10477 | #define MMEA0_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 |
10478 | #define MMEA0_UE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK 0x00000001L |
10479 | #define MMEA0_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L |
10480 | #define MMEA0_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL |
10481 | #define MMEA0_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L |
10482 | //MMEA0_UE_ERR_STATUS_HI |
10483 | #define MMEA0_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 |
10484 | #define MMEA0_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 |
10485 | #define MMEA0_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 |
10486 | #define MMEA0_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 |
10487 | #define MMEA0_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 |
10488 | #define MMEA0_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a |
10489 | #define MMEA0_UE_ERR_STATUS_HI__RESERVED_FIELD__SHIFT 0x1d |
10490 | #define MMEA0_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L |
10491 | #define MMEA0_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L |
10492 | #define MMEA0_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L |
10493 | #define MMEA0_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L |
10494 | #define MMEA0_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L |
10495 | #define MMEA0_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L |
10496 | #define MMEA0_UE_ERR_STATUS_HI__RESERVED_FIELD_MASK 0xE0000000L |
10497 | //MMEA0_DSM_CNTL |
10498 | #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
10499 | #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
10500 | #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
10501 | #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
10502 | #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
10503 | #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
10504 | #define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
10505 | #define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
10506 | #define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc |
10507 | #define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
10508 | #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf |
10509 | #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
10510 | #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 |
10511 | #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
10512 | #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 |
10513 | #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 |
10514 | #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
10515 | #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
10516 | #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
10517 | #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
10518 | #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
10519 | #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
10520 | #define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
10521 | #define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
10522 | #define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
10523 | #define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
10524 | #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L |
10525 | #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
10526 | #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
10527 | #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
10528 | #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L |
10529 | #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L |
10530 | //MMEA0_DSM_CNTLA |
10531 | #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
10532 | #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
10533 | #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
10534 | #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
10535 | #define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
10536 | #define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
10537 | #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
10538 | #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
10539 | #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc |
10540 | #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
10541 | #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf |
10542 | #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
10543 | #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 |
10544 | #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
10545 | #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
10546 | #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
10547 | #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
10548 | #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
10549 | #define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
10550 | #define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
10551 | #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
10552 | #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
10553 | #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
10554 | #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
10555 | #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L |
10556 | #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
10557 | #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
10558 | #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
10559 | //MMEA0_DSM_CNTLB |
10560 | #define MMEA0_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
10561 | #define MMEA0_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
10562 | #define MMEA0_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
10563 | #define MMEA0_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
10564 | #define MMEA0_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
10565 | #define MMEA0_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
10566 | #define MMEA0_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
10567 | #define MMEA0_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
10568 | #define MMEA0_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
10569 | #define MMEA0_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
10570 | #define MMEA0_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
10571 | #define MMEA0_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
10572 | #define MMEA0_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
10573 | #define MMEA0_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
10574 | #define MMEA0_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
10575 | #define MMEA0_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
10576 | //MMEA0_DSM_CNTL2 |
10577 | #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
10578 | #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
10579 | #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
10580 | #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
10581 | #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
10582 | #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
10583 | #define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
10584 | #define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb |
10585 | #define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
10586 | #define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe |
10587 | #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf |
10588 | #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 |
10589 | #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 |
10590 | #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 |
10591 | #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 |
10592 | #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 |
10593 | #define MMEA0_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a |
10594 | #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
10595 | #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
10596 | #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
10597 | #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
10598 | #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
10599 | #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
10600 | #define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
10601 | #define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
10602 | #define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
10603 | #define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
10604 | #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L |
10605 | #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L |
10606 | #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
10607 | #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L |
10608 | #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L |
10609 | #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L |
10610 | #define MMEA0_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L |
10611 | //MMEA0_DSM_CNTL2A |
10612 | #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
10613 | #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
10614 | #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
10615 | #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
10616 | #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
10617 | #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
10618 | #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
10619 | #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb |
10620 | #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
10621 | #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe |
10622 | #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf |
10623 | #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 |
10624 | #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 |
10625 | #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 |
10626 | #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
10627 | #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
10628 | #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
10629 | #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
10630 | #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
10631 | #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
10632 | #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
10633 | #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
10634 | #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
10635 | #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
10636 | #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L |
10637 | #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L |
10638 | #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
10639 | #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L |
10640 | //MMEA0_DSM_CNTL2B |
10641 | #define MMEA0_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
10642 | #define MMEA0_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
10643 | #define MMEA0_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
10644 | #define MMEA0_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
10645 | #define MMEA0_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
10646 | #define MMEA0_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
10647 | #define MMEA0_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
10648 | #define MMEA0_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY__SHIFT 0xb |
10649 | #define MMEA0_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
10650 | #define MMEA0_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
10651 | #define MMEA0_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
10652 | #define MMEA0_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
10653 | #define MMEA0_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
10654 | #define MMEA0_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
10655 | #define MMEA0_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
10656 | #define MMEA0_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
10657 | //MMEA0_CGTT_CLK_CTRL |
10658 | #define MMEA0_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
10659 | #define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
10660 | #define MMEA0_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc |
10661 | #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 |
10662 | #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 |
10663 | #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 |
10664 | #define MMEA0_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 |
10665 | #define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b |
10666 | #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c |
10667 | #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d |
10668 | #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e |
10669 | #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f |
10670 | #define MMEA0_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
10671 | #define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
10672 | #define MMEA0_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L |
10673 | #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L |
10674 | #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L |
10675 | #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L |
10676 | #define MMEA0_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L |
10677 | #define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L |
10678 | #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L |
10679 | #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L |
10680 | #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L |
10681 | #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L |
10682 | //MMEA0_EDC_MODE |
10683 | #define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 |
10684 | #define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11 |
10685 | #define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14 |
10686 | #define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d |
10687 | #define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f |
10688 | #define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L |
10689 | #define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L |
10690 | #define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L |
10691 | #define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L |
10692 | #define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L |
10693 | //MMEA0_ERR_STATUS |
10694 | #define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 |
10695 | #define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 |
10696 | #define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 |
10697 | #define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa |
10698 | #define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb |
10699 | #define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc |
10700 | #define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT 0xd |
10701 | #define MMEA0_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe |
10702 | #define MMEA0_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf |
10703 | #define MMEA0_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 |
10704 | #define MMEA0_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 |
10705 | #define MMEA0_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 |
10706 | #define MMEA0_ERR_STATUS__FUE_FLAG_CLIENT__SHIFT 0x13 |
10707 | #define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL |
10708 | #define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L |
10709 | #define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L |
10710 | #define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L |
10711 | #define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L |
10712 | #define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L |
10713 | #define MMEA0_ERR_STATUS__FUE_FLAG_MASK 0x00002000L |
10714 | #define MMEA0_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L |
10715 | #define MMEA0_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L |
10716 | #define MMEA0_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L |
10717 | #define MMEA0_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L |
10718 | #define MMEA0_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L |
10719 | #define MMEA0_ERR_STATUS__FUE_FLAG_CLIENT_MASK 0x00080000L |
10720 | //MMEA0_MISC2 |
10721 | #define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 |
10722 | #define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 |
10723 | #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 |
10724 | #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 |
10725 | #define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc |
10726 | #define MMEA0_MISC2__RRET_SWAP_MODE__SHIFT 0xd |
10727 | #define MMEA0_MISC2__BLOCK_REQUESTS__SHIFT 0xe |
10728 | #define MMEA0_MISC2__REQUESTS_BLOCKED__SHIFT 0xf |
10729 | #define MMEA0_MISC2__DRAM_RD_THROTTLE__SHIFT 0x10 |
10730 | #define MMEA0_MISC2__DRAM_WR_THROTTLE__SHIFT 0x11 |
10731 | #define MMEA0_MISC2__GMI_RD_THROTTLE__SHIFT 0x12 |
10732 | #define MMEA0_MISC2__GMI_WR_THROTTLE__SHIFT 0x13 |
10733 | #define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L |
10734 | #define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L |
10735 | #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL |
10736 | #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L |
10737 | #define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L |
10738 | #define MMEA0_MISC2__RRET_SWAP_MODE_MASK 0x00002000L |
10739 | #define MMEA0_MISC2__BLOCK_REQUESTS_MASK 0x00004000L |
10740 | #define MMEA0_MISC2__REQUESTS_BLOCKED_MASK 0x00008000L |
10741 | #define MMEA0_MISC2__DRAM_RD_THROTTLE_MASK 0x00010000L |
10742 | #define MMEA0_MISC2__DRAM_WR_THROTTLE_MASK 0x00020000L |
10743 | #define MMEA0_MISC2__GMI_RD_THROTTLE_MASK 0x00040000L |
10744 | #define MMEA0_MISC2__GMI_WR_THROTTLE_MASK 0x00080000L |
10745 | //MMEA0_CE_ERR_STATUS_LO |
10746 | #define MMEA0_CE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT 0x0 |
10747 | #define MMEA0_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 |
10748 | #define MMEA0_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 |
10749 | #define MMEA0_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 |
10750 | #define MMEA0_CE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK 0x00000001L |
10751 | #define MMEA0_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L |
10752 | #define MMEA0_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL |
10753 | #define MMEA0_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L |
10754 | //MMEA0_MISC_AON |
10755 | #define MMEA0_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 |
10756 | #define MMEA0_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 |
10757 | #define MMEA0_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L |
10758 | #define MMEA0_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L |
10759 | //MMEA0_CE_ERR_STATUS_HI |
10760 | #define MMEA0_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 |
10761 | #define MMEA0_CE_ERR_STATUS_HI__RESERVED_FIELD0__SHIFT 0x1 |
10762 | #define MMEA0_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 |
10763 | #define MMEA0_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 |
10764 | #define MMEA0_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 |
10765 | #define MMEA0_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a |
10766 | #define MMEA0_CE_ERR_STATUS_HI__RESERVED_FIELD1__SHIFT 0x1b |
10767 | #define MMEA0_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L |
10768 | #define MMEA0_CE_ERR_STATUS_HI__RESERVED_FIELD0_MASK 0x00000002L |
10769 | #define MMEA0_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L |
10770 | #define MMEA0_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L |
10771 | #define MMEA0_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L |
10772 | #define MMEA0_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L |
10773 | #define MMEA0_CE_ERR_STATUS_HI__RESERVED_FIELD1_MASK 0xF8000000L |
10774 | |
10775 | // addressBlock: aid_mmhub_ea_mmeadec1 |
10776 | //MMEA1_DRAM_RD_CLI2GRP_MAP0 |
10777 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
10778 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
10779 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
10780 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
10781 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
10782 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
10783 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
10784 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
10785 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
10786 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
10787 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
10788 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
10789 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
10790 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
10791 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
10792 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
10793 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
10794 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
10795 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
10796 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
10797 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
10798 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
10799 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
10800 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
10801 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
10802 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
10803 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
10804 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
10805 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
10806 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
10807 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
10808 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
10809 | //MMEA1_DRAM_RD_CLI2GRP_MAP1 |
10810 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
10811 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
10812 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
10813 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
10814 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
10815 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
10816 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
10817 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
10818 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
10819 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
10820 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
10821 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
10822 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
10823 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
10824 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
10825 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
10826 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
10827 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
10828 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
10829 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
10830 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
10831 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
10832 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
10833 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
10834 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
10835 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
10836 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
10837 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
10838 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
10839 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
10840 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
10841 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
10842 | //MMEA1_DRAM_WR_CLI2GRP_MAP0 |
10843 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
10844 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
10845 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
10846 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
10847 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
10848 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
10849 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
10850 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
10851 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
10852 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
10853 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
10854 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
10855 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
10856 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
10857 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
10858 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
10859 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
10860 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
10861 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
10862 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
10863 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
10864 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
10865 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
10866 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
10867 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
10868 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
10869 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
10870 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
10871 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
10872 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
10873 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
10874 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
10875 | //MMEA1_DRAM_WR_CLI2GRP_MAP1 |
10876 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
10877 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
10878 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
10879 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
10880 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
10881 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
10882 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
10883 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
10884 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
10885 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
10886 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
10887 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
10888 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
10889 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
10890 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
10891 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
10892 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
10893 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
10894 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
10895 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
10896 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
10897 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
10898 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
10899 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
10900 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
10901 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
10902 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
10903 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
10904 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
10905 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
10906 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
10907 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
10908 | //MMEA1_DRAM_RD_GRP2VC_MAP |
10909 | #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
10910 | #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
10911 | #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
10912 | #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
10913 | #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
10914 | #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
10915 | #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
10916 | #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
10917 | //MMEA1_DRAM_WR_GRP2VC_MAP |
10918 | #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
10919 | #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
10920 | #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
10921 | #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
10922 | #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
10923 | #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
10924 | #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
10925 | #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
10926 | //MMEA1_DRAM_RD_LAZY |
10927 | #define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 |
10928 | #define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 |
10929 | #define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 |
10930 | #define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 |
10931 | #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
10932 | #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
10933 | #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
10934 | #define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L |
10935 | #define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L |
10936 | #define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
10937 | #define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
10938 | #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
10939 | #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
10940 | #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
10941 | //MMEA1_DRAM_WR_LAZY |
10942 | #define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 |
10943 | #define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 |
10944 | #define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 |
10945 | #define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 |
10946 | #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
10947 | #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
10948 | #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
10949 | #define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L |
10950 | #define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L |
10951 | #define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
10952 | #define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
10953 | #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
10954 | #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
10955 | #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
10956 | //MMEA1_DRAM_RD_CAM_CNTL |
10957 | #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
10958 | #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
10959 | #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
10960 | #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
10961 | #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
10962 | #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
10963 | #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
10964 | #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
10965 | #define MMEA1_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
10966 | #define MMEA1_DRAM_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d |
10967 | #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
10968 | #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
10969 | #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
10970 | #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
10971 | #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
10972 | #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
10973 | #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
10974 | #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
10975 | #define MMEA1_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
10976 | #define MMEA1_DRAM_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L |
10977 | //MMEA1_DRAM_WR_CAM_CNTL |
10978 | #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
10979 | #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
10980 | #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
10981 | #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
10982 | #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
10983 | #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
10984 | #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
10985 | #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
10986 | #define MMEA1_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
10987 | #define MMEA1_DRAM_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d |
10988 | #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
10989 | #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
10990 | #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
10991 | #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
10992 | #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
10993 | #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
10994 | #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
10995 | #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
10996 | #define MMEA1_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
10997 | #define MMEA1_DRAM_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L |
10998 | //MMEA1_DRAM_PAGE_BURST |
10999 | #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 |
11000 | #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 |
11001 | #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 |
11002 | #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 |
11003 | #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
11004 | #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
11005 | #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
11006 | #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
11007 | //MMEA1_DRAM_RD_PRI_AGE |
11008 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
11009 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
11010 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
11011 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
11012 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
11013 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
11014 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
11015 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
11016 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
11017 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
11018 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
11019 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
11020 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
11021 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
11022 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
11023 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
11024 | //MMEA1_DRAM_WR_PRI_AGE |
11025 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
11026 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
11027 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
11028 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
11029 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
11030 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
11031 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
11032 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
11033 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
11034 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
11035 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
11036 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
11037 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
11038 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
11039 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
11040 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
11041 | //MMEA1_DRAM_RD_PRI_QUEUING |
11042 | #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
11043 | #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
11044 | #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
11045 | #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
11046 | #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
11047 | #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
11048 | #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
11049 | #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
11050 | //MMEA1_DRAM_WR_PRI_QUEUING |
11051 | #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
11052 | #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
11053 | #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
11054 | #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
11055 | #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
11056 | #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
11057 | #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
11058 | #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
11059 | //MMEA1_DRAM_RD_PRI_FIXED |
11060 | #define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
11061 | #define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
11062 | #define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
11063 | #define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
11064 | #define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
11065 | #define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
11066 | #define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
11067 | #define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
11068 | //MMEA1_DRAM_WR_PRI_FIXED |
11069 | #define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
11070 | #define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
11071 | #define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
11072 | #define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
11073 | #define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
11074 | #define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
11075 | #define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
11076 | #define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
11077 | //MMEA1_DRAM_RD_PRI_URGENCY |
11078 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
11079 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
11080 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
11081 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
11082 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
11083 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
11084 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
11085 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
11086 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
11087 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
11088 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
11089 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
11090 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
11091 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
11092 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
11093 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
11094 | //MMEA1_DRAM_WR_PRI_URGENCY |
11095 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
11096 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
11097 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
11098 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
11099 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
11100 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
11101 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
11102 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
11103 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
11104 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
11105 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
11106 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
11107 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
11108 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
11109 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
11110 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
11111 | //MMEA1_DRAM_RD_PRI_QUANT_PRI1 |
11112 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
11113 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
11114 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
11115 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
11116 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
11117 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
11118 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
11119 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
11120 | //MMEA1_DRAM_RD_PRI_QUANT_PRI2 |
11121 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
11122 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
11123 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
11124 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
11125 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
11126 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
11127 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
11128 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
11129 | //MMEA1_DRAM_RD_PRI_QUANT_PRI3 |
11130 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
11131 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
11132 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
11133 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
11134 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
11135 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
11136 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
11137 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
11138 | //MMEA1_DRAM_WR_PRI_QUANT_PRI1 |
11139 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
11140 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
11141 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
11142 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
11143 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
11144 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
11145 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
11146 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
11147 | //MMEA1_DRAM_WR_PRI_QUANT_PRI2 |
11148 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
11149 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
11150 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
11151 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
11152 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
11153 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
11154 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
11155 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
11156 | //MMEA1_DRAM_WR_PRI_QUANT_PRI3 |
11157 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
11158 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
11159 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
11160 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
11161 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
11162 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
11163 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
11164 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
11165 | //MMEA1_GMI_RD_CLI2GRP_MAP0 |
11166 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
11167 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
11168 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
11169 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
11170 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
11171 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
11172 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
11173 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
11174 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
11175 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
11176 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
11177 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
11178 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
11179 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
11180 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
11181 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
11182 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
11183 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
11184 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
11185 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
11186 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
11187 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
11188 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
11189 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
11190 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
11191 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
11192 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
11193 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
11194 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
11195 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
11196 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
11197 | #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
11198 | //MMEA1_GMI_RD_CLI2GRP_MAP1 |
11199 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
11200 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
11201 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
11202 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
11203 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
11204 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
11205 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
11206 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
11207 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
11208 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
11209 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
11210 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
11211 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
11212 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
11213 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
11214 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
11215 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
11216 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
11217 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
11218 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
11219 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
11220 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
11221 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
11222 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
11223 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
11224 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
11225 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
11226 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
11227 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
11228 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
11229 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
11230 | #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
11231 | //MMEA1_GMI_WR_CLI2GRP_MAP0 |
11232 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
11233 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
11234 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
11235 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
11236 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
11237 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
11238 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
11239 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
11240 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
11241 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
11242 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
11243 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
11244 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
11245 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
11246 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
11247 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
11248 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
11249 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
11250 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
11251 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
11252 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
11253 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
11254 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
11255 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
11256 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
11257 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
11258 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
11259 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
11260 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
11261 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
11262 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
11263 | #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
11264 | //MMEA1_GMI_WR_CLI2GRP_MAP1 |
11265 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
11266 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
11267 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
11268 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
11269 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
11270 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
11271 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
11272 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
11273 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
11274 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
11275 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
11276 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
11277 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
11278 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
11279 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
11280 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
11281 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
11282 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
11283 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
11284 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
11285 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
11286 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
11287 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
11288 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
11289 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
11290 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
11291 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
11292 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
11293 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
11294 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
11295 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
11296 | #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
11297 | //MMEA1_GMI_RD_GRP2VC_MAP |
11298 | #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
11299 | #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
11300 | #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
11301 | #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
11302 | #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
11303 | #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
11304 | #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
11305 | #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
11306 | //MMEA1_GMI_WR_GRP2VC_MAP |
11307 | #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
11308 | #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
11309 | #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
11310 | #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
11311 | #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
11312 | #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
11313 | #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
11314 | #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
11315 | //MMEA1_GMI_RD_LAZY |
11316 | #define MMEA1_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 |
11317 | #define MMEA1_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 |
11318 | #define MMEA1_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 |
11319 | #define MMEA1_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 |
11320 | #define MMEA1_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
11321 | #define MMEA1_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
11322 | #define MMEA1_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
11323 | #define MMEA1_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L |
11324 | #define MMEA1_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L |
11325 | #define MMEA1_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
11326 | #define MMEA1_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
11327 | #define MMEA1_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
11328 | #define MMEA1_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
11329 | #define MMEA1_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
11330 | //MMEA1_GMI_WR_LAZY |
11331 | #define MMEA1_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 |
11332 | #define MMEA1_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 |
11333 | #define MMEA1_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 |
11334 | #define MMEA1_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 |
11335 | #define MMEA1_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
11336 | #define MMEA1_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
11337 | #define MMEA1_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
11338 | #define MMEA1_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L |
11339 | #define MMEA1_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L |
11340 | #define MMEA1_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
11341 | #define MMEA1_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
11342 | #define MMEA1_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
11343 | #define MMEA1_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
11344 | #define MMEA1_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
11345 | //MMEA1_GMI_RD_CAM_CNTL |
11346 | #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
11347 | #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
11348 | #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
11349 | #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
11350 | #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
11351 | #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
11352 | #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
11353 | #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
11354 | #define MMEA1_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
11355 | #define MMEA1_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d |
11356 | #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
11357 | #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
11358 | #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
11359 | #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
11360 | #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
11361 | #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
11362 | #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
11363 | #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
11364 | #define MMEA1_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
11365 | #define MMEA1_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L |
11366 | //MMEA1_GMI_WR_CAM_CNTL |
11367 | #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
11368 | #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
11369 | #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
11370 | #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
11371 | #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
11372 | #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
11373 | #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
11374 | #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
11375 | #define MMEA1_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
11376 | #define MMEA1_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d |
11377 | #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
11378 | #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
11379 | #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
11380 | #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
11381 | #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
11382 | #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
11383 | #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
11384 | #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
11385 | #define MMEA1_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
11386 | #define MMEA1_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L |
11387 | //MMEA1_GMI_PAGE_BURST |
11388 | #define MMEA1_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 |
11389 | #define MMEA1_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 |
11390 | #define MMEA1_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 |
11391 | #define MMEA1_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 |
11392 | #define MMEA1_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
11393 | #define MMEA1_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
11394 | #define MMEA1_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
11395 | #define MMEA1_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
11396 | //MMEA1_GMI_RD_PRI_AGE |
11397 | #define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
11398 | #define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
11399 | #define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
11400 | #define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
11401 | #define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
11402 | #define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
11403 | #define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
11404 | #define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
11405 | #define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
11406 | #define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
11407 | #define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
11408 | #define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
11409 | #define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
11410 | #define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
11411 | #define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
11412 | #define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
11413 | //MMEA1_GMI_WR_PRI_AGE |
11414 | #define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
11415 | #define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
11416 | #define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
11417 | #define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
11418 | #define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
11419 | #define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
11420 | #define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
11421 | #define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
11422 | #define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
11423 | #define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
11424 | #define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
11425 | #define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
11426 | #define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
11427 | #define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
11428 | #define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
11429 | #define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
11430 | //MMEA1_GMI_RD_PRI_QUEUING |
11431 | #define MMEA1_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
11432 | #define MMEA1_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
11433 | #define MMEA1_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
11434 | #define MMEA1_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
11435 | #define MMEA1_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
11436 | #define MMEA1_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
11437 | #define MMEA1_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
11438 | #define MMEA1_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
11439 | //MMEA1_GMI_WR_PRI_QUEUING |
11440 | #define MMEA1_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
11441 | #define MMEA1_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
11442 | #define MMEA1_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
11443 | #define MMEA1_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
11444 | #define MMEA1_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
11445 | #define MMEA1_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
11446 | #define MMEA1_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
11447 | #define MMEA1_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
11448 | //MMEA1_GMI_RD_PRI_FIXED |
11449 | #define MMEA1_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
11450 | #define MMEA1_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
11451 | #define MMEA1_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
11452 | #define MMEA1_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
11453 | #define MMEA1_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
11454 | #define MMEA1_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
11455 | #define MMEA1_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
11456 | #define MMEA1_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
11457 | //MMEA1_GMI_WR_PRI_FIXED |
11458 | #define MMEA1_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
11459 | #define MMEA1_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
11460 | #define MMEA1_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
11461 | #define MMEA1_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
11462 | #define MMEA1_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
11463 | #define MMEA1_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
11464 | #define MMEA1_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
11465 | #define MMEA1_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
11466 | //MMEA1_GMI_RD_PRI_URGENCY |
11467 | #define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
11468 | #define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
11469 | #define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
11470 | #define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
11471 | #define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
11472 | #define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
11473 | #define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
11474 | #define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
11475 | #define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
11476 | #define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
11477 | #define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
11478 | #define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
11479 | #define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
11480 | #define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
11481 | #define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
11482 | #define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
11483 | //MMEA1_GMI_WR_PRI_URGENCY |
11484 | #define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
11485 | #define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
11486 | #define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
11487 | #define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
11488 | #define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
11489 | #define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
11490 | #define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
11491 | #define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
11492 | #define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
11493 | #define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
11494 | #define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
11495 | #define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
11496 | #define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
11497 | #define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
11498 | #define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
11499 | #define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
11500 | //MMEA1_GMI_RD_PRI_URGENCY_MASKING |
11501 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
11502 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
11503 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
11504 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
11505 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
11506 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
11507 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
11508 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
11509 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
11510 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
11511 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
11512 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
11513 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
11514 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
11515 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
11516 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
11517 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
11518 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
11519 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
11520 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
11521 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
11522 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
11523 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
11524 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
11525 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
11526 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
11527 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
11528 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
11529 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
11530 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
11531 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
11532 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
11533 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
11534 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
11535 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
11536 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
11537 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
11538 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
11539 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
11540 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
11541 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
11542 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
11543 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
11544 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
11545 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
11546 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
11547 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
11548 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
11549 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
11550 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
11551 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
11552 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
11553 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
11554 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
11555 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
11556 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
11557 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
11558 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
11559 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
11560 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
11561 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
11562 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
11563 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
11564 | #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
11565 | //MMEA1_GMI_WR_PRI_URGENCY_MASKING |
11566 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
11567 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
11568 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
11569 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
11570 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
11571 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
11572 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
11573 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
11574 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
11575 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
11576 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
11577 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
11578 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
11579 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
11580 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
11581 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
11582 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
11583 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
11584 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
11585 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
11586 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
11587 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
11588 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
11589 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
11590 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
11591 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
11592 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
11593 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
11594 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
11595 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
11596 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
11597 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
11598 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
11599 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
11600 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
11601 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
11602 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
11603 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
11604 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
11605 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
11606 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
11607 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
11608 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
11609 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
11610 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
11611 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
11612 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
11613 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
11614 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
11615 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
11616 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
11617 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
11618 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
11619 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
11620 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
11621 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
11622 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
11623 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
11624 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
11625 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
11626 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
11627 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
11628 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
11629 | #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
11630 | //MMEA1_GMI_RD_PRI_QUANT_PRI1 |
11631 | #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
11632 | #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
11633 | #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
11634 | #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
11635 | #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
11636 | #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
11637 | #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
11638 | #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
11639 | //MMEA1_GMI_RD_PRI_QUANT_PRI2 |
11640 | #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
11641 | #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
11642 | #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
11643 | #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
11644 | #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
11645 | #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
11646 | #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
11647 | #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
11648 | //MMEA1_GMI_RD_PRI_QUANT_PRI3 |
11649 | #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
11650 | #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
11651 | #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
11652 | #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
11653 | #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
11654 | #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
11655 | #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
11656 | #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
11657 | //MMEA1_GMI_WR_PRI_QUANT_PRI1 |
11658 | #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
11659 | #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
11660 | #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
11661 | #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
11662 | #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
11663 | #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
11664 | #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
11665 | #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
11666 | //MMEA1_GMI_WR_PRI_QUANT_PRI2 |
11667 | #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
11668 | #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
11669 | #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
11670 | #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
11671 | #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
11672 | #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
11673 | #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
11674 | #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
11675 | //MMEA1_GMI_WR_PRI_QUANT_PRI3 |
11676 | #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
11677 | #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
11678 | #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
11679 | #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
11680 | #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
11681 | #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
11682 | #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
11683 | #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
11684 | //MMEA1_IO_RD_CLI2GRP_MAP0 |
11685 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
11686 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
11687 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
11688 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
11689 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
11690 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
11691 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
11692 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
11693 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
11694 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
11695 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
11696 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
11697 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
11698 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
11699 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
11700 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
11701 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
11702 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
11703 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
11704 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
11705 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
11706 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
11707 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
11708 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
11709 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
11710 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
11711 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
11712 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
11713 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
11714 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
11715 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
11716 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
11717 | //MMEA1_IO_RD_CLI2GRP_MAP1 |
11718 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
11719 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
11720 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
11721 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
11722 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
11723 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
11724 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
11725 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
11726 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
11727 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
11728 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
11729 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
11730 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
11731 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
11732 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
11733 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
11734 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
11735 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
11736 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
11737 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
11738 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
11739 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
11740 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
11741 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
11742 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
11743 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
11744 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
11745 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
11746 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
11747 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
11748 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
11749 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
11750 | //MMEA1_IO_WR_CLI2GRP_MAP0 |
11751 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
11752 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
11753 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
11754 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
11755 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
11756 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
11757 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
11758 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
11759 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
11760 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
11761 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
11762 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
11763 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
11764 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
11765 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
11766 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
11767 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
11768 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
11769 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
11770 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
11771 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
11772 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
11773 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
11774 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
11775 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
11776 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
11777 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
11778 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
11779 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
11780 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
11781 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
11782 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
11783 | //MMEA1_IO_WR_CLI2GRP_MAP1 |
11784 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
11785 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
11786 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
11787 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
11788 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
11789 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
11790 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
11791 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
11792 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
11793 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
11794 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
11795 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
11796 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
11797 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
11798 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
11799 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
11800 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
11801 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
11802 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
11803 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
11804 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
11805 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
11806 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
11807 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
11808 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
11809 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
11810 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
11811 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
11812 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
11813 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
11814 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
11815 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
11816 | //MMEA1_IO_RD_COMBINE_FLUSH |
11817 | #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
11818 | #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
11819 | #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
11820 | #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
11821 | #define MMEA1_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 |
11822 | #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
11823 | #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
11824 | #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
11825 | #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
11826 | #define MMEA1_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L |
11827 | //MMEA1_IO_WR_COMBINE_FLUSH |
11828 | #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
11829 | #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
11830 | #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
11831 | #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
11832 | #define MMEA1_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 |
11833 | #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
11834 | #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
11835 | #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
11836 | #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
11837 | #define MMEA1_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L |
11838 | //MMEA1_IO_GROUP_BURST |
11839 | #define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 |
11840 | #define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 |
11841 | #define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 |
11842 | #define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 |
11843 | #define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
11844 | #define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
11845 | #define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
11846 | #define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
11847 | //MMEA1_IO_RD_PRI_AGE |
11848 | #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
11849 | #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
11850 | #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
11851 | #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
11852 | #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
11853 | #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
11854 | #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
11855 | #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
11856 | #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
11857 | #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
11858 | #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
11859 | #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
11860 | #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
11861 | #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
11862 | #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
11863 | #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
11864 | //MMEA1_IO_WR_PRI_AGE |
11865 | #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
11866 | #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
11867 | #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
11868 | #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
11869 | #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
11870 | #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
11871 | #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
11872 | #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
11873 | #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
11874 | #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
11875 | #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
11876 | #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
11877 | #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
11878 | #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
11879 | #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
11880 | #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
11881 | //MMEA1_IO_RD_PRI_QUEUING |
11882 | #define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
11883 | #define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
11884 | #define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
11885 | #define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
11886 | #define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
11887 | #define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
11888 | #define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
11889 | #define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
11890 | //MMEA1_IO_WR_PRI_QUEUING |
11891 | #define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
11892 | #define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
11893 | #define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
11894 | #define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
11895 | #define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
11896 | #define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
11897 | #define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
11898 | #define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
11899 | //MMEA1_IO_RD_PRI_FIXED |
11900 | #define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
11901 | #define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
11902 | #define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
11903 | #define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
11904 | #define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
11905 | #define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
11906 | #define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
11907 | #define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
11908 | //MMEA1_IO_WR_PRI_FIXED |
11909 | #define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
11910 | #define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
11911 | #define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
11912 | #define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
11913 | #define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
11914 | #define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
11915 | #define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
11916 | #define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
11917 | //MMEA1_IO_RD_PRI_URGENCY |
11918 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
11919 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
11920 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
11921 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
11922 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
11923 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
11924 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
11925 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
11926 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
11927 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
11928 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
11929 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
11930 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
11931 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
11932 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
11933 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
11934 | //MMEA1_IO_WR_PRI_URGENCY |
11935 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
11936 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
11937 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
11938 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
11939 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
11940 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
11941 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
11942 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
11943 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
11944 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
11945 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
11946 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
11947 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
11948 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
11949 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
11950 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
11951 | //MMEA1_IO_RD_PRI_URGENCY_MASKING |
11952 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
11953 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
11954 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
11955 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
11956 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
11957 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
11958 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
11959 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
11960 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
11961 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
11962 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
11963 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
11964 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
11965 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
11966 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
11967 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
11968 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
11969 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
11970 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
11971 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
11972 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
11973 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
11974 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
11975 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
11976 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
11977 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
11978 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
11979 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
11980 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
11981 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
11982 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
11983 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
11984 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
11985 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
11986 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
11987 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
11988 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
11989 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
11990 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
11991 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
11992 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
11993 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
11994 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
11995 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
11996 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
11997 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
11998 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
11999 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
12000 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
12001 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
12002 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
12003 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
12004 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
12005 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
12006 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
12007 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
12008 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
12009 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
12010 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
12011 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
12012 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
12013 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
12014 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
12015 | #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
12016 | //MMEA1_IO_WR_PRI_URGENCY_MASKING |
12017 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
12018 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
12019 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
12020 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
12021 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
12022 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
12023 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
12024 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
12025 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
12026 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
12027 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
12028 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
12029 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
12030 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
12031 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
12032 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
12033 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
12034 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
12035 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
12036 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
12037 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
12038 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
12039 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
12040 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
12041 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
12042 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
12043 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
12044 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
12045 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
12046 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
12047 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
12048 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
12049 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
12050 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
12051 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
12052 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
12053 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
12054 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
12055 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
12056 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
12057 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
12058 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
12059 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
12060 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
12061 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
12062 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
12063 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
12064 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
12065 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
12066 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
12067 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
12068 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
12069 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
12070 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
12071 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
12072 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
12073 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
12074 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
12075 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
12076 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
12077 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
12078 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
12079 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
12080 | #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
12081 | //MMEA1_IO_RD_PRI_QUANT_PRI1 |
12082 | #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
12083 | #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
12084 | #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
12085 | #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
12086 | #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
12087 | #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
12088 | #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
12089 | #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
12090 | //MMEA1_IO_RD_PRI_QUANT_PRI2 |
12091 | #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
12092 | #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
12093 | #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
12094 | #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
12095 | #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
12096 | #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
12097 | #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
12098 | #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
12099 | //MMEA1_IO_RD_PRI_QUANT_PRI3 |
12100 | #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
12101 | #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
12102 | #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
12103 | #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
12104 | #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
12105 | #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
12106 | #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
12107 | #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
12108 | //MMEA1_IO_WR_PRI_QUANT_PRI1 |
12109 | #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
12110 | #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
12111 | #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
12112 | #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
12113 | #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
12114 | #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
12115 | #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
12116 | #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
12117 | //MMEA1_IO_WR_PRI_QUANT_PRI2 |
12118 | #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
12119 | #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
12120 | #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
12121 | #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
12122 | #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
12123 | #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
12124 | #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
12125 | #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
12126 | //MMEA1_IO_WR_PRI_QUANT_PRI3 |
12127 | #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
12128 | #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
12129 | #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
12130 | #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
12131 | #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
12132 | #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
12133 | #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
12134 | #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
12135 | //MMEA1_SDP_ARB_DRAM |
12136 | #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 |
12137 | #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 |
12138 | #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 |
12139 | #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 |
12140 | #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 |
12141 | #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 |
12142 | #define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 |
12143 | #define MMEA1_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 |
12144 | #define MMEA1_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING__SHIFT 0x16 |
12145 | #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL |
12146 | #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L |
12147 | #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L |
12148 | #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L |
12149 | #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L |
12150 | #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L |
12151 | #define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L |
12152 | #define MMEA1_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L |
12153 | #define MMEA1_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING_MASK 0x00400000L |
12154 | //MMEA1_SDP_ARB_GMI |
12155 | #define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 |
12156 | #define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 |
12157 | #define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 |
12158 | #define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 |
12159 | #define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 |
12160 | #define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 |
12161 | #define MMEA1_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 |
12162 | #define MMEA1_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 |
12163 | #define MMEA1_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 |
12164 | #define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL |
12165 | #define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L |
12166 | #define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L |
12167 | #define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L |
12168 | #define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L |
12169 | #define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L |
12170 | #define MMEA1_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L |
12171 | #define MMEA1_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L |
12172 | #define MMEA1_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L |
12173 | //MMEA1_SDP_ARB_FINAL |
12174 | #define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 |
12175 | #define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 |
12176 | #define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa |
12177 | #define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf |
12178 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 |
12179 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 |
12180 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 |
12181 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 |
12182 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 |
12183 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 |
12184 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 |
12185 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 |
12186 | #define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 |
12187 | #define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a |
12188 | #define MMEA1_SDP_ARB_FINAL__DRAM_BURST_STRETCH__SHIFT 0x1b |
12189 | #define MMEA1_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1c |
12190 | #define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL |
12191 | #define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L |
12192 | #define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L |
12193 | #define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L |
12194 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L |
12195 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L |
12196 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L |
12197 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L |
12198 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L |
12199 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L |
12200 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L |
12201 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L |
12202 | #define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L |
12203 | #define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L |
12204 | #define MMEA1_SDP_ARB_FINAL__DRAM_BURST_STRETCH_MASK 0x08000000L |
12205 | #define MMEA1_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x10000000L |
12206 | //MMEA1_SDP_DRAM_PRIORITY |
12207 | #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 |
12208 | #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 |
12209 | #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 |
12210 | #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc |
12211 | #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 |
12212 | #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 |
12213 | #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 |
12214 | #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c |
12215 | #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL |
12216 | #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L |
12217 | #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L |
12218 | #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L |
12219 | #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L |
12220 | #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L |
12221 | #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L |
12222 | #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L |
12223 | //MMEA1_SDP_GMI_PRIORITY |
12224 | #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 |
12225 | #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 |
12226 | #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 |
12227 | #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc |
12228 | #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 |
12229 | #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 |
12230 | #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 |
12231 | #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c |
12232 | #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL |
12233 | #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L |
12234 | #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L |
12235 | #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L |
12236 | #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L |
12237 | #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L |
12238 | #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L |
12239 | #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L |
12240 | //MMEA1_SDP_IO_PRIORITY |
12241 | #define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 |
12242 | #define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 |
12243 | #define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 |
12244 | #define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc |
12245 | #define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 |
12246 | #define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 |
12247 | #define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 |
12248 | #define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c |
12249 | #define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL |
12250 | #define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L |
12251 | #define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L |
12252 | #define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L |
12253 | #define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L |
12254 | #define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L |
12255 | #define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L |
12256 | #define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L |
12257 | //MMEA1_SDP_CREDITS |
12258 | #define MMEA1_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 |
12259 | #define MMEA1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 |
12260 | #define MMEA1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 |
12261 | #define MMEA1_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL |
12262 | #define MMEA1_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L |
12263 | #define MMEA1_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L |
12264 | //MMEA1_SDP_TAG_RESERVE0 |
12265 | #define MMEA1_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 |
12266 | #define MMEA1_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 |
12267 | #define MMEA1_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 |
12268 | #define MMEA1_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 |
12269 | #define MMEA1_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL |
12270 | #define MMEA1_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L |
12271 | #define MMEA1_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L |
12272 | #define MMEA1_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L |
12273 | //MMEA1_SDP_TAG_RESERVE1 |
12274 | #define MMEA1_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 |
12275 | #define MMEA1_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 |
12276 | #define MMEA1_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 |
12277 | #define MMEA1_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 |
12278 | #define MMEA1_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL |
12279 | #define MMEA1_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L |
12280 | #define MMEA1_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L |
12281 | #define MMEA1_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L |
12282 | //MMEA1_SDP_VCC_RESERVE0 |
12283 | #define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 |
12284 | #define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 |
12285 | #define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc |
12286 | #define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 |
12287 | #define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 |
12288 | #define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL |
12289 | #define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L |
12290 | #define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L |
12291 | #define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L |
12292 | #define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L |
12293 | //MMEA1_SDP_VCC_RESERVE1 |
12294 | #define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 |
12295 | #define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 |
12296 | #define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc |
12297 | #define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f |
12298 | #define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL |
12299 | #define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L |
12300 | #define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L |
12301 | #define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L |
12302 | //MMEA1_SDP_VCD_RESERVE0 |
12303 | #define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 |
12304 | #define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 |
12305 | #define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc |
12306 | #define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 |
12307 | #define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 |
12308 | #define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL |
12309 | #define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L |
12310 | #define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L |
12311 | #define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L |
12312 | #define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L |
12313 | //MMEA1_SDP_VCD_RESERVE1 |
12314 | #define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 |
12315 | #define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 |
12316 | #define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc |
12317 | #define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f |
12318 | #define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL |
12319 | #define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L |
12320 | #define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L |
12321 | #define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L |
12322 | //MMEA1_SDP_REQ_CNTL |
12323 | #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 |
12324 | #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 |
12325 | #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 |
12326 | #define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 |
12327 | #define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 |
12328 | #define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 |
12329 | #define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 |
12330 | #define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 |
12331 | #define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa |
12332 | #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L |
12333 | #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L |
12334 | #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L |
12335 | #define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L |
12336 | #define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L |
12337 | #define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L |
12338 | #define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L |
12339 | #define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L |
12340 | #define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L |
12341 | //MMEA1_MISC |
12342 | #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 |
12343 | #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 |
12344 | #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 |
12345 | #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 |
12346 | #define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 |
12347 | #define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 |
12348 | #define MMEA1_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 |
12349 | #define MMEA1_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 |
12350 | #define MMEA1_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 |
12351 | #define MMEA1_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 |
12352 | #define MMEA1_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa |
12353 | #define MMEA1_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb |
12354 | #define MMEA1_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc |
12355 | #define MMEA1_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd |
12356 | #define MMEA1_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe |
12357 | #define MMEA1_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf |
12358 | #define MMEA1_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 |
12359 | #define MMEA1_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 |
12360 | #define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 |
12361 | #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a |
12362 | #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b |
12363 | #define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c |
12364 | #define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d |
12365 | #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e |
12366 | #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f |
12367 | #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L |
12368 | #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L |
12369 | #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L |
12370 | #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L |
12371 | #define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L |
12372 | #define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L |
12373 | #define MMEA1_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L |
12374 | #define MMEA1_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L |
12375 | #define MMEA1_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L |
12376 | #define MMEA1_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L |
12377 | #define MMEA1_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L |
12378 | #define MMEA1_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L |
12379 | #define MMEA1_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L |
12380 | #define MMEA1_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L |
12381 | #define MMEA1_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L |
12382 | #define MMEA1_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L |
12383 | #define MMEA1_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L |
12384 | #define MMEA1_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L |
12385 | #define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L |
12386 | #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L |
12387 | #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L |
12388 | #define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L |
12389 | #define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L |
12390 | #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L |
12391 | #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L |
12392 | //MMEA1_LATENCY_SAMPLING |
12393 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 |
12394 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 |
12395 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 |
12396 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 |
12397 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 |
12398 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 |
12399 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 |
12400 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 |
12401 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 |
12402 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 |
12403 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa |
12404 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb |
12405 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc |
12406 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd |
12407 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe |
12408 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 |
12409 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L |
12410 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L |
12411 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L |
12412 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L |
12413 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L |
12414 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L |
12415 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L |
12416 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L |
12417 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L |
12418 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L |
12419 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L |
12420 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L |
12421 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L |
12422 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L |
12423 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L |
12424 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L |
12425 | //MMEA1_PERFCOUNTER_LO |
12426 | #define MMEA1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
12427 | #define MMEA1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
12428 | //MMEA1_PERFCOUNTER_HI |
12429 | #define MMEA1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
12430 | #define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
12431 | #define MMEA1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
12432 | #define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
12433 | //MMEA1_PERFCOUNTER0_CFG |
12434 | #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
12435 | #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
12436 | #define MMEA1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
12437 | #define MMEA1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
12438 | #define MMEA1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
12439 | #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
12440 | #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
12441 | #define MMEA1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
12442 | #define MMEA1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
12443 | #define MMEA1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
12444 | //MMEA1_PERFCOUNTER1_CFG |
12445 | #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
12446 | #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
12447 | #define MMEA1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
12448 | #define MMEA1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
12449 | #define MMEA1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
12450 | #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
12451 | #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
12452 | #define MMEA1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
12453 | #define MMEA1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
12454 | #define MMEA1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
12455 | //MMEA1_PERFCOUNTER_RSLT_CNTL |
12456 | #define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
12457 | #define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
12458 | #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
12459 | #define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
12460 | #define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
12461 | #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
12462 | #define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
12463 | #define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
12464 | #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
12465 | #define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
12466 | #define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
12467 | #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
12468 | //MMEA1_UE_ERR_STATUS_LO |
12469 | #define MMEA1_UE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT 0x0 |
12470 | #define MMEA1_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 |
12471 | #define MMEA1_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 |
12472 | #define MMEA1_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 |
12473 | #define MMEA1_UE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK 0x00000001L |
12474 | #define MMEA1_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L |
12475 | #define MMEA1_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL |
12476 | #define MMEA1_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L |
12477 | //MMEA1_UE_ERR_STATUS_HI |
12478 | #define MMEA1_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 |
12479 | #define MMEA1_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 |
12480 | #define MMEA1_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 |
12481 | #define MMEA1_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 |
12482 | #define MMEA1_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 |
12483 | #define MMEA1_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a |
12484 | #define MMEA1_UE_ERR_STATUS_HI__RESERVED_FIELD__SHIFT 0x1d |
12485 | #define MMEA1_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L |
12486 | #define MMEA1_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L |
12487 | #define MMEA1_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L |
12488 | #define MMEA1_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L |
12489 | #define MMEA1_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L |
12490 | #define MMEA1_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L |
12491 | #define MMEA1_UE_ERR_STATUS_HI__RESERVED_FIELD_MASK 0xE0000000L |
12492 | //MMEA1_DSM_CNTL |
12493 | #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
12494 | #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
12495 | #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
12496 | #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
12497 | #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
12498 | #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
12499 | #define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
12500 | #define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
12501 | #define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc |
12502 | #define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
12503 | #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf |
12504 | #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
12505 | #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 |
12506 | #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
12507 | #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 |
12508 | #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 |
12509 | #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
12510 | #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
12511 | #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
12512 | #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
12513 | #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
12514 | #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
12515 | #define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
12516 | #define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
12517 | #define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
12518 | #define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
12519 | #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L |
12520 | #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
12521 | #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
12522 | #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
12523 | #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L |
12524 | #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L |
12525 | //MMEA1_DSM_CNTLA |
12526 | #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
12527 | #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
12528 | #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
12529 | #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
12530 | #define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
12531 | #define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
12532 | #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
12533 | #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
12534 | #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc |
12535 | #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
12536 | #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf |
12537 | #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
12538 | #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 |
12539 | #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
12540 | #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
12541 | #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
12542 | #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
12543 | #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
12544 | #define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
12545 | #define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
12546 | #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
12547 | #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
12548 | #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
12549 | #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
12550 | #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L |
12551 | #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
12552 | #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
12553 | #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
12554 | //MMEA1_DSM_CNTLB |
12555 | #define MMEA1_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
12556 | #define MMEA1_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
12557 | #define MMEA1_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
12558 | #define MMEA1_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
12559 | #define MMEA1_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
12560 | #define MMEA1_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
12561 | #define MMEA1_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
12562 | #define MMEA1_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
12563 | #define MMEA1_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
12564 | #define MMEA1_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
12565 | #define MMEA1_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
12566 | #define MMEA1_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
12567 | #define MMEA1_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
12568 | #define MMEA1_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
12569 | #define MMEA1_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
12570 | #define MMEA1_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
12571 | //MMEA1_DSM_CNTL2 |
12572 | #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
12573 | #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
12574 | #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
12575 | #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
12576 | #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
12577 | #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
12578 | #define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
12579 | #define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb |
12580 | #define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
12581 | #define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe |
12582 | #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf |
12583 | #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 |
12584 | #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 |
12585 | #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 |
12586 | #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 |
12587 | #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 |
12588 | #define MMEA1_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a |
12589 | #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
12590 | #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
12591 | #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
12592 | #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
12593 | #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
12594 | #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
12595 | #define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
12596 | #define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
12597 | #define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
12598 | #define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
12599 | #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L |
12600 | #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L |
12601 | #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
12602 | #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L |
12603 | #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L |
12604 | #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L |
12605 | #define MMEA1_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L |
12606 | //MMEA1_DSM_CNTL2A |
12607 | #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
12608 | #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
12609 | #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
12610 | #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
12611 | #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
12612 | #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
12613 | #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
12614 | #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb |
12615 | #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
12616 | #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe |
12617 | #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf |
12618 | #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 |
12619 | #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 |
12620 | #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 |
12621 | #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
12622 | #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
12623 | #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
12624 | #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
12625 | #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
12626 | #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
12627 | #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
12628 | #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
12629 | #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
12630 | #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
12631 | #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L |
12632 | #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L |
12633 | #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
12634 | #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L |
12635 | //MMEA1_DSM_CNTL2B |
12636 | #define MMEA1_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
12637 | #define MMEA1_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
12638 | #define MMEA1_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
12639 | #define MMEA1_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
12640 | #define MMEA1_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
12641 | #define MMEA1_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
12642 | #define MMEA1_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
12643 | #define MMEA1_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY__SHIFT 0xb |
12644 | #define MMEA1_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
12645 | #define MMEA1_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
12646 | #define MMEA1_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
12647 | #define MMEA1_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
12648 | #define MMEA1_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
12649 | #define MMEA1_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
12650 | #define MMEA1_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
12651 | #define MMEA1_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
12652 | //MMEA1_CGTT_CLK_CTRL |
12653 | #define MMEA1_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
12654 | #define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
12655 | #define MMEA1_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc |
12656 | #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 |
12657 | #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 |
12658 | #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 |
12659 | #define MMEA1_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 |
12660 | #define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b |
12661 | #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c |
12662 | #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d |
12663 | #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e |
12664 | #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f |
12665 | #define MMEA1_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
12666 | #define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
12667 | #define MMEA1_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L |
12668 | #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L |
12669 | #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L |
12670 | #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L |
12671 | #define MMEA1_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L |
12672 | #define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L |
12673 | #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L |
12674 | #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L |
12675 | #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L |
12676 | #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L |
12677 | //MMEA1_EDC_MODE |
12678 | #define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 |
12679 | #define MMEA1_EDC_MODE__GATE_FUE__SHIFT 0x11 |
12680 | #define MMEA1_EDC_MODE__DED_MODE__SHIFT 0x14 |
12681 | #define MMEA1_EDC_MODE__PROP_FED__SHIFT 0x1d |
12682 | #define MMEA1_EDC_MODE__BYPASS__SHIFT 0x1f |
12683 | #define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L |
12684 | #define MMEA1_EDC_MODE__GATE_FUE_MASK 0x00020000L |
12685 | #define MMEA1_EDC_MODE__DED_MODE_MASK 0x00300000L |
12686 | #define MMEA1_EDC_MODE__PROP_FED_MASK 0x20000000L |
12687 | #define MMEA1_EDC_MODE__BYPASS_MASK 0x80000000L |
12688 | //MMEA1_ERR_STATUS |
12689 | #define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 |
12690 | #define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 |
12691 | #define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 |
12692 | #define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa |
12693 | #define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb |
12694 | #define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc |
12695 | #define MMEA1_ERR_STATUS__FUE_FLAG__SHIFT 0xd |
12696 | #define MMEA1_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe |
12697 | #define MMEA1_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf |
12698 | #define MMEA1_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 |
12699 | #define MMEA1_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 |
12700 | #define MMEA1_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 |
12701 | #define MMEA1_ERR_STATUS__FUE_FLAG_CLIENT__SHIFT 0x13 |
12702 | #define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL |
12703 | #define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L |
12704 | #define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L |
12705 | #define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L |
12706 | #define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L |
12707 | #define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L |
12708 | #define MMEA1_ERR_STATUS__FUE_FLAG_MASK 0x00002000L |
12709 | #define MMEA1_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L |
12710 | #define MMEA1_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L |
12711 | #define MMEA1_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L |
12712 | #define MMEA1_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L |
12713 | #define MMEA1_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L |
12714 | #define MMEA1_ERR_STATUS__FUE_FLAG_CLIENT_MASK 0x00080000L |
12715 | //MMEA1_MISC2 |
12716 | #define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 |
12717 | #define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 |
12718 | #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 |
12719 | #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 |
12720 | #define MMEA1_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc |
12721 | #define MMEA1_MISC2__RRET_SWAP_MODE__SHIFT 0xd |
12722 | #define MMEA1_MISC2__BLOCK_REQUESTS__SHIFT 0xe |
12723 | #define MMEA1_MISC2__REQUESTS_BLOCKED__SHIFT 0xf |
12724 | #define MMEA1_MISC2__DRAM_RD_THROTTLE__SHIFT 0x10 |
12725 | #define MMEA1_MISC2__DRAM_WR_THROTTLE__SHIFT 0x11 |
12726 | #define MMEA1_MISC2__GMI_RD_THROTTLE__SHIFT 0x12 |
12727 | #define MMEA1_MISC2__GMI_WR_THROTTLE__SHIFT 0x13 |
12728 | #define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L |
12729 | #define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L |
12730 | #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL |
12731 | #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L |
12732 | #define MMEA1_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L |
12733 | #define MMEA1_MISC2__RRET_SWAP_MODE_MASK 0x00002000L |
12734 | #define MMEA1_MISC2__BLOCK_REQUESTS_MASK 0x00004000L |
12735 | #define MMEA1_MISC2__REQUESTS_BLOCKED_MASK 0x00008000L |
12736 | #define MMEA1_MISC2__DRAM_RD_THROTTLE_MASK 0x00010000L |
12737 | #define MMEA1_MISC2__DRAM_WR_THROTTLE_MASK 0x00020000L |
12738 | #define MMEA1_MISC2__GMI_RD_THROTTLE_MASK 0x00040000L |
12739 | #define MMEA1_MISC2__GMI_WR_THROTTLE_MASK 0x00080000L |
12740 | //MMEA1_CE_ERR_STATUS_LO |
12741 | #define MMEA1_CE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT 0x0 |
12742 | #define MMEA1_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 |
12743 | #define MMEA1_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 |
12744 | #define MMEA1_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 |
12745 | #define MMEA1_CE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK 0x00000001L |
12746 | #define MMEA1_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L |
12747 | #define MMEA1_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL |
12748 | #define MMEA1_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L |
12749 | //MMEA1_MISC_AON |
12750 | #define MMEA1_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 |
12751 | #define MMEA1_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 |
12752 | #define MMEA1_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L |
12753 | #define MMEA1_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L |
12754 | //MMEA1_CE_ERR_STATUS_HI |
12755 | #define MMEA1_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 |
12756 | #define MMEA1_CE_ERR_STATUS_HI__RESERVED_FIELD0__SHIFT 0x1 |
12757 | #define MMEA1_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 |
12758 | #define MMEA1_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 |
12759 | #define MMEA1_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 |
12760 | #define MMEA1_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a |
12761 | #define MMEA1_CE_ERR_STATUS_HI__RESERVED_FIELD1__SHIFT 0x1b |
12762 | #define MMEA1_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L |
12763 | #define MMEA1_CE_ERR_STATUS_HI__RESERVED_FIELD0_MASK 0x00000002L |
12764 | #define MMEA1_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L |
12765 | #define MMEA1_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L |
12766 | #define MMEA1_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L |
12767 | #define MMEA1_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L |
12768 | #define MMEA1_CE_ERR_STATUS_HI__RESERVED_FIELD1_MASK 0xF8000000L |
12769 | |
12770 | // addressBlock: aid_mmhub_ea_mmeadec2 |
12771 | //MMEA2_DRAM_RD_CLI2GRP_MAP0 |
12772 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
12773 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
12774 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
12775 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
12776 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
12777 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
12778 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
12779 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
12780 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
12781 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
12782 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
12783 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
12784 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
12785 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
12786 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
12787 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
12788 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
12789 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
12790 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
12791 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
12792 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
12793 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
12794 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
12795 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
12796 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
12797 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
12798 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
12799 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
12800 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
12801 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
12802 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
12803 | #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
12804 | //MMEA2_DRAM_RD_CLI2GRP_MAP1 |
12805 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
12806 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
12807 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
12808 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
12809 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
12810 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
12811 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
12812 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
12813 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
12814 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
12815 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
12816 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
12817 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
12818 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
12819 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
12820 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
12821 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
12822 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
12823 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
12824 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
12825 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
12826 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
12827 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
12828 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
12829 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
12830 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
12831 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
12832 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
12833 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
12834 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
12835 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
12836 | #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
12837 | //MMEA2_DRAM_WR_CLI2GRP_MAP0 |
12838 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
12839 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
12840 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
12841 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
12842 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
12843 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
12844 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
12845 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
12846 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
12847 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
12848 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
12849 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
12850 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
12851 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
12852 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
12853 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
12854 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
12855 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
12856 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
12857 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
12858 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
12859 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
12860 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
12861 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
12862 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
12863 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
12864 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
12865 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
12866 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
12867 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
12868 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
12869 | #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
12870 | //MMEA2_DRAM_WR_CLI2GRP_MAP1 |
12871 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
12872 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
12873 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
12874 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
12875 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
12876 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
12877 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
12878 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
12879 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
12880 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
12881 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
12882 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
12883 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
12884 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
12885 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
12886 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
12887 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
12888 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
12889 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
12890 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
12891 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
12892 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
12893 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
12894 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
12895 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
12896 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
12897 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
12898 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
12899 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
12900 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
12901 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
12902 | #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
12903 | //MMEA2_DRAM_RD_GRP2VC_MAP |
12904 | #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
12905 | #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
12906 | #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
12907 | #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
12908 | #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
12909 | #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
12910 | #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
12911 | #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
12912 | //MMEA2_DRAM_WR_GRP2VC_MAP |
12913 | #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
12914 | #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
12915 | #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
12916 | #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
12917 | #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
12918 | #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
12919 | #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
12920 | #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
12921 | //MMEA2_DRAM_RD_LAZY |
12922 | #define MMEA2_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 |
12923 | #define MMEA2_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 |
12924 | #define MMEA2_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 |
12925 | #define MMEA2_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 |
12926 | #define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
12927 | #define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
12928 | #define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
12929 | #define MMEA2_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L |
12930 | #define MMEA2_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L |
12931 | #define MMEA2_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
12932 | #define MMEA2_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
12933 | #define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
12934 | #define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
12935 | #define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
12936 | //MMEA2_DRAM_WR_LAZY |
12937 | #define MMEA2_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 |
12938 | #define MMEA2_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 |
12939 | #define MMEA2_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 |
12940 | #define MMEA2_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 |
12941 | #define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
12942 | #define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
12943 | #define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
12944 | #define MMEA2_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L |
12945 | #define MMEA2_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L |
12946 | #define MMEA2_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
12947 | #define MMEA2_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
12948 | #define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
12949 | #define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
12950 | #define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
12951 | //MMEA2_DRAM_RD_CAM_CNTL |
12952 | #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
12953 | #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
12954 | #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
12955 | #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
12956 | #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
12957 | #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
12958 | #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
12959 | #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
12960 | #define MMEA2_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
12961 | #define MMEA2_DRAM_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d |
12962 | #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
12963 | #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
12964 | #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
12965 | #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
12966 | #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
12967 | #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
12968 | #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
12969 | #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
12970 | #define MMEA2_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
12971 | #define MMEA2_DRAM_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L |
12972 | //MMEA2_DRAM_WR_CAM_CNTL |
12973 | #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
12974 | #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
12975 | #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
12976 | #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
12977 | #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
12978 | #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
12979 | #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
12980 | #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
12981 | #define MMEA2_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
12982 | #define MMEA2_DRAM_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d |
12983 | #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
12984 | #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
12985 | #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
12986 | #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
12987 | #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
12988 | #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
12989 | #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
12990 | #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
12991 | #define MMEA2_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
12992 | #define MMEA2_DRAM_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L |
12993 | //MMEA2_DRAM_PAGE_BURST |
12994 | #define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 |
12995 | #define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 |
12996 | #define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 |
12997 | #define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 |
12998 | #define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
12999 | #define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
13000 | #define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
13001 | #define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
13002 | //MMEA2_DRAM_RD_PRI_AGE |
13003 | #define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
13004 | #define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
13005 | #define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
13006 | #define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
13007 | #define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
13008 | #define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
13009 | #define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
13010 | #define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
13011 | #define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
13012 | #define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
13013 | #define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
13014 | #define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
13015 | #define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
13016 | #define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
13017 | #define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
13018 | #define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
13019 | //MMEA2_DRAM_WR_PRI_AGE |
13020 | #define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
13021 | #define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
13022 | #define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
13023 | #define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
13024 | #define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
13025 | #define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
13026 | #define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
13027 | #define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
13028 | #define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
13029 | #define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
13030 | #define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
13031 | #define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
13032 | #define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
13033 | #define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
13034 | #define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
13035 | #define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
13036 | //MMEA2_DRAM_RD_PRI_QUEUING |
13037 | #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
13038 | #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
13039 | #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
13040 | #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
13041 | #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
13042 | #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
13043 | #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
13044 | #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
13045 | //MMEA2_DRAM_WR_PRI_QUEUING |
13046 | #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
13047 | #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
13048 | #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
13049 | #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
13050 | #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
13051 | #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
13052 | #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
13053 | #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
13054 | //MMEA2_DRAM_RD_PRI_FIXED |
13055 | #define MMEA2_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
13056 | #define MMEA2_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
13057 | #define MMEA2_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
13058 | #define MMEA2_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
13059 | #define MMEA2_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
13060 | #define MMEA2_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
13061 | #define MMEA2_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
13062 | #define MMEA2_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
13063 | //MMEA2_DRAM_WR_PRI_FIXED |
13064 | #define MMEA2_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
13065 | #define MMEA2_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
13066 | #define MMEA2_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
13067 | #define MMEA2_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
13068 | #define MMEA2_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
13069 | #define MMEA2_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
13070 | #define MMEA2_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
13071 | #define MMEA2_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
13072 | //MMEA2_DRAM_RD_PRI_URGENCY |
13073 | #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
13074 | #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
13075 | #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
13076 | #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
13077 | #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
13078 | #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
13079 | #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
13080 | #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
13081 | #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
13082 | #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
13083 | #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
13084 | #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
13085 | #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
13086 | #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
13087 | #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
13088 | #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
13089 | //MMEA2_DRAM_WR_PRI_URGENCY |
13090 | #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
13091 | #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
13092 | #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
13093 | #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
13094 | #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
13095 | #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
13096 | #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
13097 | #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
13098 | #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
13099 | #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
13100 | #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
13101 | #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
13102 | #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
13103 | #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
13104 | #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
13105 | #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
13106 | //MMEA2_DRAM_RD_PRI_QUANT_PRI1 |
13107 | #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
13108 | #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
13109 | #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
13110 | #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
13111 | #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
13112 | #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
13113 | #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
13114 | #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
13115 | //MMEA2_DRAM_RD_PRI_QUANT_PRI2 |
13116 | #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
13117 | #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
13118 | #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
13119 | #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
13120 | #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
13121 | #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
13122 | #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
13123 | #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
13124 | //MMEA2_DRAM_RD_PRI_QUANT_PRI3 |
13125 | #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
13126 | #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
13127 | #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
13128 | #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
13129 | #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
13130 | #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
13131 | #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
13132 | #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
13133 | //MMEA2_DRAM_WR_PRI_QUANT_PRI1 |
13134 | #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
13135 | #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
13136 | #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
13137 | #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
13138 | #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
13139 | #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
13140 | #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
13141 | #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
13142 | //MMEA2_DRAM_WR_PRI_QUANT_PRI2 |
13143 | #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
13144 | #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
13145 | #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
13146 | #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
13147 | #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
13148 | #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
13149 | #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
13150 | #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
13151 | //MMEA2_DRAM_WR_PRI_QUANT_PRI3 |
13152 | #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
13153 | #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
13154 | #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
13155 | #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
13156 | #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
13157 | #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
13158 | #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
13159 | #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
13160 | //MMEA2_GMI_RD_CLI2GRP_MAP0 |
13161 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
13162 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
13163 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
13164 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
13165 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
13166 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
13167 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
13168 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
13169 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
13170 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
13171 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
13172 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
13173 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
13174 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
13175 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
13176 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
13177 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
13178 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
13179 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
13180 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
13181 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
13182 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
13183 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
13184 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
13185 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
13186 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
13187 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
13188 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
13189 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
13190 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
13191 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
13192 | #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
13193 | //MMEA2_GMI_RD_CLI2GRP_MAP1 |
13194 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
13195 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
13196 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
13197 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
13198 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
13199 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
13200 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
13201 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
13202 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
13203 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
13204 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
13205 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
13206 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
13207 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
13208 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
13209 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
13210 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
13211 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
13212 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
13213 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
13214 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
13215 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
13216 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
13217 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
13218 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
13219 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
13220 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
13221 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
13222 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
13223 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
13224 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
13225 | #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
13226 | //MMEA2_GMI_WR_CLI2GRP_MAP0 |
13227 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
13228 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
13229 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
13230 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
13231 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
13232 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
13233 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
13234 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
13235 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
13236 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
13237 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
13238 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
13239 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
13240 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
13241 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
13242 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
13243 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
13244 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
13245 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
13246 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
13247 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
13248 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
13249 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
13250 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
13251 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
13252 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
13253 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
13254 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
13255 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
13256 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
13257 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
13258 | #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
13259 | //MMEA2_GMI_WR_CLI2GRP_MAP1 |
13260 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
13261 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
13262 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
13263 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
13264 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
13265 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
13266 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
13267 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
13268 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
13269 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
13270 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
13271 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
13272 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
13273 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
13274 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
13275 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
13276 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
13277 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
13278 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
13279 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
13280 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
13281 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
13282 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
13283 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
13284 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
13285 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
13286 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
13287 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
13288 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
13289 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
13290 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
13291 | #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
13292 | //MMEA2_GMI_RD_GRP2VC_MAP |
13293 | #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
13294 | #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
13295 | #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
13296 | #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
13297 | #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
13298 | #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
13299 | #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
13300 | #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
13301 | //MMEA2_GMI_WR_GRP2VC_MAP |
13302 | #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
13303 | #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
13304 | #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
13305 | #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
13306 | #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
13307 | #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
13308 | #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
13309 | #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
13310 | //MMEA2_GMI_RD_LAZY |
13311 | #define MMEA2_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 |
13312 | #define MMEA2_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 |
13313 | #define MMEA2_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 |
13314 | #define MMEA2_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 |
13315 | #define MMEA2_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
13316 | #define MMEA2_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
13317 | #define MMEA2_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
13318 | #define MMEA2_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L |
13319 | #define MMEA2_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L |
13320 | #define MMEA2_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
13321 | #define MMEA2_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
13322 | #define MMEA2_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
13323 | #define MMEA2_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
13324 | #define MMEA2_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
13325 | //MMEA2_GMI_WR_LAZY |
13326 | #define MMEA2_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 |
13327 | #define MMEA2_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 |
13328 | #define MMEA2_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 |
13329 | #define MMEA2_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 |
13330 | #define MMEA2_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
13331 | #define MMEA2_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
13332 | #define MMEA2_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
13333 | #define MMEA2_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L |
13334 | #define MMEA2_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L |
13335 | #define MMEA2_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
13336 | #define MMEA2_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
13337 | #define MMEA2_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
13338 | #define MMEA2_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
13339 | #define MMEA2_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
13340 | //MMEA2_GMI_RD_CAM_CNTL |
13341 | #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
13342 | #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
13343 | #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
13344 | #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
13345 | #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
13346 | #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
13347 | #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
13348 | #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
13349 | #define MMEA2_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
13350 | #define MMEA2_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d |
13351 | #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
13352 | #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
13353 | #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
13354 | #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
13355 | #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
13356 | #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
13357 | #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
13358 | #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
13359 | #define MMEA2_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
13360 | #define MMEA2_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L |
13361 | //MMEA2_GMI_WR_CAM_CNTL |
13362 | #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
13363 | #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
13364 | #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
13365 | #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
13366 | #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
13367 | #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
13368 | #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
13369 | #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
13370 | #define MMEA2_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
13371 | #define MMEA2_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d |
13372 | #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
13373 | #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
13374 | #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
13375 | #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
13376 | #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
13377 | #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
13378 | #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
13379 | #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
13380 | #define MMEA2_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
13381 | #define MMEA2_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L |
13382 | //MMEA2_GMI_PAGE_BURST |
13383 | #define MMEA2_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 |
13384 | #define MMEA2_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 |
13385 | #define MMEA2_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 |
13386 | #define MMEA2_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 |
13387 | #define MMEA2_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
13388 | #define MMEA2_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
13389 | #define MMEA2_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
13390 | #define MMEA2_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
13391 | //MMEA2_GMI_RD_PRI_AGE |
13392 | #define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
13393 | #define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
13394 | #define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
13395 | #define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
13396 | #define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
13397 | #define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
13398 | #define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
13399 | #define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
13400 | #define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
13401 | #define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
13402 | #define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
13403 | #define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
13404 | #define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
13405 | #define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
13406 | #define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
13407 | #define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
13408 | //MMEA2_GMI_WR_PRI_AGE |
13409 | #define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
13410 | #define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
13411 | #define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
13412 | #define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
13413 | #define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
13414 | #define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
13415 | #define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
13416 | #define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
13417 | #define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
13418 | #define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
13419 | #define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
13420 | #define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
13421 | #define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
13422 | #define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
13423 | #define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
13424 | #define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
13425 | //MMEA2_GMI_RD_PRI_QUEUING |
13426 | #define MMEA2_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
13427 | #define MMEA2_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
13428 | #define MMEA2_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
13429 | #define MMEA2_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
13430 | #define MMEA2_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
13431 | #define MMEA2_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
13432 | #define MMEA2_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
13433 | #define MMEA2_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
13434 | //MMEA2_GMI_WR_PRI_QUEUING |
13435 | #define MMEA2_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
13436 | #define MMEA2_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
13437 | #define MMEA2_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
13438 | #define MMEA2_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
13439 | #define MMEA2_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
13440 | #define MMEA2_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
13441 | #define MMEA2_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
13442 | #define MMEA2_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
13443 | //MMEA2_GMI_RD_PRI_FIXED |
13444 | #define MMEA2_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
13445 | #define MMEA2_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
13446 | #define MMEA2_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
13447 | #define MMEA2_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
13448 | #define MMEA2_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
13449 | #define MMEA2_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
13450 | #define MMEA2_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
13451 | #define MMEA2_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
13452 | //MMEA2_GMI_WR_PRI_FIXED |
13453 | #define MMEA2_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
13454 | #define MMEA2_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
13455 | #define MMEA2_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
13456 | #define MMEA2_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
13457 | #define MMEA2_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
13458 | #define MMEA2_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
13459 | #define MMEA2_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
13460 | #define MMEA2_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
13461 | //MMEA2_GMI_RD_PRI_URGENCY |
13462 | #define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
13463 | #define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
13464 | #define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
13465 | #define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
13466 | #define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
13467 | #define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
13468 | #define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
13469 | #define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
13470 | #define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
13471 | #define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
13472 | #define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
13473 | #define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
13474 | #define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
13475 | #define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
13476 | #define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
13477 | #define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
13478 | //MMEA2_GMI_WR_PRI_URGENCY |
13479 | #define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
13480 | #define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
13481 | #define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
13482 | #define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
13483 | #define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
13484 | #define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
13485 | #define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
13486 | #define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
13487 | #define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
13488 | #define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
13489 | #define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
13490 | #define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
13491 | #define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
13492 | #define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
13493 | #define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
13494 | #define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
13495 | //MMEA2_GMI_RD_PRI_URGENCY_MASKING |
13496 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
13497 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
13498 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
13499 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
13500 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
13501 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
13502 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
13503 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
13504 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
13505 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
13506 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
13507 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
13508 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
13509 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
13510 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
13511 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
13512 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
13513 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
13514 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
13515 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
13516 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
13517 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
13518 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
13519 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
13520 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
13521 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
13522 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
13523 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
13524 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
13525 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
13526 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
13527 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
13528 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
13529 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
13530 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
13531 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
13532 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
13533 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
13534 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
13535 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
13536 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
13537 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
13538 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
13539 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
13540 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
13541 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
13542 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
13543 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
13544 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
13545 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
13546 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
13547 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
13548 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
13549 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
13550 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
13551 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
13552 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
13553 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
13554 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
13555 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
13556 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
13557 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
13558 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
13559 | #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
13560 | //MMEA2_GMI_WR_PRI_URGENCY_MASKING |
13561 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
13562 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
13563 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
13564 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
13565 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
13566 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
13567 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
13568 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
13569 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
13570 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
13571 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
13572 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
13573 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
13574 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
13575 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
13576 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
13577 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
13578 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
13579 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
13580 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
13581 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
13582 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
13583 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
13584 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
13585 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
13586 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
13587 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
13588 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
13589 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
13590 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
13591 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
13592 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
13593 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
13594 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
13595 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
13596 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
13597 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
13598 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
13599 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
13600 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
13601 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
13602 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
13603 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
13604 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
13605 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
13606 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
13607 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
13608 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
13609 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
13610 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
13611 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
13612 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
13613 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
13614 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
13615 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
13616 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
13617 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
13618 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
13619 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
13620 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
13621 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
13622 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
13623 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
13624 | #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
13625 | //MMEA2_GMI_RD_PRI_QUANT_PRI1 |
13626 | #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
13627 | #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
13628 | #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
13629 | #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
13630 | #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
13631 | #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
13632 | #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
13633 | #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
13634 | //MMEA2_GMI_RD_PRI_QUANT_PRI2 |
13635 | #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
13636 | #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
13637 | #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
13638 | #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
13639 | #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
13640 | #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
13641 | #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
13642 | #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
13643 | //MMEA2_GMI_RD_PRI_QUANT_PRI3 |
13644 | #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
13645 | #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
13646 | #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
13647 | #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
13648 | #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
13649 | #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
13650 | #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
13651 | #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
13652 | //MMEA2_GMI_WR_PRI_QUANT_PRI1 |
13653 | #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
13654 | #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
13655 | #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
13656 | #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
13657 | #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
13658 | #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
13659 | #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
13660 | #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
13661 | //MMEA2_GMI_WR_PRI_QUANT_PRI2 |
13662 | #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
13663 | #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
13664 | #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
13665 | #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
13666 | #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
13667 | #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
13668 | #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
13669 | #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
13670 | //MMEA2_GMI_WR_PRI_QUANT_PRI3 |
13671 | #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
13672 | #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
13673 | #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
13674 | #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
13675 | #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
13676 | #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
13677 | #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
13678 | #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
13679 | //MMEA2_IO_RD_CLI2GRP_MAP0 |
13680 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
13681 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
13682 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
13683 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
13684 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
13685 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
13686 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
13687 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
13688 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
13689 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
13690 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
13691 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
13692 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
13693 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
13694 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
13695 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
13696 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
13697 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
13698 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
13699 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
13700 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
13701 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
13702 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
13703 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
13704 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
13705 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
13706 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
13707 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
13708 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
13709 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
13710 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
13711 | #define MMEA2_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
13712 | //MMEA2_IO_RD_CLI2GRP_MAP1 |
13713 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
13714 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
13715 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
13716 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
13717 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
13718 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
13719 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
13720 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
13721 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
13722 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
13723 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
13724 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
13725 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
13726 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
13727 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
13728 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
13729 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
13730 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
13731 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
13732 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
13733 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
13734 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
13735 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
13736 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
13737 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
13738 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
13739 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
13740 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
13741 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
13742 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
13743 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
13744 | #define MMEA2_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
13745 | //MMEA2_IO_WR_CLI2GRP_MAP0 |
13746 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
13747 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
13748 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
13749 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
13750 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
13751 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
13752 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
13753 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
13754 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
13755 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
13756 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
13757 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
13758 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
13759 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
13760 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
13761 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
13762 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
13763 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
13764 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
13765 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
13766 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
13767 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
13768 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
13769 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
13770 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
13771 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
13772 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
13773 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
13774 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
13775 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
13776 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
13777 | #define MMEA2_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
13778 | //MMEA2_IO_WR_CLI2GRP_MAP1 |
13779 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
13780 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
13781 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
13782 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
13783 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
13784 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
13785 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
13786 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
13787 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
13788 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
13789 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
13790 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
13791 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
13792 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
13793 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
13794 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
13795 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
13796 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
13797 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
13798 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
13799 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
13800 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
13801 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
13802 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
13803 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
13804 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
13805 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
13806 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
13807 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
13808 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
13809 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
13810 | #define MMEA2_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
13811 | //MMEA2_IO_RD_COMBINE_FLUSH |
13812 | #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
13813 | #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
13814 | #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
13815 | #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
13816 | #define MMEA2_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 |
13817 | #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
13818 | #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
13819 | #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
13820 | #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
13821 | #define MMEA2_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L |
13822 | //MMEA2_IO_WR_COMBINE_FLUSH |
13823 | #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
13824 | #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
13825 | #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
13826 | #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
13827 | #define MMEA2_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 |
13828 | #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
13829 | #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
13830 | #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
13831 | #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
13832 | #define MMEA2_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L |
13833 | //MMEA2_IO_GROUP_BURST |
13834 | #define MMEA2_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 |
13835 | #define MMEA2_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 |
13836 | #define MMEA2_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 |
13837 | #define MMEA2_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 |
13838 | #define MMEA2_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
13839 | #define MMEA2_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
13840 | #define MMEA2_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
13841 | #define MMEA2_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
13842 | //MMEA2_IO_RD_PRI_AGE |
13843 | #define MMEA2_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
13844 | #define MMEA2_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
13845 | #define MMEA2_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
13846 | #define MMEA2_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
13847 | #define MMEA2_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
13848 | #define MMEA2_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
13849 | #define MMEA2_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
13850 | #define MMEA2_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
13851 | #define MMEA2_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
13852 | #define MMEA2_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
13853 | #define MMEA2_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
13854 | #define MMEA2_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
13855 | #define MMEA2_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
13856 | #define MMEA2_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
13857 | #define MMEA2_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
13858 | #define MMEA2_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
13859 | //MMEA2_IO_WR_PRI_AGE |
13860 | #define MMEA2_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
13861 | #define MMEA2_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
13862 | #define MMEA2_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
13863 | #define MMEA2_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
13864 | #define MMEA2_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
13865 | #define MMEA2_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
13866 | #define MMEA2_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
13867 | #define MMEA2_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
13868 | #define MMEA2_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
13869 | #define MMEA2_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
13870 | #define MMEA2_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
13871 | #define MMEA2_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
13872 | #define MMEA2_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
13873 | #define MMEA2_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
13874 | #define MMEA2_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
13875 | #define MMEA2_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
13876 | //MMEA2_IO_RD_PRI_QUEUING |
13877 | #define MMEA2_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
13878 | #define MMEA2_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
13879 | #define MMEA2_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
13880 | #define MMEA2_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
13881 | #define MMEA2_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
13882 | #define MMEA2_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
13883 | #define MMEA2_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
13884 | #define MMEA2_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
13885 | //MMEA2_IO_WR_PRI_QUEUING |
13886 | #define MMEA2_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
13887 | #define MMEA2_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
13888 | #define MMEA2_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
13889 | #define MMEA2_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
13890 | #define MMEA2_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
13891 | #define MMEA2_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
13892 | #define MMEA2_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
13893 | #define MMEA2_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
13894 | //MMEA2_IO_RD_PRI_FIXED |
13895 | #define MMEA2_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
13896 | #define MMEA2_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
13897 | #define MMEA2_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
13898 | #define MMEA2_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
13899 | #define MMEA2_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
13900 | #define MMEA2_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
13901 | #define MMEA2_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
13902 | #define MMEA2_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
13903 | //MMEA2_IO_WR_PRI_FIXED |
13904 | #define MMEA2_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
13905 | #define MMEA2_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
13906 | #define MMEA2_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
13907 | #define MMEA2_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
13908 | #define MMEA2_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
13909 | #define MMEA2_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
13910 | #define MMEA2_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
13911 | #define MMEA2_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
13912 | //MMEA2_IO_RD_PRI_URGENCY |
13913 | #define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
13914 | #define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
13915 | #define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
13916 | #define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
13917 | #define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
13918 | #define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
13919 | #define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
13920 | #define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
13921 | #define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
13922 | #define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
13923 | #define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
13924 | #define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
13925 | #define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
13926 | #define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
13927 | #define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
13928 | #define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
13929 | //MMEA2_IO_WR_PRI_URGENCY |
13930 | #define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
13931 | #define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
13932 | #define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
13933 | #define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
13934 | #define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
13935 | #define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
13936 | #define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
13937 | #define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
13938 | #define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
13939 | #define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
13940 | #define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
13941 | #define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
13942 | #define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
13943 | #define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
13944 | #define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
13945 | #define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
13946 | //MMEA2_IO_RD_PRI_URGENCY_MASKING |
13947 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
13948 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
13949 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
13950 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
13951 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
13952 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
13953 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
13954 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
13955 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
13956 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
13957 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
13958 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
13959 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
13960 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
13961 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
13962 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
13963 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
13964 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
13965 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
13966 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
13967 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
13968 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
13969 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
13970 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
13971 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
13972 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
13973 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
13974 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
13975 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
13976 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
13977 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
13978 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
13979 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
13980 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
13981 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
13982 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
13983 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
13984 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
13985 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
13986 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
13987 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
13988 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
13989 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
13990 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
13991 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
13992 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
13993 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
13994 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
13995 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
13996 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
13997 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
13998 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
13999 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
14000 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
14001 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
14002 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
14003 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
14004 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
14005 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
14006 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
14007 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
14008 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
14009 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
14010 | #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
14011 | //MMEA2_IO_WR_PRI_URGENCY_MASKING |
14012 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
14013 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
14014 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
14015 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
14016 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
14017 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
14018 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
14019 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
14020 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
14021 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
14022 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
14023 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
14024 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
14025 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
14026 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
14027 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
14028 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
14029 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
14030 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
14031 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
14032 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
14033 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
14034 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
14035 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
14036 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
14037 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
14038 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
14039 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
14040 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
14041 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
14042 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
14043 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
14044 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
14045 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
14046 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
14047 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
14048 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
14049 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
14050 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
14051 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
14052 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
14053 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
14054 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
14055 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
14056 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
14057 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
14058 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
14059 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
14060 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
14061 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
14062 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
14063 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
14064 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
14065 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
14066 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
14067 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
14068 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
14069 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
14070 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
14071 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
14072 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
14073 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
14074 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
14075 | #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
14076 | //MMEA2_IO_RD_PRI_QUANT_PRI1 |
14077 | #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
14078 | #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
14079 | #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
14080 | #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
14081 | #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
14082 | #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
14083 | #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
14084 | #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
14085 | //MMEA2_IO_RD_PRI_QUANT_PRI2 |
14086 | #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
14087 | #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
14088 | #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
14089 | #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
14090 | #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
14091 | #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
14092 | #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
14093 | #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
14094 | //MMEA2_IO_RD_PRI_QUANT_PRI3 |
14095 | #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
14096 | #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
14097 | #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
14098 | #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
14099 | #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
14100 | #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
14101 | #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
14102 | #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
14103 | //MMEA2_IO_WR_PRI_QUANT_PRI1 |
14104 | #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
14105 | #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
14106 | #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
14107 | #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
14108 | #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
14109 | #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
14110 | #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
14111 | #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
14112 | //MMEA2_IO_WR_PRI_QUANT_PRI2 |
14113 | #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
14114 | #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
14115 | #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
14116 | #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
14117 | #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
14118 | #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
14119 | #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
14120 | #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
14121 | //MMEA2_IO_WR_PRI_QUANT_PRI3 |
14122 | #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
14123 | #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
14124 | #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
14125 | #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
14126 | #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
14127 | #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
14128 | #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
14129 | #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
14130 | //MMEA2_SDP_ARB_DRAM |
14131 | #define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 |
14132 | #define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 |
14133 | #define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 |
14134 | #define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 |
14135 | #define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 |
14136 | #define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 |
14137 | #define MMEA2_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 |
14138 | #define MMEA2_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 |
14139 | #define MMEA2_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING__SHIFT 0x16 |
14140 | #define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL |
14141 | #define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L |
14142 | #define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L |
14143 | #define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L |
14144 | #define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L |
14145 | #define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L |
14146 | #define MMEA2_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L |
14147 | #define MMEA2_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L |
14148 | #define MMEA2_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING_MASK 0x00400000L |
14149 | //MMEA2_SDP_ARB_GMI |
14150 | #define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 |
14151 | #define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 |
14152 | #define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 |
14153 | #define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 |
14154 | #define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 |
14155 | #define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 |
14156 | #define MMEA2_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 |
14157 | #define MMEA2_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 |
14158 | #define MMEA2_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 |
14159 | #define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL |
14160 | #define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L |
14161 | #define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L |
14162 | #define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L |
14163 | #define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L |
14164 | #define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L |
14165 | #define MMEA2_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L |
14166 | #define MMEA2_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L |
14167 | #define MMEA2_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L |
14168 | //MMEA2_SDP_ARB_FINAL |
14169 | #define MMEA2_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 |
14170 | #define MMEA2_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 |
14171 | #define MMEA2_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa |
14172 | #define MMEA2_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf |
14173 | #define MMEA2_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 |
14174 | #define MMEA2_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 |
14175 | #define MMEA2_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 |
14176 | #define MMEA2_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 |
14177 | #define MMEA2_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 |
14178 | #define MMEA2_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 |
14179 | #define MMEA2_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 |
14180 | #define MMEA2_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 |
14181 | #define MMEA2_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 |
14182 | #define MMEA2_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a |
14183 | #define MMEA2_SDP_ARB_FINAL__DRAM_BURST_STRETCH__SHIFT 0x1b |
14184 | #define MMEA2_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1c |
14185 | #define MMEA2_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL |
14186 | #define MMEA2_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L |
14187 | #define MMEA2_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L |
14188 | #define MMEA2_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L |
14189 | #define MMEA2_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L |
14190 | #define MMEA2_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L |
14191 | #define MMEA2_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L |
14192 | #define MMEA2_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L |
14193 | #define MMEA2_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L |
14194 | #define MMEA2_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L |
14195 | #define MMEA2_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L |
14196 | #define MMEA2_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L |
14197 | #define MMEA2_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L |
14198 | #define MMEA2_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L |
14199 | #define MMEA2_SDP_ARB_FINAL__DRAM_BURST_STRETCH_MASK 0x08000000L |
14200 | #define MMEA2_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x10000000L |
14201 | //MMEA2_SDP_DRAM_PRIORITY |
14202 | #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 |
14203 | #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 |
14204 | #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 |
14205 | #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc |
14206 | #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 |
14207 | #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 |
14208 | #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 |
14209 | #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c |
14210 | #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL |
14211 | #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L |
14212 | #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L |
14213 | #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L |
14214 | #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L |
14215 | #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L |
14216 | #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L |
14217 | #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L |
14218 | //MMEA2_SDP_GMI_PRIORITY |
14219 | #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 |
14220 | #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 |
14221 | #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 |
14222 | #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc |
14223 | #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 |
14224 | #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 |
14225 | #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 |
14226 | #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c |
14227 | #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL |
14228 | #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L |
14229 | #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L |
14230 | #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L |
14231 | #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L |
14232 | #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L |
14233 | #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L |
14234 | #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L |
14235 | //MMEA2_SDP_IO_PRIORITY |
14236 | #define MMEA2_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 |
14237 | #define MMEA2_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 |
14238 | #define MMEA2_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 |
14239 | #define MMEA2_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc |
14240 | #define MMEA2_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 |
14241 | #define MMEA2_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 |
14242 | #define MMEA2_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 |
14243 | #define MMEA2_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c |
14244 | #define MMEA2_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL |
14245 | #define MMEA2_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L |
14246 | #define MMEA2_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L |
14247 | #define MMEA2_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L |
14248 | #define MMEA2_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L |
14249 | #define MMEA2_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L |
14250 | #define MMEA2_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L |
14251 | #define MMEA2_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L |
14252 | //MMEA2_SDP_CREDITS |
14253 | #define MMEA2_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 |
14254 | #define MMEA2_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 |
14255 | #define MMEA2_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 |
14256 | #define MMEA2_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL |
14257 | #define MMEA2_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L |
14258 | #define MMEA2_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L |
14259 | //MMEA2_SDP_TAG_RESERVE0 |
14260 | #define MMEA2_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 |
14261 | #define MMEA2_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 |
14262 | #define MMEA2_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 |
14263 | #define MMEA2_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 |
14264 | #define MMEA2_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL |
14265 | #define MMEA2_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L |
14266 | #define MMEA2_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L |
14267 | #define MMEA2_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L |
14268 | //MMEA2_SDP_TAG_RESERVE1 |
14269 | #define MMEA2_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 |
14270 | #define MMEA2_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 |
14271 | #define MMEA2_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 |
14272 | #define MMEA2_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 |
14273 | #define MMEA2_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL |
14274 | #define MMEA2_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L |
14275 | #define MMEA2_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L |
14276 | #define MMEA2_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L |
14277 | //MMEA2_SDP_VCC_RESERVE0 |
14278 | #define MMEA2_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 |
14279 | #define MMEA2_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 |
14280 | #define MMEA2_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc |
14281 | #define MMEA2_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 |
14282 | #define MMEA2_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 |
14283 | #define MMEA2_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL |
14284 | #define MMEA2_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L |
14285 | #define MMEA2_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L |
14286 | #define MMEA2_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L |
14287 | #define MMEA2_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L |
14288 | //MMEA2_SDP_VCC_RESERVE1 |
14289 | #define MMEA2_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 |
14290 | #define MMEA2_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 |
14291 | #define MMEA2_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc |
14292 | #define MMEA2_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f |
14293 | #define MMEA2_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL |
14294 | #define MMEA2_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L |
14295 | #define MMEA2_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L |
14296 | #define MMEA2_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L |
14297 | //MMEA2_SDP_VCD_RESERVE0 |
14298 | #define MMEA2_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 |
14299 | #define MMEA2_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 |
14300 | #define MMEA2_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc |
14301 | #define MMEA2_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 |
14302 | #define MMEA2_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 |
14303 | #define MMEA2_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL |
14304 | #define MMEA2_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L |
14305 | #define MMEA2_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L |
14306 | #define MMEA2_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L |
14307 | #define MMEA2_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L |
14308 | //MMEA2_SDP_VCD_RESERVE1 |
14309 | #define MMEA2_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 |
14310 | #define MMEA2_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 |
14311 | #define MMEA2_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc |
14312 | #define MMEA2_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f |
14313 | #define MMEA2_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL |
14314 | #define MMEA2_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L |
14315 | #define MMEA2_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L |
14316 | #define MMEA2_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L |
14317 | //MMEA2_SDP_REQ_CNTL |
14318 | #define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 |
14319 | #define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 |
14320 | #define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 |
14321 | #define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 |
14322 | #define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 |
14323 | #define MMEA2_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 |
14324 | #define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 |
14325 | #define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 |
14326 | #define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa |
14327 | #define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L |
14328 | #define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L |
14329 | #define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L |
14330 | #define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L |
14331 | #define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L |
14332 | #define MMEA2_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L |
14333 | #define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L |
14334 | #define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L |
14335 | #define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L |
14336 | //MMEA2_MISC |
14337 | #define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 |
14338 | #define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 |
14339 | #define MMEA2_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 |
14340 | #define MMEA2_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 |
14341 | #define MMEA2_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 |
14342 | #define MMEA2_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 |
14343 | #define MMEA2_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 |
14344 | #define MMEA2_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 |
14345 | #define MMEA2_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 |
14346 | #define MMEA2_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 |
14347 | #define MMEA2_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa |
14348 | #define MMEA2_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb |
14349 | #define MMEA2_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc |
14350 | #define MMEA2_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd |
14351 | #define MMEA2_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe |
14352 | #define MMEA2_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf |
14353 | #define MMEA2_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 |
14354 | #define MMEA2_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 |
14355 | #define MMEA2_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 |
14356 | #define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a |
14357 | #define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b |
14358 | #define MMEA2_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c |
14359 | #define MMEA2_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d |
14360 | #define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e |
14361 | #define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f |
14362 | #define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L |
14363 | #define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L |
14364 | #define MMEA2_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L |
14365 | #define MMEA2_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L |
14366 | #define MMEA2_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L |
14367 | #define MMEA2_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L |
14368 | #define MMEA2_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L |
14369 | #define MMEA2_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L |
14370 | #define MMEA2_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L |
14371 | #define MMEA2_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L |
14372 | #define MMEA2_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L |
14373 | #define MMEA2_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L |
14374 | #define MMEA2_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L |
14375 | #define MMEA2_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L |
14376 | #define MMEA2_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L |
14377 | #define MMEA2_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L |
14378 | #define MMEA2_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L |
14379 | #define MMEA2_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L |
14380 | #define MMEA2_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L |
14381 | #define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L |
14382 | #define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L |
14383 | #define MMEA2_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L |
14384 | #define MMEA2_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L |
14385 | #define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L |
14386 | #define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L |
14387 | //MMEA2_LATENCY_SAMPLING |
14388 | #define MMEA2_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 |
14389 | #define MMEA2_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 |
14390 | #define MMEA2_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 |
14391 | #define MMEA2_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 |
14392 | #define MMEA2_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 |
14393 | #define MMEA2_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 |
14394 | #define MMEA2_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 |
14395 | #define MMEA2_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 |
14396 | #define MMEA2_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 |
14397 | #define MMEA2_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 |
14398 | #define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa |
14399 | #define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb |
14400 | #define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc |
14401 | #define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd |
14402 | #define MMEA2_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe |
14403 | #define MMEA2_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 |
14404 | #define MMEA2_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L |
14405 | #define MMEA2_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L |
14406 | #define MMEA2_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L |
14407 | #define MMEA2_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L |
14408 | #define MMEA2_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L |
14409 | #define MMEA2_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L |
14410 | #define MMEA2_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L |
14411 | #define MMEA2_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L |
14412 | #define MMEA2_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L |
14413 | #define MMEA2_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L |
14414 | #define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L |
14415 | #define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L |
14416 | #define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L |
14417 | #define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L |
14418 | #define MMEA2_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L |
14419 | #define MMEA2_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L |
14420 | //MMEA2_PERFCOUNTER_LO |
14421 | #define MMEA2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
14422 | #define MMEA2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
14423 | //MMEA2_PERFCOUNTER_HI |
14424 | #define MMEA2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
14425 | #define MMEA2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
14426 | #define MMEA2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
14427 | #define MMEA2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
14428 | //MMEA2_PERFCOUNTER0_CFG |
14429 | #define MMEA2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
14430 | #define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
14431 | #define MMEA2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
14432 | #define MMEA2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
14433 | #define MMEA2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
14434 | #define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
14435 | #define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
14436 | #define MMEA2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
14437 | #define MMEA2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
14438 | #define MMEA2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
14439 | //MMEA2_PERFCOUNTER1_CFG |
14440 | #define MMEA2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
14441 | #define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
14442 | #define MMEA2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
14443 | #define MMEA2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
14444 | #define MMEA2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
14445 | #define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
14446 | #define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
14447 | #define MMEA2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
14448 | #define MMEA2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
14449 | #define MMEA2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
14450 | //MMEA2_PERFCOUNTER_RSLT_CNTL |
14451 | #define MMEA2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
14452 | #define MMEA2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
14453 | #define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
14454 | #define MMEA2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
14455 | #define MMEA2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
14456 | #define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
14457 | #define MMEA2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
14458 | #define MMEA2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
14459 | #define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
14460 | #define MMEA2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
14461 | #define MMEA2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
14462 | #define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
14463 | //MMEA2_UE_ERR_STATUS_LO |
14464 | #define MMEA2_UE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT 0x0 |
14465 | #define MMEA2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 |
14466 | #define MMEA2_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 |
14467 | #define MMEA2_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 |
14468 | #define MMEA2_UE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK 0x00000001L |
14469 | #define MMEA2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L |
14470 | #define MMEA2_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL |
14471 | #define MMEA2_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L |
14472 | //MMEA2_UE_ERR_STATUS_HI |
14473 | #define MMEA2_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 |
14474 | #define MMEA2_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 |
14475 | #define MMEA2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 |
14476 | #define MMEA2_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 |
14477 | #define MMEA2_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 |
14478 | #define MMEA2_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a |
14479 | #define MMEA2_UE_ERR_STATUS_HI__RESERVED_FIELD__SHIFT 0x1d |
14480 | #define MMEA2_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L |
14481 | #define MMEA2_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L |
14482 | #define MMEA2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L |
14483 | #define MMEA2_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L |
14484 | #define MMEA2_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L |
14485 | #define MMEA2_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L |
14486 | #define MMEA2_UE_ERR_STATUS_HI__RESERVED_FIELD_MASK 0xE0000000L |
14487 | //MMEA2_DSM_CNTL |
14488 | #define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
14489 | #define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
14490 | #define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
14491 | #define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
14492 | #define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
14493 | #define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
14494 | #define MMEA2_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
14495 | #define MMEA2_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
14496 | #define MMEA2_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc |
14497 | #define MMEA2_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
14498 | #define MMEA2_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf |
14499 | #define MMEA2_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
14500 | #define MMEA2_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 |
14501 | #define MMEA2_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
14502 | #define MMEA2_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 |
14503 | #define MMEA2_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 |
14504 | #define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
14505 | #define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
14506 | #define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
14507 | #define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
14508 | #define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
14509 | #define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
14510 | #define MMEA2_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
14511 | #define MMEA2_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
14512 | #define MMEA2_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
14513 | #define MMEA2_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
14514 | #define MMEA2_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L |
14515 | #define MMEA2_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
14516 | #define MMEA2_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
14517 | #define MMEA2_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
14518 | #define MMEA2_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L |
14519 | #define MMEA2_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L |
14520 | //MMEA2_DSM_CNTLA |
14521 | #define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
14522 | #define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
14523 | #define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
14524 | #define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
14525 | #define MMEA2_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
14526 | #define MMEA2_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
14527 | #define MMEA2_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
14528 | #define MMEA2_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
14529 | #define MMEA2_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc |
14530 | #define MMEA2_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
14531 | #define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf |
14532 | #define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
14533 | #define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 |
14534 | #define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
14535 | #define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
14536 | #define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
14537 | #define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
14538 | #define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
14539 | #define MMEA2_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
14540 | #define MMEA2_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
14541 | #define MMEA2_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
14542 | #define MMEA2_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
14543 | #define MMEA2_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
14544 | #define MMEA2_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
14545 | #define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L |
14546 | #define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
14547 | #define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
14548 | #define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
14549 | //MMEA2_DSM_CNTLB |
14550 | #define MMEA2_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
14551 | #define MMEA2_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
14552 | #define MMEA2_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
14553 | #define MMEA2_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
14554 | #define MMEA2_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
14555 | #define MMEA2_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
14556 | #define MMEA2_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
14557 | #define MMEA2_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
14558 | #define MMEA2_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
14559 | #define MMEA2_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
14560 | #define MMEA2_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
14561 | #define MMEA2_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
14562 | #define MMEA2_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
14563 | #define MMEA2_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
14564 | #define MMEA2_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
14565 | #define MMEA2_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
14566 | //MMEA2_DSM_CNTL2 |
14567 | #define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
14568 | #define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
14569 | #define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
14570 | #define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
14571 | #define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
14572 | #define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
14573 | #define MMEA2_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
14574 | #define MMEA2_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb |
14575 | #define MMEA2_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
14576 | #define MMEA2_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe |
14577 | #define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf |
14578 | #define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 |
14579 | #define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 |
14580 | #define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 |
14581 | #define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 |
14582 | #define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 |
14583 | #define MMEA2_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a |
14584 | #define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
14585 | #define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
14586 | #define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
14587 | #define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
14588 | #define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
14589 | #define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
14590 | #define MMEA2_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
14591 | #define MMEA2_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
14592 | #define MMEA2_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
14593 | #define MMEA2_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
14594 | #define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L |
14595 | #define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L |
14596 | #define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
14597 | #define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L |
14598 | #define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L |
14599 | #define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L |
14600 | #define MMEA2_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L |
14601 | //MMEA2_DSM_CNTL2A |
14602 | #define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
14603 | #define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
14604 | #define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
14605 | #define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
14606 | #define MMEA2_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
14607 | #define MMEA2_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
14608 | #define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
14609 | #define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb |
14610 | #define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
14611 | #define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe |
14612 | #define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf |
14613 | #define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 |
14614 | #define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 |
14615 | #define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 |
14616 | #define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
14617 | #define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
14618 | #define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
14619 | #define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
14620 | #define MMEA2_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
14621 | #define MMEA2_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
14622 | #define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
14623 | #define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
14624 | #define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
14625 | #define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
14626 | #define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L |
14627 | #define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L |
14628 | #define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
14629 | #define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L |
14630 | //MMEA2_DSM_CNTL2B |
14631 | #define MMEA2_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
14632 | #define MMEA2_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
14633 | #define MMEA2_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
14634 | #define MMEA2_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
14635 | #define MMEA2_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
14636 | #define MMEA2_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
14637 | #define MMEA2_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
14638 | #define MMEA2_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY__SHIFT 0xb |
14639 | #define MMEA2_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
14640 | #define MMEA2_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
14641 | #define MMEA2_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
14642 | #define MMEA2_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
14643 | #define MMEA2_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
14644 | #define MMEA2_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
14645 | #define MMEA2_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
14646 | #define MMEA2_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
14647 | //MMEA2_CGTT_CLK_CTRL |
14648 | #define MMEA2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
14649 | #define MMEA2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
14650 | #define MMEA2_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc |
14651 | #define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 |
14652 | #define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 |
14653 | #define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 |
14654 | #define MMEA2_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 |
14655 | #define MMEA2_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b |
14656 | #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c |
14657 | #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d |
14658 | #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e |
14659 | #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f |
14660 | #define MMEA2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
14661 | #define MMEA2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
14662 | #define MMEA2_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L |
14663 | #define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L |
14664 | #define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L |
14665 | #define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L |
14666 | #define MMEA2_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L |
14667 | #define MMEA2_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L |
14668 | #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L |
14669 | #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L |
14670 | #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L |
14671 | #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L |
14672 | //MMEA2_EDC_MODE |
14673 | #define MMEA2_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 |
14674 | #define MMEA2_EDC_MODE__GATE_FUE__SHIFT 0x11 |
14675 | #define MMEA2_EDC_MODE__DED_MODE__SHIFT 0x14 |
14676 | #define MMEA2_EDC_MODE__PROP_FED__SHIFT 0x1d |
14677 | #define MMEA2_EDC_MODE__BYPASS__SHIFT 0x1f |
14678 | #define MMEA2_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L |
14679 | #define MMEA2_EDC_MODE__GATE_FUE_MASK 0x00020000L |
14680 | #define MMEA2_EDC_MODE__DED_MODE_MASK 0x00300000L |
14681 | #define MMEA2_EDC_MODE__PROP_FED_MASK 0x20000000L |
14682 | #define MMEA2_EDC_MODE__BYPASS_MASK 0x80000000L |
14683 | //MMEA2_ERR_STATUS |
14684 | #define MMEA2_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 |
14685 | #define MMEA2_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 |
14686 | #define MMEA2_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 |
14687 | #define MMEA2_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa |
14688 | #define MMEA2_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb |
14689 | #define MMEA2_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc |
14690 | #define MMEA2_ERR_STATUS__FUE_FLAG__SHIFT 0xd |
14691 | #define MMEA2_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe |
14692 | #define MMEA2_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf |
14693 | #define MMEA2_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 |
14694 | #define MMEA2_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 |
14695 | #define MMEA2_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 |
14696 | #define MMEA2_ERR_STATUS__FUE_FLAG_CLIENT__SHIFT 0x13 |
14697 | #define MMEA2_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL |
14698 | #define MMEA2_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L |
14699 | #define MMEA2_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L |
14700 | #define MMEA2_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L |
14701 | #define MMEA2_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L |
14702 | #define MMEA2_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L |
14703 | #define MMEA2_ERR_STATUS__FUE_FLAG_MASK 0x00002000L |
14704 | #define MMEA2_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L |
14705 | #define MMEA2_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L |
14706 | #define MMEA2_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L |
14707 | #define MMEA2_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L |
14708 | #define MMEA2_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L |
14709 | #define MMEA2_ERR_STATUS__FUE_FLAG_CLIENT_MASK 0x00080000L |
14710 | //MMEA2_MISC2 |
14711 | #define MMEA2_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 |
14712 | #define MMEA2_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 |
14713 | #define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 |
14714 | #define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 |
14715 | #define MMEA2_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc |
14716 | #define MMEA2_MISC2__RRET_SWAP_MODE__SHIFT 0xd |
14717 | #define MMEA2_MISC2__BLOCK_REQUESTS__SHIFT 0xe |
14718 | #define MMEA2_MISC2__REQUESTS_BLOCKED__SHIFT 0xf |
14719 | #define MMEA2_MISC2__DRAM_RD_THROTTLE__SHIFT 0x10 |
14720 | #define MMEA2_MISC2__DRAM_WR_THROTTLE__SHIFT 0x11 |
14721 | #define MMEA2_MISC2__GMI_RD_THROTTLE__SHIFT 0x12 |
14722 | #define MMEA2_MISC2__GMI_WR_THROTTLE__SHIFT 0x13 |
14723 | #define MMEA2_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L |
14724 | #define MMEA2_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L |
14725 | #define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL |
14726 | #define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L |
14727 | #define MMEA2_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L |
14728 | #define MMEA2_MISC2__RRET_SWAP_MODE_MASK 0x00002000L |
14729 | #define MMEA2_MISC2__BLOCK_REQUESTS_MASK 0x00004000L |
14730 | #define MMEA2_MISC2__REQUESTS_BLOCKED_MASK 0x00008000L |
14731 | #define MMEA2_MISC2__DRAM_RD_THROTTLE_MASK 0x00010000L |
14732 | #define MMEA2_MISC2__DRAM_WR_THROTTLE_MASK 0x00020000L |
14733 | #define MMEA2_MISC2__GMI_RD_THROTTLE_MASK 0x00040000L |
14734 | #define MMEA2_MISC2__GMI_WR_THROTTLE_MASK 0x00080000L |
14735 | //MMEA2_CE_ERR_STATUS_LO |
14736 | #define MMEA2_CE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT 0x0 |
14737 | #define MMEA2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 |
14738 | #define MMEA2_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 |
14739 | #define MMEA2_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 |
14740 | #define MMEA2_CE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK 0x00000001L |
14741 | #define MMEA2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L |
14742 | #define MMEA2_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL |
14743 | #define MMEA2_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L |
14744 | //MMEA2_MISC_AON |
14745 | #define MMEA2_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 |
14746 | #define MMEA2_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 |
14747 | #define MMEA2_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L |
14748 | #define MMEA2_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L |
14749 | //MMEA2_CE_ERR_STATUS_HI |
14750 | #define MMEA2_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 |
14751 | #define MMEA2_CE_ERR_STATUS_HI__RESERVED_FIELD0__SHIFT 0x1 |
14752 | #define MMEA2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 |
14753 | #define MMEA2_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 |
14754 | #define MMEA2_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 |
14755 | #define MMEA2_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a |
14756 | #define MMEA2_CE_ERR_STATUS_HI__RESERVED_FIELD1__SHIFT 0x1b |
14757 | #define MMEA2_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L |
14758 | #define MMEA2_CE_ERR_STATUS_HI__RESERVED_FIELD0_MASK 0x00000002L |
14759 | #define MMEA2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L |
14760 | #define MMEA2_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L |
14761 | #define MMEA2_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L |
14762 | #define MMEA2_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L |
14763 | #define MMEA2_CE_ERR_STATUS_HI__RESERVED_FIELD1_MASK 0xF8000000L |
14764 | |
14765 | // addressBlock: aid_mmhub_ea_mmeadec3 |
14766 | //MMEA3_DRAM_RD_CLI2GRP_MAP0 |
14767 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
14768 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
14769 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
14770 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
14771 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
14772 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
14773 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
14774 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
14775 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
14776 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
14777 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
14778 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
14779 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
14780 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
14781 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
14782 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
14783 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
14784 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
14785 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
14786 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
14787 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
14788 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
14789 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
14790 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
14791 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
14792 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
14793 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
14794 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
14795 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
14796 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
14797 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
14798 | #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
14799 | //MMEA3_DRAM_RD_CLI2GRP_MAP1 |
14800 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
14801 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
14802 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
14803 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
14804 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
14805 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
14806 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
14807 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
14808 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
14809 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
14810 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
14811 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
14812 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
14813 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
14814 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
14815 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
14816 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
14817 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
14818 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
14819 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
14820 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
14821 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
14822 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
14823 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
14824 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
14825 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
14826 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
14827 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
14828 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
14829 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
14830 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
14831 | #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
14832 | //MMEA3_DRAM_WR_CLI2GRP_MAP0 |
14833 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
14834 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
14835 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
14836 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
14837 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
14838 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
14839 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
14840 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
14841 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
14842 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
14843 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
14844 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
14845 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
14846 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
14847 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
14848 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
14849 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
14850 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
14851 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
14852 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
14853 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
14854 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
14855 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
14856 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
14857 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
14858 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
14859 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
14860 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
14861 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
14862 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
14863 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
14864 | #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
14865 | //MMEA3_DRAM_WR_CLI2GRP_MAP1 |
14866 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
14867 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
14868 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
14869 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
14870 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
14871 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
14872 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
14873 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
14874 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
14875 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
14876 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
14877 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
14878 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
14879 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
14880 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
14881 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
14882 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
14883 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
14884 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
14885 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
14886 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
14887 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
14888 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
14889 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
14890 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
14891 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
14892 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
14893 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
14894 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
14895 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
14896 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
14897 | #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
14898 | //MMEA3_DRAM_RD_GRP2VC_MAP |
14899 | #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
14900 | #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
14901 | #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
14902 | #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
14903 | #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
14904 | #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
14905 | #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
14906 | #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
14907 | //MMEA3_DRAM_WR_GRP2VC_MAP |
14908 | #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
14909 | #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
14910 | #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
14911 | #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
14912 | #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
14913 | #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
14914 | #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
14915 | #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
14916 | //MMEA3_DRAM_RD_LAZY |
14917 | #define MMEA3_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 |
14918 | #define MMEA3_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 |
14919 | #define MMEA3_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 |
14920 | #define MMEA3_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 |
14921 | #define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
14922 | #define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
14923 | #define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
14924 | #define MMEA3_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L |
14925 | #define MMEA3_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L |
14926 | #define MMEA3_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
14927 | #define MMEA3_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
14928 | #define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
14929 | #define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
14930 | #define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
14931 | //MMEA3_DRAM_WR_LAZY |
14932 | #define MMEA3_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 |
14933 | #define MMEA3_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 |
14934 | #define MMEA3_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 |
14935 | #define MMEA3_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 |
14936 | #define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
14937 | #define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
14938 | #define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
14939 | #define MMEA3_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L |
14940 | #define MMEA3_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L |
14941 | #define MMEA3_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
14942 | #define MMEA3_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
14943 | #define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
14944 | #define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
14945 | #define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
14946 | //MMEA3_DRAM_RD_CAM_CNTL |
14947 | #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
14948 | #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
14949 | #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
14950 | #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
14951 | #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
14952 | #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
14953 | #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
14954 | #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
14955 | #define MMEA3_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
14956 | #define MMEA3_DRAM_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d |
14957 | #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
14958 | #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
14959 | #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
14960 | #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
14961 | #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
14962 | #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
14963 | #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
14964 | #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
14965 | #define MMEA3_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
14966 | #define MMEA3_DRAM_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L |
14967 | //MMEA3_DRAM_WR_CAM_CNTL |
14968 | #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
14969 | #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
14970 | #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
14971 | #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
14972 | #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
14973 | #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
14974 | #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
14975 | #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
14976 | #define MMEA3_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
14977 | #define MMEA3_DRAM_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d |
14978 | #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
14979 | #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
14980 | #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
14981 | #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
14982 | #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
14983 | #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
14984 | #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
14985 | #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
14986 | #define MMEA3_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
14987 | #define MMEA3_DRAM_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L |
14988 | //MMEA3_DRAM_PAGE_BURST |
14989 | #define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 |
14990 | #define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 |
14991 | #define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 |
14992 | #define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 |
14993 | #define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
14994 | #define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
14995 | #define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
14996 | #define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
14997 | //MMEA3_DRAM_RD_PRI_AGE |
14998 | #define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
14999 | #define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
15000 | #define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
15001 | #define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
15002 | #define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
15003 | #define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
15004 | #define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
15005 | #define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
15006 | #define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
15007 | #define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
15008 | #define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
15009 | #define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
15010 | #define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
15011 | #define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
15012 | #define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
15013 | #define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
15014 | //MMEA3_DRAM_WR_PRI_AGE |
15015 | #define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
15016 | #define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
15017 | #define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
15018 | #define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
15019 | #define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
15020 | #define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
15021 | #define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
15022 | #define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
15023 | #define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
15024 | #define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
15025 | #define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
15026 | #define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
15027 | #define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
15028 | #define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
15029 | #define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
15030 | #define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
15031 | //MMEA3_DRAM_RD_PRI_QUEUING |
15032 | #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
15033 | #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
15034 | #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
15035 | #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
15036 | #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
15037 | #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
15038 | #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
15039 | #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
15040 | //MMEA3_DRAM_WR_PRI_QUEUING |
15041 | #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
15042 | #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
15043 | #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
15044 | #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
15045 | #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
15046 | #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
15047 | #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
15048 | #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
15049 | //MMEA3_DRAM_RD_PRI_FIXED |
15050 | #define MMEA3_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
15051 | #define MMEA3_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
15052 | #define MMEA3_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
15053 | #define MMEA3_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
15054 | #define MMEA3_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
15055 | #define MMEA3_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
15056 | #define MMEA3_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
15057 | #define MMEA3_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
15058 | //MMEA3_DRAM_WR_PRI_FIXED |
15059 | #define MMEA3_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
15060 | #define MMEA3_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
15061 | #define MMEA3_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
15062 | #define MMEA3_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
15063 | #define MMEA3_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
15064 | #define MMEA3_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
15065 | #define MMEA3_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
15066 | #define MMEA3_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
15067 | //MMEA3_DRAM_RD_PRI_URGENCY |
15068 | #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
15069 | #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
15070 | #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
15071 | #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
15072 | #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
15073 | #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
15074 | #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
15075 | #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
15076 | #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
15077 | #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
15078 | #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
15079 | #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
15080 | #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
15081 | #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
15082 | #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
15083 | #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
15084 | //MMEA3_DRAM_WR_PRI_URGENCY |
15085 | #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
15086 | #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
15087 | #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
15088 | #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
15089 | #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
15090 | #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
15091 | #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
15092 | #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
15093 | #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
15094 | #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
15095 | #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
15096 | #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
15097 | #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
15098 | #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
15099 | #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
15100 | #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
15101 | //MMEA3_DRAM_RD_PRI_QUANT_PRI1 |
15102 | #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
15103 | #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
15104 | #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
15105 | #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
15106 | #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
15107 | #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
15108 | #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
15109 | #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
15110 | //MMEA3_DRAM_RD_PRI_QUANT_PRI2 |
15111 | #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
15112 | #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
15113 | #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
15114 | #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
15115 | #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
15116 | #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
15117 | #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
15118 | #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
15119 | //MMEA3_DRAM_RD_PRI_QUANT_PRI3 |
15120 | #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
15121 | #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
15122 | #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
15123 | #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
15124 | #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
15125 | #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
15126 | #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
15127 | #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
15128 | //MMEA3_DRAM_WR_PRI_QUANT_PRI1 |
15129 | #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
15130 | #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
15131 | #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
15132 | #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
15133 | #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
15134 | #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
15135 | #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
15136 | #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
15137 | //MMEA3_DRAM_WR_PRI_QUANT_PRI2 |
15138 | #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
15139 | #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
15140 | #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
15141 | #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
15142 | #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
15143 | #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
15144 | #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
15145 | #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
15146 | //MMEA3_DRAM_WR_PRI_QUANT_PRI3 |
15147 | #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
15148 | #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
15149 | #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
15150 | #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
15151 | #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
15152 | #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
15153 | #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
15154 | #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
15155 | //MMEA3_GMI_RD_CLI2GRP_MAP0 |
15156 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
15157 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
15158 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
15159 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
15160 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
15161 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
15162 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
15163 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
15164 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
15165 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
15166 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
15167 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
15168 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
15169 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
15170 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
15171 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
15172 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
15173 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
15174 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
15175 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
15176 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
15177 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
15178 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
15179 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
15180 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
15181 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
15182 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
15183 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
15184 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
15185 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
15186 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
15187 | #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
15188 | //MMEA3_GMI_RD_CLI2GRP_MAP1 |
15189 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
15190 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
15191 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
15192 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
15193 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
15194 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
15195 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
15196 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
15197 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
15198 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
15199 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
15200 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
15201 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
15202 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
15203 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
15204 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
15205 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
15206 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
15207 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
15208 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
15209 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
15210 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
15211 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
15212 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
15213 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
15214 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
15215 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
15216 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
15217 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
15218 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
15219 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
15220 | #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
15221 | //MMEA3_GMI_WR_CLI2GRP_MAP0 |
15222 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
15223 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
15224 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
15225 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
15226 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
15227 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
15228 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
15229 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
15230 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
15231 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
15232 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
15233 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
15234 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
15235 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
15236 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
15237 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
15238 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
15239 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
15240 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
15241 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
15242 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
15243 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
15244 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
15245 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
15246 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
15247 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
15248 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
15249 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
15250 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
15251 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
15252 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
15253 | #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
15254 | //MMEA3_GMI_WR_CLI2GRP_MAP1 |
15255 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
15256 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
15257 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
15258 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
15259 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
15260 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
15261 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
15262 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
15263 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
15264 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
15265 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
15266 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
15267 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
15268 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
15269 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
15270 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
15271 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
15272 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
15273 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
15274 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
15275 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
15276 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
15277 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
15278 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
15279 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
15280 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
15281 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
15282 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
15283 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
15284 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
15285 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
15286 | #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
15287 | //MMEA3_GMI_RD_GRP2VC_MAP |
15288 | #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
15289 | #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
15290 | #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
15291 | #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
15292 | #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
15293 | #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
15294 | #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
15295 | #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
15296 | //MMEA3_GMI_WR_GRP2VC_MAP |
15297 | #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
15298 | #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
15299 | #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
15300 | #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
15301 | #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
15302 | #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
15303 | #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
15304 | #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
15305 | //MMEA3_GMI_RD_LAZY |
15306 | #define MMEA3_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 |
15307 | #define MMEA3_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 |
15308 | #define MMEA3_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 |
15309 | #define MMEA3_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 |
15310 | #define MMEA3_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
15311 | #define MMEA3_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
15312 | #define MMEA3_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
15313 | #define MMEA3_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L |
15314 | #define MMEA3_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L |
15315 | #define MMEA3_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
15316 | #define MMEA3_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
15317 | #define MMEA3_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
15318 | #define MMEA3_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
15319 | #define MMEA3_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
15320 | //MMEA3_GMI_WR_LAZY |
15321 | #define MMEA3_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 |
15322 | #define MMEA3_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 |
15323 | #define MMEA3_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 |
15324 | #define MMEA3_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 |
15325 | #define MMEA3_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
15326 | #define MMEA3_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
15327 | #define MMEA3_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
15328 | #define MMEA3_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L |
15329 | #define MMEA3_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L |
15330 | #define MMEA3_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
15331 | #define MMEA3_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
15332 | #define MMEA3_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
15333 | #define MMEA3_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
15334 | #define MMEA3_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
15335 | //MMEA3_GMI_RD_CAM_CNTL |
15336 | #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
15337 | #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
15338 | #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
15339 | #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
15340 | #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
15341 | #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
15342 | #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
15343 | #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
15344 | #define MMEA3_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
15345 | #define MMEA3_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d |
15346 | #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
15347 | #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
15348 | #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
15349 | #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
15350 | #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
15351 | #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
15352 | #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
15353 | #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
15354 | #define MMEA3_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
15355 | #define MMEA3_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L |
15356 | //MMEA3_GMI_WR_CAM_CNTL |
15357 | #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
15358 | #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
15359 | #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
15360 | #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
15361 | #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
15362 | #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
15363 | #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
15364 | #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
15365 | #define MMEA3_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
15366 | #define MMEA3_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d |
15367 | #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
15368 | #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
15369 | #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
15370 | #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
15371 | #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
15372 | #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
15373 | #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
15374 | #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
15375 | #define MMEA3_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
15376 | #define MMEA3_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L |
15377 | //MMEA3_GMI_PAGE_BURST |
15378 | #define MMEA3_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 |
15379 | #define MMEA3_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 |
15380 | #define MMEA3_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 |
15381 | #define MMEA3_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 |
15382 | #define MMEA3_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
15383 | #define MMEA3_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
15384 | #define MMEA3_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
15385 | #define MMEA3_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
15386 | //MMEA3_GMI_RD_PRI_AGE |
15387 | #define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
15388 | #define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
15389 | #define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
15390 | #define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
15391 | #define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
15392 | #define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
15393 | #define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
15394 | #define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
15395 | #define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
15396 | #define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
15397 | #define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
15398 | #define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
15399 | #define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
15400 | #define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
15401 | #define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
15402 | #define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
15403 | //MMEA3_GMI_WR_PRI_AGE |
15404 | #define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
15405 | #define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
15406 | #define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
15407 | #define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
15408 | #define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
15409 | #define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
15410 | #define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
15411 | #define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
15412 | #define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
15413 | #define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
15414 | #define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
15415 | #define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
15416 | #define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
15417 | #define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
15418 | #define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
15419 | #define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
15420 | //MMEA3_GMI_RD_PRI_QUEUING |
15421 | #define MMEA3_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
15422 | #define MMEA3_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
15423 | #define MMEA3_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
15424 | #define MMEA3_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
15425 | #define MMEA3_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
15426 | #define MMEA3_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
15427 | #define MMEA3_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
15428 | #define MMEA3_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
15429 | //MMEA3_GMI_WR_PRI_QUEUING |
15430 | #define MMEA3_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
15431 | #define MMEA3_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
15432 | #define MMEA3_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
15433 | #define MMEA3_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
15434 | #define MMEA3_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
15435 | #define MMEA3_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
15436 | #define MMEA3_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
15437 | #define MMEA3_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
15438 | //MMEA3_GMI_RD_PRI_FIXED |
15439 | #define MMEA3_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
15440 | #define MMEA3_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
15441 | #define MMEA3_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
15442 | #define MMEA3_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
15443 | #define MMEA3_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
15444 | #define MMEA3_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
15445 | #define MMEA3_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
15446 | #define MMEA3_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
15447 | //MMEA3_GMI_WR_PRI_FIXED |
15448 | #define MMEA3_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
15449 | #define MMEA3_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
15450 | #define MMEA3_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
15451 | #define MMEA3_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
15452 | #define MMEA3_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
15453 | #define MMEA3_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
15454 | #define MMEA3_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
15455 | #define MMEA3_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
15456 | //MMEA3_GMI_RD_PRI_URGENCY |
15457 | #define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
15458 | #define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
15459 | #define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
15460 | #define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
15461 | #define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
15462 | #define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
15463 | #define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
15464 | #define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
15465 | #define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
15466 | #define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
15467 | #define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
15468 | #define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
15469 | #define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
15470 | #define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
15471 | #define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
15472 | #define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
15473 | //MMEA3_GMI_WR_PRI_URGENCY |
15474 | #define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
15475 | #define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
15476 | #define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
15477 | #define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
15478 | #define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
15479 | #define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
15480 | #define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
15481 | #define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
15482 | #define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
15483 | #define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
15484 | #define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
15485 | #define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
15486 | #define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
15487 | #define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
15488 | #define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
15489 | #define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
15490 | //MMEA3_GMI_RD_PRI_URGENCY_MASKING |
15491 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
15492 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
15493 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
15494 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
15495 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
15496 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
15497 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
15498 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
15499 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
15500 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
15501 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
15502 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
15503 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
15504 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
15505 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
15506 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
15507 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
15508 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
15509 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
15510 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
15511 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
15512 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
15513 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
15514 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
15515 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
15516 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
15517 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
15518 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
15519 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
15520 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
15521 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
15522 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
15523 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
15524 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
15525 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
15526 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
15527 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
15528 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
15529 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
15530 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
15531 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
15532 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
15533 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
15534 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
15535 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
15536 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
15537 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
15538 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
15539 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
15540 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
15541 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
15542 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
15543 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
15544 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
15545 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
15546 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
15547 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
15548 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
15549 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
15550 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
15551 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
15552 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
15553 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
15554 | #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
15555 | //MMEA3_GMI_WR_PRI_URGENCY_MASKING |
15556 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
15557 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
15558 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
15559 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
15560 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
15561 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
15562 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
15563 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
15564 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
15565 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
15566 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
15567 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
15568 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
15569 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
15570 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
15571 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
15572 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
15573 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
15574 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
15575 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
15576 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
15577 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
15578 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
15579 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
15580 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
15581 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
15582 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
15583 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
15584 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
15585 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
15586 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
15587 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
15588 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
15589 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
15590 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
15591 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
15592 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
15593 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
15594 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
15595 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
15596 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
15597 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
15598 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
15599 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
15600 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
15601 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
15602 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
15603 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
15604 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
15605 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
15606 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
15607 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
15608 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
15609 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
15610 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
15611 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
15612 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
15613 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
15614 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
15615 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
15616 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
15617 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
15618 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
15619 | #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
15620 | //MMEA3_GMI_RD_PRI_QUANT_PRI1 |
15621 | #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
15622 | #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
15623 | #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
15624 | #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
15625 | #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
15626 | #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
15627 | #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
15628 | #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
15629 | //MMEA3_GMI_RD_PRI_QUANT_PRI2 |
15630 | #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
15631 | #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
15632 | #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
15633 | #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
15634 | #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
15635 | #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
15636 | #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
15637 | #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
15638 | //MMEA3_GMI_RD_PRI_QUANT_PRI3 |
15639 | #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
15640 | #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
15641 | #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
15642 | #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
15643 | #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
15644 | #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
15645 | #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
15646 | #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
15647 | //MMEA3_GMI_WR_PRI_QUANT_PRI1 |
15648 | #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
15649 | #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
15650 | #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
15651 | #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
15652 | #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
15653 | #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
15654 | #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
15655 | #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
15656 | //MMEA3_GMI_WR_PRI_QUANT_PRI2 |
15657 | #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
15658 | #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
15659 | #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
15660 | #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
15661 | #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
15662 | #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
15663 | #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
15664 | #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
15665 | //MMEA3_GMI_WR_PRI_QUANT_PRI3 |
15666 | #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
15667 | #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
15668 | #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
15669 | #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
15670 | #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
15671 | #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
15672 | #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
15673 | #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
15674 | //MMEA3_IO_RD_CLI2GRP_MAP0 |
15675 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
15676 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
15677 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
15678 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
15679 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
15680 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
15681 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
15682 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
15683 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
15684 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
15685 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
15686 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
15687 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
15688 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
15689 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
15690 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
15691 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
15692 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
15693 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
15694 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
15695 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
15696 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
15697 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
15698 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
15699 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
15700 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
15701 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
15702 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
15703 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
15704 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
15705 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
15706 | #define MMEA3_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
15707 | //MMEA3_IO_RD_CLI2GRP_MAP1 |
15708 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
15709 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
15710 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
15711 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
15712 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
15713 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
15714 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
15715 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
15716 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
15717 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
15718 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
15719 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
15720 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
15721 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
15722 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
15723 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
15724 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
15725 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
15726 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
15727 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
15728 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
15729 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
15730 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
15731 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
15732 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
15733 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
15734 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
15735 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
15736 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
15737 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
15738 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
15739 | #define MMEA3_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
15740 | //MMEA3_IO_WR_CLI2GRP_MAP0 |
15741 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
15742 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
15743 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
15744 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
15745 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
15746 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
15747 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
15748 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
15749 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
15750 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
15751 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
15752 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
15753 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
15754 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
15755 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
15756 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
15757 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
15758 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
15759 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
15760 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
15761 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
15762 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
15763 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
15764 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
15765 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
15766 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
15767 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
15768 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
15769 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
15770 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
15771 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
15772 | #define MMEA3_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
15773 | //MMEA3_IO_WR_CLI2GRP_MAP1 |
15774 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
15775 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
15776 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
15777 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
15778 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
15779 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
15780 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
15781 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
15782 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
15783 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
15784 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
15785 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
15786 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
15787 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
15788 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
15789 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
15790 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
15791 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
15792 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
15793 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
15794 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
15795 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
15796 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
15797 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
15798 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
15799 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
15800 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
15801 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
15802 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
15803 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
15804 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
15805 | #define MMEA3_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
15806 | //MMEA3_IO_RD_COMBINE_FLUSH |
15807 | #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
15808 | #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
15809 | #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
15810 | #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
15811 | #define MMEA3_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 |
15812 | #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
15813 | #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
15814 | #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
15815 | #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
15816 | #define MMEA3_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L |
15817 | //MMEA3_IO_WR_COMBINE_FLUSH |
15818 | #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
15819 | #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
15820 | #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
15821 | #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
15822 | #define MMEA3_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 |
15823 | #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
15824 | #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
15825 | #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
15826 | #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
15827 | #define MMEA3_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L |
15828 | //MMEA3_IO_GROUP_BURST |
15829 | #define MMEA3_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 |
15830 | #define MMEA3_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 |
15831 | #define MMEA3_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 |
15832 | #define MMEA3_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 |
15833 | #define MMEA3_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
15834 | #define MMEA3_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
15835 | #define MMEA3_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
15836 | #define MMEA3_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
15837 | //MMEA3_IO_RD_PRI_AGE |
15838 | #define MMEA3_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
15839 | #define MMEA3_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
15840 | #define MMEA3_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
15841 | #define MMEA3_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
15842 | #define MMEA3_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
15843 | #define MMEA3_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
15844 | #define MMEA3_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
15845 | #define MMEA3_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
15846 | #define MMEA3_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
15847 | #define MMEA3_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
15848 | #define MMEA3_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
15849 | #define MMEA3_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
15850 | #define MMEA3_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
15851 | #define MMEA3_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
15852 | #define MMEA3_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
15853 | #define MMEA3_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
15854 | //MMEA3_IO_WR_PRI_AGE |
15855 | #define MMEA3_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
15856 | #define MMEA3_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
15857 | #define MMEA3_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
15858 | #define MMEA3_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
15859 | #define MMEA3_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
15860 | #define MMEA3_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
15861 | #define MMEA3_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
15862 | #define MMEA3_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
15863 | #define MMEA3_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
15864 | #define MMEA3_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
15865 | #define MMEA3_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
15866 | #define MMEA3_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
15867 | #define MMEA3_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
15868 | #define MMEA3_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
15869 | #define MMEA3_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
15870 | #define MMEA3_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
15871 | //MMEA3_IO_RD_PRI_QUEUING |
15872 | #define MMEA3_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
15873 | #define MMEA3_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
15874 | #define MMEA3_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
15875 | #define MMEA3_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
15876 | #define MMEA3_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
15877 | #define MMEA3_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
15878 | #define MMEA3_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
15879 | #define MMEA3_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
15880 | //MMEA3_IO_WR_PRI_QUEUING |
15881 | #define MMEA3_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
15882 | #define MMEA3_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
15883 | #define MMEA3_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
15884 | #define MMEA3_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
15885 | #define MMEA3_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
15886 | #define MMEA3_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
15887 | #define MMEA3_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
15888 | #define MMEA3_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
15889 | //MMEA3_IO_RD_PRI_FIXED |
15890 | #define MMEA3_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
15891 | #define MMEA3_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
15892 | #define MMEA3_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
15893 | #define MMEA3_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
15894 | #define MMEA3_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
15895 | #define MMEA3_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
15896 | #define MMEA3_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
15897 | #define MMEA3_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
15898 | //MMEA3_IO_WR_PRI_FIXED |
15899 | #define MMEA3_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
15900 | #define MMEA3_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
15901 | #define MMEA3_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
15902 | #define MMEA3_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
15903 | #define MMEA3_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
15904 | #define MMEA3_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
15905 | #define MMEA3_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
15906 | #define MMEA3_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
15907 | //MMEA3_IO_RD_PRI_URGENCY |
15908 | #define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
15909 | #define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
15910 | #define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
15911 | #define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
15912 | #define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
15913 | #define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
15914 | #define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
15915 | #define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
15916 | #define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
15917 | #define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
15918 | #define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
15919 | #define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
15920 | #define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
15921 | #define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
15922 | #define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
15923 | #define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
15924 | //MMEA3_IO_WR_PRI_URGENCY |
15925 | #define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
15926 | #define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
15927 | #define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
15928 | #define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
15929 | #define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
15930 | #define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
15931 | #define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
15932 | #define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
15933 | #define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
15934 | #define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
15935 | #define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
15936 | #define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
15937 | #define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
15938 | #define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
15939 | #define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
15940 | #define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
15941 | //MMEA3_IO_RD_PRI_URGENCY_MASKING |
15942 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
15943 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
15944 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
15945 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
15946 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
15947 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
15948 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
15949 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
15950 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
15951 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
15952 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
15953 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
15954 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
15955 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
15956 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
15957 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
15958 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
15959 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
15960 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
15961 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
15962 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
15963 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
15964 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
15965 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
15966 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
15967 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
15968 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
15969 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
15970 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
15971 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
15972 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
15973 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
15974 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
15975 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
15976 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
15977 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
15978 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
15979 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
15980 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
15981 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
15982 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
15983 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
15984 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
15985 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
15986 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
15987 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
15988 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
15989 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
15990 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
15991 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
15992 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
15993 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
15994 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
15995 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
15996 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
15997 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
15998 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
15999 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
16000 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
16001 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
16002 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
16003 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
16004 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
16005 | #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
16006 | //MMEA3_IO_WR_PRI_URGENCY_MASKING |
16007 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
16008 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
16009 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
16010 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
16011 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
16012 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
16013 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
16014 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
16015 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
16016 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
16017 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
16018 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
16019 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
16020 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
16021 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
16022 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
16023 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
16024 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
16025 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
16026 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
16027 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
16028 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
16029 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
16030 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
16031 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
16032 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
16033 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
16034 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
16035 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
16036 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
16037 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
16038 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
16039 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
16040 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
16041 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
16042 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
16043 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
16044 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
16045 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
16046 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
16047 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
16048 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
16049 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
16050 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
16051 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
16052 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
16053 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
16054 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
16055 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
16056 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
16057 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
16058 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
16059 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
16060 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
16061 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
16062 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
16063 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
16064 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
16065 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
16066 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
16067 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
16068 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
16069 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
16070 | #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
16071 | //MMEA3_IO_RD_PRI_QUANT_PRI1 |
16072 | #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
16073 | #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
16074 | #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
16075 | #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
16076 | #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
16077 | #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
16078 | #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
16079 | #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
16080 | //MMEA3_IO_RD_PRI_QUANT_PRI2 |
16081 | #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
16082 | #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
16083 | #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
16084 | #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
16085 | #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
16086 | #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
16087 | #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
16088 | #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
16089 | //MMEA3_IO_RD_PRI_QUANT_PRI3 |
16090 | #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
16091 | #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
16092 | #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
16093 | #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
16094 | #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
16095 | #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
16096 | #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
16097 | #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
16098 | //MMEA3_IO_WR_PRI_QUANT_PRI1 |
16099 | #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
16100 | #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
16101 | #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
16102 | #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
16103 | #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
16104 | #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
16105 | #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
16106 | #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
16107 | //MMEA3_IO_WR_PRI_QUANT_PRI2 |
16108 | #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
16109 | #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
16110 | #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
16111 | #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
16112 | #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
16113 | #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
16114 | #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
16115 | #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
16116 | //MMEA3_IO_WR_PRI_QUANT_PRI3 |
16117 | #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
16118 | #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
16119 | #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
16120 | #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
16121 | #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
16122 | #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
16123 | #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
16124 | #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
16125 | //MMEA3_SDP_ARB_DRAM |
16126 | #define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 |
16127 | #define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 |
16128 | #define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 |
16129 | #define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 |
16130 | #define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 |
16131 | #define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 |
16132 | #define MMEA3_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 |
16133 | #define MMEA3_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 |
16134 | #define MMEA3_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING__SHIFT 0x16 |
16135 | #define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL |
16136 | #define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L |
16137 | #define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L |
16138 | #define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L |
16139 | #define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L |
16140 | #define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L |
16141 | #define MMEA3_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L |
16142 | #define MMEA3_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L |
16143 | #define MMEA3_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING_MASK 0x00400000L |
16144 | //MMEA3_SDP_ARB_GMI |
16145 | #define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 |
16146 | #define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 |
16147 | #define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 |
16148 | #define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 |
16149 | #define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 |
16150 | #define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 |
16151 | #define MMEA3_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 |
16152 | #define MMEA3_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 |
16153 | #define MMEA3_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 |
16154 | #define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL |
16155 | #define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L |
16156 | #define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L |
16157 | #define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L |
16158 | #define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L |
16159 | #define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L |
16160 | #define MMEA3_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L |
16161 | #define MMEA3_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L |
16162 | #define MMEA3_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L |
16163 | //MMEA3_SDP_ARB_FINAL |
16164 | #define MMEA3_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 |
16165 | #define MMEA3_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 |
16166 | #define MMEA3_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa |
16167 | #define MMEA3_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf |
16168 | #define MMEA3_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 |
16169 | #define MMEA3_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 |
16170 | #define MMEA3_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 |
16171 | #define MMEA3_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 |
16172 | #define MMEA3_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 |
16173 | #define MMEA3_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 |
16174 | #define MMEA3_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 |
16175 | #define MMEA3_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 |
16176 | #define MMEA3_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 |
16177 | #define MMEA3_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a |
16178 | #define MMEA3_SDP_ARB_FINAL__DRAM_BURST_STRETCH__SHIFT 0x1b |
16179 | #define MMEA3_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1c |
16180 | #define MMEA3_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL |
16181 | #define MMEA3_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L |
16182 | #define MMEA3_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L |
16183 | #define MMEA3_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L |
16184 | #define MMEA3_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L |
16185 | #define MMEA3_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L |
16186 | #define MMEA3_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L |
16187 | #define MMEA3_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L |
16188 | #define MMEA3_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L |
16189 | #define MMEA3_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L |
16190 | #define MMEA3_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L |
16191 | #define MMEA3_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L |
16192 | #define MMEA3_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L |
16193 | #define MMEA3_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L |
16194 | #define MMEA3_SDP_ARB_FINAL__DRAM_BURST_STRETCH_MASK 0x08000000L |
16195 | #define MMEA3_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x10000000L |
16196 | //MMEA3_SDP_DRAM_PRIORITY |
16197 | #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 |
16198 | #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 |
16199 | #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 |
16200 | #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc |
16201 | #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 |
16202 | #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 |
16203 | #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 |
16204 | #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c |
16205 | #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL |
16206 | #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L |
16207 | #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L |
16208 | #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L |
16209 | #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L |
16210 | #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L |
16211 | #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L |
16212 | #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L |
16213 | //MMEA3_SDP_GMI_PRIORITY |
16214 | #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 |
16215 | #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 |
16216 | #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 |
16217 | #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc |
16218 | #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 |
16219 | #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 |
16220 | #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 |
16221 | #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c |
16222 | #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL |
16223 | #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L |
16224 | #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L |
16225 | #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L |
16226 | #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L |
16227 | #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L |
16228 | #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L |
16229 | #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L |
16230 | //MMEA3_SDP_IO_PRIORITY |
16231 | #define MMEA3_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 |
16232 | #define MMEA3_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 |
16233 | #define MMEA3_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 |
16234 | #define MMEA3_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc |
16235 | #define MMEA3_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 |
16236 | #define MMEA3_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 |
16237 | #define MMEA3_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 |
16238 | #define MMEA3_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c |
16239 | #define MMEA3_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL |
16240 | #define MMEA3_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L |
16241 | #define MMEA3_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L |
16242 | #define MMEA3_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L |
16243 | #define MMEA3_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L |
16244 | #define MMEA3_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L |
16245 | #define MMEA3_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L |
16246 | #define MMEA3_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L |
16247 | //MMEA3_SDP_CREDITS |
16248 | #define MMEA3_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 |
16249 | #define MMEA3_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 |
16250 | #define MMEA3_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 |
16251 | #define MMEA3_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL |
16252 | #define MMEA3_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L |
16253 | #define MMEA3_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L |
16254 | //MMEA3_SDP_TAG_RESERVE0 |
16255 | #define MMEA3_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 |
16256 | #define MMEA3_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 |
16257 | #define MMEA3_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 |
16258 | #define MMEA3_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 |
16259 | #define MMEA3_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL |
16260 | #define MMEA3_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L |
16261 | #define MMEA3_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L |
16262 | #define MMEA3_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L |
16263 | //MMEA3_SDP_TAG_RESERVE1 |
16264 | #define MMEA3_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 |
16265 | #define MMEA3_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 |
16266 | #define MMEA3_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 |
16267 | #define MMEA3_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 |
16268 | #define MMEA3_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL |
16269 | #define MMEA3_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L |
16270 | #define MMEA3_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L |
16271 | #define MMEA3_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L |
16272 | //MMEA3_SDP_VCC_RESERVE0 |
16273 | #define MMEA3_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 |
16274 | #define MMEA3_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 |
16275 | #define MMEA3_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc |
16276 | #define MMEA3_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 |
16277 | #define MMEA3_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 |
16278 | #define MMEA3_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL |
16279 | #define MMEA3_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L |
16280 | #define MMEA3_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L |
16281 | #define MMEA3_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L |
16282 | #define MMEA3_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L |
16283 | //MMEA3_SDP_VCC_RESERVE1 |
16284 | #define MMEA3_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 |
16285 | #define MMEA3_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 |
16286 | #define MMEA3_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc |
16287 | #define MMEA3_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f |
16288 | #define MMEA3_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL |
16289 | #define MMEA3_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L |
16290 | #define MMEA3_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L |
16291 | #define MMEA3_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L |
16292 | //MMEA3_SDP_VCD_RESERVE0 |
16293 | #define MMEA3_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 |
16294 | #define MMEA3_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 |
16295 | #define MMEA3_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc |
16296 | #define MMEA3_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 |
16297 | #define MMEA3_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 |
16298 | #define MMEA3_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL |
16299 | #define MMEA3_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L |
16300 | #define MMEA3_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L |
16301 | #define MMEA3_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L |
16302 | #define MMEA3_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L |
16303 | //MMEA3_SDP_VCD_RESERVE1 |
16304 | #define MMEA3_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 |
16305 | #define MMEA3_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 |
16306 | #define MMEA3_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc |
16307 | #define MMEA3_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f |
16308 | #define MMEA3_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL |
16309 | #define MMEA3_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L |
16310 | #define MMEA3_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L |
16311 | #define MMEA3_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L |
16312 | //MMEA3_SDP_REQ_CNTL |
16313 | #define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 |
16314 | #define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 |
16315 | #define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 |
16316 | #define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 |
16317 | #define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 |
16318 | #define MMEA3_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 |
16319 | #define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 |
16320 | #define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 |
16321 | #define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa |
16322 | #define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L |
16323 | #define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L |
16324 | #define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L |
16325 | #define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L |
16326 | #define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L |
16327 | #define MMEA3_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L |
16328 | #define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L |
16329 | #define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L |
16330 | #define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L |
16331 | //MMEA3_MISC |
16332 | #define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 |
16333 | #define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 |
16334 | #define MMEA3_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 |
16335 | #define MMEA3_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 |
16336 | #define MMEA3_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 |
16337 | #define MMEA3_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 |
16338 | #define MMEA3_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 |
16339 | #define MMEA3_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 |
16340 | #define MMEA3_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 |
16341 | #define MMEA3_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 |
16342 | #define MMEA3_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa |
16343 | #define MMEA3_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb |
16344 | #define MMEA3_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc |
16345 | #define MMEA3_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd |
16346 | #define MMEA3_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe |
16347 | #define MMEA3_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf |
16348 | #define MMEA3_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 |
16349 | #define MMEA3_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 |
16350 | #define MMEA3_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 |
16351 | #define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a |
16352 | #define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b |
16353 | #define MMEA3_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c |
16354 | #define MMEA3_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d |
16355 | #define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e |
16356 | #define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f |
16357 | #define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L |
16358 | #define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L |
16359 | #define MMEA3_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L |
16360 | #define MMEA3_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L |
16361 | #define MMEA3_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L |
16362 | #define MMEA3_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L |
16363 | #define MMEA3_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L |
16364 | #define MMEA3_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L |
16365 | #define MMEA3_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L |
16366 | #define MMEA3_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L |
16367 | #define MMEA3_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L |
16368 | #define MMEA3_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L |
16369 | #define MMEA3_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L |
16370 | #define MMEA3_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L |
16371 | #define MMEA3_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L |
16372 | #define MMEA3_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L |
16373 | #define MMEA3_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L |
16374 | #define MMEA3_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L |
16375 | #define MMEA3_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L |
16376 | #define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L |
16377 | #define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L |
16378 | #define MMEA3_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L |
16379 | #define MMEA3_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L |
16380 | #define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L |
16381 | #define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L |
16382 | //MMEA3_LATENCY_SAMPLING |
16383 | #define MMEA3_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 |
16384 | #define MMEA3_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 |
16385 | #define MMEA3_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 |
16386 | #define MMEA3_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 |
16387 | #define MMEA3_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 |
16388 | #define MMEA3_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 |
16389 | #define MMEA3_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 |
16390 | #define MMEA3_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 |
16391 | #define MMEA3_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 |
16392 | #define MMEA3_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 |
16393 | #define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa |
16394 | #define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb |
16395 | #define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc |
16396 | #define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd |
16397 | #define MMEA3_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe |
16398 | #define MMEA3_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 |
16399 | #define MMEA3_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L |
16400 | #define MMEA3_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L |
16401 | #define MMEA3_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L |
16402 | #define MMEA3_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L |
16403 | #define MMEA3_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L |
16404 | #define MMEA3_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L |
16405 | #define MMEA3_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L |
16406 | #define MMEA3_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L |
16407 | #define MMEA3_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L |
16408 | #define MMEA3_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L |
16409 | #define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L |
16410 | #define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L |
16411 | #define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L |
16412 | #define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L |
16413 | #define MMEA3_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L |
16414 | #define MMEA3_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L |
16415 | //MMEA3_PERFCOUNTER_LO |
16416 | #define MMEA3_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
16417 | #define MMEA3_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
16418 | //MMEA3_PERFCOUNTER_HI |
16419 | #define MMEA3_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
16420 | #define MMEA3_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
16421 | #define MMEA3_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
16422 | #define MMEA3_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
16423 | //MMEA3_PERFCOUNTER0_CFG |
16424 | #define MMEA3_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
16425 | #define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
16426 | #define MMEA3_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
16427 | #define MMEA3_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
16428 | #define MMEA3_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
16429 | #define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
16430 | #define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
16431 | #define MMEA3_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
16432 | #define MMEA3_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
16433 | #define MMEA3_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
16434 | //MMEA3_PERFCOUNTER1_CFG |
16435 | #define MMEA3_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
16436 | #define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
16437 | #define MMEA3_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
16438 | #define MMEA3_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
16439 | #define MMEA3_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
16440 | #define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
16441 | #define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
16442 | #define MMEA3_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
16443 | #define MMEA3_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
16444 | #define MMEA3_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
16445 | //MMEA3_PERFCOUNTER_RSLT_CNTL |
16446 | #define MMEA3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
16447 | #define MMEA3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
16448 | #define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
16449 | #define MMEA3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
16450 | #define MMEA3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
16451 | #define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
16452 | #define MMEA3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
16453 | #define MMEA3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
16454 | #define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
16455 | #define MMEA3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
16456 | #define MMEA3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
16457 | #define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
16458 | //MMEA3_UE_ERR_STATUS_LO |
16459 | #define MMEA3_UE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT 0x0 |
16460 | #define MMEA3_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 |
16461 | #define MMEA3_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 |
16462 | #define MMEA3_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 |
16463 | #define MMEA3_UE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK 0x00000001L |
16464 | #define MMEA3_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L |
16465 | #define MMEA3_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL |
16466 | #define MMEA3_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L |
16467 | //MMEA3_UE_ERR_STATUS_HI |
16468 | #define MMEA3_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 |
16469 | #define MMEA3_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 |
16470 | #define MMEA3_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 |
16471 | #define MMEA3_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 |
16472 | #define MMEA3_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 |
16473 | #define MMEA3_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a |
16474 | #define MMEA3_UE_ERR_STATUS_HI__RESERVED_FIELD__SHIFT 0x1d |
16475 | #define MMEA3_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L |
16476 | #define MMEA3_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L |
16477 | #define MMEA3_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L |
16478 | #define MMEA3_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L |
16479 | #define MMEA3_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L |
16480 | #define MMEA3_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L |
16481 | #define MMEA3_UE_ERR_STATUS_HI__RESERVED_FIELD_MASK 0xE0000000L |
16482 | //MMEA3_DSM_CNTL |
16483 | #define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
16484 | #define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
16485 | #define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
16486 | #define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
16487 | #define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
16488 | #define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
16489 | #define MMEA3_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
16490 | #define MMEA3_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
16491 | #define MMEA3_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc |
16492 | #define MMEA3_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
16493 | #define MMEA3_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf |
16494 | #define MMEA3_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
16495 | #define MMEA3_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 |
16496 | #define MMEA3_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
16497 | #define MMEA3_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 |
16498 | #define MMEA3_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 |
16499 | #define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
16500 | #define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
16501 | #define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
16502 | #define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
16503 | #define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
16504 | #define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
16505 | #define MMEA3_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
16506 | #define MMEA3_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
16507 | #define MMEA3_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
16508 | #define MMEA3_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
16509 | #define MMEA3_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L |
16510 | #define MMEA3_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
16511 | #define MMEA3_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
16512 | #define MMEA3_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
16513 | #define MMEA3_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L |
16514 | #define MMEA3_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L |
16515 | //MMEA3_DSM_CNTLA |
16516 | #define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
16517 | #define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
16518 | #define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
16519 | #define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
16520 | #define MMEA3_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
16521 | #define MMEA3_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
16522 | #define MMEA3_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
16523 | #define MMEA3_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
16524 | #define MMEA3_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc |
16525 | #define MMEA3_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
16526 | #define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf |
16527 | #define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
16528 | #define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 |
16529 | #define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
16530 | #define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
16531 | #define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
16532 | #define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
16533 | #define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
16534 | #define MMEA3_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
16535 | #define MMEA3_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
16536 | #define MMEA3_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
16537 | #define MMEA3_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
16538 | #define MMEA3_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
16539 | #define MMEA3_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
16540 | #define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L |
16541 | #define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
16542 | #define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
16543 | #define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
16544 | //MMEA3_DSM_CNTLB |
16545 | #define MMEA3_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
16546 | #define MMEA3_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
16547 | #define MMEA3_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
16548 | #define MMEA3_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
16549 | #define MMEA3_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
16550 | #define MMEA3_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
16551 | #define MMEA3_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
16552 | #define MMEA3_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
16553 | #define MMEA3_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
16554 | #define MMEA3_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
16555 | #define MMEA3_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
16556 | #define MMEA3_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
16557 | #define MMEA3_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
16558 | #define MMEA3_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
16559 | #define MMEA3_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
16560 | #define MMEA3_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
16561 | //MMEA3_DSM_CNTL2 |
16562 | #define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
16563 | #define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
16564 | #define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
16565 | #define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
16566 | #define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
16567 | #define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
16568 | #define MMEA3_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
16569 | #define MMEA3_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb |
16570 | #define MMEA3_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
16571 | #define MMEA3_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe |
16572 | #define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf |
16573 | #define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 |
16574 | #define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 |
16575 | #define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 |
16576 | #define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 |
16577 | #define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 |
16578 | #define MMEA3_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a |
16579 | #define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
16580 | #define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
16581 | #define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
16582 | #define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
16583 | #define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
16584 | #define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
16585 | #define MMEA3_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
16586 | #define MMEA3_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
16587 | #define MMEA3_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
16588 | #define MMEA3_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
16589 | #define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L |
16590 | #define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L |
16591 | #define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
16592 | #define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L |
16593 | #define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L |
16594 | #define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L |
16595 | #define MMEA3_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L |
16596 | //MMEA3_DSM_CNTL2A |
16597 | #define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
16598 | #define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
16599 | #define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
16600 | #define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
16601 | #define MMEA3_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
16602 | #define MMEA3_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
16603 | #define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
16604 | #define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb |
16605 | #define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
16606 | #define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe |
16607 | #define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf |
16608 | #define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 |
16609 | #define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 |
16610 | #define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 |
16611 | #define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
16612 | #define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
16613 | #define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
16614 | #define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
16615 | #define MMEA3_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
16616 | #define MMEA3_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
16617 | #define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
16618 | #define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
16619 | #define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
16620 | #define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
16621 | #define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L |
16622 | #define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L |
16623 | #define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
16624 | #define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L |
16625 | //MMEA3_DSM_CNTL2B |
16626 | #define MMEA3_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
16627 | #define MMEA3_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
16628 | #define MMEA3_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
16629 | #define MMEA3_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
16630 | #define MMEA3_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
16631 | #define MMEA3_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
16632 | #define MMEA3_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
16633 | #define MMEA3_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY__SHIFT 0xb |
16634 | #define MMEA3_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
16635 | #define MMEA3_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
16636 | #define MMEA3_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
16637 | #define MMEA3_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
16638 | #define MMEA3_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
16639 | #define MMEA3_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
16640 | #define MMEA3_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
16641 | #define MMEA3_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
16642 | //MMEA3_CGTT_CLK_CTRL |
16643 | #define MMEA3_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
16644 | #define MMEA3_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
16645 | #define MMEA3_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc |
16646 | #define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 |
16647 | #define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 |
16648 | #define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 |
16649 | #define MMEA3_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 |
16650 | #define MMEA3_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b |
16651 | #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c |
16652 | #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d |
16653 | #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e |
16654 | #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f |
16655 | #define MMEA3_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
16656 | #define MMEA3_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
16657 | #define MMEA3_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L |
16658 | #define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L |
16659 | #define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L |
16660 | #define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L |
16661 | #define MMEA3_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L |
16662 | #define MMEA3_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L |
16663 | #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L |
16664 | #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L |
16665 | #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L |
16666 | #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L |
16667 | //MMEA3_EDC_MODE |
16668 | #define MMEA3_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 |
16669 | #define MMEA3_EDC_MODE__GATE_FUE__SHIFT 0x11 |
16670 | #define MMEA3_EDC_MODE__DED_MODE__SHIFT 0x14 |
16671 | #define MMEA3_EDC_MODE__PROP_FED__SHIFT 0x1d |
16672 | #define MMEA3_EDC_MODE__BYPASS__SHIFT 0x1f |
16673 | #define MMEA3_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L |
16674 | #define MMEA3_EDC_MODE__GATE_FUE_MASK 0x00020000L |
16675 | #define MMEA3_EDC_MODE__DED_MODE_MASK 0x00300000L |
16676 | #define MMEA3_EDC_MODE__PROP_FED_MASK 0x20000000L |
16677 | #define MMEA3_EDC_MODE__BYPASS_MASK 0x80000000L |
16678 | //MMEA3_ERR_STATUS |
16679 | #define MMEA3_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 |
16680 | #define MMEA3_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 |
16681 | #define MMEA3_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 |
16682 | #define MMEA3_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa |
16683 | #define MMEA3_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb |
16684 | #define MMEA3_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc |
16685 | #define MMEA3_ERR_STATUS__FUE_FLAG__SHIFT 0xd |
16686 | #define MMEA3_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe |
16687 | #define MMEA3_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf |
16688 | #define MMEA3_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 |
16689 | #define MMEA3_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 |
16690 | #define MMEA3_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 |
16691 | #define MMEA3_ERR_STATUS__FUE_FLAG_CLIENT__SHIFT 0x13 |
16692 | #define MMEA3_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL |
16693 | #define MMEA3_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L |
16694 | #define MMEA3_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L |
16695 | #define MMEA3_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L |
16696 | #define MMEA3_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L |
16697 | #define MMEA3_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L |
16698 | #define MMEA3_ERR_STATUS__FUE_FLAG_MASK 0x00002000L |
16699 | #define MMEA3_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L |
16700 | #define MMEA3_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L |
16701 | #define MMEA3_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L |
16702 | #define MMEA3_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L |
16703 | #define MMEA3_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L |
16704 | #define MMEA3_ERR_STATUS__FUE_FLAG_CLIENT_MASK 0x00080000L |
16705 | //MMEA3_MISC2 |
16706 | #define MMEA3_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 |
16707 | #define MMEA3_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 |
16708 | #define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 |
16709 | #define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 |
16710 | #define MMEA3_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc |
16711 | #define MMEA3_MISC2__RRET_SWAP_MODE__SHIFT 0xd |
16712 | #define MMEA3_MISC2__BLOCK_REQUESTS__SHIFT 0xe |
16713 | #define MMEA3_MISC2__REQUESTS_BLOCKED__SHIFT 0xf |
16714 | #define MMEA3_MISC2__DRAM_RD_THROTTLE__SHIFT 0x10 |
16715 | #define MMEA3_MISC2__DRAM_WR_THROTTLE__SHIFT 0x11 |
16716 | #define MMEA3_MISC2__GMI_RD_THROTTLE__SHIFT 0x12 |
16717 | #define MMEA3_MISC2__GMI_WR_THROTTLE__SHIFT 0x13 |
16718 | #define MMEA3_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L |
16719 | #define MMEA3_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L |
16720 | #define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL |
16721 | #define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L |
16722 | #define MMEA3_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L |
16723 | #define MMEA3_MISC2__RRET_SWAP_MODE_MASK 0x00002000L |
16724 | #define MMEA3_MISC2__BLOCK_REQUESTS_MASK 0x00004000L |
16725 | #define MMEA3_MISC2__REQUESTS_BLOCKED_MASK 0x00008000L |
16726 | #define MMEA3_MISC2__DRAM_RD_THROTTLE_MASK 0x00010000L |
16727 | #define MMEA3_MISC2__DRAM_WR_THROTTLE_MASK 0x00020000L |
16728 | #define MMEA3_MISC2__GMI_RD_THROTTLE_MASK 0x00040000L |
16729 | #define MMEA3_MISC2__GMI_WR_THROTTLE_MASK 0x00080000L |
16730 | //MMEA3_CE_ERR_STATUS_LO |
16731 | #define MMEA3_CE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT 0x0 |
16732 | #define MMEA3_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 |
16733 | #define MMEA3_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 |
16734 | #define MMEA3_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 |
16735 | #define MMEA3_CE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK 0x00000001L |
16736 | #define MMEA3_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L |
16737 | #define MMEA3_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL |
16738 | #define MMEA3_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L |
16739 | //MMEA3_MISC_AON |
16740 | #define MMEA3_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 |
16741 | #define MMEA3_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 |
16742 | #define MMEA3_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L |
16743 | #define MMEA3_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L |
16744 | //MMEA3_CE_ERR_STATUS_HI |
16745 | #define MMEA3_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 |
16746 | #define MMEA3_CE_ERR_STATUS_HI__RESERVED_FIELD0__SHIFT 0x1 |
16747 | #define MMEA3_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 |
16748 | #define MMEA3_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 |
16749 | #define MMEA3_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 |
16750 | #define MMEA3_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a |
16751 | #define MMEA3_CE_ERR_STATUS_HI__RESERVED_FIELD1__SHIFT 0x1b |
16752 | #define MMEA3_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L |
16753 | #define MMEA3_CE_ERR_STATUS_HI__RESERVED_FIELD0_MASK 0x00000002L |
16754 | #define MMEA3_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L |
16755 | #define MMEA3_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L |
16756 | #define MMEA3_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L |
16757 | #define MMEA3_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L |
16758 | #define MMEA3_CE_ERR_STATUS_HI__RESERVED_FIELD1_MASK 0xF8000000L |
16759 | |
16760 | // addressBlock: aid_mmhub_ea_mmeadec4 |
16761 | //MMEA4_DRAM_RD_CLI2GRP_MAP0 |
16762 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
16763 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
16764 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
16765 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
16766 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
16767 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
16768 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
16769 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
16770 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
16771 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
16772 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
16773 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
16774 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
16775 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
16776 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
16777 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
16778 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
16779 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
16780 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
16781 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
16782 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
16783 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
16784 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
16785 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
16786 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
16787 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
16788 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
16789 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
16790 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
16791 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
16792 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
16793 | #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
16794 | //MMEA4_DRAM_RD_CLI2GRP_MAP1 |
16795 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
16796 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
16797 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
16798 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
16799 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
16800 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
16801 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
16802 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
16803 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
16804 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
16805 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
16806 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
16807 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
16808 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
16809 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
16810 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
16811 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
16812 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
16813 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
16814 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
16815 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
16816 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
16817 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
16818 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
16819 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
16820 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
16821 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
16822 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
16823 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
16824 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
16825 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
16826 | #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
16827 | //MMEA4_DRAM_WR_CLI2GRP_MAP0 |
16828 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
16829 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
16830 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
16831 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
16832 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
16833 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
16834 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
16835 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
16836 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
16837 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
16838 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
16839 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
16840 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
16841 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
16842 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
16843 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
16844 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
16845 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
16846 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
16847 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
16848 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
16849 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
16850 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
16851 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
16852 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
16853 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
16854 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
16855 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
16856 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
16857 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
16858 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
16859 | #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
16860 | //MMEA4_DRAM_WR_CLI2GRP_MAP1 |
16861 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
16862 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
16863 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
16864 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
16865 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
16866 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
16867 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
16868 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
16869 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
16870 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
16871 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
16872 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
16873 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
16874 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
16875 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
16876 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
16877 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
16878 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
16879 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
16880 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
16881 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
16882 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
16883 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
16884 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
16885 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
16886 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
16887 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
16888 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
16889 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
16890 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
16891 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
16892 | #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
16893 | //MMEA4_DRAM_RD_GRP2VC_MAP |
16894 | #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
16895 | #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
16896 | #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
16897 | #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
16898 | #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
16899 | #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
16900 | #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
16901 | #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
16902 | //MMEA4_DRAM_WR_GRP2VC_MAP |
16903 | #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
16904 | #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
16905 | #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
16906 | #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
16907 | #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
16908 | #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
16909 | #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
16910 | #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
16911 | //MMEA4_DRAM_RD_LAZY |
16912 | #define MMEA4_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 |
16913 | #define MMEA4_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 |
16914 | #define MMEA4_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 |
16915 | #define MMEA4_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 |
16916 | #define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
16917 | #define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
16918 | #define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
16919 | #define MMEA4_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L |
16920 | #define MMEA4_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L |
16921 | #define MMEA4_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
16922 | #define MMEA4_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
16923 | #define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
16924 | #define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
16925 | #define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
16926 | //MMEA4_DRAM_WR_LAZY |
16927 | #define MMEA4_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 |
16928 | #define MMEA4_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 |
16929 | #define MMEA4_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 |
16930 | #define MMEA4_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 |
16931 | #define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
16932 | #define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
16933 | #define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
16934 | #define MMEA4_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L |
16935 | #define MMEA4_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L |
16936 | #define MMEA4_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
16937 | #define MMEA4_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
16938 | #define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
16939 | #define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
16940 | #define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
16941 | //MMEA4_DRAM_RD_CAM_CNTL |
16942 | #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
16943 | #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
16944 | #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
16945 | #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
16946 | #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
16947 | #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
16948 | #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
16949 | #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
16950 | #define MMEA4_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
16951 | #define MMEA4_DRAM_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d |
16952 | #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
16953 | #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
16954 | #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
16955 | #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
16956 | #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
16957 | #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
16958 | #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
16959 | #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
16960 | #define MMEA4_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
16961 | #define MMEA4_DRAM_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L |
16962 | //MMEA4_DRAM_WR_CAM_CNTL |
16963 | #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
16964 | #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
16965 | #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
16966 | #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
16967 | #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
16968 | #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
16969 | #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
16970 | #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
16971 | #define MMEA4_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
16972 | #define MMEA4_DRAM_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d |
16973 | #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
16974 | #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
16975 | #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
16976 | #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
16977 | #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
16978 | #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
16979 | #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
16980 | #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
16981 | #define MMEA4_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
16982 | #define MMEA4_DRAM_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L |
16983 | //MMEA4_DRAM_PAGE_BURST |
16984 | #define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 |
16985 | #define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 |
16986 | #define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 |
16987 | #define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 |
16988 | #define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
16989 | #define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
16990 | #define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
16991 | #define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
16992 | //MMEA4_DRAM_RD_PRI_AGE |
16993 | #define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
16994 | #define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
16995 | #define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
16996 | #define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
16997 | #define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
16998 | #define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
16999 | #define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
17000 | #define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
17001 | #define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
17002 | #define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
17003 | #define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
17004 | #define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
17005 | #define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
17006 | #define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
17007 | #define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
17008 | #define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
17009 | //MMEA4_DRAM_WR_PRI_AGE |
17010 | #define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
17011 | #define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
17012 | #define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
17013 | #define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
17014 | #define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
17015 | #define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
17016 | #define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
17017 | #define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
17018 | #define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
17019 | #define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
17020 | #define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
17021 | #define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
17022 | #define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
17023 | #define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
17024 | #define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
17025 | #define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
17026 | //MMEA4_DRAM_RD_PRI_QUEUING |
17027 | #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
17028 | #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
17029 | #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
17030 | #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
17031 | #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
17032 | #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
17033 | #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
17034 | #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
17035 | //MMEA4_DRAM_WR_PRI_QUEUING |
17036 | #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
17037 | #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
17038 | #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
17039 | #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
17040 | #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
17041 | #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
17042 | #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
17043 | #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
17044 | //MMEA4_DRAM_RD_PRI_FIXED |
17045 | #define MMEA4_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
17046 | #define MMEA4_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
17047 | #define MMEA4_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
17048 | #define MMEA4_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
17049 | #define MMEA4_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
17050 | #define MMEA4_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
17051 | #define MMEA4_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
17052 | #define MMEA4_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
17053 | //MMEA4_DRAM_WR_PRI_FIXED |
17054 | #define MMEA4_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
17055 | #define MMEA4_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
17056 | #define MMEA4_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
17057 | #define MMEA4_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
17058 | #define MMEA4_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
17059 | #define MMEA4_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
17060 | #define MMEA4_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
17061 | #define MMEA4_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
17062 | //MMEA4_DRAM_RD_PRI_URGENCY |
17063 | #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
17064 | #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
17065 | #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
17066 | #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
17067 | #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
17068 | #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
17069 | #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
17070 | #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
17071 | #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
17072 | #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
17073 | #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
17074 | #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
17075 | #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
17076 | #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
17077 | #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
17078 | #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
17079 | //MMEA4_DRAM_WR_PRI_URGENCY |
17080 | #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
17081 | #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
17082 | #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
17083 | #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
17084 | #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
17085 | #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
17086 | #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
17087 | #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
17088 | #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
17089 | #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
17090 | #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
17091 | #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
17092 | #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
17093 | #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
17094 | #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
17095 | #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
17096 | //MMEA4_DRAM_RD_PRI_QUANT_PRI1 |
17097 | #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
17098 | #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
17099 | #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
17100 | #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
17101 | #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
17102 | #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
17103 | #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
17104 | #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
17105 | //MMEA4_DRAM_RD_PRI_QUANT_PRI2 |
17106 | #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
17107 | #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
17108 | #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
17109 | #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
17110 | #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
17111 | #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
17112 | #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
17113 | #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
17114 | //MMEA4_DRAM_RD_PRI_QUANT_PRI3 |
17115 | #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
17116 | #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
17117 | #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
17118 | #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
17119 | #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
17120 | #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
17121 | #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
17122 | #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
17123 | //MMEA4_DRAM_WR_PRI_QUANT_PRI1 |
17124 | #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
17125 | #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
17126 | #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
17127 | #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
17128 | #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
17129 | #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
17130 | #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
17131 | #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
17132 | //MMEA4_DRAM_WR_PRI_QUANT_PRI2 |
17133 | #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
17134 | #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
17135 | #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
17136 | #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
17137 | #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
17138 | #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
17139 | #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
17140 | #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
17141 | //MMEA4_DRAM_WR_PRI_QUANT_PRI3 |
17142 | #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
17143 | #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
17144 | #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
17145 | #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
17146 | #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
17147 | #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
17148 | #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
17149 | #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
17150 | //MMEA4_GMI_RD_CLI2GRP_MAP0 |
17151 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
17152 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
17153 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
17154 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
17155 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
17156 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
17157 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
17158 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
17159 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
17160 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
17161 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
17162 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
17163 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
17164 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
17165 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
17166 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
17167 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
17168 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
17169 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
17170 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
17171 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
17172 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
17173 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
17174 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
17175 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
17176 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
17177 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
17178 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
17179 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
17180 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
17181 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
17182 | #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
17183 | //MMEA4_GMI_RD_CLI2GRP_MAP1 |
17184 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
17185 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
17186 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
17187 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
17188 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
17189 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
17190 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
17191 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
17192 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
17193 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
17194 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
17195 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
17196 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
17197 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
17198 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
17199 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
17200 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
17201 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
17202 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
17203 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
17204 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
17205 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
17206 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
17207 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
17208 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
17209 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
17210 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
17211 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
17212 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
17213 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
17214 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
17215 | #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
17216 | //MMEA4_GMI_WR_CLI2GRP_MAP0 |
17217 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
17218 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
17219 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
17220 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
17221 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
17222 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
17223 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
17224 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
17225 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
17226 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
17227 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
17228 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
17229 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
17230 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
17231 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
17232 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
17233 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
17234 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
17235 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
17236 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
17237 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
17238 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
17239 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
17240 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
17241 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
17242 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
17243 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
17244 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
17245 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
17246 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
17247 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
17248 | #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
17249 | //MMEA4_GMI_WR_CLI2GRP_MAP1 |
17250 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
17251 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
17252 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
17253 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
17254 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
17255 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
17256 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
17257 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
17258 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
17259 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
17260 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
17261 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
17262 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
17263 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
17264 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
17265 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
17266 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
17267 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
17268 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
17269 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
17270 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
17271 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
17272 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
17273 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
17274 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
17275 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
17276 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
17277 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
17278 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
17279 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
17280 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
17281 | #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
17282 | //MMEA4_GMI_RD_GRP2VC_MAP |
17283 | #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
17284 | #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
17285 | #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
17286 | #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
17287 | #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
17288 | #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
17289 | #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
17290 | #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
17291 | //MMEA4_GMI_WR_GRP2VC_MAP |
17292 | #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
17293 | #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
17294 | #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
17295 | #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
17296 | #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
17297 | #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
17298 | #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
17299 | #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
17300 | //MMEA4_GMI_RD_LAZY |
17301 | #define MMEA4_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 |
17302 | #define MMEA4_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 |
17303 | #define MMEA4_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 |
17304 | #define MMEA4_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 |
17305 | #define MMEA4_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
17306 | #define MMEA4_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
17307 | #define MMEA4_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
17308 | #define MMEA4_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L |
17309 | #define MMEA4_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L |
17310 | #define MMEA4_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
17311 | #define MMEA4_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
17312 | #define MMEA4_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
17313 | #define MMEA4_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
17314 | #define MMEA4_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
17315 | //MMEA4_GMI_WR_LAZY |
17316 | #define MMEA4_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 |
17317 | #define MMEA4_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 |
17318 | #define MMEA4_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 |
17319 | #define MMEA4_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 |
17320 | #define MMEA4_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
17321 | #define MMEA4_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
17322 | #define MMEA4_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
17323 | #define MMEA4_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L |
17324 | #define MMEA4_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L |
17325 | #define MMEA4_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
17326 | #define MMEA4_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
17327 | #define MMEA4_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
17328 | #define MMEA4_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
17329 | #define MMEA4_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
17330 | //MMEA4_GMI_RD_CAM_CNTL |
17331 | #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
17332 | #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
17333 | #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
17334 | #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
17335 | #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
17336 | #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
17337 | #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
17338 | #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
17339 | #define MMEA4_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
17340 | #define MMEA4_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d |
17341 | #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
17342 | #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
17343 | #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
17344 | #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
17345 | #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
17346 | #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
17347 | #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
17348 | #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
17349 | #define MMEA4_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
17350 | #define MMEA4_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L |
17351 | //MMEA4_GMI_WR_CAM_CNTL |
17352 | #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
17353 | #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
17354 | #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
17355 | #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
17356 | #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
17357 | #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
17358 | #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
17359 | #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
17360 | #define MMEA4_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
17361 | #define MMEA4_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d |
17362 | #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
17363 | #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
17364 | #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
17365 | #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
17366 | #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
17367 | #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
17368 | #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
17369 | #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
17370 | #define MMEA4_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
17371 | #define MMEA4_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L |
17372 | //MMEA4_GMI_PAGE_BURST |
17373 | #define MMEA4_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 |
17374 | #define MMEA4_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 |
17375 | #define MMEA4_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 |
17376 | #define MMEA4_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 |
17377 | #define MMEA4_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
17378 | #define MMEA4_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
17379 | #define MMEA4_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
17380 | #define MMEA4_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
17381 | //MMEA4_GMI_RD_PRI_AGE |
17382 | #define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
17383 | #define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
17384 | #define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
17385 | #define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
17386 | #define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
17387 | #define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
17388 | #define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
17389 | #define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
17390 | #define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
17391 | #define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
17392 | #define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
17393 | #define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
17394 | #define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
17395 | #define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
17396 | #define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
17397 | #define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
17398 | //MMEA4_GMI_WR_PRI_AGE |
17399 | #define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
17400 | #define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
17401 | #define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
17402 | #define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
17403 | #define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
17404 | #define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
17405 | #define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
17406 | #define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
17407 | #define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
17408 | #define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
17409 | #define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
17410 | #define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
17411 | #define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
17412 | #define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
17413 | #define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
17414 | #define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
17415 | //MMEA4_GMI_RD_PRI_QUEUING |
17416 | #define MMEA4_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
17417 | #define MMEA4_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
17418 | #define MMEA4_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
17419 | #define MMEA4_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
17420 | #define MMEA4_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
17421 | #define MMEA4_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
17422 | #define MMEA4_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
17423 | #define MMEA4_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
17424 | //MMEA4_GMI_WR_PRI_QUEUING |
17425 | #define MMEA4_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
17426 | #define MMEA4_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
17427 | #define MMEA4_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
17428 | #define MMEA4_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
17429 | #define MMEA4_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
17430 | #define MMEA4_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
17431 | #define MMEA4_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
17432 | #define MMEA4_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
17433 | //MMEA4_GMI_RD_PRI_FIXED |
17434 | #define MMEA4_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
17435 | #define MMEA4_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
17436 | #define MMEA4_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
17437 | #define MMEA4_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
17438 | #define MMEA4_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
17439 | #define MMEA4_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
17440 | #define MMEA4_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
17441 | #define MMEA4_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
17442 | //MMEA4_GMI_WR_PRI_FIXED |
17443 | #define MMEA4_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
17444 | #define MMEA4_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
17445 | #define MMEA4_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
17446 | #define MMEA4_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
17447 | #define MMEA4_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
17448 | #define MMEA4_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
17449 | #define MMEA4_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
17450 | #define MMEA4_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
17451 | //MMEA4_GMI_RD_PRI_URGENCY |
17452 | #define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
17453 | #define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
17454 | #define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
17455 | #define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
17456 | #define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
17457 | #define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
17458 | #define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
17459 | #define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
17460 | #define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
17461 | #define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
17462 | #define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
17463 | #define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
17464 | #define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
17465 | #define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
17466 | #define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
17467 | #define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
17468 | //MMEA4_GMI_WR_PRI_URGENCY |
17469 | #define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
17470 | #define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
17471 | #define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
17472 | #define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
17473 | #define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
17474 | #define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
17475 | #define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
17476 | #define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
17477 | #define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
17478 | #define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
17479 | #define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
17480 | #define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
17481 | #define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
17482 | #define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
17483 | #define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
17484 | #define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
17485 | //MMEA4_GMI_RD_PRI_URGENCY_MASKING |
17486 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
17487 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
17488 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
17489 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
17490 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
17491 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
17492 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
17493 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
17494 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
17495 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
17496 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
17497 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
17498 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
17499 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
17500 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
17501 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
17502 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
17503 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
17504 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
17505 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
17506 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
17507 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
17508 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
17509 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
17510 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
17511 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
17512 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
17513 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
17514 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
17515 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
17516 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
17517 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
17518 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
17519 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
17520 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
17521 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
17522 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
17523 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
17524 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
17525 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
17526 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
17527 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
17528 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
17529 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
17530 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
17531 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
17532 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
17533 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
17534 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
17535 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
17536 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
17537 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
17538 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
17539 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
17540 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
17541 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
17542 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
17543 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
17544 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
17545 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
17546 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
17547 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
17548 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
17549 | #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
17550 | //MMEA4_GMI_WR_PRI_URGENCY_MASKING |
17551 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
17552 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
17553 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
17554 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
17555 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
17556 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
17557 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
17558 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
17559 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
17560 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
17561 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
17562 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
17563 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
17564 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
17565 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
17566 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
17567 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
17568 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
17569 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
17570 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
17571 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
17572 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
17573 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
17574 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
17575 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
17576 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
17577 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
17578 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
17579 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
17580 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
17581 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
17582 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
17583 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
17584 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
17585 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
17586 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
17587 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
17588 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
17589 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
17590 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
17591 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
17592 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
17593 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
17594 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
17595 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
17596 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
17597 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
17598 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
17599 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
17600 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
17601 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
17602 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
17603 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
17604 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
17605 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
17606 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
17607 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
17608 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
17609 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
17610 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
17611 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
17612 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
17613 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
17614 | #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
17615 | //MMEA4_GMI_RD_PRI_QUANT_PRI1 |
17616 | #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
17617 | #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
17618 | #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
17619 | #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
17620 | #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
17621 | #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
17622 | #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
17623 | #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
17624 | //MMEA4_GMI_RD_PRI_QUANT_PRI2 |
17625 | #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
17626 | #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
17627 | #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
17628 | #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
17629 | #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
17630 | #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
17631 | #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
17632 | #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
17633 | //MMEA4_GMI_RD_PRI_QUANT_PRI3 |
17634 | #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
17635 | #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
17636 | #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
17637 | #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
17638 | #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
17639 | #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
17640 | #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
17641 | #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
17642 | //MMEA4_GMI_WR_PRI_QUANT_PRI1 |
17643 | #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
17644 | #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
17645 | #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
17646 | #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
17647 | #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
17648 | #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
17649 | #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
17650 | #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
17651 | //MMEA4_GMI_WR_PRI_QUANT_PRI2 |
17652 | #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
17653 | #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
17654 | #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
17655 | #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
17656 | #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
17657 | #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
17658 | #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
17659 | #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
17660 | //MMEA4_GMI_WR_PRI_QUANT_PRI3 |
17661 | #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
17662 | #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
17663 | #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
17664 | #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
17665 | #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
17666 | #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
17667 | #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
17668 | #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
17669 | //MMEA4_IO_RD_CLI2GRP_MAP0 |
17670 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
17671 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
17672 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
17673 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
17674 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
17675 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
17676 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
17677 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
17678 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
17679 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
17680 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
17681 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
17682 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
17683 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
17684 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
17685 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
17686 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
17687 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
17688 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
17689 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
17690 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
17691 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
17692 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
17693 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
17694 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
17695 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
17696 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
17697 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
17698 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
17699 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
17700 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
17701 | #define MMEA4_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
17702 | //MMEA4_IO_RD_CLI2GRP_MAP1 |
17703 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
17704 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
17705 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
17706 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
17707 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
17708 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
17709 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
17710 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
17711 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
17712 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
17713 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
17714 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
17715 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
17716 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
17717 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
17718 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
17719 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
17720 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
17721 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
17722 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
17723 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
17724 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
17725 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
17726 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
17727 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
17728 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
17729 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
17730 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
17731 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
17732 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
17733 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
17734 | #define MMEA4_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
17735 | //MMEA4_IO_WR_CLI2GRP_MAP0 |
17736 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
17737 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
17738 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
17739 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
17740 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
17741 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
17742 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
17743 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
17744 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
17745 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
17746 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
17747 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
17748 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
17749 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
17750 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
17751 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
17752 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
17753 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
17754 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
17755 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
17756 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
17757 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
17758 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
17759 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
17760 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
17761 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
17762 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
17763 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
17764 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
17765 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
17766 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
17767 | #define MMEA4_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
17768 | //MMEA4_IO_WR_CLI2GRP_MAP1 |
17769 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
17770 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
17771 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
17772 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
17773 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
17774 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
17775 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
17776 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
17777 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
17778 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
17779 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
17780 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
17781 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
17782 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
17783 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
17784 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
17785 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
17786 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
17787 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
17788 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
17789 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
17790 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
17791 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
17792 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
17793 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
17794 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
17795 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
17796 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
17797 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
17798 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
17799 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
17800 | #define MMEA4_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
17801 | //MMEA4_IO_RD_COMBINE_FLUSH |
17802 | #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
17803 | #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
17804 | #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
17805 | #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
17806 | #define MMEA4_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 |
17807 | #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
17808 | #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
17809 | #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
17810 | #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
17811 | #define MMEA4_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L |
17812 | //MMEA4_IO_WR_COMBINE_FLUSH |
17813 | #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
17814 | #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
17815 | #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
17816 | #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
17817 | #define MMEA4_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 |
17818 | #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
17819 | #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
17820 | #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
17821 | #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
17822 | #define MMEA4_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L |
17823 | //MMEA4_IO_GROUP_BURST |
17824 | #define MMEA4_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 |
17825 | #define MMEA4_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 |
17826 | #define MMEA4_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 |
17827 | #define MMEA4_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 |
17828 | #define MMEA4_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
17829 | #define MMEA4_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
17830 | #define MMEA4_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
17831 | #define MMEA4_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
17832 | //MMEA4_IO_RD_PRI_AGE |
17833 | #define MMEA4_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
17834 | #define MMEA4_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
17835 | #define MMEA4_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
17836 | #define MMEA4_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
17837 | #define MMEA4_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
17838 | #define MMEA4_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
17839 | #define MMEA4_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
17840 | #define MMEA4_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
17841 | #define MMEA4_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
17842 | #define MMEA4_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
17843 | #define MMEA4_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
17844 | #define MMEA4_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
17845 | #define MMEA4_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
17846 | #define MMEA4_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
17847 | #define MMEA4_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
17848 | #define MMEA4_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
17849 | //MMEA4_IO_WR_PRI_AGE |
17850 | #define MMEA4_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
17851 | #define MMEA4_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
17852 | #define MMEA4_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
17853 | #define MMEA4_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
17854 | #define MMEA4_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
17855 | #define MMEA4_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
17856 | #define MMEA4_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
17857 | #define MMEA4_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
17858 | #define MMEA4_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
17859 | #define MMEA4_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
17860 | #define MMEA4_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
17861 | #define MMEA4_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
17862 | #define MMEA4_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
17863 | #define MMEA4_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
17864 | #define MMEA4_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
17865 | #define MMEA4_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
17866 | //MMEA4_IO_RD_PRI_QUEUING |
17867 | #define MMEA4_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
17868 | #define MMEA4_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
17869 | #define MMEA4_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
17870 | #define MMEA4_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
17871 | #define MMEA4_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
17872 | #define MMEA4_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
17873 | #define MMEA4_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
17874 | #define MMEA4_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
17875 | //MMEA4_IO_WR_PRI_QUEUING |
17876 | #define MMEA4_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
17877 | #define MMEA4_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
17878 | #define MMEA4_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
17879 | #define MMEA4_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
17880 | #define MMEA4_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
17881 | #define MMEA4_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
17882 | #define MMEA4_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
17883 | #define MMEA4_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
17884 | //MMEA4_IO_RD_PRI_FIXED |
17885 | #define MMEA4_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
17886 | #define MMEA4_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
17887 | #define MMEA4_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
17888 | #define MMEA4_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
17889 | #define MMEA4_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
17890 | #define MMEA4_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
17891 | #define MMEA4_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
17892 | #define MMEA4_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
17893 | //MMEA4_IO_WR_PRI_FIXED |
17894 | #define MMEA4_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
17895 | #define MMEA4_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
17896 | #define MMEA4_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
17897 | #define MMEA4_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
17898 | #define MMEA4_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
17899 | #define MMEA4_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
17900 | #define MMEA4_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
17901 | #define MMEA4_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
17902 | //MMEA4_IO_RD_PRI_URGENCY |
17903 | #define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
17904 | #define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
17905 | #define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
17906 | #define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
17907 | #define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
17908 | #define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
17909 | #define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
17910 | #define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
17911 | #define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
17912 | #define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
17913 | #define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
17914 | #define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
17915 | #define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
17916 | #define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
17917 | #define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
17918 | #define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
17919 | //MMEA4_IO_WR_PRI_URGENCY |
17920 | #define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
17921 | #define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
17922 | #define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
17923 | #define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
17924 | #define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
17925 | #define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
17926 | #define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
17927 | #define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
17928 | #define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
17929 | #define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
17930 | #define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
17931 | #define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
17932 | #define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
17933 | #define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
17934 | #define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
17935 | #define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
17936 | //MMEA4_IO_RD_PRI_URGENCY_MASKING |
17937 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
17938 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
17939 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
17940 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
17941 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
17942 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
17943 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
17944 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
17945 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
17946 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
17947 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
17948 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
17949 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
17950 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
17951 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
17952 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
17953 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
17954 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
17955 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
17956 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
17957 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
17958 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
17959 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
17960 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
17961 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
17962 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
17963 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
17964 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
17965 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
17966 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
17967 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
17968 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
17969 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
17970 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
17971 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
17972 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
17973 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
17974 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
17975 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
17976 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
17977 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
17978 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
17979 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
17980 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
17981 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
17982 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
17983 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
17984 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
17985 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
17986 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
17987 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
17988 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
17989 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
17990 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
17991 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
17992 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
17993 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
17994 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
17995 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
17996 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
17997 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
17998 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
17999 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
18000 | #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
18001 | //MMEA4_IO_WR_PRI_URGENCY_MASKING |
18002 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
18003 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
18004 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
18005 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
18006 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
18007 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
18008 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
18009 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
18010 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
18011 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
18012 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
18013 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
18014 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
18015 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
18016 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
18017 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
18018 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
18019 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
18020 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
18021 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
18022 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
18023 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
18024 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
18025 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
18026 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
18027 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
18028 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
18029 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
18030 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
18031 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
18032 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
18033 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
18034 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
18035 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
18036 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
18037 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
18038 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
18039 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
18040 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
18041 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
18042 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
18043 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
18044 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
18045 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
18046 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
18047 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
18048 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
18049 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
18050 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
18051 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
18052 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
18053 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
18054 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
18055 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
18056 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
18057 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
18058 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
18059 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
18060 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
18061 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
18062 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
18063 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
18064 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
18065 | #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
18066 | //MMEA4_IO_RD_PRI_QUANT_PRI1 |
18067 | #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
18068 | #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
18069 | #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
18070 | #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
18071 | #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
18072 | #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
18073 | #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
18074 | #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
18075 | //MMEA4_IO_RD_PRI_QUANT_PRI2 |
18076 | #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
18077 | #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
18078 | #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
18079 | #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
18080 | #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
18081 | #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
18082 | #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
18083 | #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
18084 | //MMEA4_IO_RD_PRI_QUANT_PRI3 |
18085 | #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
18086 | #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
18087 | #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
18088 | #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
18089 | #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
18090 | #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
18091 | #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
18092 | #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
18093 | //MMEA4_IO_WR_PRI_QUANT_PRI1 |
18094 | #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
18095 | #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
18096 | #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
18097 | #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
18098 | #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
18099 | #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
18100 | #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
18101 | #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
18102 | //MMEA4_IO_WR_PRI_QUANT_PRI2 |
18103 | #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
18104 | #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
18105 | #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
18106 | #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
18107 | #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
18108 | #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
18109 | #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
18110 | #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
18111 | //MMEA4_IO_WR_PRI_QUANT_PRI3 |
18112 | #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
18113 | #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
18114 | #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
18115 | #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
18116 | #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
18117 | #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
18118 | #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
18119 | #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
18120 | //MMEA4_SDP_ARB_DRAM |
18121 | #define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 |
18122 | #define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 |
18123 | #define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 |
18124 | #define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 |
18125 | #define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 |
18126 | #define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 |
18127 | #define MMEA4_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 |
18128 | #define MMEA4_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 |
18129 | #define MMEA4_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING__SHIFT 0x16 |
18130 | #define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL |
18131 | #define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L |
18132 | #define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L |
18133 | #define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L |
18134 | #define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L |
18135 | #define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L |
18136 | #define MMEA4_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L |
18137 | #define MMEA4_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L |
18138 | #define MMEA4_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING_MASK 0x00400000L |
18139 | //MMEA4_SDP_ARB_GMI |
18140 | #define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 |
18141 | #define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 |
18142 | #define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 |
18143 | #define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 |
18144 | #define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 |
18145 | #define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 |
18146 | #define MMEA4_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 |
18147 | #define MMEA4_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 |
18148 | #define MMEA4_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 |
18149 | #define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL |
18150 | #define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L |
18151 | #define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L |
18152 | #define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L |
18153 | #define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L |
18154 | #define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L |
18155 | #define MMEA4_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L |
18156 | #define MMEA4_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L |
18157 | #define MMEA4_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L |
18158 | //MMEA4_SDP_ARB_FINAL |
18159 | #define MMEA4_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 |
18160 | #define MMEA4_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 |
18161 | #define MMEA4_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa |
18162 | #define MMEA4_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf |
18163 | #define MMEA4_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 |
18164 | #define MMEA4_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 |
18165 | #define MMEA4_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 |
18166 | #define MMEA4_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 |
18167 | #define MMEA4_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 |
18168 | #define MMEA4_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 |
18169 | #define MMEA4_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 |
18170 | #define MMEA4_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 |
18171 | #define MMEA4_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 |
18172 | #define MMEA4_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a |
18173 | #define MMEA4_SDP_ARB_FINAL__DRAM_BURST_STRETCH__SHIFT 0x1b |
18174 | #define MMEA4_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1c |
18175 | #define MMEA4_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL |
18176 | #define MMEA4_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L |
18177 | #define MMEA4_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L |
18178 | #define MMEA4_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L |
18179 | #define MMEA4_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L |
18180 | #define MMEA4_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L |
18181 | #define MMEA4_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L |
18182 | #define MMEA4_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L |
18183 | #define MMEA4_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L |
18184 | #define MMEA4_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L |
18185 | #define MMEA4_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L |
18186 | #define MMEA4_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L |
18187 | #define MMEA4_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L |
18188 | #define MMEA4_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L |
18189 | #define MMEA4_SDP_ARB_FINAL__DRAM_BURST_STRETCH_MASK 0x08000000L |
18190 | #define MMEA4_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x10000000L |
18191 | //MMEA4_SDP_DRAM_PRIORITY |
18192 | #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 |
18193 | #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 |
18194 | #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 |
18195 | #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc |
18196 | #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 |
18197 | #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 |
18198 | #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 |
18199 | #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c |
18200 | #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL |
18201 | #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L |
18202 | #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L |
18203 | #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L |
18204 | #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L |
18205 | #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L |
18206 | #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L |
18207 | #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L |
18208 | //MMEA4_SDP_GMI_PRIORITY |
18209 | #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 |
18210 | #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 |
18211 | #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 |
18212 | #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc |
18213 | #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 |
18214 | #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 |
18215 | #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 |
18216 | #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c |
18217 | #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL |
18218 | #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L |
18219 | #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L |
18220 | #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L |
18221 | #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L |
18222 | #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L |
18223 | #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L |
18224 | #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L |
18225 | //MMEA4_SDP_IO_PRIORITY |
18226 | #define MMEA4_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 |
18227 | #define MMEA4_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 |
18228 | #define MMEA4_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 |
18229 | #define MMEA4_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc |
18230 | #define MMEA4_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 |
18231 | #define MMEA4_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 |
18232 | #define MMEA4_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 |
18233 | #define MMEA4_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c |
18234 | #define MMEA4_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL |
18235 | #define MMEA4_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L |
18236 | #define MMEA4_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L |
18237 | #define MMEA4_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L |
18238 | #define MMEA4_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L |
18239 | #define MMEA4_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L |
18240 | #define MMEA4_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L |
18241 | #define MMEA4_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L |
18242 | //MMEA4_SDP_CREDITS |
18243 | #define MMEA4_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 |
18244 | #define MMEA4_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 |
18245 | #define MMEA4_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 |
18246 | #define MMEA4_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL |
18247 | #define MMEA4_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L |
18248 | #define MMEA4_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L |
18249 | //MMEA4_SDP_TAG_RESERVE0 |
18250 | #define MMEA4_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 |
18251 | #define MMEA4_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 |
18252 | #define MMEA4_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 |
18253 | #define MMEA4_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 |
18254 | #define MMEA4_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL |
18255 | #define MMEA4_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L |
18256 | #define MMEA4_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L |
18257 | #define MMEA4_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L |
18258 | //MMEA4_SDP_TAG_RESERVE1 |
18259 | #define MMEA4_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 |
18260 | #define MMEA4_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 |
18261 | #define MMEA4_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 |
18262 | #define MMEA4_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 |
18263 | #define MMEA4_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL |
18264 | #define MMEA4_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L |
18265 | #define MMEA4_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L |
18266 | #define MMEA4_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L |
18267 | //MMEA4_SDP_VCC_RESERVE0 |
18268 | #define MMEA4_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 |
18269 | #define MMEA4_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 |
18270 | #define MMEA4_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc |
18271 | #define MMEA4_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 |
18272 | #define MMEA4_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 |
18273 | #define MMEA4_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL |
18274 | #define MMEA4_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L |
18275 | #define MMEA4_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L |
18276 | #define MMEA4_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L |
18277 | #define MMEA4_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L |
18278 | //MMEA4_SDP_VCC_RESERVE1 |
18279 | #define MMEA4_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 |
18280 | #define MMEA4_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 |
18281 | #define MMEA4_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc |
18282 | #define MMEA4_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f |
18283 | #define MMEA4_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL |
18284 | #define MMEA4_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L |
18285 | #define MMEA4_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L |
18286 | #define MMEA4_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L |
18287 | //MMEA4_SDP_VCD_RESERVE0 |
18288 | #define MMEA4_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 |
18289 | #define MMEA4_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 |
18290 | #define MMEA4_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc |
18291 | #define MMEA4_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 |
18292 | #define MMEA4_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 |
18293 | #define MMEA4_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL |
18294 | #define MMEA4_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L |
18295 | #define MMEA4_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L |
18296 | #define MMEA4_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L |
18297 | #define MMEA4_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L |
18298 | //MMEA4_SDP_VCD_RESERVE1 |
18299 | #define MMEA4_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 |
18300 | #define MMEA4_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 |
18301 | #define MMEA4_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc |
18302 | #define MMEA4_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f |
18303 | #define MMEA4_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL |
18304 | #define MMEA4_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L |
18305 | #define MMEA4_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L |
18306 | #define MMEA4_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L |
18307 | //MMEA4_SDP_REQ_CNTL |
18308 | #define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 |
18309 | #define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 |
18310 | #define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 |
18311 | #define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 |
18312 | #define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 |
18313 | #define MMEA4_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 |
18314 | #define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 |
18315 | #define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 |
18316 | #define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa |
18317 | #define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L |
18318 | #define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L |
18319 | #define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L |
18320 | #define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L |
18321 | #define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L |
18322 | #define MMEA4_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L |
18323 | #define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L |
18324 | #define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L |
18325 | #define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L |
18326 | //MMEA4_MISC |
18327 | #define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 |
18328 | #define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 |
18329 | #define MMEA4_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 |
18330 | #define MMEA4_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 |
18331 | #define MMEA4_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 |
18332 | #define MMEA4_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 |
18333 | #define MMEA4_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 |
18334 | #define MMEA4_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 |
18335 | #define MMEA4_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 |
18336 | #define MMEA4_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 |
18337 | #define MMEA4_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa |
18338 | #define MMEA4_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb |
18339 | #define MMEA4_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc |
18340 | #define MMEA4_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd |
18341 | #define MMEA4_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe |
18342 | #define MMEA4_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf |
18343 | #define MMEA4_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 |
18344 | #define MMEA4_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 |
18345 | #define MMEA4_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 |
18346 | #define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a |
18347 | #define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b |
18348 | #define MMEA4_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c |
18349 | #define MMEA4_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d |
18350 | #define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e |
18351 | #define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f |
18352 | #define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L |
18353 | #define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L |
18354 | #define MMEA4_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L |
18355 | #define MMEA4_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L |
18356 | #define MMEA4_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L |
18357 | #define MMEA4_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L |
18358 | #define MMEA4_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L |
18359 | #define MMEA4_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L |
18360 | #define MMEA4_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L |
18361 | #define MMEA4_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L |
18362 | #define MMEA4_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L |
18363 | #define MMEA4_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L |
18364 | #define MMEA4_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L |
18365 | #define MMEA4_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L |
18366 | #define MMEA4_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L |
18367 | #define MMEA4_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L |
18368 | #define MMEA4_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L |
18369 | #define MMEA4_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L |
18370 | #define MMEA4_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L |
18371 | #define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L |
18372 | #define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L |
18373 | #define MMEA4_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L |
18374 | #define MMEA4_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L |
18375 | #define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L |
18376 | #define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L |
18377 | //MMEA4_LATENCY_SAMPLING |
18378 | #define MMEA4_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 |
18379 | #define MMEA4_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 |
18380 | #define MMEA4_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 |
18381 | #define MMEA4_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 |
18382 | #define MMEA4_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 |
18383 | #define MMEA4_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 |
18384 | #define MMEA4_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 |
18385 | #define MMEA4_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 |
18386 | #define MMEA4_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 |
18387 | #define MMEA4_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 |
18388 | #define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa |
18389 | #define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb |
18390 | #define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc |
18391 | #define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd |
18392 | #define MMEA4_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe |
18393 | #define MMEA4_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 |
18394 | #define MMEA4_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L |
18395 | #define MMEA4_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L |
18396 | #define MMEA4_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L |
18397 | #define MMEA4_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L |
18398 | #define MMEA4_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L |
18399 | #define MMEA4_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L |
18400 | #define MMEA4_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L |
18401 | #define MMEA4_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L |
18402 | #define MMEA4_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L |
18403 | #define MMEA4_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L |
18404 | #define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L |
18405 | #define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L |
18406 | #define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L |
18407 | #define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L |
18408 | #define MMEA4_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L |
18409 | #define MMEA4_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L |
18410 | //MMEA4_PERFCOUNTER_LO |
18411 | #define MMEA4_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
18412 | #define MMEA4_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
18413 | //MMEA4_PERFCOUNTER_HI |
18414 | #define MMEA4_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
18415 | #define MMEA4_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
18416 | #define MMEA4_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
18417 | #define MMEA4_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
18418 | //MMEA4_PERFCOUNTER0_CFG |
18419 | #define MMEA4_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
18420 | #define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
18421 | #define MMEA4_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
18422 | #define MMEA4_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
18423 | #define MMEA4_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
18424 | #define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
18425 | #define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
18426 | #define MMEA4_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
18427 | #define MMEA4_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
18428 | #define MMEA4_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
18429 | //MMEA4_PERFCOUNTER1_CFG |
18430 | #define MMEA4_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
18431 | #define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
18432 | #define MMEA4_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
18433 | #define MMEA4_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
18434 | #define MMEA4_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
18435 | #define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
18436 | #define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
18437 | #define MMEA4_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
18438 | #define MMEA4_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
18439 | #define MMEA4_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
18440 | //MMEA4_PERFCOUNTER_RSLT_CNTL |
18441 | #define MMEA4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
18442 | #define MMEA4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
18443 | #define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
18444 | #define MMEA4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
18445 | #define MMEA4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
18446 | #define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
18447 | #define MMEA4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
18448 | #define MMEA4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
18449 | #define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
18450 | #define MMEA4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
18451 | #define MMEA4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
18452 | #define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
18453 | //MMEA4_UE_ERR_STATUS_LO |
18454 | #define MMEA4_UE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT 0x0 |
18455 | #define MMEA4_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 |
18456 | #define MMEA4_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 |
18457 | #define MMEA4_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 |
18458 | #define MMEA4_UE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK 0x00000001L |
18459 | #define MMEA4_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L |
18460 | #define MMEA4_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL |
18461 | #define MMEA4_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L |
18462 | //MMEA4_UE_ERR_STATUS_HI |
18463 | #define MMEA4_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 |
18464 | #define MMEA4_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 |
18465 | #define MMEA4_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 |
18466 | #define MMEA4_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 |
18467 | #define MMEA4_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 |
18468 | #define MMEA4_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a |
18469 | #define MMEA4_UE_ERR_STATUS_HI__RESERVED_FIELD__SHIFT 0x1d |
18470 | #define MMEA4_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L |
18471 | #define MMEA4_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L |
18472 | #define MMEA4_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L |
18473 | #define MMEA4_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L |
18474 | #define MMEA4_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L |
18475 | #define MMEA4_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L |
18476 | #define MMEA4_UE_ERR_STATUS_HI__RESERVED_FIELD_MASK 0xE0000000L |
18477 | //MMEA4_DSM_CNTL |
18478 | #define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
18479 | #define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
18480 | #define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
18481 | #define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
18482 | #define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
18483 | #define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
18484 | #define MMEA4_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
18485 | #define MMEA4_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
18486 | #define MMEA4_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc |
18487 | #define MMEA4_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
18488 | #define MMEA4_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf |
18489 | #define MMEA4_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
18490 | #define MMEA4_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 |
18491 | #define MMEA4_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
18492 | #define MMEA4_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 |
18493 | #define MMEA4_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 |
18494 | #define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
18495 | #define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
18496 | #define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
18497 | #define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
18498 | #define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
18499 | #define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
18500 | #define MMEA4_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
18501 | #define MMEA4_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
18502 | #define MMEA4_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
18503 | #define MMEA4_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
18504 | #define MMEA4_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L |
18505 | #define MMEA4_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
18506 | #define MMEA4_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
18507 | #define MMEA4_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
18508 | #define MMEA4_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L |
18509 | #define MMEA4_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L |
18510 | //MMEA4_DSM_CNTLA |
18511 | #define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
18512 | #define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
18513 | #define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
18514 | #define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
18515 | #define MMEA4_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
18516 | #define MMEA4_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
18517 | #define MMEA4_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
18518 | #define MMEA4_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
18519 | #define MMEA4_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc |
18520 | #define MMEA4_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
18521 | #define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf |
18522 | #define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
18523 | #define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 |
18524 | #define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
18525 | #define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
18526 | #define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
18527 | #define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
18528 | #define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
18529 | #define MMEA4_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
18530 | #define MMEA4_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
18531 | #define MMEA4_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
18532 | #define MMEA4_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
18533 | #define MMEA4_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
18534 | #define MMEA4_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
18535 | #define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L |
18536 | #define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
18537 | #define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
18538 | #define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
18539 | //MMEA4_DSM_CNTLB |
18540 | #define MMEA4_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
18541 | #define MMEA4_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
18542 | #define MMEA4_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
18543 | #define MMEA4_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
18544 | #define MMEA4_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
18545 | #define MMEA4_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
18546 | #define MMEA4_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
18547 | #define MMEA4_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
18548 | #define MMEA4_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
18549 | #define MMEA4_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
18550 | #define MMEA4_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
18551 | #define MMEA4_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
18552 | #define MMEA4_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
18553 | #define MMEA4_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
18554 | #define MMEA4_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
18555 | #define MMEA4_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
18556 | //MMEA4_DSM_CNTL2 |
18557 | #define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
18558 | #define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
18559 | #define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
18560 | #define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
18561 | #define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
18562 | #define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
18563 | #define MMEA4_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
18564 | #define MMEA4_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb |
18565 | #define MMEA4_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
18566 | #define MMEA4_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe |
18567 | #define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf |
18568 | #define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 |
18569 | #define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 |
18570 | #define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 |
18571 | #define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 |
18572 | #define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 |
18573 | #define MMEA4_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a |
18574 | #define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
18575 | #define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
18576 | #define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
18577 | #define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
18578 | #define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
18579 | #define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
18580 | #define MMEA4_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
18581 | #define MMEA4_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
18582 | #define MMEA4_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
18583 | #define MMEA4_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
18584 | #define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L |
18585 | #define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L |
18586 | #define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
18587 | #define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L |
18588 | #define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L |
18589 | #define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L |
18590 | #define MMEA4_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L |
18591 | //MMEA4_DSM_CNTL2A |
18592 | #define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
18593 | #define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
18594 | #define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
18595 | #define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
18596 | #define MMEA4_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
18597 | #define MMEA4_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
18598 | #define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
18599 | #define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb |
18600 | #define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
18601 | #define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe |
18602 | #define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf |
18603 | #define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 |
18604 | #define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 |
18605 | #define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 |
18606 | #define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
18607 | #define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
18608 | #define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
18609 | #define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
18610 | #define MMEA4_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
18611 | #define MMEA4_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
18612 | #define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
18613 | #define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
18614 | #define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
18615 | #define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
18616 | #define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L |
18617 | #define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L |
18618 | #define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
18619 | #define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L |
18620 | //MMEA4_DSM_CNTL2B |
18621 | #define MMEA4_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
18622 | #define MMEA4_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
18623 | #define MMEA4_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
18624 | #define MMEA4_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
18625 | #define MMEA4_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
18626 | #define MMEA4_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
18627 | #define MMEA4_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
18628 | #define MMEA4_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY__SHIFT 0xb |
18629 | #define MMEA4_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
18630 | #define MMEA4_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
18631 | #define MMEA4_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
18632 | #define MMEA4_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
18633 | #define MMEA4_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
18634 | #define MMEA4_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
18635 | #define MMEA4_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
18636 | #define MMEA4_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
18637 | //MMEA4_CGTT_CLK_CTRL |
18638 | #define MMEA4_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
18639 | #define MMEA4_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
18640 | #define MMEA4_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc |
18641 | #define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 |
18642 | #define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 |
18643 | #define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 |
18644 | #define MMEA4_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 |
18645 | #define MMEA4_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b |
18646 | #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c |
18647 | #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d |
18648 | #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e |
18649 | #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f |
18650 | #define MMEA4_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
18651 | #define MMEA4_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
18652 | #define MMEA4_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L |
18653 | #define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L |
18654 | #define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L |
18655 | #define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L |
18656 | #define MMEA4_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L |
18657 | #define MMEA4_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L |
18658 | #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L |
18659 | #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L |
18660 | #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L |
18661 | #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L |
18662 | //MMEA4_EDC_MODE |
18663 | #define MMEA4_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 |
18664 | #define MMEA4_EDC_MODE__GATE_FUE__SHIFT 0x11 |
18665 | #define MMEA4_EDC_MODE__DED_MODE__SHIFT 0x14 |
18666 | #define MMEA4_EDC_MODE__PROP_FED__SHIFT 0x1d |
18667 | #define MMEA4_EDC_MODE__BYPASS__SHIFT 0x1f |
18668 | #define MMEA4_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L |
18669 | #define MMEA4_EDC_MODE__GATE_FUE_MASK 0x00020000L |
18670 | #define MMEA4_EDC_MODE__DED_MODE_MASK 0x00300000L |
18671 | #define MMEA4_EDC_MODE__PROP_FED_MASK 0x20000000L |
18672 | #define MMEA4_EDC_MODE__BYPASS_MASK 0x80000000L |
18673 | //MMEA4_ERR_STATUS |
18674 | #define MMEA4_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 |
18675 | #define MMEA4_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 |
18676 | #define MMEA4_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 |
18677 | #define MMEA4_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa |
18678 | #define MMEA4_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb |
18679 | #define MMEA4_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc |
18680 | #define MMEA4_ERR_STATUS__FUE_FLAG__SHIFT 0xd |
18681 | #define MMEA4_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe |
18682 | #define MMEA4_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf |
18683 | #define MMEA4_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 |
18684 | #define MMEA4_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 |
18685 | #define MMEA4_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 |
18686 | #define MMEA4_ERR_STATUS__FUE_FLAG_CLIENT__SHIFT 0x13 |
18687 | #define MMEA4_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL |
18688 | #define MMEA4_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L |
18689 | #define MMEA4_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L |
18690 | #define MMEA4_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L |
18691 | #define MMEA4_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L |
18692 | #define MMEA4_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L |
18693 | #define MMEA4_ERR_STATUS__FUE_FLAG_MASK 0x00002000L |
18694 | #define MMEA4_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L |
18695 | #define MMEA4_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L |
18696 | #define MMEA4_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L |
18697 | #define MMEA4_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L |
18698 | #define MMEA4_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L |
18699 | #define MMEA4_ERR_STATUS__FUE_FLAG_CLIENT_MASK 0x00080000L |
18700 | //MMEA4_MISC2 |
18701 | #define MMEA4_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 |
18702 | #define MMEA4_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 |
18703 | #define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 |
18704 | #define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 |
18705 | #define MMEA4_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc |
18706 | #define MMEA4_MISC2__RRET_SWAP_MODE__SHIFT 0xd |
18707 | #define MMEA4_MISC2__BLOCK_REQUESTS__SHIFT 0xe |
18708 | #define MMEA4_MISC2__REQUESTS_BLOCKED__SHIFT 0xf |
18709 | #define MMEA4_MISC2__DRAM_RD_THROTTLE__SHIFT 0x10 |
18710 | #define MMEA4_MISC2__DRAM_WR_THROTTLE__SHIFT 0x11 |
18711 | #define MMEA4_MISC2__GMI_RD_THROTTLE__SHIFT 0x12 |
18712 | #define MMEA4_MISC2__GMI_WR_THROTTLE__SHIFT 0x13 |
18713 | #define MMEA4_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L |
18714 | #define MMEA4_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L |
18715 | #define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL |
18716 | #define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L |
18717 | #define MMEA4_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L |
18718 | #define MMEA4_MISC2__RRET_SWAP_MODE_MASK 0x00002000L |
18719 | #define MMEA4_MISC2__BLOCK_REQUESTS_MASK 0x00004000L |
18720 | #define MMEA4_MISC2__REQUESTS_BLOCKED_MASK 0x00008000L |
18721 | #define MMEA4_MISC2__DRAM_RD_THROTTLE_MASK 0x00010000L |
18722 | #define MMEA4_MISC2__DRAM_WR_THROTTLE_MASK 0x00020000L |
18723 | #define MMEA4_MISC2__GMI_RD_THROTTLE_MASK 0x00040000L |
18724 | #define MMEA4_MISC2__GMI_WR_THROTTLE_MASK 0x00080000L |
18725 | //MMEA4_CE_ERR_STATUS_LO |
18726 | #define MMEA4_CE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT 0x0 |
18727 | #define MMEA4_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 |
18728 | #define MMEA4_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 |
18729 | #define MMEA4_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 |
18730 | #define MMEA4_CE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK 0x00000001L |
18731 | #define MMEA4_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L |
18732 | #define MMEA4_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL |
18733 | #define MMEA4_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L |
18734 | //MMEA4_MISC_AON |
18735 | #define MMEA4_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 |
18736 | #define MMEA4_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 |
18737 | #define MMEA4_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L |
18738 | #define MMEA4_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L |
18739 | //MMEA4_CE_ERR_STATUS_HI |
18740 | #define MMEA4_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 |
18741 | #define MMEA4_CE_ERR_STATUS_HI__RESERVED_FIELD0__SHIFT 0x1 |
18742 | #define MMEA4_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 |
18743 | #define MMEA4_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 |
18744 | #define MMEA4_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 |
18745 | #define MMEA4_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a |
18746 | #define MMEA4_CE_ERR_STATUS_HI__RESERVED_FIELD1__SHIFT 0x1b |
18747 | #define MMEA4_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L |
18748 | #define MMEA4_CE_ERR_STATUS_HI__RESERVED_FIELD0_MASK 0x00000002L |
18749 | #define MMEA4_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L |
18750 | #define MMEA4_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L |
18751 | #define MMEA4_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L |
18752 | #define MMEA4_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L |
18753 | #define MMEA4_CE_ERR_STATUS_HI__RESERVED_FIELD1_MASK 0xF8000000L |
18754 | |
18755 | // addressBlock: aid_mmhub_pctldec0 |
18756 | //PCTL0_CTRL |
18757 | #define PCTL0_CTRL__PG_ENABLE__SHIFT 0x0 |
18758 | #define PCTL0_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1 |
18759 | #define PCTL0_CTRL__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x4 |
18760 | #define PCTL0_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0xb |
18761 | #define PCTL0_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x10 |
18762 | #define PCTL0_CTRL__OVR_EA0_SDP_PARTACK__SHIFT 0x11 |
18763 | #define PCTL0_CTRL__OVR_EA1_SDP_PARTACK__SHIFT 0x12 |
18764 | #define PCTL0_CTRL__OVR_EA2_SDP_PARTACK__SHIFT 0x13 |
18765 | #define PCTL0_CTRL__OVR_EA3_SDP_PARTACK__SHIFT 0x14 |
18766 | #define PCTL0_CTRL__OVR_EA4_SDP_PARTACK__SHIFT 0x15 |
18767 | #define PCTL0_CTRL__OVR_EA5_SDP_PARTACK__SHIFT 0x16 |
18768 | #define PCTL0_CTRL__OVR_EA0_SDP_FULLACK__SHIFT 0x17 |
18769 | #define PCTL0_CTRL__OVR_EA1_SDP_FULLACK__SHIFT 0x18 |
18770 | #define PCTL0_CTRL__OVR_EA2_SDP_FULLACK__SHIFT 0x19 |
18771 | #define PCTL0_CTRL__OVR_EA3_SDP_FULLACK__SHIFT 0x1a |
18772 | #define PCTL0_CTRL__OVR_EA4_SDP_FULLACK__SHIFT 0x1b |
18773 | #define PCTL0_CTRL__OVR_EA5_SDP_FULLACK__SHIFT 0x1c |
18774 | #define PCTL0_CTRL__RSMU_RDTIMER_ENABLE__SHIFT 0x1d |
18775 | #define PCTL0_CTRL__RSMU_RDTIMER_THRESHOLD__SHIFT 0x1e |
18776 | #define PCTL0_CTRL__PG_ENABLE_MASK 0x00000001L |
18777 | #define PCTL0_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK 0x0000000EL |
18778 | #define PCTL0_CTRL__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x000007F0L |
18779 | #define PCTL0_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x0000F800L |
18780 | #define PCTL0_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00010000L |
18781 | #define PCTL0_CTRL__OVR_EA0_SDP_PARTACK_MASK 0x00020000L |
18782 | #define PCTL0_CTRL__OVR_EA1_SDP_PARTACK_MASK 0x00040000L |
18783 | #define PCTL0_CTRL__OVR_EA2_SDP_PARTACK_MASK 0x00080000L |
18784 | #define PCTL0_CTRL__OVR_EA3_SDP_PARTACK_MASK 0x00100000L |
18785 | #define PCTL0_CTRL__OVR_EA4_SDP_PARTACK_MASK 0x00200000L |
18786 | #define PCTL0_CTRL__OVR_EA5_SDP_PARTACK_MASK 0x00400000L |
18787 | #define PCTL0_CTRL__OVR_EA0_SDP_FULLACK_MASK 0x00800000L |
18788 | #define PCTL0_CTRL__OVR_EA1_SDP_FULLACK_MASK 0x01000000L |
18789 | #define PCTL0_CTRL__OVR_EA2_SDP_FULLACK_MASK 0x02000000L |
18790 | #define PCTL0_CTRL__OVR_EA3_SDP_FULLACK_MASK 0x04000000L |
18791 | #define PCTL0_CTRL__OVR_EA4_SDP_FULLACK_MASK 0x08000000L |
18792 | #define PCTL0_CTRL__OVR_EA5_SDP_FULLACK_MASK 0x10000000L |
18793 | #define PCTL0_CTRL__RSMU_RDTIMER_ENABLE_MASK 0x20000000L |
18794 | #define PCTL0_CTRL__RSMU_RDTIMER_THRESHOLD_MASK 0xC0000000L |
18795 | //PCTL0_MMHUB_DEEPSLEEP_IB |
18796 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS0__SHIFT 0x0 |
18797 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS1__SHIFT 0x1 |
18798 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS2__SHIFT 0x2 |
18799 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS3__SHIFT 0x3 |
18800 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS4__SHIFT 0x4 |
18801 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS5__SHIFT 0x5 |
18802 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS6__SHIFT 0x6 |
18803 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS7__SHIFT 0x7 |
18804 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS8__SHIFT 0x8 |
18805 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS9__SHIFT 0x9 |
18806 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS10__SHIFT 0xa |
18807 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS11__SHIFT 0xb |
18808 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS12__SHIFT 0xc |
18809 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS13__SHIFT 0xd |
18810 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS14__SHIFT 0xe |
18811 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS15__SHIFT 0xf |
18812 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS16__SHIFT 0x10 |
18813 | #define PCTL0_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT 0x1f |
18814 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS0_MASK 0x00000001L |
18815 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS1_MASK 0x00000002L |
18816 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS2_MASK 0x00000004L |
18817 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS3_MASK 0x00000008L |
18818 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS4_MASK 0x00000010L |
18819 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS5_MASK 0x00000020L |
18820 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS6_MASK 0x00000040L |
18821 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS7_MASK 0x00000080L |
18822 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS8_MASK 0x00000100L |
18823 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS9_MASK 0x00000200L |
18824 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS10_MASK 0x00000400L |
18825 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS11_MASK 0x00000800L |
18826 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS12_MASK 0x00001000L |
18827 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS13_MASK 0x00002000L |
18828 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS14_MASK 0x00004000L |
18829 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS15_MASK 0x00008000L |
18830 | #define PCTL0_MMHUB_DEEPSLEEP_IB__DS16_MASK 0x00010000L |
18831 | #define PCTL0_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK 0x80000000L |
18832 | //PCTL0_MMHUB_DEEPSLEEP_OVERRIDE |
18833 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 |
18834 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 |
18835 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 |
18836 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 |
18837 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 |
18838 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 |
18839 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 |
18840 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 |
18841 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 |
18842 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 |
18843 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa |
18844 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb |
18845 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc |
18846 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd |
18847 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe |
18848 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf |
18849 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 |
18850 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT 0x11 |
18851 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS_CANE__SHIFT 0x12 |
18852 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L |
18853 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L |
18854 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L |
18855 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L |
18856 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L |
18857 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L |
18858 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L |
18859 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L |
18860 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L |
18861 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L |
18862 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L |
18863 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L |
18864 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L |
18865 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L |
18866 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L |
18867 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L |
18868 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L |
18869 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK 0x00020000L |
18870 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS_CANE_MASK 0x00040000L |
18871 | //PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB |
18872 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT 0x0 |
18873 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT 0x1 |
18874 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT 0x2 |
18875 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT 0x3 |
18876 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT 0x4 |
18877 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT 0x5 |
18878 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT 0x6 |
18879 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT 0x7 |
18880 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT 0x8 |
18881 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT 0x9 |
18882 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT 0xa |
18883 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT 0xb |
18884 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT 0xc |
18885 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT 0xd |
18886 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT 0xe |
18887 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT 0xf |
18888 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT 0x10 |
18889 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK 0x00000001L |
18890 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK 0x00000002L |
18891 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK 0x00000004L |
18892 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK 0x00000008L |
18893 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK 0x00000010L |
18894 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK 0x00000020L |
18895 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK 0x00000040L |
18896 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK 0x00000080L |
18897 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK 0x00000100L |
18898 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK 0x00000200L |
18899 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK 0x00000400L |
18900 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK 0x00000800L |
18901 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK 0x00001000L |
18902 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK 0x00002000L |
18903 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK 0x00004000L |
18904 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK 0x00008000L |
18905 | #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK 0x00010000L |
18906 | //PCTL0_PG_IGNORE_DEEPSLEEP |
18907 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x0 |
18908 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x1 |
18909 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x2 |
18910 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x3 |
18911 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x4 |
18912 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x5 |
18913 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x6 |
18914 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x7 |
18915 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x8 |
18916 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0x9 |
18917 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xa |
18918 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xb |
18919 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xc |
18920 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xd |
18921 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xe |
18922 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0xf |
18923 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x10 |
18924 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT 0x11 |
18925 | #define PCTL0_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x12 |
18926 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000001L |
18927 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000002L |
18928 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000004L |
18929 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000008L |
18930 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000010L |
18931 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000020L |
18932 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000040L |
18933 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000080L |
18934 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000100L |
18935 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000200L |
18936 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000400L |
18937 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00000800L |
18938 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00001000L |
18939 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00002000L |
18940 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00004000L |
18941 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00008000L |
18942 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00010000L |
18943 | #define PCTL0_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK 0x00020000L |
18944 | #define PCTL0_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00040000L |
18945 | //PCTL0_PG_IGNORE_DEEPSLEEP_IB |
18946 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT 0x0 |
18947 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT 0x1 |
18948 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT 0x2 |
18949 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT 0x3 |
18950 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT 0x4 |
18951 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT 0x5 |
18952 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT 0x6 |
18953 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT 0x7 |
18954 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT 0x8 |
18955 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT 0x9 |
18956 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT 0xa |
18957 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT 0xb |
18958 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT 0xc |
18959 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT 0xd |
18960 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT 0xe |
18961 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT 0xf |
18962 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT 0x10 |
18963 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT 0x11 |
18964 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK 0x00000001L |
18965 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK 0x00000002L |
18966 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK 0x00000004L |
18967 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK 0x00000008L |
18968 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK 0x00000010L |
18969 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK 0x00000020L |
18970 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK 0x00000040L |
18971 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK 0x00000080L |
18972 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK 0x00000100L |
18973 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK 0x00000200L |
18974 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK 0x00000400L |
18975 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK 0x00000800L |
18976 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK 0x00001000L |
18977 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK 0x00002000L |
18978 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK 0x00004000L |
18979 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK 0x00008000L |
18980 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK 0x00010000L |
18981 | #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK 0x00020000L |
18982 | //PCTL0_SLICE0_CFG_DAGB_BUSY |
18983 | #define PCTL0_SLICE0_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 |
18984 | #define PCTL0_SLICE0_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL |
18985 | //PCTL0_SLICE0_CFG_DS_ALLOW |
18986 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS0__SHIFT 0x0 |
18987 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS1__SHIFT 0x1 |
18988 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS2__SHIFT 0x2 |
18989 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS3__SHIFT 0x3 |
18990 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS4__SHIFT 0x4 |
18991 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS5__SHIFT 0x5 |
18992 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS6__SHIFT 0x6 |
18993 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS7__SHIFT 0x7 |
18994 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS8__SHIFT 0x8 |
18995 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS9__SHIFT 0x9 |
18996 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS10__SHIFT 0xa |
18997 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS11__SHIFT 0xb |
18998 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS12__SHIFT 0xc |
18999 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS13__SHIFT 0xd |
19000 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS14__SHIFT 0xe |
19001 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS15__SHIFT 0xf |
19002 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS16__SHIFT 0x10 |
19003 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS0_MASK 0x00000001L |
19004 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS1_MASK 0x00000002L |
19005 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS2_MASK 0x00000004L |
19006 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS3_MASK 0x00000008L |
19007 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS4_MASK 0x00000010L |
19008 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS5_MASK 0x00000020L |
19009 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS6_MASK 0x00000040L |
19010 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS7_MASK 0x00000080L |
19011 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS8_MASK 0x00000100L |
19012 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS9_MASK 0x00000200L |
19013 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS10_MASK 0x00000400L |
19014 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS11_MASK 0x00000800L |
19015 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS12_MASK 0x00001000L |
19016 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS13_MASK 0x00002000L |
19017 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS14_MASK 0x00004000L |
19018 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS15_MASK 0x00008000L |
19019 | #define PCTL0_SLICE0_CFG_DS_ALLOW__DS16_MASK 0x00010000L |
19020 | //PCTL0_SLICE0_CFG_DS_ALLOW_IB |
19021 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 |
19022 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 |
19023 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 |
19024 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 |
19025 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 |
19026 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 |
19027 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 |
19028 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 |
19029 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 |
19030 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 |
19031 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa |
19032 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb |
19033 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc |
19034 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd |
19035 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe |
19036 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf |
19037 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 |
19038 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L |
19039 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L |
19040 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L |
19041 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L |
19042 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L |
19043 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L |
19044 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L |
19045 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L |
19046 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L |
19047 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L |
19048 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L |
19049 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L |
19050 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L |
19051 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L |
19052 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L |
19053 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L |
19054 | #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L |
19055 | //PCTL0_SLICE1_CFG_DAGB_BUSY |
19056 | #define PCTL0_SLICE1_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 |
19057 | #define PCTL0_SLICE1_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL |
19058 | //PCTL0_SLICE1_CFG_DS_ALLOW |
19059 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS0__SHIFT 0x0 |
19060 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS1__SHIFT 0x1 |
19061 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS2__SHIFT 0x2 |
19062 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS3__SHIFT 0x3 |
19063 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS4__SHIFT 0x4 |
19064 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS5__SHIFT 0x5 |
19065 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS6__SHIFT 0x6 |
19066 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS7__SHIFT 0x7 |
19067 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS8__SHIFT 0x8 |
19068 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS9__SHIFT 0x9 |
19069 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS10__SHIFT 0xa |
19070 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS11__SHIFT 0xb |
19071 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS12__SHIFT 0xc |
19072 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS13__SHIFT 0xd |
19073 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS14__SHIFT 0xe |
19074 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS15__SHIFT 0xf |
19075 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS16__SHIFT 0x10 |
19076 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS0_MASK 0x00000001L |
19077 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS1_MASK 0x00000002L |
19078 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS2_MASK 0x00000004L |
19079 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS3_MASK 0x00000008L |
19080 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS4_MASK 0x00000010L |
19081 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS5_MASK 0x00000020L |
19082 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS6_MASK 0x00000040L |
19083 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS7_MASK 0x00000080L |
19084 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS8_MASK 0x00000100L |
19085 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS9_MASK 0x00000200L |
19086 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS10_MASK 0x00000400L |
19087 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS11_MASK 0x00000800L |
19088 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS12_MASK 0x00001000L |
19089 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS13_MASK 0x00002000L |
19090 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS14_MASK 0x00004000L |
19091 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS15_MASK 0x00008000L |
19092 | #define PCTL0_SLICE1_CFG_DS_ALLOW__DS16_MASK 0x00010000L |
19093 | //PCTL0_SLICE1_CFG_DS_ALLOW_IB |
19094 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 |
19095 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 |
19096 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 |
19097 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 |
19098 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 |
19099 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 |
19100 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 |
19101 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 |
19102 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 |
19103 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 |
19104 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa |
19105 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb |
19106 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc |
19107 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd |
19108 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe |
19109 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf |
19110 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 |
19111 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L |
19112 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L |
19113 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L |
19114 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L |
19115 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L |
19116 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L |
19117 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L |
19118 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L |
19119 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L |
19120 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L |
19121 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L |
19122 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L |
19123 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L |
19124 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L |
19125 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L |
19126 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L |
19127 | #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L |
19128 | //PCTL0_SLICE2_CFG_DAGB_BUSY |
19129 | #define PCTL0_SLICE2_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 |
19130 | #define PCTL0_SLICE2_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL |
19131 | //PCTL0_SLICE2_CFG_DS_ALLOW |
19132 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS0__SHIFT 0x0 |
19133 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS1__SHIFT 0x1 |
19134 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS2__SHIFT 0x2 |
19135 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS3__SHIFT 0x3 |
19136 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS4__SHIFT 0x4 |
19137 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS5__SHIFT 0x5 |
19138 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS6__SHIFT 0x6 |
19139 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS7__SHIFT 0x7 |
19140 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS8__SHIFT 0x8 |
19141 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS9__SHIFT 0x9 |
19142 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS10__SHIFT 0xa |
19143 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS11__SHIFT 0xb |
19144 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS12__SHIFT 0xc |
19145 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS13__SHIFT 0xd |
19146 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS14__SHIFT 0xe |
19147 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS15__SHIFT 0xf |
19148 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS16__SHIFT 0x10 |
19149 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS0_MASK 0x00000001L |
19150 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS1_MASK 0x00000002L |
19151 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS2_MASK 0x00000004L |
19152 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS3_MASK 0x00000008L |
19153 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS4_MASK 0x00000010L |
19154 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS5_MASK 0x00000020L |
19155 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS6_MASK 0x00000040L |
19156 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS7_MASK 0x00000080L |
19157 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS8_MASK 0x00000100L |
19158 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS9_MASK 0x00000200L |
19159 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS10_MASK 0x00000400L |
19160 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS11_MASK 0x00000800L |
19161 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS12_MASK 0x00001000L |
19162 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS13_MASK 0x00002000L |
19163 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS14_MASK 0x00004000L |
19164 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS15_MASK 0x00008000L |
19165 | #define PCTL0_SLICE2_CFG_DS_ALLOW__DS16_MASK 0x00010000L |
19166 | //PCTL0_SLICE2_CFG_DS_ALLOW_IB |
19167 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 |
19168 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 |
19169 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 |
19170 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 |
19171 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 |
19172 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 |
19173 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 |
19174 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 |
19175 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 |
19176 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 |
19177 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa |
19178 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb |
19179 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc |
19180 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd |
19181 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe |
19182 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf |
19183 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 |
19184 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L |
19185 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L |
19186 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L |
19187 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L |
19188 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L |
19189 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L |
19190 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L |
19191 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L |
19192 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L |
19193 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L |
19194 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L |
19195 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L |
19196 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L |
19197 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L |
19198 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L |
19199 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L |
19200 | #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L |
19201 | //PCTL0_SLICE3_CFG_DAGB_BUSY |
19202 | #define PCTL0_SLICE3_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 |
19203 | #define PCTL0_SLICE3_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL |
19204 | //PCTL0_SLICE3_CFG_DS_ALLOW |
19205 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS0__SHIFT 0x0 |
19206 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS1__SHIFT 0x1 |
19207 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS2__SHIFT 0x2 |
19208 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS3__SHIFT 0x3 |
19209 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS4__SHIFT 0x4 |
19210 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS5__SHIFT 0x5 |
19211 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS6__SHIFT 0x6 |
19212 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS7__SHIFT 0x7 |
19213 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS8__SHIFT 0x8 |
19214 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS9__SHIFT 0x9 |
19215 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS10__SHIFT 0xa |
19216 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS11__SHIFT 0xb |
19217 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS12__SHIFT 0xc |
19218 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS13__SHIFT 0xd |
19219 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS14__SHIFT 0xe |
19220 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS15__SHIFT 0xf |
19221 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS16__SHIFT 0x10 |
19222 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS0_MASK 0x00000001L |
19223 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS1_MASK 0x00000002L |
19224 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS2_MASK 0x00000004L |
19225 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS3_MASK 0x00000008L |
19226 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS4_MASK 0x00000010L |
19227 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS5_MASK 0x00000020L |
19228 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS6_MASK 0x00000040L |
19229 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS7_MASK 0x00000080L |
19230 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS8_MASK 0x00000100L |
19231 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS9_MASK 0x00000200L |
19232 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS10_MASK 0x00000400L |
19233 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS11_MASK 0x00000800L |
19234 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS12_MASK 0x00001000L |
19235 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS13_MASK 0x00002000L |
19236 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS14_MASK 0x00004000L |
19237 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS15_MASK 0x00008000L |
19238 | #define PCTL0_SLICE3_CFG_DS_ALLOW__DS16_MASK 0x00010000L |
19239 | //PCTL0_SLICE3_CFG_DS_ALLOW_IB |
19240 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 |
19241 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 |
19242 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 |
19243 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 |
19244 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 |
19245 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 |
19246 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 |
19247 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 |
19248 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 |
19249 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 |
19250 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa |
19251 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb |
19252 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc |
19253 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd |
19254 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe |
19255 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf |
19256 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 |
19257 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L |
19258 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L |
19259 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L |
19260 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L |
19261 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L |
19262 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L |
19263 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L |
19264 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L |
19265 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L |
19266 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L |
19267 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L |
19268 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L |
19269 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L |
19270 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L |
19271 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L |
19272 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L |
19273 | #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L |
19274 | //PCTL0_SLICE4_CFG_DAGB_BUSY |
19275 | #define PCTL0_SLICE4_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 |
19276 | #define PCTL0_SLICE4_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL |
19277 | //PCTL0_SLICE4_CFG_DS_ALLOW |
19278 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS0__SHIFT 0x0 |
19279 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS1__SHIFT 0x1 |
19280 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS2__SHIFT 0x2 |
19281 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS3__SHIFT 0x3 |
19282 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS4__SHIFT 0x4 |
19283 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS5__SHIFT 0x5 |
19284 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS6__SHIFT 0x6 |
19285 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS7__SHIFT 0x7 |
19286 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS8__SHIFT 0x8 |
19287 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS9__SHIFT 0x9 |
19288 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS10__SHIFT 0xa |
19289 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS11__SHIFT 0xb |
19290 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS12__SHIFT 0xc |
19291 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS13__SHIFT 0xd |
19292 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS14__SHIFT 0xe |
19293 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS15__SHIFT 0xf |
19294 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS16__SHIFT 0x10 |
19295 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS0_MASK 0x00000001L |
19296 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS1_MASK 0x00000002L |
19297 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS2_MASK 0x00000004L |
19298 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS3_MASK 0x00000008L |
19299 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS4_MASK 0x00000010L |
19300 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS5_MASK 0x00000020L |
19301 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS6_MASK 0x00000040L |
19302 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS7_MASK 0x00000080L |
19303 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS8_MASK 0x00000100L |
19304 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS9_MASK 0x00000200L |
19305 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS10_MASK 0x00000400L |
19306 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS11_MASK 0x00000800L |
19307 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS12_MASK 0x00001000L |
19308 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS13_MASK 0x00002000L |
19309 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS14_MASK 0x00004000L |
19310 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS15_MASK 0x00008000L |
19311 | #define PCTL0_SLICE4_CFG_DS_ALLOW__DS16_MASK 0x00010000L |
19312 | //PCTL0_SLICE4_CFG_DS_ALLOW_IB |
19313 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 |
19314 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 |
19315 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 |
19316 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 |
19317 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 |
19318 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 |
19319 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 |
19320 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 |
19321 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 |
19322 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 |
19323 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa |
19324 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb |
19325 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc |
19326 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd |
19327 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe |
19328 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf |
19329 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 |
19330 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L |
19331 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L |
19332 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L |
19333 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L |
19334 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L |
19335 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L |
19336 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L |
19337 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L |
19338 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L |
19339 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L |
19340 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L |
19341 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L |
19342 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L |
19343 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L |
19344 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L |
19345 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L |
19346 | #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L |
19347 | //PCTL0_UTCL2_MISC |
19348 | #define PCTL0_UTCL2_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0 |
19349 | #define PCTL0_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb |
19350 | #define PCTL0_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc |
19351 | #define PCTL0_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf |
19352 | #define PCTL0_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 |
19353 | #define PCTL0_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 |
19354 | #define PCTL0_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT 0x12 |
19355 | #define PCTL0_UTCL2_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000007FFL |
19356 | #define PCTL0_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L |
19357 | #define PCTL0_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L |
19358 | #define PCTL0_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L |
19359 | #define PCTL0_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L |
19360 | #define PCTL0_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L |
19361 | #define PCTL0_UTCL2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L |
19362 | //PCTL0_SLICE0_MISC |
19363 | #define PCTL0_SLICE0_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0 |
19364 | #define PCTL0_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa |
19365 | #define PCTL0_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb |
19366 | #define PCTL0_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe |
19367 | #define PCTL0_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf |
19368 | #define PCTL0_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 |
19369 | #define PCTL0_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 |
19370 | #define PCTL0_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT 0x12 |
19371 | #define PCTL0_SLICE0_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000003FFL |
19372 | #define PCTL0_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L |
19373 | #define PCTL0_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L |
19374 | #define PCTL0_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L |
19375 | #define PCTL0_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L |
19376 | #define PCTL0_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L |
19377 | #define PCTL0_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L |
19378 | #define PCTL0_SLICE0_MISC__RD_TIMER_ENABLE_MASK 0x00040000L |
19379 | //PCTL0_SLICE1_MISC |
19380 | #define PCTL0_SLICE1_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0 |
19381 | #define PCTL0_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa |
19382 | #define PCTL0_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb |
19383 | #define PCTL0_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe |
19384 | #define PCTL0_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf |
19385 | #define PCTL0_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 |
19386 | #define PCTL0_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 |
19387 | #define PCTL0_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT 0x12 |
19388 | #define PCTL0_SLICE1_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000003FFL |
19389 | #define PCTL0_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L |
19390 | #define PCTL0_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L |
19391 | #define PCTL0_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L |
19392 | #define PCTL0_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L |
19393 | #define PCTL0_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L |
19394 | #define PCTL0_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L |
19395 | #define PCTL0_SLICE1_MISC__RD_TIMER_ENABLE_MASK 0x00040000L |
19396 | //PCTL0_SLICE2_MISC |
19397 | #define PCTL0_SLICE2_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0 |
19398 | #define PCTL0_SLICE2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa |
19399 | #define PCTL0_SLICE2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb |
19400 | #define PCTL0_SLICE2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe |
19401 | #define PCTL0_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf |
19402 | #define PCTL0_SLICE2_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 |
19403 | #define PCTL0_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 |
19404 | #define PCTL0_SLICE2_MISC__RD_TIMER_ENABLE__SHIFT 0x12 |
19405 | #define PCTL0_SLICE2_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000003FFL |
19406 | #define PCTL0_SLICE2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L |
19407 | #define PCTL0_SLICE2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L |
19408 | #define PCTL0_SLICE2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L |
19409 | #define PCTL0_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L |
19410 | #define PCTL0_SLICE2_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L |
19411 | #define PCTL0_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L |
19412 | #define PCTL0_SLICE2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L |
19413 | //PCTL0_SLICE3_MISC |
19414 | #define PCTL0_SLICE3_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0 |
19415 | #define PCTL0_SLICE3_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa |
19416 | #define PCTL0_SLICE3_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb |
19417 | #define PCTL0_SLICE3_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe |
19418 | #define PCTL0_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf |
19419 | #define PCTL0_SLICE3_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 |
19420 | #define PCTL0_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 |
19421 | #define PCTL0_SLICE3_MISC__RD_TIMER_ENABLE__SHIFT 0x12 |
19422 | #define PCTL0_SLICE3_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000003FFL |
19423 | #define PCTL0_SLICE3_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L |
19424 | #define PCTL0_SLICE3_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L |
19425 | #define PCTL0_SLICE3_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L |
19426 | #define PCTL0_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L |
19427 | #define PCTL0_SLICE3_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L |
19428 | #define PCTL0_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L |
19429 | #define PCTL0_SLICE3_MISC__RD_TIMER_ENABLE_MASK 0x00040000L |
19430 | //PCTL0_SLICE4_MISC |
19431 | #define PCTL0_SLICE4_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0 |
19432 | #define PCTL0_SLICE4_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa |
19433 | #define PCTL0_SLICE4_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb |
19434 | #define PCTL0_SLICE4_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe |
19435 | #define PCTL0_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf |
19436 | #define PCTL0_SLICE4_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 |
19437 | #define PCTL0_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 |
19438 | #define PCTL0_SLICE4_MISC__RD_TIMER_ENABLE__SHIFT 0x12 |
19439 | #define PCTL0_SLICE4_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000003FFL |
19440 | #define PCTL0_SLICE4_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L |
19441 | #define PCTL0_SLICE4_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L |
19442 | #define PCTL0_SLICE4_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L |
19443 | #define PCTL0_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L |
19444 | #define PCTL0_SLICE4_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L |
19445 | #define PCTL0_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L |
19446 | #define PCTL0_SLICE4_MISC__RD_TIMER_ENABLE_MASK 0x00040000L |
19447 | |
19448 | |
19449 | // addressBlock: aid_mmhub_l1tlb_vml1dec |
19450 | //MC_VM_MX_L1_TLB0_STATUS |
19451 | #define MC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0 |
19452 | #define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 |
19453 | #define MC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L |
19454 | #define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L |
19455 | //MC_VM_MX_L1_TLB1_STATUS |
19456 | #define MC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0 |
19457 | #define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 |
19458 | #define MC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L |
19459 | #define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L |
19460 | //MC_VM_MX_L1_TLB2_STATUS |
19461 | #define MC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0 |
19462 | #define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 |
19463 | #define MC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L |
19464 | #define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L |
19465 | //MC_VM_MX_L1_TLB3_STATUS |
19466 | #define MC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0 |
19467 | #define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 |
19468 | #define MC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L |
19469 | #define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L |
19470 | //MC_VM_MX_L1_TLB4_STATUS |
19471 | #define MC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0 |
19472 | #define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 |
19473 | #define MC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L |
19474 | #define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L |
19475 | //MC_VM_MX_L1_TLB5_STATUS |
19476 | #define MC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0 |
19477 | #define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 |
19478 | #define MC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L |
19479 | #define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L |
19480 | //MC_VM_MX_L1_TLB6_STATUS |
19481 | #define MC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0 |
19482 | #define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 |
19483 | #define MC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L |
19484 | #define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L |
19485 | //MC_VM_MX_L1_TLB7_STATUS |
19486 | #define MC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0 |
19487 | #define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 |
19488 | #define MC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L |
19489 | #define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L |
19490 | |
19491 | |
19492 | // addressBlock: aid_mmhub_l1tlb_vml1pldec |
19493 | //MC_VM_MX_L1_PERFCOUNTER0_CFG |
19494 | #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
19495 | #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
19496 | #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
19497 | #define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
19498 | #define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
19499 | #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
19500 | #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
19501 | #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
19502 | #define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
19503 | #define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
19504 | //MC_VM_MX_L1_PERFCOUNTER1_CFG |
19505 | #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
19506 | #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
19507 | #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
19508 | #define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
19509 | #define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
19510 | #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
19511 | #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
19512 | #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
19513 | #define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
19514 | #define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
19515 | //MC_VM_MX_L1_PERFCOUNTER2_CFG |
19516 | #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 |
19517 | #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 |
19518 | #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 |
19519 | #define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c |
19520 | #define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d |
19521 | #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL |
19522 | #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L |
19523 | #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L |
19524 | #define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L |
19525 | #define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L |
19526 | //MC_VM_MX_L1_PERFCOUNTER3_CFG |
19527 | #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 |
19528 | #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 |
19529 | #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 |
19530 | #define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c |
19531 | #define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d |
19532 | #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL |
19533 | #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L |
19534 | #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L |
19535 | #define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L |
19536 | #define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L |
19537 | //MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL |
19538 | #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
19539 | #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
19540 | #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
19541 | #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
19542 | #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
19543 | #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
19544 | #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
19545 | #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
19546 | #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
19547 | #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
19548 | #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
19549 | #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
19550 | |
19551 | |
19552 | // addressBlock: aid_mmhub_l1tlb_vml1prdec |
19553 | //MC_VM_MX_L1_PERFCOUNTER_LO |
19554 | #define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
19555 | #define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
19556 | //MC_VM_MX_L1_PERFCOUNTER_HI |
19557 | #define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
19558 | #define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
19559 | #define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
19560 | #define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
19561 | |
19562 | |
19563 | // addressBlock: aid_mmhub_utcl2_atcl2dec |
19564 | //ATC_L2_CNTL |
19565 | #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 |
19566 | #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 |
19567 | #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 |
19568 | #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 |
19569 | #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT 0x8 |
19570 | #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT 0xb |
19571 | #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0xe |
19572 | #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0xf |
19573 | #define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x10 |
19574 | #define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0x13 |
19575 | #define ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x14 |
19576 | #define ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT 0x16 |
19577 | #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L |
19578 | #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L |
19579 | #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L |
19580 | #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L |
19581 | #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK 0x00000300L |
19582 | #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK 0x00001800L |
19583 | #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00004000L |
19584 | #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00008000L |
19585 | #define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00070000L |
19586 | #define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00080000L |
19587 | #define ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK 0x00300000L |
19588 | #define ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK 0x0FC00000L |
19589 | //ATC_L2_CNTL2 |
19590 | #define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 |
19591 | #define ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT 0x6 |
19592 | #define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x9 |
19593 | #define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xb |
19594 | #define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0xc |
19595 | #define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xf |
19596 | #define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x12 |
19597 | #define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL |
19598 | #define ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK 0x000001C0L |
19599 | #define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x00000600L |
19600 | #define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000800L |
19601 | #define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00007000L |
19602 | #define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00038000L |
19603 | #define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00FC0000L |
19604 | //ATC_L2_CACHE_DATA0 |
19605 | #define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 |
19606 | #define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 |
19607 | #define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 |
19608 | #define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17 |
19609 | #define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L |
19610 | #define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L |
19611 | #define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL |
19612 | #define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L |
19613 | //ATC_L2_CACHE_DATA1 |
19614 | #define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 |
19615 | #define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL |
19616 | //ATC_L2_CACHE_DATA2 |
19617 | #define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 |
19618 | #define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL |
19619 | //ATC_L2_CACHE_DATA3 |
19620 | #define ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 |
19621 | #define ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL |
19622 | //ATC_L2_CNTL3 |
19623 | #define ATC_L2_CNTL3__L2_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
19624 | #define ATC_L2_CNTL3__L2_MIDK_FRAGMENT_SIZE__SHIFT 0x6 |
19625 | #define ATC_L2_CNTL3__L2_BIGK_FRAGMENT_SIZE__SHIFT 0xc |
19626 | #define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x12 |
19627 | #define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x15 |
19628 | #define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x1b |
19629 | #define ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT 0x1e |
19630 | #define ATC_L2_CNTL3__L2_SMALLK_FRAGMENT_SIZE_MASK 0x0000003FL |
19631 | #define ATC_L2_CNTL3__L2_MIDK_FRAGMENT_SIZE_MASK 0x00000FC0L |
19632 | #define ATC_L2_CNTL3__L2_BIGK_FRAGMENT_SIZE_MASK 0x0003F000L |
19633 | #define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x001C0000L |
19634 | #define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x07E00000L |
19635 | #define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x38000000L |
19636 | #define ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK 0x40000000L |
19637 | //ATC_L2_STATUS |
19638 | #define ATC_L2_STATUS__BUSY__SHIFT 0x0 |
19639 | #define ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS__SHIFT 0x1 |
19640 | #define ATC_L2_STATUS__BUSY_MASK 0x00000001L |
19641 | #define ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS_MASK 0x00000002L |
19642 | //ATC_L2_STATUS2 |
19643 | #define ATC_L2_STATUS2__UCE_MEM_ADDR__SHIFT 0x0 |
19644 | #define ATC_L2_STATUS2__UCE_MEM_INST__SHIFT 0xc |
19645 | #define ATC_L2_STATUS2__UCE_SRT_CACHE__SHIFT 0x14 |
19646 | #define ATC_L2_STATUS2__UCE__SHIFT 0x15 |
19647 | #define ATC_L2_STATUS2__UCE_MEM_ADDR_MASK 0x00000FFFL |
19648 | #define ATC_L2_STATUS2__UCE_MEM_INST_MASK 0x000FF000L |
19649 | #define ATC_L2_STATUS2__UCE_SRT_CACHE_MASK 0x00100000L |
19650 | #define ATC_L2_STATUS2__UCE_MASK 0x00200000L |
19651 | //ATC_L2_MISC_CG |
19652 | #define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 |
19653 | #define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 |
19654 | #define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 |
19655 | #define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L |
19656 | #define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L |
19657 | #define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L |
19658 | //ATC_L2_MEM_POWER_LS |
19659 | #define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 |
19660 | #define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 |
19661 | #define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL |
19662 | #define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L |
19663 | //ATC_L2_CGTT_CLK_CTRL |
19664 | #define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
19665 | #define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
19666 | #define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
19667 | #define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 |
19668 | #define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 |
19669 | #define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
19670 | #define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
19671 | #define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
19672 | #define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L |
19673 | #define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L |
19674 | //ATC_L2_CACHE_4K_DSM_INDEX |
19675 | #define ATC_L2_CACHE_4K_DSM_INDEX__INDEX__SHIFT 0x0 |
19676 | #define ATC_L2_CACHE_4K_DSM_INDEX__INDEX_MASK 0x000000FFL |
19677 | //ATC_L2_CACHE_32K_DSM_INDEX |
19678 | #define ATC_L2_CACHE_32K_DSM_INDEX__INDEX__SHIFT 0x0 |
19679 | #define ATC_L2_CACHE_32K_DSM_INDEX__INDEX_MASK 0x000000FFL |
19680 | //ATC_L2_CACHE_2M_DSM_INDEX |
19681 | #define ATC_L2_CACHE_2M_DSM_INDEX__INDEX__SHIFT 0x0 |
19682 | #define ATC_L2_CACHE_2M_DSM_INDEX__INDEX_MASK 0x000000FFL |
19683 | //ATC_L2_CACHE_4K_DSM_CNTL |
19684 | #define ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY__SHIFT 0x0 |
19685 | #define ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 |
19686 | #define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 |
19687 | #define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 |
19688 | #define ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb |
19689 | #define ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc |
19690 | #define ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT__SHIFT 0xd |
19691 | #define ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT__SHIFT 0xf |
19692 | #define ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE__SHIFT 0x11 |
19693 | #define ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL |
19694 | #define ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L |
19695 | #define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L |
19696 | #define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L |
19697 | #define ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L |
19698 | #define ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L |
19699 | #define ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT_MASK 0x00006000L |
19700 | #define ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT_MASK 0x00018000L |
19701 | #define ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE_MASK 0x00020000L |
19702 | //ATC_L2_CACHE_32K_DSM_CNTL |
19703 | #define ATC_L2_CACHE_32K_DSM_CNTL__INJECT_DELAY__SHIFT 0x0 |
19704 | #define ATC_L2_CACHE_32K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 |
19705 | #define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 |
19706 | #define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 |
19707 | #define ATC_L2_CACHE_32K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb |
19708 | #define ATC_L2_CACHE_32K_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc |
19709 | #define ATC_L2_CACHE_32K_DSM_CNTL__SEC_COUNT__SHIFT 0xd |
19710 | #define ATC_L2_CACHE_32K_DSM_CNTL__DED_COUNT__SHIFT 0xf |
19711 | #define ATC_L2_CACHE_32K_DSM_CNTL__TEST_FUE__SHIFT 0x11 |
19712 | #define ATC_L2_CACHE_32K_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL |
19713 | #define ATC_L2_CACHE_32K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L |
19714 | #define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L |
19715 | #define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L |
19716 | #define ATC_L2_CACHE_32K_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L |
19717 | #define ATC_L2_CACHE_32K_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L |
19718 | #define ATC_L2_CACHE_32K_DSM_CNTL__SEC_COUNT_MASK 0x00006000L |
19719 | #define ATC_L2_CACHE_32K_DSM_CNTL__DED_COUNT_MASK 0x00018000L |
19720 | #define ATC_L2_CACHE_32K_DSM_CNTL__TEST_FUE_MASK 0x00020000L |
19721 | //ATC_L2_CACHE_2M_DSM_CNTL |
19722 | #define ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY__SHIFT 0x0 |
19723 | #define ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 |
19724 | #define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 |
19725 | #define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 |
19726 | #define ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb |
19727 | #define ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc |
19728 | #define ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT__SHIFT 0xd |
19729 | #define ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT__SHIFT 0xf |
19730 | #define ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE__SHIFT 0x11 |
19731 | #define ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL |
19732 | #define ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L |
19733 | #define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L |
19734 | #define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L |
19735 | #define ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L |
19736 | #define ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L |
19737 | #define ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT_MASK 0x00006000L |
19738 | #define ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT_MASK 0x00018000L |
19739 | #define ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE_MASK 0x00020000L |
19740 | //ATC_L2_CNTL4 |
19741 | #define ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x0 |
19742 | #define ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0xa |
19743 | #define ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000003FFL |
19744 | #define ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000FFC00L |
19745 | //ATC_L2_MM_GROUP_RT_CLASSES |
19746 | #define ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT 0x0 |
19747 | #define ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK 0xFFFFFFFFL |
19748 | |
19749 | |
19750 | // addressBlock: aid_mmhub_utcl2_vml2pfdec |
19751 | //VM_L2_CNTL |
19752 | #define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 |
19753 | #define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 |
19754 | #define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 |
19755 | #define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 |
19756 | #define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 |
19757 | #define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 |
19758 | #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa |
19759 | #define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb |
19760 | #define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc |
19761 | #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf |
19762 | #define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 |
19763 | #define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 |
19764 | #define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 |
19765 | #define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a |
19766 | #define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L |
19767 | #define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L |
19768 | #define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL |
19769 | #define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L |
19770 | #define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L |
19771 | #define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L |
19772 | #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L |
19773 | #define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L |
19774 | #define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L |
19775 | #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L |
19776 | #define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L |
19777 | #define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L |
19778 | #define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L |
19779 | #define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L |
19780 | //VM_L2_CNTL2 |
19781 | #define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 |
19782 | #define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 |
19783 | #define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 |
19784 | #define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 |
19785 | #define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 |
19786 | #define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a |
19787 | #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c |
19788 | #define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L |
19789 | #define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L |
19790 | #define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L |
19791 | #define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L |
19792 | #define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L |
19793 | #define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L |
19794 | #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L |
19795 | //VM_L2_CNTL3 |
19796 | #define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 |
19797 | #define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 |
19798 | #define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 |
19799 | #define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf |
19800 | #define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 |
19801 | #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 |
19802 | #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 |
19803 | #define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c |
19804 | #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d |
19805 | #define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e |
19806 | #define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f |
19807 | #define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL |
19808 | #define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L |
19809 | #define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L |
19810 | #define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L |
19811 | #define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L |
19812 | #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L |
19813 | #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L |
19814 | #define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L |
19815 | #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L |
19816 | #define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L |
19817 | #define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L |
19818 | //VM_L2_STATUS |
19819 | #define VM_L2_STATUS__L2_BUSY__SHIFT 0x0 |
19820 | #define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 |
19821 | #define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 |
19822 | #define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 |
19823 | #define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 |
19824 | #define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 |
19825 | #define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 |
19826 | #define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L |
19827 | #define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL |
19828 | #define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L |
19829 | #define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L |
19830 | #define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L |
19831 | #define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L |
19832 | #define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L |
19833 | //VM_DUMMY_PAGE_FAULT_CNTL |
19834 | #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 |
19835 | #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 |
19836 | #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 |
19837 | #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L |
19838 | #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L |
19839 | #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL |
19840 | //VM_DUMMY_PAGE_FAULT_ADDR_LO32 |
19841 | #define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 |
19842 | #define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL |
19843 | //VM_DUMMY_PAGE_FAULT_ADDR_HI32 |
19844 | #define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 |
19845 | #define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL |
19846 | //VM_L2_PROTECTION_FAULT_CNTL |
19847 | #define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 |
19848 | #define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 |
19849 | #define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 |
19850 | #define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 |
19851 | #define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 |
19852 | #define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 |
19853 | #define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 |
19854 | #define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 |
19855 | #define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 |
19856 | #define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 |
19857 | #define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
19858 | #define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb |
19859 | #define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
19860 | #define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd |
19861 | #define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d |
19862 | #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e |
19863 | #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f |
19864 | #define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L |
19865 | #define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L |
19866 | #define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L |
19867 | #define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L |
19868 | #define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L |
19869 | #define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L |
19870 | #define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L |
19871 | #define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L |
19872 | #define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L |
19873 | #define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L |
19874 | #define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
19875 | #define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L |
19876 | #define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
19877 | #define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L |
19878 | #define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L |
19879 | #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L |
19880 | #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L |
19881 | //VM_L2_PROTECTION_FAULT_CNTL2 |
19882 | #define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 |
19883 | #define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 |
19884 | #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 |
19885 | #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 |
19886 | #define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 |
19887 | #define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL |
19888 | #define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L |
19889 | #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L |
19890 | #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L |
19891 | #define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L |
19892 | //VM_L2_PROTECTION_FAULT_MM_CNTL3 |
19893 | #define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 |
19894 | #define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL |
19895 | //VM_L2_PROTECTION_FAULT_MM_CNTL4 |
19896 | #define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 |
19897 | #define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL |
19898 | //VM_L2_PROTECTION_FAULT_STATUS |
19899 | #define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 |
19900 | #define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 |
19901 | #define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 |
19902 | #define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 |
19903 | #define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 |
19904 | #define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 |
19905 | #define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 |
19906 | #define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 |
19907 | #define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 |
19908 | #define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 |
19909 | #define VM_L2_PROTECTION_FAULT_STATUS__UCE__SHIFT 0x1d |
19910 | #define VM_L2_PROTECTION_FAULT_STATUS__FED__SHIFT 0x1e |
19911 | #define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L |
19912 | #define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL |
19913 | #define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L |
19914 | #define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L |
19915 | #define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L |
19916 | #define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L |
19917 | #define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L |
19918 | #define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L |
19919 | #define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L |
19920 | #define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L |
19921 | #define VM_L2_PROTECTION_FAULT_STATUS__UCE_MASK 0x20000000L |
19922 | #define VM_L2_PROTECTION_FAULT_STATUS__FED_MASK 0x40000000L |
19923 | //VM_L2_PROTECTION_FAULT_ADDR_LO32 |
19924 | #define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 |
19925 | #define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL |
19926 | //VM_L2_PROTECTION_FAULT_ADDR_HI32 |
19927 | #define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 |
19928 | #define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL |
19929 | //VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 |
19930 | #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 |
19931 | #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL |
19932 | //VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 |
19933 | #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 |
19934 | #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL |
19935 | //VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 |
19936 | #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
19937 | #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
19938 | //VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 |
19939 | #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
19940 | #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
19941 | //VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 |
19942 | #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
19943 | #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
19944 | //VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 |
19945 | #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
19946 | #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
19947 | //VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 |
19948 | #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 |
19949 | #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL |
19950 | //VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 |
19951 | #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 |
19952 | #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL |
19953 | //VM_L2_CNTL4 |
19954 | #define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 |
19955 | #define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 |
19956 | #define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 |
19957 | #define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 |
19958 | #define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 |
19959 | #define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c |
19960 | #define VM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d |
19961 | #define VM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT 0x1e |
19962 | #define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL |
19963 | #define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L |
19964 | #define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L |
19965 | #define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L |
19966 | #define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L |
19967 | #define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L |
19968 | #define VM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L |
19969 | #define VM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK 0x40000000L |
19970 | //VM_L2_CNTL5 |
19971 | #define VM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT 0x0 |
19972 | #define VM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT 0x1 |
19973 | #define VM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK 0x00000001L |
19974 | #define VM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK 0x00000002L |
19975 | //VM_L2_MM_GROUP_RT_CLASSES |
19976 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 |
19977 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 |
19978 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 |
19979 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 |
19980 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 |
19981 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 |
19982 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 |
19983 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 |
19984 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 |
19985 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 |
19986 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa |
19987 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb |
19988 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc |
19989 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd |
19990 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe |
19991 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf |
19992 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 |
19993 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 |
19994 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 |
19995 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 |
19996 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 |
19997 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 |
19998 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 |
19999 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 |
20000 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 |
20001 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 |
20002 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a |
20003 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b |
20004 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c |
20005 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d |
20006 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e |
20007 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f |
20008 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L |
20009 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L |
20010 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L |
20011 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L |
20012 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L |
20013 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L |
20014 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L |
20015 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L |
20016 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L |
20017 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L |
20018 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L |
20019 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L |
20020 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L |
20021 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L |
20022 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L |
20023 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L |
20024 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L |
20025 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L |
20026 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L |
20027 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L |
20028 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L |
20029 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L |
20030 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L |
20031 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L |
20032 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L |
20033 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L |
20034 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L |
20035 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L |
20036 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L |
20037 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L |
20038 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L |
20039 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L |
20040 | //VM_L2_BANK_SELECT_RESERVED_CID |
20041 | #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 |
20042 | #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa |
20043 | #define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 |
20044 | #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 |
20045 | #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 |
20046 | #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL |
20047 | #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L |
20048 | #define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L |
20049 | #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L |
20050 | #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L |
20051 | //VM_L2_BANK_SELECT_RESERVED_CID2 |
20052 | #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 |
20053 | #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa |
20054 | #define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 |
20055 | #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 |
20056 | #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 |
20057 | #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL |
20058 | #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L |
20059 | #define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L |
20060 | #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L |
20061 | #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L |
20062 | //VM_L2_CACHE_PARITY_CNTL |
20063 | #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 |
20064 | #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 |
20065 | #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 |
20066 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 |
20067 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 |
20068 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 |
20069 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 |
20070 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 |
20071 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc |
20072 | #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L |
20073 | #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L |
20074 | #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L |
20075 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L |
20076 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L |
20077 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L |
20078 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L |
20079 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L |
20080 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L |
20081 | //VM_L2_CGTT_CLK_CTRL |
20082 | #define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
20083 | #define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
20084 | #define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
20085 | #define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 |
20086 | #define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 |
20087 | #define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
20088 | #define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
20089 | #define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
20090 | #define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L |
20091 | #define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L |
20092 | //VM_L2_CGTT_BUSY_CTRL |
20093 | #define VM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 |
20094 | #define VM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x4 |
20095 | #define VM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000000FL |
20096 | #define VM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000010L |
20097 | //VML2_MEM_ECC_INDEX |
20098 | #define VML2_MEM_ECC_INDEX__INDEX__SHIFT 0x0 |
20099 | #define VML2_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL |
20100 | //VML2_WALKER_MEM_ECC_INDEX |
20101 | #define VML2_WALKER_MEM_ECC_INDEX__INDEX__SHIFT 0x0 |
20102 | #define VML2_WALKER_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL |
20103 | //UTCL2_MEM_ECC_INDEX |
20104 | #define UTCL2_MEM_ECC_INDEX__INDEX__SHIFT 0x0 |
20105 | #define UTCL2_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL |
20106 | //VML2_MEM_ECC_CNTL |
20107 | #define VML2_MEM_ECC_CNTL__INJECT_DELAY__SHIFT 0x0 |
20108 | #define VML2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 |
20109 | #define VML2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 |
20110 | #define VML2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 |
20111 | #define VML2_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb |
20112 | #define VML2_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc |
20113 | #define VML2_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe |
20114 | #define VML2_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT 0x10 |
20115 | #define VML2_MEM_ECC_CNTL__TEST_FUE__SHIFT 0x11 |
20116 | #define VML2_MEM_ECC_CNTL__INJECT_DELAY_MASK 0x0000003FL |
20117 | #define VML2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L |
20118 | #define VML2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L |
20119 | #define VML2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L |
20120 | #define VML2_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L |
20121 | #define VML2_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L |
20122 | #define VML2_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L |
20123 | #define VML2_MEM_ECC_CNTL__WRITE_COUNTERS_MASK 0x00010000L |
20124 | #define VML2_MEM_ECC_CNTL__TEST_FUE_MASK 0x00020000L |
20125 | //VML2_WALKER_MEM_ECC_CNTL |
20126 | #define VML2_WALKER_MEM_ECC_CNTL__INJECT_DELAY__SHIFT 0x0 |
20127 | #define VML2_WALKER_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 |
20128 | #define VML2_WALKER_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 |
20129 | #define VML2_WALKER_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 |
20130 | #define VML2_WALKER_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb |
20131 | #define VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc |
20132 | #define VML2_WALKER_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe |
20133 | #define VML2_WALKER_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT 0x10 |
20134 | #define VML2_WALKER_MEM_ECC_CNTL__TEST_FUE__SHIFT 0x11 |
20135 | #define VML2_WALKER_MEM_ECC_CNTL__INJECT_DELAY_MASK 0x0000003FL |
20136 | #define VML2_WALKER_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L |
20137 | #define VML2_WALKER_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L |
20138 | #define VML2_WALKER_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L |
20139 | #define VML2_WALKER_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L |
20140 | #define VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L |
20141 | #define VML2_WALKER_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L |
20142 | #define VML2_WALKER_MEM_ECC_CNTL__WRITE_COUNTERS_MASK 0x00010000L |
20143 | #define VML2_WALKER_MEM_ECC_CNTL__TEST_FUE_MASK 0x00020000L |
20144 | //UTCL2_MEM_ECC_CNTL |
20145 | #define UTCL2_MEM_ECC_CNTL__INJECT_DELAY__SHIFT 0x0 |
20146 | #define UTCL2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 |
20147 | #define UTCL2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 |
20148 | #define UTCL2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 |
20149 | #define UTCL2_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb |
20150 | #define UTCL2_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc |
20151 | #define UTCL2_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe |
20152 | #define UTCL2_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT 0x10 |
20153 | #define UTCL2_MEM_ECC_CNTL__TEST_FUE__SHIFT 0x11 |
20154 | #define UTCL2_MEM_ECC_CNTL__INJECT_DELAY_MASK 0x0000003FL |
20155 | #define UTCL2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L |
20156 | #define UTCL2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L |
20157 | #define UTCL2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L |
20158 | #define UTCL2_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L |
20159 | #define UTCL2_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L |
20160 | #define UTCL2_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L |
20161 | #define UTCL2_MEM_ECC_CNTL__WRITE_COUNTERS_MASK 0x00010000L |
20162 | #define UTCL2_MEM_ECC_CNTL__TEST_FUE_MASK 0x00020000L |
20163 | //VML2_MEM_ECC_STATUS |
20164 | #define VML2_MEM_ECC_STATUS__UCE__SHIFT 0x0 |
20165 | #define VML2_MEM_ECC_STATUS__FED__SHIFT 0x1 |
20166 | #define VML2_MEM_ECC_STATUS__UCE_MASK 0x00000001L |
20167 | #define VML2_MEM_ECC_STATUS__FED_MASK 0x00000002L |
20168 | //VML2_WALKER_MEM_ECC_STATUS |
20169 | #define VML2_WALKER_MEM_ECC_STATUS__UCE__SHIFT 0x0 |
20170 | #define VML2_WALKER_MEM_ECC_STATUS__FED__SHIFT 0x1 |
20171 | #define VML2_WALKER_MEM_ECC_STATUS__UCE_MASK 0x00000001L |
20172 | #define VML2_WALKER_MEM_ECC_STATUS__FED_MASK 0x00000002L |
20173 | //UTCL2_MEM_ECC_STATUS |
20174 | #define UTCL2_MEM_ECC_STATUS__UCE__SHIFT 0x0 |
20175 | #define UTCL2_MEM_ECC_STATUS__FED__SHIFT 0x1 |
20176 | #define UTCL2_MEM_ECC_STATUS__UCE_MASK 0x00000001L |
20177 | #define UTCL2_MEM_ECC_STATUS__FED_MASK 0x00000002L |
20178 | //UTCL2_EDC_MODE |
20179 | #define UTCL2_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf |
20180 | #define UTCL2_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 |
20181 | #define UTCL2_EDC_MODE__GATE_FUE__SHIFT 0x11 |
20182 | #define UTCL2_EDC_MODE__DED_MODE__SHIFT 0x14 |
20183 | #define UTCL2_EDC_MODE__PROP_FED__SHIFT 0x1d |
20184 | #define UTCL2_EDC_MODE__BYPASS__SHIFT 0x1f |
20185 | #define UTCL2_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L |
20186 | #define UTCL2_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L |
20187 | #define UTCL2_EDC_MODE__GATE_FUE_MASK 0x00020000L |
20188 | #define UTCL2_EDC_MODE__DED_MODE_MASK 0x00300000L |
20189 | #define UTCL2_EDC_MODE__PROP_FED_MASK 0x20000000L |
20190 | #define UTCL2_EDC_MODE__BYPASS_MASK 0x80000000L |
20191 | //UTCL2_EDC_CONFIG |
20192 | #define UTCL2_EDC_CONFIG__WRITE_DIS__SHIFT 0x0 |
20193 | #define UTCL2_EDC_CONFIG__DIS_EDC__SHIFT 0x1 |
20194 | #define UTCL2_EDC_CONFIG__WRITE_DIS_MASK 0x00000001L |
20195 | #define UTCL2_EDC_CONFIG__DIS_EDC_MASK 0x00000002L |
20196 | |
20197 | |
20198 | // addressBlock: aid_mmhub_utcl2_vml2vcdec |
20199 | //VM_CONTEXT0_CNTL |
20200 | #define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
20201 | #define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
20202 | #define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
20203 | #define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
20204 | #define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
20205 | #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
20206 | #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
20207 | #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
20208 | #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
20209 | #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
20210 | #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
20211 | #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
20212 | #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
20213 | #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
20214 | #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
20215 | #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
20216 | #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
20217 | #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
20218 | #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
20219 | #define VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
20220 | #define VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
20221 | #define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
20222 | #define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
20223 | #define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
20224 | #define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
20225 | #define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
20226 | #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
20227 | #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
20228 | #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
20229 | #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
20230 | #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
20231 | #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
20232 | #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
20233 | #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
20234 | #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
20235 | #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
20236 | #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
20237 | #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
20238 | #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
20239 | #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
20240 | #define VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
20241 | #define VM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
20242 | //VM_CONTEXT1_CNTL |
20243 | #define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
20244 | #define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
20245 | #define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
20246 | #define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
20247 | #define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
20248 | #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
20249 | #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
20250 | #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
20251 | #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
20252 | #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
20253 | #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
20254 | #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
20255 | #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
20256 | #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
20257 | #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
20258 | #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
20259 | #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
20260 | #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
20261 | #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
20262 | #define VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
20263 | #define VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
20264 | #define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
20265 | #define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
20266 | #define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
20267 | #define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
20268 | #define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
20269 | #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
20270 | #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
20271 | #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
20272 | #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
20273 | #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
20274 | #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
20275 | #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
20276 | #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
20277 | #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
20278 | #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
20279 | #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
20280 | #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
20281 | #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
20282 | #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
20283 | #define VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
20284 | #define VM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
20285 | //VM_CONTEXT2_CNTL |
20286 | #define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
20287 | #define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
20288 | #define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
20289 | #define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
20290 | #define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
20291 | #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
20292 | #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
20293 | #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
20294 | #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
20295 | #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
20296 | #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
20297 | #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
20298 | #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
20299 | #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
20300 | #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
20301 | #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
20302 | #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
20303 | #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
20304 | #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
20305 | #define VM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
20306 | #define VM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
20307 | #define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
20308 | #define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
20309 | #define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
20310 | #define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
20311 | #define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
20312 | #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
20313 | #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
20314 | #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
20315 | #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
20316 | #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
20317 | #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
20318 | #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
20319 | #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
20320 | #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
20321 | #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
20322 | #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
20323 | #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
20324 | #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
20325 | #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
20326 | #define VM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
20327 | #define VM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
20328 | //VM_CONTEXT3_CNTL |
20329 | #define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
20330 | #define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
20331 | #define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
20332 | #define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
20333 | #define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
20334 | #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
20335 | #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
20336 | #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
20337 | #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
20338 | #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
20339 | #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
20340 | #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
20341 | #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
20342 | #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
20343 | #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
20344 | #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
20345 | #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
20346 | #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
20347 | #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
20348 | #define VM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
20349 | #define VM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
20350 | #define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
20351 | #define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
20352 | #define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
20353 | #define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
20354 | #define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
20355 | #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
20356 | #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
20357 | #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
20358 | #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
20359 | #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
20360 | #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
20361 | #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
20362 | #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
20363 | #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
20364 | #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
20365 | #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
20366 | #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
20367 | #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
20368 | #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
20369 | #define VM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
20370 | #define VM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
20371 | //VM_CONTEXT4_CNTL |
20372 | #define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
20373 | #define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
20374 | #define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
20375 | #define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
20376 | #define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
20377 | #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
20378 | #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
20379 | #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
20380 | #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
20381 | #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
20382 | #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
20383 | #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
20384 | #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
20385 | #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
20386 | #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
20387 | #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
20388 | #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
20389 | #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
20390 | #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
20391 | #define VM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
20392 | #define VM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
20393 | #define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
20394 | #define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
20395 | #define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
20396 | #define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
20397 | #define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
20398 | #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
20399 | #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
20400 | #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
20401 | #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
20402 | #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
20403 | #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
20404 | #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
20405 | #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
20406 | #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
20407 | #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
20408 | #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
20409 | #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
20410 | #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
20411 | #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
20412 | #define VM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
20413 | #define VM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
20414 | //VM_CONTEXT5_CNTL |
20415 | #define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
20416 | #define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
20417 | #define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
20418 | #define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
20419 | #define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
20420 | #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
20421 | #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
20422 | #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
20423 | #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
20424 | #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
20425 | #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
20426 | #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
20427 | #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
20428 | #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
20429 | #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
20430 | #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
20431 | #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
20432 | #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
20433 | #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
20434 | #define VM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
20435 | #define VM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
20436 | #define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
20437 | #define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
20438 | #define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
20439 | #define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
20440 | #define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
20441 | #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
20442 | #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
20443 | #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
20444 | #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
20445 | #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
20446 | #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
20447 | #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
20448 | #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
20449 | #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
20450 | #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
20451 | #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
20452 | #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
20453 | #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
20454 | #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
20455 | #define VM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
20456 | #define VM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
20457 | //VM_CONTEXT6_CNTL |
20458 | #define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
20459 | #define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
20460 | #define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
20461 | #define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
20462 | #define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
20463 | #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
20464 | #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
20465 | #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
20466 | #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
20467 | #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
20468 | #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
20469 | #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
20470 | #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
20471 | #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
20472 | #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
20473 | #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
20474 | #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
20475 | #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
20476 | #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
20477 | #define VM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
20478 | #define VM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
20479 | #define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
20480 | #define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
20481 | #define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
20482 | #define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
20483 | #define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
20484 | #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
20485 | #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
20486 | #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
20487 | #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
20488 | #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
20489 | #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
20490 | #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
20491 | #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
20492 | #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
20493 | #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
20494 | #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
20495 | #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
20496 | #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
20497 | #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
20498 | #define VM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
20499 | #define VM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
20500 | //VM_CONTEXT7_CNTL |
20501 | #define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
20502 | #define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
20503 | #define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
20504 | #define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
20505 | #define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
20506 | #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
20507 | #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
20508 | #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
20509 | #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
20510 | #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
20511 | #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
20512 | #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
20513 | #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
20514 | #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
20515 | #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
20516 | #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
20517 | #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
20518 | #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
20519 | #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
20520 | #define VM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
20521 | #define VM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
20522 | #define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
20523 | #define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
20524 | #define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
20525 | #define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
20526 | #define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
20527 | #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
20528 | #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
20529 | #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
20530 | #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
20531 | #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
20532 | #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
20533 | #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
20534 | #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
20535 | #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
20536 | #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
20537 | #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
20538 | #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
20539 | #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
20540 | #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
20541 | #define VM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
20542 | #define VM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
20543 | //VM_CONTEXT8_CNTL |
20544 | #define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
20545 | #define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
20546 | #define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
20547 | #define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
20548 | #define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
20549 | #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
20550 | #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
20551 | #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
20552 | #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
20553 | #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
20554 | #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
20555 | #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
20556 | #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
20557 | #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
20558 | #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
20559 | #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
20560 | #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
20561 | #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
20562 | #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
20563 | #define VM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
20564 | #define VM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
20565 | #define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
20566 | #define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
20567 | #define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
20568 | #define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
20569 | #define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
20570 | #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
20571 | #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
20572 | #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
20573 | #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
20574 | #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
20575 | #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
20576 | #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
20577 | #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
20578 | #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
20579 | #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
20580 | #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
20581 | #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
20582 | #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
20583 | #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
20584 | #define VM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
20585 | #define VM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
20586 | //VM_CONTEXT9_CNTL |
20587 | #define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
20588 | #define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
20589 | #define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
20590 | #define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
20591 | #define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
20592 | #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
20593 | #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
20594 | #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
20595 | #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
20596 | #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
20597 | #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
20598 | #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
20599 | #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
20600 | #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
20601 | #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
20602 | #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
20603 | #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
20604 | #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
20605 | #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
20606 | #define VM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
20607 | #define VM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
20608 | #define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
20609 | #define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
20610 | #define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
20611 | #define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
20612 | #define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
20613 | #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
20614 | #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
20615 | #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
20616 | #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
20617 | #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
20618 | #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
20619 | #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
20620 | #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
20621 | #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
20622 | #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
20623 | #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
20624 | #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
20625 | #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
20626 | #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
20627 | #define VM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
20628 | #define VM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
20629 | //VM_CONTEXT10_CNTL |
20630 | #define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
20631 | #define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
20632 | #define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
20633 | #define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
20634 | #define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
20635 | #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
20636 | #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
20637 | #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
20638 | #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
20639 | #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
20640 | #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
20641 | #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
20642 | #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
20643 | #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
20644 | #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
20645 | #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
20646 | #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
20647 | #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
20648 | #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
20649 | #define VM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
20650 | #define VM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
20651 | #define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
20652 | #define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
20653 | #define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
20654 | #define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
20655 | #define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
20656 | #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
20657 | #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
20658 | #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
20659 | #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
20660 | #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
20661 | #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
20662 | #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
20663 | #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
20664 | #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
20665 | #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
20666 | #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
20667 | #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
20668 | #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
20669 | #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
20670 | #define VM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
20671 | #define VM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
20672 | //VM_CONTEXT11_CNTL |
20673 | #define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
20674 | #define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
20675 | #define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
20676 | #define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
20677 | #define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
20678 | #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
20679 | #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
20680 | #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
20681 | #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
20682 | #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
20683 | #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
20684 | #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
20685 | #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
20686 | #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
20687 | #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
20688 | #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
20689 | #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
20690 | #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
20691 | #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
20692 | #define VM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
20693 | #define VM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
20694 | #define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
20695 | #define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
20696 | #define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
20697 | #define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
20698 | #define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
20699 | #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
20700 | #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
20701 | #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
20702 | #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
20703 | #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
20704 | #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
20705 | #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
20706 | #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
20707 | #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
20708 | #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
20709 | #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
20710 | #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
20711 | #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
20712 | #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
20713 | #define VM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
20714 | #define VM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
20715 | //VM_CONTEXT12_CNTL |
20716 | #define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
20717 | #define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
20718 | #define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
20719 | #define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
20720 | #define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
20721 | #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
20722 | #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
20723 | #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
20724 | #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
20725 | #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
20726 | #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
20727 | #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
20728 | #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
20729 | #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
20730 | #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
20731 | #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
20732 | #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
20733 | #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
20734 | #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
20735 | #define VM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
20736 | #define VM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
20737 | #define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
20738 | #define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
20739 | #define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
20740 | #define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
20741 | #define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
20742 | #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
20743 | #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
20744 | #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
20745 | #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
20746 | #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
20747 | #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
20748 | #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
20749 | #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
20750 | #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
20751 | #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
20752 | #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
20753 | #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
20754 | #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
20755 | #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
20756 | #define VM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
20757 | #define VM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
20758 | //VM_CONTEXT13_CNTL |
20759 | #define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
20760 | #define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
20761 | #define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
20762 | #define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
20763 | #define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
20764 | #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
20765 | #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
20766 | #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
20767 | #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
20768 | #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
20769 | #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
20770 | #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
20771 | #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
20772 | #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
20773 | #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
20774 | #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
20775 | #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
20776 | #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
20777 | #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
20778 | #define VM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
20779 | #define VM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
20780 | #define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
20781 | #define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
20782 | #define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
20783 | #define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
20784 | #define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
20785 | #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
20786 | #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
20787 | #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
20788 | #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
20789 | #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
20790 | #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
20791 | #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
20792 | #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
20793 | #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
20794 | #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
20795 | #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
20796 | #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
20797 | #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
20798 | #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
20799 | #define VM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
20800 | #define VM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
20801 | //VM_CONTEXT14_CNTL |
20802 | #define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
20803 | #define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
20804 | #define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
20805 | #define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
20806 | #define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
20807 | #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
20808 | #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
20809 | #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
20810 | #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
20811 | #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
20812 | #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
20813 | #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
20814 | #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
20815 | #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
20816 | #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
20817 | #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
20818 | #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
20819 | #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
20820 | #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
20821 | #define VM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
20822 | #define VM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
20823 | #define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
20824 | #define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
20825 | #define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
20826 | #define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
20827 | #define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
20828 | #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
20829 | #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
20830 | #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
20831 | #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
20832 | #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
20833 | #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
20834 | #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
20835 | #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
20836 | #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
20837 | #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
20838 | #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
20839 | #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
20840 | #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
20841 | #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
20842 | #define VM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
20843 | #define VM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
20844 | //VM_CONTEXT15_CNTL |
20845 | #define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
20846 | #define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
20847 | #define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
20848 | #define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
20849 | #define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
20850 | #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
20851 | #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
20852 | #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
20853 | #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
20854 | #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
20855 | #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
20856 | #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
20857 | #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
20858 | #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
20859 | #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
20860 | #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
20861 | #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
20862 | #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
20863 | #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
20864 | #define VM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
20865 | #define VM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
20866 | #define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
20867 | #define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
20868 | #define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
20869 | #define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
20870 | #define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
20871 | #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
20872 | #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
20873 | #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
20874 | #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
20875 | #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
20876 | #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
20877 | #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
20878 | #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
20879 | #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
20880 | #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
20881 | #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
20882 | #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
20883 | #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
20884 | #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
20885 | #define VM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
20886 | #define VM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
20887 | //VM_CONTEXTS_DISABLE |
20888 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 |
20889 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 |
20890 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 |
20891 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 |
20892 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 |
20893 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 |
20894 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 |
20895 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 |
20896 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 |
20897 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 |
20898 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa |
20899 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb |
20900 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc |
20901 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd |
20902 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe |
20903 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf |
20904 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L |
20905 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L |
20906 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L |
20907 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L |
20908 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L |
20909 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L |
20910 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L |
20911 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L |
20912 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L |
20913 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L |
20914 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L |
20915 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L |
20916 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L |
20917 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L |
20918 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L |
20919 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L |
20920 | //VM_INVALIDATE_ENG0_SEM |
20921 | #define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 |
20922 | #define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L |
20923 | //VM_INVALIDATE_ENG1_SEM |
20924 | #define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 |
20925 | #define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L |
20926 | //VM_INVALIDATE_ENG2_SEM |
20927 | #define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 |
20928 | #define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L |
20929 | //VM_INVALIDATE_ENG3_SEM |
20930 | #define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 |
20931 | #define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L |
20932 | //VM_INVALIDATE_ENG4_SEM |
20933 | #define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 |
20934 | #define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L |
20935 | //VM_INVALIDATE_ENG5_SEM |
20936 | #define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 |
20937 | #define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L |
20938 | //VM_INVALIDATE_ENG6_SEM |
20939 | #define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 |
20940 | #define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L |
20941 | //VM_INVALIDATE_ENG7_SEM |
20942 | #define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 |
20943 | #define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L |
20944 | //VM_INVALIDATE_ENG8_SEM |
20945 | #define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 |
20946 | #define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L |
20947 | //VM_INVALIDATE_ENG9_SEM |
20948 | #define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 |
20949 | #define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L |
20950 | //VM_INVALIDATE_ENG10_SEM |
20951 | #define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 |
20952 | #define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L |
20953 | //VM_INVALIDATE_ENG11_SEM |
20954 | #define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 |
20955 | #define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L |
20956 | //VM_INVALIDATE_ENG12_SEM |
20957 | #define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 |
20958 | #define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L |
20959 | //VM_INVALIDATE_ENG13_SEM |
20960 | #define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 |
20961 | #define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L |
20962 | //VM_INVALIDATE_ENG14_SEM |
20963 | #define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 |
20964 | #define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L |
20965 | //VM_INVALIDATE_ENG15_SEM |
20966 | #define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 |
20967 | #define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L |
20968 | //VM_INVALIDATE_ENG16_SEM |
20969 | #define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 |
20970 | #define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L |
20971 | //VM_INVALIDATE_ENG17_SEM |
20972 | #define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 |
20973 | #define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L |
20974 | //VM_INVALIDATE_ENG0_REQ |
20975 | #define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
20976 | #define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 |
20977 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
20978 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
20979 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
20980 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
20981 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
20982 | #define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
20983 | #define VM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x18 |
20984 | #define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
20985 | #define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L |
20986 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
20987 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
20988 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
20989 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
20990 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
20991 | #define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
20992 | #define VM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x01000000L |
20993 | //VM_INVALIDATE_ENG1_REQ |
20994 | #define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
20995 | #define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 |
20996 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
20997 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
20998 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
20999 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
21000 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
21001 | #define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
21002 | #define VM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x18 |
21003 | #define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
21004 | #define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L |
21005 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
21006 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
21007 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
21008 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
21009 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
21010 | #define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
21011 | #define VM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x01000000L |
21012 | //VM_INVALIDATE_ENG2_REQ |
21013 | #define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
21014 | #define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 |
21015 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
21016 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
21017 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
21018 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
21019 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
21020 | #define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
21021 | #define VM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x18 |
21022 | #define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
21023 | #define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L |
21024 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
21025 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
21026 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
21027 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
21028 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
21029 | #define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
21030 | #define VM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x01000000L |
21031 | //VM_INVALIDATE_ENG3_REQ |
21032 | #define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
21033 | #define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 |
21034 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
21035 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
21036 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
21037 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
21038 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
21039 | #define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
21040 | #define VM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x18 |
21041 | #define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
21042 | #define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L |
21043 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
21044 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
21045 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
21046 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
21047 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
21048 | #define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
21049 | #define VM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x01000000L |
21050 | //VM_INVALIDATE_ENG4_REQ |
21051 | #define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
21052 | #define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 |
21053 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
21054 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
21055 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
21056 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
21057 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
21058 | #define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
21059 | #define VM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x18 |
21060 | #define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
21061 | #define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L |
21062 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
21063 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
21064 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
21065 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
21066 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
21067 | #define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
21068 | #define VM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x01000000L |
21069 | //VM_INVALIDATE_ENG5_REQ |
21070 | #define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
21071 | #define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 |
21072 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
21073 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
21074 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
21075 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
21076 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
21077 | #define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
21078 | #define VM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x18 |
21079 | #define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
21080 | #define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L |
21081 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
21082 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
21083 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
21084 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
21085 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
21086 | #define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
21087 | #define VM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x01000000L |
21088 | //VM_INVALIDATE_ENG6_REQ |
21089 | #define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
21090 | #define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 |
21091 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
21092 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
21093 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
21094 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
21095 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
21096 | #define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
21097 | #define VM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x18 |
21098 | #define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
21099 | #define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L |
21100 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
21101 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
21102 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
21103 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
21104 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
21105 | #define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
21106 | #define VM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x01000000L |
21107 | //VM_INVALIDATE_ENG7_REQ |
21108 | #define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
21109 | #define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 |
21110 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
21111 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
21112 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
21113 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
21114 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
21115 | #define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
21116 | #define VM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x18 |
21117 | #define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
21118 | #define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L |
21119 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
21120 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
21121 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
21122 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
21123 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
21124 | #define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
21125 | #define VM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x01000000L |
21126 | //VM_INVALIDATE_ENG8_REQ |
21127 | #define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
21128 | #define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 |
21129 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
21130 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
21131 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
21132 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
21133 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
21134 | #define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
21135 | #define VM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x18 |
21136 | #define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
21137 | #define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L |
21138 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
21139 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
21140 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
21141 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
21142 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
21143 | #define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
21144 | #define VM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x01000000L |
21145 | //VM_INVALIDATE_ENG9_REQ |
21146 | #define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
21147 | #define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 |
21148 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
21149 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
21150 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
21151 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
21152 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
21153 | #define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
21154 | #define VM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x18 |
21155 | #define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
21156 | #define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L |
21157 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
21158 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
21159 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
21160 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
21161 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
21162 | #define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
21163 | #define VM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x01000000L |
21164 | //VM_INVALIDATE_ENG10_REQ |
21165 | #define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
21166 | #define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 |
21167 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
21168 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
21169 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
21170 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
21171 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
21172 | #define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
21173 | #define VM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x18 |
21174 | #define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
21175 | #define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L |
21176 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
21177 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
21178 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
21179 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
21180 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
21181 | #define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
21182 | #define VM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x01000000L |
21183 | //VM_INVALIDATE_ENG11_REQ |
21184 | #define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
21185 | #define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 |
21186 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
21187 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
21188 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
21189 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
21190 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
21191 | #define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
21192 | #define VM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x18 |
21193 | #define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
21194 | #define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L |
21195 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
21196 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
21197 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
21198 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
21199 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
21200 | #define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
21201 | #define VM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x01000000L |
21202 | //VM_INVALIDATE_ENG12_REQ |
21203 | #define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
21204 | #define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 |
21205 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
21206 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
21207 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
21208 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
21209 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
21210 | #define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
21211 | #define VM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x18 |
21212 | #define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
21213 | #define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L |
21214 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
21215 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
21216 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
21217 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
21218 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
21219 | #define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
21220 | #define VM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x01000000L |
21221 | //VM_INVALIDATE_ENG13_REQ |
21222 | #define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
21223 | #define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 |
21224 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
21225 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
21226 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
21227 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
21228 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
21229 | #define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
21230 | #define VM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x18 |
21231 | #define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
21232 | #define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L |
21233 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
21234 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
21235 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
21236 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
21237 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
21238 | #define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
21239 | #define VM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x01000000L |
21240 | //VM_INVALIDATE_ENG14_REQ |
21241 | #define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
21242 | #define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 |
21243 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
21244 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
21245 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
21246 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
21247 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
21248 | #define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
21249 | #define VM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x18 |
21250 | #define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
21251 | #define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L |
21252 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
21253 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
21254 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
21255 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
21256 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
21257 | #define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
21258 | #define VM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x01000000L |
21259 | //VM_INVALIDATE_ENG15_REQ |
21260 | #define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
21261 | #define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 |
21262 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
21263 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
21264 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
21265 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
21266 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
21267 | #define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
21268 | #define VM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x18 |
21269 | #define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
21270 | #define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L |
21271 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
21272 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
21273 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
21274 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
21275 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
21276 | #define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
21277 | #define VM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x01000000L |
21278 | //VM_INVALIDATE_ENG16_REQ |
21279 | #define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
21280 | #define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 |
21281 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
21282 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
21283 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
21284 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
21285 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
21286 | #define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
21287 | #define VM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x18 |
21288 | #define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
21289 | #define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L |
21290 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
21291 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
21292 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
21293 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
21294 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
21295 | #define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
21296 | #define VM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x01000000L |
21297 | //VM_INVALIDATE_ENG17_REQ |
21298 | #define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
21299 | #define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 |
21300 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
21301 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
21302 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
21303 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
21304 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
21305 | #define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
21306 | #define VM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x18 |
21307 | #define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
21308 | #define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L |
21309 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
21310 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
21311 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
21312 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
21313 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
21314 | #define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
21315 | #define VM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x01000000L |
21316 | //VM_INVALIDATE_ENG0_ACK |
21317 | #define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
21318 | #define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 |
21319 | #define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
21320 | #define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L |
21321 | //VM_INVALIDATE_ENG1_ACK |
21322 | #define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
21323 | #define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 |
21324 | #define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
21325 | #define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L |
21326 | //VM_INVALIDATE_ENG2_ACK |
21327 | #define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
21328 | #define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 |
21329 | #define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
21330 | #define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L |
21331 | //VM_INVALIDATE_ENG3_ACK |
21332 | #define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
21333 | #define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 |
21334 | #define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
21335 | #define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L |
21336 | //VM_INVALIDATE_ENG4_ACK |
21337 | #define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
21338 | #define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 |
21339 | #define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
21340 | #define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L |
21341 | //VM_INVALIDATE_ENG5_ACK |
21342 | #define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
21343 | #define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 |
21344 | #define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
21345 | #define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L |
21346 | //VM_INVALIDATE_ENG6_ACK |
21347 | #define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
21348 | #define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 |
21349 | #define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
21350 | #define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L |
21351 | //VM_INVALIDATE_ENG7_ACK |
21352 | #define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
21353 | #define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 |
21354 | #define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
21355 | #define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L |
21356 | //VM_INVALIDATE_ENG8_ACK |
21357 | #define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
21358 | #define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 |
21359 | #define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
21360 | #define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L |
21361 | //VM_INVALIDATE_ENG9_ACK |
21362 | #define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
21363 | #define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 |
21364 | #define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
21365 | #define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L |
21366 | //VM_INVALIDATE_ENG10_ACK |
21367 | #define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
21368 | #define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 |
21369 | #define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
21370 | #define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L |
21371 | //VM_INVALIDATE_ENG11_ACK |
21372 | #define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
21373 | #define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 |
21374 | #define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
21375 | #define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L |
21376 | //VM_INVALIDATE_ENG12_ACK |
21377 | #define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
21378 | #define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 |
21379 | #define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
21380 | #define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L |
21381 | //VM_INVALIDATE_ENG13_ACK |
21382 | #define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
21383 | #define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 |
21384 | #define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
21385 | #define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L |
21386 | //VM_INVALIDATE_ENG14_ACK |
21387 | #define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
21388 | #define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 |
21389 | #define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
21390 | #define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L |
21391 | //VM_INVALIDATE_ENG15_ACK |
21392 | #define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
21393 | #define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 |
21394 | #define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
21395 | #define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L |
21396 | //VM_INVALIDATE_ENG16_ACK |
21397 | #define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
21398 | #define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 |
21399 | #define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
21400 | #define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L |
21401 | //VM_INVALIDATE_ENG17_ACK |
21402 | #define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
21403 | #define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 |
21404 | #define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
21405 | #define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L |
21406 | //VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 |
21407 | #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
21408 | #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
21409 | #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
21410 | #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
21411 | //VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 |
21412 | #define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
21413 | #define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
21414 | //VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 |
21415 | #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
21416 | #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
21417 | #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
21418 | #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
21419 | //VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 |
21420 | #define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
21421 | #define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
21422 | //VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 |
21423 | #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
21424 | #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
21425 | #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
21426 | #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
21427 | //VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 |
21428 | #define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
21429 | #define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
21430 | //VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 |
21431 | #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
21432 | #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
21433 | #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
21434 | #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
21435 | //VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 |
21436 | #define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
21437 | #define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
21438 | //VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 |
21439 | #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
21440 | #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
21441 | #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
21442 | #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
21443 | //VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 |
21444 | #define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
21445 | #define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
21446 | //VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 |
21447 | #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
21448 | #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
21449 | #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
21450 | #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
21451 | //VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 |
21452 | #define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
21453 | #define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
21454 | //VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 |
21455 | #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
21456 | #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
21457 | #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
21458 | #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
21459 | //VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 |
21460 | #define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
21461 | #define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
21462 | //VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 |
21463 | #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
21464 | #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
21465 | #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
21466 | #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
21467 | //VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 |
21468 | #define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
21469 | #define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
21470 | //VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 |
21471 | #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
21472 | #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
21473 | #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
21474 | #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
21475 | //VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 |
21476 | #define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
21477 | #define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
21478 | //VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 |
21479 | #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
21480 | #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
21481 | #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
21482 | #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
21483 | //VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 |
21484 | #define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
21485 | #define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
21486 | //VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 |
21487 | #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
21488 | #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
21489 | #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
21490 | #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
21491 | //VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 |
21492 | #define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
21493 | #define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
21494 | //VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 |
21495 | #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
21496 | #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
21497 | #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
21498 | #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
21499 | //VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 |
21500 | #define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
21501 | #define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
21502 | //VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 |
21503 | #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
21504 | #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
21505 | #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
21506 | #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
21507 | //VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 |
21508 | #define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
21509 | #define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
21510 | //VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 |
21511 | #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
21512 | #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
21513 | #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
21514 | #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
21515 | //VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 |
21516 | #define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
21517 | #define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
21518 | //VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 |
21519 | #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
21520 | #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
21521 | #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
21522 | #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
21523 | //VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 |
21524 | #define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
21525 | #define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
21526 | //VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 |
21527 | #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
21528 | #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
21529 | #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
21530 | #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
21531 | //VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 |
21532 | #define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
21533 | #define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
21534 | //VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 |
21535 | #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
21536 | #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
21537 | #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
21538 | #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
21539 | //VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 |
21540 | #define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
21541 | #define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
21542 | //VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 |
21543 | #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
21544 | #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
21545 | #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
21546 | #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
21547 | //VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 |
21548 | #define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
21549 | #define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
21550 | //VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 |
21551 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
21552 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
21553 | //VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 |
21554 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
21555 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
21556 | //VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 |
21557 | #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
21558 | #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
21559 | //VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 |
21560 | #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
21561 | #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
21562 | //VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 |
21563 | #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
21564 | #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
21565 | //VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 |
21566 | #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
21567 | #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
21568 | //VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 |
21569 | #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
21570 | #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
21571 | //VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 |
21572 | #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
21573 | #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
21574 | //VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 |
21575 | #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
21576 | #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
21577 | //VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 |
21578 | #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
21579 | #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
21580 | //VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 |
21581 | #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
21582 | #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
21583 | //VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 |
21584 | #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
21585 | #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
21586 | //VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 |
21587 | #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
21588 | #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
21589 | //VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 |
21590 | #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
21591 | #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
21592 | //VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 |
21593 | #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
21594 | #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
21595 | //VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 |
21596 | #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
21597 | #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
21598 | //VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 |
21599 | #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
21600 | #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
21601 | //VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 |
21602 | #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
21603 | #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
21604 | //VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 |
21605 | #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
21606 | #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
21607 | //VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 |
21608 | #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
21609 | #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
21610 | //VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 |
21611 | #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
21612 | #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
21613 | //VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 |
21614 | #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
21615 | #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
21616 | //VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 |
21617 | #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
21618 | #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
21619 | //VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 |
21620 | #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
21621 | #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
21622 | //VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 |
21623 | #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
21624 | #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
21625 | //VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 |
21626 | #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
21627 | #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
21628 | //VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 |
21629 | #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
21630 | #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
21631 | //VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 |
21632 | #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
21633 | #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
21634 | //VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 |
21635 | #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
21636 | #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
21637 | //VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 |
21638 | #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
21639 | #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
21640 | //VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 |
21641 | #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
21642 | #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
21643 | //VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 |
21644 | #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
21645 | #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
21646 | //VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 |
21647 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21648 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21649 | //VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 |
21650 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21651 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21652 | //VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 |
21653 | #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21654 | #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21655 | //VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 |
21656 | #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21657 | #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21658 | //VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 |
21659 | #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21660 | #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21661 | //VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 |
21662 | #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21663 | #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21664 | //VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 |
21665 | #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21666 | #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21667 | //VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 |
21668 | #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21669 | #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21670 | //VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 |
21671 | #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21672 | #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21673 | //VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 |
21674 | #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21675 | #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21676 | //VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 |
21677 | #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21678 | #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21679 | //VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 |
21680 | #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21681 | #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21682 | //VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 |
21683 | #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21684 | #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21685 | //VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 |
21686 | #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21687 | #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21688 | //VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 |
21689 | #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21690 | #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21691 | //VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 |
21692 | #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21693 | #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21694 | //VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 |
21695 | #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21696 | #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21697 | //VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 |
21698 | #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21699 | #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21700 | //VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 |
21701 | #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21702 | #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21703 | //VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 |
21704 | #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21705 | #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21706 | //VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 |
21707 | #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21708 | #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21709 | //VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 |
21710 | #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21711 | #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21712 | //VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 |
21713 | #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21714 | #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21715 | //VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 |
21716 | #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21717 | #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21718 | //VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 |
21719 | #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21720 | #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21721 | //VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 |
21722 | #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21723 | #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21724 | //VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 |
21725 | #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21726 | #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21727 | //VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 |
21728 | #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21729 | #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21730 | //VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 |
21731 | #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21732 | #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21733 | //VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 |
21734 | #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21735 | #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21736 | //VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 |
21737 | #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21738 | #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21739 | //VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 |
21740 | #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21741 | #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21742 | //VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 |
21743 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21744 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21745 | //VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 |
21746 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21747 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21748 | //VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 |
21749 | #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21750 | #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21751 | //VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 |
21752 | #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21753 | #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21754 | //VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 |
21755 | #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21756 | #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21757 | //VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 |
21758 | #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21759 | #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21760 | //VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 |
21761 | #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21762 | #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21763 | //VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 |
21764 | #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21765 | #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21766 | //VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 |
21767 | #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21768 | #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21769 | //VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 |
21770 | #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21771 | #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21772 | //VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 |
21773 | #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21774 | #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21775 | //VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 |
21776 | #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21777 | #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21778 | //VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 |
21779 | #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21780 | #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21781 | //VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 |
21782 | #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21783 | #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21784 | //VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 |
21785 | #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21786 | #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21787 | //VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 |
21788 | #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21789 | #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21790 | //VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 |
21791 | #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21792 | #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21793 | //VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 |
21794 | #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21795 | #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21796 | //VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 |
21797 | #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21798 | #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21799 | //VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 |
21800 | #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21801 | #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21802 | //VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 |
21803 | #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21804 | #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21805 | //VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 |
21806 | #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21807 | #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21808 | //VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 |
21809 | #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21810 | #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21811 | //VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 |
21812 | #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21813 | #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21814 | //VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 |
21815 | #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21816 | #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21817 | //VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 |
21818 | #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21819 | #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21820 | //VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 |
21821 | #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21822 | #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21823 | //VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 |
21824 | #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21825 | #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21826 | //VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 |
21827 | #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21828 | #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21829 | //VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 |
21830 | #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21831 | #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21832 | //VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 |
21833 | #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
21834 | #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
21835 | //VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 |
21836 | #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
21837 | #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
21838 | |
21839 | |
21840 | // addressBlock: aid_mmhub_utcl2_vmsharedpfdec |
21841 | //MC_VM_NB_MMIOBASE |
21842 | #define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 |
21843 | #define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL |
21844 | //MC_VM_NB_MMIOLIMIT |
21845 | #define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 |
21846 | #define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL |
21847 | //MC_VM_NB_PCI_CTRL |
21848 | #define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 |
21849 | #define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L |
21850 | //MC_VM_NB_PCI_ARB |
21851 | #define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 |
21852 | #define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L |
21853 | //MC_VM_NB_TOP_OF_DRAM_SLOT1 |
21854 | #define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 |
21855 | #define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L |
21856 | //MC_VM_NB_LOWER_TOP_OF_DRAM2 |
21857 | #define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 |
21858 | #define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 |
21859 | #define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L |
21860 | #define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L |
21861 | //MC_VM_NB_UPPER_TOP_OF_DRAM2 |
21862 | #define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 |
21863 | #define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x0000FFFFL |
21864 | //MC_VM_FB_OFFSET |
21865 | #define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 |
21866 | #define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL |
21867 | //MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB |
21868 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 |
21869 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL |
21870 | //MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB |
21871 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 |
21872 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL |
21873 | //MC_VM_STEERING |
21874 | #define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 |
21875 | #define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L |
21876 | //MC_SHARED_VIRT_RESET_REQ |
21877 | #define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 |
21878 | #define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f |
21879 | #define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL |
21880 | #define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L |
21881 | //MC_MEM_POWER_LS |
21882 | #define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 |
21883 | #define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 |
21884 | #define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL |
21885 | #define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L |
21886 | //MC_VM_CACHEABLE_DRAM_ADDRESS_START |
21887 | #define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 |
21888 | #define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x00FFFFFFL |
21889 | //MC_VM_CACHEABLE_DRAM_ADDRESS_END |
21890 | #define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 |
21891 | #define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x00FFFFFFL |
21892 | //MC_VM_APT_CNTL |
21893 | #define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 |
21894 | #define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 |
21895 | #define MC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT 0x2 |
21896 | #define MC_VM_APT_CNTL__PERMS_GRANTED__SHIFT 0x3 |
21897 | #define MC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT 0x4 |
21898 | #define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L |
21899 | #define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L |
21900 | #define MC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK 0x00000004L |
21901 | #define MC_VM_APT_CNTL__PERMS_GRANTED_MASK 0x00000008L |
21902 | #define MC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK 0x00000030L |
21903 | //MC_VM_LOCAL_HBM_ADDRESS_START |
21904 | #define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 |
21905 | #define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x00FFFFFFL |
21906 | //MC_VM_LOCAL_HBM_ADDRESS_END |
21907 | #define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 |
21908 | #define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x00FFFFFFL |
21909 | //MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL |
21910 | #define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 |
21911 | #define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L |
21912 | //UTCL2_CGTT_CLK_CTRL |
21913 | #define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
21914 | #define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
21915 | #define 0xc |
21916 | #define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
21917 | #define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 |
21918 | #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 |
21919 | #define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
21920 | #define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
21921 | #define 0x00007000L |
21922 | #define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
21923 | #define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L |
21924 | #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L |
21925 | //MC_VM_XGMI_LFB_CNTL |
21926 | #define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0 |
21927 | #define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x4 |
21928 | #define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x0000000FL |
21929 | #define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x000000F0L |
21930 | //MC_VM_XGMI_LFB_SIZE |
21931 | #define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0 |
21932 | #define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0001FFFFL |
21933 | //MC_VM_CACHEABLE_DRAM_CNTL |
21934 | #define MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE__SHIFT 0x0 |
21935 | #define MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE_MASK 0x00000001L |
21936 | //MC_VM_HOST_MAPPING |
21937 | #define MC_VM_HOST_MAPPING__MODE__SHIFT 0x0 |
21938 | #define MC_VM_HOST_MAPPING__MODE_MASK 0x00000001L |
21939 | |
21940 | |
21941 | // addressBlock: aid_mmhub_utcl2_vmsharedvcdec |
21942 | //MC_VM_FB_LOCATION_BASE |
21943 | #define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 |
21944 | #define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL |
21945 | //MC_VM_FB_LOCATION_TOP |
21946 | #define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 |
21947 | #define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL |
21948 | //MC_VM_AGP_TOP |
21949 | #define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 |
21950 | #define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL |
21951 | //MC_VM_AGP_BOT |
21952 | #define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 |
21953 | #define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL |
21954 | //MC_VM_AGP_BASE |
21955 | #define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 |
21956 | #define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL |
21957 | //MC_VM_SYSTEM_APERTURE_LOW_ADDR |
21958 | #define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 |
21959 | #define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL |
21960 | //MC_VM_SYSTEM_APERTURE_HIGH_ADDR |
21961 | #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 |
21962 | #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL |
21963 | //MC_VM_MX_L1_TLB_CNTL |
21964 | #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 |
21965 | #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 |
21966 | #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 |
21967 | #define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 |
21968 | #define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 |
21969 | #define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb |
21970 | #define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd |
21971 | #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L |
21972 | #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L |
21973 | #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L |
21974 | #define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L |
21975 | #define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L |
21976 | #define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L |
21977 | #define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L |
21978 | |
21979 | |
21980 | // addressBlock: aid_mmhub_utcl2_vmsharedhvdec |
21981 | //MC_VM_FB_SIZE_OFFSET_VF0 |
21982 | #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 |
21983 | #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 |
21984 | #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL |
21985 | #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L |
21986 | //MC_VM_FB_SIZE_OFFSET_VF1 |
21987 | #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 |
21988 | #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 |
21989 | #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL |
21990 | #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L |
21991 | //MC_VM_FB_SIZE_OFFSET_VF2 |
21992 | #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 |
21993 | #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 |
21994 | #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL |
21995 | #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L |
21996 | //MC_VM_FB_SIZE_OFFSET_VF3 |
21997 | #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 |
21998 | #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 |
21999 | #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL |
22000 | #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L |
22001 | //MC_VM_FB_SIZE_OFFSET_VF4 |
22002 | #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 |
22003 | #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 |
22004 | #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL |
22005 | #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L |
22006 | //MC_VM_FB_SIZE_OFFSET_VF5 |
22007 | #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 |
22008 | #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 |
22009 | #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL |
22010 | #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L |
22011 | //MC_VM_FB_SIZE_OFFSET_VF6 |
22012 | #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 |
22013 | #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 |
22014 | #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL |
22015 | #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L |
22016 | //MC_VM_FB_SIZE_OFFSET_VF7 |
22017 | #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 |
22018 | #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 |
22019 | #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL |
22020 | #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L |
22021 | //MC_VM_FB_SIZE_OFFSET_VF8 |
22022 | #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 |
22023 | #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 |
22024 | #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL |
22025 | #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L |
22026 | //MC_VM_FB_SIZE_OFFSET_VF9 |
22027 | #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 |
22028 | #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 |
22029 | #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL |
22030 | #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L |
22031 | //MC_VM_FB_SIZE_OFFSET_VF10 |
22032 | #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 |
22033 | #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 |
22034 | #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL |
22035 | #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L |
22036 | //MC_VM_FB_SIZE_OFFSET_VF11 |
22037 | #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 |
22038 | #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 |
22039 | #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL |
22040 | #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L |
22041 | //MC_VM_FB_SIZE_OFFSET_VF12 |
22042 | #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 |
22043 | #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 |
22044 | #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL |
22045 | #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L |
22046 | //MC_VM_FB_SIZE_OFFSET_VF13 |
22047 | #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 |
22048 | #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 |
22049 | #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL |
22050 | #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L |
22051 | //MC_VM_FB_SIZE_OFFSET_VF14 |
22052 | #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 |
22053 | #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 |
22054 | #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL |
22055 | #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L |
22056 | //MC_VM_FB_SIZE_OFFSET_VF15 |
22057 | #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 |
22058 | #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 |
22059 | #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL |
22060 | #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L |
22061 | //VM_IOMMU_MMIO_CNTRL_1 |
22062 | #define VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8 |
22063 | #define VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L |
22064 | //MC_VM_MARC_BASE_LO_0 |
22065 | #define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc |
22066 | #define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L |
22067 | //MC_VM_MARC_BASE_LO_1 |
22068 | #define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc |
22069 | #define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L |
22070 | //MC_VM_MARC_BASE_LO_2 |
22071 | #define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc |
22072 | #define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L |
22073 | //MC_VM_MARC_BASE_LO_3 |
22074 | #define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc |
22075 | #define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L |
22076 | //MC_VM_MARC_BASE_HI_0 |
22077 | #define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 |
22078 | #define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL |
22079 | //MC_VM_MARC_BASE_HI_1 |
22080 | #define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 |
22081 | #define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL |
22082 | //MC_VM_MARC_BASE_HI_2 |
22083 | #define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 |
22084 | #define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL |
22085 | //MC_VM_MARC_BASE_HI_3 |
22086 | #define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 |
22087 | #define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL |
22088 | //MC_VM_MARC_RELOC_LO_0 |
22089 | #define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 |
22090 | #define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 |
22091 | #define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc |
22092 | #define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L |
22093 | #define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L |
22094 | #define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L |
22095 | //MC_VM_MARC_RELOC_LO_1 |
22096 | #define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 |
22097 | #define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 |
22098 | #define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc |
22099 | #define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L |
22100 | #define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L |
22101 | #define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L |
22102 | //MC_VM_MARC_RELOC_LO_2 |
22103 | #define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 |
22104 | #define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 |
22105 | #define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc |
22106 | #define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L |
22107 | #define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L |
22108 | #define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L |
22109 | //MC_VM_MARC_RELOC_LO_3 |
22110 | #define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 |
22111 | #define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 |
22112 | #define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc |
22113 | #define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L |
22114 | #define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L |
22115 | #define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L |
22116 | //MC_VM_MARC_RELOC_HI_0 |
22117 | #define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 |
22118 | #define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL |
22119 | //MC_VM_MARC_RELOC_HI_1 |
22120 | #define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 |
22121 | #define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL |
22122 | //MC_VM_MARC_RELOC_HI_2 |
22123 | #define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 |
22124 | #define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL |
22125 | //MC_VM_MARC_RELOC_HI_3 |
22126 | #define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 |
22127 | #define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL |
22128 | //MC_VM_MARC_LEN_LO_0 |
22129 | #define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc |
22130 | #define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L |
22131 | //MC_VM_MARC_LEN_LO_1 |
22132 | #define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc |
22133 | #define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L |
22134 | //MC_VM_MARC_LEN_LO_2 |
22135 | #define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc |
22136 | #define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L |
22137 | //MC_VM_MARC_LEN_LO_3 |
22138 | #define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc |
22139 | #define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L |
22140 | //MC_VM_MARC_LEN_HI_0 |
22141 | #define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 |
22142 | #define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL |
22143 | //MC_VM_MARC_LEN_HI_1 |
22144 | #define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 |
22145 | #define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL |
22146 | //MC_VM_MARC_LEN_HI_2 |
22147 | #define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 |
22148 | #define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL |
22149 | //MC_VM_MARC_LEN_HI_3 |
22150 | #define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 |
22151 | #define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL |
22152 | //VM_IOMMU_CONTROL_REGISTER |
22153 | #define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 |
22154 | #define VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L |
22155 | //VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER |
22156 | #define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd |
22157 | #define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L |
22158 | //VM_PCIE_ATS_CNTL |
22159 | #define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10 |
22160 | #define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f |
22161 | #define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L |
22162 | #define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L |
22163 | //VM_PCIE_ATS_CNTL_VF_0 |
22164 | #define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f |
22165 | #define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L |
22166 | //VM_PCIE_ATS_CNTL_VF_1 |
22167 | #define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f |
22168 | #define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L |
22169 | //VM_PCIE_ATS_CNTL_VF_2 |
22170 | #define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f |
22171 | #define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L |
22172 | //VM_PCIE_ATS_CNTL_VF_3 |
22173 | #define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f |
22174 | #define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L |
22175 | //VM_PCIE_ATS_CNTL_VF_4 |
22176 | #define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f |
22177 | #define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L |
22178 | //VM_PCIE_ATS_CNTL_VF_5 |
22179 | #define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f |
22180 | #define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L |
22181 | //VM_PCIE_ATS_CNTL_VF_6 |
22182 | #define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f |
22183 | #define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L |
22184 | //VM_PCIE_ATS_CNTL_VF_7 |
22185 | #define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f |
22186 | #define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L |
22187 | //VM_PCIE_ATS_CNTL_VF_8 |
22188 | #define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f |
22189 | #define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L |
22190 | //VM_PCIE_ATS_CNTL_VF_9 |
22191 | #define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f |
22192 | #define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L |
22193 | //VM_PCIE_ATS_CNTL_VF_10 |
22194 | #define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f |
22195 | #define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L |
22196 | //VM_PCIE_ATS_CNTL_VF_11 |
22197 | #define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f |
22198 | #define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L |
22199 | //VM_PCIE_ATS_CNTL_VF_12 |
22200 | #define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f |
22201 | #define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L |
22202 | //VM_PCIE_ATS_CNTL_VF_13 |
22203 | #define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f |
22204 | #define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L |
22205 | //VM_PCIE_ATS_CNTL_VF_14 |
22206 | #define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f |
22207 | #define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L |
22208 | //VM_PCIE_ATS_CNTL_VF_15 |
22209 | #define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f |
22210 | #define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L |
22211 | //MC_SHARED_ACTIVE_FCN_ID |
22212 | #define MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 |
22213 | #define MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f |
22214 | #define MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL |
22215 | #define MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L |
22216 | //MC_VM_XGMI_GPUIOV_ENABLE |
22217 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT 0x0 |
22218 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT 0x1 |
22219 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT 0x2 |
22220 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT 0x3 |
22221 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT 0x4 |
22222 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT 0x5 |
22223 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT 0x6 |
22224 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT 0x7 |
22225 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT 0x8 |
22226 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT 0x9 |
22227 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT 0xa |
22228 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT 0xb |
22229 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT 0xc |
22230 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT 0xd |
22231 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT 0xe |
22232 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT 0xf |
22233 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT 0x1f |
22234 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK 0x00000001L |
22235 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK 0x00000002L |
22236 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK 0x00000004L |
22237 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK 0x00000008L |
22238 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK 0x00000010L |
22239 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK 0x00000020L |
22240 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK 0x00000040L |
22241 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK 0x00000080L |
22242 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK 0x00000100L |
22243 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK 0x00000200L |
22244 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK 0x00000400L |
22245 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK 0x00000800L |
22246 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK 0x00001000L |
22247 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK 0x00002000L |
22248 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK 0x00004000L |
22249 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK 0x00008000L |
22250 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK 0x80000000L |
22251 | |
22252 | |
22253 | // addressBlock: aid_mmhub_utcl2_atcl2pfcntrdec |
22254 | //ATC_L2_PERFCOUNTER_LO |
22255 | #define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
22256 | #define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
22257 | //ATC_L2_PERFCOUNTER_HI |
22258 | #define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
22259 | #define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
22260 | #define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
22261 | #define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
22262 | |
22263 | |
22264 | // addressBlock: aid_mmhub_utcl2_atcl2pfcntldec |
22265 | //ATC_L2_PERFCOUNTER0_CFG |
22266 | #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
22267 | #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
22268 | #define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
22269 | #define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
22270 | #define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
22271 | #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
22272 | #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
22273 | #define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
22274 | #define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
22275 | #define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
22276 | //ATC_L2_PERFCOUNTER1_CFG |
22277 | #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
22278 | #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
22279 | #define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
22280 | #define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
22281 | #define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
22282 | #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
22283 | #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
22284 | #define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
22285 | #define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
22286 | #define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
22287 | //ATC_L2_PERFCOUNTER_RSLT_CNTL |
22288 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
22289 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
22290 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
22291 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
22292 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
22293 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
22294 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
22295 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
22296 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
22297 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
22298 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
22299 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
22300 | |
22301 | |
22302 | // addressBlock: aid_mmhub_utcl2_vml2pldec |
22303 | //MC_VM_L2_PERFCOUNTER0_CFG |
22304 | #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
22305 | #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
22306 | #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
22307 | #define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
22308 | #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
22309 | #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
22310 | #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
22311 | #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
22312 | #define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
22313 | #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
22314 | //MC_VM_L2_PERFCOUNTER1_CFG |
22315 | #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
22316 | #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
22317 | #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
22318 | #define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
22319 | #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
22320 | #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
22321 | #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
22322 | #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
22323 | #define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
22324 | #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
22325 | //MC_VM_L2_PERFCOUNTER2_CFG |
22326 | #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 |
22327 | #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 |
22328 | #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 |
22329 | #define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c |
22330 | #define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d |
22331 | #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL |
22332 | #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L |
22333 | #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L |
22334 | #define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L |
22335 | #define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L |
22336 | //MC_VM_L2_PERFCOUNTER3_CFG |
22337 | #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 |
22338 | #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 |
22339 | #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 |
22340 | #define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c |
22341 | #define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d |
22342 | #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL |
22343 | #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L |
22344 | #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L |
22345 | #define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L |
22346 | #define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L |
22347 | //MC_VM_L2_PERFCOUNTER4_CFG |
22348 | #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 |
22349 | #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 |
22350 | #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 |
22351 | #define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c |
22352 | #define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d |
22353 | #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL |
22354 | #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L |
22355 | #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L |
22356 | #define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L |
22357 | #define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L |
22358 | //MC_VM_L2_PERFCOUNTER5_CFG |
22359 | #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 |
22360 | #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 |
22361 | #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 |
22362 | #define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c |
22363 | #define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d |
22364 | #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL |
22365 | #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L |
22366 | #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L |
22367 | #define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L |
22368 | #define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L |
22369 | //MC_VM_L2_PERFCOUNTER6_CFG |
22370 | #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 |
22371 | #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 |
22372 | #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 |
22373 | #define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c |
22374 | #define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d |
22375 | #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL |
22376 | #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L |
22377 | #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L |
22378 | #define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L |
22379 | #define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L |
22380 | //MC_VM_L2_PERFCOUNTER7_CFG |
22381 | #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 |
22382 | #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 |
22383 | #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 |
22384 | #define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c |
22385 | #define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d |
22386 | #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL |
22387 | #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L |
22388 | #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L |
22389 | #define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L |
22390 | #define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L |
22391 | //MC_VM_L2_PERFCOUNTER_RSLT_CNTL |
22392 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
22393 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
22394 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
22395 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
22396 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
22397 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
22398 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
22399 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
22400 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
22401 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
22402 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
22403 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
22404 | |
22405 | |
22406 | // addressBlock: aid_mmhub_utcl2_vml2prdec |
22407 | //MC_VM_L2_PERFCOUNTER_LO |
22408 | #define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
22409 | #define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
22410 | //MC_VM_L2_PERFCOUNTER_HI |
22411 | #define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
22412 | #define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
22413 | #define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
22414 | #define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
22415 | |
22416 | |
22417 | // addressBlock: aid_mmhub_utcl2_l2tlbdec |
22418 | //L2TLB_TLB0_STATUS |
22419 | #define L2TLB_TLB0_STATUS__BUSY__SHIFT 0x0 |
22420 | #define L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 |
22421 | #define L2TLB_TLB0_STATUS__BUSY_MASK 0x00000001L |
22422 | #define L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L |
22423 | //UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO |
22424 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT 0x0 |
22425 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK 0xFFFFFFFFL |
22426 | //UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI |
22427 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT 0x0 |
22428 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT 0x4 |
22429 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT 0x9 |
22430 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT 0xd |
22431 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT 0xe |
22432 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT 0x10 |
22433 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT 0x11 |
22434 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT 0x12 |
22435 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT 0x13 |
22436 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT 0x1f |
22437 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK 0x0000000FL |
22438 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK 0x000000F0L |
22439 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK 0x00001E00L |
22440 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK 0x00002000L |
22441 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK 0x0000C000L |
22442 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK 0x00010000L |
22443 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK 0x00020000L |
22444 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK 0x00040000L |
22445 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK 0x0FF80000L |
22446 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK 0x80000000L |
22447 | //UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO |
22448 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT 0x0 |
22449 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK 0xFFFFFFFFL |
22450 | //UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI |
22451 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT 0x0 |
22452 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT 0x4 |
22453 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT 0x7 |
22454 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT 0xd |
22455 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT 0xe |
22456 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT 0xf |
22457 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT 0x10 |
22458 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT 0x11 |
22459 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT 0x12 |
22460 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT 0x14 |
22461 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC__SHIFT 0x15 |
22462 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT 0x16 |
22463 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT 0x1f |
22464 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK 0x0000000FL |
22465 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK 0x00000070L |
22466 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK 0x00001F80L |
22467 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK 0x00002000L |
22468 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK 0x00004000L |
22469 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK 0x00008000L |
22470 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK 0x00010000L |
22471 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK 0x00020000L |
22472 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK 0x000C0000L |
22473 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK 0x00100000L |
22474 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC_MASK 0x00200000L |
22475 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK 0x00C00000L |
22476 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK 0x80000000L |
22477 | |
22478 | |
22479 | // addressBlock: aid_mmhub_utcl2_l2tlbpldec |
22480 | //L2TLB_PERFCOUNTER0_CFG |
22481 | #define L2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
22482 | #define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
22483 | #define L2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
22484 | #define L2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
22485 | #define L2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
22486 | #define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
22487 | #define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
22488 | #define L2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
22489 | #define L2TLB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
22490 | #define L2TLB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
22491 | //L2TLB_PERFCOUNTER1_CFG |
22492 | #define L2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
22493 | #define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
22494 | #define L2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
22495 | #define L2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
22496 | #define L2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
22497 | #define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
22498 | #define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
22499 | #define L2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
22500 | #define L2TLB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
22501 | #define L2TLB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
22502 | //L2TLB_PERFCOUNTER2_CFG |
22503 | #define L2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 |
22504 | #define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 |
22505 | #define L2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 |
22506 | #define L2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c |
22507 | #define L2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d |
22508 | #define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL |
22509 | #define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L |
22510 | #define L2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L |
22511 | #define L2TLB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L |
22512 | #define L2TLB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L |
22513 | //L2TLB_PERFCOUNTER3_CFG |
22514 | #define L2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 |
22515 | #define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 |
22516 | #define L2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 |
22517 | #define L2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c |
22518 | #define L2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d |
22519 | #define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL |
22520 | #define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L |
22521 | #define L2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L |
22522 | #define L2TLB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L |
22523 | #define L2TLB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L |
22524 | //L2TLB_PERFCOUNTER_RSLT_CNTL |
22525 | #define L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
22526 | #define L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
22527 | #define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
22528 | #define L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
22529 | #define L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
22530 | #define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
22531 | #define L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
22532 | #define L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
22533 | #define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
22534 | #define L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
22535 | #define L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
22536 | #define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
22537 | |
22538 | |
22539 | // addressBlock: aid_mmhub_utcl2_l2tlbprdec |
22540 | //L2TLB_PERFCOUNTER_LO |
22541 | #define L2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
22542 | #define L2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
22543 | //L2TLB_PERFCOUNTER_HI |
22544 | #define L2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
22545 | #define L2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
22546 | #define L2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
22547 | #define L2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
22548 | |
22549 | // addressBlock: aid_mmhub_mm_cane_mmcanedec |
22550 | //MM_CANE_ICG_CTRL |
22551 | #define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_IREQ0__SHIFT 0x0 |
22552 | #define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_ATRET__SHIFT 0x1 |
22553 | #define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_OREQ__SHIFT 0x2 |
22554 | #define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x3 |
22555 | #define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_SDPM_RETURN__SHIFT 0x4 |
22556 | #define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_IREQ0_MASK 0x00000001L |
22557 | #define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_ATRET_MASK 0x00000002L |
22558 | #define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_OREQ_MASK 0x00000004L |
22559 | #define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x00000008L |
22560 | #define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_SDPM_RETURN_MASK 0x00000010L |
22561 | //MM_CANE_ERR_STATUS |
22562 | #define MM_CANE_ERR_STATUS__SDPM_RDRSP_STATUS__SHIFT 0x0 |
22563 | #define MM_CANE_ERR_STATUS__SDPM_WRRSP_STATUS__SHIFT 0x4 |
22564 | #define MM_CANE_ERR_STATUS__SDPM_RDRSP_DATASTATUS__SHIFT 0x8 |
22565 | #define MM_CANE_ERR_STATUS__SDPM_RDRSP_DATAPARITY_ERROR__SHIFT 0xa |
22566 | #define MM_CANE_ERR_STATUS__SDPS_DAT_ERROR__SHIFT 0xb |
22567 | #define MM_CANE_ERR_STATUS__SDPS_DAT_PARITY_ERROR__SHIFT 0xc |
22568 | #define MM_CANE_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xd |
22569 | #define MM_CANE_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xe |
22570 | #define MM_CANE_ERR_STATUS__BUSY_ON_UER_ERROR__SHIFT 0xf |
22571 | #define MM_CANE_ERR_STATUS__FUE_FLAG__SHIFT 0x10 |
22572 | #define MM_CANE_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0x11 |
22573 | #define MM_CANE_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x12 |
22574 | #define MM_CANE_ERR_STATUS__SDPM_RDRSP_STATUS_MASK 0x0000000FL |
22575 | #define MM_CANE_ERR_STATUS__SDPM_WRRSP_STATUS_MASK 0x000000F0L |
22576 | #define MM_CANE_ERR_STATUS__SDPM_RDRSP_DATASTATUS_MASK 0x00000300L |
22577 | #define MM_CANE_ERR_STATUS__SDPM_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L |
22578 | #define MM_CANE_ERR_STATUS__SDPS_DAT_ERROR_MASK 0x00000800L |
22579 | #define MM_CANE_ERR_STATUS__SDPS_DAT_PARITY_ERROR_MASK 0x00001000L |
22580 | #define MM_CANE_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00002000L |
22581 | #define MM_CANE_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00004000L |
22582 | #define MM_CANE_ERR_STATUS__BUSY_ON_UER_ERROR_MASK 0x00008000L |
22583 | #define MM_CANE_ERR_STATUS__FUE_FLAG_MASK 0x00010000L |
22584 | #define MM_CANE_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00020000L |
22585 | #define MM_CANE_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00040000L |
22586 | //MM_CANE_UE_ERR_STATUS_LO |
22587 | #define MM_CANE_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 |
22588 | #define MM_CANE_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 |
22589 | #define MM_CANE_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 |
22590 | #define MM_CANE_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 |
22591 | #define MM_CANE_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L |
22592 | #define MM_CANE_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L |
22593 | #define MM_CANE_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL |
22594 | #define MM_CANE_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L |
22595 | //MM_CANE_UE_ERR_STATUS_HI |
22596 | #define MM_CANE_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 |
22597 | #define MM_CANE_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 |
22598 | #define MM_CANE_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 |
22599 | #define MM_CANE_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 |
22600 | #define MM_CANE_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 |
22601 | #define MM_CANE_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a |
22602 | #define MM_CANE_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L |
22603 | #define MM_CANE_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L |
22604 | #define MM_CANE_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L |
22605 | #define MM_CANE_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L |
22606 | #define MM_CANE_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L |
22607 | #define MM_CANE_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L |
22608 | //MM_CANE_CE_ERR_STATUS_LO |
22609 | #define MM_CANE_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 |
22610 | #define MM_CANE_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 |
22611 | #define MM_CANE_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 |
22612 | #define MM_CANE_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 |
22613 | #define MM_CANE_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L |
22614 | #define MM_CANE_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L |
22615 | #define MM_CANE_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL |
22616 | #define MM_CANE_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L |
22617 | //MM_CANE_CE_ERR_STATUS_HI |
22618 | #define MM_CANE_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 |
22619 | #define MM_CANE_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 |
22620 | #define MM_CANE_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 |
22621 | #define MM_CANE_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 |
22622 | #define MM_CANE_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a |
22623 | #define MM_CANE_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L |
22624 | #define MM_CANE_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L |
22625 | #define MM_CANE_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L |
22626 | #define MM_CANE_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L |
22627 | #define MM_CANE_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L |
22628 | #endif |
22629 | |