1/*
2 * Copyright (C) 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21#ifndef _mmhub_9_1_SH_MASK_HEADER
22#define _mmhub_9_1_SH_MASK_HEADER
23
24
25// addressBlock: mmhub_dagbdec
26//DAGB0_RDCLI0
27#define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0
28#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29#define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4
30#define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8
31#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32#define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd
33#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15
34#define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16
35#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36#define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a
37#define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L
38#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
39#define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L
40#define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L
41#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L
42#define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L
43#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L
44#define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L
45#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
46#define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L
47//DAGB0_RDCLI1
48#define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0
49#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
50#define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4
51#define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8
52#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc
53#define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd
54#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15
55#define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16
56#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
57#define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a
58#define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L
59#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
60#define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L
61#define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L
62#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L
63#define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L
64#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L
65#define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L
66#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
67#define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L
68//DAGB0_RDCLI2
69#define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0
70#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
71#define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4
72#define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8
73#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc
74#define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd
75#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15
76#define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16
77#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
78#define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a
79#define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L
80#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
81#define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L
82#define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L
83#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L
84#define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L
85#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L
86#define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L
87#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
88#define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L
89//DAGB0_RDCLI3
90#define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0
91#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
92#define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4
93#define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8
94#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc
95#define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd
96#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15
97#define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16
98#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
99#define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a
100#define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L
101#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
102#define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L
103#define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L
104#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L
105#define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L
106#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L
107#define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L
108#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
109#define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L
110//DAGB0_RDCLI4
111#define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0
112#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
113#define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4
114#define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8
115#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc
116#define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd
117#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15
118#define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16
119#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
120#define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a
121#define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L
122#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
123#define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L
124#define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L
125#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L
126#define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L
127#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L
128#define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L
129#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
130#define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L
131//DAGB0_RDCLI5
132#define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0
133#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
134#define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4
135#define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8
136#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc
137#define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd
138#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15
139#define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16
140#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
141#define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a
142#define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L
143#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
144#define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L
145#define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L
146#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L
147#define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L
148#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L
149#define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L
150#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
151#define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L
152//DAGB0_RDCLI6
153#define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0
154#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
155#define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4
156#define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8
157#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc
158#define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd
159#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15
160#define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16
161#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
162#define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a
163#define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L
164#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
165#define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L
166#define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L
167#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L
168#define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L
169#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L
170#define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L
171#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
172#define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L
173//DAGB0_RDCLI7
174#define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0
175#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
176#define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4
177#define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8
178#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc
179#define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd
180#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15
181#define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16
182#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
183#define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a
184#define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L
185#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
186#define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L
187#define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L
188#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L
189#define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L
190#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L
191#define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L
192#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
193#define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L
194//DAGB0_RDCLI8
195#define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0
196#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
197#define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4
198#define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8
199#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc
200#define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd
201#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15
202#define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16
203#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
204#define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a
205#define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L
206#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
207#define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L
208#define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L
209#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L
210#define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L
211#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L
212#define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L
213#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
214#define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L
215//DAGB0_RDCLI9
216#define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0
217#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
218#define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4
219#define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8
220#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc
221#define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd
222#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15
223#define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16
224#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
225#define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a
226#define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L
227#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
228#define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L
229#define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L
230#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L
231#define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L
232#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L
233#define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L
234#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
235#define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L
236//DAGB0_RDCLI10
237#define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0
238#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
239#define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4
240#define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8
241#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc
242#define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd
243#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15
244#define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16
245#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
246#define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a
247#define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L
248#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
249#define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L
250#define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L
251#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L
252#define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L
253#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L
254#define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L
255#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
256#define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L
257//DAGB0_RDCLI11
258#define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0
259#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
260#define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4
261#define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8
262#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc
263#define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd
264#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15
265#define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16
266#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
267#define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a
268#define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L
269#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
270#define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L
271#define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L
272#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L
273#define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L
274#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L
275#define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L
276#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
277#define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L
278//DAGB0_RDCLI12
279#define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0
280#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
281#define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4
282#define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8
283#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc
284#define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd
285#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15
286#define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16
287#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
288#define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a
289#define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L
290#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
291#define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L
292#define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L
293#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L
294#define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L
295#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L
296#define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L
297#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
298#define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L
299//DAGB0_RDCLI13
300#define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0
301#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
302#define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4
303#define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8
304#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc
305#define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd
306#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15
307#define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16
308#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
309#define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a
310#define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L
311#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
312#define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L
313#define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L
314#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L
315#define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L
316#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L
317#define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L
318#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
319#define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L
320//DAGB0_RDCLI14
321#define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0
322#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
323#define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4
324#define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8
325#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc
326#define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd
327#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15
328#define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16
329#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
330#define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a
331#define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L
332#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
333#define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L
334#define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L
335#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L
336#define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L
337#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L
338#define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L
339#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
340#define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L
341//DAGB0_RDCLI15
342#define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0
343#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
344#define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4
345#define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8
346#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc
347#define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd
348#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15
349#define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16
350#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
351#define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a
352#define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L
353#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
354#define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L
355#define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L
356#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L
357#define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L
358#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L
359#define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L
360#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
361#define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L
362//DAGB0_RDCLI16
363#define DAGB0_RDCLI16__VIRT_CHAN__SHIFT 0x0
364#define DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3
365#define DAGB0_RDCLI16__URG_HIGH__SHIFT 0x4
366#define DAGB0_RDCLI16__URG_LOW__SHIFT 0x8
367#define DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc
368#define DAGB0_RDCLI16__MAX_BW__SHIFT 0xd
369#define DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15
370#define DAGB0_RDCLI16__MIN_BW__SHIFT 0x16
371#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19
372#define DAGB0_RDCLI16__MAX_OSD__SHIFT 0x1a
373#define DAGB0_RDCLI16__VIRT_CHAN_MASK 0x00000007L
374#define DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L
375#define DAGB0_RDCLI16__URG_HIGH_MASK 0x000000F0L
376#define DAGB0_RDCLI16__URG_LOW_MASK 0x00000F00L
377#define DAGB0_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L
378#define DAGB0_RDCLI16__MAX_BW_MASK 0x001FE000L
379#define DAGB0_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L
380#define DAGB0_RDCLI16__MIN_BW_MASK 0x01C00000L
381#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L
382#define DAGB0_RDCLI16__MAX_OSD_MASK 0xFC000000L
383//DAGB0_RDCLI17
384#define DAGB0_RDCLI17__VIRT_CHAN__SHIFT 0x0
385#define DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3
386#define DAGB0_RDCLI17__URG_HIGH__SHIFT 0x4
387#define DAGB0_RDCLI17__URG_LOW__SHIFT 0x8
388#define DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc
389#define DAGB0_RDCLI17__MAX_BW__SHIFT 0xd
390#define DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15
391#define DAGB0_RDCLI17__MIN_BW__SHIFT 0x16
392#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19
393#define DAGB0_RDCLI17__MAX_OSD__SHIFT 0x1a
394#define DAGB0_RDCLI17__VIRT_CHAN_MASK 0x00000007L
395#define DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L
396#define DAGB0_RDCLI17__URG_HIGH_MASK 0x000000F0L
397#define DAGB0_RDCLI17__URG_LOW_MASK 0x00000F00L
398#define DAGB0_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L
399#define DAGB0_RDCLI17__MAX_BW_MASK 0x001FE000L
400#define DAGB0_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L
401#define DAGB0_RDCLI17__MIN_BW_MASK 0x01C00000L
402#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L
403#define DAGB0_RDCLI17__MAX_OSD_MASK 0xFC000000L
404//DAGB0_RDCLI18
405#define DAGB0_RDCLI18__VIRT_CHAN__SHIFT 0x0
406#define DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3
407#define DAGB0_RDCLI18__URG_HIGH__SHIFT 0x4
408#define DAGB0_RDCLI18__URG_LOW__SHIFT 0x8
409#define DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc
410#define DAGB0_RDCLI18__MAX_BW__SHIFT 0xd
411#define DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15
412#define DAGB0_RDCLI18__MIN_BW__SHIFT 0x16
413#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19
414#define DAGB0_RDCLI18__MAX_OSD__SHIFT 0x1a
415#define DAGB0_RDCLI18__VIRT_CHAN_MASK 0x00000007L
416#define DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L
417#define DAGB0_RDCLI18__URG_HIGH_MASK 0x000000F0L
418#define DAGB0_RDCLI18__URG_LOW_MASK 0x00000F00L
419#define DAGB0_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L
420#define DAGB0_RDCLI18__MAX_BW_MASK 0x001FE000L
421#define DAGB0_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L
422#define DAGB0_RDCLI18__MIN_BW_MASK 0x01C00000L
423#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L
424#define DAGB0_RDCLI18__MAX_OSD_MASK 0xFC000000L
425//DAGB0_RDCLI19
426#define DAGB0_RDCLI19__VIRT_CHAN__SHIFT 0x0
427#define DAGB0_RDCLI19__CHECK_TLB_CREDIT__SHIFT 0x3
428#define DAGB0_RDCLI19__URG_HIGH__SHIFT 0x4
429#define DAGB0_RDCLI19__URG_LOW__SHIFT 0x8
430#define DAGB0_RDCLI19__MAX_BW_ENABLE__SHIFT 0xc
431#define DAGB0_RDCLI19__MAX_BW__SHIFT 0xd
432#define DAGB0_RDCLI19__MIN_BW_ENABLE__SHIFT 0x15
433#define DAGB0_RDCLI19__MIN_BW__SHIFT 0x16
434#define DAGB0_RDCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19
435#define DAGB0_RDCLI19__MAX_OSD__SHIFT 0x1a
436#define DAGB0_RDCLI19__VIRT_CHAN_MASK 0x00000007L
437#define DAGB0_RDCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L
438#define DAGB0_RDCLI19__URG_HIGH_MASK 0x000000F0L
439#define DAGB0_RDCLI19__URG_LOW_MASK 0x00000F00L
440#define DAGB0_RDCLI19__MAX_BW_ENABLE_MASK 0x00001000L
441#define DAGB0_RDCLI19__MAX_BW_MASK 0x001FE000L
442#define DAGB0_RDCLI19__MIN_BW_ENABLE_MASK 0x00200000L
443#define DAGB0_RDCLI19__MIN_BW_MASK 0x01C00000L
444#define DAGB0_RDCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L
445#define DAGB0_RDCLI19__MAX_OSD_MASK 0xFC000000L
446//DAGB0_RDCLI20
447#define DAGB0_RDCLI20__VIRT_CHAN__SHIFT 0x0
448#define DAGB0_RDCLI20__CHECK_TLB_CREDIT__SHIFT 0x3
449#define DAGB0_RDCLI20__URG_HIGH__SHIFT 0x4
450#define DAGB0_RDCLI20__URG_LOW__SHIFT 0x8
451#define DAGB0_RDCLI20__MAX_BW_ENABLE__SHIFT 0xc
452#define DAGB0_RDCLI20__MAX_BW__SHIFT 0xd
453#define DAGB0_RDCLI20__MIN_BW_ENABLE__SHIFT 0x15
454#define DAGB0_RDCLI20__MIN_BW__SHIFT 0x16
455#define DAGB0_RDCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19
456#define DAGB0_RDCLI20__MAX_OSD__SHIFT 0x1a
457#define DAGB0_RDCLI20__VIRT_CHAN_MASK 0x00000007L
458#define DAGB0_RDCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L
459#define DAGB0_RDCLI20__URG_HIGH_MASK 0x000000F0L
460#define DAGB0_RDCLI20__URG_LOW_MASK 0x00000F00L
461#define DAGB0_RDCLI20__MAX_BW_ENABLE_MASK 0x00001000L
462#define DAGB0_RDCLI20__MAX_BW_MASK 0x001FE000L
463#define DAGB0_RDCLI20__MIN_BW_ENABLE_MASK 0x00200000L
464#define DAGB0_RDCLI20__MIN_BW_MASK 0x01C00000L
465#define DAGB0_RDCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L
466#define DAGB0_RDCLI20__MAX_OSD_MASK 0xFC000000L
467//DAGB0_RDCLI21
468#define DAGB0_RDCLI21__VIRT_CHAN__SHIFT 0x0
469#define DAGB0_RDCLI21__CHECK_TLB_CREDIT__SHIFT 0x3
470#define DAGB0_RDCLI21__URG_HIGH__SHIFT 0x4
471#define DAGB0_RDCLI21__URG_LOW__SHIFT 0x8
472#define DAGB0_RDCLI21__MAX_BW_ENABLE__SHIFT 0xc
473#define DAGB0_RDCLI21__MAX_BW__SHIFT 0xd
474#define DAGB0_RDCLI21__MIN_BW_ENABLE__SHIFT 0x15
475#define DAGB0_RDCLI21__MIN_BW__SHIFT 0x16
476#define DAGB0_RDCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19
477#define DAGB0_RDCLI21__MAX_OSD__SHIFT 0x1a
478#define DAGB0_RDCLI21__VIRT_CHAN_MASK 0x00000007L
479#define DAGB0_RDCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L
480#define DAGB0_RDCLI21__URG_HIGH_MASK 0x000000F0L
481#define DAGB0_RDCLI21__URG_LOW_MASK 0x00000F00L
482#define DAGB0_RDCLI21__MAX_BW_ENABLE_MASK 0x00001000L
483#define DAGB0_RDCLI21__MAX_BW_MASK 0x001FE000L
484#define DAGB0_RDCLI21__MIN_BW_ENABLE_MASK 0x00200000L
485#define DAGB0_RDCLI21__MIN_BW_MASK 0x01C00000L
486#define DAGB0_RDCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L
487#define DAGB0_RDCLI21__MAX_OSD_MASK 0xFC000000L
488//DAGB0_RDCLI22
489#define DAGB0_RDCLI22__VIRT_CHAN__SHIFT 0x0
490#define DAGB0_RDCLI22__CHECK_TLB_CREDIT__SHIFT 0x3
491#define DAGB0_RDCLI22__URG_HIGH__SHIFT 0x4
492#define DAGB0_RDCLI22__URG_LOW__SHIFT 0x8
493#define DAGB0_RDCLI22__MAX_BW_ENABLE__SHIFT 0xc
494#define DAGB0_RDCLI22__MAX_BW__SHIFT 0xd
495#define DAGB0_RDCLI22__MIN_BW_ENABLE__SHIFT 0x15
496#define DAGB0_RDCLI22__MIN_BW__SHIFT 0x16
497#define DAGB0_RDCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19
498#define DAGB0_RDCLI22__MAX_OSD__SHIFT 0x1a
499#define DAGB0_RDCLI22__VIRT_CHAN_MASK 0x00000007L
500#define DAGB0_RDCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L
501#define DAGB0_RDCLI22__URG_HIGH_MASK 0x000000F0L
502#define DAGB0_RDCLI22__URG_LOW_MASK 0x00000F00L
503#define DAGB0_RDCLI22__MAX_BW_ENABLE_MASK 0x00001000L
504#define DAGB0_RDCLI22__MAX_BW_MASK 0x001FE000L
505#define DAGB0_RDCLI22__MIN_BW_ENABLE_MASK 0x00200000L
506#define DAGB0_RDCLI22__MIN_BW_MASK 0x01C00000L
507#define DAGB0_RDCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L
508#define DAGB0_RDCLI22__MAX_OSD_MASK 0xFC000000L
509//DAGB0_RDCLI23
510#define DAGB0_RDCLI23__VIRT_CHAN__SHIFT 0x0
511#define DAGB0_RDCLI23__CHECK_TLB_CREDIT__SHIFT 0x3
512#define DAGB0_RDCLI23__URG_HIGH__SHIFT 0x4
513#define DAGB0_RDCLI23__URG_LOW__SHIFT 0x8
514#define DAGB0_RDCLI23__MAX_BW_ENABLE__SHIFT 0xc
515#define DAGB0_RDCLI23__MAX_BW__SHIFT 0xd
516#define DAGB0_RDCLI23__MIN_BW_ENABLE__SHIFT 0x15
517#define DAGB0_RDCLI23__MIN_BW__SHIFT 0x16
518#define DAGB0_RDCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19
519#define DAGB0_RDCLI23__MAX_OSD__SHIFT 0x1a
520#define DAGB0_RDCLI23__VIRT_CHAN_MASK 0x00000007L
521#define DAGB0_RDCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L
522#define DAGB0_RDCLI23__URG_HIGH_MASK 0x000000F0L
523#define DAGB0_RDCLI23__URG_LOW_MASK 0x00000F00L
524#define DAGB0_RDCLI23__MAX_BW_ENABLE_MASK 0x00001000L
525#define DAGB0_RDCLI23__MAX_BW_MASK 0x001FE000L
526#define DAGB0_RDCLI23__MIN_BW_ENABLE_MASK 0x00200000L
527#define DAGB0_RDCLI23__MIN_BW_MASK 0x01C00000L
528#define DAGB0_RDCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L
529#define DAGB0_RDCLI23__MAX_OSD_MASK 0xFC000000L
530//DAGB0_RDCLI24
531#define DAGB0_RDCLI24__VIRT_CHAN__SHIFT 0x0
532#define DAGB0_RDCLI24__CHECK_TLB_CREDIT__SHIFT 0x3
533#define DAGB0_RDCLI24__URG_HIGH__SHIFT 0x4
534#define DAGB0_RDCLI24__URG_LOW__SHIFT 0x8
535#define DAGB0_RDCLI24__MAX_BW_ENABLE__SHIFT 0xc
536#define DAGB0_RDCLI24__MAX_BW__SHIFT 0xd
537#define DAGB0_RDCLI24__MIN_BW_ENABLE__SHIFT 0x15
538#define DAGB0_RDCLI24__MIN_BW__SHIFT 0x16
539#define DAGB0_RDCLI24__OSD_LIMITER_ENABLE__SHIFT 0x19
540#define DAGB0_RDCLI24__MAX_OSD__SHIFT 0x1a
541#define DAGB0_RDCLI24__VIRT_CHAN_MASK 0x00000007L
542#define DAGB0_RDCLI24__CHECK_TLB_CREDIT_MASK 0x00000008L
543#define DAGB0_RDCLI24__URG_HIGH_MASK 0x000000F0L
544#define DAGB0_RDCLI24__URG_LOW_MASK 0x00000F00L
545#define DAGB0_RDCLI24__MAX_BW_ENABLE_MASK 0x00001000L
546#define DAGB0_RDCLI24__MAX_BW_MASK 0x001FE000L
547#define DAGB0_RDCLI24__MIN_BW_ENABLE_MASK 0x00200000L
548#define DAGB0_RDCLI24__MIN_BW_MASK 0x01C00000L
549#define DAGB0_RDCLI24__OSD_LIMITER_ENABLE_MASK 0x02000000L
550#define DAGB0_RDCLI24__MAX_OSD_MASK 0xFC000000L
551//DAGB0_RDCLI25
552#define DAGB0_RDCLI25__VIRT_CHAN__SHIFT 0x0
553#define DAGB0_RDCLI25__CHECK_TLB_CREDIT__SHIFT 0x3
554#define DAGB0_RDCLI25__URG_HIGH__SHIFT 0x4
555#define DAGB0_RDCLI25__URG_LOW__SHIFT 0x8
556#define DAGB0_RDCLI25__MAX_BW_ENABLE__SHIFT 0xc
557#define DAGB0_RDCLI25__MAX_BW__SHIFT 0xd
558#define DAGB0_RDCLI25__MIN_BW_ENABLE__SHIFT 0x15
559#define DAGB0_RDCLI25__MIN_BW__SHIFT 0x16
560#define DAGB0_RDCLI25__OSD_LIMITER_ENABLE__SHIFT 0x19
561#define DAGB0_RDCLI25__MAX_OSD__SHIFT 0x1a
562#define DAGB0_RDCLI25__VIRT_CHAN_MASK 0x00000007L
563#define DAGB0_RDCLI25__CHECK_TLB_CREDIT_MASK 0x00000008L
564#define DAGB0_RDCLI25__URG_HIGH_MASK 0x000000F0L
565#define DAGB0_RDCLI25__URG_LOW_MASK 0x00000F00L
566#define DAGB0_RDCLI25__MAX_BW_ENABLE_MASK 0x00001000L
567#define DAGB0_RDCLI25__MAX_BW_MASK 0x001FE000L
568#define DAGB0_RDCLI25__MIN_BW_ENABLE_MASK 0x00200000L
569#define DAGB0_RDCLI25__MIN_BW_MASK 0x01C00000L
570#define DAGB0_RDCLI25__OSD_LIMITER_ENABLE_MASK 0x02000000L
571#define DAGB0_RDCLI25__MAX_OSD_MASK 0xFC000000L
572//DAGB0_RDCLI26
573#define DAGB0_RDCLI26__VIRT_CHAN__SHIFT 0x0
574#define DAGB0_RDCLI26__CHECK_TLB_CREDIT__SHIFT 0x3
575#define DAGB0_RDCLI26__URG_HIGH__SHIFT 0x4
576#define DAGB0_RDCLI26__URG_LOW__SHIFT 0x8
577#define DAGB0_RDCLI26__MAX_BW_ENABLE__SHIFT 0xc
578#define DAGB0_RDCLI26__MAX_BW__SHIFT 0xd
579#define DAGB0_RDCLI26__MIN_BW_ENABLE__SHIFT 0x15
580#define DAGB0_RDCLI26__MIN_BW__SHIFT 0x16
581#define DAGB0_RDCLI26__OSD_LIMITER_ENABLE__SHIFT 0x19
582#define DAGB0_RDCLI26__MAX_OSD__SHIFT 0x1a
583#define DAGB0_RDCLI26__VIRT_CHAN_MASK 0x00000007L
584#define DAGB0_RDCLI26__CHECK_TLB_CREDIT_MASK 0x00000008L
585#define DAGB0_RDCLI26__URG_HIGH_MASK 0x000000F0L
586#define DAGB0_RDCLI26__URG_LOW_MASK 0x00000F00L
587#define DAGB0_RDCLI26__MAX_BW_ENABLE_MASK 0x00001000L
588#define DAGB0_RDCLI26__MAX_BW_MASK 0x001FE000L
589#define DAGB0_RDCLI26__MIN_BW_ENABLE_MASK 0x00200000L
590#define DAGB0_RDCLI26__MIN_BW_MASK 0x01C00000L
591#define DAGB0_RDCLI26__OSD_LIMITER_ENABLE_MASK 0x02000000L
592#define DAGB0_RDCLI26__MAX_OSD_MASK 0xFC000000L
593//DAGB0_RDCLI27
594#define DAGB0_RDCLI27__VIRT_CHAN__SHIFT 0x0
595#define DAGB0_RDCLI27__CHECK_TLB_CREDIT__SHIFT 0x3
596#define DAGB0_RDCLI27__URG_HIGH__SHIFT 0x4
597#define DAGB0_RDCLI27__URG_LOW__SHIFT 0x8
598#define DAGB0_RDCLI27__MAX_BW_ENABLE__SHIFT 0xc
599#define DAGB0_RDCLI27__MAX_BW__SHIFT 0xd
600#define DAGB0_RDCLI27__MIN_BW_ENABLE__SHIFT 0x15
601#define DAGB0_RDCLI27__MIN_BW__SHIFT 0x16
602#define DAGB0_RDCLI27__OSD_LIMITER_ENABLE__SHIFT 0x19
603#define DAGB0_RDCLI27__MAX_OSD__SHIFT 0x1a
604#define DAGB0_RDCLI27__VIRT_CHAN_MASK 0x00000007L
605#define DAGB0_RDCLI27__CHECK_TLB_CREDIT_MASK 0x00000008L
606#define DAGB0_RDCLI27__URG_HIGH_MASK 0x000000F0L
607#define DAGB0_RDCLI27__URG_LOW_MASK 0x00000F00L
608#define DAGB0_RDCLI27__MAX_BW_ENABLE_MASK 0x00001000L
609#define DAGB0_RDCLI27__MAX_BW_MASK 0x001FE000L
610#define DAGB0_RDCLI27__MIN_BW_ENABLE_MASK 0x00200000L
611#define DAGB0_RDCLI27__MIN_BW_MASK 0x01C00000L
612#define DAGB0_RDCLI27__OSD_LIMITER_ENABLE_MASK 0x02000000L
613#define DAGB0_RDCLI27__MAX_OSD_MASK 0xFC000000L
614//DAGB0_RDCLI28
615#define DAGB0_RDCLI28__VIRT_CHAN__SHIFT 0x0
616#define DAGB0_RDCLI28__CHECK_TLB_CREDIT__SHIFT 0x3
617#define DAGB0_RDCLI28__URG_HIGH__SHIFT 0x4
618#define DAGB0_RDCLI28__URG_LOW__SHIFT 0x8
619#define DAGB0_RDCLI28__MAX_BW_ENABLE__SHIFT 0xc
620#define DAGB0_RDCLI28__MAX_BW__SHIFT 0xd
621#define DAGB0_RDCLI28__MIN_BW_ENABLE__SHIFT 0x15
622#define DAGB0_RDCLI28__MIN_BW__SHIFT 0x16
623#define DAGB0_RDCLI28__OSD_LIMITER_ENABLE__SHIFT 0x19
624#define DAGB0_RDCLI28__MAX_OSD__SHIFT 0x1a
625#define DAGB0_RDCLI28__VIRT_CHAN_MASK 0x00000007L
626#define DAGB0_RDCLI28__CHECK_TLB_CREDIT_MASK 0x00000008L
627#define DAGB0_RDCLI28__URG_HIGH_MASK 0x000000F0L
628#define DAGB0_RDCLI28__URG_LOW_MASK 0x00000F00L
629#define DAGB0_RDCLI28__MAX_BW_ENABLE_MASK 0x00001000L
630#define DAGB0_RDCLI28__MAX_BW_MASK 0x001FE000L
631#define DAGB0_RDCLI28__MIN_BW_ENABLE_MASK 0x00200000L
632#define DAGB0_RDCLI28__MIN_BW_MASK 0x01C00000L
633#define DAGB0_RDCLI28__OSD_LIMITER_ENABLE_MASK 0x02000000L
634#define DAGB0_RDCLI28__MAX_OSD_MASK 0xFC000000L
635//DAGB0_RDCLI29
636#define DAGB0_RDCLI29__VIRT_CHAN__SHIFT 0x0
637#define DAGB0_RDCLI29__CHECK_TLB_CREDIT__SHIFT 0x3
638#define DAGB0_RDCLI29__URG_HIGH__SHIFT 0x4
639#define DAGB0_RDCLI29__URG_LOW__SHIFT 0x8
640#define DAGB0_RDCLI29__MAX_BW_ENABLE__SHIFT 0xc
641#define DAGB0_RDCLI29__MAX_BW__SHIFT 0xd
642#define DAGB0_RDCLI29__MIN_BW_ENABLE__SHIFT 0x15
643#define DAGB0_RDCLI29__MIN_BW__SHIFT 0x16
644#define DAGB0_RDCLI29__OSD_LIMITER_ENABLE__SHIFT 0x19
645#define DAGB0_RDCLI29__MAX_OSD__SHIFT 0x1a
646#define DAGB0_RDCLI29__VIRT_CHAN_MASK 0x00000007L
647#define DAGB0_RDCLI29__CHECK_TLB_CREDIT_MASK 0x00000008L
648#define DAGB0_RDCLI29__URG_HIGH_MASK 0x000000F0L
649#define DAGB0_RDCLI29__URG_LOW_MASK 0x00000F00L
650#define DAGB0_RDCLI29__MAX_BW_ENABLE_MASK 0x00001000L
651#define DAGB0_RDCLI29__MAX_BW_MASK 0x001FE000L
652#define DAGB0_RDCLI29__MIN_BW_ENABLE_MASK 0x00200000L
653#define DAGB0_RDCLI29__MIN_BW_MASK 0x01C00000L
654#define DAGB0_RDCLI29__OSD_LIMITER_ENABLE_MASK 0x02000000L
655#define DAGB0_RDCLI29__MAX_OSD_MASK 0xFC000000L
656//DAGB0_RDCLI30
657#define DAGB0_RDCLI30__VIRT_CHAN__SHIFT 0x0
658#define DAGB0_RDCLI30__CHECK_TLB_CREDIT__SHIFT 0x3
659#define DAGB0_RDCLI30__URG_HIGH__SHIFT 0x4
660#define DAGB0_RDCLI30__URG_LOW__SHIFT 0x8
661#define DAGB0_RDCLI30__MAX_BW_ENABLE__SHIFT 0xc
662#define DAGB0_RDCLI30__MAX_BW__SHIFT 0xd
663#define DAGB0_RDCLI30__MIN_BW_ENABLE__SHIFT 0x15
664#define DAGB0_RDCLI30__MIN_BW__SHIFT 0x16
665#define DAGB0_RDCLI30__OSD_LIMITER_ENABLE__SHIFT 0x19
666#define DAGB0_RDCLI30__MAX_OSD__SHIFT 0x1a
667#define DAGB0_RDCLI30__VIRT_CHAN_MASK 0x00000007L
668#define DAGB0_RDCLI30__CHECK_TLB_CREDIT_MASK 0x00000008L
669#define DAGB0_RDCLI30__URG_HIGH_MASK 0x000000F0L
670#define DAGB0_RDCLI30__URG_LOW_MASK 0x00000F00L
671#define DAGB0_RDCLI30__MAX_BW_ENABLE_MASK 0x00001000L
672#define DAGB0_RDCLI30__MAX_BW_MASK 0x001FE000L
673#define DAGB0_RDCLI30__MIN_BW_ENABLE_MASK 0x00200000L
674#define DAGB0_RDCLI30__MIN_BW_MASK 0x01C00000L
675#define DAGB0_RDCLI30__OSD_LIMITER_ENABLE_MASK 0x02000000L
676#define DAGB0_RDCLI30__MAX_OSD_MASK 0xFC000000L
677//DAGB0_RDCLI31
678#define DAGB0_RDCLI31__VIRT_CHAN__SHIFT 0x0
679#define DAGB0_RDCLI31__CHECK_TLB_CREDIT__SHIFT 0x3
680#define DAGB0_RDCLI31__URG_HIGH__SHIFT 0x4
681#define DAGB0_RDCLI31__URG_LOW__SHIFT 0x8
682#define DAGB0_RDCLI31__MAX_BW_ENABLE__SHIFT 0xc
683#define DAGB0_RDCLI31__MAX_BW__SHIFT 0xd
684#define DAGB0_RDCLI31__MIN_BW_ENABLE__SHIFT 0x15
685#define DAGB0_RDCLI31__MIN_BW__SHIFT 0x16
686#define DAGB0_RDCLI31__OSD_LIMITER_ENABLE__SHIFT 0x19
687#define DAGB0_RDCLI31__MAX_OSD__SHIFT 0x1a
688#define DAGB0_RDCLI31__VIRT_CHAN_MASK 0x00000007L
689#define DAGB0_RDCLI31__CHECK_TLB_CREDIT_MASK 0x00000008L
690#define DAGB0_RDCLI31__URG_HIGH_MASK 0x000000F0L
691#define DAGB0_RDCLI31__URG_LOW_MASK 0x00000F00L
692#define DAGB0_RDCLI31__MAX_BW_ENABLE_MASK 0x00001000L
693#define DAGB0_RDCLI31__MAX_BW_MASK 0x001FE000L
694#define DAGB0_RDCLI31__MIN_BW_ENABLE_MASK 0x00200000L
695#define DAGB0_RDCLI31__MIN_BW_MASK 0x01C00000L
696#define DAGB0_RDCLI31__OSD_LIMITER_ENABLE_MASK 0x02000000L
697#define DAGB0_RDCLI31__MAX_OSD_MASK 0xFC000000L
698//DAGB0_RD_CNTL
699#define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT 0x0
700#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
701#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
702#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
703#define DAGB0_RD_CNTL__IO_LEVEL__SHIFT 0x11
704#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
705#define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17
706#define DAGB0_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL
707#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
708#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
709#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
710#define DAGB0_RD_CNTL__IO_LEVEL_MASK 0x000E0000L
711#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
712#define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L
713//DAGB0_RD_GMI_CNTL
714#define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0
715#define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT 0x6
716#define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9
717#define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
718#define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
719#define DAGB0_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L
720#define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
721#define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
722//DAGB0_RD_ADDR_DAGB
723#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
724#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
725#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
726#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7
727#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
728#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
729#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
730#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
731//DAGB0_RD_OUTPUT_DAGB_MAX_BURST
732#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
733#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
734#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
735#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
736#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
737#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
738#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
739#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
740#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
741#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
742#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
743#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
744#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
745#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
746#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
747#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
748//DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER
749#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
750#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
751#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
752#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
753#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
754#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
755#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
756#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
757#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
758#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
759#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
760#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
761#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
762#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
763#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
764#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
765//DAGB0_RD_CGTT_CLK_CTRL
766#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
767#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
768#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
769#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
770#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
771#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
772#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
773#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
774#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
775#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
776#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
777#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
778#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
779#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
780#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
781#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
782//DAGB0_L1TLB_RD_CGTT_CLK_CTRL
783#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
784#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
785#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
786#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
787#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
788#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
789#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
790#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
791#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
792#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
793#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
794#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
795#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
796#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
797#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
798#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
799//DAGB0_ATCVM_RD_CGTT_CLK_CTRL
800#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
801#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
802#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
803#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
804#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
805#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
806#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
807#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
808#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
809#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
810#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
811#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
812#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
813#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
814#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
815#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
816//DAGB0_RD_ADDR_DAGB_MAX_BURST0
817#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
818#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
819#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
820#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
821#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
822#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
823#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
824#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
825#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
826#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
827#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
828#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
829#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
830#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
831#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
832#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
833//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0
834#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
835#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
836#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
837#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
838#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
839#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
840#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
841#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
842#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
843#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
844#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
845#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
846#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
847#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
848#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
849#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
850//DAGB0_RD_ADDR_DAGB_MAX_BURST1
851#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
852#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
853#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
854#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
855#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
856#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
857#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
858#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
859#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
860#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
861#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
862#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
863#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
864#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
865#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
866#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
867//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1
868#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
869#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
870#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
871#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
872#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
873#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
874#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
875#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
876#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
877#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
878#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
879#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
880#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
881#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
882#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
883#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
884//DAGB0_RD_ADDR_DAGB_MAX_BURST2
885#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0
886#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4
887#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8
888#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc
889#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10
890#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14
891#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18
892#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c
893#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL
894#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L
895#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L
896#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L
897#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L
898#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L
899#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L
900#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L
901//DAGB0_RD_ADDR_DAGB_LAZY_TIMER2
902#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0
903#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4
904#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8
905#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc
906#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10
907#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14
908#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18
909#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c
910#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL
911#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L
912#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L
913#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L
914#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L
915#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L
916#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L
917#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L
918//DAGB0_RD_ADDR_DAGB_MAX_BURST3
919#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0
920#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4
921#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8
922#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc
923#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10
924#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14
925#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18
926#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c
927#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL
928#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L
929#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L
930#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L
931#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L
932#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L
933#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L
934#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L
935//DAGB0_RD_ADDR_DAGB_LAZY_TIMER3
936#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0
937#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4
938#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8
939#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc
940#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10
941#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14
942#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18
943#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c
944#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL
945#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L
946#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L
947#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L
948#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L
949#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L
950#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L
951#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L
952//DAGB0_RD_VC0_CNTL
953#define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
954#define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5
955#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
956#define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc
957#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
958#define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15
959#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
960#define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19
961#define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
962#define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
963#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
964#define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L
965#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
966#define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L
967#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
968#define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
969//DAGB0_RD_VC1_CNTL
970#define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
971#define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5
972#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
973#define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc
974#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
975#define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15
976#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
977#define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19
978#define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
979#define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
980#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
981#define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L
982#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
983#define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L
984#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
985#define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
986//DAGB0_RD_VC2_CNTL
987#define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
988#define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5
989#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
990#define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc
991#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
992#define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15
993#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
994#define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19
995#define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
996#define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
997#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
998#define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L
999#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
1000#define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L
1001#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
1002#define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
1003//DAGB0_RD_VC3_CNTL
1004#define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
1005#define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5
1006#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
1007#define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc
1008#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
1009#define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15
1010#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
1011#define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19
1012#define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
1013#define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
1014#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
1015#define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L
1016#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
1017#define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L
1018#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
1019#define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
1020//DAGB0_RD_VC4_CNTL
1021#define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
1022#define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5
1023#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
1024#define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc
1025#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
1026#define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15
1027#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
1028#define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19
1029#define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
1030#define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
1031#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
1032#define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L
1033#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
1034#define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L
1035#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
1036#define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
1037//DAGB0_RD_VC5_CNTL
1038#define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
1039#define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5
1040#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
1041#define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc
1042#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
1043#define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15
1044#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
1045#define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19
1046#define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
1047#define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
1048#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
1049#define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L
1050#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
1051#define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L
1052#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
1053#define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
1054//DAGB0_RD_VC6_CNTL
1055#define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
1056#define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5
1057#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
1058#define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT 0xc
1059#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
1060#define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT 0x15
1061#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
1062#define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19
1063#define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
1064#define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
1065#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
1066#define DAGB0_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L
1067#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
1068#define DAGB0_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L
1069#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
1070#define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
1071//DAGB0_RD_VC7_CNTL
1072#define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
1073#define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5
1074#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
1075#define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT 0xc
1076#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
1077#define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT 0x15
1078#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
1079#define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19
1080#define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
1081#define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
1082#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
1083#define DAGB0_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L
1084#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
1085#define DAGB0_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L
1086#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
1087#define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
1088//DAGB0_RD_CNTL_MISC
1089#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
1090#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
1091#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
1092#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
1093#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
1094#define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15
1095#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
1096#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
1097#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
1098#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
1099#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
1100#define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
1101//DAGB0_RD_TLB_CREDIT
1102#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0
1103#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5
1104#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa
1105#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf
1106#define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14
1107#define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19
1108#define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL
1109#define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L
1110#define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L
1111#define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L
1112#define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L
1113#define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L
1114//DAGB0_RDCLI_ASK_PENDING
1115#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0
1116#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
1117//DAGB0_RDCLI_GO_PENDING
1118#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0
1119#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
1120//DAGB0_RDCLI_GBLSEND_PENDING
1121#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
1122#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
1123//DAGB0_RDCLI_TLB_PENDING
1124#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0
1125#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
1126//DAGB0_RDCLI_OARB_PENDING
1127#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0
1128#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
1129//DAGB0_RDCLI_OSD_PENDING
1130#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0
1131#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
1132//DAGB0_WRCLI0
1133#define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0
1134#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
1135#define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4
1136#define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8
1137#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc
1138#define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd
1139#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15
1140#define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16
1141#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
1142#define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a
1143#define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L
1144#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
1145#define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L
1146#define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L
1147#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L
1148#define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L
1149#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L
1150#define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L
1151#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
1152#define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L
1153//DAGB0_WRCLI1
1154#define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0
1155#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
1156#define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4
1157#define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8
1158#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc
1159#define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd
1160#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15
1161#define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16
1162#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
1163#define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a
1164#define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L
1165#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
1166#define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L
1167#define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L
1168#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L
1169#define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L
1170#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L
1171#define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L
1172#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
1173#define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L
1174//DAGB0_WRCLI2
1175#define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0
1176#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
1177#define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4
1178#define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8
1179#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc
1180#define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd
1181#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15
1182#define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16
1183#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
1184#define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a
1185#define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L
1186#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
1187#define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L
1188#define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L
1189#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L
1190#define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L
1191#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L
1192#define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L
1193#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
1194#define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L
1195//DAGB0_WRCLI3
1196#define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0
1197#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
1198#define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4
1199#define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8
1200#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc
1201#define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd
1202#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15
1203#define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16
1204#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
1205#define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a
1206#define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L
1207#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
1208#define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L
1209#define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L
1210#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L
1211#define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L
1212#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L
1213#define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L
1214#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
1215#define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L
1216//DAGB0_WRCLI4
1217#define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0
1218#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
1219#define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4
1220#define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8
1221#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc
1222#define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd
1223#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15
1224#define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16
1225#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
1226#define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a
1227#define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L
1228#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
1229#define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L
1230#define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L
1231#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L
1232#define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L
1233#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L
1234#define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L
1235#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
1236#define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L
1237//DAGB0_WRCLI5
1238#define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0
1239#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
1240#define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4
1241#define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8
1242#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc
1243#define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd
1244#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15
1245#define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16
1246#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
1247#define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a
1248#define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L
1249#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
1250#define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L
1251#define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L
1252#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L
1253#define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L
1254#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L
1255#define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L
1256#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
1257#define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L
1258//DAGB0_WRCLI6
1259#define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0
1260#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
1261#define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4
1262#define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8
1263#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc
1264#define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd
1265#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15
1266#define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16
1267#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
1268#define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a
1269#define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L
1270#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
1271#define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L
1272#define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L
1273#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L
1274#define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L
1275#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L
1276#define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L
1277#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
1278#define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L
1279//DAGB0_WRCLI7
1280#define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0
1281#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
1282#define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4
1283#define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8
1284#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc
1285#define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd
1286#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15
1287#define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16
1288#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
1289#define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a
1290#define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L
1291#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
1292#define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L
1293#define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L
1294#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L
1295#define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L
1296#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L
1297#define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L
1298#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
1299#define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L
1300//DAGB0_WRCLI8
1301#define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0
1302#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
1303#define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4
1304#define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8
1305#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc
1306#define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd
1307#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15
1308#define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16
1309#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
1310#define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a
1311#define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L
1312#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
1313#define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L
1314#define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L
1315#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L
1316#define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L
1317#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L
1318#define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L
1319#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
1320#define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L
1321//DAGB0_WRCLI9
1322#define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0
1323#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
1324#define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4
1325#define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8
1326#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc
1327#define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd
1328#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15
1329#define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16
1330#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
1331#define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a
1332#define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L
1333#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
1334#define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L
1335#define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L
1336#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L
1337#define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L
1338#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L
1339#define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L
1340#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
1341#define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L
1342//DAGB0_WRCLI10
1343#define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0
1344#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
1345#define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4
1346#define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8
1347#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc
1348#define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd
1349#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15
1350#define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16
1351#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
1352#define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a
1353#define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L
1354#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
1355#define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L
1356#define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L
1357#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L
1358#define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L
1359#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L
1360#define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L
1361#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
1362#define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L
1363//DAGB0_WRCLI11
1364#define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0
1365#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
1366#define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4
1367#define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8
1368#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc
1369#define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd
1370#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15
1371#define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16
1372#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
1373#define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a
1374#define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L
1375#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
1376#define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L
1377#define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L
1378#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L
1379#define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L
1380#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L
1381#define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L
1382#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
1383#define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L
1384//DAGB0_WRCLI12
1385#define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0
1386#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
1387#define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4
1388#define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8
1389#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc
1390#define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd
1391#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15
1392#define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16
1393#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
1394#define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a
1395#define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L
1396#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
1397#define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L
1398#define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L
1399#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L
1400#define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L
1401#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L
1402#define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L
1403#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
1404#define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L
1405//DAGB0_WRCLI13
1406#define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0
1407#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
1408#define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4
1409#define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8
1410#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc
1411#define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd
1412#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15
1413#define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16
1414#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
1415#define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a
1416#define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L
1417#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
1418#define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L
1419#define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L
1420#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L
1421#define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L
1422#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L
1423#define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L
1424#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
1425#define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L
1426//DAGB0_WRCLI14
1427#define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0
1428#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
1429#define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4
1430#define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8
1431#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc
1432#define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd
1433#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15
1434#define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16
1435#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
1436#define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a
1437#define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L
1438#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
1439#define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L
1440#define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L
1441#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L
1442#define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L
1443#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L
1444#define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L
1445#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
1446#define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L
1447//DAGB0_WRCLI15
1448#define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0
1449#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
1450#define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4
1451#define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8
1452#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc
1453#define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd
1454#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15
1455#define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16
1456#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
1457#define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a
1458#define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L
1459#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
1460#define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L
1461#define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L
1462#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L
1463#define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L
1464#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L
1465#define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L
1466#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
1467#define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L
1468//DAGB0_WRCLI16
1469#define DAGB0_WRCLI16__VIRT_CHAN__SHIFT 0x0
1470#define DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT 0x3
1471#define DAGB0_WRCLI16__URG_HIGH__SHIFT 0x4
1472#define DAGB0_WRCLI16__URG_LOW__SHIFT 0x8
1473#define DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT 0xc
1474#define DAGB0_WRCLI16__MAX_BW__SHIFT 0xd
1475#define DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT 0x15
1476#define DAGB0_WRCLI16__MIN_BW__SHIFT 0x16
1477#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19
1478#define DAGB0_WRCLI16__MAX_OSD__SHIFT 0x1a
1479#define DAGB0_WRCLI16__VIRT_CHAN_MASK 0x00000007L
1480#define DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L
1481#define DAGB0_WRCLI16__URG_HIGH_MASK 0x000000F0L
1482#define DAGB0_WRCLI16__URG_LOW_MASK 0x00000F00L
1483#define DAGB0_WRCLI16__MAX_BW_ENABLE_MASK 0x00001000L
1484#define DAGB0_WRCLI16__MAX_BW_MASK 0x001FE000L
1485#define DAGB0_WRCLI16__MIN_BW_ENABLE_MASK 0x00200000L
1486#define DAGB0_WRCLI16__MIN_BW_MASK 0x01C00000L
1487#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L
1488#define DAGB0_WRCLI16__MAX_OSD_MASK 0xFC000000L
1489//DAGB0_WRCLI17
1490#define DAGB0_WRCLI17__VIRT_CHAN__SHIFT 0x0
1491#define DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT 0x3
1492#define DAGB0_WRCLI17__URG_HIGH__SHIFT 0x4
1493#define DAGB0_WRCLI17__URG_LOW__SHIFT 0x8
1494#define DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT 0xc
1495#define DAGB0_WRCLI17__MAX_BW__SHIFT 0xd
1496#define DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT 0x15
1497#define DAGB0_WRCLI17__MIN_BW__SHIFT 0x16
1498#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19
1499#define DAGB0_WRCLI17__MAX_OSD__SHIFT 0x1a
1500#define DAGB0_WRCLI17__VIRT_CHAN_MASK 0x00000007L
1501#define DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L
1502#define DAGB0_WRCLI17__URG_HIGH_MASK 0x000000F0L
1503#define DAGB0_WRCLI17__URG_LOW_MASK 0x00000F00L
1504#define DAGB0_WRCLI17__MAX_BW_ENABLE_MASK 0x00001000L
1505#define DAGB0_WRCLI17__MAX_BW_MASK 0x001FE000L
1506#define DAGB0_WRCLI17__MIN_BW_ENABLE_MASK 0x00200000L
1507#define DAGB0_WRCLI17__MIN_BW_MASK 0x01C00000L
1508#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L
1509#define DAGB0_WRCLI17__MAX_OSD_MASK 0xFC000000L
1510//DAGB0_WRCLI18
1511#define DAGB0_WRCLI18__VIRT_CHAN__SHIFT 0x0
1512#define DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT 0x3
1513#define DAGB0_WRCLI18__URG_HIGH__SHIFT 0x4
1514#define DAGB0_WRCLI18__URG_LOW__SHIFT 0x8
1515#define DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT 0xc
1516#define DAGB0_WRCLI18__MAX_BW__SHIFT 0xd
1517#define DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT 0x15
1518#define DAGB0_WRCLI18__MIN_BW__SHIFT 0x16
1519#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19
1520#define DAGB0_WRCLI18__MAX_OSD__SHIFT 0x1a
1521#define DAGB0_WRCLI18__VIRT_CHAN_MASK 0x00000007L
1522#define DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L
1523#define DAGB0_WRCLI18__URG_HIGH_MASK 0x000000F0L
1524#define DAGB0_WRCLI18__URG_LOW_MASK 0x00000F00L
1525#define DAGB0_WRCLI18__MAX_BW_ENABLE_MASK 0x00001000L
1526#define DAGB0_WRCLI18__MAX_BW_MASK 0x001FE000L
1527#define DAGB0_WRCLI18__MIN_BW_ENABLE_MASK 0x00200000L
1528#define DAGB0_WRCLI18__MIN_BW_MASK 0x01C00000L
1529#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L
1530#define DAGB0_WRCLI18__MAX_OSD_MASK 0xFC000000L
1531//DAGB0_WRCLI19
1532#define DAGB0_WRCLI19__VIRT_CHAN__SHIFT 0x0
1533#define DAGB0_WRCLI19__CHECK_TLB_CREDIT__SHIFT 0x3
1534#define DAGB0_WRCLI19__URG_HIGH__SHIFT 0x4
1535#define DAGB0_WRCLI19__URG_LOW__SHIFT 0x8
1536#define DAGB0_WRCLI19__MAX_BW_ENABLE__SHIFT 0xc
1537#define DAGB0_WRCLI19__MAX_BW__SHIFT 0xd
1538#define DAGB0_WRCLI19__MIN_BW_ENABLE__SHIFT 0x15
1539#define DAGB0_WRCLI19__MIN_BW__SHIFT 0x16
1540#define DAGB0_WRCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19
1541#define DAGB0_WRCLI19__MAX_OSD__SHIFT 0x1a
1542#define DAGB0_WRCLI19__VIRT_CHAN_MASK 0x00000007L
1543#define DAGB0_WRCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L
1544#define DAGB0_WRCLI19__URG_HIGH_MASK 0x000000F0L
1545#define DAGB0_WRCLI19__URG_LOW_MASK 0x00000F00L
1546#define DAGB0_WRCLI19__MAX_BW_ENABLE_MASK 0x00001000L
1547#define DAGB0_WRCLI19__MAX_BW_MASK 0x001FE000L
1548#define DAGB0_WRCLI19__MIN_BW_ENABLE_MASK 0x00200000L
1549#define DAGB0_WRCLI19__MIN_BW_MASK 0x01C00000L
1550#define DAGB0_WRCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L
1551#define DAGB0_WRCLI19__MAX_OSD_MASK 0xFC000000L
1552//DAGB0_WRCLI20
1553#define DAGB0_WRCLI20__VIRT_CHAN__SHIFT 0x0
1554#define DAGB0_WRCLI20__CHECK_TLB_CREDIT__SHIFT 0x3
1555#define DAGB0_WRCLI20__URG_HIGH__SHIFT 0x4
1556#define DAGB0_WRCLI20__URG_LOW__SHIFT 0x8
1557#define DAGB0_WRCLI20__MAX_BW_ENABLE__SHIFT 0xc
1558#define DAGB0_WRCLI20__MAX_BW__SHIFT 0xd
1559#define DAGB0_WRCLI20__MIN_BW_ENABLE__SHIFT 0x15
1560#define DAGB0_WRCLI20__MIN_BW__SHIFT 0x16
1561#define DAGB0_WRCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19
1562#define DAGB0_WRCLI20__MAX_OSD__SHIFT 0x1a
1563#define DAGB0_WRCLI20__VIRT_CHAN_MASK 0x00000007L
1564#define DAGB0_WRCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L
1565#define DAGB0_WRCLI20__URG_HIGH_MASK 0x000000F0L
1566#define DAGB0_WRCLI20__URG_LOW_MASK 0x00000F00L
1567#define DAGB0_WRCLI20__MAX_BW_ENABLE_MASK 0x00001000L
1568#define DAGB0_WRCLI20__MAX_BW_MASK 0x001FE000L
1569#define DAGB0_WRCLI20__MIN_BW_ENABLE_MASK 0x00200000L
1570#define DAGB0_WRCLI20__MIN_BW_MASK 0x01C00000L
1571#define DAGB0_WRCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L
1572#define DAGB0_WRCLI20__MAX_OSD_MASK 0xFC000000L
1573//DAGB0_WRCLI21
1574#define DAGB0_WRCLI21__VIRT_CHAN__SHIFT 0x0
1575#define DAGB0_WRCLI21__CHECK_TLB_CREDIT__SHIFT 0x3
1576#define DAGB0_WRCLI21__URG_HIGH__SHIFT 0x4
1577#define DAGB0_WRCLI21__URG_LOW__SHIFT 0x8
1578#define DAGB0_WRCLI21__MAX_BW_ENABLE__SHIFT 0xc
1579#define DAGB0_WRCLI21__MAX_BW__SHIFT 0xd
1580#define DAGB0_WRCLI21__MIN_BW_ENABLE__SHIFT 0x15
1581#define DAGB0_WRCLI21__MIN_BW__SHIFT 0x16
1582#define DAGB0_WRCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19
1583#define DAGB0_WRCLI21__MAX_OSD__SHIFT 0x1a
1584#define DAGB0_WRCLI21__VIRT_CHAN_MASK 0x00000007L
1585#define DAGB0_WRCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L
1586#define DAGB0_WRCLI21__URG_HIGH_MASK 0x000000F0L
1587#define DAGB0_WRCLI21__URG_LOW_MASK 0x00000F00L
1588#define DAGB0_WRCLI21__MAX_BW_ENABLE_MASK 0x00001000L
1589#define DAGB0_WRCLI21__MAX_BW_MASK 0x001FE000L
1590#define DAGB0_WRCLI21__MIN_BW_ENABLE_MASK 0x00200000L
1591#define DAGB0_WRCLI21__MIN_BW_MASK 0x01C00000L
1592#define DAGB0_WRCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L
1593#define DAGB0_WRCLI21__MAX_OSD_MASK 0xFC000000L
1594//DAGB0_WRCLI22
1595#define DAGB0_WRCLI22__VIRT_CHAN__SHIFT 0x0
1596#define DAGB0_WRCLI22__CHECK_TLB_CREDIT__SHIFT 0x3
1597#define DAGB0_WRCLI22__URG_HIGH__SHIFT 0x4
1598#define DAGB0_WRCLI22__URG_LOW__SHIFT 0x8
1599#define DAGB0_WRCLI22__MAX_BW_ENABLE__SHIFT 0xc
1600#define DAGB0_WRCLI22__MAX_BW__SHIFT 0xd
1601#define DAGB0_WRCLI22__MIN_BW_ENABLE__SHIFT 0x15
1602#define DAGB0_WRCLI22__MIN_BW__SHIFT 0x16
1603#define DAGB0_WRCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19
1604#define DAGB0_WRCLI22__MAX_OSD__SHIFT 0x1a
1605#define DAGB0_WRCLI22__VIRT_CHAN_MASK 0x00000007L
1606#define DAGB0_WRCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L
1607#define DAGB0_WRCLI22__URG_HIGH_MASK 0x000000F0L
1608#define DAGB0_WRCLI22__URG_LOW_MASK 0x00000F00L
1609#define DAGB0_WRCLI22__MAX_BW_ENABLE_MASK 0x00001000L
1610#define DAGB0_WRCLI22__MAX_BW_MASK 0x001FE000L
1611#define DAGB0_WRCLI22__MIN_BW_ENABLE_MASK 0x00200000L
1612#define DAGB0_WRCLI22__MIN_BW_MASK 0x01C00000L
1613#define DAGB0_WRCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L
1614#define DAGB0_WRCLI22__MAX_OSD_MASK 0xFC000000L
1615//DAGB0_WRCLI23
1616#define DAGB0_WRCLI23__VIRT_CHAN__SHIFT 0x0
1617#define DAGB0_WRCLI23__CHECK_TLB_CREDIT__SHIFT 0x3
1618#define DAGB0_WRCLI23__URG_HIGH__SHIFT 0x4
1619#define DAGB0_WRCLI23__URG_LOW__SHIFT 0x8
1620#define DAGB0_WRCLI23__MAX_BW_ENABLE__SHIFT 0xc
1621#define DAGB0_WRCLI23__MAX_BW__SHIFT 0xd
1622#define DAGB0_WRCLI23__MIN_BW_ENABLE__SHIFT 0x15
1623#define DAGB0_WRCLI23__MIN_BW__SHIFT 0x16
1624#define DAGB0_WRCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19
1625#define DAGB0_WRCLI23__MAX_OSD__SHIFT 0x1a
1626#define DAGB0_WRCLI23__VIRT_CHAN_MASK 0x00000007L
1627#define DAGB0_WRCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L
1628#define DAGB0_WRCLI23__URG_HIGH_MASK 0x000000F0L
1629#define DAGB0_WRCLI23__URG_LOW_MASK 0x00000F00L
1630#define DAGB0_WRCLI23__MAX_BW_ENABLE_MASK 0x00001000L
1631#define DAGB0_WRCLI23__MAX_BW_MASK 0x001FE000L
1632#define DAGB0_WRCLI23__MIN_BW_ENABLE_MASK 0x00200000L
1633#define DAGB0_WRCLI23__MIN_BW_MASK 0x01C00000L
1634#define DAGB0_WRCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L
1635#define DAGB0_WRCLI23__MAX_OSD_MASK 0xFC000000L
1636//DAGB0_WRCLI24
1637#define DAGB0_WRCLI24__VIRT_CHAN__SHIFT 0x0
1638#define DAGB0_WRCLI24__CHECK_TLB_CREDIT__SHIFT 0x3
1639#define DAGB0_WRCLI24__URG_HIGH__SHIFT 0x4
1640#define DAGB0_WRCLI24__URG_LOW__SHIFT 0x8
1641#define DAGB0_WRCLI24__MAX_BW_ENABLE__SHIFT 0xc
1642#define DAGB0_WRCLI24__MAX_BW__SHIFT 0xd
1643#define DAGB0_WRCLI24__MIN_BW_ENABLE__SHIFT 0x15
1644#define DAGB0_WRCLI24__MIN_BW__SHIFT 0x16
1645#define DAGB0_WRCLI24__OSD_LIMITER_ENABLE__SHIFT 0x19
1646#define DAGB0_WRCLI24__MAX_OSD__SHIFT 0x1a
1647#define DAGB0_WRCLI24__VIRT_CHAN_MASK 0x00000007L
1648#define DAGB0_WRCLI24__CHECK_TLB_CREDIT_MASK 0x00000008L
1649#define DAGB0_WRCLI24__URG_HIGH_MASK 0x000000F0L
1650#define DAGB0_WRCLI24__URG_LOW_MASK 0x00000F00L
1651#define DAGB0_WRCLI24__MAX_BW_ENABLE_MASK 0x00001000L
1652#define DAGB0_WRCLI24__MAX_BW_MASK 0x001FE000L
1653#define DAGB0_WRCLI24__MIN_BW_ENABLE_MASK 0x00200000L
1654#define DAGB0_WRCLI24__MIN_BW_MASK 0x01C00000L
1655#define DAGB0_WRCLI24__OSD_LIMITER_ENABLE_MASK 0x02000000L
1656#define DAGB0_WRCLI24__MAX_OSD_MASK 0xFC000000L
1657//DAGB0_WRCLI25
1658#define DAGB0_WRCLI25__VIRT_CHAN__SHIFT 0x0
1659#define DAGB0_WRCLI25__CHECK_TLB_CREDIT__SHIFT 0x3
1660#define DAGB0_WRCLI25__URG_HIGH__SHIFT 0x4
1661#define DAGB0_WRCLI25__URG_LOW__SHIFT 0x8
1662#define DAGB0_WRCLI25__MAX_BW_ENABLE__SHIFT 0xc
1663#define DAGB0_WRCLI25__MAX_BW__SHIFT 0xd
1664#define DAGB0_WRCLI25__MIN_BW_ENABLE__SHIFT 0x15
1665#define DAGB0_WRCLI25__MIN_BW__SHIFT 0x16
1666#define DAGB0_WRCLI25__OSD_LIMITER_ENABLE__SHIFT 0x19
1667#define DAGB0_WRCLI25__MAX_OSD__SHIFT 0x1a
1668#define DAGB0_WRCLI25__VIRT_CHAN_MASK 0x00000007L
1669#define DAGB0_WRCLI25__CHECK_TLB_CREDIT_MASK 0x00000008L
1670#define DAGB0_WRCLI25__URG_HIGH_MASK 0x000000F0L
1671#define DAGB0_WRCLI25__URG_LOW_MASK 0x00000F00L
1672#define DAGB0_WRCLI25__MAX_BW_ENABLE_MASK 0x00001000L
1673#define DAGB0_WRCLI25__MAX_BW_MASK 0x001FE000L
1674#define DAGB0_WRCLI25__MIN_BW_ENABLE_MASK 0x00200000L
1675#define DAGB0_WRCLI25__MIN_BW_MASK 0x01C00000L
1676#define DAGB0_WRCLI25__OSD_LIMITER_ENABLE_MASK 0x02000000L
1677#define DAGB0_WRCLI25__MAX_OSD_MASK 0xFC000000L
1678//DAGB0_WRCLI26
1679#define DAGB0_WRCLI26__VIRT_CHAN__SHIFT 0x0
1680#define DAGB0_WRCLI26__CHECK_TLB_CREDIT__SHIFT 0x3
1681#define DAGB0_WRCLI26__URG_HIGH__SHIFT 0x4
1682#define DAGB0_WRCLI26__URG_LOW__SHIFT 0x8
1683#define DAGB0_WRCLI26__MAX_BW_ENABLE__SHIFT 0xc
1684#define DAGB0_WRCLI26__MAX_BW__SHIFT 0xd
1685#define DAGB0_WRCLI26__MIN_BW_ENABLE__SHIFT 0x15
1686#define DAGB0_WRCLI26__MIN_BW__SHIFT 0x16
1687#define DAGB0_WRCLI26__OSD_LIMITER_ENABLE__SHIFT 0x19
1688#define DAGB0_WRCLI26__MAX_OSD__SHIFT 0x1a
1689#define DAGB0_WRCLI26__VIRT_CHAN_MASK 0x00000007L
1690#define DAGB0_WRCLI26__CHECK_TLB_CREDIT_MASK 0x00000008L
1691#define DAGB0_WRCLI26__URG_HIGH_MASK 0x000000F0L
1692#define DAGB0_WRCLI26__URG_LOW_MASK 0x00000F00L
1693#define DAGB0_WRCLI26__MAX_BW_ENABLE_MASK 0x00001000L
1694#define DAGB0_WRCLI26__MAX_BW_MASK 0x001FE000L
1695#define DAGB0_WRCLI26__MIN_BW_ENABLE_MASK 0x00200000L
1696#define DAGB0_WRCLI26__MIN_BW_MASK 0x01C00000L
1697#define DAGB0_WRCLI26__OSD_LIMITER_ENABLE_MASK 0x02000000L
1698#define DAGB0_WRCLI26__MAX_OSD_MASK 0xFC000000L
1699//DAGB0_WRCLI27
1700#define DAGB0_WRCLI27__VIRT_CHAN__SHIFT 0x0
1701#define DAGB0_WRCLI27__CHECK_TLB_CREDIT__SHIFT 0x3
1702#define DAGB0_WRCLI27__URG_HIGH__SHIFT 0x4
1703#define DAGB0_WRCLI27__URG_LOW__SHIFT 0x8
1704#define DAGB0_WRCLI27__MAX_BW_ENABLE__SHIFT 0xc
1705#define DAGB0_WRCLI27__MAX_BW__SHIFT 0xd
1706#define DAGB0_WRCLI27__MIN_BW_ENABLE__SHIFT 0x15
1707#define DAGB0_WRCLI27__MIN_BW__SHIFT 0x16
1708#define DAGB0_WRCLI27__OSD_LIMITER_ENABLE__SHIFT 0x19
1709#define DAGB0_WRCLI27__MAX_OSD__SHIFT 0x1a
1710#define DAGB0_WRCLI27__VIRT_CHAN_MASK 0x00000007L
1711#define DAGB0_WRCLI27__CHECK_TLB_CREDIT_MASK 0x00000008L
1712#define DAGB0_WRCLI27__URG_HIGH_MASK 0x000000F0L
1713#define DAGB0_WRCLI27__URG_LOW_MASK 0x00000F00L
1714#define DAGB0_WRCLI27__MAX_BW_ENABLE_MASK 0x00001000L
1715#define DAGB0_WRCLI27__MAX_BW_MASK 0x001FE000L
1716#define DAGB0_WRCLI27__MIN_BW_ENABLE_MASK 0x00200000L
1717#define DAGB0_WRCLI27__MIN_BW_MASK 0x01C00000L
1718#define DAGB0_WRCLI27__OSD_LIMITER_ENABLE_MASK 0x02000000L
1719#define DAGB0_WRCLI27__MAX_OSD_MASK 0xFC000000L
1720//DAGB0_WRCLI28
1721#define DAGB0_WRCLI28__VIRT_CHAN__SHIFT 0x0
1722#define DAGB0_WRCLI28__CHECK_TLB_CREDIT__SHIFT 0x3
1723#define DAGB0_WRCLI28__URG_HIGH__SHIFT 0x4
1724#define DAGB0_WRCLI28__URG_LOW__SHIFT 0x8
1725#define DAGB0_WRCLI28__MAX_BW_ENABLE__SHIFT 0xc
1726#define DAGB0_WRCLI28__MAX_BW__SHIFT 0xd
1727#define DAGB0_WRCLI28__MIN_BW_ENABLE__SHIFT 0x15
1728#define DAGB0_WRCLI28__MIN_BW__SHIFT 0x16
1729#define DAGB0_WRCLI28__OSD_LIMITER_ENABLE__SHIFT 0x19
1730#define DAGB0_WRCLI28__MAX_OSD__SHIFT 0x1a
1731#define DAGB0_WRCLI28__VIRT_CHAN_MASK 0x00000007L
1732#define DAGB0_WRCLI28__CHECK_TLB_CREDIT_MASK 0x00000008L
1733#define DAGB0_WRCLI28__URG_HIGH_MASK 0x000000F0L
1734#define DAGB0_WRCLI28__URG_LOW_MASK 0x00000F00L
1735#define DAGB0_WRCLI28__MAX_BW_ENABLE_MASK 0x00001000L
1736#define DAGB0_WRCLI28__MAX_BW_MASK 0x001FE000L
1737#define DAGB0_WRCLI28__MIN_BW_ENABLE_MASK 0x00200000L
1738#define DAGB0_WRCLI28__MIN_BW_MASK 0x01C00000L
1739#define DAGB0_WRCLI28__OSD_LIMITER_ENABLE_MASK 0x02000000L
1740#define DAGB0_WRCLI28__MAX_OSD_MASK 0xFC000000L
1741//DAGB0_WRCLI29
1742#define DAGB0_WRCLI29__VIRT_CHAN__SHIFT 0x0
1743#define DAGB0_WRCLI29__CHECK_TLB_CREDIT__SHIFT 0x3
1744#define DAGB0_WRCLI29__URG_HIGH__SHIFT 0x4
1745#define DAGB0_WRCLI29__URG_LOW__SHIFT 0x8
1746#define DAGB0_WRCLI29__MAX_BW_ENABLE__SHIFT 0xc
1747#define DAGB0_WRCLI29__MAX_BW__SHIFT 0xd
1748#define DAGB0_WRCLI29__MIN_BW_ENABLE__SHIFT 0x15
1749#define DAGB0_WRCLI29__MIN_BW__SHIFT 0x16
1750#define DAGB0_WRCLI29__OSD_LIMITER_ENABLE__SHIFT 0x19
1751#define DAGB0_WRCLI29__MAX_OSD__SHIFT 0x1a
1752#define DAGB0_WRCLI29__VIRT_CHAN_MASK 0x00000007L
1753#define DAGB0_WRCLI29__CHECK_TLB_CREDIT_MASK 0x00000008L
1754#define DAGB0_WRCLI29__URG_HIGH_MASK 0x000000F0L
1755#define DAGB0_WRCLI29__URG_LOW_MASK 0x00000F00L
1756#define DAGB0_WRCLI29__MAX_BW_ENABLE_MASK 0x00001000L
1757#define DAGB0_WRCLI29__MAX_BW_MASK 0x001FE000L
1758#define DAGB0_WRCLI29__MIN_BW_ENABLE_MASK 0x00200000L
1759#define DAGB0_WRCLI29__MIN_BW_MASK 0x01C00000L
1760#define DAGB0_WRCLI29__OSD_LIMITER_ENABLE_MASK 0x02000000L
1761#define DAGB0_WRCLI29__MAX_OSD_MASK 0xFC000000L
1762//DAGB0_WRCLI30
1763#define DAGB0_WRCLI30__VIRT_CHAN__SHIFT 0x0
1764#define DAGB0_WRCLI30__CHECK_TLB_CREDIT__SHIFT 0x3
1765#define DAGB0_WRCLI30__URG_HIGH__SHIFT 0x4
1766#define DAGB0_WRCLI30__URG_LOW__SHIFT 0x8
1767#define DAGB0_WRCLI30__MAX_BW_ENABLE__SHIFT 0xc
1768#define DAGB0_WRCLI30__MAX_BW__SHIFT 0xd
1769#define DAGB0_WRCLI30__MIN_BW_ENABLE__SHIFT 0x15
1770#define DAGB0_WRCLI30__MIN_BW__SHIFT 0x16
1771#define DAGB0_WRCLI30__OSD_LIMITER_ENABLE__SHIFT 0x19
1772#define DAGB0_WRCLI30__MAX_OSD__SHIFT 0x1a
1773#define DAGB0_WRCLI30__VIRT_CHAN_MASK 0x00000007L
1774#define DAGB0_WRCLI30__CHECK_TLB_CREDIT_MASK 0x00000008L
1775#define DAGB0_WRCLI30__URG_HIGH_MASK 0x000000F0L
1776#define DAGB0_WRCLI30__URG_LOW_MASK 0x00000F00L
1777#define DAGB0_WRCLI30__MAX_BW_ENABLE_MASK 0x00001000L
1778#define DAGB0_WRCLI30__MAX_BW_MASK 0x001FE000L
1779#define DAGB0_WRCLI30__MIN_BW_ENABLE_MASK 0x00200000L
1780#define DAGB0_WRCLI30__MIN_BW_MASK 0x01C00000L
1781#define DAGB0_WRCLI30__OSD_LIMITER_ENABLE_MASK 0x02000000L
1782#define DAGB0_WRCLI30__MAX_OSD_MASK 0xFC000000L
1783//DAGB0_WRCLI31
1784#define DAGB0_WRCLI31__VIRT_CHAN__SHIFT 0x0
1785#define DAGB0_WRCLI31__CHECK_TLB_CREDIT__SHIFT 0x3
1786#define DAGB0_WRCLI31__URG_HIGH__SHIFT 0x4
1787#define DAGB0_WRCLI31__URG_LOW__SHIFT 0x8
1788#define DAGB0_WRCLI31__MAX_BW_ENABLE__SHIFT 0xc
1789#define DAGB0_WRCLI31__MAX_BW__SHIFT 0xd
1790#define DAGB0_WRCLI31__MIN_BW_ENABLE__SHIFT 0x15
1791#define DAGB0_WRCLI31__MIN_BW__SHIFT 0x16
1792#define DAGB0_WRCLI31__OSD_LIMITER_ENABLE__SHIFT 0x19
1793#define DAGB0_WRCLI31__MAX_OSD__SHIFT 0x1a
1794#define DAGB0_WRCLI31__VIRT_CHAN_MASK 0x00000007L
1795#define DAGB0_WRCLI31__CHECK_TLB_CREDIT_MASK 0x00000008L
1796#define DAGB0_WRCLI31__URG_HIGH_MASK 0x000000F0L
1797#define DAGB0_WRCLI31__URG_LOW_MASK 0x00000F00L
1798#define DAGB0_WRCLI31__MAX_BW_ENABLE_MASK 0x00001000L
1799#define DAGB0_WRCLI31__MAX_BW_MASK 0x001FE000L
1800#define DAGB0_WRCLI31__MIN_BW_ENABLE_MASK 0x00200000L
1801#define DAGB0_WRCLI31__MIN_BW_MASK 0x01C00000L
1802#define DAGB0_WRCLI31__OSD_LIMITER_ENABLE_MASK 0x02000000L
1803#define DAGB0_WRCLI31__MAX_OSD_MASK 0xFC000000L
1804//DAGB0_WR_CNTL
1805#define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT 0x0
1806#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
1807#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
1808#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
1809#define DAGB0_WR_CNTL__IO_LEVEL__SHIFT 0x11
1810#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
1811#define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17
1812#define DAGB0_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL
1813#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
1814#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
1815#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
1816#define DAGB0_WR_CNTL__IO_LEVEL_MASK 0x000E0000L
1817#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
1818#define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L
1819//DAGB0_WR_GMI_CNTL
1820#define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0
1821#define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT 0x6
1822#define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9
1823#define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
1824#define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
1825#define DAGB0_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L
1826#define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
1827#define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
1828//DAGB0_WR_ADDR_DAGB
1829#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
1830#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
1831#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
1832#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7
1833#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
1834#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
1835#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
1836#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
1837//DAGB0_WR_OUTPUT_DAGB_MAX_BURST
1838#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
1839#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
1840#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
1841#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
1842#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
1843#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
1844#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
1845#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
1846#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
1847#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
1848#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
1849#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
1850#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
1851#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
1852#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
1853#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
1854//DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER
1855#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
1856#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
1857#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
1858#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
1859#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
1860#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
1861#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
1862#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
1863#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
1864#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
1865#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
1866#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
1867#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
1868#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
1869#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
1870#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
1871//DAGB0_WR_CGTT_CLK_CTRL
1872#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
1873#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
1874#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
1875#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
1876#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
1877#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
1878#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
1879#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
1880#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
1881#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
1882#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
1883#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
1884#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
1885#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
1886#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
1887#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
1888//DAGB0_L1TLB_WR_CGTT_CLK_CTRL
1889#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
1890#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
1891#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
1892#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
1893#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
1894#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
1895#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
1896#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
1897#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
1898#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
1899#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
1900#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
1901#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
1902#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
1903#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
1904#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
1905//DAGB0_ATCVM_WR_CGTT_CLK_CTRL
1906#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
1907#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
1908#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
1909#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
1910#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
1911#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
1912#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
1913#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
1914#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
1915#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
1916#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
1917#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
1918#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
1919#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
1920#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
1921#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
1922//DAGB0_WR_ADDR_DAGB_MAX_BURST0
1923#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
1924#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
1925#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
1926#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
1927#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
1928#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
1929#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
1930#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
1931#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
1932#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
1933#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
1934#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
1935#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
1936#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
1937#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
1938#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
1939//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0
1940#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
1941#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
1942#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
1943#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
1944#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
1945#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
1946#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
1947#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
1948#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
1949#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
1950#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
1951#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
1952#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
1953#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
1954#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
1955#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
1956//DAGB0_WR_ADDR_DAGB_MAX_BURST1
1957#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
1958#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
1959#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
1960#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
1961#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
1962#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
1963#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
1964#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
1965#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
1966#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
1967#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
1968#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
1969#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
1970#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
1971#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
1972#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
1973//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1
1974#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
1975#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
1976#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
1977#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
1978#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
1979#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
1980#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
1981#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
1982#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
1983#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
1984#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
1985#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
1986#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
1987#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
1988#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
1989#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
1990//DAGB0_WR_ADDR_DAGB_MAX_BURST2
1991#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0
1992#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4
1993#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8
1994#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc
1995#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10
1996#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14
1997#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18
1998#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c
1999#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL
2000#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L
2001#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L
2002#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L
2003#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L
2004#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L
2005#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L
2006#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L
2007//DAGB0_WR_ADDR_DAGB_LAZY_TIMER2
2008#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0
2009#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4
2010#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8
2011#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc
2012#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10
2013#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14
2014#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18
2015#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c
2016#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL
2017#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L
2018#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L
2019#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L
2020#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L
2021#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L
2022#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L
2023#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L
2024//DAGB0_WR_ADDR_DAGB_MAX_BURST3
2025#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0
2026#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4
2027#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8
2028#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc
2029#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10
2030#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14
2031#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18
2032#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c
2033#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL
2034#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L
2035#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L
2036#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L
2037#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L
2038#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L
2039#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L
2040#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L
2041//DAGB0_WR_ADDR_DAGB_LAZY_TIMER3
2042#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0
2043#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4
2044#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8
2045#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc
2046#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10
2047#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14
2048#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18
2049#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c
2050#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL
2051#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L
2052#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L
2053#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L
2054#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L
2055#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L
2056#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L
2057#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L
2058//DAGB0_WR_DATA_DAGB
2059#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0
2060#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
2061#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
2062#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7
2063#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L
2064#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
2065#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
2066#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L
2067//DAGB0_WR_DATA_DAGB_MAX_BURST0
2068#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
2069#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
2070#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
2071#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
2072#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
2073#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
2074#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
2075#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
2076#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
2077#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
2078#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
2079#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
2080#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
2081#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
2082#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
2083#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
2084//DAGB0_WR_DATA_DAGB_LAZY_TIMER0
2085#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
2086#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
2087#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
2088#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
2089#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
2090#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
2091#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
2092#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
2093#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
2094#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
2095#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
2096#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
2097#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
2098#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
2099#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
2100#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
2101//DAGB0_WR_DATA_DAGB_MAX_BURST1
2102#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
2103#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
2104#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
2105#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
2106#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
2107#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
2108#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
2109#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
2110#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
2111#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
2112#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
2113#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
2114#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
2115#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
2116#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
2117#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
2118//DAGB0_WR_DATA_DAGB_LAZY_TIMER1
2119#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
2120#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
2121#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
2122#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
2123#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
2124#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
2125#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
2126#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
2127#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
2128#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
2129#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
2130#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
2131#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
2132#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
2133#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
2134#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
2135//DAGB0_WR_DATA_DAGB_MAX_BURST2
2136#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0
2137#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4
2138#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8
2139#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc
2140#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10
2141#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14
2142#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18
2143#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c
2144#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL
2145#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L
2146#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L
2147#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L
2148#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L
2149#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L
2150#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L
2151#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L
2152//DAGB0_WR_DATA_DAGB_LAZY_TIMER2
2153#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0
2154#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4
2155#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8
2156#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc
2157#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10
2158#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14
2159#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18
2160#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c
2161#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL
2162#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L
2163#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L
2164#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L
2165#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L
2166#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L
2167#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L
2168#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L
2169//DAGB0_WR_DATA_DAGB_MAX_BURST3
2170#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0
2171#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4
2172#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8
2173#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc
2174#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10
2175#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14
2176#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18
2177#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c
2178#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL
2179#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L
2180#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L
2181#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L
2182#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L
2183#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L
2184#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L
2185#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L
2186//DAGB0_WR_DATA_DAGB_LAZY_TIMER3
2187#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0
2188#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4
2189#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8
2190#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc
2191#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10
2192#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14
2193#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18
2194#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c
2195#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL
2196#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L
2197#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L
2198#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L
2199#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L
2200#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L
2201#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L
2202#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L
2203//DAGB0_WR_VC0_CNTL
2204#define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
2205#define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5
2206#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
2207#define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc
2208#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
2209#define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15
2210#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
2211#define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19
2212#define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
2213#define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
2214#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
2215#define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L
2216#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
2217#define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L
2218#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
2219#define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
2220//DAGB0_WR_VC1_CNTL
2221#define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
2222#define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5
2223#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
2224#define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc
2225#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
2226#define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15
2227#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
2228#define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19
2229#define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
2230#define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
2231#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
2232#define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L
2233#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
2234#define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L
2235#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
2236#define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
2237//DAGB0_WR_VC2_CNTL
2238#define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
2239#define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5
2240#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
2241#define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc
2242#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
2243#define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15
2244#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
2245#define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19
2246#define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
2247#define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
2248#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
2249#define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L
2250#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
2251#define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L
2252#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
2253#define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
2254//DAGB0_WR_VC3_CNTL
2255#define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
2256#define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5
2257#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
2258#define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc
2259#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
2260#define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15
2261#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
2262#define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19
2263#define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
2264#define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
2265#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
2266#define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L
2267#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
2268#define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L
2269#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
2270#define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
2271//DAGB0_WR_VC4_CNTL
2272#define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
2273#define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5
2274#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
2275#define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc
2276#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
2277#define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15
2278#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
2279#define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19
2280#define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
2281#define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
2282#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
2283#define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L
2284#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
2285#define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L
2286#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
2287#define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
2288//DAGB0_WR_VC5_CNTL
2289#define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
2290#define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5
2291#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
2292#define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc
2293#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
2294#define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15
2295#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
2296#define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19
2297#define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
2298#define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
2299#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
2300#define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L
2301#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
2302#define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L
2303#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
2304#define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
2305//DAGB0_WR_VC6_CNTL
2306#define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
2307#define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5
2308#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
2309#define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT 0xc
2310#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
2311#define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT 0x15
2312#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
2313#define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19
2314#define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
2315#define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
2316#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
2317#define DAGB0_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L
2318#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
2319#define DAGB0_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L
2320#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
2321#define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
2322//DAGB0_WR_VC7_CNTL
2323#define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
2324#define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5
2325#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
2326#define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT 0xc
2327#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
2328#define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT 0x15
2329#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
2330#define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19
2331#define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
2332#define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
2333#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
2334#define DAGB0_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L
2335#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
2336#define DAGB0_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L
2337#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
2338#define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
2339//DAGB0_WR_CNTL_MISC
2340#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
2341#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
2342#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
2343#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
2344#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
2345#define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15
2346#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
2347#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
2348#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
2349#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
2350#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
2351#define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
2352//DAGB0_WR_TLB_CREDIT
2353#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0
2354#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5
2355#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa
2356#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf
2357#define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14
2358#define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19
2359#define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL
2360#define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L
2361#define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L
2362#define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L
2363#define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L
2364#define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L
2365//DAGB0_WR_DATA_CREDIT
2366#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0
2367#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8
2368#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10
2369#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18
2370#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL
2371#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L
2372#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L
2373#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L
2374//DAGB0_WR_MISC_CREDIT
2375#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0
2376#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6
2377#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9
2378#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10
2379#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL
2380#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L
2381#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L
2382#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L
2383//DAGB0_WRCLI_ASK_PENDING
2384#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0
2385#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
2386//DAGB0_WRCLI_GO_PENDING
2387#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0
2388#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
2389//DAGB0_WRCLI_GBLSEND_PENDING
2390#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
2391#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
2392//DAGB0_WRCLI_TLB_PENDING
2393#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0
2394#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
2395//DAGB0_WRCLI_OARB_PENDING
2396#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0
2397#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
2398//DAGB0_WRCLI_OSD_PENDING
2399#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0
2400#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
2401//DAGB0_WRCLI_DBUS_ASK_PENDING
2402#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0
2403#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
2404//DAGB0_WRCLI_DBUS_GO_PENDING
2405#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0
2406#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
2407//DAGB0_DAGB_DLY
2408#define DAGB0_DAGB_DLY__DLY__SHIFT 0x0
2409#define DAGB0_DAGB_DLY__CLI__SHIFT 0x8
2410#define DAGB0_DAGB_DLY__POS__SHIFT 0x10
2411#define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL
2412#define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L
2413#define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L
2414//DAGB0_CNTL_MISC
2415#define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0
2416#define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3
2417#define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6
2418#define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9
2419#define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc
2420#define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf
2421#define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12
2422#define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15
2423#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18
2424#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e
2425#define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L
2426#define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L
2427#define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L
2428#define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L
2429#define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L
2430#define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L
2431#define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L
2432#define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L
2433#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L
2434#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L
2435//DAGB0_CNTL_MISC2
2436#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0
2437#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1
2438#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2
2439#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3
2440#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4
2441#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5
2442#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6
2443#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7
2444#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8
2445#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9
2446#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa
2447#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L
2448#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L
2449#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L
2450#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L
2451#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L
2452#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L
2453#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L
2454#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L
2455#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L
2456#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L
2457#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L
2458//DAGB0_FIFO_EMPTY
2459#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0
2460#define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL
2461//DAGB0_FIFO_FULL
2462#define DAGB0_FIFO_FULL__FULL__SHIFT 0x0
2463#define DAGB0_FIFO_FULL__FULL_MASK 0x007FFFFFL
2464//DAGB0_WR_CREDITS_FULL
2465#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0
2466#define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0007FFFFL
2467//DAGB0_RD_CREDITS_FULL
2468#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0
2469#define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL
2470//DAGB0_PERFCOUNTER_LO
2471#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
2472#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
2473//DAGB0_PERFCOUNTER_HI
2474#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
2475#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
2476#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
2477#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
2478//DAGB0_PERFCOUNTER0_CFG
2479#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
2480#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
2481#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
2482#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
2483#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
2484#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
2485#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
2486#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
2487#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
2488#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
2489//DAGB0_PERFCOUNTER1_CFG
2490#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
2491#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
2492#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
2493#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
2494#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
2495#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
2496#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
2497#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
2498#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
2499#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
2500//DAGB0_PERFCOUNTER2_CFG
2501#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
2502#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
2503#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
2504#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
2505#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
2506#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
2507#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
2508#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
2509#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
2510#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
2511//DAGB0_PERFCOUNTER_RSLT_CNTL
2512#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
2513#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
2514#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
2515#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
2516#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
2517#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
2518#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
2519#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
2520#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
2521#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
2522#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
2523#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
2524//DAGB0_RESERVE0
2525#define DAGB0_RESERVE0__RESERVE__SHIFT 0x0
2526#define DAGB0_RESERVE0__RESERVE_MASK 0xFFFFFFFFL
2527//DAGB0_RESERVE1
2528#define DAGB0_RESERVE1__RESERVE__SHIFT 0x0
2529#define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL
2530//DAGB0_RESERVE2
2531#define DAGB0_RESERVE2__RESERVE__SHIFT 0x0
2532#define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL
2533//DAGB0_RESERVE3
2534#define DAGB0_RESERVE3__RESERVE__SHIFT 0x0
2535#define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL
2536//DAGB0_RESERVE4
2537#define DAGB0_RESERVE4__RESERVE__SHIFT 0x0
2538#define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL
2539//DAGB0_RESERVE5
2540#define DAGB0_RESERVE5__RESERVE__SHIFT 0x0
2541#define DAGB0_RESERVE5__RESERVE_MASK 0xFFFFFFFFL
2542//DAGB0_RESERVE6
2543#define DAGB0_RESERVE6__RESERVE__SHIFT 0x0
2544#define DAGB0_RESERVE6__RESERVE_MASK 0xFFFFFFFFL
2545//DAGB0_RESERVE7
2546#define DAGB0_RESERVE7__RESERVE__SHIFT 0x0
2547#define DAGB0_RESERVE7__RESERVE_MASK 0xFFFFFFFFL
2548//DAGB0_RESERVE8
2549#define DAGB0_RESERVE8__RESERVE__SHIFT 0x0
2550#define DAGB0_RESERVE8__RESERVE_MASK 0xFFFFFFFFL
2551//DAGB0_RESERVE9
2552#define DAGB0_RESERVE9__RESERVE__SHIFT 0x0
2553#define DAGB0_RESERVE9__RESERVE_MASK 0xFFFFFFFFL
2554//DAGB0_RESERVE10
2555#define DAGB0_RESERVE10__RESERVE__SHIFT 0x0
2556#define DAGB0_RESERVE10__RESERVE_MASK 0xFFFFFFFFL
2557//DAGB0_RESERVE11
2558#define DAGB0_RESERVE11__RESERVE__SHIFT 0x0
2559#define DAGB0_RESERVE11__RESERVE_MASK 0xFFFFFFFFL
2560//DAGB0_RESERVE12
2561#define DAGB0_RESERVE12__RESERVE__SHIFT 0x0
2562#define DAGB0_RESERVE12__RESERVE_MASK 0xFFFFFFFFL
2563//DAGB0_RESERVE13
2564#define DAGB0_RESERVE13__RESERVE__SHIFT 0x0
2565#define DAGB0_RESERVE13__RESERVE_MASK 0xFFFFFFFFL
2566//DAGB0_RESERVE14
2567#define DAGB0_RESERVE14__RESERVE__SHIFT 0x0
2568#define DAGB0_RESERVE14__RESERVE_MASK 0xFFFFFFFFL
2569//DAGB0_RESERVE15
2570#define DAGB0_RESERVE15__RESERVE__SHIFT 0x0
2571#define DAGB0_RESERVE15__RESERVE_MASK 0xFFFFFFFFL
2572//DAGB0_RESERVE16
2573#define DAGB0_RESERVE16__RESERVE__SHIFT 0x0
2574#define DAGB0_RESERVE16__RESERVE_MASK 0xFFFFFFFFL
2575//DAGB0_RESERVE17
2576#define DAGB0_RESERVE17__RESERVE__SHIFT 0x0
2577#define DAGB0_RESERVE17__RESERVE_MASK 0xFFFFFFFFL
2578//DAGB0_RESERVE18
2579#define DAGB0_RESERVE18__RESERVE__SHIFT 0x0
2580#define DAGB0_RESERVE18__RESERVE_MASK 0xFFFFFFFFL
2581//DAGB0_RESERVE19
2582#define DAGB0_RESERVE19__RESERVE__SHIFT 0x0
2583#define DAGB0_RESERVE19__RESERVE_MASK 0xFFFFFFFFL
2584//DAGB0_RESERVE20
2585#define DAGB0_RESERVE20__RESERVE__SHIFT 0x0
2586#define DAGB0_RESERVE20__RESERVE_MASK 0xFFFFFFFFL
2587//DAGB0_RESERVE21
2588#define DAGB0_RESERVE21__RESERVE__SHIFT 0x0
2589#define DAGB0_RESERVE21__RESERVE_MASK 0xFFFFFFFFL
2590//DAGB0_RESERVE22
2591#define DAGB0_RESERVE22__RESERVE__SHIFT 0x0
2592#define DAGB0_RESERVE22__RESERVE_MASK 0xFFFFFFFFL
2593//DAGB0_RESERVE23
2594#define DAGB0_RESERVE23__RESERVE__SHIFT 0x0
2595#define DAGB0_RESERVE23__RESERVE_MASK 0xFFFFFFFFL
2596//DAGB0_RESERVE24
2597#define DAGB0_RESERVE24__RESERVE__SHIFT 0x0
2598#define DAGB0_RESERVE24__RESERVE_MASK 0xFFFFFFFFL
2599//DAGB0_RESERVE25
2600#define DAGB0_RESERVE25__RESERVE__SHIFT 0x0
2601#define DAGB0_RESERVE25__RESERVE_MASK 0xFFFFFFFFL
2602//DAGB0_RESERVE26
2603#define DAGB0_RESERVE26__RESERVE__SHIFT 0x0
2604#define DAGB0_RESERVE26__RESERVE_MASK 0xFFFFFFFFL
2605//DAGB0_RESERVE27
2606#define DAGB0_RESERVE27__RESERVE__SHIFT 0x0
2607#define DAGB0_RESERVE27__RESERVE_MASK 0xFFFFFFFFL
2608//DAGB0_RESERVE28
2609#define DAGB0_RESERVE28__RESERVE__SHIFT 0x0
2610#define DAGB0_RESERVE28__RESERVE_MASK 0xFFFFFFFFL
2611//DAGB0_RESERVE29
2612#define DAGB0_RESERVE29__RESERVE__SHIFT 0x0
2613#define DAGB0_RESERVE29__RESERVE_MASK 0xFFFFFFFFL
2614//DAGB0_RESERVE30
2615#define DAGB0_RESERVE30__RESERVE__SHIFT 0x0
2616#define DAGB0_RESERVE30__RESERVE_MASK 0xFFFFFFFFL
2617//DAGB0_RESERVE31
2618#define DAGB0_RESERVE31__RESERVE__SHIFT 0x0
2619#define DAGB0_RESERVE31__RESERVE_MASK 0xFFFFFFFFL
2620//DAGB0_RESERVE32
2621#define DAGB0_RESERVE32__RESERVE__SHIFT 0x0
2622#define DAGB0_RESERVE32__RESERVE_MASK 0xFFFFFFFFL
2623//DAGB0_RESERVE33
2624#define DAGB0_RESERVE33__RESERVE__SHIFT 0x0
2625#define DAGB0_RESERVE33__RESERVE_MASK 0xFFFFFFFFL
2626//DAGB0_RESERVE34
2627#define DAGB0_RESERVE34__RESERVE__SHIFT 0x0
2628#define DAGB0_RESERVE34__RESERVE_MASK 0xFFFFFFFFL
2629//DAGB0_RESERVE35
2630#define DAGB0_RESERVE35__RESERVE__SHIFT 0x0
2631#define DAGB0_RESERVE35__RESERVE_MASK 0xFFFFFFFFL
2632//DAGB0_RESERVE36
2633#define DAGB0_RESERVE36__RESERVE__SHIFT 0x0
2634#define DAGB0_RESERVE36__RESERVE_MASK 0xFFFFFFFFL
2635//DAGB0_RESERVE37
2636#define DAGB0_RESERVE37__RESERVE__SHIFT 0x0
2637#define DAGB0_RESERVE37__RESERVE_MASK 0xFFFFFFFFL
2638//DAGB0_RESERVE38
2639#define DAGB0_RESERVE38__RESERVE__SHIFT 0x0
2640#define DAGB0_RESERVE38__RESERVE_MASK 0xFFFFFFFFL
2641//DAGB0_RESERVE39
2642#define DAGB0_RESERVE39__RESERVE__SHIFT 0x0
2643#define DAGB0_RESERVE39__RESERVE_MASK 0xFFFFFFFFL
2644//DAGB0_RESERVE40
2645#define DAGB0_RESERVE40__RESERVE__SHIFT 0x0
2646#define DAGB0_RESERVE40__RESERVE_MASK 0xFFFFFFFFL
2647//DAGB0_RESERVE41
2648#define DAGB0_RESERVE41__RESERVE__SHIFT 0x0
2649#define DAGB0_RESERVE41__RESERVE_MASK 0xFFFFFFFFL
2650//DAGB0_RESERVE42
2651#define DAGB0_RESERVE42__RESERVE__SHIFT 0x0
2652#define DAGB0_RESERVE42__RESERVE_MASK 0xFFFFFFFFL
2653//DAGB0_RESERVE43
2654#define DAGB0_RESERVE43__RESERVE__SHIFT 0x0
2655#define DAGB0_RESERVE43__RESERVE_MASK 0xFFFFFFFFL
2656//DAGB0_RESERVE44
2657#define DAGB0_RESERVE44__RESERVE__SHIFT 0x0
2658#define DAGB0_RESERVE44__RESERVE_MASK 0xFFFFFFFFL
2659//DAGB0_RESERVE45
2660#define DAGB0_RESERVE45__RESERVE__SHIFT 0x0
2661#define DAGB0_RESERVE45__RESERVE_MASK 0xFFFFFFFFL
2662//DAGB0_RESERVE46
2663#define DAGB0_RESERVE46__RESERVE__SHIFT 0x0
2664#define DAGB0_RESERVE46__RESERVE_MASK 0xFFFFFFFFL
2665//DAGB0_RESERVE47
2666#define DAGB0_RESERVE47__RESERVE__SHIFT 0x0
2667#define DAGB0_RESERVE47__RESERVE_MASK 0xFFFFFFFFL
2668//DAGB0_RESERVE48
2669#define DAGB0_RESERVE48__RESERVE__SHIFT 0x0
2670#define DAGB0_RESERVE48__RESERVE_MASK 0xFFFFFFFFL
2671//DAGB0_RESERVE49
2672#define DAGB0_RESERVE49__RESERVE__SHIFT 0x0
2673#define DAGB0_RESERVE49__RESERVE_MASK 0xFFFFFFFFL
2674//DAGB0_RESERVE50
2675#define DAGB0_RESERVE50__RESERVE__SHIFT 0x0
2676#define DAGB0_RESERVE50__RESERVE_MASK 0xFFFFFFFFL
2677//DAGB0_RESERVE51
2678#define DAGB0_RESERVE51__RESERVE__SHIFT 0x0
2679#define DAGB0_RESERVE51__RESERVE_MASK 0xFFFFFFFFL
2680//DAGB0_RESERVE52
2681#define DAGB0_RESERVE52__RESERVE__SHIFT 0x0
2682#define DAGB0_RESERVE52__RESERVE_MASK 0xFFFFFFFFL
2683//DAGB0_RESERVE53
2684#define DAGB0_RESERVE53__RESERVE__SHIFT 0x0
2685#define DAGB0_RESERVE53__RESERVE_MASK 0xFFFFFFFFL
2686//DAGB0_RESERVE54
2687#define DAGB0_RESERVE54__RESERVE__SHIFT 0x0
2688#define DAGB0_RESERVE54__RESERVE_MASK 0xFFFFFFFFL
2689//DAGB0_RESERVE55
2690#define DAGB0_RESERVE55__RESERVE__SHIFT 0x0
2691#define DAGB0_RESERVE55__RESERVE_MASK 0xFFFFFFFFL
2692//DAGB0_RESERVE56
2693#define DAGB0_RESERVE56__RESERVE__SHIFT 0x0
2694#define DAGB0_RESERVE56__RESERVE_MASK 0xFFFFFFFFL
2695//DAGB0_RESERVE57
2696#define DAGB0_RESERVE57__RESERVE__SHIFT 0x0
2697#define DAGB0_RESERVE57__RESERVE_MASK 0xFFFFFFFFL
2698//DAGB0_RESERVE58
2699#define DAGB0_RESERVE58__RESERVE__SHIFT 0x0
2700#define DAGB0_RESERVE58__RESERVE_MASK 0xFFFFFFFFL
2701//DAGB0_RESERVE59
2702#define DAGB0_RESERVE59__RESERVE__SHIFT 0x0
2703#define DAGB0_RESERVE59__RESERVE_MASK 0xFFFFFFFFL
2704//DAGB0_RESERVE60
2705#define DAGB0_RESERVE60__RESERVE__SHIFT 0x0
2706#define DAGB0_RESERVE60__RESERVE_MASK 0xFFFFFFFFL
2707//DAGB0_RESERVE61
2708#define DAGB0_RESERVE61__RESERVE__SHIFT 0x0
2709#define DAGB0_RESERVE61__RESERVE_MASK 0xFFFFFFFFL
2710//DAGB0_RESERVE62
2711#define DAGB0_RESERVE62__RESERVE__SHIFT 0x0
2712#define DAGB0_RESERVE62__RESERVE_MASK 0xFFFFFFFFL
2713//DAGB0_RESERVE63
2714#define DAGB0_RESERVE63__RESERVE__SHIFT 0x0
2715#define DAGB0_RESERVE63__RESERVE_MASK 0xFFFFFFFFL
2716//DAGB0_RESERVE64
2717#define DAGB0_RESERVE64__RESERVE__SHIFT 0x0
2718#define DAGB0_RESERVE64__RESERVE_MASK 0xFFFFFFFFL
2719//DAGB0_RESERVE65
2720#define DAGB0_RESERVE65__RESERVE__SHIFT 0x0
2721#define DAGB0_RESERVE65__RESERVE_MASK 0xFFFFFFFFL
2722//DAGB0_RESERVE66
2723#define DAGB0_RESERVE66__RESERVE__SHIFT 0x0
2724#define DAGB0_RESERVE66__RESERVE_MASK 0xFFFFFFFFL
2725//DAGB0_RESERVE67
2726#define DAGB0_RESERVE67__RESERVE__SHIFT 0x0
2727#define DAGB0_RESERVE67__RESERVE_MASK 0xFFFFFFFFL
2728//DAGB0_RESERVE68
2729#define DAGB0_RESERVE68__RESERVE__SHIFT 0x0
2730#define DAGB0_RESERVE68__RESERVE_MASK 0xFFFFFFFFL
2731//DAGB0_RESERVE69
2732#define DAGB0_RESERVE69__RESERVE__SHIFT 0x0
2733#define DAGB0_RESERVE69__RESERVE_MASK 0xFFFFFFFFL
2734//DAGB0_RESERVE70
2735#define DAGB0_RESERVE70__RESERVE__SHIFT 0x0
2736#define DAGB0_RESERVE70__RESERVE_MASK 0xFFFFFFFFL
2737//DAGB0_RESERVE71
2738#define DAGB0_RESERVE71__RESERVE__SHIFT 0x0
2739#define DAGB0_RESERVE71__RESERVE_MASK 0xFFFFFFFFL
2740//DAGB0_RESERVE72
2741#define DAGB0_RESERVE72__RESERVE__SHIFT 0x0
2742#define DAGB0_RESERVE72__RESERVE_MASK 0xFFFFFFFFL
2743//DAGB0_RESERVE73
2744#define DAGB0_RESERVE73__RESERVE__SHIFT 0x0
2745#define DAGB0_RESERVE73__RESERVE_MASK 0xFFFFFFFFL
2746//DAGB0_RESERVE74
2747#define DAGB0_RESERVE74__RESERVE__SHIFT 0x0
2748#define DAGB0_RESERVE74__RESERVE_MASK 0xFFFFFFFFL
2749//DAGB0_RESERVE75
2750#define DAGB0_RESERVE75__RESERVE__SHIFT 0x0
2751#define DAGB0_RESERVE75__RESERVE_MASK 0xFFFFFFFFL
2752//DAGB0_RESERVE76
2753#define DAGB0_RESERVE76__RESERVE__SHIFT 0x0
2754#define DAGB0_RESERVE76__RESERVE_MASK 0xFFFFFFFFL
2755//DAGB0_RESERVE77
2756#define DAGB0_RESERVE77__RESERVE__SHIFT 0x0
2757#define DAGB0_RESERVE77__RESERVE_MASK 0xFFFFFFFFL
2758//DAGB0_RESERVE78
2759#define DAGB0_RESERVE78__RESERVE__SHIFT 0x0
2760#define DAGB0_RESERVE78__RESERVE_MASK 0xFFFFFFFFL
2761//DAGB0_RESERVE79
2762#define DAGB0_RESERVE79__RESERVE__SHIFT 0x0
2763#define DAGB0_RESERVE79__RESERVE_MASK 0xFFFFFFFFL
2764//DAGB0_RESERVE80
2765#define DAGB0_RESERVE80__RESERVE__SHIFT 0x0
2766#define DAGB0_RESERVE80__RESERVE_MASK 0xFFFFFFFFL
2767//DAGB0_RESERVE81
2768#define DAGB0_RESERVE81__RESERVE__SHIFT 0x0
2769#define DAGB0_RESERVE81__RESERVE_MASK 0xFFFFFFFFL
2770//DAGB0_RESERVE82
2771#define DAGB0_RESERVE82__RESERVE__SHIFT 0x0
2772#define DAGB0_RESERVE82__RESERVE_MASK 0xFFFFFFFFL
2773//DAGB0_RESERVE83
2774#define DAGB0_RESERVE83__RESERVE__SHIFT 0x0
2775#define DAGB0_RESERVE83__RESERVE_MASK 0xFFFFFFFFL
2776//DAGB0_RESERVE84
2777#define DAGB0_RESERVE84__RESERVE__SHIFT 0x0
2778#define DAGB0_RESERVE84__RESERVE_MASK 0xFFFFFFFFL
2779//DAGB0_RESERVE85
2780#define DAGB0_RESERVE85__RESERVE__SHIFT 0x0
2781#define DAGB0_RESERVE85__RESERVE_MASK 0xFFFFFFFFL
2782//DAGB0_RESERVE86
2783#define DAGB0_RESERVE86__RESERVE__SHIFT 0x0
2784#define DAGB0_RESERVE86__RESERVE_MASK 0xFFFFFFFFL
2785//DAGB0_RESERVE87
2786#define DAGB0_RESERVE87__RESERVE__SHIFT 0x0
2787#define DAGB0_RESERVE87__RESERVE_MASK 0xFFFFFFFFL
2788//DAGB0_RESERVE88
2789#define DAGB0_RESERVE88__RESERVE__SHIFT 0x0
2790#define DAGB0_RESERVE88__RESERVE_MASK 0xFFFFFFFFL
2791//DAGB0_RESERVE89
2792#define DAGB0_RESERVE89__RESERVE__SHIFT 0x0
2793#define DAGB0_RESERVE89__RESERVE_MASK 0xFFFFFFFFL
2794//DAGB0_RESERVE90
2795#define DAGB0_RESERVE90__RESERVE__SHIFT 0x0
2796#define DAGB0_RESERVE90__RESERVE_MASK 0xFFFFFFFFL
2797//DAGB0_RESERVE91
2798#define DAGB0_RESERVE91__RESERVE__SHIFT 0x0
2799#define DAGB0_RESERVE91__RESERVE_MASK 0xFFFFFFFFL
2800//DAGB0_RESERVE92
2801#define DAGB0_RESERVE92__RESERVE__SHIFT 0x0
2802#define DAGB0_RESERVE92__RESERVE_MASK 0xFFFFFFFFL
2803//DAGB0_RESERVE93
2804#define DAGB0_RESERVE93__RESERVE__SHIFT 0x0
2805#define DAGB0_RESERVE93__RESERVE_MASK 0xFFFFFFFFL
2806//DAGB0_RESERVE94
2807#define DAGB0_RESERVE94__RESERVE__SHIFT 0x0
2808#define DAGB0_RESERVE94__RESERVE_MASK 0xFFFFFFFFL
2809//DAGB0_RESERVE95
2810#define DAGB0_RESERVE95__RESERVE__SHIFT 0x0
2811#define DAGB0_RESERVE95__RESERVE_MASK 0xFFFFFFFFL
2812//DAGB0_RESERVE96
2813#define DAGB0_RESERVE96__RESERVE__SHIFT 0x0
2814#define DAGB0_RESERVE96__RESERVE_MASK 0xFFFFFFFFL
2815//DAGB0_RESERVE97
2816#define DAGB0_RESERVE97__RESERVE__SHIFT 0x0
2817#define DAGB0_RESERVE97__RESERVE_MASK 0xFFFFFFFFL
2818//DAGB0_RESERVE98
2819#define DAGB0_RESERVE98__RESERVE__SHIFT 0x0
2820#define DAGB0_RESERVE98__RESERVE_MASK 0xFFFFFFFFL
2821//DAGB0_RESERVE99
2822#define DAGB0_RESERVE99__RESERVE__SHIFT 0x0
2823#define DAGB0_RESERVE99__RESERVE_MASK 0xFFFFFFFFL
2824//DAGB0_RESERVE100
2825#define DAGB0_RESERVE100__RESERVE__SHIFT 0x0
2826#define DAGB0_RESERVE100__RESERVE_MASK 0xFFFFFFFFL
2827//DAGB0_RESERVE101
2828#define DAGB0_RESERVE101__RESERVE__SHIFT 0x0
2829#define DAGB0_RESERVE101__RESERVE_MASK 0xFFFFFFFFL
2830
2831
2832// addressBlock: mmhub_ea_mmeadec
2833//MMEA0_DRAM_RD_CLI2GRP_MAP0
2834#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
2835#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
2836#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
2837#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
2838#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
2839#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
2840#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
2841#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
2842#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
2843#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
2844#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
2845#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
2846#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
2847#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
2848#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
2849#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
2850#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
2851#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
2852#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
2853#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
2854#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
2855#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
2856#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
2857#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
2858#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
2859#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
2860#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
2861#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
2862#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
2863#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
2864#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
2865#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
2866//MMEA0_DRAM_RD_CLI2GRP_MAP1
2867#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
2868#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
2869#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
2870#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
2871#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
2872#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
2873#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
2874#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
2875#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
2876#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
2877#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
2878#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
2879#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
2880#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
2881#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
2882#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
2883#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
2884#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
2885#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
2886#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
2887#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
2888#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
2889#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
2890#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
2891#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
2892#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
2893#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
2894#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
2895#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
2896#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
2897#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
2898#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
2899//MMEA0_DRAM_WR_CLI2GRP_MAP0
2900#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
2901#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
2902#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
2903#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
2904#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
2905#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
2906#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
2907#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
2908#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
2909#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
2910#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
2911#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
2912#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
2913#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
2914#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
2915#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
2916#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
2917#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
2918#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
2919#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
2920#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
2921#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
2922#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
2923#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
2924#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
2925#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
2926#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
2927#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
2928#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
2929#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
2930#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
2931#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
2932//MMEA0_DRAM_WR_CLI2GRP_MAP1
2933#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
2934#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
2935#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
2936#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
2937#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
2938#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
2939#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
2940#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
2941#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
2942#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
2943#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
2944#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
2945#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
2946#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
2947#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
2948#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
2949#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
2950#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
2951#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
2952#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
2953#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
2954#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
2955#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
2956#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
2957#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
2958#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
2959#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
2960#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
2961#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
2962#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
2963#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
2964#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
2965//MMEA0_DRAM_RD_GRP2VC_MAP
2966#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
2967#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
2968#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
2969#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
2970#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
2971#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
2972#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
2973#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
2974//MMEA0_DRAM_WR_GRP2VC_MAP
2975#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
2976#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
2977#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
2978#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
2979#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
2980#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
2981#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
2982#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
2983//MMEA0_DRAM_RD_LAZY
2984#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0
2985#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3
2986#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6
2987#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9
2988#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L
2989#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L
2990#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L
2991#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L
2992//MMEA0_DRAM_WR_LAZY
2993#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0
2994#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3
2995#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6
2996#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9
2997#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L
2998#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L
2999#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L
3000#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L
3001//MMEA0_DRAM_RD_CAM_CNTL
3002#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
3003#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
3004#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
3005#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
3006#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
3007#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
3008#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
3009#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
3010#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
3011#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
3012#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
3013#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
3014#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
3015#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
3016#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
3017#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
3018//MMEA0_DRAM_WR_CAM_CNTL
3019#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
3020#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
3021#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
3022#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
3023#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
3024#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
3025#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
3026#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
3027#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
3028#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
3029#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
3030#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
3031#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
3032#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
3033#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
3034#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
3035//MMEA0_DRAM_PAGE_BURST
3036#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0
3037#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8
3038#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10
3039#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18
3040#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL
3041#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
3042#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
3043#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L
3044//MMEA0_DRAM_RD_PRI_AGE
3045#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
3046#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
3047#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
3048#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
3049#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
3050#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
3051#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
3052#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
3053#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
3054#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
3055#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
3056#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
3057#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
3058#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
3059#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
3060#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
3061//MMEA0_DRAM_WR_PRI_AGE
3062#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
3063#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
3064#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
3065#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
3066#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
3067#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
3068#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
3069#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
3070#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
3071#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
3072#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
3073#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
3074#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
3075#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
3076#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
3077#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
3078//MMEA0_DRAM_RD_PRI_QUEUING
3079#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
3080#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
3081#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
3082#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
3083#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
3084#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
3085#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
3086#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
3087//MMEA0_DRAM_WR_PRI_QUEUING
3088#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
3089#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
3090#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
3091#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
3092#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
3093#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
3094#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
3095#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
3096//MMEA0_DRAM_RD_PRI_FIXED
3097#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
3098#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
3099#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
3100#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
3101#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
3102#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
3103#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
3104#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
3105//MMEA0_DRAM_WR_PRI_FIXED
3106#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
3107#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
3108#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
3109#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
3110#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
3111#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
3112#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
3113#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
3114//MMEA0_DRAM_RD_PRI_URGENCY
3115#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
3116#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
3117#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
3118#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
3119#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
3120#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
3121#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
3122#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
3123#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
3124#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
3125#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
3126#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
3127#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
3128#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
3129#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
3130#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
3131//MMEA0_DRAM_WR_PRI_URGENCY
3132#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
3133#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
3134#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
3135#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
3136#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
3137#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
3138#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
3139#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
3140#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
3141#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
3142#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
3143#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
3144#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
3145#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
3146#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
3147#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
3148//MMEA0_DRAM_RD_PRI_QUANT_PRI1
3149#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
3150#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
3151#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
3152#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
3153#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
3154#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
3155#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
3156#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
3157//MMEA0_DRAM_RD_PRI_QUANT_PRI2
3158#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
3159#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
3160#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
3161#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
3162#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
3163#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
3164#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
3165#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
3166//MMEA0_DRAM_RD_PRI_QUANT_PRI3
3167#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
3168#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
3169#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
3170#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
3171#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
3172#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
3173#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
3174#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
3175//MMEA0_DRAM_WR_PRI_QUANT_PRI1
3176#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
3177#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
3178#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
3179#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
3180#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
3181#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
3182#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
3183#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
3184//MMEA0_DRAM_WR_PRI_QUANT_PRI2
3185#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
3186#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
3187#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
3188#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
3189#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
3190#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
3191#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
3192#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
3193//MMEA0_DRAM_WR_PRI_QUANT_PRI3
3194#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
3195#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
3196#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
3197#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
3198#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
3199#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
3200#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
3201#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
3202//MMEA0_ADDRNORM_BASE_ADDR0
3203#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0
3204#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1
3205#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4
3206#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8
3207#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc
3208#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L
3209#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
3210#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L
3211#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L
3212#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L
3213//MMEA0_ADDRNORM_LIMIT_ADDR0
3214#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0
3215#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8
3216#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa
3217#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc
3218#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000000FL
3219#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L
3220#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L
3221#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L
3222//MMEA0_ADDRNORM_BASE_ADDR1
3223#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0
3224#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1
3225#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4
3226#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8
3227#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc
3228#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L
3229#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
3230#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L
3231#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L
3232#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L
3233//MMEA0_ADDRNORM_LIMIT_ADDR1
3234#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0
3235#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8
3236#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa
3237#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc
3238#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000000FL
3239#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L
3240#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L
3241#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L
3242//MMEA0_ADDRNORM_OFFSET_ADDR1
3243#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0
3244#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14
3245#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L
3246#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L
3247//MMEA0_ADDRNORM_HOLE_CNTL
3248#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0
3249#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7
3250#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L
3251#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L
3252//MMEA0_ADDRDEC_BANK_CFG
3253#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0
3254#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5
3255#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa
3256#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd
3257#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10
3258#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11
3259#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL
3260#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L
3261#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L
3262#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L
3263#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L
3264#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L
3265//MMEA0_ADDRDEC_MISC_CFG
3266#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0
3267#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1
3268#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2
3269#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3
3270#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4
3271#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8
3272#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9
3273#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc
3274#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x10
3275#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x14
3276#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x16
3277#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x18
3278#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1b
3279#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L
3280#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L
3281#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L
3282#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L
3283#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L
3284#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L
3285#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L
3286#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0000F000L
3287#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x000F0000L
3288#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00300000L
3289#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x00C00000L
3290#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x07000000L
3291#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0x38000000L
3292//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0
3293#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0
3294#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1
3295#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe
3296#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L
3297#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL
3298#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L
3299//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1
3300#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0
3301#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1
3302#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe
3303#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L
3304#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL
3305#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L
3306//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2
3307#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0
3308#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1
3309#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe
3310#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L
3311#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL
3312#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L
3313//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3
3314#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0
3315#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1
3316#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe
3317#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L
3318#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL
3319#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L
3320//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4
3321#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0
3322#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1
3323#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe
3324#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L
3325#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL
3326#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L
3327//MMEA0_ADDRDECDRAM_ADDR_HASH_PC
3328#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0
3329#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1
3330#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe
3331#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L
3332#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL
3333#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L
3334//MMEA0_ADDRDECDRAM_ADDR_HASH_PC2
3335#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0
3336#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL
3337//MMEA0_ADDRDECDRAM_ADDR_HASH_CS0
3338#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0
3339#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1
3340#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L
3341#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL
3342//MMEA0_ADDRDECDRAM_ADDR_HASH_CS1
3343#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0
3344#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1
3345#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L
3346#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL
3347//MMEA0_ADDRDECDRAM_HARVEST_ENABLE
3348#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0
3349#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1
3350#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2
3351#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3
3352#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L
3353#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L
3354#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L
3355#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L
3356//MMEA0_ADDRDEC0_BASE_ADDR_CS0
3357#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0
3358#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
3359#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L
3360#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
3361//MMEA0_ADDRDEC0_BASE_ADDR_CS1
3362#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0
3363#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
3364#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L
3365#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
3366//MMEA0_ADDRDEC0_BASE_ADDR_CS2
3367#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0
3368#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
3369#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L
3370#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
3371//MMEA0_ADDRDEC0_BASE_ADDR_CS3
3372#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0
3373#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
3374#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L
3375#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
3376//MMEA0_ADDRDEC0_BASE_ADDR_SECCS0
3377#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0
3378#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
3379#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L
3380#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
3381//MMEA0_ADDRDEC0_BASE_ADDR_SECCS1
3382#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0
3383#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
3384#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L
3385#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
3386//MMEA0_ADDRDEC0_BASE_ADDR_SECCS2
3387#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0
3388#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
3389#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L
3390#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
3391//MMEA0_ADDRDEC0_BASE_ADDR_SECCS3
3392#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0
3393#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
3394#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L
3395#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
3396//MMEA0_ADDRDEC0_ADDR_MASK_CS01
3397#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
3398#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
3399//MMEA0_ADDRDEC0_ADDR_MASK_CS23
3400#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
3401#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
3402//MMEA0_ADDRDEC0_ADDR_MASK_SECCS01
3403#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
3404#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
3405//MMEA0_ADDRDEC0_ADDR_MASK_SECCS23
3406#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
3407#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
3408//MMEA0_ADDRDEC0_ADDR_CFG_CS01
3409#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2
3410#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
3411#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
3412#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
3413#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
3414#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
3415#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL
3416#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
3417#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
3418#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
3419#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
3420#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
3421//MMEA0_ADDRDEC0_ADDR_CFG_CS23
3422#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2
3423#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
3424#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
3425#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
3426#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
3427#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
3428#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL
3429#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
3430#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
3431#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
3432#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
3433#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
3434//MMEA0_ADDRDEC0_ADDR_SEL_CS01
3435#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0
3436#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4
3437#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8
3438#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc
3439#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10
3440#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
3441#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
3442#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
3443#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
3444#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
3445#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
3446#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L
3447#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
3448#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
3449//MMEA0_ADDRDEC0_ADDR_SEL_CS23
3450#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0
3451#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4
3452#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8
3453#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc
3454#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10
3455#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
3456#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
3457#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
3458#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
3459#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
3460#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
3461#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L
3462#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
3463#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
3464//MMEA0_ADDRDEC0_COL_SEL_LO_CS01
3465#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0
3466#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4
3467#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8
3468#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc
3469#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10
3470#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14
3471#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18
3472#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
3473#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
3474#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
3475#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
3476#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
3477#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
3478#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
3479#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
3480#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
3481//MMEA0_ADDRDEC0_COL_SEL_LO_CS23
3482#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0
3483#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4
3484#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8
3485#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc
3486#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10
3487#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14
3488#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18
3489#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
3490#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
3491#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
3492#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
3493#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
3494#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
3495#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
3496#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
3497#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
3498//MMEA0_ADDRDEC0_COL_SEL_HI_CS01
3499#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0
3500#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4
3501#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8
3502#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc
3503#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10
3504#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14
3505#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18
3506#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
3507#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
3508#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
3509#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
3510#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
3511#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
3512#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
3513#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
3514#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
3515//MMEA0_ADDRDEC0_COL_SEL_HI_CS23
3516#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0
3517#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4
3518#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8
3519#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc
3520#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10
3521#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14
3522#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18
3523#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
3524#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
3525#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
3526#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
3527#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
3528#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
3529#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
3530#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
3531#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
3532//MMEA0_ADDRDEC0_RM_SEL_CS01
3533#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0
3534#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4
3535#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8
3536#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
3537#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
3538#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
3539#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL
3540#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L
3541#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L
3542#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
3543#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
3544#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
3545//MMEA0_ADDRDEC0_RM_SEL_CS23
3546#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0
3547#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4
3548#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8
3549#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
3550#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
3551#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
3552#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL
3553#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L
3554#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L
3555#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
3556#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
3557#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
3558//MMEA0_ADDRDEC0_RM_SEL_SECCS01
3559#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0
3560#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4
3561#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8
3562#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
3563#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
3564#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
3565#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
3566#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
3567#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
3568#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
3569#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
3570#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
3571//MMEA0_ADDRDEC0_RM_SEL_SECCS23
3572#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0
3573#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4
3574#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8
3575#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
3576#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
3577#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
3578#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
3579#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
3580#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
3581#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
3582#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
3583#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
3584//MMEA0_ADDRDEC1_BASE_ADDR_CS0
3585#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0
3586#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
3587#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L
3588#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
3589//MMEA0_ADDRDEC1_BASE_ADDR_CS1
3590#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0
3591#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
3592#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L
3593#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
3594//MMEA0_ADDRDEC1_BASE_ADDR_CS2
3595#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0
3596#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
3597#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L
3598#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
3599//MMEA0_ADDRDEC1_BASE_ADDR_CS3
3600#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0
3601#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
3602#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L
3603#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
3604//MMEA0_ADDRDEC1_BASE_ADDR_SECCS0
3605#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0
3606#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
3607#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L
3608#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
3609//MMEA0_ADDRDEC1_BASE_ADDR_SECCS1
3610#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0
3611#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
3612#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L
3613#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
3614//MMEA0_ADDRDEC1_BASE_ADDR_SECCS2
3615#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0
3616#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
3617#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L
3618#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
3619//MMEA0_ADDRDEC1_BASE_ADDR_SECCS3
3620#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0
3621#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
3622#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L
3623#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
3624//MMEA0_ADDRDEC1_ADDR_MASK_CS01
3625#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
3626#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
3627//MMEA0_ADDRDEC1_ADDR_MASK_CS23
3628#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
3629#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
3630//MMEA0_ADDRDEC1_ADDR_MASK_SECCS01
3631#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
3632#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
3633//MMEA0_ADDRDEC1_ADDR_MASK_SECCS23
3634#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
3635#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
3636//MMEA0_ADDRDEC1_ADDR_CFG_CS01
3637#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2
3638#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
3639#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
3640#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
3641#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
3642#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
3643#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL
3644#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
3645#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
3646#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
3647#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
3648#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
3649//MMEA0_ADDRDEC1_ADDR_CFG_CS23
3650#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2
3651#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
3652#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
3653#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
3654#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
3655#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
3656#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL
3657#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
3658#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
3659#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
3660#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
3661#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
3662//MMEA0_ADDRDEC1_ADDR_SEL_CS01
3663#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0
3664#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4
3665#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8
3666#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc
3667#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10
3668#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
3669#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
3670#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
3671#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
3672#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
3673#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
3674#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L
3675#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
3676#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
3677//MMEA0_ADDRDEC1_ADDR_SEL_CS23
3678#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0
3679#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4
3680#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8
3681#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc
3682#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10
3683#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
3684#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
3685#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
3686#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
3687#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
3688#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
3689#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L
3690#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
3691#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
3692//MMEA0_ADDRDEC1_COL_SEL_LO_CS01
3693#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0
3694#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4
3695#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8
3696#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc
3697#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10
3698#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14
3699#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18
3700#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
3701#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
3702#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
3703#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
3704#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
3705#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
3706#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
3707#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
3708#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
3709//MMEA0_ADDRDEC1_COL_SEL_LO_CS23
3710#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0
3711#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4
3712#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8
3713#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc
3714#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10
3715#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14
3716#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18
3717#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
3718#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
3719#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
3720#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
3721#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
3722#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
3723#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
3724#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
3725#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
3726//MMEA0_ADDRDEC1_COL_SEL_HI_CS01
3727#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0
3728#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4
3729#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8
3730#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc
3731#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10
3732#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14
3733#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18
3734#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
3735#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
3736#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
3737#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
3738#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
3739#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
3740#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
3741#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
3742#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
3743//MMEA0_ADDRDEC1_COL_SEL_HI_CS23
3744#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0
3745#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4
3746#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8
3747#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc
3748#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10
3749#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14
3750#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18
3751#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
3752#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
3753#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
3754#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
3755#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
3756#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
3757#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
3758#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
3759#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
3760//MMEA0_ADDRDEC1_RM_SEL_CS01
3761#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0
3762#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4
3763#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8
3764#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
3765#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
3766#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
3767#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL
3768#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L
3769#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L
3770#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
3771#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
3772#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
3773//MMEA0_ADDRDEC1_RM_SEL_CS23
3774#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0
3775#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4
3776#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8
3777#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
3778#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
3779#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
3780#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL
3781#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L
3782#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L
3783#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
3784#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
3785#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
3786//MMEA0_ADDRDEC1_RM_SEL_SECCS01
3787#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0
3788#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4
3789#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8
3790#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
3791#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
3792#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
3793#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
3794#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
3795#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
3796#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
3797#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
3798#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
3799//MMEA0_ADDRDEC1_RM_SEL_SECCS23
3800#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0
3801#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4
3802#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8
3803#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
3804#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
3805#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
3806#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
3807#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
3808#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
3809#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
3810#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
3811#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
3812//MMEA0_IO_RD_CLI2GRP_MAP0
3813#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
3814#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
3815#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
3816#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
3817#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
3818#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
3819#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
3820#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
3821#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
3822#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
3823#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
3824#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
3825#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
3826#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
3827#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
3828#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
3829#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
3830#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
3831#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
3832#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
3833#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
3834#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
3835#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
3836#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
3837#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
3838#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
3839#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
3840#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
3841#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
3842#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
3843#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
3844#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
3845//MMEA0_IO_RD_CLI2GRP_MAP1
3846#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
3847#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
3848#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
3849#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
3850#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
3851#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
3852#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
3853#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
3854#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
3855#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
3856#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
3857#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
3858#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
3859#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
3860#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
3861#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
3862#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
3863#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
3864#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
3865#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
3866#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
3867#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
3868#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
3869#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
3870#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
3871#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
3872#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
3873#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
3874#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
3875#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
3876#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
3877#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
3878//MMEA0_IO_WR_CLI2GRP_MAP0
3879#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
3880#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
3881#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
3882#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
3883#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
3884#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
3885#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
3886#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
3887#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
3888#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GR