| 1 | /* |
|---|
| 2 | * Copyright (C) 2017 Advanced Micro Devices, Inc. |
|---|
| 3 | * |
|---|
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
|---|
| 5 | * copy of this software and associated documentation files (the "Software"), |
|---|
| 6 | * to deal in the Software without restriction, including without limitation |
|---|
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
|---|
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
|---|
| 9 | * Software is furnished to do so, subject to the following conditions: |
|---|
| 10 | * |
|---|
| 11 | * The above copyright notice and this permission notice shall be included |
|---|
| 12 | * in all copies or substantial portions of the Software. |
|---|
| 13 | * |
|---|
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
|---|
| 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
|---|
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
|---|
| 17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
|---|
| 18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
|---|
| 19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
|---|
| 20 | */ |
|---|
| 21 | #ifndef _mmhub_9_1_SH_MASK_HEADER |
|---|
| 22 | #define |
|---|
| 23 | |
|---|
| 24 | |
|---|
| 25 | // addressBlock: mmhub_dagbdec |
|---|
| 26 | //DAGB0_RDCLI0 |
|---|
| 27 | #define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0 |
|---|
| 28 | #define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 29 | #define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4 |
|---|
| 30 | #define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8 |
|---|
| 31 | #define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 32 | #define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd |
|---|
| 33 | #define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 34 | #define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16 |
|---|
| 35 | #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 36 | #define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a |
|---|
| 37 | #define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L |
|---|
| 38 | #define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 39 | #define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L |
|---|
| 40 | #define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L |
|---|
| 41 | #define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 42 | #define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L |
|---|
| 43 | #define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 44 | #define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L |
|---|
| 45 | #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 46 | #define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L |
|---|
| 47 | //DAGB0_RDCLI1 |
|---|
| 48 | #define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0 |
|---|
| 49 | #define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 50 | #define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4 |
|---|
| 51 | #define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8 |
|---|
| 52 | #define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 53 | #define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd |
|---|
| 54 | #define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 55 | #define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16 |
|---|
| 56 | #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 57 | #define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a |
|---|
| 58 | #define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L |
|---|
| 59 | #define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 60 | #define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L |
|---|
| 61 | #define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L |
|---|
| 62 | #define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 63 | #define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L |
|---|
| 64 | #define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 65 | #define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L |
|---|
| 66 | #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 67 | #define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L |
|---|
| 68 | //DAGB0_RDCLI2 |
|---|
| 69 | #define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0 |
|---|
| 70 | #define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 71 | #define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4 |
|---|
| 72 | #define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8 |
|---|
| 73 | #define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 74 | #define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd |
|---|
| 75 | #define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 76 | #define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16 |
|---|
| 77 | #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 78 | #define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a |
|---|
| 79 | #define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L |
|---|
| 80 | #define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 81 | #define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L |
|---|
| 82 | #define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L |
|---|
| 83 | #define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 84 | #define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L |
|---|
| 85 | #define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 86 | #define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L |
|---|
| 87 | #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 88 | #define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L |
|---|
| 89 | //DAGB0_RDCLI3 |
|---|
| 90 | #define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0 |
|---|
| 91 | #define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 92 | #define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4 |
|---|
| 93 | #define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8 |
|---|
| 94 | #define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 95 | #define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd |
|---|
| 96 | #define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 97 | #define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16 |
|---|
| 98 | #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 99 | #define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a |
|---|
| 100 | #define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L |
|---|
| 101 | #define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 102 | #define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L |
|---|
| 103 | #define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L |
|---|
| 104 | #define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 105 | #define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L |
|---|
| 106 | #define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 107 | #define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L |
|---|
| 108 | #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 109 | #define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L |
|---|
| 110 | //DAGB0_RDCLI4 |
|---|
| 111 | #define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0 |
|---|
| 112 | #define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 113 | #define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4 |
|---|
| 114 | #define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8 |
|---|
| 115 | #define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 116 | #define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd |
|---|
| 117 | #define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 118 | #define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16 |
|---|
| 119 | #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 120 | #define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a |
|---|
| 121 | #define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L |
|---|
| 122 | #define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 123 | #define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L |
|---|
| 124 | #define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L |
|---|
| 125 | #define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 126 | #define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L |
|---|
| 127 | #define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 128 | #define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L |
|---|
| 129 | #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 130 | #define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L |
|---|
| 131 | //DAGB0_RDCLI5 |
|---|
| 132 | #define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0 |
|---|
| 133 | #define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 134 | #define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4 |
|---|
| 135 | #define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8 |
|---|
| 136 | #define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 137 | #define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd |
|---|
| 138 | #define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 139 | #define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16 |
|---|
| 140 | #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 141 | #define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a |
|---|
| 142 | #define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L |
|---|
| 143 | #define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 144 | #define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L |
|---|
| 145 | #define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L |
|---|
| 146 | #define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 147 | #define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L |
|---|
| 148 | #define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 149 | #define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L |
|---|
| 150 | #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 151 | #define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L |
|---|
| 152 | //DAGB0_RDCLI6 |
|---|
| 153 | #define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0 |
|---|
| 154 | #define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 155 | #define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4 |
|---|
| 156 | #define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8 |
|---|
| 157 | #define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 158 | #define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd |
|---|
| 159 | #define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 160 | #define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16 |
|---|
| 161 | #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 162 | #define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a |
|---|
| 163 | #define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L |
|---|
| 164 | #define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 165 | #define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L |
|---|
| 166 | #define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L |
|---|
| 167 | #define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 168 | #define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L |
|---|
| 169 | #define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 170 | #define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L |
|---|
| 171 | #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 172 | #define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L |
|---|
| 173 | //DAGB0_RDCLI7 |
|---|
| 174 | #define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0 |
|---|
| 175 | #define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 176 | #define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4 |
|---|
| 177 | #define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8 |
|---|
| 178 | #define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 179 | #define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd |
|---|
| 180 | #define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 181 | #define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16 |
|---|
| 182 | #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 183 | #define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a |
|---|
| 184 | #define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L |
|---|
| 185 | #define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 186 | #define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L |
|---|
| 187 | #define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L |
|---|
| 188 | #define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 189 | #define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L |
|---|
| 190 | #define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 191 | #define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L |
|---|
| 192 | #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 193 | #define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L |
|---|
| 194 | //DAGB0_RDCLI8 |
|---|
| 195 | #define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0 |
|---|
| 196 | #define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 197 | #define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4 |
|---|
| 198 | #define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8 |
|---|
| 199 | #define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 200 | #define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd |
|---|
| 201 | #define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 202 | #define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16 |
|---|
| 203 | #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 204 | #define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a |
|---|
| 205 | #define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L |
|---|
| 206 | #define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 207 | #define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L |
|---|
| 208 | #define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L |
|---|
| 209 | #define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 210 | #define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L |
|---|
| 211 | #define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 212 | #define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L |
|---|
| 213 | #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 214 | #define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L |
|---|
| 215 | //DAGB0_RDCLI9 |
|---|
| 216 | #define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0 |
|---|
| 217 | #define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 218 | #define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4 |
|---|
| 219 | #define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8 |
|---|
| 220 | #define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 221 | #define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd |
|---|
| 222 | #define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 223 | #define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16 |
|---|
| 224 | #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 225 | #define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a |
|---|
| 226 | #define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L |
|---|
| 227 | #define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 228 | #define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L |
|---|
| 229 | #define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L |
|---|
| 230 | #define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 231 | #define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L |
|---|
| 232 | #define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 233 | #define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L |
|---|
| 234 | #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 235 | #define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L |
|---|
| 236 | //DAGB0_RDCLI10 |
|---|
| 237 | #define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0 |
|---|
| 238 | #define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 239 | #define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4 |
|---|
| 240 | #define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8 |
|---|
| 241 | #define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 242 | #define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd |
|---|
| 243 | #define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 244 | #define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16 |
|---|
| 245 | #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 246 | #define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a |
|---|
| 247 | #define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L |
|---|
| 248 | #define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 249 | #define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L |
|---|
| 250 | #define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L |
|---|
| 251 | #define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 252 | #define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L |
|---|
| 253 | #define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 254 | #define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L |
|---|
| 255 | #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 256 | #define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L |
|---|
| 257 | //DAGB0_RDCLI11 |
|---|
| 258 | #define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0 |
|---|
| 259 | #define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 260 | #define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4 |
|---|
| 261 | #define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8 |
|---|
| 262 | #define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 263 | #define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd |
|---|
| 264 | #define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 265 | #define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16 |
|---|
| 266 | #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 267 | #define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a |
|---|
| 268 | #define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L |
|---|
| 269 | #define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 270 | #define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L |
|---|
| 271 | #define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L |
|---|
| 272 | #define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 273 | #define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L |
|---|
| 274 | #define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 275 | #define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L |
|---|
| 276 | #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 277 | #define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L |
|---|
| 278 | //DAGB0_RDCLI12 |
|---|
| 279 | #define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0 |
|---|
| 280 | #define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 281 | #define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4 |
|---|
| 282 | #define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8 |
|---|
| 283 | #define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 284 | #define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd |
|---|
| 285 | #define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 286 | #define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16 |
|---|
| 287 | #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 288 | #define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a |
|---|
| 289 | #define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L |
|---|
| 290 | #define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 291 | #define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L |
|---|
| 292 | #define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L |
|---|
| 293 | #define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 294 | #define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L |
|---|
| 295 | #define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 296 | #define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L |
|---|
| 297 | #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 298 | #define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L |
|---|
| 299 | //DAGB0_RDCLI13 |
|---|
| 300 | #define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0 |
|---|
| 301 | #define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 302 | #define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4 |
|---|
| 303 | #define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8 |
|---|
| 304 | #define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 305 | #define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd |
|---|
| 306 | #define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 307 | #define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16 |
|---|
| 308 | #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 309 | #define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a |
|---|
| 310 | #define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L |
|---|
| 311 | #define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 312 | #define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L |
|---|
| 313 | #define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L |
|---|
| 314 | #define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 315 | #define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L |
|---|
| 316 | #define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 317 | #define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L |
|---|
| 318 | #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 319 | #define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L |
|---|
| 320 | //DAGB0_RDCLI14 |
|---|
| 321 | #define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0 |
|---|
| 322 | #define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 323 | #define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4 |
|---|
| 324 | #define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8 |
|---|
| 325 | #define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 326 | #define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd |
|---|
| 327 | #define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 328 | #define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16 |
|---|
| 329 | #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 330 | #define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a |
|---|
| 331 | #define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L |
|---|
| 332 | #define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 333 | #define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L |
|---|
| 334 | #define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L |
|---|
| 335 | #define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 336 | #define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L |
|---|
| 337 | #define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 338 | #define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L |
|---|
| 339 | #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 340 | #define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L |
|---|
| 341 | //DAGB0_RDCLI15 |
|---|
| 342 | #define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0 |
|---|
| 343 | #define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 344 | #define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4 |
|---|
| 345 | #define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8 |
|---|
| 346 | #define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 347 | #define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd |
|---|
| 348 | #define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 349 | #define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16 |
|---|
| 350 | #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 351 | #define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a |
|---|
| 352 | #define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L |
|---|
| 353 | #define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 354 | #define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L |
|---|
| 355 | #define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L |
|---|
| 356 | #define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 357 | #define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L |
|---|
| 358 | #define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 359 | #define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L |
|---|
| 360 | #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 361 | #define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L |
|---|
| 362 | //DAGB0_RDCLI16 |
|---|
| 363 | #define DAGB0_RDCLI16__VIRT_CHAN__SHIFT 0x0 |
|---|
| 364 | #define DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 365 | #define DAGB0_RDCLI16__URG_HIGH__SHIFT 0x4 |
|---|
| 366 | #define DAGB0_RDCLI16__URG_LOW__SHIFT 0x8 |
|---|
| 367 | #define DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 368 | #define DAGB0_RDCLI16__MAX_BW__SHIFT 0xd |
|---|
| 369 | #define DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 370 | #define DAGB0_RDCLI16__MIN_BW__SHIFT 0x16 |
|---|
| 371 | #define DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 372 | #define DAGB0_RDCLI16__MAX_OSD__SHIFT 0x1a |
|---|
| 373 | #define DAGB0_RDCLI16__VIRT_CHAN_MASK 0x00000007L |
|---|
| 374 | #define DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 375 | #define DAGB0_RDCLI16__URG_HIGH_MASK 0x000000F0L |
|---|
| 376 | #define DAGB0_RDCLI16__URG_LOW_MASK 0x00000F00L |
|---|
| 377 | #define DAGB0_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 378 | #define DAGB0_RDCLI16__MAX_BW_MASK 0x001FE000L |
|---|
| 379 | #define DAGB0_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 380 | #define DAGB0_RDCLI16__MIN_BW_MASK 0x01C00000L |
|---|
| 381 | #define DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 382 | #define DAGB0_RDCLI16__MAX_OSD_MASK 0xFC000000L |
|---|
| 383 | //DAGB0_RDCLI17 |
|---|
| 384 | #define DAGB0_RDCLI17__VIRT_CHAN__SHIFT 0x0 |
|---|
| 385 | #define DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 386 | #define DAGB0_RDCLI17__URG_HIGH__SHIFT 0x4 |
|---|
| 387 | #define DAGB0_RDCLI17__URG_LOW__SHIFT 0x8 |
|---|
| 388 | #define DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 389 | #define DAGB0_RDCLI17__MAX_BW__SHIFT 0xd |
|---|
| 390 | #define DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 391 | #define DAGB0_RDCLI17__MIN_BW__SHIFT 0x16 |
|---|
| 392 | #define DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 393 | #define DAGB0_RDCLI17__MAX_OSD__SHIFT 0x1a |
|---|
| 394 | #define DAGB0_RDCLI17__VIRT_CHAN_MASK 0x00000007L |
|---|
| 395 | #define DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 396 | #define DAGB0_RDCLI17__URG_HIGH_MASK 0x000000F0L |
|---|
| 397 | #define DAGB0_RDCLI17__URG_LOW_MASK 0x00000F00L |
|---|
| 398 | #define DAGB0_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 399 | #define DAGB0_RDCLI17__MAX_BW_MASK 0x001FE000L |
|---|
| 400 | #define DAGB0_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 401 | #define DAGB0_RDCLI17__MIN_BW_MASK 0x01C00000L |
|---|
| 402 | #define DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 403 | #define DAGB0_RDCLI17__MAX_OSD_MASK 0xFC000000L |
|---|
| 404 | //DAGB0_RDCLI18 |
|---|
| 405 | #define DAGB0_RDCLI18__VIRT_CHAN__SHIFT 0x0 |
|---|
| 406 | #define DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 407 | #define DAGB0_RDCLI18__URG_HIGH__SHIFT 0x4 |
|---|
| 408 | #define DAGB0_RDCLI18__URG_LOW__SHIFT 0x8 |
|---|
| 409 | #define DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 410 | #define DAGB0_RDCLI18__MAX_BW__SHIFT 0xd |
|---|
| 411 | #define DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 412 | #define DAGB0_RDCLI18__MIN_BW__SHIFT 0x16 |
|---|
| 413 | #define DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 414 | #define DAGB0_RDCLI18__MAX_OSD__SHIFT 0x1a |
|---|
| 415 | #define DAGB0_RDCLI18__VIRT_CHAN_MASK 0x00000007L |
|---|
| 416 | #define DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 417 | #define DAGB0_RDCLI18__URG_HIGH_MASK 0x000000F0L |
|---|
| 418 | #define DAGB0_RDCLI18__URG_LOW_MASK 0x00000F00L |
|---|
| 419 | #define DAGB0_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 420 | #define DAGB0_RDCLI18__MAX_BW_MASK 0x001FE000L |
|---|
| 421 | #define DAGB0_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 422 | #define DAGB0_RDCLI18__MIN_BW_MASK 0x01C00000L |
|---|
| 423 | #define DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 424 | #define DAGB0_RDCLI18__MAX_OSD_MASK 0xFC000000L |
|---|
| 425 | //DAGB0_RDCLI19 |
|---|
| 426 | #define DAGB0_RDCLI19__VIRT_CHAN__SHIFT 0x0 |
|---|
| 427 | #define DAGB0_RDCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 428 | #define DAGB0_RDCLI19__URG_HIGH__SHIFT 0x4 |
|---|
| 429 | #define DAGB0_RDCLI19__URG_LOW__SHIFT 0x8 |
|---|
| 430 | #define DAGB0_RDCLI19__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 431 | #define DAGB0_RDCLI19__MAX_BW__SHIFT 0xd |
|---|
| 432 | #define DAGB0_RDCLI19__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 433 | #define DAGB0_RDCLI19__MIN_BW__SHIFT 0x16 |
|---|
| 434 | #define DAGB0_RDCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 435 | #define DAGB0_RDCLI19__MAX_OSD__SHIFT 0x1a |
|---|
| 436 | #define DAGB0_RDCLI19__VIRT_CHAN_MASK 0x00000007L |
|---|
| 437 | #define DAGB0_RDCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 438 | #define DAGB0_RDCLI19__URG_HIGH_MASK 0x000000F0L |
|---|
| 439 | #define DAGB0_RDCLI19__URG_LOW_MASK 0x00000F00L |
|---|
| 440 | #define DAGB0_RDCLI19__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 441 | #define DAGB0_RDCLI19__MAX_BW_MASK 0x001FE000L |
|---|
| 442 | #define DAGB0_RDCLI19__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 443 | #define DAGB0_RDCLI19__MIN_BW_MASK 0x01C00000L |
|---|
| 444 | #define DAGB0_RDCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 445 | #define DAGB0_RDCLI19__MAX_OSD_MASK 0xFC000000L |
|---|
| 446 | //DAGB0_RDCLI20 |
|---|
| 447 | #define DAGB0_RDCLI20__VIRT_CHAN__SHIFT 0x0 |
|---|
| 448 | #define DAGB0_RDCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 449 | #define DAGB0_RDCLI20__URG_HIGH__SHIFT 0x4 |
|---|
| 450 | #define DAGB0_RDCLI20__URG_LOW__SHIFT 0x8 |
|---|
| 451 | #define DAGB0_RDCLI20__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 452 | #define DAGB0_RDCLI20__MAX_BW__SHIFT 0xd |
|---|
| 453 | #define DAGB0_RDCLI20__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 454 | #define DAGB0_RDCLI20__MIN_BW__SHIFT 0x16 |
|---|
| 455 | #define DAGB0_RDCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 456 | #define DAGB0_RDCLI20__MAX_OSD__SHIFT 0x1a |
|---|
| 457 | #define DAGB0_RDCLI20__VIRT_CHAN_MASK 0x00000007L |
|---|
| 458 | #define DAGB0_RDCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 459 | #define DAGB0_RDCLI20__URG_HIGH_MASK 0x000000F0L |
|---|
| 460 | #define DAGB0_RDCLI20__URG_LOW_MASK 0x00000F00L |
|---|
| 461 | #define DAGB0_RDCLI20__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 462 | #define DAGB0_RDCLI20__MAX_BW_MASK 0x001FE000L |
|---|
| 463 | #define DAGB0_RDCLI20__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 464 | #define DAGB0_RDCLI20__MIN_BW_MASK 0x01C00000L |
|---|
| 465 | #define DAGB0_RDCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 466 | #define DAGB0_RDCLI20__MAX_OSD_MASK 0xFC000000L |
|---|
| 467 | //DAGB0_RDCLI21 |
|---|
| 468 | #define DAGB0_RDCLI21__VIRT_CHAN__SHIFT 0x0 |
|---|
| 469 | #define DAGB0_RDCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 470 | #define DAGB0_RDCLI21__URG_HIGH__SHIFT 0x4 |
|---|
| 471 | #define DAGB0_RDCLI21__URG_LOW__SHIFT 0x8 |
|---|
| 472 | #define DAGB0_RDCLI21__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 473 | #define DAGB0_RDCLI21__MAX_BW__SHIFT 0xd |
|---|
| 474 | #define DAGB0_RDCLI21__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 475 | #define DAGB0_RDCLI21__MIN_BW__SHIFT 0x16 |
|---|
| 476 | #define DAGB0_RDCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 477 | #define DAGB0_RDCLI21__MAX_OSD__SHIFT 0x1a |
|---|
| 478 | #define DAGB0_RDCLI21__VIRT_CHAN_MASK 0x00000007L |
|---|
| 479 | #define DAGB0_RDCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 480 | #define DAGB0_RDCLI21__URG_HIGH_MASK 0x000000F0L |
|---|
| 481 | #define DAGB0_RDCLI21__URG_LOW_MASK 0x00000F00L |
|---|
| 482 | #define DAGB0_RDCLI21__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 483 | #define DAGB0_RDCLI21__MAX_BW_MASK 0x001FE000L |
|---|
| 484 | #define DAGB0_RDCLI21__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 485 | #define DAGB0_RDCLI21__MIN_BW_MASK 0x01C00000L |
|---|
| 486 | #define DAGB0_RDCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 487 | #define DAGB0_RDCLI21__MAX_OSD_MASK 0xFC000000L |
|---|
| 488 | //DAGB0_RDCLI22 |
|---|
| 489 | #define DAGB0_RDCLI22__VIRT_CHAN__SHIFT 0x0 |
|---|
| 490 | #define DAGB0_RDCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 491 | #define DAGB0_RDCLI22__URG_HIGH__SHIFT 0x4 |
|---|
| 492 | #define DAGB0_RDCLI22__URG_LOW__SHIFT 0x8 |
|---|
| 493 | #define DAGB0_RDCLI22__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 494 | #define DAGB0_RDCLI22__MAX_BW__SHIFT 0xd |
|---|
| 495 | #define DAGB0_RDCLI22__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 496 | #define DAGB0_RDCLI22__MIN_BW__SHIFT 0x16 |
|---|
| 497 | #define DAGB0_RDCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 498 | #define DAGB0_RDCLI22__MAX_OSD__SHIFT 0x1a |
|---|
| 499 | #define DAGB0_RDCLI22__VIRT_CHAN_MASK 0x00000007L |
|---|
| 500 | #define DAGB0_RDCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 501 | #define DAGB0_RDCLI22__URG_HIGH_MASK 0x000000F0L |
|---|
| 502 | #define DAGB0_RDCLI22__URG_LOW_MASK 0x00000F00L |
|---|
| 503 | #define DAGB0_RDCLI22__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 504 | #define DAGB0_RDCLI22__MAX_BW_MASK 0x001FE000L |
|---|
| 505 | #define DAGB0_RDCLI22__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 506 | #define DAGB0_RDCLI22__MIN_BW_MASK 0x01C00000L |
|---|
| 507 | #define DAGB0_RDCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 508 | #define DAGB0_RDCLI22__MAX_OSD_MASK 0xFC000000L |
|---|
| 509 | //DAGB0_RDCLI23 |
|---|
| 510 | #define DAGB0_RDCLI23__VIRT_CHAN__SHIFT 0x0 |
|---|
| 511 | #define DAGB0_RDCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 512 | #define DAGB0_RDCLI23__URG_HIGH__SHIFT 0x4 |
|---|
| 513 | #define DAGB0_RDCLI23__URG_LOW__SHIFT 0x8 |
|---|
| 514 | #define DAGB0_RDCLI23__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 515 | #define DAGB0_RDCLI23__MAX_BW__SHIFT 0xd |
|---|
| 516 | #define DAGB0_RDCLI23__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 517 | #define DAGB0_RDCLI23__MIN_BW__SHIFT 0x16 |
|---|
| 518 | #define DAGB0_RDCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 519 | #define DAGB0_RDCLI23__MAX_OSD__SHIFT 0x1a |
|---|
| 520 | #define DAGB0_RDCLI23__VIRT_CHAN_MASK 0x00000007L |
|---|
| 521 | #define DAGB0_RDCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 522 | #define DAGB0_RDCLI23__URG_HIGH_MASK 0x000000F0L |
|---|
| 523 | #define DAGB0_RDCLI23__URG_LOW_MASK 0x00000F00L |
|---|
| 524 | #define DAGB0_RDCLI23__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 525 | #define DAGB0_RDCLI23__MAX_BW_MASK 0x001FE000L |
|---|
| 526 | #define DAGB0_RDCLI23__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 527 | #define DAGB0_RDCLI23__MIN_BW_MASK 0x01C00000L |
|---|
| 528 | #define DAGB0_RDCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 529 | #define DAGB0_RDCLI23__MAX_OSD_MASK 0xFC000000L |
|---|
| 530 | //DAGB0_RDCLI24 |
|---|
| 531 | #define DAGB0_RDCLI24__VIRT_CHAN__SHIFT 0x0 |
|---|
| 532 | #define DAGB0_RDCLI24__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 533 | #define DAGB0_RDCLI24__URG_HIGH__SHIFT 0x4 |
|---|
| 534 | #define DAGB0_RDCLI24__URG_LOW__SHIFT 0x8 |
|---|
| 535 | #define DAGB0_RDCLI24__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 536 | #define DAGB0_RDCLI24__MAX_BW__SHIFT 0xd |
|---|
| 537 | #define DAGB0_RDCLI24__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 538 | #define DAGB0_RDCLI24__MIN_BW__SHIFT 0x16 |
|---|
| 539 | #define DAGB0_RDCLI24__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 540 | #define DAGB0_RDCLI24__MAX_OSD__SHIFT 0x1a |
|---|
| 541 | #define DAGB0_RDCLI24__VIRT_CHAN_MASK 0x00000007L |
|---|
| 542 | #define DAGB0_RDCLI24__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 543 | #define DAGB0_RDCLI24__URG_HIGH_MASK 0x000000F0L |
|---|
| 544 | #define DAGB0_RDCLI24__URG_LOW_MASK 0x00000F00L |
|---|
| 545 | #define DAGB0_RDCLI24__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 546 | #define DAGB0_RDCLI24__MAX_BW_MASK 0x001FE000L |
|---|
| 547 | #define DAGB0_RDCLI24__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 548 | #define DAGB0_RDCLI24__MIN_BW_MASK 0x01C00000L |
|---|
| 549 | #define DAGB0_RDCLI24__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 550 | #define DAGB0_RDCLI24__MAX_OSD_MASK 0xFC000000L |
|---|
| 551 | //DAGB0_RDCLI25 |
|---|
| 552 | #define DAGB0_RDCLI25__VIRT_CHAN__SHIFT 0x0 |
|---|
| 553 | #define DAGB0_RDCLI25__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 554 | #define DAGB0_RDCLI25__URG_HIGH__SHIFT 0x4 |
|---|
| 555 | #define DAGB0_RDCLI25__URG_LOW__SHIFT 0x8 |
|---|
| 556 | #define DAGB0_RDCLI25__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 557 | #define DAGB0_RDCLI25__MAX_BW__SHIFT 0xd |
|---|
| 558 | #define DAGB0_RDCLI25__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 559 | #define DAGB0_RDCLI25__MIN_BW__SHIFT 0x16 |
|---|
| 560 | #define DAGB0_RDCLI25__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 561 | #define DAGB0_RDCLI25__MAX_OSD__SHIFT 0x1a |
|---|
| 562 | #define DAGB0_RDCLI25__VIRT_CHAN_MASK 0x00000007L |
|---|
| 563 | #define DAGB0_RDCLI25__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 564 | #define DAGB0_RDCLI25__URG_HIGH_MASK 0x000000F0L |
|---|
| 565 | #define DAGB0_RDCLI25__URG_LOW_MASK 0x00000F00L |
|---|
| 566 | #define DAGB0_RDCLI25__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 567 | #define DAGB0_RDCLI25__MAX_BW_MASK 0x001FE000L |
|---|
| 568 | #define DAGB0_RDCLI25__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 569 | #define DAGB0_RDCLI25__MIN_BW_MASK 0x01C00000L |
|---|
| 570 | #define DAGB0_RDCLI25__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 571 | #define DAGB0_RDCLI25__MAX_OSD_MASK 0xFC000000L |
|---|
| 572 | //DAGB0_RDCLI26 |
|---|
| 573 | #define DAGB0_RDCLI26__VIRT_CHAN__SHIFT 0x0 |
|---|
| 574 | #define DAGB0_RDCLI26__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 575 | #define DAGB0_RDCLI26__URG_HIGH__SHIFT 0x4 |
|---|
| 576 | #define DAGB0_RDCLI26__URG_LOW__SHIFT 0x8 |
|---|
| 577 | #define DAGB0_RDCLI26__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 578 | #define DAGB0_RDCLI26__MAX_BW__SHIFT 0xd |
|---|
| 579 | #define DAGB0_RDCLI26__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 580 | #define DAGB0_RDCLI26__MIN_BW__SHIFT 0x16 |
|---|
| 581 | #define DAGB0_RDCLI26__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 582 | #define DAGB0_RDCLI26__MAX_OSD__SHIFT 0x1a |
|---|
| 583 | #define DAGB0_RDCLI26__VIRT_CHAN_MASK 0x00000007L |
|---|
| 584 | #define DAGB0_RDCLI26__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 585 | #define DAGB0_RDCLI26__URG_HIGH_MASK 0x000000F0L |
|---|
| 586 | #define DAGB0_RDCLI26__URG_LOW_MASK 0x00000F00L |
|---|
| 587 | #define DAGB0_RDCLI26__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 588 | #define DAGB0_RDCLI26__MAX_BW_MASK 0x001FE000L |
|---|
| 589 | #define DAGB0_RDCLI26__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 590 | #define DAGB0_RDCLI26__MIN_BW_MASK 0x01C00000L |
|---|
| 591 | #define DAGB0_RDCLI26__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 592 | #define DAGB0_RDCLI26__MAX_OSD_MASK 0xFC000000L |
|---|
| 593 | //DAGB0_RDCLI27 |
|---|
| 594 | #define DAGB0_RDCLI27__VIRT_CHAN__SHIFT 0x0 |
|---|
| 595 | #define DAGB0_RDCLI27__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 596 | #define DAGB0_RDCLI27__URG_HIGH__SHIFT 0x4 |
|---|
| 597 | #define DAGB0_RDCLI27__URG_LOW__SHIFT 0x8 |
|---|
| 598 | #define DAGB0_RDCLI27__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 599 | #define DAGB0_RDCLI27__MAX_BW__SHIFT 0xd |
|---|
| 600 | #define DAGB0_RDCLI27__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 601 | #define DAGB0_RDCLI27__MIN_BW__SHIFT 0x16 |
|---|
| 602 | #define DAGB0_RDCLI27__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 603 | #define DAGB0_RDCLI27__MAX_OSD__SHIFT 0x1a |
|---|
| 604 | #define DAGB0_RDCLI27__VIRT_CHAN_MASK 0x00000007L |
|---|
| 605 | #define DAGB0_RDCLI27__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 606 | #define DAGB0_RDCLI27__URG_HIGH_MASK 0x000000F0L |
|---|
| 607 | #define DAGB0_RDCLI27__URG_LOW_MASK 0x00000F00L |
|---|
| 608 | #define DAGB0_RDCLI27__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 609 | #define DAGB0_RDCLI27__MAX_BW_MASK 0x001FE000L |
|---|
| 610 | #define DAGB0_RDCLI27__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 611 | #define DAGB0_RDCLI27__MIN_BW_MASK 0x01C00000L |
|---|
| 612 | #define DAGB0_RDCLI27__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 613 | #define DAGB0_RDCLI27__MAX_OSD_MASK 0xFC000000L |
|---|
| 614 | //DAGB0_RDCLI28 |
|---|
| 615 | #define DAGB0_RDCLI28__VIRT_CHAN__SHIFT 0x0 |
|---|
| 616 | #define DAGB0_RDCLI28__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 617 | #define DAGB0_RDCLI28__URG_HIGH__SHIFT 0x4 |
|---|
| 618 | #define DAGB0_RDCLI28__URG_LOW__SHIFT 0x8 |
|---|
| 619 | #define DAGB0_RDCLI28__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 620 | #define DAGB0_RDCLI28__MAX_BW__SHIFT 0xd |
|---|
| 621 | #define DAGB0_RDCLI28__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 622 | #define DAGB0_RDCLI28__MIN_BW__SHIFT 0x16 |
|---|
| 623 | #define DAGB0_RDCLI28__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 624 | #define DAGB0_RDCLI28__MAX_OSD__SHIFT 0x1a |
|---|
| 625 | #define DAGB0_RDCLI28__VIRT_CHAN_MASK 0x00000007L |
|---|
| 626 | #define DAGB0_RDCLI28__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 627 | #define DAGB0_RDCLI28__URG_HIGH_MASK 0x000000F0L |
|---|
| 628 | #define DAGB0_RDCLI28__URG_LOW_MASK 0x00000F00L |
|---|
| 629 | #define DAGB0_RDCLI28__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 630 | #define DAGB0_RDCLI28__MAX_BW_MASK 0x001FE000L |
|---|
| 631 | #define DAGB0_RDCLI28__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 632 | #define DAGB0_RDCLI28__MIN_BW_MASK 0x01C00000L |
|---|
| 633 | #define DAGB0_RDCLI28__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 634 | #define DAGB0_RDCLI28__MAX_OSD_MASK 0xFC000000L |
|---|
| 635 | //DAGB0_RDCLI29 |
|---|
| 636 | #define DAGB0_RDCLI29__VIRT_CHAN__SHIFT 0x0 |
|---|
| 637 | #define DAGB0_RDCLI29__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 638 | #define DAGB0_RDCLI29__URG_HIGH__SHIFT 0x4 |
|---|
| 639 | #define DAGB0_RDCLI29__URG_LOW__SHIFT 0x8 |
|---|
| 640 | #define DAGB0_RDCLI29__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 641 | #define DAGB0_RDCLI29__MAX_BW__SHIFT 0xd |
|---|
| 642 | #define DAGB0_RDCLI29__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 643 | #define DAGB0_RDCLI29__MIN_BW__SHIFT 0x16 |
|---|
| 644 | #define DAGB0_RDCLI29__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 645 | #define DAGB0_RDCLI29__MAX_OSD__SHIFT 0x1a |
|---|
| 646 | #define DAGB0_RDCLI29__VIRT_CHAN_MASK 0x00000007L |
|---|
| 647 | #define DAGB0_RDCLI29__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 648 | #define DAGB0_RDCLI29__URG_HIGH_MASK 0x000000F0L |
|---|
| 649 | #define DAGB0_RDCLI29__URG_LOW_MASK 0x00000F00L |
|---|
| 650 | #define DAGB0_RDCLI29__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 651 | #define DAGB0_RDCLI29__MAX_BW_MASK 0x001FE000L |
|---|
| 652 | #define DAGB0_RDCLI29__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 653 | #define DAGB0_RDCLI29__MIN_BW_MASK 0x01C00000L |
|---|
| 654 | #define DAGB0_RDCLI29__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 655 | #define DAGB0_RDCLI29__MAX_OSD_MASK 0xFC000000L |
|---|
| 656 | //DAGB0_RDCLI30 |
|---|
| 657 | #define DAGB0_RDCLI30__VIRT_CHAN__SHIFT 0x0 |
|---|
| 658 | #define DAGB0_RDCLI30__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 659 | #define DAGB0_RDCLI30__URG_HIGH__SHIFT 0x4 |
|---|
| 660 | #define DAGB0_RDCLI30__URG_LOW__SHIFT 0x8 |
|---|
| 661 | #define DAGB0_RDCLI30__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 662 | #define DAGB0_RDCLI30__MAX_BW__SHIFT 0xd |
|---|
| 663 | #define DAGB0_RDCLI30__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 664 | #define DAGB0_RDCLI30__MIN_BW__SHIFT 0x16 |
|---|
| 665 | #define DAGB0_RDCLI30__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 666 | #define DAGB0_RDCLI30__MAX_OSD__SHIFT 0x1a |
|---|
| 667 | #define DAGB0_RDCLI30__VIRT_CHAN_MASK 0x00000007L |
|---|
| 668 | #define DAGB0_RDCLI30__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 669 | #define DAGB0_RDCLI30__URG_HIGH_MASK 0x000000F0L |
|---|
| 670 | #define DAGB0_RDCLI30__URG_LOW_MASK 0x00000F00L |
|---|
| 671 | #define DAGB0_RDCLI30__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 672 | #define DAGB0_RDCLI30__MAX_BW_MASK 0x001FE000L |
|---|
| 673 | #define DAGB0_RDCLI30__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 674 | #define DAGB0_RDCLI30__MIN_BW_MASK 0x01C00000L |
|---|
| 675 | #define DAGB0_RDCLI30__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 676 | #define DAGB0_RDCLI30__MAX_OSD_MASK 0xFC000000L |
|---|
| 677 | //DAGB0_RDCLI31 |
|---|
| 678 | #define DAGB0_RDCLI31__VIRT_CHAN__SHIFT 0x0 |
|---|
| 679 | #define DAGB0_RDCLI31__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 680 | #define DAGB0_RDCLI31__URG_HIGH__SHIFT 0x4 |
|---|
| 681 | #define DAGB0_RDCLI31__URG_LOW__SHIFT 0x8 |
|---|
| 682 | #define DAGB0_RDCLI31__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 683 | #define DAGB0_RDCLI31__MAX_BW__SHIFT 0xd |
|---|
| 684 | #define DAGB0_RDCLI31__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 685 | #define DAGB0_RDCLI31__MIN_BW__SHIFT 0x16 |
|---|
| 686 | #define DAGB0_RDCLI31__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 687 | #define DAGB0_RDCLI31__MAX_OSD__SHIFT 0x1a |
|---|
| 688 | #define DAGB0_RDCLI31__VIRT_CHAN_MASK 0x00000007L |
|---|
| 689 | #define DAGB0_RDCLI31__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 690 | #define DAGB0_RDCLI31__URG_HIGH_MASK 0x000000F0L |
|---|
| 691 | #define DAGB0_RDCLI31__URG_LOW_MASK 0x00000F00L |
|---|
| 692 | #define DAGB0_RDCLI31__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 693 | #define DAGB0_RDCLI31__MAX_BW_MASK 0x001FE000L |
|---|
| 694 | #define DAGB0_RDCLI31__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 695 | #define DAGB0_RDCLI31__MIN_BW_MASK 0x01C00000L |
|---|
| 696 | #define DAGB0_RDCLI31__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 697 | #define DAGB0_RDCLI31__MAX_OSD_MASK 0xFC000000L |
|---|
| 698 | //DAGB0_RD_CNTL |
|---|
| 699 | #define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT 0x0 |
|---|
| 700 | #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 |
|---|
| 701 | #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa |
|---|
| 702 | #define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 |
|---|
| 703 | #define DAGB0_RD_CNTL__IO_LEVEL__SHIFT 0x11 |
|---|
| 704 | #define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 |
|---|
| 705 | #define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 |
|---|
| 706 | #define DAGB0_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL |
|---|
| 707 | #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L |
|---|
| 708 | #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L |
|---|
| 709 | #define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L |
|---|
| 710 | #define DAGB0_RD_CNTL__IO_LEVEL_MASK 0x000E0000L |
|---|
| 711 | #define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L |
|---|
| 712 | #define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L |
|---|
| 713 | //DAGB0_RD_GMI_CNTL |
|---|
| 714 | #define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 |
|---|
| 715 | #define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT 0x6 |
|---|
| 716 | #define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 |
|---|
| 717 | #define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd |
|---|
| 718 | #define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL |
|---|
| 719 | #define DAGB0_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L |
|---|
| 720 | #define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L |
|---|
| 721 | #define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L |
|---|
| 722 | //DAGB0_RD_ADDR_DAGB |
|---|
| 723 | #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 |
|---|
| 724 | #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 |
|---|
| 725 | #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 |
|---|
| 726 | #define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 |
|---|
| 727 | #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L |
|---|
| 728 | #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L |
|---|
| 729 | #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L |
|---|
| 730 | #define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L |
|---|
| 731 | //DAGB0_RD_OUTPUT_DAGB_MAX_BURST |
|---|
| 732 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 |
|---|
| 733 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 |
|---|
| 734 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 |
|---|
| 735 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc |
|---|
| 736 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 |
|---|
| 737 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 |
|---|
| 738 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 |
|---|
| 739 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c |
|---|
| 740 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL |
|---|
| 741 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L |
|---|
| 742 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L |
|---|
| 743 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L |
|---|
| 744 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L |
|---|
| 745 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L |
|---|
| 746 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L |
|---|
| 747 | #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L |
|---|
| 748 | //DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER |
|---|
| 749 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 |
|---|
| 750 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 |
|---|
| 751 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 |
|---|
| 752 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc |
|---|
| 753 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 |
|---|
| 754 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 |
|---|
| 755 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 |
|---|
| 756 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c |
|---|
| 757 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL |
|---|
| 758 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L |
|---|
| 759 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L |
|---|
| 760 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L |
|---|
| 761 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L |
|---|
| 762 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L |
|---|
| 763 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L |
|---|
| 764 | #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L |
|---|
| 765 | //DAGB0_RD_CGTT_CLK_CTRL |
|---|
| 766 | #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
|---|
| 767 | #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
|---|
| 768 | #define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 |
|---|
| 769 | #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b |
|---|
| 770 | #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c |
|---|
| 771 | #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d |
|---|
| 772 | #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e |
|---|
| 773 | #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f |
|---|
| 774 | #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
|---|
| 775 | #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
|---|
| 776 | #define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L |
|---|
| 777 | #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L |
|---|
| 778 | #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L |
|---|
| 779 | #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L |
|---|
| 780 | #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L |
|---|
| 781 | #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L |
|---|
| 782 | //DAGB0_L1TLB_RD_CGTT_CLK_CTRL |
|---|
| 783 | #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
|---|
| 784 | #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
|---|
| 785 | #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 |
|---|
| 786 | #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b |
|---|
| 787 | #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c |
|---|
| 788 | #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d |
|---|
| 789 | #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e |
|---|
| 790 | #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f |
|---|
| 791 | #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
|---|
| 792 | #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
|---|
| 793 | #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L |
|---|
| 794 | #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L |
|---|
| 795 | #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L |
|---|
| 796 | #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L |
|---|
| 797 | #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L |
|---|
| 798 | #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L |
|---|
| 799 | //DAGB0_ATCVM_RD_CGTT_CLK_CTRL |
|---|
| 800 | #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
|---|
| 801 | #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
|---|
| 802 | #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 |
|---|
| 803 | #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b |
|---|
| 804 | #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c |
|---|
| 805 | #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d |
|---|
| 806 | #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e |
|---|
| 807 | #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f |
|---|
| 808 | #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
|---|
| 809 | #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
|---|
| 810 | #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L |
|---|
| 811 | #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L |
|---|
| 812 | #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L |
|---|
| 813 | #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L |
|---|
| 814 | #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L |
|---|
| 815 | #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L |
|---|
| 816 | //DAGB0_RD_ADDR_DAGB_MAX_BURST0 |
|---|
| 817 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 |
|---|
| 818 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 |
|---|
| 819 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 |
|---|
| 820 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc |
|---|
| 821 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 |
|---|
| 822 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 |
|---|
| 823 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 |
|---|
| 824 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c |
|---|
| 825 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL |
|---|
| 826 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L |
|---|
| 827 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L |
|---|
| 828 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L |
|---|
| 829 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L |
|---|
| 830 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L |
|---|
| 831 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L |
|---|
| 832 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L |
|---|
| 833 | //DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 |
|---|
| 834 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 |
|---|
| 835 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 |
|---|
| 836 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 |
|---|
| 837 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc |
|---|
| 838 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 |
|---|
| 839 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 |
|---|
| 840 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 |
|---|
| 841 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c |
|---|
| 842 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL |
|---|
| 843 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L |
|---|
| 844 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L |
|---|
| 845 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L |
|---|
| 846 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L |
|---|
| 847 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L |
|---|
| 848 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L |
|---|
| 849 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L |
|---|
| 850 | //DAGB0_RD_ADDR_DAGB_MAX_BURST1 |
|---|
| 851 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 |
|---|
| 852 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 |
|---|
| 853 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 |
|---|
| 854 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc |
|---|
| 855 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 |
|---|
| 856 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 |
|---|
| 857 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 |
|---|
| 858 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c |
|---|
| 859 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL |
|---|
| 860 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L |
|---|
| 861 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L |
|---|
| 862 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L |
|---|
| 863 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L |
|---|
| 864 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L |
|---|
| 865 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L |
|---|
| 866 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L |
|---|
| 867 | //DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 |
|---|
| 868 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 |
|---|
| 869 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 |
|---|
| 870 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 |
|---|
| 871 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc |
|---|
| 872 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 |
|---|
| 873 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 |
|---|
| 874 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 |
|---|
| 875 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c |
|---|
| 876 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL |
|---|
| 877 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L |
|---|
| 878 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L |
|---|
| 879 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L |
|---|
| 880 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L |
|---|
| 881 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L |
|---|
| 882 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L |
|---|
| 883 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L |
|---|
| 884 | //DAGB0_RD_ADDR_DAGB_MAX_BURST2 |
|---|
| 885 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 |
|---|
| 886 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 |
|---|
| 887 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 |
|---|
| 888 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc |
|---|
| 889 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 |
|---|
| 890 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 |
|---|
| 891 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 |
|---|
| 892 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c |
|---|
| 893 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL |
|---|
| 894 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L |
|---|
| 895 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L |
|---|
| 896 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L |
|---|
| 897 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L |
|---|
| 898 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L |
|---|
| 899 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L |
|---|
| 900 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L |
|---|
| 901 | //DAGB0_RD_ADDR_DAGB_LAZY_TIMER2 |
|---|
| 902 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 |
|---|
| 903 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 |
|---|
| 904 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 |
|---|
| 905 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc |
|---|
| 906 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 |
|---|
| 907 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 |
|---|
| 908 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 |
|---|
| 909 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c |
|---|
| 910 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL |
|---|
| 911 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L |
|---|
| 912 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L |
|---|
| 913 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L |
|---|
| 914 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L |
|---|
| 915 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L |
|---|
| 916 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L |
|---|
| 917 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L |
|---|
| 918 | //DAGB0_RD_ADDR_DAGB_MAX_BURST3 |
|---|
| 919 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0 |
|---|
| 920 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4 |
|---|
| 921 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8 |
|---|
| 922 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc |
|---|
| 923 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10 |
|---|
| 924 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14 |
|---|
| 925 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18 |
|---|
| 926 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c |
|---|
| 927 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL |
|---|
| 928 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L |
|---|
| 929 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L |
|---|
| 930 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L |
|---|
| 931 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L |
|---|
| 932 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L |
|---|
| 933 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L |
|---|
| 934 | #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L |
|---|
| 935 | //DAGB0_RD_ADDR_DAGB_LAZY_TIMER3 |
|---|
| 936 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0 |
|---|
| 937 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4 |
|---|
| 938 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8 |
|---|
| 939 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc |
|---|
| 940 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10 |
|---|
| 941 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14 |
|---|
| 942 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18 |
|---|
| 943 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c |
|---|
| 944 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL |
|---|
| 945 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L |
|---|
| 946 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L |
|---|
| 947 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L |
|---|
| 948 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L |
|---|
| 949 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L |
|---|
| 950 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L |
|---|
| 951 | #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L |
|---|
| 952 | //DAGB0_RD_VC0_CNTL |
|---|
| 953 | #define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 |
|---|
| 954 | #define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 |
|---|
| 955 | #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
|---|
| 956 | #define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc |
|---|
| 957 | #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
|---|
| 958 | #define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 |
|---|
| 959 | #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
|---|
| 960 | #define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 |
|---|
| 961 | #define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL |
|---|
| 962 | #define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L |
|---|
| 963 | #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
|---|
| 964 | #define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L |
|---|
| 965 | #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
|---|
| 966 | #define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L |
|---|
| 967 | #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
|---|
| 968 | #define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L |
|---|
| 969 | //DAGB0_RD_VC1_CNTL |
|---|
| 970 | #define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 |
|---|
| 971 | #define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 |
|---|
| 972 | #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
|---|
| 973 | #define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc |
|---|
| 974 | #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
|---|
| 975 | #define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 |
|---|
| 976 | #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
|---|
| 977 | #define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 |
|---|
| 978 | #define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL |
|---|
| 979 | #define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L |
|---|
| 980 | #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
|---|
| 981 | #define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L |
|---|
| 982 | #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
|---|
| 983 | #define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L |
|---|
| 984 | #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
|---|
| 985 | #define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L |
|---|
| 986 | //DAGB0_RD_VC2_CNTL |
|---|
| 987 | #define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 |
|---|
| 988 | #define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 |
|---|
| 989 | #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
|---|
| 990 | #define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc |
|---|
| 991 | #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
|---|
| 992 | #define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 |
|---|
| 993 | #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
|---|
| 994 | #define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 |
|---|
| 995 | #define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL |
|---|
| 996 | #define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L |
|---|
| 997 | #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
|---|
| 998 | #define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L |
|---|
| 999 | #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
|---|
| 1000 | #define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L |
|---|
| 1001 | #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
|---|
| 1002 | #define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L |
|---|
| 1003 | //DAGB0_RD_VC3_CNTL |
|---|
| 1004 | #define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 |
|---|
| 1005 | #define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 |
|---|
| 1006 | #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
|---|
| 1007 | #define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc |
|---|
| 1008 | #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
|---|
| 1009 | #define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 |
|---|
| 1010 | #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
|---|
| 1011 | #define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 |
|---|
| 1012 | #define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL |
|---|
| 1013 | #define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L |
|---|
| 1014 | #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
|---|
| 1015 | #define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L |
|---|
| 1016 | #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
|---|
| 1017 | #define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L |
|---|
| 1018 | #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
|---|
| 1019 | #define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L |
|---|
| 1020 | //DAGB0_RD_VC4_CNTL |
|---|
| 1021 | #define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 |
|---|
| 1022 | #define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 |
|---|
| 1023 | #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
|---|
| 1024 | #define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc |
|---|
| 1025 | #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
|---|
| 1026 | #define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 |
|---|
| 1027 | #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
|---|
| 1028 | #define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 |
|---|
| 1029 | #define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL |
|---|
| 1030 | #define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L |
|---|
| 1031 | #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
|---|
| 1032 | #define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L |
|---|
| 1033 | #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
|---|
| 1034 | #define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L |
|---|
| 1035 | #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
|---|
| 1036 | #define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L |
|---|
| 1037 | //DAGB0_RD_VC5_CNTL |
|---|
| 1038 | #define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 |
|---|
| 1039 | #define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 |
|---|
| 1040 | #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
|---|
| 1041 | #define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc |
|---|
| 1042 | #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
|---|
| 1043 | #define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 |
|---|
| 1044 | #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
|---|
| 1045 | #define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 |
|---|
| 1046 | #define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL |
|---|
| 1047 | #define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L |
|---|
| 1048 | #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
|---|
| 1049 | #define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L |
|---|
| 1050 | #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
|---|
| 1051 | #define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L |
|---|
| 1052 | #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
|---|
| 1053 | #define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L |
|---|
| 1054 | //DAGB0_RD_VC6_CNTL |
|---|
| 1055 | #define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 |
|---|
| 1056 | #define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 |
|---|
| 1057 | #define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
|---|
| 1058 | #define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT 0xc |
|---|
| 1059 | #define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
|---|
| 1060 | #define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 |
|---|
| 1061 | #define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
|---|
| 1062 | #define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 |
|---|
| 1063 | #define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL |
|---|
| 1064 | #define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L |
|---|
| 1065 | #define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
|---|
| 1066 | #define DAGB0_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L |
|---|
| 1067 | #define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
|---|
| 1068 | #define DAGB0_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L |
|---|
| 1069 | #define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
|---|
| 1070 | #define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L |
|---|
| 1071 | //DAGB0_RD_VC7_CNTL |
|---|
| 1072 | #define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 |
|---|
| 1073 | #define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 |
|---|
| 1074 | #define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
|---|
| 1075 | #define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT 0xc |
|---|
| 1076 | #define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
|---|
| 1077 | #define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 |
|---|
| 1078 | #define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
|---|
| 1079 | #define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 |
|---|
| 1080 | #define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL |
|---|
| 1081 | #define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L |
|---|
| 1082 | #define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
|---|
| 1083 | #define DAGB0_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L |
|---|
| 1084 | #define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
|---|
| 1085 | #define DAGB0_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L |
|---|
| 1086 | #define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
|---|
| 1087 | #define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L |
|---|
| 1088 | //DAGB0_RD_CNTL_MISC |
|---|
| 1089 | #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 |
|---|
| 1090 | #define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 |
|---|
| 1091 | #define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd |
|---|
| 1092 | #define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 |
|---|
| 1093 | #define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 |
|---|
| 1094 | #define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 |
|---|
| 1095 | #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL |
|---|
| 1096 | #define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L |
|---|
| 1097 | #define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L |
|---|
| 1098 | #define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L |
|---|
| 1099 | #define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L |
|---|
| 1100 | #define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L |
|---|
| 1101 | //DAGB0_RD_TLB_CREDIT |
|---|
| 1102 | #define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0 |
|---|
| 1103 | #define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5 |
|---|
| 1104 | #define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa |
|---|
| 1105 | #define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf |
|---|
| 1106 | #define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14 |
|---|
| 1107 | #define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19 |
|---|
| 1108 | #define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL |
|---|
| 1109 | #define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L |
|---|
| 1110 | #define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L |
|---|
| 1111 | #define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L |
|---|
| 1112 | #define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L |
|---|
| 1113 | #define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L |
|---|
| 1114 | //DAGB0_RDCLI_ASK_PENDING |
|---|
| 1115 | #define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 |
|---|
| 1116 | #define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL |
|---|
| 1117 | //DAGB0_RDCLI_GO_PENDING |
|---|
| 1118 | #define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 |
|---|
| 1119 | #define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL |
|---|
| 1120 | //DAGB0_RDCLI_GBLSEND_PENDING |
|---|
| 1121 | #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 |
|---|
| 1122 | #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL |
|---|
| 1123 | //DAGB0_RDCLI_TLB_PENDING |
|---|
| 1124 | #define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 |
|---|
| 1125 | #define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL |
|---|
| 1126 | //DAGB0_RDCLI_OARB_PENDING |
|---|
| 1127 | #define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 |
|---|
| 1128 | #define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL |
|---|
| 1129 | //DAGB0_RDCLI_OSD_PENDING |
|---|
| 1130 | #define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 |
|---|
| 1131 | #define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL |
|---|
| 1132 | //DAGB0_WRCLI0 |
|---|
| 1133 | #define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1134 | #define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1135 | #define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4 |
|---|
| 1136 | #define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8 |
|---|
| 1137 | #define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1138 | #define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd |
|---|
| 1139 | #define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1140 | #define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16 |
|---|
| 1141 | #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1142 | #define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a |
|---|
| 1143 | #define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1144 | #define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1145 | #define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L |
|---|
| 1146 | #define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L |
|---|
| 1147 | #define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1148 | #define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L |
|---|
| 1149 | #define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1150 | #define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L |
|---|
| 1151 | #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1152 | #define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L |
|---|
| 1153 | //DAGB0_WRCLI1 |
|---|
| 1154 | #define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1155 | #define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1156 | #define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4 |
|---|
| 1157 | #define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8 |
|---|
| 1158 | #define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1159 | #define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd |
|---|
| 1160 | #define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1161 | #define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16 |
|---|
| 1162 | #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1163 | #define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a |
|---|
| 1164 | #define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1165 | #define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1166 | #define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L |
|---|
| 1167 | #define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L |
|---|
| 1168 | #define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1169 | #define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L |
|---|
| 1170 | #define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1171 | #define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L |
|---|
| 1172 | #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1173 | #define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L |
|---|
| 1174 | //DAGB0_WRCLI2 |
|---|
| 1175 | #define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1176 | #define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1177 | #define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4 |
|---|
| 1178 | #define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8 |
|---|
| 1179 | #define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1180 | #define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd |
|---|
| 1181 | #define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1182 | #define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16 |
|---|
| 1183 | #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1184 | #define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a |
|---|
| 1185 | #define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1186 | #define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1187 | #define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L |
|---|
| 1188 | #define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L |
|---|
| 1189 | #define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1190 | #define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L |
|---|
| 1191 | #define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1192 | #define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L |
|---|
| 1193 | #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1194 | #define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L |
|---|
| 1195 | //DAGB0_WRCLI3 |
|---|
| 1196 | #define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1197 | #define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1198 | #define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4 |
|---|
| 1199 | #define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8 |
|---|
| 1200 | #define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1201 | #define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd |
|---|
| 1202 | #define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1203 | #define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16 |
|---|
| 1204 | #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1205 | #define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a |
|---|
| 1206 | #define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1207 | #define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1208 | #define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L |
|---|
| 1209 | #define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L |
|---|
| 1210 | #define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1211 | #define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L |
|---|
| 1212 | #define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1213 | #define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L |
|---|
| 1214 | #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1215 | #define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L |
|---|
| 1216 | //DAGB0_WRCLI4 |
|---|
| 1217 | #define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1218 | #define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1219 | #define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4 |
|---|
| 1220 | #define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8 |
|---|
| 1221 | #define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1222 | #define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd |
|---|
| 1223 | #define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1224 | #define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16 |
|---|
| 1225 | #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1226 | #define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a |
|---|
| 1227 | #define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1228 | #define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1229 | #define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L |
|---|
| 1230 | #define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L |
|---|
| 1231 | #define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1232 | #define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L |
|---|
| 1233 | #define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1234 | #define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L |
|---|
| 1235 | #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1236 | #define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L |
|---|
| 1237 | //DAGB0_WRCLI5 |
|---|
| 1238 | #define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1239 | #define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1240 | #define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4 |
|---|
| 1241 | #define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8 |
|---|
| 1242 | #define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1243 | #define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd |
|---|
| 1244 | #define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1245 | #define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16 |
|---|
| 1246 | #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1247 | #define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a |
|---|
| 1248 | #define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1249 | #define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1250 | #define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L |
|---|
| 1251 | #define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L |
|---|
| 1252 | #define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1253 | #define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L |
|---|
| 1254 | #define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1255 | #define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L |
|---|
| 1256 | #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1257 | #define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L |
|---|
| 1258 | //DAGB0_WRCLI6 |
|---|
| 1259 | #define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1260 | #define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1261 | #define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4 |
|---|
| 1262 | #define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8 |
|---|
| 1263 | #define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1264 | #define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd |
|---|
| 1265 | #define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1266 | #define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16 |
|---|
| 1267 | #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1268 | #define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a |
|---|
| 1269 | #define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1270 | #define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1271 | #define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L |
|---|
| 1272 | #define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L |
|---|
| 1273 | #define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1274 | #define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L |
|---|
| 1275 | #define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1276 | #define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L |
|---|
| 1277 | #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1278 | #define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L |
|---|
| 1279 | //DAGB0_WRCLI7 |
|---|
| 1280 | #define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1281 | #define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1282 | #define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4 |
|---|
| 1283 | #define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8 |
|---|
| 1284 | #define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1285 | #define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd |
|---|
| 1286 | #define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1287 | #define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16 |
|---|
| 1288 | #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1289 | #define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a |
|---|
| 1290 | #define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1291 | #define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1292 | #define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L |
|---|
| 1293 | #define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L |
|---|
| 1294 | #define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1295 | #define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L |
|---|
| 1296 | #define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1297 | #define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L |
|---|
| 1298 | #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1299 | #define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L |
|---|
| 1300 | //DAGB0_WRCLI8 |
|---|
| 1301 | #define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1302 | #define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1303 | #define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4 |
|---|
| 1304 | #define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8 |
|---|
| 1305 | #define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1306 | #define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd |
|---|
| 1307 | #define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1308 | #define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16 |
|---|
| 1309 | #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1310 | #define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a |
|---|
| 1311 | #define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1312 | #define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1313 | #define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L |
|---|
| 1314 | #define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L |
|---|
| 1315 | #define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1316 | #define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L |
|---|
| 1317 | #define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1318 | #define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L |
|---|
| 1319 | #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1320 | #define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L |
|---|
| 1321 | //DAGB0_WRCLI9 |
|---|
| 1322 | #define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1323 | #define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1324 | #define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4 |
|---|
| 1325 | #define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8 |
|---|
| 1326 | #define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1327 | #define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd |
|---|
| 1328 | #define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1329 | #define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16 |
|---|
| 1330 | #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1331 | #define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a |
|---|
| 1332 | #define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1333 | #define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1334 | #define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L |
|---|
| 1335 | #define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L |
|---|
| 1336 | #define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1337 | #define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L |
|---|
| 1338 | #define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1339 | #define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L |
|---|
| 1340 | #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1341 | #define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L |
|---|
| 1342 | //DAGB0_WRCLI10 |
|---|
| 1343 | #define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1344 | #define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1345 | #define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4 |
|---|
| 1346 | #define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8 |
|---|
| 1347 | #define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1348 | #define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd |
|---|
| 1349 | #define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1350 | #define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16 |
|---|
| 1351 | #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1352 | #define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a |
|---|
| 1353 | #define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1354 | #define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1355 | #define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L |
|---|
| 1356 | #define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L |
|---|
| 1357 | #define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1358 | #define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L |
|---|
| 1359 | #define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1360 | #define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L |
|---|
| 1361 | #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1362 | #define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L |
|---|
| 1363 | //DAGB0_WRCLI11 |
|---|
| 1364 | #define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1365 | #define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1366 | #define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4 |
|---|
| 1367 | #define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8 |
|---|
| 1368 | #define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1369 | #define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd |
|---|
| 1370 | #define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1371 | #define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16 |
|---|
| 1372 | #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1373 | #define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a |
|---|
| 1374 | #define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1375 | #define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1376 | #define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L |
|---|
| 1377 | #define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L |
|---|
| 1378 | #define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1379 | #define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L |
|---|
| 1380 | #define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1381 | #define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L |
|---|
| 1382 | #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1383 | #define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L |
|---|
| 1384 | //DAGB0_WRCLI12 |
|---|
| 1385 | #define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1386 | #define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1387 | #define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4 |
|---|
| 1388 | #define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8 |
|---|
| 1389 | #define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1390 | #define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd |
|---|
| 1391 | #define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1392 | #define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16 |
|---|
| 1393 | #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1394 | #define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a |
|---|
| 1395 | #define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1396 | #define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1397 | #define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L |
|---|
| 1398 | #define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L |
|---|
| 1399 | #define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1400 | #define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L |
|---|
| 1401 | #define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1402 | #define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L |
|---|
| 1403 | #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1404 | #define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L |
|---|
| 1405 | //DAGB0_WRCLI13 |
|---|
| 1406 | #define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1407 | #define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1408 | #define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4 |
|---|
| 1409 | #define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8 |
|---|
| 1410 | #define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1411 | #define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd |
|---|
| 1412 | #define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1413 | #define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16 |
|---|
| 1414 | #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1415 | #define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a |
|---|
| 1416 | #define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1417 | #define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1418 | #define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L |
|---|
| 1419 | #define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L |
|---|
| 1420 | #define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1421 | #define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L |
|---|
| 1422 | #define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1423 | #define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L |
|---|
| 1424 | #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1425 | #define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L |
|---|
| 1426 | //DAGB0_WRCLI14 |
|---|
| 1427 | #define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1428 | #define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1429 | #define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4 |
|---|
| 1430 | #define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8 |
|---|
| 1431 | #define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1432 | #define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd |
|---|
| 1433 | #define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1434 | #define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16 |
|---|
| 1435 | #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1436 | #define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a |
|---|
| 1437 | #define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1438 | #define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1439 | #define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L |
|---|
| 1440 | #define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L |
|---|
| 1441 | #define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1442 | #define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L |
|---|
| 1443 | #define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1444 | #define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L |
|---|
| 1445 | #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1446 | #define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L |
|---|
| 1447 | //DAGB0_WRCLI15 |
|---|
| 1448 | #define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1449 | #define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1450 | #define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4 |
|---|
| 1451 | #define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8 |
|---|
| 1452 | #define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1453 | #define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd |
|---|
| 1454 | #define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1455 | #define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16 |
|---|
| 1456 | #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1457 | #define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a |
|---|
| 1458 | #define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1459 | #define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1460 | #define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L |
|---|
| 1461 | #define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L |
|---|
| 1462 | #define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1463 | #define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L |
|---|
| 1464 | #define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1465 | #define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L |
|---|
| 1466 | #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1467 | #define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L |
|---|
| 1468 | //DAGB0_WRCLI16 |
|---|
| 1469 | #define DAGB0_WRCLI16__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1470 | #define DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1471 | #define DAGB0_WRCLI16__URG_HIGH__SHIFT 0x4 |
|---|
| 1472 | #define DAGB0_WRCLI16__URG_LOW__SHIFT 0x8 |
|---|
| 1473 | #define DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1474 | #define DAGB0_WRCLI16__MAX_BW__SHIFT 0xd |
|---|
| 1475 | #define DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1476 | #define DAGB0_WRCLI16__MIN_BW__SHIFT 0x16 |
|---|
| 1477 | #define DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1478 | #define DAGB0_WRCLI16__MAX_OSD__SHIFT 0x1a |
|---|
| 1479 | #define DAGB0_WRCLI16__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1480 | #define DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1481 | #define DAGB0_WRCLI16__URG_HIGH_MASK 0x000000F0L |
|---|
| 1482 | #define DAGB0_WRCLI16__URG_LOW_MASK 0x00000F00L |
|---|
| 1483 | #define DAGB0_WRCLI16__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1484 | #define DAGB0_WRCLI16__MAX_BW_MASK 0x001FE000L |
|---|
| 1485 | #define DAGB0_WRCLI16__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1486 | #define DAGB0_WRCLI16__MIN_BW_MASK 0x01C00000L |
|---|
| 1487 | #define DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1488 | #define DAGB0_WRCLI16__MAX_OSD_MASK 0xFC000000L |
|---|
| 1489 | //DAGB0_WRCLI17 |
|---|
| 1490 | #define DAGB0_WRCLI17__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1491 | #define DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1492 | #define DAGB0_WRCLI17__URG_HIGH__SHIFT 0x4 |
|---|
| 1493 | #define DAGB0_WRCLI17__URG_LOW__SHIFT 0x8 |
|---|
| 1494 | #define DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1495 | #define DAGB0_WRCLI17__MAX_BW__SHIFT 0xd |
|---|
| 1496 | #define DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1497 | #define DAGB0_WRCLI17__MIN_BW__SHIFT 0x16 |
|---|
| 1498 | #define DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1499 | #define DAGB0_WRCLI17__MAX_OSD__SHIFT 0x1a |
|---|
| 1500 | #define DAGB0_WRCLI17__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1501 | #define DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1502 | #define DAGB0_WRCLI17__URG_HIGH_MASK 0x000000F0L |
|---|
| 1503 | #define DAGB0_WRCLI17__URG_LOW_MASK 0x00000F00L |
|---|
| 1504 | #define DAGB0_WRCLI17__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1505 | #define DAGB0_WRCLI17__MAX_BW_MASK 0x001FE000L |
|---|
| 1506 | #define DAGB0_WRCLI17__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1507 | #define DAGB0_WRCLI17__MIN_BW_MASK 0x01C00000L |
|---|
| 1508 | #define DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1509 | #define DAGB0_WRCLI17__MAX_OSD_MASK 0xFC000000L |
|---|
| 1510 | //DAGB0_WRCLI18 |
|---|
| 1511 | #define DAGB0_WRCLI18__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1512 | #define DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1513 | #define DAGB0_WRCLI18__URG_HIGH__SHIFT 0x4 |
|---|
| 1514 | #define DAGB0_WRCLI18__URG_LOW__SHIFT 0x8 |
|---|
| 1515 | #define DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1516 | #define DAGB0_WRCLI18__MAX_BW__SHIFT 0xd |
|---|
| 1517 | #define DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1518 | #define DAGB0_WRCLI18__MIN_BW__SHIFT 0x16 |
|---|
| 1519 | #define DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1520 | #define DAGB0_WRCLI18__MAX_OSD__SHIFT 0x1a |
|---|
| 1521 | #define DAGB0_WRCLI18__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1522 | #define DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1523 | #define DAGB0_WRCLI18__URG_HIGH_MASK 0x000000F0L |
|---|
| 1524 | #define DAGB0_WRCLI18__URG_LOW_MASK 0x00000F00L |
|---|
| 1525 | #define DAGB0_WRCLI18__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1526 | #define DAGB0_WRCLI18__MAX_BW_MASK 0x001FE000L |
|---|
| 1527 | #define DAGB0_WRCLI18__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1528 | #define DAGB0_WRCLI18__MIN_BW_MASK 0x01C00000L |
|---|
| 1529 | #define DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1530 | #define DAGB0_WRCLI18__MAX_OSD_MASK 0xFC000000L |
|---|
| 1531 | //DAGB0_WRCLI19 |
|---|
| 1532 | #define DAGB0_WRCLI19__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1533 | #define DAGB0_WRCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1534 | #define DAGB0_WRCLI19__URG_HIGH__SHIFT 0x4 |
|---|
| 1535 | #define DAGB0_WRCLI19__URG_LOW__SHIFT 0x8 |
|---|
| 1536 | #define DAGB0_WRCLI19__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1537 | #define DAGB0_WRCLI19__MAX_BW__SHIFT 0xd |
|---|
| 1538 | #define DAGB0_WRCLI19__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1539 | #define DAGB0_WRCLI19__MIN_BW__SHIFT 0x16 |
|---|
| 1540 | #define DAGB0_WRCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1541 | #define DAGB0_WRCLI19__MAX_OSD__SHIFT 0x1a |
|---|
| 1542 | #define DAGB0_WRCLI19__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1543 | #define DAGB0_WRCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1544 | #define DAGB0_WRCLI19__URG_HIGH_MASK 0x000000F0L |
|---|
| 1545 | #define DAGB0_WRCLI19__URG_LOW_MASK 0x00000F00L |
|---|
| 1546 | #define DAGB0_WRCLI19__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1547 | #define DAGB0_WRCLI19__MAX_BW_MASK 0x001FE000L |
|---|
| 1548 | #define DAGB0_WRCLI19__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1549 | #define DAGB0_WRCLI19__MIN_BW_MASK 0x01C00000L |
|---|
| 1550 | #define DAGB0_WRCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1551 | #define DAGB0_WRCLI19__MAX_OSD_MASK 0xFC000000L |
|---|
| 1552 | //DAGB0_WRCLI20 |
|---|
| 1553 | #define DAGB0_WRCLI20__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1554 | #define DAGB0_WRCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1555 | #define DAGB0_WRCLI20__URG_HIGH__SHIFT 0x4 |
|---|
| 1556 | #define DAGB0_WRCLI20__URG_LOW__SHIFT 0x8 |
|---|
| 1557 | #define DAGB0_WRCLI20__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1558 | #define DAGB0_WRCLI20__MAX_BW__SHIFT 0xd |
|---|
| 1559 | #define DAGB0_WRCLI20__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1560 | #define DAGB0_WRCLI20__MIN_BW__SHIFT 0x16 |
|---|
| 1561 | #define DAGB0_WRCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1562 | #define DAGB0_WRCLI20__MAX_OSD__SHIFT 0x1a |
|---|
| 1563 | #define DAGB0_WRCLI20__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1564 | #define DAGB0_WRCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1565 | #define DAGB0_WRCLI20__URG_HIGH_MASK 0x000000F0L |
|---|
| 1566 | #define DAGB0_WRCLI20__URG_LOW_MASK 0x00000F00L |
|---|
| 1567 | #define DAGB0_WRCLI20__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1568 | #define DAGB0_WRCLI20__MAX_BW_MASK 0x001FE000L |
|---|
| 1569 | #define DAGB0_WRCLI20__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1570 | #define DAGB0_WRCLI20__MIN_BW_MASK 0x01C00000L |
|---|
| 1571 | #define DAGB0_WRCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1572 | #define DAGB0_WRCLI20__MAX_OSD_MASK 0xFC000000L |
|---|
| 1573 | //DAGB0_WRCLI21 |
|---|
| 1574 | #define DAGB0_WRCLI21__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1575 | #define DAGB0_WRCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1576 | #define DAGB0_WRCLI21__URG_HIGH__SHIFT 0x4 |
|---|
| 1577 | #define DAGB0_WRCLI21__URG_LOW__SHIFT 0x8 |
|---|
| 1578 | #define DAGB0_WRCLI21__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1579 | #define DAGB0_WRCLI21__MAX_BW__SHIFT 0xd |
|---|
| 1580 | #define DAGB0_WRCLI21__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1581 | #define DAGB0_WRCLI21__MIN_BW__SHIFT 0x16 |
|---|
| 1582 | #define DAGB0_WRCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1583 | #define DAGB0_WRCLI21__MAX_OSD__SHIFT 0x1a |
|---|
| 1584 | #define DAGB0_WRCLI21__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1585 | #define DAGB0_WRCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1586 | #define DAGB0_WRCLI21__URG_HIGH_MASK 0x000000F0L |
|---|
| 1587 | #define DAGB0_WRCLI21__URG_LOW_MASK 0x00000F00L |
|---|
| 1588 | #define DAGB0_WRCLI21__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1589 | #define DAGB0_WRCLI21__MAX_BW_MASK 0x001FE000L |
|---|
| 1590 | #define DAGB0_WRCLI21__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1591 | #define DAGB0_WRCLI21__MIN_BW_MASK 0x01C00000L |
|---|
| 1592 | #define DAGB0_WRCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1593 | #define DAGB0_WRCLI21__MAX_OSD_MASK 0xFC000000L |
|---|
| 1594 | //DAGB0_WRCLI22 |
|---|
| 1595 | #define DAGB0_WRCLI22__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1596 | #define DAGB0_WRCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1597 | #define DAGB0_WRCLI22__URG_HIGH__SHIFT 0x4 |
|---|
| 1598 | #define DAGB0_WRCLI22__URG_LOW__SHIFT 0x8 |
|---|
| 1599 | #define DAGB0_WRCLI22__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1600 | #define DAGB0_WRCLI22__MAX_BW__SHIFT 0xd |
|---|
| 1601 | #define DAGB0_WRCLI22__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1602 | #define DAGB0_WRCLI22__MIN_BW__SHIFT 0x16 |
|---|
| 1603 | #define DAGB0_WRCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1604 | #define DAGB0_WRCLI22__MAX_OSD__SHIFT 0x1a |
|---|
| 1605 | #define DAGB0_WRCLI22__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1606 | #define DAGB0_WRCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1607 | #define DAGB0_WRCLI22__URG_HIGH_MASK 0x000000F0L |
|---|
| 1608 | #define DAGB0_WRCLI22__URG_LOW_MASK 0x00000F00L |
|---|
| 1609 | #define DAGB0_WRCLI22__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1610 | #define DAGB0_WRCLI22__MAX_BW_MASK 0x001FE000L |
|---|
| 1611 | #define DAGB0_WRCLI22__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1612 | #define DAGB0_WRCLI22__MIN_BW_MASK 0x01C00000L |
|---|
| 1613 | #define DAGB0_WRCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1614 | #define DAGB0_WRCLI22__MAX_OSD_MASK 0xFC000000L |
|---|
| 1615 | //DAGB0_WRCLI23 |
|---|
| 1616 | #define DAGB0_WRCLI23__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1617 | #define DAGB0_WRCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1618 | #define DAGB0_WRCLI23__URG_HIGH__SHIFT 0x4 |
|---|
| 1619 | #define DAGB0_WRCLI23__URG_LOW__SHIFT 0x8 |
|---|
| 1620 | #define DAGB0_WRCLI23__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1621 | #define DAGB0_WRCLI23__MAX_BW__SHIFT 0xd |
|---|
| 1622 | #define DAGB0_WRCLI23__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1623 | #define DAGB0_WRCLI23__MIN_BW__SHIFT 0x16 |
|---|
| 1624 | #define DAGB0_WRCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1625 | #define DAGB0_WRCLI23__MAX_OSD__SHIFT 0x1a |
|---|
| 1626 | #define DAGB0_WRCLI23__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1627 | #define DAGB0_WRCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1628 | #define DAGB0_WRCLI23__URG_HIGH_MASK 0x000000F0L |
|---|
| 1629 | #define DAGB0_WRCLI23__URG_LOW_MASK 0x00000F00L |
|---|
| 1630 | #define DAGB0_WRCLI23__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1631 | #define DAGB0_WRCLI23__MAX_BW_MASK 0x001FE000L |
|---|
| 1632 | #define DAGB0_WRCLI23__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1633 | #define DAGB0_WRCLI23__MIN_BW_MASK 0x01C00000L |
|---|
| 1634 | #define DAGB0_WRCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1635 | #define DAGB0_WRCLI23__MAX_OSD_MASK 0xFC000000L |
|---|
| 1636 | //DAGB0_WRCLI24 |
|---|
| 1637 | #define DAGB0_WRCLI24__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1638 | #define DAGB0_WRCLI24__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1639 | #define DAGB0_WRCLI24__URG_HIGH__SHIFT 0x4 |
|---|
| 1640 | #define DAGB0_WRCLI24__URG_LOW__SHIFT 0x8 |
|---|
| 1641 | #define DAGB0_WRCLI24__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1642 | #define DAGB0_WRCLI24__MAX_BW__SHIFT 0xd |
|---|
| 1643 | #define DAGB0_WRCLI24__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1644 | #define DAGB0_WRCLI24__MIN_BW__SHIFT 0x16 |
|---|
| 1645 | #define DAGB0_WRCLI24__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1646 | #define DAGB0_WRCLI24__MAX_OSD__SHIFT 0x1a |
|---|
| 1647 | #define DAGB0_WRCLI24__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1648 | #define DAGB0_WRCLI24__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1649 | #define DAGB0_WRCLI24__URG_HIGH_MASK 0x000000F0L |
|---|
| 1650 | #define DAGB0_WRCLI24__URG_LOW_MASK 0x00000F00L |
|---|
| 1651 | #define DAGB0_WRCLI24__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1652 | #define DAGB0_WRCLI24__MAX_BW_MASK 0x001FE000L |
|---|
| 1653 | #define DAGB0_WRCLI24__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1654 | #define DAGB0_WRCLI24__MIN_BW_MASK 0x01C00000L |
|---|
| 1655 | #define DAGB0_WRCLI24__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1656 | #define DAGB0_WRCLI24__MAX_OSD_MASK 0xFC000000L |
|---|
| 1657 | //DAGB0_WRCLI25 |
|---|
| 1658 | #define DAGB0_WRCLI25__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1659 | #define DAGB0_WRCLI25__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1660 | #define DAGB0_WRCLI25__URG_HIGH__SHIFT 0x4 |
|---|
| 1661 | #define DAGB0_WRCLI25__URG_LOW__SHIFT 0x8 |
|---|
| 1662 | #define DAGB0_WRCLI25__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1663 | #define DAGB0_WRCLI25__MAX_BW__SHIFT 0xd |
|---|
| 1664 | #define DAGB0_WRCLI25__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1665 | #define DAGB0_WRCLI25__MIN_BW__SHIFT 0x16 |
|---|
| 1666 | #define DAGB0_WRCLI25__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1667 | #define DAGB0_WRCLI25__MAX_OSD__SHIFT 0x1a |
|---|
| 1668 | #define DAGB0_WRCLI25__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1669 | #define DAGB0_WRCLI25__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1670 | #define DAGB0_WRCLI25__URG_HIGH_MASK 0x000000F0L |
|---|
| 1671 | #define DAGB0_WRCLI25__URG_LOW_MASK 0x00000F00L |
|---|
| 1672 | #define DAGB0_WRCLI25__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1673 | #define DAGB0_WRCLI25__MAX_BW_MASK 0x001FE000L |
|---|
| 1674 | #define DAGB0_WRCLI25__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1675 | #define DAGB0_WRCLI25__MIN_BW_MASK 0x01C00000L |
|---|
| 1676 | #define DAGB0_WRCLI25__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1677 | #define DAGB0_WRCLI25__MAX_OSD_MASK 0xFC000000L |
|---|
| 1678 | //DAGB0_WRCLI26 |
|---|
| 1679 | #define DAGB0_WRCLI26__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1680 | #define DAGB0_WRCLI26__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1681 | #define DAGB0_WRCLI26__URG_HIGH__SHIFT 0x4 |
|---|
| 1682 | #define DAGB0_WRCLI26__URG_LOW__SHIFT 0x8 |
|---|
| 1683 | #define DAGB0_WRCLI26__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1684 | #define DAGB0_WRCLI26__MAX_BW__SHIFT 0xd |
|---|
| 1685 | #define DAGB0_WRCLI26__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1686 | #define DAGB0_WRCLI26__MIN_BW__SHIFT 0x16 |
|---|
| 1687 | #define DAGB0_WRCLI26__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1688 | #define DAGB0_WRCLI26__MAX_OSD__SHIFT 0x1a |
|---|
| 1689 | #define DAGB0_WRCLI26__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1690 | #define DAGB0_WRCLI26__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1691 | #define DAGB0_WRCLI26__URG_HIGH_MASK 0x000000F0L |
|---|
| 1692 | #define DAGB0_WRCLI26__URG_LOW_MASK 0x00000F00L |
|---|
| 1693 | #define DAGB0_WRCLI26__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1694 | #define DAGB0_WRCLI26__MAX_BW_MASK 0x001FE000L |
|---|
| 1695 | #define DAGB0_WRCLI26__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1696 | #define DAGB0_WRCLI26__MIN_BW_MASK 0x01C00000L |
|---|
| 1697 | #define DAGB0_WRCLI26__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1698 | #define DAGB0_WRCLI26__MAX_OSD_MASK 0xFC000000L |
|---|
| 1699 | //DAGB0_WRCLI27 |
|---|
| 1700 | #define DAGB0_WRCLI27__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1701 | #define DAGB0_WRCLI27__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1702 | #define DAGB0_WRCLI27__URG_HIGH__SHIFT 0x4 |
|---|
| 1703 | #define DAGB0_WRCLI27__URG_LOW__SHIFT 0x8 |
|---|
| 1704 | #define DAGB0_WRCLI27__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1705 | #define DAGB0_WRCLI27__MAX_BW__SHIFT 0xd |
|---|
| 1706 | #define DAGB0_WRCLI27__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1707 | #define DAGB0_WRCLI27__MIN_BW__SHIFT 0x16 |
|---|
| 1708 | #define DAGB0_WRCLI27__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1709 | #define DAGB0_WRCLI27__MAX_OSD__SHIFT 0x1a |
|---|
| 1710 | #define DAGB0_WRCLI27__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1711 | #define DAGB0_WRCLI27__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1712 | #define DAGB0_WRCLI27__URG_HIGH_MASK 0x000000F0L |
|---|
| 1713 | #define DAGB0_WRCLI27__URG_LOW_MASK 0x00000F00L |
|---|
| 1714 | #define DAGB0_WRCLI27__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1715 | #define DAGB0_WRCLI27__MAX_BW_MASK 0x001FE000L |
|---|
| 1716 | #define DAGB0_WRCLI27__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1717 | #define DAGB0_WRCLI27__MIN_BW_MASK 0x01C00000L |
|---|
| 1718 | #define DAGB0_WRCLI27__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1719 | #define DAGB0_WRCLI27__MAX_OSD_MASK 0xFC000000L |
|---|
| 1720 | //DAGB0_WRCLI28 |
|---|
| 1721 | #define DAGB0_WRCLI28__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1722 | #define DAGB0_WRCLI28__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1723 | #define DAGB0_WRCLI28__URG_HIGH__SHIFT 0x4 |
|---|
| 1724 | #define DAGB0_WRCLI28__URG_LOW__SHIFT 0x8 |
|---|
| 1725 | #define DAGB0_WRCLI28__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1726 | #define DAGB0_WRCLI28__MAX_BW__SHIFT 0xd |
|---|
| 1727 | #define DAGB0_WRCLI28__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1728 | #define DAGB0_WRCLI28__MIN_BW__SHIFT 0x16 |
|---|
| 1729 | #define DAGB0_WRCLI28__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1730 | #define DAGB0_WRCLI28__MAX_OSD__SHIFT 0x1a |
|---|
| 1731 | #define DAGB0_WRCLI28__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1732 | #define DAGB0_WRCLI28__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1733 | #define DAGB0_WRCLI28__URG_HIGH_MASK 0x000000F0L |
|---|
| 1734 | #define DAGB0_WRCLI28__URG_LOW_MASK 0x00000F00L |
|---|
| 1735 | #define DAGB0_WRCLI28__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1736 | #define DAGB0_WRCLI28__MAX_BW_MASK 0x001FE000L |
|---|
| 1737 | #define DAGB0_WRCLI28__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1738 | #define DAGB0_WRCLI28__MIN_BW_MASK 0x01C00000L |
|---|
| 1739 | #define DAGB0_WRCLI28__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1740 | #define DAGB0_WRCLI28__MAX_OSD_MASK 0xFC000000L |
|---|
| 1741 | //DAGB0_WRCLI29 |
|---|
| 1742 | #define DAGB0_WRCLI29__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1743 | #define DAGB0_WRCLI29__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1744 | #define DAGB0_WRCLI29__URG_HIGH__SHIFT 0x4 |
|---|
| 1745 | #define DAGB0_WRCLI29__URG_LOW__SHIFT 0x8 |
|---|
| 1746 | #define DAGB0_WRCLI29__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1747 | #define DAGB0_WRCLI29__MAX_BW__SHIFT 0xd |
|---|
| 1748 | #define DAGB0_WRCLI29__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1749 | #define DAGB0_WRCLI29__MIN_BW__SHIFT 0x16 |
|---|
| 1750 | #define DAGB0_WRCLI29__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1751 | #define DAGB0_WRCLI29__MAX_OSD__SHIFT 0x1a |
|---|
| 1752 | #define DAGB0_WRCLI29__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1753 | #define DAGB0_WRCLI29__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1754 | #define DAGB0_WRCLI29__URG_HIGH_MASK 0x000000F0L |
|---|
| 1755 | #define DAGB0_WRCLI29__URG_LOW_MASK 0x00000F00L |
|---|
| 1756 | #define DAGB0_WRCLI29__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1757 | #define DAGB0_WRCLI29__MAX_BW_MASK 0x001FE000L |
|---|
| 1758 | #define DAGB0_WRCLI29__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1759 | #define DAGB0_WRCLI29__MIN_BW_MASK 0x01C00000L |
|---|
| 1760 | #define DAGB0_WRCLI29__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1761 | #define DAGB0_WRCLI29__MAX_OSD_MASK 0xFC000000L |
|---|
| 1762 | //DAGB0_WRCLI30 |
|---|
| 1763 | #define DAGB0_WRCLI30__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1764 | #define DAGB0_WRCLI30__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1765 | #define DAGB0_WRCLI30__URG_HIGH__SHIFT 0x4 |
|---|
| 1766 | #define DAGB0_WRCLI30__URG_LOW__SHIFT 0x8 |
|---|
| 1767 | #define DAGB0_WRCLI30__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1768 | #define DAGB0_WRCLI30__MAX_BW__SHIFT 0xd |
|---|
| 1769 | #define DAGB0_WRCLI30__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1770 | #define DAGB0_WRCLI30__MIN_BW__SHIFT 0x16 |
|---|
| 1771 | #define DAGB0_WRCLI30__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1772 | #define DAGB0_WRCLI30__MAX_OSD__SHIFT 0x1a |
|---|
| 1773 | #define DAGB0_WRCLI30__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1774 | #define DAGB0_WRCLI30__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1775 | #define DAGB0_WRCLI30__URG_HIGH_MASK 0x000000F0L |
|---|
| 1776 | #define DAGB0_WRCLI30__URG_LOW_MASK 0x00000F00L |
|---|
| 1777 | #define DAGB0_WRCLI30__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1778 | #define DAGB0_WRCLI30__MAX_BW_MASK 0x001FE000L |
|---|
| 1779 | #define DAGB0_WRCLI30__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1780 | #define DAGB0_WRCLI30__MIN_BW_MASK 0x01C00000L |
|---|
| 1781 | #define DAGB0_WRCLI30__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1782 | #define DAGB0_WRCLI30__MAX_OSD_MASK 0xFC000000L |
|---|
| 1783 | //DAGB0_WRCLI31 |
|---|
| 1784 | #define DAGB0_WRCLI31__VIRT_CHAN__SHIFT 0x0 |
|---|
| 1785 | #define DAGB0_WRCLI31__CHECK_TLB_CREDIT__SHIFT 0x3 |
|---|
| 1786 | #define DAGB0_WRCLI31__URG_HIGH__SHIFT 0x4 |
|---|
| 1787 | #define DAGB0_WRCLI31__URG_LOW__SHIFT 0x8 |
|---|
| 1788 | #define DAGB0_WRCLI31__MAX_BW_ENABLE__SHIFT 0xc |
|---|
| 1789 | #define DAGB0_WRCLI31__MAX_BW__SHIFT 0xd |
|---|
| 1790 | #define DAGB0_WRCLI31__MIN_BW_ENABLE__SHIFT 0x15 |
|---|
| 1791 | #define DAGB0_WRCLI31__MIN_BW__SHIFT 0x16 |
|---|
| 1792 | #define DAGB0_WRCLI31__OSD_LIMITER_ENABLE__SHIFT 0x19 |
|---|
| 1793 | #define DAGB0_WRCLI31__MAX_OSD__SHIFT 0x1a |
|---|
| 1794 | #define DAGB0_WRCLI31__VIRT_CHAN_MASK 0x00000007L |
|---|
| 1795 | #define DAGB0_WRCLI31__CHECK_TLB_CREDIT_MASK 0x00000008L |
|---|
| 1796 | #define DAGB0_WRCLI31__URG_HIGH_MASK 0x000000F0L |
|---|
| 1797 | #define DAGB0_WRCLI31__URG_LOW_MASK 0x00000F00L |
|---|
| 1798 | #define DAGB0_WRCLI31__MAX_BW_ENABLE_MASK 0x00001000L |
|---|
| 1799 | #define DAGB0_WRCLI31__MAX_BW_MASK 0x001FE000L |
|---|
| 1800 | #define DAGB0_WRCLI31__MIN_BW_ENABLE_MASK 0x00200000L |
|---|
| 1801 | #define DAGB0_WRCLI31__MIN_BW_MASK 0x01C00000L |
|---|
| 1802 | #define DAGB0_WRCLI31__OSD_LIMITER_ENABLE_MASK 0x02000000L |
|---|
| 1803 | #define DAGB0_WRCLI31__MAX_OSD_MASK 0xFC000000L |
|---|
| 1804 | //DAGB0_WR_CNTL |
|---|
| 1805 | #define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT 0x0 |
|---|
| 1806 | #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 |
|---|
| 1807 | #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa |
|---|
| 1808 | #define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 |
|---|
| 1809 | #define DAGB0_WR_CNTL__IO_LEVEL__SHIFT 0x11 |
|---|
| 1810 | #define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 |
|---|
| 1811 | #define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 |
|---|
| 1812 | #define DAGB0_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL |
|---|
| 1813 | #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L |
|---|
| 1814 | #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L |
|---|
| 1815 | #define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L |
|---|
| 1816 | #define DAGB0_WR_CNTL__IO_LEVEL_MASK 0x000E0000L |
|---|
| 1817 | #define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L |
|---|
| 1818 | #define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L |
|---|
| 1819 | //DAGB0_WR_GMI_CNTL |
|---|
| 1820 | #define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 |
|---|
| 1821 | #define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT 0x6 |
|---|
| 1822 | #define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 |
|---|
| 1823 | #define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd |
|---|
| 1824 | #define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL |
|---|
| 1825 | #define DAGB0_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L |
|---|
| 1826 | #define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L |
|---|
| 1827 | #define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L |
|---|
| 1828 | //DAGB0_WR_ADDR_DAGB |
|---|
| 1829 | #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 |
|---|
| 1830 | #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 |
|---|
| 1831 | #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 |
|---|
| 1832 | #define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 |
|---|
| 1833 | #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L |
|---|
| 1834 | #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L |
|---|
| 1835 | #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L |
|---|
| 1836 | #define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L |
|---|
| 1837 | //DAGB0_WR_OUTPUT_DAGB_MAX_BURST |
|---|
| 1838 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 |
|---|
| 1839 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 |
|---|
| 1840 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 |
|---|
| 1841 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc |
|---|
| 1842 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 |
|---|
| 1843 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 |
|---|
| 1844 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 |
|---|
| 1845 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c |
|---|
| 1846 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL |
|---|
| 1847 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L |
|---|
| 1848 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L |
|---|
| 1849 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L |
|---|
| 1850 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L |
|---|
| 1851 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L |
|---|
| 1852 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L |
|---|
| 1853 | #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L |
|---|
| 1854 | //DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER |
|---|
| 1855 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 |
|---|
| 1856 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 |
|---|
| 1857 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 |
|---|
| 1858 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc |
|---|
| 1859 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 |
|---|
| 1860 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 |
|---|
| 1861 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 |
|---|
| 1862 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c |
|---|
| 1863 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL |
|---|
| 1864 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L |
|---|
| 1865 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L |
|---|
| 1866 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L |
|---|
| 1867 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L |
|---|
| 1868 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L |
|---|
| 1869 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L |
|---|
| 1870 | #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L |
|---|
| 1871 | //DAGB0_WR_CGTT_CLK_CTRL |
|---|
| 1872 | #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
|---|
| 1873 | #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
|---|
| 1874 | #define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 |
|---|
| 1875 | #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b |
|---|
| 1876 | #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c |
|---|
| 1877 | #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d |
|---|
| 1878 | #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e |
|---|
| 1879 | #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f |
|---|
| 1880 | #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
|---|
| 1881 | #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
|---|
| 1882 | #define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L |
|---|
| 1883 | #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L |
|---|
| 1884 | #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L |
|---|
| 1885 | #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L |
|---|
| 1886 | #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L |
|---|
| 1887 | #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L |
|---|
| 1888 | //DAGB0_L1TLB_WR_CGTT_CLK_CTRL |
|---|
| 1889 | #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
|---|
| 1890 | #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
|---|
| 1891 | #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 |
|---|
| 1892 | #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b |
|---|
| 1893 | #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c |
|---|
| 1894 | #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d |
|---|
| 1895 | #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e |
|---|
| 1896 | #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f |
|---|
| 1897 | #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
|---|
| 1898 | #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
|---|
| 1899 | #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L |
|---|
| 1900 | #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L |
|---|
| 1901 | #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L |
|---|
| 1902 | #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L |
|---|
| 1903 | #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L |
|---|
| 1904 | #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L |
|---|
| 1905 | //DAGB0_ATCVM_WR_CGTT_CLK_CTRL |
|---|
| 1906 | #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
|---|
| 1907 | #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
|---|
| 1908 | #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 |
|---|
| 1909 | #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b |
|---|
| 1910 | #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c |
|---|
| 1911 | #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d |
|---|
| 1912 | #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e |
|---|
| 1913 | #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f |
|---|
| 1914 | #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
|---|
| 1915 | #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
|---|
| 1916 | #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L |
|---|
| 1917 | #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L |
|---|
| 1918 | #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L |
|---|
| 1919 | #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L |
|---|
| 1920 | #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L |
|---|
| 1921 | #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L |
|---|
| 1922 | //DAGB0_WR_ADDR_DAGB_MAX_BURST0 |
|---|
| 1923 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 |
|---|
| 1924 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 |
|---|
| 1925 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 |
|---|
| 1926 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc |
|---|
| 1927 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 |
|---|
| 1928 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 |
|---|
| 1929 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 |
|---|
| 1930 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c |
|---|
| 1931 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL |
|---|
| 1932 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L |
|---|
| 1933 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L |
|---|
| 1934 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L |
|---|
| 1935 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L |
|---|
| 1936 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L |
|---|
| 1937 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L |
|---|
| 1938 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L |
|---|
| 1939 | //DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 |
|---|
| 1940 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 |
|---|
| 1941 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 |
|---|
| 1942 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 |
|---|
| 1943 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc |
|---|
| 1944 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 |
|---|
| 1945 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 |
|---|
| 1946 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 |
|---|
| 1947 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c |
|---|
| 1948 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL |
|---|
| 1949 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L |
|---|
| 1950 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L |
|---|
| 1951 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L |
|---|
| 1952 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L |
|---|
| 1953 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L |
|---|
| 1954 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L |
|---|
| 1955 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L |
|---|
| 1956 | //DAGB0_WR_ADDR_DAGB_MAX_BURST1 |
|---|
| 1957 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 |
|---|
| 1958 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 |
|---|
| 1959 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 |
|---|
| 1960 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc |
|---|
| 1961 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 |
|---|
| 1962 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 |
|---|
| 1963 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 |
|---|
| 1964 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c |
|---|
| 1965 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL |
|---|
| 1966 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L |
|---|
| 1967 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L |
|---|
| 1968 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L |
|---|
| 1969 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L |
|---|
| 1970 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L |
|---|
| 1971 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L |
|---|
| 1972 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L |
|---|
| 1973 | //DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 |
|---|
| 1974 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 |
|---|
| 1975 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 |
|---|
| 1976 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 |
|---|
| 1977 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc |
|---|
| 1978 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 |
|---|
| 1979 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 |
|---|
| 1980 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 |
|---|
| 1981 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c |
|---|
| 1982 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL |
|---|
| 1983 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L |
|---|
| 1984 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L |
|---|
| 1985 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L |
|---|
| 1986 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L |
|---|
| 1987 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L |
|---|
| 1988 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L |
|---|
| 1989 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L |
|---|
| 1990 | //DAGB0_WR_ADDR_DAGB_MAX_BURST2 |
|---|
| 1991 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 |
|---|
| 1992 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 |
|---|
| 1993 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 |
|---|
| 1994 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc |
|---|
| 1995 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 |
|---|
| 1996 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 |
|---|
| 1997 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 |
|---|
| 1998 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c |
|---|
| 1999 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL |
|---|
| 2000 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L |
|---|
| 2001 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L |
|---|
| 2002 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L |
|---|
| 2003 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L |
|---|
| 2004 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L |
|---|
| 2005 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L |
|---|
| 2006 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L |
|---|
| 2007 | //DAGB0_WR_ADDR_DAGB_LAZY_TIMER2 |
|---|
| 2008 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 |
|---|
| 2009 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 |
|---|
| 2010 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 |
|---|
| 2011 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc |
|---|
| 2012 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 |
|---|
| 2013 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 |
|---|
| 2014 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 |
|---|
| 2015 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c |
|---|
| 2016 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL |
|---|
| 2017 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L |
|---|
| 2018 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L |
|---|
| 2019 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L |
|---|
| 2020 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L |
|---|
| 2021 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L |
|---|
| 2022 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L |
|---|
| 2023 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L |
|---|
| 2024 | //DAGB0_WR_ADDR_DAGB_MAX_BURST3 |
|---|
| 2025 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0 |
|---|
| 2026 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4 |
|---|
| 2027 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8 |
|---|
| 2028 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc |
|---|
| 2029 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10 |
|---|
| 2030 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14 |
|---|
| 2031 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18 |
|---|
| 2032 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c |
|---|
| 2033 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL |
|---|
| 2034 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L |
|---|
| 2035 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L |
|---|
| 2036 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L |
|---|
| 2037 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L |
|---|
| 2038 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L |
|---|
| 2039 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L |
|---|
| 2040 | #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L |
|---|
| 2041 | //DAGB0_WR_ADDR_DAGB_LAZY_TIMER3 |
|---|
| 2042 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0 |
|---|
| 2043 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4 |
|---|
| 2044 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8 |
|---|
| 2045 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc |
|---|
| 2046 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10 |
|---|
| 2047 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14 |
|---|
| 2048 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18 |
|---|
| 2049 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c |
|---|
| 2050 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL |
|---|
| 2051 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L |
|---|
| 2052 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L |
|---|
| 2053 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L |
|---|
| 2054 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L |
|---|
| 2055 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L |
|---|
| 2056 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L |
|---|
| 2057 | #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L |
|---|
| 2058 | //DAGB0_WR_DATA_DAGB |
|---|
| 2059 | #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 |
|---|
| 2060 | #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 |
|---|
| 2061 | #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 |
|---|
| 2062 | #define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 |
|---|
| 2063 | #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L |
|---|
| 2064 | #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L |
|---|
| 2065 | #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L |
|---|
| 2066 | #define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L |
|---|
| 2067 | //DAGB0_WR_DATA_DAGB_MAX_BURST0 |
|---|
| 2068 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 |
|---|
| 2069 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 |
|---|
| 2070 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 |
|---|
| 2071 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc |
|---|
| 2072 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 |
|---|
| 2073 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 |
|---|
| 2074 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 |
|---|
| 2075 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c |
|---|
| 2076 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL |
|---|
| 2077 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L |
|---|
| 2078 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L |
|---|
| 2079 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L |
|---|
| 2080 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L |
|---|
| 2081 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L |
|---|
| 2082 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L |
|---|
| 2083 | #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L |
|---|
| 2084 | //DAGB0_WR_DATA_DAGB_LAZY_TIMER0 |
|---|
| 2085 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 |
|---|
| 2086 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 |
|---|
| 2087 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 |
|---|
| 2088 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc |
|---|
| 2089 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 |
|---|
| 2090 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 |
|---|
| 2091 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 |
|---|
| 2092 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c |
|---|
| 2093 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL |
|---|
| 2094 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L |
|---|
| 2095 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L |
|---|
| 2096 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L |
|---|
| 2097 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L |
|---|
| 2098 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L |
|---|
| 2099 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L |
|---|
| 2100 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L |
|---|
| 2101 | //DAGB0_WR_DATA_DAGB_MAX_BURST1 |
|---|
| 2102 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 |
|---|
| 2103 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 |
|---|
| 2104 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 |
|---|
| 2105 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc |
|---|
| 2106 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 |
|---|
| 2107 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 |
|---|
| 2108 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 |
|---|
| 2109 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c |
|---|
| 2110 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL |
|---|
| 2111 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L |
|---|
| 2112 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L |
|---|
| 2113 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L |
|---|
| 2114 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L |
|---|
| 2115 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L |
|---|
| 2116 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L |
|---|
| 2117 | #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L |
|---|
| 2118 | //DAGB0_WR_DATA_DAGB_LAZY_TIMER1 |
|---|
| 2119 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 |
|---|
| 2120 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 |
|---|
| 2121 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 |
|---|
| 2122 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc |
|---|
| 2123 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 |
|---|
| 2124 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 |
|---|
| 2125 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 |
|---|
| 2126 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c |
|---|
| 2127 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL |
|---|
| 2128 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L |
|---|
| 2129 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L |
|---|
| 2130 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L |
|---|
| 2131 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L |
|---|
| 2132 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L |
|---|
| 2133 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L |
|---|
| 2134 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L |
|---|
| 2135 | //DAGB0_WR_DATA_DAGB_MAX_BURST2 |
|---|
| 2136 | #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 |
|---|
| 2137 | #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 |
|---|
| 2138 | #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 |
|---|
| 2139 | #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc |
|---|
| 2140 | #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 |
|---|
| 2141 | #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 |
|---|
| 2142 | #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 |
|---|
| 2143 | #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c |
|---|
| 2144 | #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL |
|---|
| 2145 | #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L |
|---|
| 2146 | #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L |
|---|
| 2147 | #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L |
|---|
| 2148 | #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L |
|---|
| 2149 | #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L |
|---|
| 2150 | #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L |
|---|
| 2151 | #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L |
|---|
| 2152 | //DAGB0_WR_DATA_DAGB_LAZY_TIMER2 |
|---|
| 2153 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 |
|---|
| 2154 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 |
|---|
| 2155 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 |
|---|
| 2156 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc |
|---|
| 2157 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 |
|---|
| 2158 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 |
|---|
| 2159 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 |
|---|
| 2160 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c |
|---|
| 2161 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL |
|---|
| 2162 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L |
|---|
| 2163 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L |
|---|
| 2164 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L |
|---|
| 2165 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L |
|---|
| 2166 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L |
|---|
| 2167 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L |
|---|
| 2168 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L |
|---|
| 2169 | //DAGB0_WR_DATA_DAGB_MAX_BURST3 |
|---|
| 2170 | #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0 |
|---|
| 2171 | #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4 |
|---|
| 2172 | #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8 |
|---|
| 2173 | #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc |
|---|
| 2174 | #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10 |
|---|
| 2175 | #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14 |
|---|
| 2176 | #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18 |
|---|
| 2177 | #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c |
|---|
| 2178 | #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL |
|---|
| 2179 | #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L |
|---|
| 2180 | #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L |
|---|
| 2181 | #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L |
|---|
| 2182 | #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L |
|---|
| 2183 | #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L |
|---|
| 2184 | #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L |
|---|
| 2185 | #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L |
|---|
| 2186 | //DAGB0_WR_DATA_DAGB_LAZY_TIMER3 |
|---|
| 2187 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0 |
|---|
| 2188 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4 |
|---|
| 2189 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8 |
|---|
| 2190 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc |
|---|
| 2191 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10 |
|---|
| 2192 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14 |
|---|
| 2193 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18 |
|---|
| 2194 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c |
|---|
| 2195 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL |
|---|
| 2196 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L |
|---|
| 2197 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L |
|---|
| 2198 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L |
|---|
| 2199 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L |
|---|
| 2200 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L |
|---|
| 2201 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L |
|---|
| 2202 | #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L |
|---|
| 2203 | //DAGB0_WR_VC0_CNTL |
|---|
| 2204 | #define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 |
|---|
| 2205 | #define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 |
|---|
| 2206 | #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
|---|
| 2207 | #define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc |
|---|
| 2208 | #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
|---|
| 2209 | #define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 |
|---|
| 2210 | #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
|---|
| 2211 | #define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 |
|---|
| 2212 | #define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL |
|---|
| 2213 | #define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L |
|---|
| 2214 | #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
|---|
| 2215 | #define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L |
|---|
| 2216 | #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
|---|
| 2217 | #define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L |
|---|
| 2218 | #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
|---|
| 2219 | #define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L |
|---|
| 2220 | //DAGB0_WR_VC1_CNTL |
|---|
| 2221 | #define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 |
|---|
| 2222 | #define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 |
|---|
| 2223 | #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
|---|
| 2224 | #define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc |
|---|
| 2225 | #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
|---|
| 2226 | #define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 |
|---|
| 2227 | #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
|---|
| 2228 | #define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 |
|---|
| 2229 | #define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL |
|---|
| 2230 | #define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L |
|---|
| 2231 | #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
|---|
| 2232 | #define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L |
|---|
| 2233 | #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
|---|
| 2234 | #define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L |
|---|
| 2235 | #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
|---|
| 2236 | #define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L |
|---|
| 2237 | //DAGB0_WR_VC2_CNTL |
|---|
| 2238 | #define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 |
|---|
| 2239 | #define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 |
|---|
| 2240 | #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
|---|
| 2241 | #define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc |
|---|
| 2242 | #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
|---|
| 2243 | #define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 |
|---|
| 2244 | #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
|---|
| 2245 | #define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 |
|---|
| 2246 | #define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL |
|---|
| 2247 | #define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L |
|---|
| 2248 | #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
|---|
| 2249 | #define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L |
|---|
| 2250 | #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
|---|
| 2251 | #define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L |
|---|
| 2252 | #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
|---|
| 2253 | #define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L |
|---|
| 2254 | //DAGB0_WR_VC3_CNTL |
|---|
| 2255 | #define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 |
|---|
| 2256 | #define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 |
|---|
| 2257 | #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
|---|
| 2258 | #define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc |
|---|
| 2259 | #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
|---|
| 2260 | #define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 |
|---|
| 2261 | #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
|---|
| 2262 | #define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 |
|---|
| 2263 | #define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL |
|---|
| 2264 | #define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L |
|---|
| 2265 | #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
|---|
| 2266 | #define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L |
|---|
| 2267 | #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
|---|
| 2268 | #define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L |
|---|
| 2269 | #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
|---|
| 2270 | #define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L |
|---|
| 2271 | //DAGB0_WR_VC4_CNTL |
|---|
| 2272 | #define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 |
|---|
| 2273 | #define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 |
|---|
| 2274 | #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
|---|
| 2275 | #define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc |
|---|
| 2276 | #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
|---|
| 2277 | #define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 |
|---|
| 2278 | #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
|---|
| 2279 | #define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 |
|---|
| 2280 | #define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL |
|---|
| 2281 | #define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L |
|---|
| 2282 | #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
|---|
| 2283 | #define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L |
|---|
| 2284 | #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
|---|
| 2285 | #define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L |
|---|
| 2286 | #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
|---|
| 2287 | #define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L |
|---|
| 2288 | //DAGB0_WR_VC5_CNTL |
|---|
| 2289 | #define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 |
|---|
| 2290 | #define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 |
|---|
| 2291 | #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
|---|
| 2292 | #define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc |
|---|
| 2293 | #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
|---|
| 2294 | #define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 |
|---|
| 2295 | #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
|---|
| 2296 | #define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 |
|---|
| 2297 | #define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL |
|---|
| 2298 | #define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L |
|---|
| 2299 | #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
|---|
| 2300 | #define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L |
|---|
| 2301 | #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
|---|
| 2302 | #define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L |
|---|
| 2303 | #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
|---|
| 2304 | #define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L |
|---|
| 2305 | //DAGB0_WR_VC6_CNTL |
|---|
| 2306 | #define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 |
|---|
| 2307 | #define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 |
|---|
| 2308 | #define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
|---|
| 2309 | #define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT 0xc |
|---|
| 2310 | #define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
|---|
| 2311 | #define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 |
|---|
| 2312 | #define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
|---|
| 2313 | #define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 |
|---|
| 2314 | #define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL |
|---|
| 2315 | #define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L |
|---|
| 2316 | #define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
|---|
| 2317 | #define DAGB0_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L |
|---|
| 2318 | #define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
|---|
| 2319 | #define DAGB0_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L |
|---|
| 2320 | #define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
|---|
| 2321 | #define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L |
|---|
| 2322 | //DAGB0_WR_VC7_CNTL |
|---|
| 2323 | #define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 |
|---|
| 2324 | #define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 |
|---|
| 2325 | #define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb |
|---|
| 2326 | #define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT 0xc |
|---|
| 2327 | #define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 |
|---|
| 2328 | #define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 |
|---|
| 2329 | #define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 |
|---|
| 2330 | #define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 |
|---|
| 2331 | #define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL |
|---|
| 2332 | #define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L |
|---|
| 2333 | #define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L |
|---|
| 2334 | #define DAGB0_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L |
|---|
| 2335 | #define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L |
|---|
| 2336 | #define DAGB0_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L |
|---|
| 2337 | #define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L |
|---|
| 2338 | #define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L |
|---|
| 2339 | //DAGB0_WR_CNTL_MISC |
|---|
| 2340 | #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 |
|---|
| 2341 | #define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 |
|---|
| 2342 | #define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd |
|---|
| 2343 | #define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 |
|---|
| 2344 | #define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 |
|---|
| 2345 | #define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 |
|---|
| 2346 | #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL |
|---|
| 2347 | #define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L |
|---|
| 2348 | #define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L |
|---|
| 2349 | #define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L |
|---|
| 2350 | #define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L |
|---|
| 2351 | #define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L |
|---|
| 2352 | //DAGB0_WR_TLB_CREDIT |
|---|
| 2353 | #define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0 |
|---|
| 2354 | #define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5 |
|---|
| 2355 | #define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa |
|---|
| 2356 | #define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf |
|---|
| 2357 | #define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14 |
|---|
| 2358 | #define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19 |
|---|
| 2359 | #define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL |
|---|
| 2360 | #define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L |
|---|
| 2361 | #define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L |
|---|
| 2362 | #define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L |
|---|
| 2363 | #define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L |
|---|
| 2364 | #define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L |
|---|
| 2365 | //DAGB0_WR_DATA_CREDIT |
|---|
| 2366 | #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 |
|---|
| 2367 | #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 |
|---|
| 2368 | #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 |
|---|
| 2369 | #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 |
|---|
| 2370 | #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL |
|---|
| 2371 | #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L |
|---|
| 2372 | #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L |
|---|
| 2373 | #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L |
|---|
| 2374 | //DAGB0_WR_MISC_CREDIT |
|---|
| 2375 | #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 |
|---|
| 2376 | #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 |
|---|
| 2377 | #define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 |
|---|
| 2378 | #define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 |
|---|
| 2379 | #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL |
|---|
| 2380 | #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L |
|---|
| 2381 | #define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L |
|---|
| 2382 | #define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L |
|---|
| 2383 | //DAGB0_WRCLI_ASK_PENDING |
|---|
| 2384 | #define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 |
|---|
| 2385 | #define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL |
|---|
| 2386 | //DAGB0_WRCLI_GO_PENDING |
|---|
| 2387 | #define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 |
|---|
| 2388 | #define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL |
|---|
| 2389 | //DAGB0_WRCLI_GBLSEND_PENDING |
|---|
| 2390 | #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 |
|---|
| 2391 | #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL |
|---|
| 2392 | //DAGB0_WRCLI_TLB_PENDING |
|---|
| 2393 | #define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 |
|---|
| 2394 | #define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL |
|---|
| 2395 | //DAGB0_WRCLI_OARB_PENDING |
|---|
| 2396 | #define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 |
|---|
| 2397 | #define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL |
|---|
| 2398 | //DAGB0_WRCLI_OSD_PENDING |
|---|
| 2399 | #define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 |
|---|
| 2400 | #define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL |
|---|
| 2401 | //DAGB0_WRCLI_DBUS_ASK_PENDING |
|---|
| 2402 | #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 |
|---|
| 2403 | #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL |
|---|
| 2404 | //DAGB0_WRCLI_DBUS_GO_PENDING |
|---|
| 2405 | #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 |
|---|
| 2406 | #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL |
|---|
| 2407 | //DAGB0_DAGB_DLY |
|---|
| 2408 | #define DAGB0_DAGB_DLY__DLY__SHIFT 0x0 |
|---|
| 2409 | #define DAGB0_DAGB_DLY__CLI__SHIFT 0x8 |
|---|
| 2410 | #define DAGB0_DAGB_DLY__POS__SHIFT 0x10 |
|---|
| 2411 | #define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL |
|---|
| 2412 | #define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L |
|---|
| 2413 | #define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L |
|---|
| 2414 | //DAGB0_CNTL_MISC |
|---|
| 2415 | #define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 |
|---|
| 2416 | #define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 |
|---|
| 2417 | #define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 |
|---|
| 2418 | #define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 |
|---|
| 2419 | #define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc |
|---|
| 2420 | #define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf |
|---|
| 2421 | #define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 |
|---|
| 2422 | #define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 |
|---|
| 2423 | #define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 |
|---|
| 2424 | #define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e |
|---|
| 2425 | #define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L |
|---|
| 2426 | #define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L |
|---|
| 2427 | #define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L |
|---|
| 2428 | #define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L |
|---|
| 2429 | #define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L |
|---|
| 2430 | #define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L |
|---|
| 2431 | #define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L |
|---|
| 2432 | #define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L |
|---|
| 2433 | #define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L |
|---|
| 2434 | #define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L |
|---|
| 2435 | //DAGB0_CNTL_MISC2 |
|---|
| 2436 | #define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 |
|---|
| 2437 | #define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 |
|---|
| 2438 | #define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 |
|---|
| 2439 | #define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 |
|---|
| 2440 | #define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 |
|---|
| 2441 | #define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 |
|---|
| 2442 | #define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 |
|---|
| 2443 | #define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 |
|---|
| 2444 | #define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 |
|---|
| 2445 | #define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 |
|---|
| 2446 | #define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa |
|---|
| 2447 | #define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L |
|---|
| 2448 | #define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L |
|---|
| 2449 | #define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L |
|---|
| 2450 | #define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L |
|---|
| 2451 | #define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L |
|---|
| 2452 | #define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L |
|---|
| 2453 | #define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L |
|---|
| 2454 | #define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L |
|---|
| 2455 | #define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L |
|---|
| 2456 | #define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L |
|---|
| 2457 | #define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L |
|---|
| 2458 | //DAGB0_FIFO_EMPTY |
|---|
| 2459 | #define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0 |
|---|
| 2460 | #define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL |
|---|
| 2461 | //DAGB0_FIFO_FULL |
|---|
| 2462 | #define DAGB0_FIFO_FULL__FULL__SHIFT 0x0 |
|---|
| 2463 | #define DAGB0_FIFO_FULL__FULL_MASK 0x007FFFFFL |
|---|
| 2464 | //DAGB0_WR_CREDITS_FULL |
|---|
| 2465 | #define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0 |
|---|
| 2466 | #define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0007FFFFL |
|---|
| 2467 | //DAGB0_RD_CREDITS_FULL |
|---|
| 2468 | #define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0 |
|---|
| 2469 | #define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL |
|---|
| 2470 | //DAGB0_PERFCOUNTER_LO |
|---|
| 2471 | #define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
|---|
| 2472 | #define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
|---|
| 2473 | //DAGB0_PERFCOUNTER_HI |
|---|
| 2474 | #define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
|---|
| 2475 | #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
|---|
| 2476 | #define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
|---|
| 2477 | #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
|---|
| 2478 | //DAGB0_PERFCOUNTER0_CFG |
|---|
| 2479 | #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
|---|
| 2480 | #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
|---|
| 2481 | #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
|---|
| 2482 | #define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
|---|
| 2483 | #define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
|---|
| 2484 | #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
|---|
| 2485 | #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
|---|
| 2486 | #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
|---|
| 2487 | #define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
|---|
| 2488 | #define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
|---|
| 2489 | //DAGB0_PERFCOUNTER1_CFG |
|---|
| 2490 | #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
|---|
| 2491 | #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
|---|
| 2492 | #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
|---|
| 2493 | #define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
|---|
| 2494 | #define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
|---|
| 2495 | #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
|---|
| 2496 | #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
|---|
| 2497 | #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
|---|
| 2498 | #define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
|---|
| 2499 | #define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
|---|
| 2500 | //DAGB0_PERFCOUNTER2_CFG |
|---|
| 2501 | #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 |
|---|
| 2502 | #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 |
|---|
| 2503 | #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 |
|---|
| 2504 | #define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c |
|---|
| 2505 | #define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d |
|---|
| 2506 | #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL |
|---|
| 2507 | #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L |
|---|
| 2508 | #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L |
|---|
| 2509 | #define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L |
|---|
| 2510 | #define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L |
|---|
| 2511 | //DAGB0_PERFCOUNTER_RSLT_CNTL |
|---|
| 2512 | #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
|---|
| 2513 | #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
|---|
| 2514 | #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
|---|
| 2515 | #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
|---|
| 2516 | #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
|---|
| 2517 | #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
|---|
| 2518 | #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
|---|
| 2519 | #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
|---|
| 2520 | #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
|---|
| 2521 | #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
|---|
| 2522 | #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
|---|
| 2523 | #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
|---|
| 2524 | //DAGB0_RESERVE0 |
|---|
| 2525 | #define DAGB0_RESERVE0__RESERVE__SHIFT 0x0 |
|---|
| 2526 | #define DAGB0_RESERVE0__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2527 | //DAGB0_RESERVE1 |
|---|
| 2528 | #define DAGB0_RESERVE1__RESERVE__SHIFT 0x0 |
|---|
| 2529 | #define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2530 | //DAGB0_RESERVE2 |
|---|
| 2531 | #define DAGB0_RESERVE2__RESERVE__SHIFT 0x0 |
|---|
| 2532 | #define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2533 | //DAGB0_RESERVE3 |
|---|
| 2534 | #define DAGB0_RESERVE3__RESERVE__SHIFT 0x0 |
|---|
| 2535 | #define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2536 | //DAGB0_RESERVE4 |
|---|
| 2537 | #define DAGB0_RESERVE4__RESERVE__SHIFT 0x0 |
|---|
| 2538 | #define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2539 | //DAGB0_RESERVE5 |
|---|
| 2540 | #define DAGB0_RESERVE5__RESERVE__SHIFT 0x0 |
|---|
| 2541 | #define DAGB0_RESERVE5__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2542 | //DAGB0_RESERVE6 |
|---|
| 2543 | #define DAGB0_RESERVE6__RESERVE__SHIFT 0x0 |
|---|
| 2544 | #define DAGB0_RESERVE6__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2545 | //DAGB0_RESERVE7 |
|---|
| 2546 | #define DAGB0_RESERVE7__RESERVE__SHIFT 0x0 |
|---|
| 2547 | #define DAGB0_RESERVE7__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2548 | //DAGB0_RESERVE8 |
|---|
| 2549 | #define DAGB0_RESERVE8__RESERVE__SHIFT 0x0 |
|---|
| 2550 | #define DAGB0_RESERVE8__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2551 | //DAGB0_RESERVE9 |
|---|
| 2552 | #define DAGB0_RESERVE9__RESERVE__SHIFT 0x0 |
|---|
| 2553 | #define DAGB0_RESERVE9__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2554 | //DAGB0_RESERVE10 |
|---|
| 2555 | #define DAGB0_RESERVE10__RESERVE__SHIFT 0x0 |
|---|
| 2556 | #define DAGB0_RESERVE10__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2557 | //DAGB0_RESERVE11 |
|---|
| 2558 | #define DAGB0_RESERVE11__RESERVE__SHIFT 0x0 |
|---|
| 2559 | #define DAGB0_RESERVE11__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2560 | //DAGB0_RESERVE12 |
|---|
| 2561 | #define DAGB0_RESERVE12__RESERVE__SHIFT 0x0 |
|---|
| 2562 | #define DAGB0_RESERVE12__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2563 | //DAGB0_RESERVE13 |
|---|
| 2564 | #define DAGB0_RESERVE13__RESERVE__SHIFT 0x0 |
|---|
| 2565 | #define DAGB0_RESERVE13__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2566 | //DAGB0_RESERVE14 |
|---|
| 2567 | #define DAGB0_RESERVE14__RESERVE__SHIFT 0x0 |
|---|
| 2568 | #define DAGB0_RESERVE14__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2569 | //DAGB0_RESERVE15 |
|---|
| 2570 | #define DAGB0_RESERVE15__RESERVE__SHIFT 0x0 |
|---|
| 2571 | #define DAGB0_RESERVE15__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2572 | //DAGB0_RESERVE16 |
|---|
| 2573 | #define DAGB0_RESERVE16__RESERVE__SHIFT 0x0 |
|---|
| 2574 | #define DAGB0_RESERVE16__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2575 | //DAGB0_RESERVE17 |
|---|
| 2576 | #define DAGB0_RESERVE17__RESERVE__SHIFT 0x0 |
|---|
| 2577 | #define DAGB0_RESERVE17__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2578 | //DAGB0_RESERVE18 |
|---|
| 2579 | #define DAGB0_RESERVE18__RESERVE__SHIFT 0x0 |
|---|
| 2580 | #define DAGB0_RESERVE18__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2581 | //DAGB0_RESERVE19 |
|---|
| 2582 | #define DAGB0_RESERVE19__RESERVE__SHIFT 0x0 |
|---|
| 2583 | #define DAGB0_RESERVE19__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2584 | //DAGB0_RESERVE20 |
|---|
| 2585 | #define DAGB0_RESERVE20__RESERVE__SHIFT 0x0 |
|---|
| 2586 | #define DAGB0_RESERVE20__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2587 | //DAGB0_RESERVE21 |
|---|
| 2588 | #define DAGB0_RESERVE21__RESERVE__SHIFT 0x0 |
|---|
| 2589 | #define DAGB0_RESERVE21__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2590 | //DAGB0_RESERVE22 |
|---|
| 2591 | #define DAGB0_RESERVE22__RESERVE__SHIFT 0x0 |
|---|
| 2592 | #define DAGB0_RESERVE22__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2593 | //DAGB0_RESERVE23 |
|---|
| 2594 | #define DAGB0_RESERVE23__RESERVE__SHIFT 0x0 |
|---|
| 2595 | #define DAGB0_RESERVE23__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2596 | //DAGB0_RESERVE24 |
|---|
| 2597 | #define DAGB0_RESERVE24__RESERVE__SHIFT 0x0 |
|---|
| 2598 | #define DAGB0_RESERVE24__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2599 | //DAGB0_RESERVE25 |
|---|
| 2600 | #define DAGB0_RESERVE25__RESERVE__SHIFT 0x0 |
|---|
| 2601 | #define DAGB0_RESERVE25__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2602 | //DAGB0_RESERVE26 |
|---|
| 2603 | #define DAGB0_RESERVE26__RESERVE__SHIFT 0x0 |
|---|
| 2604 | #define DAGB0_RESERVE26__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2605 | //DAGB0_RESERVE27 |
|---|
| 2606 | #define DAGB0_RESERVE27__RESERVE__SHIFT 0x0 |
|---|
| 2607 | #define DAGB0_RESERVE27__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2608 | //DAGB0_RESERVE28 |
|---|
| 2609 | #define DAGB0_RESERVE28__RESERVE__SHIFT 0x0 |
|---|
| 2610 | #define DAGB0_RESERVE28__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2611 | //DAGB0_RESERVE29 |
|---|
| 2612 | #define DAGB0_RESERVE29__RESERVE__SHIFT 0x0 |
|---|
| 2613 | #define DAGB0_RESERVE29__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2614 | //DAGB0_RESERVE30 |
|---|
| 2615 | #define DAGB0_RESERVE30__RESERVE__SHIFT 0x0 |
|---|
| 2616 | #define DAGB0_RESERVE30__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2617 | //DAGB0_RESERVE31 |
|---|
| 2618 | #define DAGB0_RESERVE31__RESERVE__SHIFT 0x0 |
|---|
| 2619 | #define DAGB0_RESERVE31__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2620 | //DAGB0_RESERVE32 |
|---|
| 2621 | #define DAGB0_RESERVE32__RESERVE__SHIFT 0x0 |
|---|
| 2622 | #define DAGB0_RESERVE32__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2623 | //DAGB0_RESERVE33 |
|---|
| 2624 | #define DAGB0_RESERVE33__RESERVE__SHIFT 0x0 |
|---|
| 2625 | #define DAGB0_RESERVE33__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2626 | //DAGB0_RESERVE34 |
|---|
| 2627 | #define DAGB0_RESERVE34__RESERVE__SHIFT 0x0 |
|---|
| 2628 | #define DAGB0_RESERVE34__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2629 | //DAGB0_RESERVE35 |
|---|
| 2630 | #define DAGB0_RESERVE35__RESERVE__SHIFT 0x0 |
|---|
| 2631 | #define DAGB0_RESERVE35__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2632 | //DAGB0_RESERVE36 |
|---|
| 2633 | #define DAGB0_RESERVE36__RESERVE__SHIFT 0x0 |
|---|
| 2634 | #define DAGB0_RESERVE36__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2635 | //DAGB0_RESERVE37 |
|---|
| 2636 | #define DAGB0_RESERVE37__RESERVE__SHIFT 0x0 |
|---|
| 2637 | #define DAGB0_RESERVE37__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2638 | //DAGB0_RESERVE38 |
|---|
| 2639 | #define DAGB0_RESERVE38__RESERVE__SHIFT 0x0 |
|---|
| 2640 | #define DAGB0_RESERVE38__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2641 | //DAGB0_RESERVE39 |
|---|
| 2642 | #define DAGB0_RESERVE39__RESERVE__SHIFT 0x0 |
|---|
| 2643 | #define DAGB0_RESERVE39__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2644 | //DAGB0_RESERVE40 |
|---|
| 2645 | #define DAGB0_RESERVE40__RESERVE__SHIFT 0x0 |
|---|
| 2646 | #define DAGB0_RESERVE40__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2647 | //DAGB0_RESERVE41 |
|---|
| 2648 | #define DAGB0_RESERVE41__RESERVE__SHIFT 0x0 |
|---|
| 2649 | #define DAGB0_RESERVE41__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2650 | //DAGB0_RESERVE42 |
|---|
| 2651 | #define DAGB0_RESERVE42__RESERVE__SHIFT 0x0 |
|---|
| 2652 | #define DAGB0_RESERVE42__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2653 | //DAGB0_RESERVE43 |
|---|
| 2654 | #define DAGB0_RESERVE43__RESERVE__SHIFT 0x0 |
|---|
| 2655 | #define DAGB0_RESERVE43__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2656 | //DAGB0_RESERVE44 |
|---|
| 2657 | #define DAGB0_RESERVE44__RESERVE__SHIFT 0x0 |
|---|
| 2658 | #define DAGB0_RESERVE44__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2659 | //DAGB0_RESERVE45 |
|---|
| 2660 | #define DAGB0_RESERVE45__RESERVE__SHIFT 0x0 |
|---|
| 2661 | #define DAGB0_RESERVE45__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2662 | //DAGB0_RESERVE46 |
|---|
| 2663 | #define DAGB0_RESERVE46__RESERVE__SHIFT 0x0 |
|---|
| 2664 | #define DAGB0_RESERVE46__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2665 | //DAGB0_RESERVE47 |
|---|
| 2666 | #define DAGB0_RESERVE47__RESERVE__SHIFT 0x0 |
|---|
| 2667 | #define DAGB0_RESERVE47__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2668 | //DAGB0_RESERVE48 |
|---|
| 2669 | #define DAGB0_RESERVE48__RESERVE__SHIFT 0x0 |
|---|
| 2670 | #define DAGB0_RESERVE48__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2671 | //DAGB0_RESERVE49 |
|---|
| 2672 | #define DAGB0_RESERVE49__RESERVE__SHIFT 0x0 |
|---|
| 2673 | #define DAGB0_RESERVE49__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2674 | //DAGB0_RESERVE50 |
|---|
| 2675 | #define DAGB0_RESERVE50__RESERVE__SHIFT 0x0 |
|---|
| 2676 | #define DAGB0_RESERVE50__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2677 | //DAGB0_RESERVE51 |
|---|
| 2678 | #define DAGB0_RESERVE51__RESERVE__SHIFT 0x0 |
|---|
| 2679 | #define DAGB0_RESERVE51__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2680 | //DAGB0_RESERVE52 |
|---|
| 2681 | #define DAGB0_RESERVE52__RESERVE__SHIFT 0x0 |
|---|
| 2682 | #define DAGB0_RESERVE52__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2683 | //DAGB0_RESERVE53 |
|---|
| 2684 | #define DAGB0_RESERVE53__RESERVE__SHIFT 0x0 |
|---|
| 2685 | #define DAGB0_RESERVE53__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2686 | //DAGB0_RESERVE54 |
|---|
| 2687 | #define DAGB0_RESERVE54__RESERVE__SHIFT 0x0 |
|---|
| 2688 | #define DAGB0_RESERVE54__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2689 | //DAGB0_RESERVE55 |
|---|
| 2690 | #define DAGB0_RESERVE55__RESERVE__SHIFT 0x0 |
|---|
| 2691 | #define DAGB0_RESERVE55__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2692 | //DAGB0_RESERVE56 |
|---|
| 2693 | #define DAGB0_RESERVE56__RESERVE__SHIFT 0x0 |
|---|
| 2694 | #define DAGB0_RESERVE56__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2695 | //DAGB0_RESERVE57 |
|---|
| 2696 | #define DAGB0_RESERVE57__RESERVE__SHIFT 0x0 |
|---|
| 2697 | #define DAGB0_RESERVE57__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2698 | //DAGB0_RESERVE58 |
|---|
| 2699 | #define DAGB0_RESERVE58__RESERVE__SHIFT 0x0 |
|---|
| 2700 | #define DAGB0_RESERVE58__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2701 | //DAGB0_RESERVE59 |
|---|
| 2702 | #define DAGB0_RESERVE59__RESERVE__SHIFT 0x0 |
|---|
| 2703 | #define DAGB0_RESERVE59__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2704 | //DAGB0_RESERVE60 |
|---|
| 2705 | #define DAGB0_RESERVE60__RESERVE__SHIFT 0x0 |
|---|
| 2706 | #define DAGB0_RESERVE60__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2707 | //DAGB0_RESERVE61 |
|---|
| 2708 | #define DAGB0_RESERVE61__RESERVE__SHIFT 0x0 |
|---|
| 2709 | #define DAGB0_RESERVE61__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2710 | //DAGB0_RESERVE62 |
|---|
| 2711 | #define DAGB0_RESERVE62__RESERVE__SHIFT 0x0 |
|---|
| 2712 | #define DAGB0_RESERVE62__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2713 | //DAGB0_RESERVE63 |
|---|
| 2714 | #define DAGB0_RESERVE63__RESERVE__SHIFT 0x0 |
|---|
| 2715 | #define DAGB0_RESERVE63__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2716 | //DAGB0_RESERVE64 |
|---|
| 2717 | #define DAGB0_RESERVE64__RESERVE__SHIFT 0x0 |
|---|
| 2718 | #define DAGB0_RESERVE64__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2719 | //DAGB0_RESERVE65 |
|---|
| 2720 | #define DAGB0_RESERVE65__RESERVE__SHIFT 0x0 |
|---|
| 2721 | #define DAGB0_RESERVE65__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2722 | //DAGB0_RESERVE66 |
|---|
| 2723 | #define DAGB0_RESERVE66__RESERVE__SHIFT 0x0 |
|---|
| 2724 | #define DAGB0_RESERVE66__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2725 | //DAGB0_RESERVE67 |
|---|
| 2726 | #define DAGB0_RESERVE67__RESERVE__SHIFT 0x0 |
|---|
| 2727 | #define DAGB0_RESERVE67__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2728 | //DAGB0_RESERVE68 |
|---|
| 2729 | #define DAGB0_RESERVE68__RESERVE__SHIFT 0x0 |
|---|
| 2730 | #define DAGB0_RESERVE68__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2731 | //DAGB0_RESERVE69 |
|---|
| 2732 | #define DAGB0_RESERVE69__RESERVE__SHIFT 0x0 |
|---|
| 2733 | #define DAGB0_RESERVE69__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2734 | //DAGB0_RESERVE70 |
|---|
| 2735 | #define DAGB0_RESERVE70__RESERVE__SHIFT 0x0 |
|---|
| 2736 | #define DAGB0_RESERVE70__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2737 | //DAGB0_RESERVE71 |
|---|
| 2738 | #define DAGB0_RESERVE71__RESERVE__SHIFT 0x0 |
|---|
| 2739 | #define DAGB0_RESERVE71__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2740 | //DAGB0_RESERVE72 |
|---|
| 2741 | #define DAGB0_RESERVE72__RESERVE__SHIFT 0x0 |
|---|
| 2742 | #define DAGB0_RESERVE72__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2743 | //DAGB0_RESERVE73 |
|---|
| 2744 | #define DAGB0_RESERVE73__RESERVE__SHIFT 0x0 |
|---|
| 2745 | #define DAGB0_RESERVE73__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2746 | //DAGB0_RESERVE74 |
|---|
| 2747 | #define DAGB0_RESERVE74__RESERVE__SHIFT 0x0 |
|---|
| 2748 | #define DAGB0_RESERVE74__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2749 | //DAGB0_RESERVE75 |
|---|
| 2750 | #define DAGB0_RESERVE75__RESERVE__SHIFT 0x0 |
|---|
| 2751 | #define DAGB0_RESERVE75__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2752 | //DAGB0_RESERVE76 |
|---|
| 2753 | #define DAGB0_RESERVE76__RESERVE__SHIFT 0x0 |
|---|
| 2754 | #define DAGB0_RESERVE76__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2755 | //DAGB0_RESERVE77 |
|---|
| 2756 | #define DAGB0_RESERVE77__RESERVE__SHIFT 0x0 |
|---|
| 2757 | #define DAGB0_RESERVE77__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2758 | //DAGB0_RESERVE78 |
|---|
| 2759 | #define DAGB0_RESERVE78__RESERVE__SHIFT 0x0 |
|---|
| 2760 | #define DAGB0_RESERVE78__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2761 | //DAGB0_RESERVE79 |
|---|
| 2762 | #define DAGB0_RESERVE79__RESERVE__SHIFT 0x0 |
|---|
| 2763 | #define DAGB0_RESERVE79__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2764 | //DAGB0_RESERVE80 |
|---|
| 2765 | #define DAGB0_RESERVE80__RESERVE__SHIFT 0x0 |
|---|
| 2766 | #define DAGB0_RESERVE80__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2767 | //DAGB0_RESERVE81 |
|---|
| 2768 | #define DAGB0_RESERVE81__RESERVE__SHIFT 0x0 |
|---|
| 2769 | #define DAGB0_RESERVE81__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2770 | //DAGB0_RESERVE82 |
|---|
| 2771 | #define DAGB0_RESERVE82__RESERVE__SHIFT 0x0 |
|---|
| 2772 | #define DAGB0_RESERVE82__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2773 | //DAGB0_RESERVE83 |
|---|
| 2774 | #define DAGB0_RESERVE83__RESERVE__SHIFT 0x0 |
|---|
| 2775 | #define DAGB0_RESERVE83__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2776 | //DAGB0_RESERVE84 |
|---|
| 2777 | #define DAGB0_RESERVE84__RESERVE__SHIFT 0x0 |
|---|
| 2778 | #define DAGB0_RESERVE84__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2779 | //DAGB0_RESERVE85 |
|---|
| 2780 | #define DAGB0_RESERVE85__RESERVE__SHIFT 0x0 |
|---|
| 2781 | #define DAGB0_RESERVE85__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2782 | //DAGB0_RESERVE86 |
|---|
| 2783 | #define DAGB0_RESERVE86__RESERVE__SHIFT 0x0 |
|---|
| 2784 | #define DAGB0_RESERVE86__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2785 | //DAGB0_RESERVE87 |
|---|
| 2786 | #define DAGB0_RESERVE87__RESERVE__SHIFT 0x0 |
|---|
| 2787 | #define DAGB0_RESERVE87__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2788 | //DAGB0_RESERVE88 |
|---|
| 2789 | #define DAGB0_RESERVE88__RESERVE__SHIFT 0x0 |
|---|
| 2790 | #define DAGB0_RESERVE88__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2791 | //DAGB0_RESERVE89 |
|---|
| 2792 | #define DAGB0_RESERVE89__RESERVE__SHIFT 0x0 |
|---|
| 2793 | #define DAGB0_RESERVE89__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2794 | //DAGB0_RESERVE90 |
|---|
| 2795 | #define DAGB0_RESERVE90__RESERVE__SHIFT 0x0 |
|---|
| 2796 | #define DAGB0_RESERVE90__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2797 | //DAGB0_RESERVE91 |
|---|
| 2798 | #define DAGB0_RESERVE91__RESERVE__SHIFT 0x0 |
|---|
| 2799 | #define DAGB0_RESERVE91__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2800 | //DAGB0_RESERVE92 |
|---|
| 2801 | #define DAGB0_RESERVE92__RESERVE__SHIFT 0x0 |
|---|
| 2802 | #define DAGB0_RESERVE92__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2803 | //DAGB0_RESERVE93 |
|---|
| 2804 | #define DAGB0_RESERVE93__RESERVE__SHIFT 0x0 |
|---|
| 2805 | #define DAGB0_RESERVE93__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2806 | //DAGB0_RESERVE94 |
|---|
| 2807 | #define DAGB0_RESERVE94__RESERVE__SHIFT 0x0 |
|---|
| 2808 | #define DAGB0_RESERVE94__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2809 | //DAGB0_RESERVE95 |
|---|
| 2810 | #define DAGB0_RESERVE95__RESERVE__SHIFT 0x0 |
|---|
| 2811 | #define DAGB0_RESERVE95__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2812 | //DAGB0_RESERVE96 |
|---|
| 2813 | #define DAGB0_RESERVE96__RESERVE__SHIFT 0x0 |
|---|
| 2814 | #define DAGB0_RESERVE96__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2815 | //DAGB0_RESERVE97 |
|---|
| 2816 | #define DAGB0_RESERVE97__RESERVE__SHIFT 0x0 |
|---|
| 2817 | #define DAGB0_RESERVE97__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2818 | //DAGB0_RESERVE98 |
|---|
| 2819 | #define DAGB0_RESERVE98__RESERVE__SHIFT 0x0 |
|---|
| 2820 | #define DAGB0_RESERVE98__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2821 | //DAGB0_RESERVE99 |
|---|
| 2822 | #define DAGB0_RESERVE99__RESERVE__SHIFT 0x0 |
|---|
| 2823 | #define DAGB0_RESERVE99__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2824 | //DAGB0_RESERVE100 |
|---|
| 2825 | #define DAGB0_RESERVE100__RESERVE__SHIFT 0x0 |
|---|
| 2826 | #define DAGB0_RESERVE100__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2827 | //DAGB0_RESERVE101 |
|---|
| 2828 | #define DAGB0_RESERVE101__RESERVE__SHIFT 0x0 |
|---|
| 2829 | #define DAGB0_RESERVE101__RESERVE_MASK 0xFFFFFFFFL |
|---|
| 2830 | |
|---|
| 2831 | |
|---|
| 2832 | // addressBlock: mmhub_ea_mmeadec |
|---|
| 2833 | //MMEA0_DRAM_RD_CLI2GRP_MAP0 |
|---|
| 2834 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
|---|
| 2835 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
|---|
| 2836 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
|---|
| 2837 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
|---|
| 2838 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
|---|
| 2839 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
|---|
| 2840 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
|---|
| 2841 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
|---|
| 2842 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
|---|
| 2843 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
|---|
| 2844 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
|---|
| 2845 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
|---|
| 2846 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
|---|
| 2847 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
|---|
| 2848 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
|---|
| 2849 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
|---|
| 2850 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
|---|
| 2851 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
|---|
| 2852 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
|---|
| 2853 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
|---|
| 2854 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
|---|
| 2855 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
|---|
| 2856 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
|---|
| 2857 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
|---|
| 2858 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
|---|
| 2859 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
|---|
| 2860 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
|---|
| 2861 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
|---|
| 2862 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
|---|
| 2863 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
|---|
| 2864 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
|---|
| 2865 | #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
|---|
| 2866 | //MMEA0_DRAM_RD_CLI2GRP_MAP1 |
|---|
| 2867 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
|---|
| 2868 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
|---|
| 2869 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
|---|
| 2870 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
|---|
| 2871 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
|---|
| 2872 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
|---|
| 2873 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
|---|
| 2874 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
|---|
| 2875 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
|---|
| 2876 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
|---|
| 2877 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
|---|
| 2878 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
|---|
| 2879 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
|---|
| 2880 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
|---|
| 2881 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
|---|
| 2882 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
|---|
| 2883 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
|---|
| 2884 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
|---|
| 2885 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
|---|
| 2886 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
|---|
| 2887 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
|---|
| 2888 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
|---|
| 2889 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
|---|
| 2890 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
|---|
| 2891 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
|---|
| 2892 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
|---|
| 2893 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
|---|
| 2894 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
|---|
| 2895 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
|---|
| 2896 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
|---|
| 2897 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
|---|
| 2898 | #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
|---|
| 2899 | //MMEA0_DRAM_WR_CLI2GRP_MAP0 |
|---|
| 2900 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
|---|
| 2901 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
|---|
| 2902 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
|---|
| 2903 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
|---|
| 2904 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
|---|
| 2905 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
|---|
| 2906 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
|---|
| 2907 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
|---|
| 2908 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
|---|
| 2909 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
|---|
| 2910 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
|---|
| 2911 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
|---|
| 2912 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
|---|
| 2913 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
|---|
| 2914 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
|---|
| 2915 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
|---|
| 2916 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
|---|
| 2917 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
|---|
| 2918 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
|---|
| 2919 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
|---|
| 2920 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
|---|
| 2921 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
|---|
| 2922 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
|---|
| 2923 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
|---|
| 2924 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
|---|
| 2925 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
|---|
| 2926 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
|---|
| 2927 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
|---|
| 2928 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
|---|
| 2929 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
|---|
| 2930 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
|---|
| 2931 | #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
|---|
| 2932 | //MMEA0_DRAM_WR_CLI2GRP_MAP1 |
|---|
| 2933 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
|---|
| 2934 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
|---|
| 2935 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
|---|
| 2936 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
|---|
| 2937 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
|---|
| 2938 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
|---|
| 2939 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
|---|
| 2940 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
|---|
| 2941 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
|---|
| 2942 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
|---|
| 2943 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
|---|
| 2944 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
|---|
| 2945 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
|---|
| 2946 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
|---|
| 2947 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
|---|
| 2948 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
|---|
| 2949 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
|---|
| 2950 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
|---|
| 2951 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
|---|
| 2952 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
|---|
| 2953 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
|---|
| 2954 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
|---|
| 2955 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
|---|
| 2956 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
|---|
| 2957 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
|---|
| 2958 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
|---|
| 2959 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
|---|
| 2960 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
|---|
| 2961 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
|---|
| 2962 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
|---|
| 2963 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
|---|
| 2964 | #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
|---|
| 2965 | //MMEA0_DRAM_RD_GRP2VC_MAP |
|---|
| 2966 | #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
|---|
| 2967 | #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
|---|
| 2968 | #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
|---|
| 2969 | #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
|---|
| 2970 | #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
|---|
| 2971 | #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
|---|
| 2972 | #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
|---|
| 2973 | #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
|---|
| 2974 | //MMEA0_DRAM_WR_GRP2VC_MAP |
|---|
| 2975 | #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
|---|
| 2976 | #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
|---|
| 2977 | #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
|---|
| 2978 | #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
|---|
| 2979 | #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
|---|
| 2980 | #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
|---|
| 2981 | #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
|---|
| 2982 | #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
|---|
| 2983 | //MMEA0_DRAM_RD_LAZY |
|---|
| 2984 | #define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 |
|---|
| 2985 | #define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 |
|---|
| 2986 | #define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 |
|---|
| 2987 | #define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 |
|---|
| 2988 | #define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L |
|---|
| 2989 | #define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L |
|---|
| 2990 | #define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
|---|
| 2991 | #define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
|---|
| 2992 | //MMEA0_DRAM_WR_LAZY |
|---|
| 2993 | #define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 |
|---|
| 2994 | #define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 |
|---|
| 2995 | #define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 |
|---|
| 2996 | #define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 |
|---|
| 2997 | #define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L |
|---|
| 2998 | #define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L |
|---|
| 2999 | #define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
|---|
| 3000 | #define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
|---|
| 3001 | //MMEA0_DRAM_RD_CAM_CNTL |
|---|
| 3002 | #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
|---|
| 3003 | #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
|---|
| 3004 | #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
|---|
| 3005 | #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
|---|
| 3006 | #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
|---|
| 3007 | #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
|---|
| 3008 | #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
|---|
| 3009 | #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
|---|
| 3010 | #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
|---|
| 3011 | #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
|---|
| 3012 | #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
|---|
| 3013 | #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
|---|
| 3014 | #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
|---|
| 3015 | #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
|---|
| 3016 | #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
|---|
| 3017 | #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
|---|
| 3018 | //MMEA0_DRAM_WR_CAM_CNTL |
|---|
| 3019 | #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
|---|
| 3020 | #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
|---|
| 3021 | #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
|---|
| 3022 | #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
|---|
| 3023 | #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
|---|
| 3024 | #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
|---|
| 3025 | #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
|---|
| 3026 | #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
|---|
| 3027 | #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
|---|
| 3028 | #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
|---|
| 3029 | #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
|---|
| 3030 | #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
|---|
| 3031 | #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
|---|
| 3032 | #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
|---|
| 3033 | #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
|---|
| 3034 | #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
|---|
| 3035 | //MMEA0_DRAM_PAGE_BURST |
|---|
| 3036 | #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 |
|---|
| 3037 | #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 |
|---|
| 3038 | #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 |
|---|
| 3039 | #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 |
|---|
| 3040 | #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
|---|
| 3041 | #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
|---|
| 3042 | #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
|---|
| 3043 | #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
|---|
| 3044 | //MMEA0_DRAM_RD_PRI_AGE |
|---|
| 3045 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
|---|
| 3046 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
|---|
| 3047 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
|---|
| 3048 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
|---|
| 3049 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
|---|
| 3050 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
|---|
| 3051 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
|---|
| 3052 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
|---|
| 3053 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
|---|
| 3054 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
|---|
| 3055 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
|---|
| 3056 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
|---|
| 3057 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
|---|
| 3058 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
|---|
| 3059 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
|---|
| 3060 | #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
|---|
| 3061 | //MMEA0_DRAM_WR_PRI_AGE |
|---|
| 3062 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
|---|
| 3063 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
|---|
| 3064 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
|---|
| 3065 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
|---|
| 3066 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
|---|
| 3067 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
|---|
| 3068 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
|---|
| 3069 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
|---|
| 3070 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
|---|
| 3071 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
|---|
| 3072 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
|---|
| 3073 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
|---|
| 3074 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
|---|
| 3075 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
|---|
| 3076 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
|---|
| 3077 | #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
|---|
| 3078 | //MMEA0_DRAM_RD_PRI_QUEUING |
|---|
| 3079 | #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
|---|
| 3080 | #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
|---|
| 3081 | #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
|---|
| 3082 | #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
|---|
| 3083 | #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
|---|
| 3084 | #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
|---|
| 3085 | #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
|---|
| 3086 | #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
|---|
| 3087 | //MMEA0_DRAM_WR_PRI_QUEUING |
|---|
| 3088 | #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
|---|
| 3089 | #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
|---|
| 3090 | #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
|---|
| 3091 | #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
|---|
| 3092 | #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
|---|
| 3093 | #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
|---|
| 3094 | #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
|---|
| 3095 | #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
|---|
| 3096 | //MMEA0_DRAM_RD_PRI_FIXED |
|---|
| 3097 | #define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
|---|
| 3098 | #define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
|---|
| 3099 | #define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
|---|
| 3100 | #define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
|---|
| 3101 | #define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
|---|
| 3102 | #define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
|---|
| 3103 | #define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
|---|
| 3104 | #define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
|---|
| 3105 | //MMEA0_DRAM_WR_PRI_FIXED |
|---|
| 3106 | #define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
|---|
| 3107 | #define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
|---|
| 3108 | #define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
|---|
| 3109 | #define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
|---|
| 3110 | #define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
|---|
| 3111 | #define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
|---|
| 3112 | #define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
|---|
| 3113 | #define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
|---|
| 3114 | //MMEA0_DRAM_RD_PRI_URGENCY |
|---|
| 3115 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
|---|
| 3116 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
|---|
| 3117 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
|---|
| 3118 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
|---|
| 3119 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
|---|
| 3120 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
|---|
| 3121 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
|---|
| 3122 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
|---|
| 3123 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
|---|
| 3124 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
|---|
| 3125 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
|---|
| 3126 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
|---|
| 3127 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
|---|
| 3128 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
|---|
| 3129 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
|---|
| 3130 | #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
|---|
| 3131 | //MMEA0_DRAM_WR_PRI_URGENCY |
|---|
| 3132 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
|---|
| 3133 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
|---|
| 3134 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
|---|
| 3135 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
|---|
| 3136 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
|---|
| 3137 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
|---|
| 3138 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
|---|
| 3139 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
|---|
| 3140 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
|---|
| 3141 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
|---|
| 3142 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
|---|
| 3143 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
|---|
| 3144 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
|---|
| 3145 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
|---|
| 3146 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
|---|
| 3147 | #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
|---|
| 3148 | //MMEA0_DRAM_RD_PRI_QUANT_PRI1 |
|---|
| 3149 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
|---|
| 3150 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
|---|
| 3151 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
|---|
| 3152 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
|---|
| 3153 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
|---|
| 3154 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
|---|
| 3155 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
|---|
| 3156 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
|---|
| 3157 | //MMEA0_DRAM_RD_PRI_QUANT_PRI2 |
|---|
| 3158 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
|---|
| 3159 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
|---|
| 3160 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
|---|
| 3161 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
|---|
| 3162 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
|---|
| 3163 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
|---|
| 3164 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
|---|
| 3165 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
|---|
| 3166 | //MMEA0_DRAM_RD_PRI_QUANT_PRI3 |
|---|
| 3167 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
|---|
| 3168 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
|---|
| 3169 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
|---|
| 3170 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
|---|
| 3171 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
|---|
| 3172 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
|---|
| 3173 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
|---|
| 3174 | #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
|---|
| 3175 | //MMEA0_DRAM_WR_PRI_QUANT_PRI1 |
|---|
| 3176 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
|---|
| 3177 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
|---|
| 3178 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
|---|
| 3179 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
|---|
| 3180 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
|---|
| 3181 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
|---|
| 3182 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
|---|
| 3183 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
|---|
| 3184 | //MMEA0_DRAM_WR_PRI_QUANT_PRI2 |
|---|
| 3185 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
|---|
| 3186 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
|---|
| 3187 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
|---|
| 3188 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
|---|
| 3189 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
|---|
| 3190 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
|---|
| 3191 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
|---|
| 3192 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
|---|
| 3193 | //MMEA0_DRAM_WR_PRI_QUANT_PRI3 |
|---|
| 3194 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
|---|
| 3195 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
|---|
| 3196 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
|---|
| 3197 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
|---|
| 3198 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
|---|
| 3199 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
|---|
| 3200 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
|---|
| 3201 | #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
|---|
| 3202 | //MMEA0_ADDRNORM_BASE_ADDR0 |
|---|
| 3203 | #define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 |
|---|
| 3204 | #define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 |
|---|
| 3205 | #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4 |
|---|
| 3206 | #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8 |
|---|
| 3207 | #define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc |
|---|
| 3208 | #define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L |
|---|
| 3209 | #define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L |
|---|
| 3210 | #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L |
|---|
| 3211 | #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L |
|---|
| 3212 | #define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L |
|---|
| 3213 | //MMEA0_ADDRNORM_LIMIT_ADDR0 |
|---|
| 3214 | #define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 |
|---|
| 3215 | #define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 |
|---|
| 3216 | #define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa |
|---|
| 3217 | #define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc |
|---|
| 3218 | #define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000000FL |
|---|
| 3219 | #define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L |
|---|
| 3220 | #define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L |
|---|
| 3221 | #define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L |
|---|
| 3222 | //MMEA0_ADDRNORM_BASE_ADDR1 |
|---|
| 3223 | #define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 |
|---|
| 3224 | #define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 |
|---|
| 3225 | #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4 |
|---|
| 3226 | #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8 |
|---|
| 3227 | #define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc |
|---|
| 3228 | #define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L |
|---|
| 3229 | #define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L |
|---|
| 3230 | #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L |
|---|
| 3231 | #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L |
|---|
| 3232 | #define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L |
|---|
| 3233 | //MMEA0_ADDRNORM_LIMIT_ADDR1 |
|---|
| 3234 | #define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 |
|---|
| 3235 | #define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 |
|---|
| 3236 | #define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa |
|---|
| 3237 | #define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc |
|---|
| 3238 | #define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000000FL |
|---|
| 3239 | #define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L |
|---|
| 3240 | #define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L |
|---|
| 3241 | #define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L |
|---|
| 3242 | //MMEA0_ADDRNORM_OFFSET_ADDR1 |
|---|
| 3243 | #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 |
|---|
| 3244 | #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 |
|---|
| 3245 | #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L |
|---|
| 3246 | #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L |
|---|
| 3247 | //MMEA0_ADDRNORM_HOLE_CNTL |
|---|
| 3248 | #define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 |
|---|
| 3249 | #define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 |
|---|
| 3250 | #define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L |
|---|
| 3251 | #define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L |
|---|
| 3252 | //MMEA0_ADDRDEC_BANK_CFG |
|---|
| 3253 | #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 |
|---|
| 3254 | #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5 |
|---|
| 3255 | #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa |
|---|
| 3256 | #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd |
|---|
| 3257 | #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10 |
|---|
| 3258 | #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11 |
|---|
| 3259 | #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL |
|---|
| 3260 | #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L |
|---|
| 3261 | #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L |
|---|
| 3262 | #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L |
|---|
| 3263 | #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L |
|---|
| 3264 | #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L |
|---|
| 3265 | //MMEA0_ADDRDEC_MISC_CFG |
|---|
| 3266 | #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 |
|---|
| 3267 | #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 |
|---|
| 3268 | #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 |
|---|
| 3269 | #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3 |
|---|
| 3270 | #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4 |
|---|
| 3271 | #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 |
|---|
| 3272 | #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 |
|---|
| 3273 | #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc |
|---|
| 3274 | #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x10 |
|---|
| 3275 | #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x14 |
|---|
| 3276 | #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x16 |
|---|
| 3277 | #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x18 |
|---|
| 3278 | #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1b |
|---|
| 3279 | #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L |
|---|
| 3280 | #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L |
|---|
| 3281 | #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L |
|---|
| 3282 | #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L |
|---|
| 3283 | #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L |
|---|
| 3284 | #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L |
|---|
| 3285 | #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L |
|---|
| 3286 | #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0000F000L |
|---|
| 3287 | #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x000F0000L |
|---|
| 3288 | #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00300000L |
|---|
| 3289 | #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x00C00000L |
|---|
| 3290 | #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x07000000L |
|---|
| 3291 | #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0x38000000L |
|---|
| 3292 | //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 |
|---|
| 3293 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 |
|---|
| 3294 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 |
|---|
| 3295 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe |
|---|
| 3296 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L |
|---|
| 3297 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL |
|---|
| 3298 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L |
|---|
| 3299 | //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 |
|---|
| 3300 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 |
|---|
| 3301 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 |
|---|
| 3302 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe |
|---|
| 3303 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L |
|---|
| 3304 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL |
|---|
| 3305 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L |
|---|
| 3306 | //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 |
|---|
| 3307 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 |
|---|
| 3308 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 |
|---|
| 3309 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe |
|---|
| 3310 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L |
|---|
| 3311 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL |
|---|
| 3312 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L |
|---|
| 3313 | //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 |
|---|
| 3314 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 |
|---|
| 3315 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 |
|---|
| 3316 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe |
|---|
| 3317 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L |
|---|
| 3318 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL |
|---|
| 3319 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L |
|---|
| 3320 | //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 |
|---|
| 3321 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 |
|---|
| 3322 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 |
|---|
| 3323 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe |
|---|
| 3324 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L |
|---|
| 3325 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL |
|---|
| 3326 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L |
|---|
| 3327 | //MMEA0_ADDRDECDRAM_ADDR_HASH_PC |
|---|
| 3328 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 |
|---|
| 3329 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 |
|---|
| 3330 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe |
|---|
| 3331 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L |
|---|
| 3332 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL |
|---|
| 3333 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L |
|---|
| 3334 | //MMEA0_ADDRDECDRAM_ADDR_HASH_PC2 |
|---|
| 3335 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 |
|---|
| 3336 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL |
|---|
| 3337 | //MMEA0_ADDRDECDRAM_ADDR_HASH_CS0 |
|---|
| 3338 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 |
|---|
| 3339 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 |
|---|
| 3340 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L |
|---|
| 3341 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL |
|---|
| 3342 | //MMEA0_ADDRDECDRAM_ADDR_HASH_CS1 |
|---|
| 3343 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 |
|---|
| 3344 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 |
|---|
| 3345 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L |
|---|
| 3346 | #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL |
|---|
| 3347 | //MMEA0_ADDRDECDRAM_HARVEST_ENABLE |
|---|
| 3348 | #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 |
|---|
| 3349 | #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 |
|---|
| 3350 | #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 |
|---|
| 3351 | #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 |
|---|
| 3352 | #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L |
|---|
| 3353 | #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L |
|---|
| 3354 | #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L |
|---|
| 3355 | #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L |
|---|
| 3356 | //MMEA0_ADDRDEC0_BASE_ADDR_CS0 |
|---|
| 3357 | #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 |
|---|
| 3358 | #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 |
|---|
| 3359 | #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L |
|---|
| 3360 | #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 3361 | //MMEA0_ADDRDEC0_BASE_ADDR_CS1 |
|---|
| 3362 | #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 |
|---|
| 3363 | #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 |
|---|
| 3364 | #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L |
|---|
| 3365 | #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 3366 | //MMEA0_ADDRDEC0_BASE_ADDR_CS2 |
|---|
| 3367 | #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 |
|---|
| 3368 | #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 |
|---|
| 3369 | #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L |
|---|
| 3370 | #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 3371 | //MMEA0_ADDRDEC0_BASE_ADDR_CS3 |
|---|
| 3372 | #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 |
|---|
| 3373 | #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 |
|---|
| 3374 | #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L |
|---|
| 3375 | #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 3376 | //MMEA0_ADDRDEC0_BASE_ADDR_SECCS0 |
|---|
| 3377 | #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 |
|---|
| 3378 | #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 |
|---|
| 3379 | #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L |
|---|
| 3380 | #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 3381 | //MMEA0_ADDRDEC0_BASE_ADDR_SECCS1 |
|---|
| 3382 | #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 |
|---|
| 3383 | #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 |
|---|
| 3384 | #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L |
|---|
| 3385 | #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 3386 | //MMEA0_ADDRDEC0_BASE_ADDR_SECCS2 |
|---|
| 3387 | #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 |
|---|
| 3388 | #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 |
|---|
| 3389 | #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L |
|---|
| 3390 | #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 3391 | //MMEA0_ADDRDEC0_BASE_ADDR_SECCS3 |
|---|
| 3392 | #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 |
|---|
| 3393 | #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 |
|---|
| 3394 | #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L |
|---|
| 3395 | #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 3396 | //MMEA0_ADDRDEC0_ADDR_MASK_CS01 |
|---|
| 3397 | #define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 |
|---|
| 3398 | #define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL |
|---|
| 3399 | //MMEA0_ADDRDEC0_ADDR_MASK_CS23 |
|---|
| 3400 | #define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 |
|---|
| 3401 | #define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL |
|---|
| 3402 | //MMEA0_ADDRDEC0_ADDR_MASK_SECCS01 |
|---|
| 3403 | #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 |
|---|
| 3404 | #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL |
|---|
| 3405 | //MMEA0_ADDRDEC0_ADDR_MASK_SECCS23 |
|---|
| 3406 | #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 |
|---|
| 3407 | #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL |
|---|
| 3408 | //MMEA0_ADDRDEC0_ADDR_CFG_CS01 |
|---|
| 3409 | #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 |
|---|
| 3410 | #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 |
|---|
| 3411 | #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 |
|---|
| 3412 | #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc |
|---|
| 3413 | #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 |
|---|
| 3414 | #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 |
|---|
| 3415 | #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL |
|---|
| 3416 | #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L |
|---|
| 3417 | #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L |
|---|
| 3418 | #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L |
|---|
| 3419 | #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L |
|---|
| 3420 | #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L |
|---|
| 3421 | //MMEA0_ADDRDEC0_ADDR_CFG_CS23 |
|---|
| 3422 | #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 |
|---|
| 3423 | #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 |
|---|
| 3424 | #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 |
|---|
| 3425 | #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc |
|---|
| 3426 | #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 |
|---|
| 3427 | #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 |
|---|
| 3428 | #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL |
|---|
| 3429 | #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L |
|---|
| 3430 | #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L |
|---|
| 3431 | #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L |
|---|
| 3432 | #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L |
|---|
| 3433 | #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L |
|---|
| 3434 | //MMEA0_ADDRDEC0_ADDR_SEL_CS01 |
|---|
| 3435 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 |
|---|
| 3436 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 |
|---|
| 3437 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 |
|---|
| 3438 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc |
|---|
| 3439 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 |
|---|
| 3440 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 |
|---|
| 3441 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c |
|---|
| 3442 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL |
|---|
| 3443 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L |
|---|
| 3444 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L |
|---|
| 3445 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L |
|---|
| 3446 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L |
|---|
| 3447 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L |
|---|
| 3448 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L |
|---|
| 3449 | //MMEA0_ADDRDEC0_ADDR_SEL_CS23 |
|---|
| 3450 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 |
|---|
| 3451 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 |
|---|
| 3452 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 |
|---|
| 3453 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc |
|---|
| 3454 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 |
|---|
| 3455 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 |
|---|
| 3456 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c |
|---|
| 3457 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL |
|---|
| 3458 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L |
|---|
| 3459 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L |
|---|
| 3460 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L |
|---|
| 3461 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L |
|---|
| 3462 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L |
|---|
| 3463 | #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L |
|---|
| 3464 | //MMEA0_ADDRDEC0_COL_SEL_LO_CS01 |
|---|
| 3465 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 |
|---|
| 3466 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 |
|---|
| 3467 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 |
|---|
| 3468 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc |
|---|
| 3469 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 |
|---|
| 3470 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 |
|---|
| 3471 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 |
|---|
| 3472 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c |
|---|
| 3473 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL |
|---|
| 3474 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L |
|---|
| 3475 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L |
|---|
| 3476 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L |
|---|
| 3477 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L |
|---|
| 3478 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L |
|---|
| 3479 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L |
|---|
| 3480 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L |
|---|
| 3481 | //MMEA0_ADDRDEC0_COL_SEL_LO_CS23 |
|---|
| 3482 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 |
|---|
| 3483 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 |
|---|
| 3484 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 |
|---|
| 3485 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc |
|---|
| 3486 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 |
|---|
| 3487 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 |
|---|
| 3488 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 |
|---|
| 3489 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c |
|---|
| 3490 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL |
|---|
| 3491 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L |
|---|
| 3492 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L |
|---|
| 3493 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L |
|---|
| 3494 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L |
|---|
| 3495 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L |
|---|
| 3496 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L |
|---|
| 3497 | #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L |
|---|
| 3498 | //MMEA0_ADDRDEC0_COL_SEL_HI_CS01 |
|---|
| 3499 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 |
|---|
| 3500 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 |
|---|
| 3501 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 |
|---|
| 3502 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc |
|---|
| 3503 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 |
|---|
| 3504 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 |
|---|
| 3505 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 |
|---|
| 3506 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c |
|---|
| 3507 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL |
|---|
| 3508 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L |
|---|
| 3509 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L |
|---|
| 3510 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L |
|---|
| 3511 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L |
|---|
| 3512 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L |
|---|
| 3513 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L |
|---|
| 3514 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L |
|---|
| 3515 | //MMEA0_ADDRDEC0_COL_SEL_HI_CS23 |
|---|
| 3516 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 |
|---|
| 3517 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 |
|---|
| 3518 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 |
|---|
| 3519 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc |
|---|
| 3520 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 |
|---|
| 3521 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 |
|---|
| 3522 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 |
|---|
| 3523 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c |
|---|
| 3524 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL |
|---|
| 3525 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L |
|---|
| 3526 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L |
|---|
| 3527 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L |
|---|
| 3528 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L |
|---|
| 3529 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L |
|---|
| 3530 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L |
|---|
| 3531 | #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L |
|---|
| 3532 | //MMEA0_ADDRDEC0_RM_SEL_CS01 |
|---|
| 3533 | #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 |
|---|
| 3534 | #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 |
|---|
| 3535 | #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 |
|---|
| 3536 | #define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc |
|---|
| 3537 | #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
|---|
| 3538 | #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
|---|
| 3539 | #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL |
|---|
| 3540 | #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L |
|---|
| 3541 | #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L |
|---|
| 3542 | #define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L |
|---|
| 3543 | #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
|---|
| 3544 | #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
|---|
| 3545 | //MMEA0_ADDRDEC0_RM_SEL_CS23 |
|---|
| 3546 | #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 |
|---|
| 3547 | #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 |
|---|
| 3548 | #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 |
|---|
| 3549 | #define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc |
|---|
| 3550 | #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
|---|
| 3551 | #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
|---|
| 3552 | #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL |
|---|
| 3553 | #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L |
|---|
| 3554 | #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L |
|---|
| 3555 | #define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L |
|---|
| 3556 | #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
|---|
| 3557 | #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
|---|
| 3558 | //MMEA0_ADDRDEC0_RM_SEL_SECCS01 |
|---|
| 3559 | #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 |
|---|
| 3560 | #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 |
|---|
| 3561 | #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 |
|---|
| 3562 | #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc |
|---|
| 3563 | #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
|---|
| 3564 | #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
|---|
| 3565 | #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL |
|---|
| 3566 | #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L |
|---|
| 3567 | #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L |
|---|
| 3568 | #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L |
|---|
| 3569 | #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
|---|
| 3570 | #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
|---|
| 3571 | //MMEA0_ADDRDEC0_RM_SEL_SECCS23 |
|---|
| 3572 | #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 |
|---|
| 3573 | #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 |
|---|
| 3574 | #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 |
|---|
| 3575 | #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc |
|---|
| 3576 | #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
|---|
| 3577 | #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
|---|
| 3578 | #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL |
|---|
| 3579 | #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L |
|---|
| 3580 | #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L |
|---|
| 3581 | #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L |
|---|
| 3582 | #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
|---|
| 3583 | #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
|---|
| 3584 | //MMEA0_ADDRDEC1_BASE_ADDR_CS0 |
|---|
| 3585 | #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 |
|---|
| 3586 | #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 |
|---|
| 3587 | #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L |
|---|
| 3588 | #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 3589 | //MMEA0_ADDRDEC1_BASE_ADDR_CS1 |
|---|
| 3590 | #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 |
|---|
| 3591 | #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 |
|---|
| 3592 | #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L |
|---|
| 3593 | #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 3594 | //MMEA0_ADDRDEC1_BASE_ADDR_CS2 |
|---|
| 3595 | #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 |
|---|
| 3596 | #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 |
|---|
| 3597 | #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L |
|---|
| 3598 | #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 3599 | //MMEA0_ADDRDEC1_BASE_ADDR_CS3 |
|---|
| 3600 | #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 |
|---|
| 3601 | #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 |
|---|
| 3602 | #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L |
|---|
| 3603 | #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 3604 | //MMEA0_ADDRDEC1_BASE_ADDR_SECCS0 |
|---|
| 3605 | #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 |
|---|
| 3606 | #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 |
|---|
| 3607 | #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L |
|---|
| 3608 | #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 3609 | //MMEA0_ADDRDEC1_BASE_ADDR_SECCS1 |
|---|
| 3610 | #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 |
|---|
| 3611 | #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 |
|---|
| 3612 | #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L |
|---|
| 3613 | #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 3614 | //MMEA0_ADDRDEC1_BASE_ADDR_SECCS2 |
|---|
| 3615 | #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 |
|---|
| 3616 | #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 |
|---|
| 3617 | #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L |
|---|
| 3618 | #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 3619 | //MMEA0_ADDRDEC1_BASE_ADDR_SECCS3 |
|---|
| 3620 | #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 |
|---|
| 3621 | #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 |
|---|
| 3622 | #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L |
|---|
| 3623 | #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 3624 | //MMEA0_ADDRDEC1_ADDR_MASK_CS01 |
|---|
| 3625 | #define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 |
|---|
| 3626 | #define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL |
|---|
| 3627 | //MMEA0_ADDRDEC1_ADDR_MASK_CS23 |
|---|
| 3628 | #define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 |
|---|
| 3629 | #define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL |
|---|
| 3630 | //MMEA0_ADDRDEC1_ADDR_MASK_SECCS01 |
|---|
| 3631 | #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 |
|---|
| 3632 | #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL |
|---|
| 3633 | //MMEA0_ADDRDEC1_ADDR_MASK_SECCS23 |
|---|
| 3634 | #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 |
|---|
| 3635 | #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL |
|---|
| 3636 | //MMEA0_ADDRDEC1_ADDR_CFG_CS01 |
|---|
| 3637 | #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 |
|---|
| 3638 | #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 |
|---|
| 3639 | #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 |
|---|
| 3640 | #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc |
|---|
| 3641 | #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 |
|---|
| 3642 | #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 |
|---|
| 3643 | #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL |
|---|
| 3644 | #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L |
|---|
| 3645 | #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L |
|---|
| 3646 | #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L |
|---|
| 3647 | #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L |
|---|
| 3648 | #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L |
|---|
| 3649 | //MMEA0_ADDRDEC1_ADDR_CFG_CS23 |
|---|
| 3650 | #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 |
|---|
| 3651 | #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 |
|---|
| 3652 | #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 |
|---|
| 3653 | #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc |
|---|
| 3654 | #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 |
|---|
| 3655 | #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 |
|---|
| 3656 | #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL |
|---|
| 3657 | #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L |
|---|
| 3658 | #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L |
|---|
| 3659 | #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L |
|---|
| 3660 | #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L |
|---|
| 3661 | #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L |
|---|
| 3662 | //MMEA0_ADDRDEC1_ADDR_SEL_CS01 |
|---|
| 3663 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 |
|---|
| 3664 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 |
|---|
| 3665 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 |
|---|
| 3666 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc |
|---|
| 3667 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 |
|---|
| 3668 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 |
|---|
| 3669 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c |
|---|
| 3670 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL |
|---|
| 3671 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L |
|---|
| 3672 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L |
|---|
| 3673 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L |
|---|
| 3674 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L |
|---|
| 3675 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L |
|---|
| 3676 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L |
|---|
| 3677 | //MMEA0_ADDRDEC1_ADDR_SEL_CS23 |
|---|
| 3678 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 |
|---|
| 3679 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 |
|---|
| 3680 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 |
|---|
| 3681 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc |
|---|
| 3682 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 |
|---|
| 3683 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 |
|---|
| 3684 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c |
|---|
| 3685 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL |
|---|
| 3686 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L |
|---|
| 3687 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L |
|---|
| 3688 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L |
|---|
| 3689 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L |
|---|
| 3690 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L |
|---|
| 3691 | #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L |
|---|
| 3692 | //MMEA0_ADDRDEC1_COL_SEL_LO_CS01 |
|---|
| 3693 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 |
|---|
| 3694 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 |
|---|
| 3695 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 |
|---|
| 3696 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc |
|---|
| 3697 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 |
|---|
| 3698 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 |
|---|
| 3699 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 |
|---|
| 3700 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c |
|---|
| 3701 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL |
|---|
| 3702 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L |
|---|
| 3703 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L |
|---|
| 3704 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L |
|---|
| 3705 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L |
|---|
| 3706 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L |
|---|
| 3707 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L |
|---|
| 3708 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L |
|---|
| 3709 | //MMEA0_ADDRDEC1_COL_SEL_LO_CS23 |
|---|
| 3710 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 |
|---|
| 3711 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 |
|---|
| 3712 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 |
|---|
| 3713 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc |
|---|
| 3714 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 |
|---|
| 3715 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 |
|---|
| 3716 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 |
|---|
| 3717 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c |
|---|
| 3718 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL |
|---|
| 3719 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L |
|---|
| 3720 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L |
|---|
| 3721 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L |
|---|
| 3722 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L |
|---|
| 3723 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L |
|---|
| 3724 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L |
|---|
| 3725 | #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L |
|---|
| 3726 | //MMEA0_ADDRDEC1_COL_SEL_HI_CS01 |
|---|
| 3727 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 |
|---|
| 3728 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 |
|---|
| 3729 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 |
|---|
| 3730 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc |
|---|
| 3731 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 |
|---|
| 3732 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 |
|---|
| 3733 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 |
|---|
| 3734 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c |
|---|
| 3735 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL |
|---|
| 3736 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L |
|---|
| 3737 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L |
|---|
| 3738 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L |
|---|
| 3739 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L |
|---|
| 3740 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L |
|---|
| 3741 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L |
|---|
| 3742 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L |
|---|
| 3743 | //MMEA0_ADDRDEC1_COL_SEL_HI_CS23 |
|---|
| 3744 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 |
|---|
| 3745 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 |
|---|
| 3746 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 |
|---|
| 3747 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc |
|---|
| 3748 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 |
|---|
| 3749 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 |
|---|
| 3750 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 |
|---|
| 3751 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c |
|---|
| 3752 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL |
|---|
| 3753 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L |
|---|
| 3754 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L |
|---|
| 3755 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L |
|---|
| 3756 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L |
|---|
| 3757 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L |
|---|
| 3758 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L |
|---|
| 3759 | #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L |
|---|
| 3760 | //MMEA0_ADDRDEC1_RM_SEL_CS01 |
|---|
| 3761 | #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 |
|---|
| 3762 | #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 |
|---|
| 3763 | #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 |
|---|
| 3764 | #define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc |
|---|
| 3765 | #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
|---|
| 3766 | #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
|---|
| 3767 | #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL |
|---|
| 3768 | #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L |
|---|
| 3769 | #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L |
|---|
| 3770 | #define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L |
|---|
| 3771 | #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
|---|
| 3772 | #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
|---|
| 3773 | //MMEA0_ADDRDEC1_RM_SEL_CS23 |
|---|
| 3774 | #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 |
|---|
| 3775 | #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 |
|---|
| 3776 | #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 |
|---|
| 3777 | #define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc |
|---|
| 3778 | #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
|---|
| 3779 | #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
|---|
| 3780 | #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL |
|---|
| 3781 | #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L |
|---|
| 3782 | #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L |
|---|
| 3783 | #define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L |
|---|
| 3784 | #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
|---|
| 3785 | #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
|---|
| 3786 | //MMEA0_ADDRDEC1_RM_SEL_SECCS01 |
|---|
| 3787 | #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 |
|---|
| 3788 | #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 |
|---|
| 3789 | #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 |
|---|
| 3790 | #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc |
|---|
| 3791 | #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
|---|
| 3792 | #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
|---|
| 3793 | #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL |
|---|
| 3794 | #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L |
|---|
| 3795 | #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L |
|---|
| 3796 | #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L |
|---|
| 3797 | #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
|---|
| 3798 | #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
|---|
| 3799 | //MMEA0_ADDRDEC1_RM_SEL_SECCS23 |
|---|
| 3800 | #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 |
|---|
| 3801 | #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 |
|---|
| 3802 | #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 |
|---|
| 3803 | #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc |
|---|
| 3804 | #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
|---|
| 3805 | #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
|---|
| 3806 | #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL |
|---|
| 3807 | #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L |
|---|
| 3808 | #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L |
|---|
| 3809 | #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L |
|---|
| 3810 | #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
|---|
| 3811 | #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
|---|
| 3812 | //MMEA0_IO_RD_CLI2GRP_MAP0 |
|---|
| 3813 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
|---|
| 3814 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
|---|
| 3815 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
|---|
| 3816 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
|---|
| 3817 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
|---|
| 3818 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
|---|
| 3819 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
|---|
| 3820 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
|---|
| 3821 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
|---|
| 3822 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
|---|
| 3823 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
|---|
| 3824 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
|---|
| 3825 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
|---|
| 3826 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
|---|
| 3827 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
|---|
| 3828 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
|---|
| 3829 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
|---|
| 3830 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
|---|
| 3831 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
|---|
| 3832 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
|---|
| 3833 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
|---|
| 3834 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
|---|
| 3835 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
|---|
| 3836 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
|---|
| 3837 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
|---|
| 3838 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
|---|
| 3839 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
|---|
| 3840 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
|---|
| 3841 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
|---|
| 3842 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
|---|
| 3843 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
|---|
| 3844 | #define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
|---|
| 3845 | //MMEA0_IO_RD_CLI2GRP_MAP1 |
|---|
| 3846 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
|---|
| 3847 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
|---|
| 3848 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
|---|
| 3849 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
|---|
| 3850 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
|---|
| 3851 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
|---|
| 3852 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
|---|
| 3853 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
|---|
| 3854 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
|---|
| 3855 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
|---|
| 3856 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
|---|
| 3857 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
|---|
| 3858 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
|---|
| 3859 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
|---|
| 3860 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
|---|
| 3861 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
|---|
| 3862 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
|---|
| 3863 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
|---|
| 3864 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
|---|
| 3865 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
|---|
| 3866 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
|---|
| 3867 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
|---|
| 3868 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
|---|
| 3869 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
|---|
| 3870 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
|---|
| 3871 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
|---|
| 3872 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
|---|
| 3873 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
|---|
| 3874 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
|---|
| 3875 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
|---|
| 3876 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
|---|
| 3877 | #define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
|---|
| 3878 | //MMEA0_IO_WR_CLI2GRP_MAP0 |
|---|
| 3879 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
|---|
| 3880 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
|---|
| 3881 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
|---|
| 3882 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
|---|
| 3883 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
|---|
| 3884 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
|---|
| 3885 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
|---|
| 3886 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
|---|
| 3887 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
|---|
| 3888 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
|---|
| 3889 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
|---|
| 3890 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
|---|
| 3891 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
|---|
| 3892 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
|---|
| 3893 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
|---|
| 3894 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
|---|
| 3895 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
|---|
| 3896 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
|---|
| 3897 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
|---|
| 3898 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
|---|
| 3899 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
|---|
| 3900 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
|---|
| 3901 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
|---|
| 3902 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
|---|
| 3903 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
|---|
| 3904 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
|---|
| 3905 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
|---|
| 3906 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
|---|
| 3907 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
|---|
| 3908 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
|---|
| 3909 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
|---|
| 3910 | #define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
|---|
| 3911 | //MMEA0_IO_WR_CLI2GRP_MAP1 |
|---|
| 3912 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
|---|
| 3913 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
|---|
| 3914 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
|---|
| 3915 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
|---|
| 3916 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
|---|
| 3917 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
|---|
| 3918 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
|---|
| 3919 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
|---|
| 3920 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
|---|
| 3921 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
|---|
| 3922 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
|---|
| 3923 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
|---|
| 3924 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
|---|
| 3925 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
|---|
| 3926 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
|---|
| 3927 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
|---|
| 3928 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
|---|
| 3929 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
|---|
| 3930 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
|---|
| 3931 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
|---|
| 3932 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
|---|
| 3933 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
|---|
| 3934 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
|---|
| 3935 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
|---|
| 3936 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
|---|
| 3937 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
|---|
| 3938 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
|---|
| 3939 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
|---|
| 3940 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
|---|
| 3941 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
|---|
| 3942 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
|---|
| 3943 | #define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
|---|
| 3944 | //MMEA0_IO_RD_COMBINE_FLUSH |
|---|
| 3945 | #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
|---|
| 3946 | #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
|---|
| 3947 | #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
|---|
| 3948 | #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
|---|
| 3949 | #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
|---|
| 3950 | #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
|---|
| 3951 | #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
|---|
| 3952 | #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
|---|
| 3953 | //MMEA0_IO_WR_COMBINE_FLUSH |
|---|
| 3954 | #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
|---|
| 3955 | #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
|---|
| 3956 | #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
|---|
| 3957 | #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
|---|
| 3958 | #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
|---|
| 3959 | #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
|---|
| 3960 | #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
|---|
| 3961 | #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
|---|
| 3962 | //MMEA0_IO_GROUP_BURST |
|---|
| 3963 | #define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 |
|---|
| 3964 | #define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 |
|---|
| 3965 | #define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 |
|---|
| 3966 | #define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 |
|---|
| 3967 | #define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
|---|
| 3968 | #define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
|---|
| 3969 | #define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
|---|
| 3970 | #define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
|---|
| 3971 | //MMEA0_IO_RD_PRI_AGE |
|---|
| 3972 | #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
|---|
| 3973 | #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
|---|
| 3974 | #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
|---|
| 3975 | #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
|---|
| 3976 | #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
|---|
| 3977 | #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
|---|
| 3978 | #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
|---|
| 3979 | #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
|---|
| 3980 | #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
|---|
| 3981 | #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
|---|
| 3982 | #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
|---|
| 3983 | #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
|---|
| 3984 | #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
|---|
| 3985 | #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
|---|
| 3986 | #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
|---|
| 3987 | #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
|---|
| 3988 | //MMEA0_IO_WR_PRI_AGE |
|---|
| 3989 | #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
|---|
| 3990 | #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
|---|
| 3991 | #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
|---|
| 3992 | #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
|---|
| 3993 | #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
|---|
| 3994 | #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
|---|
| 3995 | #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
|---|
| 3996 | #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
|---|
| 3997 | #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
|---|
| 3998 | #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
|---|
| 3999 | #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
|---|
| 4000 | #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
|---|
| 4001 | #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
|---|
| 4002 | #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
|---|
| 4003 | #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
|---|
| 4004 | #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
|---|
| 4005 | //MMEA0_IO_RD_PRI_QUEUING |
|---|
| 4006 | #define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
|---|
| 4007 | #define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
|---|
| 4008 | #define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
|---|
| 4009 | #define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
|---|
| 4010 | #define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
|---|
| 4011 | #define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
|---|
| 4012 | #define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
|---|
| 4013 | #define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
|---|
| 4014 | //MMEA0_IO_WR_PRI_QUEUING |
|---|
| 4015 | #define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
|---|
| 4016 | #define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
|---|
| 4017 | #define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
|---|
| 4018 | #define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
|---|
| 4019 | #define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
|---|
| 4020 | #define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
|---|
| 4021 | #define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
|---|
| 4022 | #define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
|---|
| 4023 | //MMEA0_IO_RD_PRI_FIXED |
|---|
| 4024 | #define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
|---|
| 4025 | #define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
|---|
| 4026 | #define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
|---|
| 4027 | #define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
|---|
| 4028 | #define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
|---|
| 4029 | #define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
|---|
| 4030 | #define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
|---|
| 4031 | #define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
|---|
| 4032 | //MMEA0_IO_WR_PRI_FIXED |
|---|
| 4033 | #define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
|---|
| 4034 | #define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
|---|
| 4035 | #define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
|---|
| 4036 | #define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
|---|
| 4037 | #define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
|---|
| 4038 | #define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
|---|
| 4039 | #define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
|---|
| 4040 | #define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
|---|
| 4041 | //MMEA0_IO_RD_PRI_URGENCY |
|---|
| 4042 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
|---|
| 4043 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
|---|
| 4044 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
|---|
| 4045 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
|---|
| 4046 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
|---|
| 4047 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
|---|
| 4048 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
|---|
| 4049 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
|---|
| 4050 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
|---|
| 4051 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
|---|
| 4052 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
|---|
| 4053 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
|---|
| 4054 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
|---|
| 4055 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
|---|
| 4056 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
|---|
| 4057 | #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
|---|
| 4058 | //MMEA0_IO_WR_PRI_URGENCY |
|---|
| 4059 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
|---|
| 4060 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
|---|
| 4061 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
|---|
| 4062 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
|---|
| 4063 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
|---|
| 4064 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
|---|
| 4065 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
|---|
| 4066 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
|---|
| 4067 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
|---|
| 4068 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
|---|
| 4069 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
|---|
| 4070 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
|---|
| 4071 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
|---|
| 4072 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
|---|
| 4073 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
|---|
| 4074 | #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
|---|
| 4075 | //MMEA0_IO_RD_PRI_URGENCY_MASK |
|---|
| 4076 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 |
|---|
| 4077 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 |
|---|
| 4078 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 |
|---|
| 4079 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 |
|---|
| 4080 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 |
|---|
| 4081 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 |
|---|
| 4082 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 |
|---|
| 4083 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 |
|---|
| 4084 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 |
|---|
| 4085 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 |
|---|
| 4086 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa |
|---|
| 4087 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb |
|---|
| 4088 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc |
|---|
| 4089 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd |
|---|
| 4090 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe |
|---|
| 4091 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf |
|---|
| 4092 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 |
|---|
| 4093 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 |
|---|
| 4094 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 |
|---|
| 4095 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 |
|---|
| 4096 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 |
|---|
| 4097 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 |
|---|
| 4098 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 |
|---|
| 4099 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 |
|---|
| 4100 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 |
|---|
| 4101 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 |
|---|
| 4102 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a |
|---|
| 4103 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b |
|---|
| 4104 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c |
|---|
| 4105 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d |
|---|
| 4106 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e |
|---|
| 4107 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f |
|---|
| 4108 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L |
|---|
| 4109 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L |
|---|
| 4110 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L |
|---|
| 4111 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L |
|---|
| 4112 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L |
|---|
| 4113 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L |
|---|
| 4114 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L |
|---|
| 4115 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L |
|---|
| 4116 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L |
|---|
| 4117 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L |
|---|
| 4118 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L |
|---|
| 4119 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L |
|---|
| 4120 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L |
|---|
| 4121 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L |
|---|
| 4122 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L |
|---|
| 4123 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L |
|---|
| 4124 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L |
|---|
| 4125 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L |
|---|
| 4126 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L |
|---|
| 4127 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L |
|---|
| 4128 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L |
|---|
| 4129 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L |
|---|
| 4130 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L |
|---|
| 4131 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L |
|---|
| 4132 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L |
|---|
| 4133 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L |
|---|
| 4134 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L |
|---|
| 4135 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L |
|---|
| 4136 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L |
|---|
| 4137 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L |
|---|
| 4138 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L |
|---|
| 4139 | #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L |
|---|
| 4140 | //MMEA0_IO_WR_PRI_URGENCY_MASK |
|---|
| 4141 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 |
|---|
| 4142 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 |
|---|
| 4143 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 |
|---|
| 4144 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 |
|---|
| 4145 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 |
|---|
| 4146 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 |
|---|
| 4147 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 |
|---|
| 4148 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 |
|---|
| 4149 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 |
|---|
| 4150 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 |
|---|
| 4151 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa |
|---|
| 4152 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb |
|---|
| 4153 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc |
|---|
| 4154 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd |
|---|
| 4155 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe |
|---|
| 4156 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf |
|---|
| 4157 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 |
|---|
| 4158 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 |
|---|
| 4159 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 |
|---|
| 4160 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 |
|---|
| 4161 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 |
|---|
| 4162 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 |
|---|
| 4163 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 |
|---|
| 4164 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 |
|---|
| 4165 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 |
|---|
| 4166 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 |
|---|
| 4167 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a |
|---|
| 4168 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b |
|---|
| 4169 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c |
|---|
| 4170 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d |
|---|
| 4171 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e |
|---|
| 4172 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f |
|---|
| 4173 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L |
|---|
| 4174 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L |
|---|
| 4175 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L |
|---|
| 4176 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L |
|---|
| 4177 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L |
|---|
| 4178 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L |
|---|
| 4179 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L |
|---|
| 4180 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L |
|---|
| 4181 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L |
|---|
| 4182 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L |
|---|
| 4183 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L |
|---|
| 4184 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L |
|---|
| 4185 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L |
|---|
| 4186 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L |
|---|
| 4187 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L |
|---|
| 4188 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L |
|---|
| 4189 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L |
|---|
| 4190 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L |
|---|
| 4191 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L |
|---|
| 4192 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L |
|---|
| 4193 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L |
|---|
| 4194 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L |
|---|
| 4195 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L |
|---|
| 4196 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L |
|---|
| 4197 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L |
|---|
| 4198 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L |
|---|
| 4199 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L |
|---|
| 4200 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L |
|---|
| 4201 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L |
|---|
| 4202 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L |
|---|
| 4203 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L |
|---|
| 4204 | #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L |
|---|
| 4205 | //MMEA0_IO_RD_PRI_QUANT_PRI1 |
|---|
| 4206 | #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
|---|
| 4207 | #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
|---|
| 4208 | #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
|---|
| 4209 | #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
|---|
| 4210 | #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
|---|
| 4211 | #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
|---|
| 4212 | #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
|---|
| 4213 | #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
|---|
| 4214 | //MMEA0_IO_RD_PRI_QUANT_PRI2 |
|---|
| 4215 | #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
|---|
| 4216 | #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
|---|
| 4217 | #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
|---|
| 4218 | #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
|---|
| 4219 | #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
|---|
| 4220 | #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
|---|
| 4221 | #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
|---|
| 4222 | #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
|---|
| 4223 | //MMEA0_IO_RD_PRI_QUANT_PRI3 |
|---|
| 4224 | #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
|---|
| 4225 | #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
|---|
| 4226 | #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
|---|
| 4227 | #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
|---|
| 4228 | #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
|---|
| 4229 | #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
|---|
| 4230 | #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
|---|
| 4231 | #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
|---|
| 4232 | //MMEA0_IO_WR_PRI_QUANT_PRI1 |
|---|
| 4233 | #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
|---|
| 4234 | #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
|---|
| 4235 | #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
|---|
| 4236 | #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
|---|
| 4237 | #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
|---|
| 4238 | #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
|---|
| 4239 | #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
|---|
| 4240 | #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
|---|
| 4241 | //MMEA0_IO_WR_PRI_QUANT_PRI2 |
|---|
| 4242 | #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
|---|
| 4243 | #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
|---|
| 4244 | #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
|---|
| 4245 | #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
|---|
| 4246 | #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
|---|
| 4247 | #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
|---|
| 4248 | #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
|---|
| 4249 | #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
|---|
| 4250 | //MMEA0_IO_WR_PRI_QUANT_PRI3 |
|---|
| 4251 | #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
|---|
| 4252 | #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
|---|
| 4253 | #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
|---|
| 4254 | #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
|---|
| 4255 | #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
|---|
| 4256 | #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
|---|
| 4257 | #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
|---|
| 4258 | #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
|---|
| 4259 | //MMEA0_SDP_ARB_DRAM |
|---|
| 4260 | #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 |
|---|
| 4261 | #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 |
|---|
| 4262 | #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 |
|---|
| 4263 | #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 |
|---|
| 4264 | #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 |
|---|
| 4265 | #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 |
|---|
| 4266 | #define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 |
|---|
| 4267 | #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL |
|---|
| 4268 | #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L |
|---|
| 4269 | #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L |
|---|
| 4270 | #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L |
|---|
| 4271 | #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L |
|---|
| 4272 | #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L |
|---|
| 4273 | #define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L |
|---|
| 4274 | //MMEA0_SDP_ARB_FINAL |
|---|
| 4275 | #define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 |
|---|
| 4276 | #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 |
|---|
| 4277 | #define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa |
|---|
| 4278 | #define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf |
|---|
| 4279 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 |
|---|
| 4280 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 |
|---|
| 4281 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 |
|---|
| 4282 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 |
|---|
| 4283 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 |
|---|
| 4284 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 |
|---|
| 4285 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 |
|---|
| 4286 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 |
|---|
| 4287 | #define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 |
|---|
| 4288 | #define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a |
|---|
| 4289 | #define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL |
|---|
| 4290 | #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L |
|---|
| 4291 | #define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L |
|---|
| 4292 | #define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L |
|---|
| 4293 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L |
|---|
| 4294 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L |
|---|
| 4295 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L |
|---|
| 4296 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L |
|---|
| 4297 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L |
|---|
| 4298 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L |
|---|
| 4299 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L |
|---|
| 4300 | #define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L |
|---|
| 4301 | #define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L |
|---|
| 4302 | #define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L |
|---|
| 4303 | //MMEA0_SDP_DRAM_PRIORITY |
|---|
| 4304 | #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 |
|---|
| 4305 | #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 |
|---|
| 4306 | #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 |
|---|
| 4307 | #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc |
|---|
| 4308 | #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 |
|---|
| 4309 | #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 |
|---|
| 4310 | #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 |
|---|
| 4311 | #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c |
|---|
| 4312 | #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL |
|---|
| 4313 | #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L |
|---|
| 4314 | #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L |
|---|
| 4315 | #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L |
|---|
| 4316 | #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L |
|---|
| 4317 | #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L |
|---|
| 4318 | #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L |
|---|
| 4319 | #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L |
|---|
| 4320 | //MMEA0_SDP_IO_PRIORITY |
|---|
| 4321 | #define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 |
|---|
| 4322 | #define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 |
|---|
| 4323 | #define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 |
|---|
| 4324 | #define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc |
|---|
| 4325 | #define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 |
|---|
| 4326 | #define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 |
|---|
| 4327 | #define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 |
|---|
| 4328 | #define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c |
|---|
| 4329 | #define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL |
|---|
| 4330 | #define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L |
|---|
| 4331 | #define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L |
|---|
| 4332 | #define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L |
|---|
| 4333 | #define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L |
|---|
| 4334 | #define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L |
|---|
| 4335 | #define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L |
|---|
| 4336 | #define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L |
|---|
| 4337 | //MMEA0_SDP_CREDITS |
|---|
| 4338 | #define MMEA0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 |
|---|
| 4339 | #define MMEA0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 |
|---|
| 4340 | #define MMEA0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 |
|---|
| 4341 | #define MMEA0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL |
|---|
| 4342 | #define MMEA0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L |
|---|
| 4343 | #define MMEA0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L |
|---|
| 4344 | //MMEA0_SDP_TAG_RESERVE0 |
|---|
| 4345 | #define MMEA0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 |
|---|
| 4346 | #define MMEA0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 |
|---|
| 4347 | #define MMEA0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 |
|---|
| 4348 | #define MMEA0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 |
|---|
| 4349 | #define MMEA0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL |
|---|
| 4350 | #define MMEA0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L |
|---|
| 4351 | #define MMEA0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L |
|---|
| 4352 | #define MMEA0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L |
|---|
| 4353 | //MMEA0_SDP_TAG_RESERVE1 |
|---|
| 4354 | #define MMEA0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 |
|---|
| 4355 | #define MMEA0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 |
|---|
| 4356 | #define MMEA0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 |
|---|
| 4357 | #define MMEA0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 |
|---|
| 4358 | #define MMEA0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL |
|---|
| 4359 | #define MMEA0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L |
|---|
| 4360 | #define MMEA0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L |
|---|
| 4361 | #define MMEA0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L |
|---|
| 4362 | //MMEA0_SDP_VCC_RESERVE0 |
|---|
| 4363 | #define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 |
|---|
| 4364 | #define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 |
|---|
| 4365 | #define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc |
|---|
| 4366 | #define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 |
|---|
| 4367 | #define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 |
|---|
| 4368 | #define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL |
|---|
| 4369 | #define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L |
|---|
| 4370 | #define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L |
|---|
| 4371 | #define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L |
|---|
| 4372 | #define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L |
|---|
| 4373 | //MMEA0_SDP_VCC_RESERVE1 |
|---|
| 4374 | #define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 |
|---|
| 4375 | #define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 |
|---|
| 4376 | #define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc |
|---|
| 4377 | #define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f |
|---|
| 4378 | #define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL |
|---|
| 4379 | #define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L |
|---|
| 4380 | #define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L |
|---|
| 4381 | #define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L |
|---|
| 4382 | //MMEA0_SDP_VCD_RESERVE0 |
|---|
| 4383 | #define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 |
|---|
| 4384 | #define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 |
|---|
| 4385 | #define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc |
|---|
| 4386 | #define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 |
|---|
| 4387 | #define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 |
|---|
| 4388 | #define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL |
|---|
| 4389 | #define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L |
|---|
| 4390 | #define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L |
|---|
| 4391 | #define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L |
|---|
| 4392 | #define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L |
|---|
| 4393 | //MMEA0_SDP_VCD_RESERVE1 |
|---|
| 4394 | #define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 |
|---|
| 4395 | #define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 |
|---|
| 4396 | #define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc |
|---|
| 4397 | #define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f |
|---|
| 4398 | #define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL |
|---|
| 4399 | #define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L |
|---|
| 4400 | #define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L |
|---|
| 4401 | #define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L |
|---|
| 4402 | //MMEA0_SDP_REQ_CNTL |
|---|
| 4403 | #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 |
|---|
| 4404 | #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 |
|---|
| 4405 | #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 |
|---|
| 4406 | #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 |
|---|
| 4407 | #define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 |
|---|
| 4408 | #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L |
|---|
| 4409 | #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L |
|---|
| 4410 | #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L |
|---|
| 4411 | #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L |
|---|
| 4412 | #define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L |
|---|
| 4413 | //MMEA0_MISC |
|---|
| 4414 | #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 |
|---|
| 4415 | #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 |
|---|
| 4416 | #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 |
|---|
| 4417 | #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 |
|---|
| 4418 | #define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 |
|---|
| 4419 | #define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 |
|---|
| 4420 | #define MMEA0_MISC__RRET_SWAP_MODE__SHIFT 0x6 |
|---|
| 4421 | #define MMEA0_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x7 |
|---|
| 4422 | #define MMEA0_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x8 |
|---|
| 4423 | #define MMEA0_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xa |
|---|
| 4424 | #define MMEA0_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xc |
|---|
| 4425 | #define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xe |
|---|
| 4426 | #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x13 |
|---|
| 4427 | #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x14 |
|---|
| 4428 | #define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x15 |
|---|
| 4429 | #define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x16 |
|---|
| 4430 | #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x17 |
|---|
| 4431 | #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x18 |
|---|
| 4432 | #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L |
|---|
| 4433 | #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L |
|---|
| 4434 | #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L |
|---|
| 4435 | #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L |
|---|
| 4436 | #define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L |
|---|
| 4437 | #define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L |
|---|
| 4438 | #define MMEA0_MISC__RRET_SWAP_MODE_MASK 0x00000040L |
|---|
| 4439 | #define MMEA0_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000080L |
|---|
| 4440 | #define MMEA0_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000300L |
|---|
| 4441 | #define MMEA0_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00000C00L |
|---|
| 4442 | #define MMEA0_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00003000L |
|---|
| 4443 | #define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x0007C000L |
|---|
| 4444 | #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x00080000L |
|---|
| 4445 | #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x00100000L |
|---|
| 4446 | #define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x00200000L |
|---|
| 4447 | #define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x00400000L |
|---|
| 4448 | #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x00800000L |
|---|
| 4449 | #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x01000000L |
|---|
| 4450 | //MMEA0_LATENCY_SAMPLING |
|---|
| 4451 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 |
|---|
| 4452 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 |
|---|
| 4453 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 |
|---|
| 4454 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 |
|---|
| 4455 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 |
|---|
| 4456 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 |
|---|
| 4457 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 |
|---|
| 4458 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 |
|---|
| 4459 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 |
|---|
| 4460 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 |
|---|
| 4461 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa |
|---|
| 4462 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb |
|---|
| 4463 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc |
|---|
| 4464 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd |
|---|
| 4465 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe |
|---|
| 4466 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 |
|---|
| 4467 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L |
|---|
| 4468 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L |
|---|
| 4469 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L |
|---|
| 4470 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L |
|---|
| 4471 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L |
|---|
| 4472 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L |
|---|
| 4473 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L |
|---|
| 4474 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L |
|---|
| 4475 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L |
|---|
| 4476 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L |
|---|
| 4477 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L |
|---|
| 4478 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L |
|---|
| 4479 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L |
|---|
| 4480 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L |
|---|
| 4481 | #define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L |
|---|
| 4482 | #define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L |
|---|
| 4483 | //MMEA0_PERFCOUNTER_LO |
|---|
| 4484 | #define MMEA0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
|---|
| 4485 | #define MMEA0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
|---|
| 4486 | //MMEA0_PERFCOUNTER_HI |
|---|
| 4487 | #define MMEA0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
|---|
| 4488 | #define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
|---|
| 4489 | #define MMEA0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
|---|
| 4490 | #define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
|---|
| 4491 | //MMEA0_PERFCOUNTER0_CFG |
|---|
| 4492 | #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
|---|
| 4493 | #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
|---|
| 4494 | #define MMEA0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
|---|
| 4495 | #define MMEA0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
|---|
| 4496 | #define MMEA0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
|---|
| 4497 | #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
|---|
| 4498 | #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
|---|
| 4499 | #define MMEA0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
|---|
| 4500 | #define MMEA0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
|---|
| 4501 | #define MMEA0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
|---|
| 4502 | //MMEA0_PERFCOUNTER1_CFG |
|---|
| 4503 | #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
|---|
| 4504 | #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
|---|
| 4505 | #define MMEA0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
|---|
| 4506 | #define MMEA0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
|---|
| 4507 | #define MMEA0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
|---|
| 4508 | #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
|---|
| 4509 | #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
|---|
| 4510 | #define MMEA0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
|---|
| 4511 | #define MMEA0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
|---|
| 4512 | #define MMEA0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
|---|
| 4513 | //MMEA0_PERFCOUNTER_RSLT_CNTL |
|---|
| 4514 | #define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
|---|
| 4515 | #define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
|---|
| 4516 | #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
|---|
| 4517 | #define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
|---|
| 4518 | #define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
|---|
| 4519 | #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
|---|
| 4520 | #define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
|---|
| 4521 | #define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
|---|
| 4522 | #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
|---|
| 4523 | #define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
|---|
| 4524 | #define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
|---|
| 4525 | #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
|---|
| 4526 | //MMEA0_EDC_CNT |
|---|
| 4527 | #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 |
|---|
| 4528 | #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 |
|---|
| 4529 | #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 |
|---|
| 4530 | #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 |
|---|
| 4531 | #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 |
|---|
| 4532 | #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa |
|---|
| 4533 | #define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc |
|---|
| 4534 | #define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe |
|---|
| 4535 | #define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 |
|---|
| 4536 | #define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 |
|---|
| 4537 | #define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 |
|---|
| 4538 | #define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 |
|---|
| 4539 | #define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 |
|---|
| 4540 | #define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a |
|---|
| 4541 | #define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c |
|---|
| 4542 | #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L |
|---|
| 4543 | #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL |
|---|
| 4544 | #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L |
|---|
| 4545 | #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L |
|---|
| 4546 | #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L |
|---|
| 4547 | #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L |
|---|
| 4548 | #define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L |
|---|
| 4549 | #define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L |
|---|
| 4550 | #define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L |
|---|
| 4551 | #define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L |
|---|
| 4552 | #define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L |
|---|
| 4553 | #define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L |
|---|
| 4554 | #define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L |
|---|
| 4555 | #define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L |
|---|
| 4556 | #define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L |
|---|
| 4557 | //MMEA0_EDC_CNT2 |
|---|
| 4558 | #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 |
|---|
| 4559 | #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 |
|---|
| 4560 | #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 |
|---|
| 4561 | #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 |
|---|
| 4562 | #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 |
|---|
| 4563 | #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa |
|---|
| 4564 | #define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc |
|---|
| 4565 | #define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe |
|---|
| 4566 | #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L |
|---|
| 4567 | #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL |
|---|
| 4568 | #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L |
|---|
| 4569 | #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L |
|---|
| 4570 | #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L |
|---|
| 4571 | #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L |
|---|
| 4572 | #define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L |
|---|
| 4573 | #define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L |
|---|
| 4574 | //MMEA0_DSM_CNTL |
|---|
| 4575 | #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
|---|
| 4576 | #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
|---|
| 4577 | #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
|---|
| 4578 | #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
|---|
| 4579 | #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
|---|
| 4580 | #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
|---|
| 4581 | #define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
|---|
| 4582 | #define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
|---|
| 4583 | #define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc |
|---|
| 4584 | #define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
|---|
| 4585 | #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf |
|---|
| 4586 | #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
|---|
| 4587 | #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 |
|---|
| 4588 | #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
|---|
| 4589 | #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 |
|---|
| 4590 | #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 |
|---|
| 4591 | #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
|---|
| 4592 | #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
|---|
| 4593 | #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
|---|
| 4594 | #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
|---|
| 4595 | #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
|---|
| 4596 | #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
|---|
| 4597 | #define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
|---|
| 4598 | #define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
|---|
| 4599 | #define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
|---|
| 4600 | #define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
|---|
| 4601 | #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L |
|---|
| 4602 | #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
|---|
| 4603 | #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
|---|
| 4604 | #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
|---|
| 4605 | #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L |
|---|
| 4606 | #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L |
|---|
| 4607 | //MMEA0_DSM_CNTLA |
|---|
| 4608 | #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
|---|
| 4609 | #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
|---|
| 4610 | #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
|---|
| 4611 | #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
|---|
| 4612 | #define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
|---|
| 4613 | #define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
|---|
| 4614 | #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
|---|
| 4615 | #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
|---|
| 4616 | #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc |
|---|
| 4617 | #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
|---|
| 4618 | #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf |
|---|
| 4619 | #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
|---|
| 4620 | #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 |
|---|
| 4621 | #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
|---|
| 4622 | #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
|---|
| 4623 | #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
|---|
| 4624 | #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
|---|
| 4625 | #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
|---|
| 4626 | #define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
|---|
| 4627 | #define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
|---|
| 4628 | #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
|---|
| 4629 | #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
|---|
| 4630 | #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
|---|
| 4631 | #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
|---|
| 4632 | #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L |
|---|
| 4633 | #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
|---|
| 4634 | #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
|---|
| 4635 | #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
|---|
| 4636 | //MMEA0_DSM_CNTLB |
|---|
| 4637 | //MMEA0_DSM_CNTL2 |
|---|
| 4638 | #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
|---|
| 4639 | #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
|---|
| 4640 | #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
|---|
| 4641 | #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
|---|
| 4642 | #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
|---|
| 4643 | #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
|---|
| 4644 | #define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
|---|
| 4645 | #define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb |
|---|
| 4646 | #define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
|---|
| 4647 | #define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe |
|---|
| 4648 | #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf |
|---|
| 4649 | #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 |
|---|
| 4650 | #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 |
|---|
| 4651 | #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 |
|---|
| 4652 | #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 |
|---|
| 4653 | #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 |
|---|
| 4654 | #define MMEA0_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a |
|---|
| 4655 | #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
|---|
| 4656 | #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
|---|
| 4657 | #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
|---|
| 4658 | #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
|---|
| 4659 | #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
|---|
| 4660 | #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
|---|
| 4661 | #define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
|---|
| 4662 | #define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
|---|
| 4663 | #define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
|---|
| 4664 | #define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
|---|
| 4665 | #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L |
|---|
| 4666 | #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L |
|---|
| 4667 | #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
|---|
| 4668 | #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L |
|---|
| 4669 | #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L |
|---|
| 4670 | #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L |
|---|
| 4671 | #define MMEA0_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L |
|---|
| 4672 | //MMEA0_DSM_CNTL2A |
|---|
| 4673 | #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
|---|
| 4674 | #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
|---|
| 4675 | #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
|---|
| 4676 | #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
|---|
| 4677 | #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
|---|
| 4678 | #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
|---|
| 4679 | #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
|---|
| 4680 | #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb |
|---|
| 4681 | #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
|---|
| 4682 | #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe |
|---|
| 4683 | #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf |
|---|
| 4684 | #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 |
|---|
| 4685 | #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 |
|---|
| 4686 | #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 |
|---|
| 4687 | #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
|---|
| 4688 | #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
|---|
| 4689 | #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
|---|
| 4690 | #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
|---|
| 4691 | #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
|---|
| 4692 | #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
|---|
| 4693 | #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
|---|
| 4694 | #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
|---|
| 4695 | #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
|---|
| 4696 | #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
|---|
| 4697 | #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L |
|---|
| 4698 | #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L |
|---|
| 4699 | #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
|---|
| 4700 | #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L |
|---|
| 4701 | //MMEA0_DSM_CNTL2B |
|---|
| 4702 | //MMEA0_CGTT_CLK_CTRL |
|---|
| 4703 | #define MMEA0_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
|---|
| 4704 | #define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
|---|
| 4705 | #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 |
|---|
| 4706 | #define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b |
|---|
| 4707 | #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c |
|---|
| 4708 | #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d |
|---|
| 4709 | #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e |
|---|
| 4710 | #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f |
|---|
| 4711 | #define MMEA0_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
|---|
| 4712 | #define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
|---|
| 4713 | #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L |
|---|
| 4714 | #define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L |
|---|
| 4715 | #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L |
|---|
| 4716 | #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L |
|---|
| 4717 | #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L |
|---|
| 4718 | #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L |
|---|
| 4719 | //MMEA0_EDC_MODE |
|---|
| 4720 | #define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 |
|---|
| 4721 | #define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11 |
|---|
| 4722 | #define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14 |
|---|
| 4723 | #define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d |
|---|
| 4724 | #define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f |
|---|
| 4725 | #define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L |
|---|
| 4726 | #define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L |
|---|
| 4727 | #define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L |
|---|
| 4728 | #define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L |
|---|
| 4729 | #define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L |
|---|
| 4730 | //MMEA0_ERR_STATUS |
|---|
| 4731 | #define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 |
|---|
| 4732 | #define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 |
|---|
| 4733 | #define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0x8 |
|---|
| 4734 | #define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0x9 |
|---|
| 4735 | #define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xa |
|---|
| 4736 | #define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL |
|---|
| 4737 | #define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L |
|---|
| 4738 | #define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000100L |
|---|
| 4739 | #define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000200L |
|---|
| 4740 | #define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00000400L |
|---|
| 4741 | //MMEA0_MISC2 |
|---|
| 4742 | #define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 |
|---|
| 4743 | #define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 |
|---|
| 4744 | #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 |
|---|
| 4745 | #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 |
|---|
| 4746 | #define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L |
|---|
| 4747 | #define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L |
|---|
| 4748 | #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL |
|---|
| 4749 | #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L |
|---|
| 4750 | //MMEA1_DRAM_RD_CLI2GRP_MAP0 |
|---|
| 4751 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
|---|
| 4752 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
|---|
| 4753 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
|---|
| 4754 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
|---|
| 4755 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
|---|
| 4756 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
|---|
| 4757 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
|---|
| 4758 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
|---|
| 4759 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
|---|
| 4760 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
|---|
| 4761 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
|---|
| 4762 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
|---|
| 4763 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
|---|
| 4764 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
|---|
| 4765 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
|---|
| 4766 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
|---|
| 4767 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
|---|
| 4768 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
|---|
| 4769 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
|---|
| 4770 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
|---|
| 4771 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
|---|
| 4772 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
|---|
| 4773 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
|---|
| 4774 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
|---|
| 4775 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
|---|
| 4776 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
|---|
| 4777 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
|---|
| 4778 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
|---|
| 4779 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
|---|
| 4780 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
|---|
| 4781 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
|---|
| 4782 | #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
|---|
| 4783 | //MMEA1_DRAM_RD_CLI2GRP_MAP1 |
|---|
| 4784 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
|---|
| 4785 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
|---|
| 4786 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
|---|
| 4787 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
|---|
| 4788 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
|---|
| 4789 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
|---|
| 4790 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
|---|
| 4791 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
|---|
| 4792 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
|---|
| 4793 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
|---|
| 4794 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
|---|
| 4795 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
|---|
| 4796 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
|---|
| 4797 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
|---|
| 4798 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
|---|
| 4799 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
|---|
| 4800 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
|---|
| 4801 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
|---|
| 4802 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
|---|
| 4803 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
|---|
| 4804 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
|---|
| 4805 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
|---|
| 4806 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
|---|
| 4807 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
|---|
| 4808 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
|---|
| 4809 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
|---|
| 4810 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
|---|
| 4811 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
|---|
| 4812 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
|---|
| 4813 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
|---|
| 4814 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
|---|
| 4815 | #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
|---|
| 4816 | //MMEA1_DRAM_WR_CLI2GRP_MAP0 |
|---|
| 4817 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
|---|
| 4818 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
|---|
| 4819 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
|---|
| 4820 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
|---|
| 4821 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
|---|
| 4822 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
|---|
| 4823 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
|---|
| 4824 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
|---|
| 4825 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
|---|
| 4826 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
|---|
| 4827 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
|---|
| 4828 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
|---|
| 4829 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
|---|
| 4830 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
|---|
| 4831 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
|---|
| 4832 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
|---|
| 4833 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
|---|
| 4834 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
|---|
| 4835 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
|---|
| 4836 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
|---|
| 4837 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
|---|
| 4838 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
|---|
| 4839 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
|---|
| 4840 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
|---|
| 4841 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
|---|
| 4842 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
|---|
| 4843 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
|---|
| 4844 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
|---|
| 4845 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
|---|
| 4846 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
|---|
| 4847 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
|---|
| 4848 | #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
|---|
| 4849 | //MMEA1_DRAM_WR_CLI2GRP_MAP1 |
|---|
| 4850 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
|---|
| 4851 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
|---|
| 4852 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
|---|
| 4853 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
|---|
| 4854 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
|---|
| 4855 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
|---|
| 4856 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
|---|
| 4857 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
|---|
| 4858 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
|---|
| 4859 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
|---|
| 4860 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
|---|
| 4861 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
|---|
| 4862 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
|---|
| 4863 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
|---|
| 4864 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
|---|
| 4865 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
|---|
| 4866 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
|---|
| 4867 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
|---|
| 4868 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
|---|
| 4869 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
|---|
| 4870 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
|---|
| 4871 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
|---|
| 4872 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
|---|
| 4873 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
|---|
| 4874 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
|---|
| 4875 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
|---|
| 4876 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
|---|
| 4877 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
|---|
| 4878 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
|---|
| 4879 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
|---|
| 4880 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
|---|
| 4881 | #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
|---|
| 4882 | //MMEA1_DRAM_RD_GRP2VC_MAP |
|---|
| 4883 | #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
|---|
| 4884 | #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
|---|
| 4885 | #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
|---|
| 4886 | #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
|---|
| 4887 | #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
|---|
| 4888 | #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
|---|
| 4889 | #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
|---|
| 4890 | #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
|---|
| 4891 | //MMEA1_DRAM_WR_GRP2VC_MAP |
|---|
| 4892 | #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
|---|
| 4893 | #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
|---|
| 4894 | #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
|---|
| 4895 | #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
|---|
| 4896 | #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
|---|
| 4897 | #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
|---|
| 4898 | #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
|---|
| 4899 | #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
|---|
| 4900 | //MMEA1_DRAM_RD_LAZY |
|---|
| 4901 | #define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 |
|---|
| 4902 | #define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 |
|---|
| 4903 | #define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 |
|---|
| 4904 | #define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 |
|---|
| 4905 | #define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L |
|---|
| 4906 | #define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L |
|---|
| 4907 | #define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
|---|
| 4908 | #define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
|---|
| 4909 | //MMEA1_DRAM_WR_LAZY |
|---|
| 4910 | #define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 |
|---|
| 4911 | #define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 |
|---|
| 4912 | #define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 |
|---|
| 4913 | #define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 |
|---|
| 4914 | #define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L |
|---|
| 4915 | #define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L |
|---|
| 4916 | #define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
|---|
| 4917 | #define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
|---|
| 4918 | //MMEA1_DRAM_RD_CAM_CNTL |
|---|
| 4919 | #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
|---|
| 4920 | #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
|---|
| 4921 | #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
|---|
| 4922 | #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
|---|
| 4923 | #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
|---|
| 4924 | #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
|---|
| 4925 | #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
|---|
| 4926 | #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
|---|
| 4927 | #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
|---|
| 4928 | #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
|---|
| 4929 | #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
|---|
| 4930 | #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
|---|
| 4931 | #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
|---|
| 4932 | #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
|---|
| 4933 | #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
|---|
| 4934 | #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
|---|
| 4935 | //MMEA1_DRAM_WR_CAM_CNTL |
|---|
| 4936 | #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
|---|
| 4937 | #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
|---|
| 4938 | #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
|---|
| 4939 | #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
|---|
| 4940 | #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
|---|
| 4941 | #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
|---|
| 4942 | #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
|---|
| 4943 | #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
|---|
| 4944 | #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
|---|
| 4945 | #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
|---|
| 4946 | #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
|---|
| 4947 | #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
|---|
| 4948 | #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
|---|
| 4949 | #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
|---|
| 4950 | #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
|---|
| 4951 | #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
|---|
| 4952 | //MMEA1_DRAM_PAGE_BURST |
|---|
| 4953 | #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 |
|---|
| 4954 | #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 |
|---|
| 4955 | #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 |
|---|
| 4956 | #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 |
|---|
| 4957 | #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
|---|
| 4958 | #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
|---|
| 4959 | #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
|---|
| 4960 | #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
|---|
| 4961 | //MMEA1_DRAM_RD_PRI_AGE |
|---|
| 4962 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
|---|
| 4963 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
|---|
| 4964 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
|---|
| 4965 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
|---|
| 4966 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
|---|
| 4967 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
|---|
| 4968 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
|---|
| 4969 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
|---|
| 4970 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
|---|
| 4971 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
|---|
| 4972 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
|---|
| 4973 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
|---|
| 4974 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
|---|
| 4975 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
|---|
| 4976 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
|---|
| 4977 | #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
|---|
| 4978 | //MMEA1_DRAM_WR_PRI_AGE |
|---|
| 4979 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
|---|
| 4980 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
|---|
| 4981 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
|---|
| 4982 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
|---|
| 4983 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
|---|
| 4984 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
|---|
| 4985 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
|---|
| 4986 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
|---|
| 4987 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
|---|
| 4988 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
|---|
| 4989 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
|---|
| 4990 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
|---|
| 4991 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
|---|
| 4992 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
|---|
| 4993 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
|---|
| 4994 | #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
|---|
| 4995 | //MMEA1_DRAM_RD_PRI_QUEUING |
|---|
| 4996 | #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
|---|
| 4997 | #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
|---|
| 4998 | #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
|---|
| 4999 | #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
|---|
| 5000 | #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
|---|
| 5001 | #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
|---|
| 5002 | #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
|---|
| 5003 | #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
|---|
| 5004 | //MMEA1_DRAM_WR_PRI_QUEUING |
|---|
| 5005 | #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
|---|
| 5006 | #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
|---|
| 5007 | #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
|---|
| 5008 | #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
|---|
| 5009 | #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
|---|
| 5010 | #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
|---|
| 5011 | #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
|---|
| 5012 | #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
|---|
| 5013 | //MMEA1_DRAM_RD_PRI_FIXED |
|---|
| 5014 | #define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
|---|
| 5015 | #define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
|---|
| 5016 | #define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
|---|
| 5017 | #define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
|---|
| 5018 | #define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
|---|
| 5019 | #define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
|---|
| 5020 | #define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
|---|
| 5021 | #define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
|---|
| 5022 | //MMEA1_DRAM_WR_PRI_FIXED |
|---|
| 5023 | #define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
|---|
| 5024 | #define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
|---|
| 5025 | #define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
|---|
| 5026 | #define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
|---|
| 5027 | #define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
|---|
| 5028 | #define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
|---|
| 5029 | #define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
|---|
| 5030 | #define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
|---|
| 5031 | //MMEA1_DRAM_RD_PRI_URGENCY |
|---|
| 5032 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
|---|
| 5033 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
|---|
| 5034 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
|---|
| 5035 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
|---|
| 5036 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
|---|
| 5037 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
|---|
| 5038 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
|---|
| 5039 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
|---|
| 5040 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
|---|
| 5041 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
|---|
| 5042 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
|---|
| 5043 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
|---|
| 5044 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
|---|
| 5045 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
|---|
| 5046 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
|---|
| 5047 | #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
|---|
| 5048 | //MMEA1_DRAM_WR_PRI_URGENCY |
|---|
| 5049 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
|---|
| 5050 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
|---|
| 5051 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
|---|
| 5052 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
|---|
| 5053 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
|---|
| 5054 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
|---|
| 5055 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
|---|
| 5056 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
|---|
| 5057 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
|---|
| 5058 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
|---|
| 5059 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
|---|
| 5060 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
|---|
| 5061 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
|---|
| 5062 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
|---|
| 5063 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
|---|
| 5064 | #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
|---|
| 5065 | //MMEA1_DRAM_RD_PRI_QUANT_PRI1 |
|---|
| 5066 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
|---|
| 5067 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
|---|
| 5068 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
|---|
| 5069 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
|---|
| 5070 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
|---|
| 5071 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
|---|
| 5072 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
|---|
| 5073 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
|---|
| 5074 | //MMEA1_DRAM_RD_PRI_QUANT_PRI2 |
|---|
| 5075 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
|---|
| 5076 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
|---|
| 5077 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
|---|
| 5078 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
|---|
| 5079 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
|---|
| 5080 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
|---|
| 5081 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
|---|
| 5082 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
|---|
| 5083 | //MMEA1_DRAM_RD_PRI_QUANT_PRI3 |
|---|
| 5084 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
|---|
| 5085 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
|---|
| 5086 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
|---|
| 5087 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
|---|
| 5088 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
|---|
| 5089 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
|---|
| 5090 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
|---|
| 5091 | #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
|---|
| 5092 | //MMEA1_DRAM_WR_PRI_QUANT_PRI1 |
|---|
| 5093 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
|---|
| 5094 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
|---|
| 5095 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
|---|
| 5096 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
|---|
| 5097 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
|---|
| 5098 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
|---|
| 5099 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
|---|
| 5100 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
|---|
| 5101 | //MMEA1_DRAM_WR_PRI_QUANT_PRI2 |
|---|
| 5102 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
|---|
| 5103 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
|---|
| 5104 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
|---|
| 5105 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
|---|
| 5106 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
|---|
| 5107 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
|---|
| 5108 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
|---|
| 5109 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
|---|
| 5110 | //MMEA1_DRAM_WR_PRI_QUANT_PRI3 |
|---|
| 5111 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
|---|
| 5112 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
|---|
| 5113 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
|---|
| 5114 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
|---|
| 5115 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
|---|
| 5116 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
|---|
| 5117 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
|---|
| 5118 | #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
|---|
| 5119 | //MMEA1_ADDRNORM_BASE_ADDR0 |
|---|
| 5120 | #define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 |
|---|
| 5121 | #define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 |
|---|
| 5122 | #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4 |
|---|
| 5123 | #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8 |
|---|
| 5124 | #define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc |
|---|
| 5125 | #define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L |
|---|
| 5126 | #define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L |
|---|
| 5127 | #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L |
|---|
| 5128 | #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L |
|---|
| 5129 | #define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L |
|---|
| 5130 | //MMEA1_ADDRNORM_LIMIT_ADDR0 |
|---|
| 5131 | #define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 |
|---|
| 5132 | #define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 |
|---|
| 5133 | #define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa |
|---|
| 5134 | #define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc |
|---|
| 5135 | #define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000000FL |
|---|
| 5136 | #define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L |
|---|
| 5137 | #define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L |
|---|
| 5138 | #define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L |
|---|
| 5139 | //MMEA1_ADDRNORM_BASE_ADDR1 |
|---|
| 5140 | #define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 |
|---|
| 5141 | #define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 |
|---|
| 5142 | #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4 |
|---|
| 5143 | #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8 |
|---|
| 5144 | #define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc |
|---|
| 5145 | #define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L |
|---|
| 5146 | #define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L |
|---|
| 5147 | #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L |
|---|
| 5148 | #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L |
|---|
| 5149 | #define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L |
|---|
| 5150 | //MMEA1_ADDRNORM_LIMIT_ADDR1 |
|---|
| 5151 | #define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 |
|---|
| 5152 | #define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 |
|---|
| 5153 | #define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa |
|---|
| 5154 | #define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc |
|---|
| 5155 | #define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000000FL |
|---|
| 5156 | #define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L |
|---|
| 5157 | #define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L |
|---|
| 5158 | #define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L |
|---|
| 5159 | //MMEA1_ADDRNORM_OFFSET_ADDR1 |
|---|
| 5160 | #define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 |
|---|
| 5161 | #define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 |
|---|
| 5162 | #define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L |
|---|
| 5163 | #define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L |
|---|
| 5164 | //MMEA1_ADDRNORM_HOLE_CNTL |
|---|
| 5165 | #define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 |
|---|
| 5166 | #define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 |
|---|
| 5167 | #define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L |
|---|
| 5168 | #define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L |
|---|
| 5169 | //MMEA1_ADDRDEC_BANK_CFG |
|---|
| 5170 | #define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 |
|---|
| 5171 | #define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5 |
|---|
| 5172 | #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa |
|---|
| 5173 | #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd |
|---|
| 5174 | #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10 |
|---|
| 5175 | #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11 |
|---|
| 5176 | #define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL |
|---|
| 5177 | #define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L |
|---|
| 5178 | #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L |
|---|
| 5179 | #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L |
|---|
| 5180 | #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L |
|---|
| 5181 | #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L |
|---|
| 5182 | //MMEA1_ADDRDEC_MISC_CFG |
|---|
| 5183 | #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 |
|---|
| 5184 | #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 |
|---|
| 5185 | #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 |
|---|
| 5186 | #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3 |
|---|
| 5187 | #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4 |
|---|
| 5188 | #define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 |
|---|
| 5189 | #define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 |
|---|
| 5190 | #define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc |
|---|
| 5191 | #define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x10 |
|---|
| 5192 | #define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x14 |
|---|
| 5193 | #define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x16 |
|---|
| 5194 | #define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x18 |
|---|
| 5195 | #define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1b |
|---|
| 5196 | #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L |
|---|
| 5197 | #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L |
|---|
| 5198 | #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L |
|---|
| 5199 | #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L |
|---|
| 5200 | #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L |
|---|
| 5201 | #define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L |
|---|
| 5202 | #define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L |
|---|
| 5203 | #define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0000F000L |
|---|
| 5204 | #define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x000F0000L |
|---|
| 5205 | #define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00300000L |
|---|
| 5206 | #define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x00C00000L |
|---|
| 5207 | #define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x07000000L |
|---|
| 5208 | #define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0x38000000L |
|---|
| 5209 | //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0 |
|---|
| 5210 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 |
|---|
| 5211 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 |
|---|
| 5212 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe |
|---|
| 5213 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L |
|---|
| 5214 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL |
|---|
| 5215 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L |
|---|
| 5216 | //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1 |
|---|
| 5217 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 |
|---|
| 5218 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 |
|---|
| 5219 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe |
|---|
| 5220 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L |
|---|
| 5221 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL |
|---|
| 5222 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L |
|---|
| 5223 | //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2 |
|---|
| 5224 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 |
|---|
| 5225 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 |
|---|
| 5226 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe |
|---|
| 5227 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L |
|---|
| 5228 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL |
|---|
| 5229 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L |
|---|
| 5230 | //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3 |
|---|
| 5231 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 |
|---|
| 5232 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 |
|---|
| 5233 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe |
|---|
| 5234 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L |
|---|
| 5235 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL |
|---|
| 5236 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L |
|---|
| 5237 | //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4 |
|---|
| 5238 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 |
|---|
| 5239 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 |
|---|
| 5240 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe |
|---|
| 5241 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L |
|---|
| 5242 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL |
|---|
| 5243 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L |
|---|
| 5244 | //MMEA1_ADDRDECDRAM_ADDR_HASH_PC |
|---|
| 5245 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 |
|---|
| 5246 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 |
|---|
| 5247 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe |
|---|
| 5248 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L |
|---|
| 5249 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL |
|---|
| 5250 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L |
|---|
| 5251 | //MMEA1_ADDRDECDRAM_ADDR_HASH_PC2 |
|---|
| 5252 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 |
|---|
| 5253 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL |
|---|
| 5254 | //MMEA1_ADDRDECDRAM_ADDR_HASH_CS0 |
|---|
| 5255 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 |
|---|
| 5256 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 |
|---|
| 5257 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L |
|---|
| 5258 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL |
|---|
| 5259 | //MMEA1_ADDRDECDRAM_ADDR_HASH_CS1 |
|---|
| 5260 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 |
|---|
| 5261 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 |
|---|
| 5262 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L |
|---|
| 5263 | #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL |
|---|
| 5264 | //MMEA1_ADDRDECDRAM_HARVEST_ENABLE |
|---|
| 5265 | #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 |
|---|
| 5266 | #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 |
|---|
| 5267 | #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 |
|---|
| 5268 | #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 |
|---|
| 5269 | #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L |
|---|
| 5270 | #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L |
|---|
| 5271 | #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L |
|---|
| 5272 | #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L |
|---|
| 5273 | //MMEA1_ADDRDEC0_BASE_ADDR_CS0 |
|---|
| 5274 | #define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 |
|---|
| 5275 | #define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 |
|---|
| 5276 | #define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L |
|---|
| 5277 | #define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 5278 | //MMEA1_ADDRDEC0_BASE_ADDR_CS1 |
|---|
| 5279 | #define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 |
|---|
| 5280 | #define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 |
|---|
| 5281 | #define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L |
|---|
| 5282 | #define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 5283 | //MMEA1_ADDRDEC0_BASE_ADDR_CS2 |
|---|
| 5284 | #define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 |
|---|
| 5285 | #define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 |
|---|
| 5286 | #define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L |
|---|
| 5287 | #define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 5288 | //MMEA1_ADDRDEC0_BASE_ADDR_CS3 |
|---|
| 5289 | #define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 |
|---|
| 5290 | #define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 |
|---|
| 5291 | #define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L |
|---|
| 5292 | #define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 5293 | //MMEA1_ADDRDEC0_BASE_ADDR_SECCS0 |
|---|
| 5294 | #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 |
|---|
| 5295 | #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 |
|---|
| 5296 | #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L |
|---|
| 5297 | #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 5298 | //MMEA1_ADDRDEC0_BASE_ADDR_SECCS1 |
|---|
| 5299 | #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 |
|---|
| 5300 | #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 |
|---|
| 5301 | #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L |
|---|
| 5302 | #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 5303 | //MMEA1_ADDRDEC0_BASE_ADDR_SECCS2 |
|---|
| 5304 | #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 |
|---|
| 5305 | #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 |
|---|
| 5306 | #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L |
|---|
| 5307 | #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 5308 | //MMEA1_ADDRDEC0_BASE_ADDR_SECCS3 |
|---|
| 5309 | #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 |
|---|
| 5310 | #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 |
|---|
| 5311 | #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L |
|---|
| 5312 | #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 5313 | //MMEA1_ADDRDEC0_ADDR_MASK_CS01 |
|---|
| 5314 | #define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 |
|---|
| 5315 | #define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL |
|---|
| 5316 | //MMEA1_ADDRDEC0_ADDR_MASK_CS23 |
|---|
| 5317 | #define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 |
|---|
| 5318 | #define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL |
|---|
| 5319 | //MMEA1_ADDRDEC0_ADDR_MASK_SECCS01 |
|---|
| 5320 | #define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 |
|---|
| 5321 | #define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL |
|---|
| 5322 | //MMEA1_ADDRDEC0_ADDR_MASK_SECCS23 |
|---|
| 5323 | #define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 |
|---|
| 5324 | #define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL |
|---|
| 5325 | //MMEA1_ADDRDEC0_ADDR_CFG_CS01 |
|---|
| 5326 | #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 |
|---|
| 5327 | #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 |
|---|
| 5328 | #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 |
|---|
| 5329 | #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc |
|---|
| 5330 | #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 |
|---|
| 5331 | #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 |
|---|
| 5332 | #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL |
|---|
| 5333 | #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L |
|---|
| 5334 | #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L |
|---|
| 5335 | #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L |
|---|
| 5336 | #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L |
|---|
| 5337 | #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L |
|---|
| 5338 | //MMEA1_ADDRDEC0_ADDR_CFG_CS23 |
|---|
| 5339 | #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 |
|---|
| 5340 | #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 |
|---|
| 5341 | #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 |
|---|
| 5342 | #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc |
|---|
| 5343 | #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 |
|---|
| 5344 | #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 |
|---|
| 5345 | #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL |
|---|
| 5346 | #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L |
|---|
| 5347 | #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L |
|---|
| 5348 | #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L |
|---|
| 5349 | #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L |
|---|
| 5350 | #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L |
|---|
| 5351 | //MMEA1_ADDRDEC0_ADDR_SEL_CS01 |
|---|
| 5352 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 |
|---|
| 5353 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 |
|---|
| 5354 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 |
|---|
| 5355 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc |
|---|
| 5356 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 |
|---|
| 5357 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 |
|---|
| 5358 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c |
|---|
| 5359 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL |
|---|
| 5360 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L |
|---|
| 5361 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L |
|---|
| 5362 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L |
|---|
| 5363 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L |
|---|
| 5364 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L |
|---|
| 5365 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L |
|---|
| 5366 | //MMEA1_ADDRDEC0_ADDR_SEL_CS23 |
|---|
| 5367 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 |
|---|
| 5368 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 |
|---|
| 5369 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 |
|---|
| 5370 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc |
|---|
| 5371 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 |
|---|
| 5372 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 |
|---|
| 5373 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c |
|---|
| 5374 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL |
|---|
| 5375 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L |
|---|
| 5376 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L |
|---|
| 5377 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L |
|---|
| 5378 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L |
|---|
| 5379 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L |
|---|
| 5380 | #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L |
|---|
| 5381 | //MMEA1_ADDRDEC0_COL_SEL_LO_CS01 |
|---|
| 5382 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 |
|---|
| 5383 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 |
|---|
| 5384 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 |
|---|
| 5385 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc |
|---|
| 5386 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 |
|---|
| 5387 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 |
|---|
| 5388 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 |
|---|
| 5389 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c |
|---|
| 5390 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL |
|---|
| 5391 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L |
|---|
| 5392 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L |
|---|
| 5393 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L |
|---|
| 5394 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L |
|---|
| 5395 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L |
|---|
| 5396 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L |
|---|
| 5397 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L |
|---|
| 5398 | //MMEA1_ADDRDEC0_COL_SEL_LO_CS23 |
|---|
| 5399 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 |
|---|
| 5400 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 |
|---|
| 5401 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 |
|---|
| 5402 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc |
|---|
| 5403 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 |
|---|
| 5404 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 |
|---|
| 5405 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 |
|---|
| 5406 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c |
|---|
| 5407 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL |
|---|
| 5408 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L |
|---|
| 5409 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L |
|---|
| 5410 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L |
|---|
| 5411 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L |
|---|
| 5412 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L |
|---|
| 5413 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L |
|---|
| 5414 | #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L |
|---|
| 5415 | //MMEA1_ADDRDEC0_COL_SEL_HI_CS01 |
|---|
| 5416 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 |
|---|
| 5417 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 |
|---|
| 5418 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 |
|---|
| 5419 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc |
|---|
| 5420 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 |
|---|
| 5421 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 |
|---|
| 5422 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 |
|---|
| 5423 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c |
|---|
| 5424 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL |
|---|
| 5425 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L |
|---|
| 5426 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L |
|---|
| 5427 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L |
|---|
| 5428 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L |
|---|
| 5429 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L |
|---|
| 5430 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L |
|---|
| 5431 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L |
|---|
| 5432 | //MMEA1_ADDRDEC0_COL_SEL_HI_CS23 |
|---|
| 5433 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 |
|---|
| 5434 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 |
|---|
| 5435 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 |
|---|
| 5436 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc |
|---|
| 5437 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 |
|---|
| 5438 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 |
|---|
| 5439 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 |
|---|
| 5440 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c |
|---|
| 5441 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL |
|---|
| 5442 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L |
|---|
| 5443 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L |
|---|
| 5444 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L |
|---|
| 5445 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L |
|---|
| 5446 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L |
|---|
| 5447 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L |
|---|
| 5448 | #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L |
|---|
| 5449 | //MMEA1_ADDRDEC0_RM_SEL_CS01 |
|---|
| 5450 | #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 |
|---|
| 5451 | #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 |
|---|
| 5452 | #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 |
|---|
| 5453 | #define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc |
|---|
| 5454 | #define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
|---|
| 5455 | #define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
|---|
| 5456 | #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL |
|---|
| 5457 | #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L |
|---|
| 5458 | #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L |
|---|
| 5459 | #define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L |
|---|
| 5460 | #define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
|---|
| 5461 | #define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
|---|
| 5462 | //MMEA1_ADDRDEC0_RM_SEL_CS23 |
|---|
| 5463 | #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 |
|---|
| 5464 | #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 |
|---|
| 5465 | #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 |
|---|
| 5466 | #define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc |
|---|
| 5467 | #define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
|---|
| 5468 | #define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
|---|
| 5469 | #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL |
|---|
| 5470 | #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L |
|---|
| 5471 | #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L |
|---|
| 5472 | #define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L |
|---|
| 5473 | #define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
|---|
| 5474 | #define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
|---|
| 5475 | //MMEA1_ADDRDEC0_RM_SEL_SECCS01 |
|---|
| 5476 | #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 |
|---|
| 5477 | #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 |
|---|
| 5478 | #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 |
|---|
| 5479 | #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc |
|---|
| 5480 | #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
|---|
| 5481 | #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
|---|
| 5482 | #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL |
|---|
| 5483 | #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L |
|---|
| 5484 | #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L |
|---|
| 5485 | #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L |
|---|
| 5486 | #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
|---|
| 5487 | #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
|---|
| 5488 | //MMEA1_ADDRDEC0_RM_SEL_SECCS23 |
|---|
| 5489 | #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 |
|---|
| 5490 | #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 |
|---|
| 5491 | #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 |
|---|
| 5492 | #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc |
|---|
| 5493 | #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
|---|
| 5494 | #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
|---|
| 5495 | #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL |
|---|
| 5496 | #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L |
|---|
| 5497 | #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L |
|---|
| 5498 | #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L |
|---|
| 5499 | #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
|---|
| 5500 | #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
|---|
| 5501 | //MMEA1_ADDRDEC1_BASE_ADDR_CS0 |
|---|
| 5502 | #define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 |
|---|
| 5503 | #define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 |
|---|
| 5504 | #define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L |
|---|
| 5505 | #define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 5506 | //MMEA1_ADDRDEC1_BASE_ADDR_CS1 |
|---|
| 5507 | #define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 |
|---|
| 5508 | #define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 |
|---|
| 5509 | #define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L |
|---|
| 5510 | #define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 5511 | //MMEA1_ADDRDEC1_BASE_ADDR_CS2 |
|---|
| 5512 | #define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 |
|---|
| 5513 | #define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 |
|---|
| 5514 | #define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L |
|---|
| 5515 | #define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 5516 | //MMEA1_ADDRDEC1_BASE_ADDR_CS3 |
|---|
| 5517 | #define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 |
|---|
| 5518 | #define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 |
|---|
| 5519 | #define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L |
|---|
| 5520 | #define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 5521 | //MMEA1_ADDRDEC1_BASE_ADDR_SECCS0 |
|---|
| 5522 | #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 |
|---|
| 5523 | #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 |
|---|
| 5524 | #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L |
|---|
| 5525 | #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 5526 | //MMEA1_ADDRDEC1_BASE_ADDR_SECCS1 |
|---|
| 5527 | #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 |
|---|
| 5528 | #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 |
|---|
| 5529 | #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L |
|---|
| 5530 | #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 5531 | //MMEA1_ADDRDEC1_BASE_ADDR_SECCS2 |
|---|
| 5532 | #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 |
|---|
| 5533 | #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 |
|---|
| 5534 | #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L |
|---|
| 5535 | #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 5536 | //MMEA1_ADDRDEC1_BASE_ADDR_SECCS3 |
|---|
| 5537 | #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 |
|---|
| 5538 | #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 |
|---|
| 5539 | #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L |
|---|
| 5540 | #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL |
|---|
| 5541 | //MMEA1_ADDRDEC1_ADDR_MASK_CS01 |
|---|
| 5542 | #define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 |
|---|
| 5543 | #define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL |
|---|
| 5544 | //MMEA1_ADDRDEC1_ADDR_MASK_CS23 |
|---|
| 5545 | #define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 |
|---|
| 5546 | #define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL |
|---|
| 5547 | //MMEA1_ADDRDEC1_ADDR_MASK_SECCS01 |
|---|
| 5548 | #define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 |
|---|
| 5549 | #define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL |
|---|
| 5550 | //MMEA1_ADDRDEC1_ADDR_MASK_SECCS23 |
|---|
| 5551 | #define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 |
|---|
| 5552 | #define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL |
|---|
| 5553 | //MMEA1_ADDRDEC1_ADDR_CFG_CS01 |
|---|
| 5554 | #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 |
|---|
| 5555 | #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 |
|---|
| 5556 | #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 |
|---|
| 5557 | #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc |
|---|
| 5558 | #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 |
|---|
| 5559 | #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 |
|---|
| 5560 | #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL |
|---|
| 5561 | #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L |
|---|
| 5562 | #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L |
|---|
| 5563 | #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L |
|---|
| 5564 | #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L |
|---|
| 5565 | #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L |
|---|
| 5566 | //MMEA1_ADDRDEC1_ADDR_CFG_CS23 |
|---|
| 5567 | #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 |
|---|
| 5568 | #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 |
|---|
| 5569 | #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 |
|---|
| 5570 | #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc |
|---|
| 5571 | #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 |
|---|
| 5572 | #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 |
|---|
| 5573 | #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL |
|---|
| 5574 | #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L |
|---|
| 5575 | #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L |
|---|
| 5576 | #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L |
|---|
| 5577 | #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L |
|---|
| 5578 | #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L |
|---|
| 5579 | //MMEA1_ADDRDEC1_ADDR_SEL_CS01 |
|---|
| 5580 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 |
|---|
| 5581 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 |
|---|
| 5582 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 |
|---|
| 5583 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc |
|---|
| 5584 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 |
|---|
| 5585 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 |
|---|
| 5586 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c |
|---|
| 5587 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL |
|---|
| 5588 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L |
|---|
| 5589 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L |
|---|
| 5590 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L |
|---|
| 5591 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L |
|---|
| 5592 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L |
|---|
| 5593 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L |
|---|
| 5594 | //MMEA1_ADDRDEC1_ADDR_SEL_CS23 |
|---|
| 5595 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 |
|---|
| 5596 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 |
|---|
| 5597 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 |
|---|
| 5598 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc |
|---|
| 5599 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 |
|---|
| 5600 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 |
|---|
| 5601 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c |
|---|
| 5602 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL |
|---|
| 5603 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L |
|---|
| 5604 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L |
|---|
| 5605 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L |
|---|
| 5606 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L |
|---|
| 5607 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L |
|---|
| 5608 | #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L |
|---|
| 5609 | //MMEA1_ADDRDEC1_COL_SEL_LO_CS01 |
|---|
| 5610 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 |
|---|
| 5611 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 |
|---|
| 5612 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 |
|---|
| 5613 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc |
|---|
| 5614 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 |
|---|
| 5615 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 |
|---|
| 5616 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 |
|---|
| 5617 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c |
|---|
| 5618 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL |
|---|
| 5619 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L |
|---|
| 5620 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L |
|---|
| 5621 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L |
|---|
| 5622 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L |
|---|
| 5623 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L |
|---|
| 5624 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L |
|---|
| 5625 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L |
|---|
| 5626 | //MMEA1_ADDRDEC1_COL_SEL_LO_CS23 |
|---|
| 5627 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 |
|---|
| 5628 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 |
|---|
| 5629 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 |
|---|
| 5630 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc |
|---|
| 5631 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 |
|---|
| 5632 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 |
|---|
| 5633 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 |
|---|
| 5634 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c |
|---|
| 5635 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL |
|---|
| 5636 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L |
|---|
| 5637 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L |
|---|
| 5638 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L |
|---|
| 5639 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L |
|---|
| 5640 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L |
|---|
| 5641 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L |
|---|
| 5642 | #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L |
|---|
| 5643 | //MMEA1_ADDRDEC1_COL_SEL_HI_CS01 |
|---|
| 5644 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 |
|---|
| 5645 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 |
|---|
| 5646 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 |
|---|
| 5647 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc |
|---|
| 5648 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 |
|---|
| 5649 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 |
|---|
| 5650 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 |
|---|
| 5651 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c |
|---|
| 5652 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL |
|---|
| 5653 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L |
|---|
| 5654 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L |
|---|
| 5655 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L |
|---|
| 5656 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L |
|---|
| 5657 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L |
|---|
| 5658 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L |
|---|
| 5659 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L |
|---|
| 5660 | //MMEA1_ADDRDEC1_COL_SEL_HI_CS23 |
|---|
| 5661 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 |
|---|
| 5662 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 |
|---|
| 5663 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 |
|---|
| 5664 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc |
|---|
| 5665 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 |
|---|
| 5666 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 |
|---|
| 5667 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 |
|---|
| 5668 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c |
|---|
| 5669 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL |
|---|
| 5670 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L |
|---|
| 5671 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L |
|---|
| 5672 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L |
|---|
| 5673 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L |
|---|
| 5674 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L |
|---|
| 5675 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L |
|---|
| 5676 | #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L |
|---|
| 5677 | //MMEA1_ADDRDEC1_RM_SEL_CS01 |
|---|
| 5678 | #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 |
|---|
| 5679 | #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 |
|---|
| 5680 | #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 |
|---|
| 5681 | #define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc |
|---|
| 5682 | #define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
|---|
| 5683 | #define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
|---|
| 5684 | #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL |
|---|
| 5685 | #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L |
|---|
| 5686 | #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L |
|---|
| 5687 | #define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L |
|---|
| 5688 | #define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
|---|
| 5689 | #define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
|---|
| 5690 | //MMEA1_ADDRDEC1_RM_SEL_CS23 |
|---|
| 5691 | #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 |
|---|
| 5692 | #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 |
|---|
| 5693 | #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 |
|---|
| 5694 | #define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc |
|---|
| 5695 | #define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
|---|
| 5696 | #define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
|---|
| 5697 | #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL |
|---|
| 5698 | #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L |
|---|
| 5699 | #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L |
|---|
| 5700 | #define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L |
|---|
| 5701 | #define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
|---|
| 5702 | #define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
|---|
| 5703 | //MMEA1_ADDRDEC1_RM_SEL_SECCS01 |
|---|
| 5704 | #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 |
|---|
| 5705 | #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 |
|---|
| 5706 | #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 |
|---|
| 5707 | #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc |
|---|
| 5708 | #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
|---|
| 5709 | #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
|---|
| 5710 | #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL |
|---|
| 5711 | #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L |
|---|
| 5712 | #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L |
|---|
| 5713 | #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L |
|---|
| 5714 | #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
|---|
| 5715 | #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
|---|
| 5716 | //MMEA1_ADDRDEC1_RM_SEL_SECCS23 |
|---|
| 5717 | #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 |
|---|
| 5718 | #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 |
|---|
| 5719 | #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 |
|---|
| 5720 | #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc |
|---|
| 5721 | #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
|---|
| 5722 | #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
|---|
| 5723 | #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL |
|---|
| 5724 | #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L |
|---|
| 5725 | #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L |
|---|
| 5726 | #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L |
|---|
| 5727 | #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
|---|
| 5728 | #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
|---|
| 5729 | //MMEA1_IO_RD_CLI2GRP_MAP0 |
|---|
| 5730 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
|---|
| 5731 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
|---|
| 5732 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
|---|
| 5733 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
|---|
| 5734 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
|---|
| 5735 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
|---|
| 5736 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
|---|
| 5737 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
|---|
| 5738 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
|---|
| 5739 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
|---|
| 5740 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
|---|
| 5741 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
|---|
| 5742 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
|---|
| 5743 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
|---|
| 5744 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
|---|
| 5745 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
|---|
| 5746 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
|---|
| 5747 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
|---|
| 5748 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
|---|
| 5749 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
|---|
| 5750 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
|---|
| 5751 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
|---|
| 5752 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
|---|
| 5753 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
|---|
| 5754 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
|---|
| 5755 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
|---|
| 5756 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
|---|
| 5757 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
|---|
| 5758 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
|---|
| 5759 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
|---|
| 5760 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
|---|
| 5761 | #define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
|---|
| 5762 | //MMEA1_IO_RD_CLI2GRP_MAP1 |
|---|
| 5763 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
|---|
| 5764 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
|---|
| 5765 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
|---|
| 5766 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
|---|
| 5767 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
|---|
| 5768 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
|---|
| 5769 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
|---|
| 5770 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
|---|
| 5771 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
|---|
| 5772 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
|---|
| 5773 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
|---|
| 5774 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
|---|
| 5775 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
|---|
| 5776 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
|---|
| 5777 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
|---|
| 5778 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
|---|
| 5779 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
|---|
| 5780 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
|---|
| 5781 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
|---|
| 5782 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
|---|
| 5783 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
|---|
| 5784 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
|---|
| 5785 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
|---|
| 5786 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
|---|
| 5787 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
|---|
| 5788 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
|---|
| 5789 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
|---|
| 5790 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
|---|
| 5791 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
|---|
| 5792 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
|---|
| 5793 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
|---|
| 5794 | #define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
|---|
| 5795 | //MMEA1_IO_WR_CLI2GRP_MAP0 |
|---|
| 5796 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
|---|
| 5797 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
|---|
| 5798 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
|---|
| 5799 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
|---|
| 5800 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
|---|
| 5801 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
|---|
| 5802 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
|---|
| 5803 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
|---|
| 5804 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
|---|
| 5805 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
|---|
| 5806 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
|---|
| 5807 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
|---|
| 5808 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
|---|
| 5809 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
|---|
| 5810 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
|---|
| 5811 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
|---|
| 5812 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
|---|
| 5813 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
|---|
| 5814 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
|---|
| 5815 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
|---|
| 5816 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
|---|
| 5817 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
|---|
| 5818 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
|---|
| 5819 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
|---|
| 5820 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
|---|
| 5821 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
|---|
| 5822 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
|---|
| 5823 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
|---|
| 5824 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
|---|
| 5825 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
|---|
| 5826 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
|---|
| 5827 | #define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
|---|
| 5828 | //MMEA1_IO_WR_CLI2GRP_MAP1 |
|---|
| 5829 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
|---|
| 5830 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
|---|
| 5831 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
|---|
| 5832 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
|---|
| 5833 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
|---|
| 5834 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
|---|
| 5835 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
|---|
| 5836 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
|---|
| 5837 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
|---|
| 5838 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
|---|
| 5839 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
|---|
| 5840 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
|---|
| 5841 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
|---|
| 5842 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
|---|
| 5843 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
|---|
| 5844 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
|---|
| 5845 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
|---|
| 5846 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
|---|
| 5847 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
|---|
| 5848 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
|---|
| 5849 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
|---|
| 5850 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
|---|
| 5851 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
|---|
| 5852 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
|---|
| 5853 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
|---|
| 5854 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
|---|
| 5855 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
|---|
| 5856 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
|---|
| 5857 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
|---|
| 5858 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
|---|
| 5859 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
|---|
| 5860 | #define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
|---|
| 5861 | //MMEA1_IO_RD_COMBINE_FLUSH |
|---|
| 5862 | #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
|---|
| 5863 | #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
|---|
| 5864 | #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
|---|
| 5865 | #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
|---|
| 5866 | #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
|---|
| 5867 | #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
|---|
| 5868 | #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
|---|
| 5869 | #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
|---|
| 5870 | //MMEA1_IO_WR_COMBINE_FLUSH |
|---|
| 5871 | #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
|---|
| 5872 | #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
|---|
| 5873 | #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
|---|
| 5874 | #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
|---|
| 5875 | #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
|---|
| 5876 | #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
|---|
| 5877 | #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
|---|
| 5878 | #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
|---|
| 5879 | //MMEA1_IO_GROUP_BURST |
|---|
| 5880 | #define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 |
|---|
| 5881 | #define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 |
|---|
| 5882 | #define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 |
|---|
| 5883 | #define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 |
|---|
| 5884 | #define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
|---|
| 5885 | #define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
|---|
| 5886 | #define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
|---|
| 5887 | #define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
|---|
| 5888 | //MMEA1_IO_RD_PRI_AGE |
|---|
| 5889 | #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
|---|
| 5890 | #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
|---|
| 5891 | #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
|---|
| 5892 | #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
|---|
| 5893 | #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
|---|
| 5894 | #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
|---|
| 5895 | #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
|---|
| 5896 | #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
|---|
| 5897 | #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
|---|
| 5898 | #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
|---|
| 5899 | #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
|---|
| 5900 | #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
|---|
| 5901 | #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
|---|
| 5902 | #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
|---|
| 5903 | #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
|---|
| 5904 | #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
|---|
| 5905 | //MMEA1_IO_WR_PRI_AGE |
|---|
| 5906 | #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
|---|
| 5907 | #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
|---|
| 5908 | #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
|---|
| 5909 | #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
|---|
| 5910 | #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
|---|
| 5911 | #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
|---|
| 5912 | #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
|---|
| 5913 | #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
|---|
| 5914 | #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
|---|
| 5915 | #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
|---|
| 5916 | #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
|---|
| 5917 | #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
|---|
| 5918 | #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
|---|
| 5919 | #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
|---|
| 5920 | #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
|---|
| 5921 | #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
|---|
| 5922 | //MMEA1_IO_RD_PRI_QUEUING |
|---|
| 5923 | #define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
|---|
| 5924 | #define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
|---|
| 5925 | #define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
|---|
| 5926 | #define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
|---|
| 5927 | #define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
|---|
| 5928 | #define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
|---|
| 5929 | #define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
|---|
| 5930 | #define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
|---|
| 5931 | //MMEA1_IO_WR_PRI_QUEUING |
|---|
| 5932 | #define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
|---|
| 5933 | #define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
|---|
| 5934 | #define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
|---|
| 5935 | #define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
|---|
| 5936 | #define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
|---|
| 5937 | #define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
|---|
| 5938 | #define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
|---|
| 5939 | #define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
|---|
| 5940 | //MMEA1_IO_RD_PRI_FIXED |
|---|
| 5941 | #define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
|---|
| 5942 | #define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
|---|
| 5943 | #define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
|---|
| 5944 | #define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
|---|
| 5945 | #define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
|---|
| 5946 | #define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
|---|
| 5947 | #define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
|---|
| 5948 | #define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
|---|
| 5949 | //MMEA1_IO_WR_PRI_FIXED |
|---|
| 5950 | #define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
|---|
| 5951 | #define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
|---|
| 5952 | #define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
|---|
| 5953 | #define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
|---|
| 5954 | #define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
|---|
| 5955 | #define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
|---|
| 5956 | #define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
|---|
| 5957 | #define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
|---|
| 5958 | //MMEA1_IO_RD_PRI_URGENCY |
|---|
| 5959 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
|---|
| 5960 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
|---|
| 5961 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
|---|
| 5962 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
|---|
| 5963 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
|---|
| 5964 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
|---|
| 5965 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
|---|
| 5966 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
|---|
| 5967 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
|---|
| 5968 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
|---|
| 5969 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
|---|
| 5970 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
|---|
| 5971 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
|---|
| 5972 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
|---|
| 5973 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
|---|
| 5974 | #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
|---|
| 5975 | //MMEA1_IO_WR_PRI_URGENCY |
|---|
| 5976 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
|---|
| 5977 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
|---|
| 5978 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
|---|
| 5979 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
|---|
| 5980 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
|---|
| 5981 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
|---|
| 5982 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
|---|
| 5983 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
|---|
| 5984 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
|---|
| 5985 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
|---|
| 5986 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
|---|
| 5987 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
|---|
| 5988 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
|---|
| 5989 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
|---|
| 5990 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
|---|
| 5991 | #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
|---|
| 5992 | //MMEA1_IO_RD_PRI_URGENCY_MASK |
|---|
| 5993 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 |
|---|
| 5994 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 |
|---|
| 5995 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 |
|---|
| 5996 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 |
|---|
| 5997 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 |
|---|
| 5998 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 |
|---|
| 5999 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 |
|---|
| 6000 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 |
|---|
| 6001 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 |
|---|
| 6002 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 |
|---|
| 6003 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa |
|---|
| 6004 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb |
|---|
| 6005 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc |
|---|
| 6006 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd |
|---|
| 6007 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe |
|---|
| 6008 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf |
|---|
| 6009 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 |
|---|
| 6010 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 |
|---|
| 6011 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 |
|---|
| 6012 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 |
|---|
| 6013 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 |
|---|
| 6014 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 |
|---|
| 6015 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 |
|---|
| 6016 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 |
|---|
| 6017 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 |
|---|
| 6018 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 |
|---|
| 6019 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a |
|---|
| 6020 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b |
|---|
| 6021 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c |
|---|
| 6022 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d |
|---|
| 6023 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e |
|---|
| 6024 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f |
|---|
| 6025 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L |
|---|
| 6026 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L |
|---|
| 6027 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L |
|---|
| 6028 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L |
|---|
| 6029 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L |
|---|
| 6030 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L |
|---|
| 6031 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L |
|---|
| 6032 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L |
|---|
| 6033 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L |
|---|
| 6034 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L |
|---|
| 6035 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L |
|---|
| 6036 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L |
|---|
| 6037 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L |
|---|
| 6038 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L |
|---|
| 6039 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L |
|---|
| 6040 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L |
|---|
| 6041 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L |
|---|
| 6042 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L |
|---|
| 6043 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L |
|---|
| 6044 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L |
|---|
| 6045 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L |
|---|
| 6046 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L |
|---|
| 6047 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L |
|---|
| 6048 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L |
|---|
| 6049 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L |
|---|
| 6050 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L |
|---|
| 6051 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L |
|---|
| 6052 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L |
|---|
| 6053 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L |
|---|
| 6054 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L |
|---|
| 6055 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L |
|---|
| 6056 | #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L |
|---|
| 6057 | //MMEA1_IO_WR_PRI_URGENCY_MASK |
|---|
| 6058 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 |
|---|
| 6059 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 |
|---|
| 6060 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 |
|---|
| 6061 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 |
|---|
| 6062 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 |
|---|
| 6063 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 |
|---|
| 6064 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 |
|---|
| 6065 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 |
|---|
| 6066 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 |
|---|
| 6067 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 |
|---|
| 6068 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa |
|---|
| 6069 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb |
|---|
| 6070 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc |
|---|
| 6071 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd |
|---|
| 6072 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe |
|---|
| 6073 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf |
|---|
| 6074 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 |
|---|
| 6075 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 |
|---|
| 6076 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 |
|---|
| 6077 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 |
|---|
| 6078 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 |
|---|
| 6079 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 |
|---|
| 6080 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 |
|---|
| 6081 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 |
|---|
| 6082 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 |
|---|
| 6083 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 |
|---|
| 6084 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a |
|---|
| 6085 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b |
|---|
| 6086 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c |
|---|
| 6087 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d |
|---|
| 6088 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e |
|---|
| 6089 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f |
|---|
| 6090 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L |
|---|
| 6091 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L |
|---|
| 6092 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L |
|---|
| 6093 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L |
|---|
| 6094 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L |
|---|
| 6095 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L |
|---|
| 6096 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L |
|---|
| 6097 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L |
|---|
| 6098 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L |
|---|
| 6099 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L |
|---|
| 6100 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L |
|---|
| 6101 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L |
|---|
| 6102 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L |
|---|
| 6103 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L |
|---|
| 6104 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L |
|---|
| 6105 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L |
|---|
| 6106 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L |
|---|
| 6107 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L |
|---|
| 6108 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L |
|---|
| 6109 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L |
|---|
| 6110 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L |
|---|
| 6111 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L |
|---|
| 6112 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L |
|---|
| 6113 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L |
|---|
| 6114 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L |
|---|
| 6115 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L |
|---|
| 6116 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L |
|---|
| 6117 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L |
|---|
| 6118 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L |
|---|
| 6119 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L |
|---|
| 6120 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L |
|---|
| 6121 | #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L |
|---|
| 6122 | //MMEA1_IO_RD_PRI_QUANT_PRI1 |
|---|
| 6123 | #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
|---|
| 6124 | #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
|---|
| 6125 | #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
|---|
| 6126 | #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
|---|
| 6127 | #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
|---|
| 6128 | #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
|---|
| 6129 | #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
|---|
| 6130 | #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
|---|
| 6131 | //MMEA1_IO_RD_PRI_QUANT_PRI2 |
|---|
| 6132 | #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
|---|
| 6133 | #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
|---|
| 6134 | #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
|---|
| 6135 | #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
|---|
| 6136 | #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
|---|
| 6137 | #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
|---|
| 6138 | #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
|---|
| 6139 | #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
|---|
| 6140 | //MMEA1_IO_RD_PRI_QUANT_PRI3 |
|---|
| 6141 | #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
|---|
| 6142 | #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
|---|
| 6143 | #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
|---|
| 6144 | #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
|---|
| 6145 | #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
|---|
| 6146 | #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
|---|
| 6147 | #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
|---|
| 6148 | #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
|---|
| 6149 | //MMEA1_IO_WR_PRI_QUANT_PRI1 |
|---|
| 6150 | #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
|---|
| 6151 | #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
|---|
| 6152 | #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
|---|
| 6153 | #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
|---|
| 6154 | #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
|---|
| 6155 | #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
|---|
| 6156 | #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
|---|
| 6157 | #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
|---|
| 6158 | //MMEA1_IO_WR_PRI_QUANT_PRI2 |
|---|
| 6159 | #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
|---|
| 6160 | #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
|---|
| 6161 | #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
|---|
| 6162 | #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
|---|
| 6163 | #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
|---|
| 6164 | #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
|---|
| 6165 | #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
|---|
| 6166 | #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
|---|
| 6167 | //MMEA1_IO_WR_PRI_QUANT_PRI3 |
|---|
| 6168 | #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
|---|
| 6169 | #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
|---|
| 6170 | #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
|---|
| 6171 | #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
|---|
| 6172 | #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
|---|
| 6173 | #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
|---|
| 6174 | #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
|---|
| 6175 | #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
|---|
| 6176 | //MMEA1_SDP_ARB_DRAM |
|---|
| 6177 | #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 |
|---|
| 6178 | #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 |
|---|
| 6179 | #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 |
|---|
| 6180 | #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 |
|---|
| 6181 | #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 |
|---|
| 6182 | #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 |
|---|
| 6183 | #define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 |
|---|
| 6184 | #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL |
|---|
| 6185 | #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L |
|---|
| 6186 | #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L |
|---|
| 6187 | #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L |
|---|
| 6188 | #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L |
|---|
| 6189 | #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L |
|---|
| 6190 | #define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L |
|---|
| 6191 | //MMEA1_SDP_ARB_FINAL |
|---|
| 6192 | #define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 |
|---|
| 6193 | #define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 |
|---|
| 6194 | #define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa |
|---|
| 6195 | #define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf |
|---|
| 6196 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 |
|---|
| 6197 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 |
|---|
| 6198 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 |
|---|
| 6199 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 |
|---|
| 6200 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 |
|---|
| 6201 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 |
|---|
| 6202 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 |
|---|
| 6203 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 |
|---|
| 6204 | #define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 |
|---|
| 6205 | #define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a |
|---|
| 6206 | #define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL |
|---|
| 6207 | #define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L |
|---|
| 6208 | #define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L |
|---|
| 6209 | #define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L |
|---|
| 6210 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L |
|---|
| 6211 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L |
|---|
| 6212 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L |
|---|
| 6213 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L |
|---|
| 6214 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L |
|---|
| 6215 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L |
|---|
| 6216 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L |
|---|
| 6217 | #define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L |
|---|
| 6218 | #define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L |
|---|
| 6219 | #define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L |
|---|
| 6220 | //MMEA1_SDP_DRAM_PRIORITY |
|---|
| 6221 | #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 |
|---|
| 6222 | #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 |
|---|
| 6223 | #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 |
|---|
| 6224 | #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc |
|---|
| 6225 | #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 |
|---|
| 6226 | #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 |
|---|
| 6227 | #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 |
|---|
| 6228 | #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c |
|---|
| 6229 | #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL |
|---|
| 6230 | #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L |
|---|
| 6231 | #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L |
|---|
| 6232 | #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L |
|---|
| 6233 | #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L |
|---|
| 6234 | #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L |
|---|
| 6235 | #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L |
|---|
| 6236 | #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L |
|---|
| 6237 | //MMEA1_SDP_IO_PRIORITY |
|---|
| 6238 | #define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 |
|---|
| 6239 | #define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 |
|---|
| 6240 | #define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 |
|---|
| 6241 | #define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc |
|---|
| 6242 | #define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 |
|---|
| 6243 | #define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 |
|---|
| 6244 | #define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 |
|---|
| 6245 | #define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c |
|---|
| 6246 | #define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL |
|---|
| 6247 | #define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L |
|---|
| 6248 | #define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L |
|---|
| 6249 | #define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L |
|---|
| 6250 | #define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L |
|---|
| 6251 | #define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L |
|---|
| 6252 | #define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L |
|---|
| 6253 | #define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L |
|---|
| 6254 | //MMEA1_SDP_CREDITS |
|---|
| 6255 | #define MMEA1_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 |
|---|
| 6256 | #define MMEA1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 |
|---|
| 6257 | #define MMEA1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 |
|---|
| 6258 | #define MMEA1_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL |
|---|
| 6259 | #define MMEA1_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L |
|---|
| 6260 | #define MMEA1_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L |
|---|
| 6261 | //MMEA1_SDP_TAG_RESERVE0 |
|---|
| 6262 | #define MMEA1_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 |
|---|
| 6263 | #define MMEA1_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 |
|---|
| 6264 | #define MMEA1_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 |
|---|
| 6265 | #define MMEA1_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 |
|---|
| 6266 | #define MMEA1_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL |
|---|
| 6267 | #define MMEA1_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L |
|---|
| 6268 | #define MMEA1_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L |
|---|
| 6269 | #define MMEA1_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L |
|---|
| 6270 | //MMEA1_SDP_TAG_RESERVE1 |
|---|
| 6271 | #define MMEA1_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 |
|---|
| 6272 | #define MMEA1_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 |
|---|
| 6273 | #define MMEA1_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 |
|---|
| 6274 | #define MMEA1_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 |
|---|
| 6275 | #define MMEA1_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL |
|---|
| 6276 | #define MMEA1_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L |
|---|
| 6277 | #define MMEA1_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L |
|---|
| 6278 | #define MMEA1_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L |
|---|
| 6279 | //MMEA1_SDP_VCC_RESERVE0 |
|---|
| 6280 | #define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 |
|---|
| 6281 | #define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 |
|---|
| 6282 | #define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc |
|---|
| 6283 | #define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 |
|---|
| 6284 | #define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 |
|---|
| 6285 | #define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL |
|---|
| 6286 | #define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L |
|---|
| 6287 | #define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L |
|---|
| 6288 | #define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L |
|---|
| 6289 | #define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L |
|---|
| 6290 | //MMEA1_SDP_VCC_RESERVE1 |
|---|
| 6291 | #define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 |
|---|
| 6292 | #define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 |
|---|
| 6293 | #define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc |
|---|
| 6294 | #define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f |
|---|
| 6295 | #define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL |
|---|
| 6296 | #define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L |
|---|
| 6297 | #define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L |
|---|
| 6298 | #define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L |
|---|
| 6299 | //MMEA1_SDP_VCD_RESERVE0 |
|---|
| 6300 | #define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 |
|---|
| 6301 | #define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 |
|---|
| 6302 | #define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc |
|---|
| 6303 | #define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 |
|---|
| 6304 | #define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 |
|---|
| 6305 | #define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL |
|---|
| 6306 | #define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L |
|---|
| 6307 | #define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L |
|---|
| 6308 | #define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L |
|---|
| 6309 | #define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L |
|---|
| 6310 | //MMEA1_SDP_VCD_RESERVE1 |
|---|
| 6311 | #define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 |
|---|
| 6312 | #define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 |
|---|
| 6313 | #define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc |
|---|
| 6314 | #define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f |
|---|
| 6315 | #define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL |
|---|
| 6316 | #define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L |
|---|
| 6317 | #define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L |
|---|
| 6318 | #define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L |
|---|
| 6319 | //MMEA1_SDP_REQ_CNTL |
|---|
| 6320 | #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 |
|---|
| 6321 | #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 |
|---|
| 6322 | #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 |
|---|
| 6323 | #define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 |
|---|
| 6324 | #define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 |
|---|
| 6325 | #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L |
|---|
| 6326 | #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L |
|---|
| 6327 | #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L |
|---|
| 6328 | #define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L |
|---|
| 6329 | #define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L |
|---|
| 6330 | //MMEA1_MISC |
|---|
| 6331 | #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 |
|---|
| 6332 | #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 |
|---|
| 6333 | #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 |
|---|
| 6334 | #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 |
|---|
| 6335 | #define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 |
|---|
| 6336 | #define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 |
|---|
| 6337 | #define MMEA1_MISC__RRET_SWAP_MODE__SHIFT 0x6 |
|---|
| 6338 | #define MMEA1_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x7 |
|---|
| 6339 | #define MMEA1_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x8 |
|---|
| 6340 | #define MMEA1_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xa |
|---|
| 6341 | #define MMEA1_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xc |
|---|
| 6342 | #define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xe |
|---|
| 6343 | #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x13 |
|---|
| 6344 | #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x14 |
|---|
| 6345 | #define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x15 |
|---|
| 6346 | #define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x16 |
|---|
| 6347 | #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x17 |
|---|
| 6348 | #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x18 |
|---|
| 6349 | #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L |
|---|
| 6350 | #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L |
|---|
| 6351 | #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L |
|---|
| 6352 | #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L |
|---|
| 6353 | #define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L |
|---|
| 6354 | #define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L |
|---|
| 6355 | #define MMEA1_MISC__RRET_SWAP_MODE_MASK 0x00000040L |
|---|
| 6356 | #define MMEA1_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000080L |
|---|
| 6357 | #define MMEA1_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000300L |
|---|
| 6358 | #define MMEA1_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00000C00L |
|---|
| 6359 | #define MMEA1_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00003000L |
|---|
| 6360 | #define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x0007C000L |
|---|
| 6361 | #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x00080000L |
|---|
| 6362 | #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x00100000L |
|---|
| 6363 | #define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x00200000L |
|---|
| 6364 | #define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x00400000L |
|---|
| 6365 | #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x00800000L |
|---|
| 6366 | #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x01000000L |
|---|
| 6367 | //MMEA1_LATENCY_SAMPLING |
|---|
| 6368 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 |
|---|
| 6369 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 |
|---|
| 6370 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 |
|---|
| 6371 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 |
|---|
| 6372 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 |
|---|
| 6373 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 |
|---|
| 6374 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 |
|---|
| 6375 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 |
|---|
| 6376 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 |
|---|
| 6377 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 |
|---|
| 6378 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa |
|---|
| 6379 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb |
|---|
| 6380 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc |
|---|
| 6381 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd |
|---|
| 6382 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe |
|---|
| 6383 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 |
|---|
| 6384 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L |
|---|
| 6385 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L |
|---|
| 6386 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L |
|---|
| 6387 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L |
|---|
| 6388 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L |
|---|
| 6389 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L |
|---|
| 6390 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L |
|---|
| 6391 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L |
|---|
| 6392 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L |
|---|
| 6393 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L |
|---|
| 6394 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L |
|---|
| 6395 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L |
|---|
| 6396 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L |
|---|
| 6397 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L |
|---|
| 6398 | #define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L |
|---|
| 6399 | #define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L |
|---|
| 6400 | //MMEA1_PERFCOUNTER_LO |
|---|
| 6401 | #define MMEA1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
|---|
| 6402 | #define MMEA1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
|---|
| 6403 | //MMEA1_PERFCOUNTER_HI |
|---|
| 6404 | #define MMEA1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
|---|
| 6405 | #define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
|---|
| 6406 | #define MMEA1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
|---|
| 6407 | #define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
|---|
| 6408 | //MMEA1_PERFCOUNTER0_CFG |
|---|
| 6409 | #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
|---|
| 6410 | #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
|---|
| 6411 | #define MMEA1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
|---|
| 6412 | #define MMEA1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
|---|
| 6413 | #define MMEA1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
|---|
| 6414 | #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
|---|
| 6415 | #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
|---|
| 6416 | #define MMEA1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
|---|
| 6417 | #define MMEA1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
|---|
| 6418 | #define MMEA1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
|---|
| 6419 | //MMEA1_PERFCOUNTER1_CFG |
|---|
| 6420 | #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
|---|
| 6421 | #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
|---|
| 6422 | #define MMEA1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
|---|
| 6423 | #define MMEA1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
|---|
| 6424 | #define MMEA1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
|---|
| 6425 | #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
|---|
| 6426 | #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
|---|
| 6427 | #define MMEA1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
|---|
| 6428 | #define MMEA1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
|---|
| 6429 | #define MMEA1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
|---|
| 6430 | //MMEA1_PERFCOUNTER_RSLT_CNTL |
|---|
| 6431 | #define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
|---|
| 6432 | #define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
|---|
| 6433 | #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
|---|
| 6434 | #define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
|---|
| 6435 | #define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
|---|
| 6436 | #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
|---|
| 6437 | #define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
|---|
| 6438 | #define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
|---|
| 6439 | #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
|---|
| 6440 | #define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
|---|
| 6441 | #define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
|---|
| 6442 | #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
|---|
| 6443 | //MMEA1_EDC_CNT |
|---|
| 6444 | #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 |
|---|
| 6445 | #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 |
|---|
| 6446 | #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 |
|---|
| 6447 | #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 |
|---|
| 6448 | #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 |
|---|
| 6449 | #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa |
|---|
| 6450 | #define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc |
|---|
| 6451 | #define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe |
|---|
| 6452 | #define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 |
|---|
| 6453 | #define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 |
|---|
| 6454 | #define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 |
|---|
| 6455 | #define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 |
|---|
| 6456 | #define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 |
|---|
| 6457 | #define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a |
|---|
| 6458 | #define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c |
|---|
| 6459 | #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L |
|---|
| 6460 | #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL |
|---|
| 6461 | #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L |
|---|
| 6462 | #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L |
|---|
| 6463 | #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L |
|---|
| 6464 | #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L |
|---|
| 6465 | #define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L |
|---|
| 6466 | #define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L |
|---|
| 6467 | #define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L |
|---|
| 6468 | #define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L |
|---|
| 6469 | #define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L |
|---|
| 6470 | #define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L |
|---|
| 6471 | #define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L |
|---|
| 6472 | #define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L |
|---|
| 6473 | #define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L |
|---|
| 6474 | //MMEA1_EDC_CNT2 |
|---|
| 6475 | #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 |
|---|
| 6476 | #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 |
|---|
| 6477 | #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 |
|---|
| 6478 | #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 |
|---|
| 6479 | #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 |
|---|
| 6480 | #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa |
|---|
| 6481 | #define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc |
|---|
| 6482 | #define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe |
|---|
| 6483 | #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L |
|---|
| 6484 | #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL |
|---|
| 6485 | #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L |
|---|
| 6486 | #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L |
|---|
| 6487 | #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L |
|---|
| 6488 | #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L |
|---|
| 6489 | #define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L |
|---|
| 6490 | #define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L |
|---|
| 6491 | //MMEA1_DSM_CNTL |
|---|
| 6492 | #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
|---|
| 6493 | #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
|---|
| 6494 | #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
|---|
| 6495 | #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
|---|
| 6496 | #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
|---|
| 6497 | #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
|---|
| 6498 | #define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
|---|
| 6499 | #define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
|---|
| 6500 | #define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc |
|---|
| 6501 | #define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
|---|
| 6502 | #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf |
|---|
| 6503 | #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
|---|
| 6504 | #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 |
|---|
| 6505 | #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
|---|
| 6506 | #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 |
|---|
| 6507 | #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 |
|---|
| 6508 | #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
|---|
| 6509 | #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
|---|
| 6510 | #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
|---|
| 6511 | #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
|---|
| 6512 | #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
|---|
| 6513 | #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
|---|
| 6514 | #define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
|---|
| 6515 | #define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
|---|
| 6516 | #define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
|---|
| 6517 | #define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
|---|
| 6518 | #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L |
|---|
| 6519 | #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
|---|
| 6520 | #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
|---|
| 6521 | #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
|---|
| 6522 | #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L |
|---|
| 6523 | #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L |
|---|
| 6524 | //MMEA1_DSM_CNTLA |
|---|
| 6525 | #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
|---|
| 6526 | #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
|---|
| 6527 | #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
|---|
| 6528 | #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
|---|
| 6529 | #define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
|---|
| 6530 | #define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
|---|
| 6531 | #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
|---|
| 6532 | #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
|---|
| 6533 | #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc |
|---|
| 6534 | #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
|---|
| 6535 | #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf |
|---|
| 6536 | #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
|---|
| 6537 | #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 |
|---|
| 6538 | #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
|---|
| 6539 | #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
|---|
| 6540 | #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
|---|
| 6541 | #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
|---|
| 6542 | #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
|---|
| 6543 | #define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
|---|
| 6544 | #define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
|---|
| 6545 | #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
|---|
| 6546 | #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
|---|
| 6547 | #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
|---|
| 6548 | #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
|---|
| 6549 | #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L |
|---|
| 6550 | #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
|---|
| 6551 | #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
|---|
| 6552 | #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
|---|
| 6553 | //MMEA1_DSM_CNTLB |
|---|
| 6554 | //MMEA1_DSM_CNTL2 |
|---|
| 6555 | #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
|---|
| 6556 | #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
|---|
| 6557 | #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
|---|
| 6558 | #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
|---|
| 6559 | #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
|---|
| 6560 | #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
|---|
| 6561 | #define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
|---|
| 6562 | #define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb |
|---|
| 6563 | #define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
|---|
| 6564 | #define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe |
|---|
| 6565 | #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf |
|---|
| 6566 | #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 |
|---|
| 6567 | #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 |
|---|
| 6568 | #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 |
|---|
| 6569 | #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 |
|---|
| 6570 | #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 |
|---|
| 6571 | #define MMEA1_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a |
|---|
| 6572 | #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
|---|
| 6573 | #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
|---|
| 6574 | #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
|---|
| 6575 | #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
|---|
| 6576 | #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
|---|
| 6577 | #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
|---|
| 6578 | #define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
|---|
| 6579 | #define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
|---|
| 6580 | #define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
|---|
| 6581 | #define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
|---|
| 6582 | #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L |
|---|
| 6583 | #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L |
|---|
| 6584 | #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
|---|
| 6585 | #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L |
|---|
| 6586 | #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L |
|---|
| 6587 | #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L |
|---|
| 6588 | #define MMEA1_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L |
|---|
| 6589 | //MMEA1_DSM_CNTL2A |
|---|
| 6590 | #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
|---|
| 6591 | #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
|---|
| 6592 | #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
|---|
| 6593 | #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
|---|
| 6594 | #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
|---|
| 6595 | #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
|---|
| 6596 | #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
|---|
| 6597 | #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb |
|---|
| 6598 | #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
|---|
| 6599 | #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe |
|---|
| 6600 | #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf |
|---|
| 6601 | #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 |
|---|
| 6602 | #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 |
|---|
| 6603 | #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 |
|---|
| 6604 | #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
|---|
| 6605 | #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
|---|
| 6606 | #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
|---|
| 6607 | #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
|---|
| 6608 | #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
|---|
| 6609 | #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
|---|
| 6610 | #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
|---|
| 6611 | #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
|---|
| 6612 | #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
|---|
| 6613 | #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
|---|
| 6614 | #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L |
|---|
| 6615 | #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L |
|---|
| 6616 | #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
|---|
| 6617 | #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L |
|---|
| 6618 | //MMEA1_DSM_CNTL2B |
|---|
| 6619 | //MMEA1_CGTT_CLK_CTRL |
|---|
| 6620 | #define MMEA1_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
|---|
| 6621 | #define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
|---|
| 6622 | #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 |
|---|
| 6623 | #define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b |
|---|
| 6624 | #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c |
|---|
| 6625 | #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d |
|---|
| 6626 | #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e |
|---|
| 6627 | #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f |
|---|
| 6628 | #define MMEA1_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
|---|
| 6629 | #define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
|---|
| 6630 | #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L |
|---|
| 6631 | #define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L |
|---|
| 6632 | #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L |
|---|
| 6633 | #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L |
|---|
| 6634 | #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L |
|---|
| 6635 | #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L |
|---|
| 6636 | //MMEA1_EDC_MODE |
|---|
| 6637 | #define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 |
|---|
| 6638 | #define MMEA1_EDC_MODE__GATE_FUE__SHIFT 0x11 |
|---|
| 6639 | #define MMEA1_EDC_MODE__DED_MODE__SHIFT 0x14 |
|---|
| 6640 | #define MMEA1_EDC_MODE__PROP_FED__SHIFT 0x1d |
|---|
| 6641 | #define MMEA1_EDC_MODE__BYPASS__SHIFT 0x1f |
|---|
| 6642 | #define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L |
|---|
| 6643 | #define MMEA1_EDC_MODE__GATE_FUE_MASK 0x00020000L |
|---|
| 6644 | #define MMEA1_EDC_MODE__DED_MODE_MASK 0x00300000L |
|---|
| 6645 | #define MMEA1_EDC_MODE__PROP_FED_MASK 0x20000000L |
|---|
| 6646 | #define MMEA1_EDC_MODE__BYPASS_MASK 0x80000000L |
|---|
| 6647 | //MMEA1_ERR_STATUS |
|---|
| 6648 | #define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 |
|---|
| 6649 | #define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 |
|---|
| 6650 | #define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0x8 |
|---|
| 6651 | #define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0x9 |
|---|
| 6652 | #define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xa |
|---|
| 6653 | #define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL |
|---|
| 6654 | #define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L |
|---|
| 6655 | #define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000100L |
|---|
| 6656 | #define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000200L |
|---|
| 6657 | #define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00000400L |
|---|
| 6658 | //MMEA1_MISC2 |
|---|
| 6659 | #define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 |
|---|
| 6660 | #define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 |
|---|
| 6661 | #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 |
|---|
| 6662 | #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 |
|---|
| 6663 | #define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L |
|---|
| 6664 | #define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L |
|---|
| 6665 | #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL |
|---|
| 6666 | #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L |
|---|
| 6667 | |
|---|
| 6668 | |
|---|
| 6669 | // addressBlock: mmhub_pctldec |
|---|
| 6670 | //PCTL_MISC |
|---|
| 6671 | #define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x0 |
|---|
| 6672 | #define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x3 |
|---|
| 6673 | #define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0x6 |
|---|
| 6674 | #define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0xb |
|---|
| 6675 | #define PCTL_MISC__IGNORE_EA0_SDP_ACK__SHIFT 0xc |
|---|
| 6676 | #define PCTL_MISC__IGNORE_EA1_SDP_ACK__SHIFT 0xd |
|---|
| 6677 | #define PCTL_MISC__PGFSM_CMD_STATUS__SHIFT 0xe |
|---|
| 6678 | #define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x00000007L |
|---|
| 6679 | #define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x00000038L |
|---|
| 6680 | #define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x000007C0L |
|---|
| 6681 | #define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00000800L |
|---|
| 6682 | #define PCTL_MISC__IGNORE_EA0_SDP_ACK_MASK 0x00001000L |
|---|
| 6683 | #define PCTL_MISC__IGNORE_EA1_SDP_ACK_MASK 0x00002000L |
|---|
| 6684 | #define PCTL_MISC__PGFSM_CMD_STATUS_MASK 0x0000C000L |
|---|
| 6685 | //PCTL_MMHUB_DEEPSLEEP |
|---|
| 6686 | #define PCTL_MMHUB_DEEPSLEEP__DS0__SHIFT 0x0 |
|---|
| 6687 | #define PCTL_MMHUB_DEEPSLEEP__DS1__SHIFT 0x1 |
|---|
| 6688 | #define PCTL_MMHUB_DEEPSLEEP__DS2__SHIFT 0x2 |
|---|
| 6689 | #define PCTL_MMHUB_DEEPSLEEP__DS3__SHIFT 0x3 |
|---|
| 6690 | #define PCTL_MMHUB_DEEPSLEEP__DS4__SHIFT 0x4 |
|---|
| 6691 | #define PCTL_MMHUB_DEEPSLEEP__DS5__SHIFT 0x5 |
|---|
| 6692 | #define PCTL_MMHUB_DEEPSLEEP__DS6__SHIFT 0x6 |
|---|
| 6693 | #define PCTL_MMHUB_DEEPSLEEP__DS7__SHIFT 0x7 |
|---|
| 6694 | #define PCTL_MMHUB_DEEPSLEEP__DS8__SHIFT 0x8 |
|---|
| 6695 | #define PCTL_MMHUB_DEEPSLEEP__DS9__SHIFT 0x9 |
|---|
| 6696 | #define PCTL_MMHUB_DEEPSLEEP__DS10__SHIFT 0xa |
|---|
| 6697 | #define PCTL_MMHUB_DEEPSLEEP__DS11__SHIFT 0xb |
|---|
| 6698 | #define PCTL_MMHUB_DEEPSLEEP__DS12__SHIFT 0xc |
|---|
| 6699 | #define PCTL_MMHUB_DEEPSLEEP__DS13__SHIFT 0xd |
|---|
| 6700 | #define PCTL_MMHUB_DEEPSLEEP__DS14__SHIFT 0xe |
|---|
| 6701 | #define PCTL_MMHUB_DEEPSLEEP__DS15__SHIFT 0xf |
|---|
| 6702 | #define PCTL_MMHUB_DEEPSLEEP__DS16__SHIFT 0x10 |
|---|
| 6703 | #define PCTL_MMHUB_DEEPSLEEP__SETCLEAR__SHIFT 0x1f |
|---|
| 6704 | #define PCTL_MMHUB_DEEPSLEEP__DS0_MASK 0x00000001L |
|---|
| 6705 | #define PCTL_MMHUB_DEEPSLEEP__DS1_MASK 0x00000002L |
|---|
| 6706 | #define PCTL_MMHUB_DEEPSLEEP__DS2_MASK 0x00000004L |
|---|
| 6707 | #define PCTL_MMHUB_DEEPSLEEP__DS3_MASK 0x00000008L |
|---|
| 6708 | #define PCTL_MMHUB_DEEPSLEEP__DS4_MASK 0x00000010L |
|---|
| 6709 | #define PCTL_MMHUB_DEEPSLEEP__DS5_MASK 0x00000020L |
|---|
| 6710 | #define PCTL_MMHUB_DEEPSLEEP__DS6_MASK 0x00000040L |
|---|
| 6711 | #define PCTL_MMHUB_DEEPSLEEP__DS7_MASK 0x00000080L |
|---|
| 6712 | #define PCTL_MMHUB_DEEPSLEEP__DS8_MASK 0x00000100L |
|---|
| 6713 | #define PCTL_MMHUB_DEEPSLEEP__DS9_MASK 0x00000200L |
|---|
| 6714 | #define PCTL_MMHUB_DEEPSLEEP__DS10_MASK 0x00000400L |
|---|
| 6715 | #define PCTL_MMHUB_DEEPSLEEP__DS11_MASK 0x00000800L |
|---|
| 6716 | #define PCTL_MMHUB_DEEPSLEEP__DS12_MASK 0x00001000L |
|---|
| 6717 | #define PCTL_MMHUB_DEEPSLEEP__DS13_MASK 0x00002000L |
|---|
| 6718 | #define PCTL_MMHUB_DEEPSLEEP__DS14_MASK 0x00004000L |
|---|
| 6719 | #define PCTL_MMHUB_DEEPSLEEP__DS15_MASK 0x00008000L |
|---|
| 6720 | #define PCTL_MMHUB_DEEPSLEEP__DS16_MASK 0x00010000L |
|---|
| 6721 | #define PCTL_MMHUB_DEEPSLEEP__SETCLEAR_MASK 0x80000000L |
|---|
| 6722 | //PCTL_MMHUB_DEEPSLEEP_OVERRIDE |
|---|
| 6723 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 |
|---|
| 6724 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 |
|---|
| 6725 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 |
|---|
| 6726 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 |
|---|
| 6727 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 |
|---|
| 6728 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 |
|---|
| 6729 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 |
|---|
| 6730 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 |
|---|
| 6731 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 |
|---|
| 6732 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 |
|---|
| 6733 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa |
|---|
| 6734 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb |
|---|
| 6735 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc |
|---|
| 6736 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd |
|---|
| 6737 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe |
|---|
| 6738 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf |
|---|
| 6739 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 |
|---|
| 6740 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L |
|---|
| 6741 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L |
|---|
| 6742 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L |
|---|
| 6743 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L |
|---|
| 6744 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L |
|---|
| 6745 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L |
|---|
| 6746 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L |
|---|
| 6747 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L |
|---|
| 6748 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L |
|---|
| 6749 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L |
|---|
| 6750 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L |
|---|
| 6751 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L |
|---|
| 6752 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L |
|---|
| 6753 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L |
|---|
| 6754 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L |
|---|
| 6755 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L |
|---|
| 6756 | #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L |
|---|
| 6757 | //PCTL_PG_IGNORE_DEEPSLEEP |
|---|
| 6758 | #define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x0 |
|---|
| 6759 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x1 |
|---|
| 6760 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x2 |
|---|
| 6761 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x3 |
|---|
| 6762 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x4 |
|---|
| 6763 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x5 |
|---|
| 6764 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x6 |
|---|
| 6765 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x7 |
|---|
| 6766 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x8 |
|---|
| 6767 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x9 |
|---|
| 6768 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0xa |
|---|
| 6769 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xb |
|---|
| 6770 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xc |
|---|
| 6771 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xd |
|---|
| 6772 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xe |
|---|
| 6773 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xf |
|---|
| 6774 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0x10 |
|---|
| 6775 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x11 |
|---|
| 6776 | #define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00000001L |
|---|
| 6777 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000002L |
|---|
| 6778 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000004L |
|---|
| 6779 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000008L |
|---|
| 6780 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000010L |
|---|
| 6781 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000020L |
|---|
| 6782 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000040L |
|---|
| 6783 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000080L |
|---|
| 6784 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000100L |
|---|
| 6785 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000200L |
|---|
| 6786 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000400L |
|---|
| 6787 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000800L |
|---|
| 6788 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00001000L |
|---|
| 6789 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00002000L |
|---|
| 6790 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00004000L |
|---|
| 6791 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00008000L |
|---|
| 6792 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00010000L |
|---|
| 6793 | #define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00020000L |
|---|
| 6794 | //PCTL_PG_DAGB |
|---|
| 6795 | #define PCTL_PG_DAGB__DS0__SHIFT 0x0 |
|---|
| 6796 | #define PCTL_PG_DAGB__DS1__SHIFT 0x1 |
|---|
| 6797 | #define PCTL_PG_DAGB__DS2__SHIFT 0x2 |
|---|
| 6798 | #define PCTL_PG_DAGB__DS3__SHIFT 0x3 |
|---|
| 6799 | #define PCTL_PG_DAGB__DS4__SHIFT 0x4 |
|---|
| 6800 | #define PCTL_PG_DAGB__DS5__SHIFT 0x5 |
|---|
| 6801 | #define PCTL_PG_DAGB__DS6__SHIFT 0x6 |
|---|
| 6802 | #define PCTL_PG_DAGB__DS7__SHIFT 0x7 |
|---|
| 6803 | #define PCTL_PG_DAGB__DS8__SHIFT 0x8 |
|---|
| 6804 | #define PCTL_PG_DAGB__DS9__SHIFT 0x9 |
|---|
| 6805 | #define PCTL_PG_DAGB__DS10__SHIFT 0xa |
|---|
| 6806 | #define PCTL_PG_DAGB__DS11__SHIFT 0xb |
|---|
| 6807 | #define PCTL_PG_DAGB__DS12__SHIFT 0xc |
|---|
| 6808 | #define PCTL_PG_DAGB__DS13__SHIFT 0xd |
|---|
| 6809 | #define PCTL_PG_DAGB__DS14__SHIFT 0xe |
|---|
| 6810 | #define PCTL_PG_DAGB__DS15__SHIFT 0xf |
|---|
| 6811 | #define PCTL_PG_DAGB__DS16__SHIFT 0x10 |
|---|
| 6812 | #define PCTL_PG_DAGB__DS0_MASK 0x00000001L |
|---|
| 6813 | #define PCTL_PG_DAGB__DS1_MASK 0x00000002L |
|---|
| 6814 | #define PCTL_PG_DAGB__DS2_MASK 0x00000004L |
|---|
| 6815 | #define PCTL_PG_DAGB__DS3_MASK 0x00000008L |
|---|
| 6816 | #define PCTL_PG_DAGB__DS4_MASK 0x00000010L |
|---|
| 6817 | #define PCTL_PG_DAGB__DS5_MASK 0x00000020L |
|---|
| 6818 | #define PCTL_PG_DAGB__DS6_MASK 0x00000040L |
|---|
| 6819 | #define PCTL_PG_DAGB__DS7_MASK 0x00000080L |
|---|
| 6820 | #define PCTL_PG_DAGB__DS8_MASK 0x00000100L |
|---|
| 6821 | #define PCTL_PG_DAGB__DS9_MASK 0x00000200L |
|---|
| 6822 | #define PCTL_PG_DAGB__DS10_MASK 0x00000400L |
|---|
| 6823 | #define PCTL_PG_DAGB__DS11_MASK 0x00000800L |
|---|
| 6824 | #define PCTL_PG_DAGB__DS12_MASK 0x00001000L |
|---|
| 6825 | #define PCTL_PG_DAGB__DS13_MASK 0x00002000L |
|---|
| 6826 | #define PCTL_PG_DAGB__DS14_MASK 0x00004000L |
|---|
| 6827 | #define PCTL_PG_DAGB__DS15_MASK 0x00008000L |
|---|
| 6828 | #define PCTL_PG_DAGB__DS16_MASK 0x00010000L |
|---|
| 6829 | //PCTL0_RENG_RAM_INDEX |
|---|
| 6830 | #define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 |
|---|
| 6831 | #define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL |
|---|
| 6832 | //PCTL0_RENG_RAM_DATA |
|---|
| 6833 | #define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 |
|---|
| 6834 | #define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL |
|---|
| 6835 | //PCTL0_RENG_EXECUTE |
|---|
| 6836 | #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 |
|---|
| 6837 | #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 |
|---|
| 6838 | #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2 |
|---|
| 6839 | #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3 |
|---|
| 6840 | #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xe |
|---|
| 6841 | #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x19 |
|---|
| 6842 | #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L |
|---|
| 6843 | #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L |
|---|
| 6844 | #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L |
|---|
| 6845 | #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00003FF8L |
|---|
| 6846 | #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x01FFC000L |
|---|
| 6847 | #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x02000000L |
|---|
| 6848 | //PCTL0_MISC |
|---|
| 6849 | #define PCTL0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb |
|---|
| 6850 | #define PCTL0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc |
|---|
| 6851 | #define PCTL0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf |
|---|
| 6852 | #define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 |
|---|
| 6853 | #define PCTL0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L |
|---|
| 6854 | #define PCTL0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L |
|---|
| 6855 | #define PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L |
|---|
| 6856 | #define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L |
|---|
| 6857 | //PCTL0_STCTRL_REGISTER_SAVE_RANGE0 |
|---|
| 6858 | #define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 |
|---|
| 6859 | #define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 |
|---|
| 6860 | #define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL |
|---|
| 6861 | #define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L |
|---|
| 6862 | //PCTL0_STCTRL_REGISTER_SAVE_RANGE1 |
|---|
| 6863 | #define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 |
|---|
| 6864 | #define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 |
|---|
| 6865 | #define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL |
|---|
| 6866 | #define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L |
|---|
| 6867 | //PCTL0_STCTRL_REGISTER_SAVE_RANGE2 |
|---|
| 6868 | #define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 |
|---|
| 6869 | #define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 |
|---|
| 6870 | #define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL |
|---|
| 6871 | #define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L |
|---|
| 6872 | //PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET |
|---|
| 6873 | #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 |
|---|
| 6874 | #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 |
|---|
| 6875 | #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL |
|---|
| 6876 | #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L |
|---|
| 6877 | //PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1 |
|---|
| 6878 | #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 |
|---|
| 6879 | #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 |
|---|
| 6880 | #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL |
|---|
| 6881 | #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L |
|---|
| 6882 | //PCTL1_RENG_RAM_INDEX |
|---|
| 6883 | #define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 |
|---|
| 6884 | #define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL |
|---|
| 6885 | //PCTL1_RENG_RAM_DATA |
|---|
| 6886 | #define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 |
|---|
| 6887 | #define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL |
|---|
| 6888 | //PCTL1_RENG_EXECUTE |
|---|
| 6889 | #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 |
|---|
| 6890 | #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 |
|---|
| 6891 | #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2 |
|---|
| 6892 | #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3 |
|---|
| 6893 | #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd |
|---|
| 6894 | #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x17 |
|---|
| 6895 | #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L |
|---|
| 6896 | #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L |
|---|
| 6897 | #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L |
|---|
| 6898 | #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FF8L |
|---|
| 6899 | #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x007FE000L |
|---|
| 6900 | #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00800000L |
|---|
| 6901 | //PCTL1_MISC |
|---|
| 6902 | #define PCTL1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa |
|---|
| 6903 | #define PCTL1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb |
|---|
| 6904 | #define PCTL1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe |
|---|
| 6905 | #define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf |
|---|
| 6906 | #define PCTL1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 |
|---|
| 6907 | #define PCTL1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L |
|---|
| 6908 | #define PCTL1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L |
|---|
| 6909 | #define PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L |
|---|
| 6910 | #define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L |
|---|
| 6911 | #define PCTL1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L |
|---|
| 6912 | //PCTL1_STCTRL_REGISTER_SAVE_RANGE0 |
|---|
| 6913 | #define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 |
|---|
| 6914 | #define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 |
|---|
| 6915 | #define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL |
|---|
| 6916 | #define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L |
|---|
| 6917 | //PCTL1_STCTRL_REGISTER_SAVE_RANGE1 |
|---|
| 6918 | #define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 |
|---|
| 6919 | #define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 |
|---|
| 6920 | #define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL |
|---|
| 6921 | #define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L |
|---|
| 6922 | //PCTL1_STCTRL_REGISTER_SAVE_RANGE2 |
|---|
| 6923 | #define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 |
|---|
| 6924 | #define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 |
|---|
| 6925 | #define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL |
|---|
| 6926 | #define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L |
|---|
| 6927 | //PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET |
|---|
| 6928 | #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 |
|---|
| 6929 | #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 |
|---|
| 6930 | #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL |
|---|
| 6931 | #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L |
|---|
| 6932 | //PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1 |
|---|
| 6933 | #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 |
|---|
| 6934 | #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 |
|---|
| 6935 | #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL |
|---|
| 6936 | #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L |
|---|
| 6937 | //PCTL2_RENG_RAM_INDEX |
|---|
| 6938 | #define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 |
|---|
| 6939 | #define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL |
|---|
| 6940 | //PCTL2_RENG_RAM_DATA |
|---|
| 6941 | #define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 |
|---|
| 6942 | #define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL |
|---|
| 6943 | //PCTL2_RENG_EXECUTE |
|---|
| 6944 | #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 |
|---|
| 6945 | #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 |
|---|
| 6946 | #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2 |
|---|
| 6947 | #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3 |
|---|
| 6948 | #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd |
|---|
| 6949 | #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x17 |
|---|
| 6950 | #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L |
|---|
| 6951 | #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L |
|---|
| 6952 | #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L |
|---|
| 6953 | #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FF8L |
|---|
| 6954 | #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x007FE000L |
|---|
| 6955 | #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00800000L |
|---|
| 6956 | //PCTL2_MISC |
|---|
| 6957 | #define PCTL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa |
|---|
| 6958 | #define PCTL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb |
|---|
| 6959 | #define PCTL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe |
|---|
| 6960 | #define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf |
|---|
| 6961 | #define PCTL2_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 |
|---|
| 6962 | #define PCTL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L |
|---|
| 6963 | #define PCTL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L |
|---|
| 6964 | #define PCTL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L |
|---|
| 6965 | #define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L |
|---|
| 6966 | #define PCTL2_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L |
|---|
| 6967 | //PCTL2_STCTRL_REGISTER_SAVE_RANGE0 |
|---|
| 6968 | #define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 |
|---|
| 6969 | #define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 |
|---|
| 6970 | #define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL |
|---|
| 6971 | #define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L |
|---|
| 6972 | //PCTL2_STCTRL_REGISTER_SAVE_RANGE1 |
|---|
| 6973 | #define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 |
|---|
| 6974 | #define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 |
|---|
| 6975 | #define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL |
|---|
| 6976 | #define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L |
|---|
| 6977 | //PCTL2_STCTRL_REGISTER_SAVE_RANGE2 |
|---|
| 6978 | #define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 |
|---|
| 6979 | #define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 |
|---|
| 6980 | #define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL |
|---|
| 6981 | #define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L |
|---|
| 6982 | //PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET |
|---|
| 6983 | #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 |
|---|
| 6984 | #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 |
|---|
| 6985 | #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL |
|---|
| 6986 | #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L |
|---|
| 6987 | //PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1 |
|---|
| 6988 | #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 |
|---|
| 6989 | #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 |
|---|
| 6990 | #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL |
|---|
| 6991 | #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L |
|---|
| 6992 | |
|---|
| 6993 | |
|---|
| 6994 | // addressBlock: mmhub_l1tlb_vml1dec |
|---|
| 6995 | //MC_VM_MX_L1_TLB0_STATUS |
|---|
| 6996 | #define MC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0 |
|---|
| 6997 | #define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 |
|---|
| 6998 | #define MC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L |
|---|
| 6999 | #define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L |
|---|
| 7000 | //MC_VM_MX_L1_TLB1_STATUS |
|---|
| 7001 | #define MC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0 |
|---|
| 7002 | #define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 |
|---|
| 7003 | #define MC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L |
|---|
| 7004 | #define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L |
|---|
| 7005 | //MC_VM_MX_L1_TLB2_STATUS |
|---|
| 7006 | #define MC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0 |
|---|
| 7007 | #define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 |
|---|
| 7008 | #define MC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L |
|---|
| 7009 | #define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L |
|---|
| 7010 | //MC_VM_MX_L1_TLB3_STATUS |
|---|
| 7011 | #define MC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0 |
|---|
| 7012 | #define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 |
|---|
| 7013 | #define MC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L |
|---|
| 7014 | #define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L |
|---|
| 7015 | //MC_VM_MX_L1_TLB4_STATUS |
|---|
| 7016 | #define MC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0 |
|---|
| 7017 | #define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 |
|---|
| 7018 | #define MC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L |
|---|
| 7019 | #define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L |
|---|
| 7020 | //MC_VM_MX_L1_TLB5_STATUS |
|---|
| 7021 | #define MC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0 |
|---|
| 7022 | #define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 |
|---|
| 7023 | #define MC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L |
|---|
| 7024 | #define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L |
|---|
| 7025 | //MC_VM_MX_L1_TLB6_STATUS |
|---|
| 7026 | #define MC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0 |
|---|
| 7027 | #define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 |
|---|
| 7028 | #define MC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L |
|---|
| 7029 | #define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L |
|---|
| 7030 | //MC_VM_MX_L1_TLB7_STATUS |
|---|
| 7031 | #define MC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0 |
|---|
| 7032 | #define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 |
|---|
| 7033 | #define MC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L |
|---|
| 7034 | #define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L |
|---|
| 7035 | |
|---|
| 7036 | |
|---|
| 7037 | // addressBlock: mmhub_l1tlb_vml1pldec |
|---|
| 7038 | //MC_VM_MX_L1_PERFCOUNTER0_CFG |
|---|
| 7039 | #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
|---|
| 7040 | #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
|---|
| 7041 | #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
|---|
| 7042 | #define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
|---|
| 7043 | #define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
|---|
| 7044 | #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
|---|
| 7045 | #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
|---|
| 7046 | #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
|---|
| 7047 | #define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
|---|
| 7048 | #define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
|---|
| 7049 | //MC_VM_MX_L1_PERFCOUNTER1_CFG |
|---|
| 7050 | #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
|---|
| 7051 | #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
|---|
| 7052 | #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
|---|
| 7053 | #define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
|---|
| 7054 | #define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
|---|
| 7055 | #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
|---|
| 7056 | #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
|---|
| 7057 | #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
|---|
| 7058 | #define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
|---|
| 7059 | #define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
|---|
| 7060 | //MC_VM_MX_L1_PERFCOUNTER2_CFG |
|---|
| 7061 | #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 |
|---|
| 7062 | #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 |
|---|
| 7063 | #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 |
|---|
| 7064 | #define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c |
|---|
| 7065 | #define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d |
|---|
| 7066 | #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL |
|---|
| 7067 | #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L |
|---|
| 7068 | #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L |
|---|
| 7069 | #define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L |
|---|
| 7070 | #define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L |
|---|
| 7071 | //MC_VM_MX_L1_PERFCOUNTER3_CFG |
|---|
| 7072 | #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 |
|---|
| 7073 | #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 |
|---|
| 7074 | #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 |
|---|
| 7075 | #define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c |
|---|
| 7076 | #define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d |
|---|
| 7077 | #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL |
|---|
| 7078 | #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L |
|---|
| 7079 | #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L |
|---|
| 7080 | #define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L |
|---|
| 7081 | #define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L |
|---|
| 7082 | //MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL |
|---|
| 7083 | #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
|---|
| 7084 | #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
|---|
| 7085 | #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
|---|
| 7086 | #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
|---|
| 7087 | #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
|---|
| 7088 | #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
|---|
| 7089 | #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
|---|
| 7090 | #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
|---|
| 7091 | #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
|---|
| 7092 | #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
|---|
| 7093 | #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
|---|
| 7094 | #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
|---|
| 7095 | |
|---|
| 7096 | |
|---|
| 7097 | // addressBlock: mmhub_l1tlb_vml1prdec |
|---|
| 7098 | //MC_VM_MX_L1_PERFCOUNTER_LO |
|---|
| 7099 | #define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
|---|
| 7100 | #define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
|---|
| 7101 | //MC_VM_MX_L1_PERFCOUNTER_HI |
|---|
| 7102 | #define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
|---|
| 7103 | #define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
|---|
| 7104 | #define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
|---|
| 7105 | #define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
|---|
| 7106 | |
|---|
| 7107 | |
|---|
| 7108 | // addressBlock: mmhub_l1tlb_vmtlspfdec |
|---|
| 7109 | //VM_L2_SAW_CNTL |
|---|
| 7110 | #define VM_L2_SAW_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 |
|---|
| 7111 | #define VM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 |
|---|
| 7112 | #define VM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 |
|---|
| 7113 | #define VM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 |
|---|
| 7114 | #define VM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 |
|---|
| 7115 | #define VM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 |
|---|
| 7116 | #define VM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa |
|---|
| 7117 | #define VM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb |
|---|
| 7118 | #define VM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc |
|---|
| 7119 | #define VM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf |
|---|
| 7120 | #define VM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 |
|---|
| 7121 | #define VM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 |
|---|
| 7122 | #define VM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 |
|---|
| 7123 | #define VM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a |
|---|
| 7124 | #define VM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c |
|---|
| 7125 | #define VM_L2_SAW_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L |
|---|
| 7126 | #define VM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L |
|---|
| 7127 | #define VM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL |
|---|
| 7128 | #define VM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L |
|---|
| 7129 | #define VM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L |
|---|
| 7130 | #define VM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L |
|---|
| 7131 | #define VM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L |
|---|
| 7132 | #define VM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L |
|---|
| 7133 | #define VM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L |
|---|
| 7134 | #define VM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L |
|---|
| 7135 | #define VM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L |
|---|
| 7136 | #define VM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L |
|---|
| 7137 | #define VM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L |
|---|
| 7138 | #define VM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0x0C000000L |
|---|
| 7139 | #define VM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000L |
|---|
| 7140 | //VM_L2_SAW_CNTL2 |
|---|
| 7141 | #define VM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 |
|---|
| 7142 | #define VM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 |
|---|
| 7143 | #define VM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 |
|---|
| 7144 | #define VM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 |
|---|
| 7145 | #define VM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x17 |
|---|
| 7146 | #define VM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a |
|---|
| 7147 | #define VM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c |
|---|
| 7148 | #define VM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L |
|---|
| 7149 | #define VM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L |
|---|
| 7150 | #define VM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L |
|---|
| 7151 | #define VM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L |
|---|
| 7152 | #define VM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x03800000L |
|---|
| 7153 | #define VM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L |
|---|
| 7154 | #define VM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L |
|---|
| 7155 | //VM_L2_SAW_CNTL3 |
|---|
| 7156 | #define VM_L2_SAW_CNTL3__BANK_SELECT__SHIFT 0x0 |
|---|
| 7157 | #define VM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 |
|---|
| 7158 | #define VM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 |
|---|
| 7159 | #define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf |
|---|
| 7160 | #define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 |
|---|
| 7161 | #define VM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 |
|---|
| 7162 | #define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 |
|---|
| 7163 | #define VM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c |
|---|
| 7164 | #define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d |
|---|
| 7165 | #define VM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e |
|---|
| 7166 | #define VM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f |
|---|
| 7167 | #define VM_L2_SAW_CNTL3__BANK_SELECT_MASK 0x0000003FL |
|---|
| 7168 | #define VM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L |
|---|
| 7169 | #define VM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L |
|---|
| 7170 | #define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L |
|---|
| 7171 | #define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L |
|---|
| 7172 | #define VM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L |
|---|
| 7173 | #define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L |
|---|
| 7174 | #define VM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L |
|---|
| 7175 | #define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L |
|---|
| 7176 | #define VM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L |
|---|
| 7177 | #define VM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L |
|---|
| 7178 | //VM_L2_SAW_CNTL4 |
|---|
| 7179 | #define VM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 |
|---|
| 7180 | #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL__SHIFT 0x6 |
|---|
| 7181 | #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED__SHIFT 0x7 |
|---|
| 7182 | #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP__SHIFT 0x8 |
|---|
| 7183 | #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL__SHIFT 0x9 |
|---|
| 7184 | #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED__SHIFT 0xa |
|---|
| 7185 | #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP__SHIFT 0xb |
|---|
| 7186 | #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL__SHIFT 0xc |
|---|
| 7187 | #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED__SHIFT 0xd |
|---|
| 7188 | #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP__SHIFT 0xe |
|---|
| 7189 | #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL__SHIFT 0xf |
|---|
| 7190 | #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED__SHIFT 0x10 |
|---|
| 7191 | #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP__SHIFT 0x11 |
|---|
| 7192 | #define VM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING__SHIFT 0x12 |
|---|
| 7193 | #define VM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL |
|---|
| 7194 | #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL_MASK 0x00000040L |
|---|
| 7195 | #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED_MASK 0x00000080L |
|---|
| 7196 | #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP_MASK 0x00000100L |
|---|
| 7197 | #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL_MASK 0x00000200L |
|---|
| 7198 | #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED_MASK 0x00000400L |
|---|
| 7199 | #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP_MASK 0x00000800L |
|---|
| 7200 | #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL_MASK 0x00001000L |
|---|
| 7201 | #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED_MASK 0x00002000L |
|---|
| 7202 | #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP_MASK 0x00004000L |
|---|
| 7203 | #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL_MASK 0x00008000L |
|---|
| 7204 | #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED_MASK 0x00010000L |
|---|
| 7205 | #define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP_MASK 0x00020000L |
|---|
| 7206 | #define VM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING_MASK 0x00040000L |
|---|
| 7207 | //VM_L2_SAW_CONTEXT0_CNTL |
|---|
| 7208 | #define VM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
|---|
| 7209 | #define VM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
|---|
| 7210 | #define VM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 |
|---|
| 7211 | #define VM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 |
|---|
| 7212 | #define VM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6 |
|---|
| 7213 | #define VM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 |
|---|
| 7214 | #define VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
|---|
| 7215 | #define VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
|---|
| 7216 | #define VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb |
|---|
| 7217 | #define VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc |
|---|
| 7218 | #define VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd |
|---|
| 7219 | #define VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe |
|---|
| 7220 | #define VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
|---|
| 7221 | #define VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
|---|
| 7222 | #define VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11 |
|---|
| 7223 | #define VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 |
|---|
| 7224 | #define VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 |
|---|
| 7225 | #define VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14 |
|---|
| 7226 | #define VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
|---|
| 7227 | #define VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
|---|
| 7228 | #define VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17 |
|---|
| 7229 | #define VM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18 |
|---|
| 7230 | #define VM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
|---|
| 7231 | #define VM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
|---|
| 7232 | #define VM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L |
|---|
| 7233 | #define VM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L |
|---|
| 7234 | #define VM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000040L |
|---|
| 7235 | #define VM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L |
|---|
| 7236 | #define VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
|---|
| 7237 | #define VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
|---|
| 7238 | #define VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00000800L |
|---|
| 7239 | #define VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L |
|---|
| 7240 | #define VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L |
|---|
| 7241 | #define VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00004000L |
|---|
| 7242 | #define VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
|---|
| 7243 | #define VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
|---|
| 7244 | #define VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00020000L |
|---|
| 7245 | #define VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L |
|---|
| 7246 | #define VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L |
|---|
| 7247 | #define VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00100000L |
|---|
| 7248 | #define VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
|---|
| 7249 | #define VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
|---|
| 7250 | #define VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00800000L |
|---|
| 7251 | #define VM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x0F000000L |
|---|
| 7252 | //VM_L2_SAW_CONTEXT0_CNTL2 |
|---|
| 7253 | #define VM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 |
|---|
| 7254 | #define VM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1 |
|---|
| 7255 | #define VM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2 |
|---|
| 7256 | #define VM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3 |
|---|
| 7257 | #define VM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4 |
|---|
| 7258 | #define VM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L |
|---|
| 7259 | #define VM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x00000002L |
|---|
| 7260 | #define VM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x00000004L |
|---|
| 7261 | #define VM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000008L |
|---|
| 7262 | #define VM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x00000010L |
|---|
| 7263 | //VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 |
|---|
| 7264 | #define VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 7265 | #define VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 7266 | //VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 |
|---|
| 7267 | #define VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 7268 | #define VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 7269 | //VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 |
|---|
| 7270 | #define VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 7271 | #define VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 7272 | //VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 |
|---|
| 7273 | #define VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 7274 | #define VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 7275 | //VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 |
|---|
| 7276 | #define VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 7277 | #define VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 7278 | //VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 |
|---|
| 7279 | #define VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 7280 | #define VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 7281 | //VM_L2_SAW_CONTEXTS_DISABLE |
|---|
| 7282 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 |
|---|
| 7283 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 |
|---|
| 7284 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 |
|---|
| 7285 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 |
|---|
| 7286 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 |
|---|
| 7287 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 |
|---|
| 7288 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 |
|---|
| 7289 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 |
|---|
| 7290 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 |
|---|
| 7291 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 |
|---|
| 7292 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa |
|---|
| 7293 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb |
|---|
| 7294 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc |
|---|
| 7295 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd |
|---|
| 7296 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe |
|---|
| 7297 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf |
|---|
| 7298 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L |
|---|
| 7299 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L |
|---|
| 7300 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L |
|---|
| 7301 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L |
|---|
| 7302 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L |
|---|
| 7303 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L |
|---|
| 7304 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L |
|---|
| 7305 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L |
|---|
| 7306 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L |
|---|
| 7307 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L |
|---|
| 7308 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L |
|---|
| 7309 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L |
|---|
| 7310 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L |
|---|
| 7311 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L |
|---|
| 7312 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L |
|---|
| 7313 | #define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L |
|---|
| 7314 | //VM_L2_SAW_PIPES_BUSY |
|---|
| 7315 | #define VM_L2_SAW_PIPES_BUSY__PIPES_BUSY__SHIFT 0x0 |
|---|
| 7316 | #define VM_L2_SAW_PIPES_BUSY__PIPES_BUSY_MASK 0xFFFFFFFFL |
|---|
| 7317 | |
|---|
| 7318 | |
|---|
| 7319 | // addressBlock: mmhub_utcl2_atcl2dec |
|---|
| 7320 | //ATC_L2_CNTL |
|---|
| 7321 | #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 |
|---|
| 7322 | #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 |
|---|
| 7323 | #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 |
|---|
| 7324 | #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 |
|---|
| 7325 | #define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8 |
|---|
| 7326 | #define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb |
|---|
| 7327 | #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L |
|---|
| 7328 | #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L |
|---|
| 7329 | #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L |
|---|
| 7330 | #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L |
|---|
| 7331 | #define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L |
|---|
| 7332 | #define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L |
|---|
| 7333 | //ATC_L2_CNTL2 |
|---|
| 7334 | #define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 |
|---|
| 7335 | #define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 |
|---|
| 7336 | #define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 |
|---|
| 7337 | #define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 |
|---|
| 7338 | #define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc |
|---|
| 7339 | #define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf |
|---|
| 7340 | #define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL |
|---|
| 7341 | #define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L |
|---|
| 7342 | #define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L |
|---|
| 7343 | #define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L |
|---|
| 7344 | #define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L |
|---|
| 7345 | #define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L |
|---|
| 7346 | //ATC_L2_CACHE_DATA0 |
|---|
| 7347 | #define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 |
|---|
| 7348 | #define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 |
|---|
| 7349 | #define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 |
|---|
| 7350 | #define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17 |
|---|
| 7351 | #define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L |
|---|
| 7352 | #define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L |
|---|
| 7353 | #define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL |
|---|
| 7354 | #define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L |
|---|
| 7355 | //ATC_L2_CACHE_DATA1 |
|---|
| 7356 | #define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 |
|---|
| 7357 | #define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL |
|---|
| 7358 | //ATC_L2_CACHE_DATA2 |
|---|
| 7359 | #define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 |
|---|
| 7360 | #define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL |
|---|
| 7361 | //ATC_L2_CNTL3 |
|---|
| 7362 | #define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0 |
|---|
| 7363 | #define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3 |
|---|
| 7364 | #define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L |
|---|
| 7365 | #define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L |
|---|
| 7366 | //ATC_L2_STATUS |
|---|
| 7367 | #define ATC_L2_STATUS__BUSY__SHIFT 0x0 |
|---|
| 7368 | #define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1 |
|---|
| 7369 | #define ATC_L2_STATUS__BUSY_MASK 0x00000001L |
|---|
| 7370 | #define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL |
|---|
| 7371 | //ATC_L2_STATUS2 |
|---|
| 7372 | #define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 |
|---|
| 7373 | #define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 |
|---|
| 7374 | #define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL |
|---|
| 7375 | #define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L |
|---|
| 7376 | //ATC_L2_MISC_CG |
|---|
| 7377 | #define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 |
|---|
| 7378 | #define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 |
|---|
| 7379 | #define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 |
|---|
| 7380 | #define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L |
|---|
| 7381 | #define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L |
|---|
| 7382 | #define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L |
|---|
| 7383 | //ATC_L2_MEM_POWER_LS |
|---|
| 7384 | #define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 |
|---|
| 7385 | #define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 |
|---|
| 7386 | #define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL |
|---|
| 7387 | #define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L |
|---|
| 7388 | //ATC_L2_CGTT_CLK_CTRL |
|---|
| 7389 | #define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
|---|
| 7390 | #define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
|---|
| 7391 | #define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
|---|
| 7392 | #define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 |
|---|
| 7393 | #define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 |
|---|
| 7394 | #define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
|---|
| 7395 | #define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
|---|
| 7396 | #define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
|---|
| 7397 | #define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L |
|---|
| 7398 | #define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L |
|---|
| 7399 | |
|---|
| 7400 | |
|---|
| 7401 | // addressBlock: mmhub_utcl2_vml2pfdec |
|---|
| 7402 | //VM_L2_CNTL |
|---|
| 7403 | #define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 |
|---|
| 7404 | #define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 |
|---|
| 7405 | #define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 |
|---|
| 7406 | #define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 |
|---|
| 7407 | #define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 |
|---|
| 7408 | #define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 |
|---|
| 7409 | #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa |
|---|
| 7410 | #define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb |
|---|
| 7411 | #define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc |
|---|
| 7412 | #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf |
|---|
| 7413 | #define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 |
|---|
| 7414 | #define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 |
|---|
| 7415 | #define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 |
|---|
| 7416 | #define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a |
|---|
| 7417 | #define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L |
|---|
| 7418 | #define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L |
|---|
| 7419 | #define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL |
|---|
| 7420 | #define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L |
|---|
| 7421 | #define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L |
|---|
| 7422 | #define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L |
|---|
| 7423 | #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L |
|---|
| 7424 | #define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L |
|---|
| 7425 | #define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L |
|---|
| 7426 | #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L |
|---|
| 7427 | #define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L |
|---|
| 7428 | #define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L |
|---|
| 7429 | #define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L |
|---|
| 7430 | #define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L |
|---|
| 7431 | //VM_L2_CNTL2 |
|---|
| 7432 | #define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 |
|---|
| 7433 | #define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 |
|---|
| 7434 | #define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 |
|---|
| 7435 | #define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 |
|---|
| 7436 | #define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 |
|---|
| 7437 | #define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a |
|---|
| 7438 | #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c |
|---|
| 7439 | #define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L |
|---|
| 7440 | #define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L |
|---|
| 7441 | #define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L |
|---|
| 7442 | #define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L |
|---|
| 7443 | #define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L |
|---|
| 7444 | #define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L |
|---|
| 7445 | #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L |
|---|
| 7446 | //VM_L2_CNTL3 |
|---|
| 7447 | #define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 |
|---|
| 7448 | #define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 |
|---|
| 7449 | #define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 |
|---|
| 7450 | #define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf |
|---|
| 7451 | #define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 |
|---|
| 7452 | #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 |
|---|
| 7453 | #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 |
|---|
| 7454 | #define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c |
|---|
| 7455 | #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d |
|---|
| 7456 | #define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e |
|---|
| 7457 | #define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f |
|---|
| 7458 | #define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL |
|---|
| 7459 | #define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L |
|---|
| 7460 | #define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L |
|---|
| 7461 | #define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L |
|---|
| 7462 | #define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L |
|---|
| 7463 | #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L |
|---|
| 7464 | #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L |
|---|
| 7465 | #define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L |
|---|
| 7466 | #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L |
|---|
| 7467 | #define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L |
|---|
| 7468 | #define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L |
|---|
| 7469 | //VM_L2_STATUS |
|---|
| 7470 | #define VM_L2_STATUS__L2_BUSY__SHIFT 0x0 |
|---|
| 7471 | #define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 |
|---|
| 7472 | #define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 |
|---|
| 7473 | #define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 |
|---|
| 7474 | #define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 |
|---|
| 7475 | #define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 |
|---|
| 7476 | #define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 |
|---|
| 7477 | #define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L |
|---|
| 7478 | #define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL |
|---|
| 7479 | #define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L |
|---|
| 7480 | #define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L |
|---|
| 7481 | #define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L |
|---|
| 7482 | #define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L |
|---|
| 7483 | #define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L |
|---|
| 7484 | //VM_DUMMY_PAGE_FAULT_CNTL |
|---|
| 7485 | #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 |
|---|
| 7486 | #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 |
|---|
| 7487 | #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 |
|---|
| 7488 | #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L |
|---|
| 7489 | #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L |
|---|
| 7490 | #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL |
|---|
| 7491 | //VM_DUMMY_PAGE_FAULT_ADDR_LO32 |
|---|
| 7492 | #define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 |
|---|
| 7493 | #define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL |
|---|
| 7494 | //VM_DUMMY_PAGE_FAULT_ADDR_HI32 |
|---|
| 7495 | #define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 |
|---|
| 7496 | #define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL |
|---|
| 7497 | //VM_L2_PROTECTION_FAULT_CNTL |
|---|
| 7498 | #define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 |
|---|
| 7499 | #define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 |
|---|
| 7500 | #define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 |
|---|
| 7501 | #define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 |
|---|
| 7502 | #define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 |
|---|
| 7503 | #define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 |
|---|
| 7504 | #define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 |
|---|
| 7505 | #define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 |
|---|
| 7506 | #define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 |
|---|
| 7507 | #define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 |
|---|
| 7508 | #define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
|---|
| 7509 | #define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb |
|---|
| 7510 | #define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
|---|
| 7511 | #define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd |
|---|
| 7512 | #define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d |
|---|
| 7513 | #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e |
|---|
| 7514 | #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f |
|---|
| 7515 | #define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L |
|---|
| 7516 | #define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L |
|---|
| 7517 | #define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L |
|---|
| 7518 | #define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L |
|---|
| 7519 | #define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L |
|---|
| 7520 | #define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L |
|---|
| 7521 | #define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L |
|---|
| 7522 | #define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L |
|---|
| 7523 | #define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L |
|---|
| 7524 | #define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L |
|---|
| 7525 | #define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
|---|
| 7526 | #define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L |
|---|
| 7527 | #define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
|---|
| 7528 | #define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L |
|---|
| 7529 | #define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L |
|---|
| 7530 | #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L |
|---|
| 7531 | #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L |
|---|
| 7532 | //VM_L2_PROTECTION_FAULT_CNTL2 |
|---|
| 7533 | #define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 |
|---|
| 7534 | #define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 |
|---|
| 7535 | #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 |
|---|
| 7536 | #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 |
|---|
| 7537 | #define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 |
|---|
| 7538 | #define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL |
|---|
| 7539 | #define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L |
|---|
| 7540 | #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L |
|---|
| 7541 | #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L |
|---|
| 7542 | #define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L |
|---|
| 7543 | //VM_L2_PROTECTION_FAULT_MM_CNTL3 |
|---|
| 7544 | #define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 |
|---|
| 7545 | #define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL |
|---|
| 7546 | //VM_L2_PROTECTION_FAULT_MM_CNTL4 |
|---|
| 7547 | #define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 |
|---|
| 7548 | #define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL |
|---|
| 7549 | //VM_L2_PROTECTION_FAULT_STATUS |
|---|
| 7550 | #define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 |
|---|
| 7551 | #define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 |
|---|
| 7552 | #define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 |
|---|
| 7553 | #define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 |
|---|
| 7554 | #define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 |
|---|
| 7555 | #define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 |
|---|
| 7556 | #define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 |
|---|
| 7557 | #define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 |
|---|
| 7558 | #define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 |
|---|
| 7559 | #define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 |
|---|
| 7560 | #define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L |
|---|
| 7561 | #define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL |
|---|
| 7562 | #define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L |
|---|
| 7563 | #define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L |
|---|
| 7564 | #define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L |
|---|
| 7565 | #define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L |
|---|
| 7566 | #define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L |
|---|
| 7567 | #define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L |
|---|
| 7568 | #define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L |
|---|
| 7569 | #define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L |
|---|
| 7570 | //VM_L2_PROTECTION_FAULT_ADDR_LO32 |
|---|
| 7571 | #define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 |
|---|
| 7572 | #define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL |
|---|
| 7573 | //VM_L2_PROTECTION_FAULT_ADDR_HI32 |
|---|
| 7574 | #define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 |
|---|
| 7575 | #define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL |
|---|
| 7576 | //VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 |
|---|
| 7577 | #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 |
|---|
| 7578 | #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL |
|---|
| 7579 | //VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 |
|---|
| 7580 | #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 |
|---|
| 7581 | #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL |
|---|
| 7582 | //VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 |
|---|
| 7583 | #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 7584 | #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 7585 | //VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 |
|---|
| 7586 | #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 7587 | #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 7588 | //VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 |
|---|
| 7589 | #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 7590 | #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 7591 | //VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 |
|---|
| 7592 | #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 7593 | #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 7594 | //VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 |
|---|
| 7595 | #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 |
|---|
| 7596 | #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL |
|---|
| 7597 | //VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 |
|---|
| 7598 | #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 |
|---|
| 7599 | #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL |
|---|
| 7600 | //VM_L2_CNTL4 |
|---|
| 7601 | #define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 |
|---|
| 7602 | #define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 |
|---|
| 7603 | #define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 |
|---|
| 7604 | #define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 |
|---|
| 7605 | #define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 |
|---|
| 7606 | #define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c |
|---|
| 7607 | #define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL |
|---|
| 7608 | #define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L |
|---|
| 7609 | #define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L |
|---|
| 7610 | #define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L |
|---|
| 7611 | #define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L |
|---|
| 7612 | #define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L |
|---|
| 7613 | //VM_L2_MM_GROUP_RT_CLASSES |
|---|
| 7614 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 |
|---|
| 7615 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 |
|---|
| 7616 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 |
|---|
| 7617 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 |
|---|
| 7618 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 |
|---|
| 7619 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 |
|---|
| 7620 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 |
|---|
| 7621 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 |
|---|
| 7622 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 |
|---|
| 7623 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 |
|---|
| 7624 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa |
|---|
| 7625 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb |
|---|
| 7626 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc |
|---|
| 7627 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd |
|---|
| 7628 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe |
|---|
| 7629 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf |
|---|
| 7630 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 |
|---|
| 7631 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 |
|---|
| 7632 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 |
|---|
| 7633 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 |
|---|
| 7634 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 |
|---|
| 7635 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 |
|---|
| 7636 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 |
|---|
| 7637 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 |
|---|
| 7638 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 |
|---|
| 7639 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 |
|---|
| 7640 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a |
|---|
| 7641 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b |
|---|
| 7642 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c |
|---|
| 7643 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d |
|---|
| 7644 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e |
|---|
| 7645 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f |
|---|
| 7646 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L |
|---|
| 7647 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L |
|---|
| 7648 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L |
|---|
| 7649 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L |
|---|
| 7650 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L |
|---|
| 7651 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L |
|---|
| 7652 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L |
|---|
| 7653 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L |
|---|
| 7654 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L |
|---|
| 7655 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L |
|---|
| 7656 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L |
|---|
| 7657 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L |
|---|
| 7658 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L |
|---|
| 7659 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L |
|---|
| 7660 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L |
|---|
| 7661 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L |
|---|
| 7662 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L |
|---|
| 7663 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L |
|---|
| 7664 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L |
|---|
| 7665 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L |
|---|
| 7666 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L |
|---|
| 7667 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L |
|---|
| 7668 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L |
|---|
| 7669 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L |
|---|
| 7670 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L |
|---|
| 7671 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L |
|---|
| 7672 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L |
|---|
| 7673 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L |
|---|
| 7674 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L |
|---|
| 7675 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L |
|---|
| 7676 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L |
|---|
| 7677 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L |
|---|
| 7678 | //VM_L2_BANK_SELECT_RESERVED_CID |
|---|
| 7679 | #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 |
|---|
| 7680 | #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa |
|---|
| 7681 | #define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 |
|---|
| 7682 | #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 |
|---|
| 7683 | #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 |
|---|
| 7684 | #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL |
|---|
| 7685 | #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L |
|---|
| 7686 | #define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L |
|---|
| 7687 | #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L |
|---|
| 7688 | #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L |
|---|
| 7689 | //VM_L2_BANK_SELECT_RESERVED_CID2 |
|---|
| 7690 | #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 |
|---|
| 7691 | #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa |
|---|
| 7692 | #define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 |
|---|
| 7693 | #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 |
|---|
| 7694 | #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 |
|---|
| 7695 | #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL |
|---|
| 7696 | #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L |
|---|
| 7697 | #define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L |
|---|
| 7698 | #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L |
|---|
| 7699 | #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L |
|---|
| 7700 | //VM_L2_CACHE_PARITY_CNTL |
|---|
| 7701 | #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 |
|---|
| 7702 | #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 |
|---|
| 7703 | #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 |
|---|
| 7704 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 |
|---|
| 7705 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 |
|---|
| 7706 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 |
|---|
| 7707 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 |
|---|
| 7708 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 |
|---|
| 7709 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc |
|---|
| 7710 | #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L |
|---|
| 7711 | #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L |
|---|
| 7712 | #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L |
|---|
| 7713 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L |
|---|
| 7714 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L |
|---|
| 7715 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L |
|---|
| 7716 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L |
|---|
| 7717 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L |
|---|
| 7718 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L |
|---|
| 7719 | //VM_L2_CGTT_CLK_CTRL |
|---|
| 7720 | #define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
|---|
| 7721 | #define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
|---|
| 7722 | #define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
|---|
| 7723 | #define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 |
|---|
| 7724 | #define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 |
|---|
| 7725 | #define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
|---|
| 7726 | #define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
|---|
| 7727 | #define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
|---|
| 7728 | #define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L |
|---|
| 7729 | #define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L |
|---|
| 7730 | |
|---|
| 7731 | |
|---|
| 7732 | // addressBlock: mmhub_utcl2_vml2vcdec |
|---|
| 7733 | //VM_CONTEXT0_CNTL |
|---|
| 7734 | #define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
|---|
| 7735 | #define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
|---|
| 7736 | #define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
|---|
| 7737 | #define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
|---|
| 7738 | #define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
|---|
| 7739 | #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
|---|
| 7740 | #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
|---|
| 7741 | #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
|---|
| 7742 | #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
|---|
| 7743 | #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
|---|
| 7744 | #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
|---|
| 7745 | #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
|---|
| 7746 | #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
|---|
| 7747 | #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
|---|
| 7748 | #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
|---|
| 7749 | #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
|---|
| 7750 | #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
|---|
| 7751 | #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
|---|
| 7752 | #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
|---|
| 7753 | #define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
|---|
| 7754 | #define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
|---|
| 7755 | #define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
|---|
| 7756 | #define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
|---|
| 7757 | #define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
|---|
| 7758 | #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
|---|
| 7759 | #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
|---|
| 7760 | #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
|---|
| 7761 | #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
|---|
| 7762 | #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
|---|
| 7763 | #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
|---|
| 7764 | #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
|---|
| 7765 | #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
|---|
| 7766 | #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
|---|
| 7767 | #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
|---|
| 7768 | #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
|---|
| 7769 | #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
|---|
| 7770 | #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
|---|
| 7771 | #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
|---|
| 7772 | //VM_CONTEXT1_CNTL |
|---|
| 7773 | #define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
|---|
| 7774 | #define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
|---|
| 7775 | #define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
|---|
| 7776 | #define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
|---|
| 7777 | #define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
|---|
| 7778 | #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
|---|
| 7779 | #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
|---|
| 7780 | #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
|---|
| 7781 | #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
|---|
| 7782 | #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
|---|
| 7783 | #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
|---|
| 7784 | #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
|---|
| 7785 | #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
|---|
| 7786 | #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
|---|
| 7787 | #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
|---|
| 7788 | #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
|---|
| 7789 | #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
|---|
| 7790 | #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
|---|
| 7791 | #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
|---|
| 7792 | #define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
|---|
| 7793 | #define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
|---|
| 7794 | #define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
|---|
| 7795 | #define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
|---|
| 7796 | #define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
|---|
| 7797 | #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
|---|
| 7798 | #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
|---|
| 7799 | #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
|---|
| 7800 | #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
|---|
| 7801 | #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
|---|
| 7802 | #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
|---|
| 7803 | #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
|---|
| 7804 | #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
|---|
| 7805 | #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
|---|
| 7806 | #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
|---|
| 7807 | #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
|---|
| 7808 | #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
|---|
| 7809 | #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
|---|
| 7810 | #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
|---|
| 7811 | //VM_CONTEXT2_CNTL |
|---|
| 7812 | #define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
|---|
| 7813 | #define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
|---|
| 7814 | #define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
|---|
| 7815 | #define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
|---|
| 7816 | #define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
|---|
| 7817 | #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
|---|
| 7818 | #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
|---|
| 7819 | #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
|---|
| 7820 | #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
|---|
| 7821 | #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
|---|
| 7822 | #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
|---|
| 7823 | #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
|---|
| 7824 | #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
|---|
| 7825 | #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
|---|
| 7826 | #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
|---|
| 7827 | #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
|---|
| 7828 | #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
|---|
| 7829 | #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
|---|
| 7830 | #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
|---|
| 7831 | #define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
|---|
| 7832 | #define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
|---|
| 7833 | #define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
|---|
| 7834 | #define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
|---|
| 7835 | #define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
|---|
| 7836 | #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
|---|
| 7837 | #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
|---|
| 7838 | #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
|---|
| 7839 | #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
|---|
| 7840 | #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
|---|
| 7841 | #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
|---|
| 7842 | #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
|---|
| 7843 | #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
|---|
| 7844 | #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
|---|
| 7845 | #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
|---|
| 7846 | #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
|---|
| 7847 | #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
|---|
| 7848 | #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
|---|
| 7849 | #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
|---|
| 7850 | //VM_CONTEXT3_CNTL |
|---|
| 7851 | #define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
|---|
| 7852 | #define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
|---|
| 7853 | #define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
|---|
| 7854 | #define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
|---|
| 7855 | #define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
|---|
| 7856 | #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
|---|
| 7857 | #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
|---|
| 7858 | #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
|---|
| 7859 | #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
|---|
| 7860 | #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
|---|
| 7861 | #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
|---|
| 7862 | #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
|---|
| 7863 | #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
|---|
| 7864 | #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
|---|
| 7865 | #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
|---|
| 7866 | #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
|---|
| 7867 | #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
|---|
| 7868 | #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
|---|
| 7869 | #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
|---|
| 7870 | #define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
|---|
| 7871 | #define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
|---|
| 7872 | #define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
|---|
| 7873 | #define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
|---|
| 7874 | #define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
|---|
| 7875 | #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
|---|
| 7876 | #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
|---|
| 7877 | #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
|---|
| 7878 | #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
|---|
| 7879 | #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
|---|
| 7880 | #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
|---|
| 7881 | #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
|---|
| 7882 | #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
|---|
| 7883 | #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
|---|
| 7884 | #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
|---|
| 7885 | #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
|---|
| 7886 | #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
|---|
| 7887 | #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
|---|
| 7888 | #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
|---|
| 7889 | //VM_CONTEXT4_CNTL |
|---|
| 7890 | #define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
|---|
| 7891 | #define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
|---|
| 7892 | #define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
|---|
| 7893 | #define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
|---|
| 7894 | #define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
|---|
| 7895 | #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
|---|
| 7896 | #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
|---|
| 7897 | #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
|---|
| 7898 | #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
|---|
| 7899 | #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
|---|
| 7900 | #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
|---|
| 7901 | #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
|---|
| 7902 | #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
|---|
| 7903 | #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
|---|
| 7904 | #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
|---|
| 7905 | #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
|---|
| 7906 | #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
|---|
| 7907 | #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
|---|
| 7908 | #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
|---|
| 7909 | #define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
|---|
| 7910 | #define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
|---|
| 7911 | #define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
|---|
| 7912 | #define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
|---|
| 7913 | #define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
|---|
| 7914 | #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
|---|
| 7915 | #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
|---|
| 7916 | #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
|---|
| 7917 | #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
|---|
| 7918 | #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
|---|
| 7919 | #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
|---|
| 7920 | #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
|---|
| 7921 | #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
|---|
| 7922 | #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
|---|
| 7923 | #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
|---|
| 7924 | #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
|---|
| 7925 | #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
|---|
| 7926 | #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
|---|
| 7927 | #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
|---|
| 7928 | //VM_CONTEXT5_CNTL |
|---|
| 7929 | #define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
|---|
| 7930 | #define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
|---|
| 7931 | #define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
|---|
| 7932 | #define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
|---|
| 7933 | #define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
|---|
| 7934 | #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
|---|
| 7935 | #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
|---|
| 7936 | #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
|---|
| 7937 | #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
|---|
| 7938 | #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
|---|
| 7939 | #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
|---|
| 7940 | #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
|---|
| 7941 | #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
|---|
| 7942 | #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
|---|
| 7943 | #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
|---|
| 7944 | #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
|---|
| 7945 | #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
|---|
| 7946 | #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
|---|
| 7947 | #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
|---|
| 7948 | #define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
|---|
| 7949 | #define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
|---|
| 7950 | #define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
|---|
| 7951 | #define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
|---|
| 7952 | #define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
|---|
| 7953 | #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
|---|
| 7954 | #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
|---|
| 7955 | #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
|---|
| 7956 | #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
|---|
| 7957 | #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
|---|
| 7958 | #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
|---|
| 7959 | #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
|---|
| 7960 | #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
|---|
| 7961 | #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
|---|
| 7962 | #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
|---|
| 7963 | #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
|---|
| 7964 | #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
|---|
| 7965 | #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
|---|
| 7966 | #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
|---|
| 7967 | //VM_CONTEXT6_CNTL |
|---|
| 7968 | #define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
|---|
| 7969 | #define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
|---|
| 7970 | #define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
|---|
| 7971 | #define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
|---|
| 7972 | #define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
|---|
| 7973 | #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
|---|
| 7974 | #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
|---|
| 7975 | #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
|---|
| 7976 | #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
|---|
| 7977 | #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
|---|
| 7978 | #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
|---|
| 7979 | #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
|---|
| 7980 | #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
|---|
| 7981 | #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
|---|
| 7982 | #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
|---|
| 7983 | #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
|---|
| 7984 | #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
|---|
| 7985 | #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
|---|
| 7986 | #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
|---|
| 7987 | #define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
|---|
| 7988 | #define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
|---|
| 7989 | #define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
|---|
| 7990 | #define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
|---|
| 7991 | #define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
|---|
| 7992 | #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
|---|
| 7993 | #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
|---|
| 7994 | #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
|---|
| 7995 | #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
|---|
| 7996 | #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
|---|
| 7997 | #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
|---|
| 7998 | #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
|---|
| 7999 | #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
|---|
| 8000 | #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
|---|
| 8001 | #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
|---|
| 8002 | #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
|---|
| 8003 | #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
|---|
| 8004 | #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
|---|
| 8005 | #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
|---|
| 8006 | //VM_CONTEXT7_CNTL |
|---|
| 8007 | #define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
|---|
| 8008 | #define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
|---|
| 8009 | #define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
|---|
| 8010 | #define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
|---|
| 8011 | #define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
|---|
| 8012 | #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
|---|
| 8013 | #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
|---|
| 8014 | #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
|---|
| 8015 | #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
|---|
| 8016 | #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
|---|
| 8017 | #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
|---|
| 8018 | #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
|---|
| 8019 | #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
|---|
| 8020 | #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
|---|
| 8021 | #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
|---|
| 8022 | #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
|---|
| 8023 | #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
|---|
| 8024 | #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
|---|
| 8025 | #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
|---|
| 8026 | #define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
|---|
| 8027 | #define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
|---|
| 8028 | #define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
|---|
| 8029 | #define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
|---|
| 8030 | #define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
|---|
| 8031 | #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
|---|
| 8032 | #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
|---|
| 8033 | #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
|---|
| 8034 | #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
|---|
| 8035 | #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
|---|
| 8036 | #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
|---|
| 8037 | #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
|---|
| 8038 | #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
|---|
| 8039 | #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
|---|
| 8040 | #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
|---|
| 8041 | #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
|---|
| 8042 | #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
|---|
| 8043 | #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
|---|
| 8044 | #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
|---|
| 8045 | //VM_CONTEXT8_CNTL |
|---|
| 8046 | #define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
|---|
| 8047 | #define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
|---|
| 8048 | #define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
|---|
| 8049 | #define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
|---|
| 8050 | #define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
|---|
| 8051 | #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
|---|
| 8052 | #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
|---|
| 8053 | #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
|---|
| 8054 | #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
|---|
| 8055 | #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
|---|
| 8056 | #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
|---|
| 8057 | #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
|---|
| 8058 | #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
|---|
| 8059 | #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
|---|
| 8060 | #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
|---|
| 8061 | #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
|---|
| 8062 | #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
|---|
| 8063 | #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
|---|
| 8064 | #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
|---|
| 8065 | #define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
|---|
| 8066 | #define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
|---|
| 8067 | #define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
|---|
| 8068 | #define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
|---|
| 8069 | #define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
|---|
| 8070 | #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
|---|
| 8071 | #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
|---|
| 8072 | #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
|---|
| 8073 | #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
|---|
| 8074 | #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
|---|
| 8075 | #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
|---|
| 8076 | #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
|---|
| 8077 | #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
|---|
| 8078 | #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
|---|
| 8079 | #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
|---|
| 8080 | #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
|---|
| 8081 | #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
|---|
| 8082 | #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
|---|
| 8083 | #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
|---|
| 8084 | //VM_CONTEXT9_CNTL |
|---|
| 8085 | #define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
|---|
| 8086 | #define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
|---|
| 8087 | #define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
|---|
| 8088 | #define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
|---|
| 8089 | #define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
|---|
| 8090 | #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
|---|
| 8091 | #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
|---|
| 8092 | #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
|---|
| 8093 | #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
|---|
| 8094 | #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
|---|
| 8095 | #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
|---|
| 8096 | #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
|---|
| 8097 | #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
|---|
| 8098 | #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
|---|
| 8099 | #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
|---|
| 8100 | #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
|---|
| 8101 | #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
|---|
| 8102 | #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
|---|
| 8103 | #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
|---|
| 8104 | #define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
|---|
| 8105 | #define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
|---|
| 8106 | #define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
|---|
| 8107 | #define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
|---|
| 8108 | #define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
|---|
| 8109 | #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
|---|
| 8110 | #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
|---|
| 8111 | #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
|---|
| 8112 | #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
|---|
| 8113 | #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
|---|
| 8114 | #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
|---|
| 8115 | #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
|---|
| 8116 | #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
|---|
| 8117 | #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
|---|
| 8118 | #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
|---|
| 8119 | #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
|---|
| 8120 | #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
|---|
| 8121 | #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
|---|
| 8122 | #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
|---|
| 8123 | //VM_CONTEXT10_CNTL |
|---|
| 8124 | #define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
|---|
| 8125 | #define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
|---|
| 8126 | #define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
|---|
| 8127 | #define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
|---|
| 8128 | #define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
|---|
| 8129 | #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
|---|
| 8130 | #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
|---|
| 8131 | #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
|---|
| 8132 | #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
|---|
| 8133 | #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
|---|
| 8134 | #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
|---|
| 8135 | #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
|---|
| 8136 | #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
|---|
| 8137 | #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
|---|
| 8138 | #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
|---|
| 8139 | #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
|---|
| 8140 | #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
|---|
| 8141 | #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
|---|
| 8142 | #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
|---|
| 8143 | #define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
|---|
| 8144 | #define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
|---|
| 8145 | #define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
|---|
| 8146 | #define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
|---|
| 8147 | #define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
|---|
| 8148 | #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
|---|
| 8149 | #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
|---|
| 8150 | #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
|---|
| 8151 | #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
|---|
| 8152 | #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
|---|
| 8153 | #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
|---|
| 8154 | #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
|---|
| 8155 | #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
|---|
| 8156 | #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
|---|
| 8157 | #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
|---|
| 8158 | #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
|---|
| 8159 | #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
|---|
| 8160 | #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
|---|
| 8161 | #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
|---|
| 8162 | //VM_CONTEXT11_CNTL |
|---|
| 8163 | #define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
|---|
| 8164 | #define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
|---|
| 8165 | #define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
|---|
| 8166 | #define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
|---|
| 8167 | #define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
|---|
| 8168 | #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
|---|
| 8169 | #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
|---|
| 8170 | #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
|---|
| 8171 | #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
|---|
| 8172 | #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
|---|
| 8173 | #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
|---|
| 8174 | #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
|---|
| 8175 | #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
|---|
| 8176 | #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
|---|
| 8177 | #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
|---|
| 8178 | #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
|---|
| 8179 | #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
|---|
| 8180 | #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
|---|
| 8181 | #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
|---|
| 8182 | #define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
|---|
| 8183 | #define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
|---|
| 8184 | #define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
|---|
| 8185 | #define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
|---|
| 8186 | #define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
|---|
| 8187 | #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
|---|
| 8188 | #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
|---|
| 8189 | #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
|---|
| 8190 | #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
|---|
| 8191 | #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
|---|
| 8192 | #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
|---|
| 8193 | #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
|---|
| 8194 | #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
|---|
| 8195 | #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
|---|
| 8196 | #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
|---|
| 8197 | #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
|---|
| 8198 | #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
|---|
| 8199 | #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
|---|
| 8200 | #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
|---|
| 8201 | //VM_CONTEXT12_CNTL |
|---|
| 8202 | #define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
|---|
| 8203 | #define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
|---|
| 8204 | #define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
|---|
| 8205 | #define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
|---|
| 8206 | #define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
|---|
| 8207 | #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
|---|
| 8208 | #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
|---|
| 8209 | #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
|---|
| 8210 | #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
|---|
| 8211 | #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
|---|
| 8212 | #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
|---|
| 8213 | #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
|---|
| 8214 | #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
|---|
| 8215 | #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
|---|
| 8216 | #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
|---|
| 8217 | #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
|---|
| 8218 | #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
|---|
| 8219 | #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
|---|
| 8220 | #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
|---|
| 8221 | #define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
|---|
| 8222 | #define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
|---|
| 8223 | #define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
|---|
| 8224 | #define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
|---|
| 8225 | #define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
|---|
| 8226 | #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
|---|
| 8227 | #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
|---|
| 8228 | #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
|---|
| 8229 | #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
|---|
| 8230 | #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
|---|
| 8231 | #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
|---|
| 8232 | #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
|---|
| 8233 | #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
|---|
| 8234 | #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
|---|
| 8235 | #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
|---|
| 8236 | #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
|---|
| 8237 | #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
|---|
| 8238 | #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
|---|
| 8239 | #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
|---|
| 8240 | //VM_CONTEXT13_CNTL |
|---|
| 8241 | #define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
|---|
| 8242 | #define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
|---|
| 8243 | #define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
|---|
| 8244 | #define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
|---|
| 8245 | #define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
|---|
| 8246 | #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
|---|
| 8247 | #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
|---|
| 8248 | #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
|---|
| 8249 | #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
|---|
| 8250 | #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
|---|
| 8251 | #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
|---|
| 8252 | #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
|---|
| 8253 | #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
|---|
| 8254 | #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
|---|
| 8255 | #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
|---|
| 8256 | #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
|---|
| 8257 | #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
|---|
| 8258 | #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
|---|
| 8259 | #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
|---|
| 8260 | #define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
|---|
| 8261 | #define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
|---|
| 8262 | #define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
|---|
| 8263 | #define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
|---|
| 8264 | #define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
|---|
| 8265 | #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
|---|
| 8266 | #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
|---|
| 8267 | #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
|---|
| 8268 | #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
|---|
| 8269 | #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
|---|
| 8270 | #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
|---|
| 8271 | #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
|---|
| 8272 | #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
|---|
| 8273 | #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
|---|
| 8274 | #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
|---|
| 8275 | #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
|---|
| 8276 | #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
|---|
| 8277 | #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
|---|
| 8278 | #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
|---|
| 8279 | //VM_CONTEXT14_CNTL |
|---|
| 8280 | #define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
|---|
| 8281 | #define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
|---|
| 8282 | #define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
|---|
| 8283 | #define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
|---|
| 8284 | #define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
|---|
| 8285 | #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
|---|
| 8286 | #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
|---|
| 8287 | #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
|---|
| 8288 | #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
|---|
| 8289 | #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
|---|
| 8290 | #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
|---|
| 8291 | #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
|---|
| 8292 | #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
|---|
| 8293 | #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
|---|
| 8294 | #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
|---|
| 8295 | #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
|---|
| 8296 | #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
|---|
| 8297 | #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
|---|
| 8298 | #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
|---|
| 8299 | #define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
|---|
| 8300 | #define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
|---|
| 8301 | #define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
|---|
| 8302 | #define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
|---|
| 8303 | #define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
|---|
| 8304 | #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
|---|
| 8305 | #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
|---|
| 8306 | #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
|---|
| 8307 | #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
|---|
| 8308 | #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
|---|
| 8309 | #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
|---|
| 8310 | #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
|---|
| 8311 | #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
|---|
| 8312 | #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
|---|
| 8313 | #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
|---|
| 8314 | #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
|---|
| 8315 | #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
|---|
| 8316 | #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
|---|
| 8317 | #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
|---|
| 8318 | //VM_CONTEXT15_CNTL |
|---|
| 8319 | #define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
|---|
| 8320 | #define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
|---|
| 8321 | #define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
|---|
| 8322 | #define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
|---|
| 8323 | #define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
|---|
| 8324 | #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
|---|
| 8325 | #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
|---|
| 8326 | #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
|---|
| 8327 | #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
|---|
| 8328 | #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
|---|
| 8329 | #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
|---|
| 8330 | #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
|---|
| 8331 | #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
|---|
| 8332 | #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
|---|
| 8333 | #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
|---|
| 8334 | #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
|---|
| 8335 | #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
|---|
| 8336 | #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
|---|
| 8337 | #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
|---|
| 8338 | #define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
|---|
| 8339 | #define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
|---|
| 8340 | #define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
|---|
| 8341 | #define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
|---|
| 8342 | #define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
|---|
| 8343 | #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
|---|
| 8344 | #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
|---|
| 8345 | #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
|---|
| 8346 | #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
|---|
| 8347 | #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
|---|
| 8348 | #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
|---|
| 8349 | #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
|---|
| 8350 | #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
|---|
| 8351 | #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
|---|
| 8352 | #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
|---|
| 8353 | #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
|---|
| 8354 | #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
|---|
| 8355 | #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
|---|
| 8356 | #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
|---|
| 8357 | //VM_CONTEXTS_DISABLE |
|---|
| 8358 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 |
|---|
| 8359 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 |
|---|
| 8360 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 |
|---|
| 8361 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 |
|---|
| 8362 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 |
|---|
| 8363 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 |
|---|
| 8364 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 |
|---|
| 8365 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 |
|---|
| 8366 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 |
|---|
| 8367 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 |
|---|
| 8368 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa |
|---|
| 8369 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb |
|---|
| 8370 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc |
|---|
| 8371 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd |
|---|
| 8372 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe |
|---|
| 8373 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf |
|---|
| 8374 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L |
|---|
| 8375 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L |
|---|
| 8376 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L |
|---|
| 8377 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L |
|---|
| 8378 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L |
|---|
| 8379 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L |
|---|
| 8380 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L |
|---|
| 8381 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L |
|---|
| 8382 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L |
|---|
| 8383 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L |
|---|
| 8384 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L |
|---|
| 8385 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L |
|---|
| 8386 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L |
|---|
| 8387 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L |
|---|
| 8388 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L |
|---|
| 8389 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L |
|---|
| 8390 | //VM_INVALIDATE_ENG0_SEM |
|---|
| 8391 | #define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 |
|---|
| 8392 | #define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L |
|---|
| 8393 | //VM_INVALIDATE_ENG1_SEM |
|---|
| 8394 | #define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 |
|---|
| 8395 | #define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L |
|---|
| 8396 | //VM_INVALIDATE_ENG2_SEM |
|---|
| 8397 | #define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 |
|---|
| 8398 | #define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L |
|---|
| 8399 | //VM_INVALIDATE_ENG3_SEM |
|---|
| 8400 | #define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 |
|---|
| 8401 | #define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L |
|---|
| 8402 | //VM_INVALIDATE_ENG4_SEM |
|---|
| 8403 | #define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 |
|---|
| 8404 | #define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L |
|---|
| 8405 | //VM_INVALIDATE_ENG5_SEM |
|---|
| 8406 | #define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 |
|---|
| 8407 | #define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L |
|---|
| 8408 | //VM_INVALIDATE_ENG6_SEM |
|---|
| 8409 | #define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 |
|---|
| 8410 | #define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L |
|---|
| 8411 | //VM_INVALIDATE_ENG7_SEM |
|---|
| 8412 | #define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 |
|---|
| 8413 | #define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L |
|---|
| 8414 | //VM_INVALIDATE_ENG8_SEM |
|---|
| 8415 | #define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 |
|---|
| 8416 | #define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L |
|---|
| 8417 | //VM_INVALIDATE_ENG9_SEM |
|---|
| 8418 | #define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 |
|---|
| 8419 | #define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L |
|---|
| 8420 | //VM_INVALIDATE_ENG10_SEM |
|---|
| 8421 | #define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 |
|---|
| 8422 | #define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L |
|---|
| 8423 | //VM_INVALIDATE_ENG11_SEM |
|---|
| 8424 | #define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 |
|---|
| 8425 | #define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L |
|---|
| 8426 | //VM_INVALIDATE_ENG12_SEM |
|---|
| 8427 | #define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 |
|---|
| 8428 | #define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L |
|---|
| 8429 | //VM_INVALIDATE_ENG13_SEM |
|---|
| 8430 | #define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 |
|---|
| 8431 | #define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L |
|---|
| 8432 | //VM_INVALIDATE_ENG14_SEM |
|---|
| 8433 | #define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 |
|---|
| 8434 | #define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L |
|---|
| 8435 | //VM_INVALIDATE_ENG15_SEM |
|---|
| 8436 | #define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 |
|---|
| 8437 | #define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L |
|---|
| 8438 | //VM_INVALIDATE_ENG16_SEM |
|---|
| 8439 | #define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 |
|---|
| 8440 | #define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L |
|---|
| 8441 | //VM_INVALIDATE_ENG17_SEM |
|---|
| 8442 | #define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 |
|---|
| 8443 | #define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L |
|---|
| 8444 | //VM_INVALIDATE_ENG0_REQ |
|---|
| 8445 | #define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
|---|
| 8446 | #define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 |
|---|
| 8447 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
|---|
| 8448 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
|---|
| 8449 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
|---|
| 8450 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
|---|
| 8451 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
|---|
| 8452 | #define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
|---|
| 8453 | #define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
|---|
| 8454 | #define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L |
|---|
| 8455 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
|---|
| 8456 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
|---|
| 8457 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
|---|
| 8458 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
|---|
| 8459 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
|---|
| 8460 | #define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
|---|
| 8461 | //VM_INVALIDATE_ENG1_REQ |
|---|
| 8462 | #define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
|---|
| 8463 | #define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 |
|---|
| 8464 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
|---|
| 8465 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
|---|
| 8466 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
|---|
| 8467 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
|---|
| 8468 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
|---|
| 8469 | #define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
|---|
| 8470 | #define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
|---|
| 8471 | #define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L |
|---|
| 8472 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
|---|
| 8473 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
|---|
| 8474 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
|---|
| 8475 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
|---|
| 8476 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
|---|
| 8477 | #define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
|---|
| 8478 | //VM_INVALIDATE_ENG2_REQ |
|---|
| 8479 | #define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
|---|
| 8480 | #define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 |
|---|
| 8481 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
|---|
| 8482 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
|---|
| 8483 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
|---|
| 8484 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
|---|
| 8485 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
|---|
| 8486 | #define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
|---|
| 8487 | #define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
|---|
| 8488 | #define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L |
|---|
| 8489 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
|---|
| 8490 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
|---|
| 8491 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
|---|
| 8492 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
|---|
| 8493 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
|---|
| 8494 | #define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
|---|
| 8495 | //VM_INVALIDATE_ENG3_REQ |
|---|
| 8496 | #define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
|---|
| 8497 | #define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 |
|---|
| 8498 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
|---|
| 8499 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
|---|
| 8500 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
|---|
| 8501 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
|---|
| 8502 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
|---|
| 8503 | #define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
|---|
| 8504 | #define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
|---|
| 8505 | #define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L |
|---|
| 8506 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
|---|
| 8507 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
|---|
| 8508 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
|---|
| 8509 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
|---|
| 8510 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
|---|
| 8511 | #define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
|---|
| 8512 | //VM_INVALIDATE_ENG4_REQ |
|---|
| 8513 | #define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
|---|
| 8514 | #define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 |
|---|
| 8515 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
|---|
| 8516 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
|---|
| 8517 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
|---|
| 8518 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
|---|
| 8519 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
|---|
| 8520 | #define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
|---|
| 8521 | #define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
|---|
| 8522 | #define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L |
|---|
| 8523 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
|---|
| 8524 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
|---|
| 8525 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
|---|
| 8526 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
|---|
| 8527 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
|---|
| 8528 | #define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
|---|
| 8529 | //VM_INVALIDATE_ENG5_REQ |
|---|
| 8530 | #define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
|---|
| 8531 | #define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 |
|---|
| 8532 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
|---|
| 8533 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
|---|
| 8534 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
|---|
| 8535 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
|---|
| 8536 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
|---|
| 8537 | #define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
|---|
| 8538 | #define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
|---|
| 8539 | #define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L |
|---|
| 8540 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
|---|
| 8541 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
|---|
| 8542 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
|---|
| 8543 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
|---|
| 8544 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
|---|
| 8545 | #define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
|---|
| 8546 | //VM_INVALIDATE_ENG6_REQ |
|---|
| 8547 | #define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
|---|
| 8548 | #define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 |
|---|
| 8549 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
|---|
| 8550 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
|---|
| 8551 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
|---|
| 8552 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
|---|
| 8553 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
|---|
| 8554 | #define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
|---|
| 8555 | #define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
|---|
| 8556 | #define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L |
|---|
| 8557 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
|---|
| 8558 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
|---|
| 8559 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
|---|
| 8560 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
|---|
| 8561 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
|---|
| 8562 | #define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
|---|
| 8563 | //VM_INVALIDATE_ENG7_REQ |
|---|
| 8564 | #define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
|---|
| 8565 | #define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 |
|---|
| 8566 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
|---|
| 8567 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
|---|
| 8568 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
|---|
| 8569 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
|---|
| 8570 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
|---|
| 8571 | #define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
|---|
| 8572 | #define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
|---|
| 8573 | #define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L |
|---|
| 8574 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
|---|
| 8575 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
|---|
| 8576 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
|---|
| 8577 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
|---|
| 8578 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
|---|
| 8579 | #define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
|---|
| 8580 | //VM_INVALIDATE_ENG8_REQ |
|---|
| 8581 | #define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
|---|
| 8582 | #define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 |
|---|
| 8583 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
|---|
| 8584 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
|---|
| 8585 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
|---|
| 8586 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
|---|
| 8587 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
|---|
| 8588 | #define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
|---|
| 8589 | #define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
|---|
| 8590 | #define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L |
|---|
| 8591 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
|---|
| 8592 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
|---|
| 8593 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
|---|
| 8594 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
|---|
| 8595 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
|---|
| 8596 | #define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
|---|
| 8597 | //VM_INVALIDATE_ENG9_REQ |
|---|
| 8598 | #define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
|---|
| 8599 | #define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 |
|---|
| 8600 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
|---|
| 8601 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
|---|
| 8602 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
|---|
| 8603 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
|---|
| 8604 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
|---|
| 8605 | #define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
|---|
| 8606 | #define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
|---|
| 8607 | #define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L |
|---|
| 8608 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
|---|
| 8609 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
|---|
| 8610 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
|---|
| 8611 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
|---|
| 8612 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
|---|
| 8613 | #define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
|---|
| 8614 | //VM_INVALIDATE_ENG10_REQ |
|---|
| 8615 | #define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
|---|
| 8616 | #define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 |
|---|
| 8617 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
|---|
| 8618 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
|---|
| 8619 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
|---|
| 8620 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
|---|
| 8621 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
|---|
| 8622 | #define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
|---|
| 8623 | #define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
|---|
| 8624 | #define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L |
|---|
| 8625 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
|---|
| 8626 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
|---|
| 8627 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
|---|
| 8628 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
|---|
| 8629 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
|---|
| 8630 | #define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
|---|
| 8631 | //VM_INVALIDATE_ENG11_REQ |
|---|
| 8632 | #define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
|---|
| 8633 | #define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 |
|---|
| 8634 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
|---|
| 8635 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
|---|
| 8636 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
|---|
| 8637 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
|---|
| 8638 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
|---|
| 8639 | #define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
|---|
| 8640 | #define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
|---|
| 8641 | #define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L |
|---|
| 8642 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
|---|
| 8643 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
|---|
| 8644 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
|---|
| 8645 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
|---|
| 8646 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
|---|
| 8647 | #define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
|---|
| 8648 | //VM_INVALIDATE_ENG12_REQ |
|---|
| 8649 | #define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
|---|
| 8650 | #define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 |
|---|
| 8651 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
|---|
| 8652 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
|---|
| 8653 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
|---|
| 8654 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
|---|
| 8655 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
|---|
| 8656 | #define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
|---|
| 8657 | #define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
|---|
| 8658 | #define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L |
|---|
| 8659 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
|---|
| 8660 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
|---|
| 8661 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
|---|
| 8662 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
|---|
| 8663 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
|---|
| 8664 | #define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
|---|
| 8665 | //VM_INVALIDATE_ENG13_REQ |
|---|
| 8666 | #define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
|---|
| 8667 | #define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 |
|---|
| 8668 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
|---|
| 8669 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
|---|
| 8670 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
|---|
| 8671 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
|---|
| 8672 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
|---|
| 8673 | #define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
|---|
| 8674 | #define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
|---|
| 8675 | #define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L |
|---|
| 8676 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
|---|
| 8677 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
|---|
| 8678 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
|---|
| 8679 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
|---|
| 8680 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
|---|
| 8681 | #define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
|---|
| 8682 | //VM_INVALIDATE_ENG14_REQ |
|---|
| 8683 | #define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
|---|
| 8684 | #define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 |
|---|
| 8685 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
|---|
| 8686 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
|---|
| 8687 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
|---|
| 8688 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
|---|
| 8689 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
|---|
| 8690 | #define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
|---|
| 8691 | #define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
|---|
| 8692 | #define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L |
|---|
| 8693 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
|---|
| 8694 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
|---|
| 8695 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
|---|
| 8696 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
|---|
| 8697 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
|---|
| 8698 | #define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
|---|
| 8699 | //VM_INVALIDATE_ENG15_REQ |
|---|
| 8700 | #define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
|---|
| 8701 | #define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 |
|---|
| 8702 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
|---|
| 8703 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
|---|
| 8704 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
|---|
| 8705 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
|---|
| 8706 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
|---|
| 8707 | #define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
|---|
| 8708 | #define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
|---|
| 8709 | #define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L |
|---|
| 8710 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
|---|
| 8711 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
|---|
| 8712 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
|---|
| 8713 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
|---|
| 8714 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
|---|
| 8715 | #define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
|---|
| 8716 | //VM_INVALIDATE_ENG16_REQ |
|---|
| 8717 | #define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
|---|
| 8718 | #define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 |
|---|
| 8719 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
|---|
| 8720 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
|---|
| 8721 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
|---|
| 8722 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
|---|
| 8723 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
|---|
| 8724 | #define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
|---|
| 8725 | #define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
|---|
| 8726 | #define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L |
|---|
| 8727 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
|---|
| 8728 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
|---|
| 8729 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
|---|
| 8730 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
|---|
| 8731 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
|---|
| 8732 | #define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
|---|
| 8733 | //VM_INVALIDATE_ENG17_REQ |
|---|
| 8734 | #define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
|---|
| 8735 | #define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 |
|---|
| 8736 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
|---|
| 8737 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
|---|
| 8738 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
|---|
| 8739 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
|---|
| 8740 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
|---|
| 8741 | #define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
|---|
| 8742 | #define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
|---|
| 8743 | #define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L |
|---|
| 8744 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
|---|
| 8745 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
|---|
| 8746 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
|---|
| 8747 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
|---|
| 8748 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
|---|
| 8749 | #define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
|---|
| 8750 | //VM_INVALIDATE_ENG0_ACK |
|---|
| 8751 | #define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
|---|
| 8752 | #define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 |
|---|
| 8753 | #define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
|---|
| 8754 | #define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L |
|---|
| 8755 | //VM_INVALIDATE_ENG1_ACK |
|---|
| 8756 | #define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
|---|
| 8757 | #define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 |
|---|
| 8758 | #define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
|---|
| 8759 | #define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L |
|---|
| 8760 | //VM_INVALIDATE_ENG2_ACK |
|---|
| 8761 | #define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
|---|
| 8762 | #define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 |
|---|
| 8763 | #define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
|---|
| 8764 | #define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L |
|---|
| 8765 | //VM_INVALIDATE_ENG3_ACK |
|---|
| 8766 | #define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
|---|
| 8767 | #define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 |
|---|
| 8768 | #define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
|---|
| 8769 | #define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L |
|---|
| 8770 | //VM_INVALIDATE_ENG4_ACK |
|---|
| 8771 | #define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
|---|
| 8772 | #define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 |
|---|
| 8773 | #define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
|---|
| 8774 | #define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L |
|---|
| 8775 | //VM_INVALIDATE_ENG5_ACK |
|---|
| 8776 | #define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
|---|
| 8777 | #define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 |
|---|
| 8778 | #define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
|---|
| 8779 | #define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L |
|---|
| 8780 | //VM_INVALIDATE_ENG6_ACK |
|---|
| 8781 | #define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
|---|
| 8782 | #define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 |
|---|
| 8783 | #define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
|---|
| 8784 | #define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L |
|---|
| 8785 | //VM_INVALIDATE_ENG7_ACK |
|---|
| 8786 | #define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
|---|
| 8787 | #define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 |
|---|
| 8788 | #define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
|---|
| 8789 | #define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L |
|---|
| 8790 | //VM_INVALIDATE_ENG8_ACK |
|---|
| 8791 | #define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
|---|
| 8792 | #define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 |
|---|
| 8793 | #define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
|---|
| 8794 | #define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L |
|---|
| 8795 | //VM_INVALIDATE_ENG9_ACK |
|---|
| 8796 | #define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
|---|
| 8797 | #define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 |
|---|
| 8798 | #define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
|---|
| 8799 | #define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L |
|---|
| 8800 | //VM_INVALIDATE_ENG10_ACK |
|---|
| 8801 | #define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
|---|
| 8802 | #define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 |
|---|
| 8803 | #define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
|---|
| 8804 | #define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L |
|---|
| 8805 | //VM_INVALIDATE_ENG11_ACK |
|---|
| 8806 | #define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
|---|
| 8807 | #define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 |
|---|
| 8808 | #define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
|---|
| 8809 | #define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L |
|---|
| 8810 | //VM_INVALIDATE_ENG12_ACK |
|---|
| 8811 | #define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
|---|
| 8812 | #define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 |
|---|
| 8813 | #define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
|---|
| 8814 | #define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L |
|---|
| 8815 | //VM_INVALIDATE_ENG13_ACK |
|---|
| 8816 | #define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
|---|
| 8817 | #define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 |
|---|
| 8818 | #define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
|---|
| 8819 | #define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L |
|---|
| 8820 | //VM_INVALIDATE_ENG14_ACK |
|---|
| 8821 | #define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
|---|
| 8822 | #define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 |
|---|
| 8823 | #define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
|---|
| 8824 | #define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L |
|---|
| 8825 | //VM_INVALIDATE_ENG15_ACK |
|---|
| 8826 | #define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
|---|
| 8827 | #define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 |
|---|
| 8828 | #define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
|---|
| 8829 | #define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L |
|---|
| 8830 | //VM_INVALIDATE_ENG16_ACK |
|---|
| 8831 | #define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
|---|
| 8832 | #define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 |
|---|
| 8833 | #define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
|---|
| 8834 | #define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L |
|---|
| 8835 | //VM_INVALIDATE_ENG17_ACK |
|---|
| 8836 | #define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
|---|
| 8837 | #define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 |
|---|
| 8838 | #define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
|---|
| 8839 | #define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L |
|---|
| 8840 | //VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 |
|---|
| 8841 | #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
|---|
| 8842 | #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
|---|
| 8843 | #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
|---|
| 8844 | #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
|---|
| 8845 | //VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 |
|---|
| 8846 | #define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
|---|
| 8847 | #define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
|---|
| 8848 | //VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 |
|---|
| 8849 | #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
|---|
| 8850 | #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
|---|
| 8851 | #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
|---|
| 8852 | #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
|---|
| 8853 | //VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 |
|---|
| 8854 | #define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
|---|
| 8855 | #define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
|---|
| 8856 | //VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 |
|---|
| 8857 | #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
|---|
| 8858 | #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
|---|
| 8859 | #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
|---|
| 8860 | #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
|---|
| 8861 | //VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 |
|---|
| 8862 | #define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
|---|
| 8863 | #define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
|---|
| 8864 | //VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 |
|---|
| 8865 | #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
|---|
| 8866 | #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
|---|
| 8867 | #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
|---|
| 8868 | #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
|---|
| 8869 | //VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 |
|---|
| 8870 | #define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
|---|
| 8871 | #define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
|---|
| 8872 | //VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 |
|---|
| 8873 | #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
|---|
| 8874 | #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
|---|
| 8875 | #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
|---|
| 8876 | #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
|---|
| 8877 | //VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 |
|---|
| 8878 | #define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
|---|
| 8879 | #define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
|---|
| 8880 | //VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 |
|---|
| 8881 | #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
|---|
| 8882 | #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
|---|
| 8883 | #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
|---|
| 8884 | #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
|---|
| 8885 | //VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 |
|---|
| 8886 | #define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
|---|
| 8887 | #define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
|---|
| 8888 | //VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 |
|---|
| 8889 | #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
|---|
| 8890 | #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
|---|
| 8891 | #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
|---|
| 8892 | #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
|---|
| 8893 | //VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 |
|---|
| 8894 | #define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
|---|
| 8895 | #define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
|---|
| 8896 | //VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 |
|---|
| 8897 | #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
|---|
| 8898 | #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
|---|
| 8899 | #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
|---|
| 8900 | #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
|---|
| 8901 | //VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 |
|---|
| 8902 | #define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
|---|
| 8903 | #define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
|---|
| 8904 | //VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 |
|---|
| 8905 | #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
|---|
| 8906 | #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
|---|
| 8907 | #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
|---|
| 8908 | #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
|---|
| 8909 | //VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 |
|---|
| 8910 | #define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
|---|
| 8911 | #define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
|---|
| 8912 | //VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 |
|---|
| 8913 | #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
|---|
| 8914 | #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
|---|
| 8915 | #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
|---|
| 8916 | #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
|---|
| 8917 | //VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 |
|---|
| 8918 | #define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
|---|
| 8919 | #define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
|---|
| 8920 | //VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 |
|---|
| 8921 | #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
|---|
| 8922 | #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
|---|
| 8923 | #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
|---|
| 8924 | #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
|---|
| 8925 | //VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 |
|---|
| 8926 | #define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
|---|
| 8927 | #define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
|---|
| 8928 | //VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 |
|---|
| 8929 | #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
|---|
| 8930 | #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
|---|
| 8931 | #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
|---|
| 8932 | #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
|---|
| 8933 | //VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 |
|---|
| 8934 | #define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
|---|
| 8935 | #define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
|---|
| 8936 | //VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 |
|---|
| 8937 | #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
|---|
| 8938 | #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
|---|
| 8939 | #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
|---|
| 8940 | #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
|---|
| 8941 | //VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 |
|---|
| 8942 | #define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
|---|
| 8943 | #define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
|---|
| 8944 | //VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 |
|---|
| 8945 | #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
|---|
| 8946 | #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
|---|
| 8947 | #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
|---|
| 8948 | #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
|---|
| 8949 | //VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 |
|---|
| 8950 | #define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
|---|
| 8951 | #define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
|---|
| 8952 | //VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 |
|---|
| 8953 | #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
|---|
| 8954 | #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
|---|
| 8955 | #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
|---|
| 8956 | #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
|---|
| 8957 | //VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 |
|---|
| 8958 | #define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
|---|
| 8959 | #define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
|---|
| 8960 | //VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 |
|---|
| 8961 | #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
|---|
| 8962 | #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
|---|
| 8963 | #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
|---|
| 8964 | #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
|---|
| 8965 | //VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 |
|---|
| 8966 | #define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
|---|
| 8967 | #define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
|---|
| 8968 | //VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 |
|---|
| 8969 | #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
|---|
| 8970 | #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
|---|
| 8971 | #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
|---|
| 8972 | #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
|---|
| 8973 | //VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 |
|---|
| 8974 | #define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
|---|
| 8975 | #define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
|---|
| 8976 | //VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 |
|---|
| 8977 | #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
|---|
| 8978 | #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
|---|
| 8979 | #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
|---|
| 8980 | #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
|---|
| 8981 | //VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 |
|---|
| 8982 | #define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
|---|
| 8983 | #define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
|---|
| 8984 | //VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 |
|---|
| 8985 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
|---|
| 8986 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
|---|
| 8987 | //VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 |
|---|
| 8988 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
|---|
| 8989 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
|---|
| 8990 | //VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 |
|---|
| 8991 | #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
|---|
| 8992 | #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
|---|
| 8993 | //VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 |
|---|
| 8994 | #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
|---|
| 8995 | #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
|---|
| 8996 | //VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 |
|---|
| 8997 | #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
|---|
| 8998 | #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
|---|
| 8999 | //VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 |
|---|
| 9000 | #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
|---|
| 9001 | #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
|---|
| 9002 | //VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 |
|---|
| 9003 | #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
|---|
| 9004 | #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
|---|
| 9005 | //VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 |
|---|
| 9006 | #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
|---|
| 9007 | #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
|---|
| 9008 | //VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 |
|---|
| 9009 | #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
|---|
| 9010 | #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
|---|
| 9011 | //VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 |
|---|
| 9012 | #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
|---|
| 9013 | #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
|---|
| 9014 | //VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 |
|---|
| 9015 | #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
|---|
| 9016 | #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
|---|
| 9017 | //VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 |
|---|
| 9018 | #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
|---|
| 9019 | #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
|---|
| 9020 | //VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 |
|---|
| 9021 | #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
|---|
| 9022 | #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
|---|
| 9023 | //VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 |
|---|
| 9024 | #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
|---|
| 9025 | #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
|---|
| 9026 | //VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 |
|---|
| 9027 | #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
|---|
| 9028 | #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
|---|
| 9029 | //VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 |
|---|
| 9030 | #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
|---|
| 9031 | #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
|---|
| 9032 | //VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 |
|---|
| 9033 | #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
|---|
| 9034 | #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
|---|
| 9035 | //VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 |
|---|
| 9036 | #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
|---|
| 9037 | #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
|---|
| 9038 | //VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 |
|---|
| 9039 | #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
|---|
| 9040 | #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
|---|
| 9041 | //VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 |
|---|
| 9042 | #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
|---|
| 9043 | #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
|---|
| 9044 | //VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 |
|---|
| 9045 | #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
|---|
| 9046 | #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
|---|
| 9047 | //VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 |
|---|
| 9048 | #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
|---|
| 9049 | #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
|---|
| 9050 | //VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 |
|---|
| 9051 | #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
|---|
| 9052 | #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
|---|
| 9053 | //VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 |
|---|
| 9054 | #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
|---|
| 9055 | #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
|---|
| 9056 | //VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 |
|---|
| 9057 | #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
|---|
| 9058 | #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
|---|
| 9059 | //VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 |
|---|
| 9060 | #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
|---|
| 9061 | #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
|---|
| 9062 | //VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 |
|---|
| 9063 | #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
|---|
| 9064 | #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
|---|
| 9065 | //VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 |
|---|
| 9066 | #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
|---|
| 9067 | #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
|---|
| 9068 | //VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 |
|---|
| 9069 | #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
|---|
| 9070 | #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
|---|
| 9071 | //VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 |
|---|
| 9072 | #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
|---|
| 9073 | #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
|---|
| 9074 | //VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 |
|---|
| 9075 | #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
|---|
| 9076 | #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
|---|
| 9077 | //VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 |
|---|
| 9078 | #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
|---|
| 9079 | #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
|---|
| 9080 | //VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 |
|---|
| 9081 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9082 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9083 | //VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 |
|---|
| 9084 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9085 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9086 | //VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 |
|---|
| 9087 | #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9088 | #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9089 | //VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 |
|---|
| 9090 | #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9091 | #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9092 | //VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 |
|---|
| 9093 | #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9094 | #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9095 | //VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 |
|---|
| 9096 | #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9097 | #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9098 | //VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 |
|---|
| 9099 | #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9100 | #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9101 | //VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 |
|---|
| 9102 | #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9103 | #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9104 | //VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 |
|---|
| 9105 | #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9106 | #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9107 | //VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 |
|---|
| 9108 | #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9109 | #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9110 | //VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 |
|---|
| 9111 | #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9112 | #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9113 | //VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 |
|---|
| 9114 | #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9115 | #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9116 | //VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 |
|---|
| 9117 | #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9118 | #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9119 | //VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 |
|---|
| 9120 | #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9121 | #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9122 | //VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 |
|---|
| 9123 | #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9124 | #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9125 | //VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 |
|---|
| 9126 | #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9127 | #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9128 | //VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 |
|---|
| 9129 | #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9130 | #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9131 | //VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 |
|---|
| 9132 | #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9133 | #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9134 | //VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 |
|---|
| 9135 | #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9136 | #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9137 | //VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 |
|---|
| 9138 | #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9139 | #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9140 | //VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 |
|---|
| 9141 | #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9142 | #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9143 | //VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 |
|---|
| 9144 | #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9145 | #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9146 | //VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 |
|---|
| 9147 | #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9148 | #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9149 | //VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 |
|---|
| 9150 | #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9151 | #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9152 | //VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 |
|---|
| 9153 | #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9154 | #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9155 | //VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 |
|---|
| 9156 | #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9157 | #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9158 | //VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 |
|---|
| 9159 | #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9160 | #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9161 | //VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 |
|---|
| 9162 | #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9163 | #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9164 | //VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 |
|---|
| 9165 | #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9166 | #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9167 | //VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 |
|---|
| 9168 | #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9169 | #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9170 | //VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 |
|---|
| 9171 | #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9172 | #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9173 | //VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 |
|---|
| 9174 | #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9175 | #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9176 | //VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 |
|---|
| 9177 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9178 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9179 | //VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 |
|---|
| 9180 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9181 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9182 | //VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 |
|---|
| 9183 | #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9184 | #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9185 | //VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 |
|---|
| 9186 | #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9187 | #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9188 | //VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 |
|---|
| 9189 | #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9190 | #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9191 | //VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 |
|---|
| 9192 | #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9193 | #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9194 | //VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 |
|---|
| 9195 | #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9196 | #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9197 | //VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 |
|---|
| 9198 | #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9199 | #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9200 | //VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 |
|---|
| 9201 | #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9202 | #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9203 | //VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 |
|---|
| 9204 | #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9205 | #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9206 | //VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 |
|---|
| 9207 | #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9208 | #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9209 | //VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 |
|---|
| 9210 | #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9211 | #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9212 | //VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 |
|---|
| 9213 | #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9214 | #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9215 | //VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 |
|---|
| 9216 | #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9217 | #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9218 | //VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 |
|---|
| 9219 | #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9220 | #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9221 | //VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 |
|---|
| 9222 | #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9223 | #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9224 | //VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 |
|---|
| 9225 | #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9226 | #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9227 | //VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 |
|---|
| 9228 | #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9229 | #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9230 | //VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 |
|---|
| 9231 | #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9232 | #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9233 | //VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 |
|---|
| 9234 | #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9235 | #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9236 | //VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 |
|---|
| 9237 | #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9238 | #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9239 | //VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 |
|---|
| 9240 | #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9241 | #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9242 | //VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 |
|---|
| 9243 | #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9244 | #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9245 | //VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 |
|---|
| 9246 | #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9247 | #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9248 | //VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 |
|---|
| 9249 | #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9250 | #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9251 | //VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 |
|---|
| 9252 | #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9253 | #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9254 | //VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 |
|---|
| 9255 | #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9256 | #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9257 | //VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 |
|---|
| 9258 | #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9259 | #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9260 | //VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 |
|---|
| 9261 | #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9262 | #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9263 | //VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 |
|---|
| 9264 | #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9265 | #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9266 | //VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 |
|---|
| 9267 | #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
|---|
| 9268 | #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
|---|
| 9269 | //VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 |
|---|
| 9270 | #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
|---|
| 9271 | #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
|---|
| 9272 | |
|---|
| 9273 | |
|---|
| 9274 | // addressBlock: mmhub_utcl2_vml2pldec |
|---|
| 9275 | //MC_VM_L2_PERFCOUNTER0_CFG |
|---|
| 9276 | #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
|---|
| 9277 | #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
|---|
| 9278 | #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
|---|
| 9279 | #define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
|---|
| 9280 | #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
|---|
| 9281 | #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
|---|
| 9282 | #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
|---|
| 9283 | #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
|---|
| 9284 | #define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
|---|
| 9285 | #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
|---|
| 9286 | //MC_VM_L2_PERFCOUNTER1_CFG |
|---|
| 9287 | #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
|---|
| 9288 | #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
|---|
| 9289 | #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
|---|
| 9290 | #define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
|---|
| 9291 | #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
|---|
| 9292 | #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
|---|
| 9293 | #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
|---|
| 9294 | #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
|---|
| 9295 | #define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
|---|
| 9296 | #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
|---|
| 9297 | //MC_VM_L2_PERFCOUNTER2_CFG |
|---|
| 9298 | #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 |
|---|
| 9299 | #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 |
|---|
| 9300 | #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 |
|---|
| 9301 | #define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c |
|---|
| 9302 | #define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d |
|---|
| 9303 | #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL |
|---|
| 9304 | #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L |
|---|
| 9305 | #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L |
|---|
| 9306 | #define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L |
|---|
| 9307 | #define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L |
|---|
| 9308 | //MC_VM_L2_PERFCOUNTER3_CFG |
|---|
| 9309 | #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 |
|---|
| 9310 | #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 |
|---|
| 9311 | #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 |
|---|
| 9312 | #define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c |
|---|
| 9313 | #define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d |
|---|
| 9314 | #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL |
|---|
| 9315 | #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L |
|---|
| 9316 | #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L |
|---|
| 9317 | #define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L |
|---|
| 9318 | #define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L |
|---|
| 9319 | //MC_VM_L2_PERFCOUNTER4_CFG |
|---|
| 9320 | #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 |
|---|
| 9321 | #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 |
|---|
| 9322 | #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 |
|---|
| 9323 | #define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c |
|---|
| 9324 | #define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d |
|---|
| 9325 | #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL |
|---|
| 9326 | #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L |
|---|
| 9327 | #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L |
|---|
| 9328 | #define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L |
|---|
| 9329 | #define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L |
|---|
| 9330 | //MC_VM_L2_PERFCOUNTER5_CFG |
|---|
| 9331 | #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 |
|---|
| 9332 | #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 |
|---|
| 9333 | #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 |
|---|
| 9334 | #define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c |
|---|
| 9335 | #define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d |
|---|
| 9336 | #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL |
|---|
| 9337 | #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L |
|---|
| 9338 | #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L |
|---|
| 9339 | #define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L |
|---|
| 9340 | #define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L |
|---|
| 9341 | //MC_VM_L2_PERFCOUNTER6_CFG |
|---|
| 9342 | #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 |
|---|
| 9343 | #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 |
|---|
| 9344 | #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 |
|---|
| 9345 | #define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c |
|---|
| 9346 | #define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d |
|---|
| 9347 | #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL |
|---|
| 9348 | #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L |
|---|
| 9349 | #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L |
|---|
| 9350 | #define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L |
|---|
| 9351 | #define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L |
|---|
| 9352 | //MC_VM_L2_PERFCOUNTER7_CFG |
|---|
| 9353 | #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 |
|---|
| 9354 | #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 |
|---|
| 9355 | #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 |
|---|
| 9356 | #define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c |
|---|
| 9357 | #define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d |
|---|
| 9358 | #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL |
|---|
| 9359 | #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L |
|---|
| 9360 | #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L |
|---|
| 9361 | #define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L |
|---|
| 9362 | #define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L |
|---|
| 9363 | //MC_VM_L2_PERFCOUNTER_RSLT_CNTL |
|---|
| 9364 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
|---|
| 9365 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
|---|
| 9366 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
|---|
| 9367 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
|---|
| 9368 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
|---|
| 9369 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
|---|
| 9370 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
|---|
| 9371 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
|---|
| 9372 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
|---|
| 9373 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
|---|
| 9374 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
|---|
| 9375 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
|---|
| 9376 | |
|---|
| 9377 | |
|---|
| 9378 | // addressBlock: mmhub_utcl2_vml2prdec |
|---|
| 9379 | //MC_VM_L2_PERFCOUNTER_LO |
|---|
| 9380 | #define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
|---|
| 9381 | #define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
|---|
| 9382 | //MC_VM_L2_PERFCOUNTER_HI |
|---|
| 9383 | #define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
|---|
| 9384 | #define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
|---|
| 9385 | #define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
|---|
| 9386 | #define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
|---|
| 9387 | |
|---|
| 9388 | |
|---|
| 9389 | // addressBlock: mmhub_utcl2_vmsharedhvdec |
|---|
| 9390 | //MC_VM_FB_SIZE_OFFSET_VF0 |
|---|
| 9391 | #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 |
|---|
| 9392 | #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 |
|---|
| 9393 | #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9394 | #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9395 | //MC_VM_FB_SIZE_OFFSET_VF1 |
|---|
| 9396 | #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 |
|---|
| 9397 | #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 |
|---|
| 9398 | #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9399 | #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9400 | //MC_VM_FB_SIZE_OFFSET_VF2 |
|---|
| 9401 | #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 |
|---|
| 9402 | #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 |
|---|
| 9403 | #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9404 | #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9405 | //MC_VM_FB_SIZE_OFFSET_VF3 |
|---|
| 9406 | #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 |
|---|
| 9407 | #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 |
|---|
| 9408 | #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9409 | #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9410 | //MC_VM_FB_SIZE_OFFSET_VF4 |
|---|
| 9411 | #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 |
|---|
| 9412 | #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 |
|---|
| 9413 | #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9414 | #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9415 | //MC_VM_FB_SIZE_OFFSET_VF5 |
|---|
| 9416 | #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 |
|---|
| 9417 | #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 |
|---|
| 9418 | #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9419 | #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9420 | //MC_VM_FB_SIZE_OFFSET_VF6 |
|---|
| 9421 | #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 |
|---|
| 9422 | #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 |
|---|
| 9423 | #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9424 | #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9425 | //MC_VM_FB_SIZE_OFFSET_VF7 |
|---|
| 9426 | #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 |
|---|
| 9427 | #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 |
|---|
| 9428 | #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9429 | #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9430 | //MC_VM_FB_SIZE_OFFSET_VF8 |
|---|
| 9431 | #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 |
|---|
| 9432 | #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 |
|---|
| 9433 | #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9434 | #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9435 | //MC_VM_FB_SIZE_OFFSET_VF9 |
|---|
| 9436 | #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 |
|---|
| 9437 | #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 |
|---|
| 9438 | #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9439 | #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9440 | //MC_VM_FB_SIZE_OFFSET_VF10 |
|---|
| 9441 | #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 |
|---|
| 9442 | #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 |
|---|
| 9443 | #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9444 | #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9445 | //MC_VM_FB_SIZE_OFFSET_VF11 |
|---|
| 9446 | #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 |
|---|
| 9447 | #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 |
|---|
| 9448 | #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9449 | #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9450 | //MC_VM_FB_SIZE_OFFSET_VF12 |
|---|
| 9451 | #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 |
|---|
| 9452 | #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 |
|---|
| 9453 | #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9454 | #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9455 | //MC_VM_FB_SIZE_OFFSET_VF13 |
|---|
| 9456 | #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 |
|---|
| 9457 | #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 |
|---|
| 9458 | #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9459 | #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9460 | //MC_VM_FB_SIZE_OFFSET_VF14 |
|---|
| 9461 | #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 |
|---|
| 9462 | #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 |
|---|
| 9463 | #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9464 | #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9465 | //MC_VM_FB_SIZE_OFFSET_VF15 |
|---|
| 9466 | #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 |
|---|
| 9467 | #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 |
|---|
| 9468 | #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9469 | #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9470 | //VM_IOMMU_MMIO_CNTRL_1 |
|---|
| 9471 | #define VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8 |
|---|
| 9472 | #define VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L |
|---|
| 9473 | //MC_VM_MARC_BASE_LO_0 |
|---|
| 9474 | #define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc |
|---|
| 9475 | #define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L |
|---|
| 9476 | //MC_VM_MARC_BASE_LO_1 |
|---|
| 9477 | #define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc |
|---|
| 9478 | #define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L |
|---|
| 9479 | //MC_VM_MARC_BASE_LO_2 |
|---|
| 9480 | #define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc |
|---|
| 9481 | #define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L |
|---|
| 9482 | //MC_VM_MARC_BASE_LO_3 |
|---|
| 9483 | #define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc |
|---|
| 9484 | #define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L |
|---|
| 9485 | //MC_VM_MARC_BASE_HI_0 |
|---|
| 9486 | #define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 |
|---|
| 9487 | #define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL |
|---|
| 9488 | //MC_VM_MARC_BASE_HI_1 |
|---|
| 9489 | #define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 |
|---|
| 9490 | #define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL |
|---|
| 9491 | //MC_VM_MARC_BASE_HI_2 |
|---|
| 9492 | #define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 |
|---|
| 9493 | #define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL |
|---|
| 9494 | //MC_VM_MARC_BASE_HI_3 |
|---|
| 9495 | #define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 |
|---|
| 9496 | #define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL |
|---|
| 9497 | //MC_VM_MARC_RELOC_LO_0 |
|---|
| 9498 | #define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 |
|---|
| 9499 | #define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 |
|---|
| 9500 | #define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc |
|---|
| 9501 | #define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L |
|---|
| 9502 | #define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L |
|---|
| 9503 | #define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L |
|---|
| 9504 | //MC_VM_MARC_RELOC_LO_1 |
|---|
| 9505 | #define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 |
|---|
| 9506 | #define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 |
|---|
| 9507 | #define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc |
|---|
| 9508 | #define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L |
|---|
| 9509 | #define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L |
|---|
| 9510 | #define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L |
|---|
| 9511 | //MC_VM_MARC_RELOC_LO_2 |
|---|
| 9512 | #define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 |
|---|
| 9513 | #define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 |
|---|
| 9514 | #define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc |
|---|
| 9515 | #define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L |
|---|
| 9516 | #define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L |
|---|
| 9517 | #define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L |
|---|
| 9518 | //MC_VM_MARC_RELOC_LO_3 |
|---|
| 9519 | #define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 |
|---|
| 9520 | #define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 |
|---|
| 9521 | #define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc |
|---|
| 9522 | #define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L |
|---|
| 9523 | #define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L |
|---|
| 9524 | #define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L |
|---|
| 9525 | //MC_VM_MARC_RELOC_HI_0 |
|---|
| 9526 | #define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 |
|---|
| 9527 | #define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL |
|---|
| 9528 | //MC_VM_MARC_RELOC_HI_1 |
|---|
| 9529 | #define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 |
|---|
| 9530 | #define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL |
|---|
| 9531 | //MC_VM_MARC_RELOC_HI_2 |
|---|
| 9532 | #define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 |
|---|
| 9533 | #define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL |
|---|
| 9534 | //MC_VM_MARC_RELOC_HI_3 |
|---|
| 9535 | #define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 |
|---|
| 9536 | #define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL |
|---|
| 9537 | //MC_VM_MARC_LEN_LO_0 |
|---|
| 9538 | #define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc |
|---|
| 9539 | #define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L |
|---|
| 9540 | //MC_VM_MARC_LEN_LO_1 |
|---|
| 9541 | #define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc |
|---|
| 9542 | #define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L |
|---|
| 9543 | //MC_VM_MARC_LEN_LO_2 |
|---|
| 9544 | #define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc |
|---|
| 9545 | #define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L |
|---|
| 9546 | //MC_VM_MARC_LEN_LO_3 |
|---|
| 9547 | #define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc |
|---|
| 9548 | #define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L |
|---|
| 9549 | //MC_VM_MARC_LEN_HI_0 |
|---|
| 9550 | #define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 |
|---|
| 9551 | #define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL |
|---|
| 9552 | //MC_VM_MARC_LEN_HI_1 |
|---|
| 9553 | #define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 |
|---|
| 9554 | #define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL |
|---|
| 9555 | //MC_VM_MARC_LEN_HI_2 |
|---|
| 9556 | #define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 |
|---|
| 9557 | #define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL |
|---|
| 9558 | //MC_VM_MARC_LEN_HI_3 |
|---|
| 9559 | #define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 |
|---|
| 9560 | #define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL |
|---|
| 9561 | //VM_IOMMU_CONTROL_REGISTER |
|---|
| 9562 | #define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 |
|---|
| 9563 | #define VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L |
|---|
| 9564 | //VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER |
|---|
| 9565 | #define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd |
|---|
| 9566 | #define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L |
|---|
| 9567 | //VM_PCIE_ATS_CNTL |
|---|
| 9568 | #define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10 |
|---|
| 9569 | #define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f |
|---|
| 9570 | #define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L |
|---|
| 9571 | #define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L |
|---|
| 9572 | //VM_PCIE_ATS_CNTL_VF_0 |
|---|
| 9573 | #define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f |
|---|
| 9574 | #define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L |
|---|
| 9575 | //VM_PCIE_ATS_CNTL_VF_1 |
|---|
| 9576 | #define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f |
|---|
| 9577 | #define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L |
|---|
| 9578 | //VM_PCIE_ATS_CNTL_VF_2 |
|---|
| 9579 | #define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f |
|---|
| 9580 | #define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L |
|---|
| 9581 | //VM_PCIE_ATS_CNTL_VF_3 |
|---|
| 9582 | #define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f |
|---|
| 9583 | #define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L |
|---|
| 9584 | //VM_PCIE_ATS_CNTL_VF_4 |
|---|
| 9585 | #define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f |
|---|
| 9586 | #define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L |
|---|
| 9587 | //VM_PCIE_ATS_CNTL_VF_5 |
|---|
| 9588 | #define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f |
|---|
| 9589 | #define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L |
|---|
| 9590 | //VM_PCIE_ATS_CNTL_VF_6 |
|---|
| 9591 | #define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f |
|---|
| 9592 | #define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L |
|---|
| 9593 | //VM_PCIE_ATS_CNTL_VF_7 |
|---|
| 9594 | #define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f |
|---|
| 9595 | #define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L |
|---|
| 9596 | //VM_PCIE_ATS_CNTL_VF_8 |
|---|
| 9597 | #define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f |
|---|
| 9598 | #define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L |
|---|
| 9599 | //VM_PCIE_ATS_CNTL_VF_9 |
|---|
| 9600 | #define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f |
|---|
| 9601 | #define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L |
|---|
| 9602 | //VM_PCIE_ATS_CNTL_VF_10 |
|---|
| 9603 | #define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f |
|---|
| 9604 | #define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L |
|---|
| 9605 | //VM_PCIE_ATS_CNTL_VF_11 |
|---|
| 9606 | #define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f |
|---|
| 9607 | #define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L |
|---|
| 9608 | //VM_PCIE_ATS_CNTL_VF_12 |
|---|
| 9609 | #define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f |
|---|
| 9610 | #define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L |
|---|
| 9611 | //VM_PCIE_ATS_CNTL_VF_13 |
|---|
| 9612 | #define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f |
|---|
| 9613 | #define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L |
|---|
| 9614 | //VM_PCIE_ATS_CNTL_VF_14 |
|---|
| 9615 | #define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f |
|---|
| 9616 | #define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L |
|---|
| 9617 | //VM_PCIE_ATS_CNTL_VF_15 |
|---|
| 9618 | #define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f |
|---|
| 9619 | #define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L |
|---|
| 9620 | //UTCL2_CGTT_CLK_CTRL |
|---|
| 9621 | #define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
|---|
| 9622 | #define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
|---|
| 9623 | #define 0xc |
|---|
| 9624 | #define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
|---|
| 9625 | #define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 |
|---|
| 9626 | #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 |
|---|
| 9627 | #define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
|---|
| 9628 | #define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
|---|
| 9629 | #define 0x00007000L |
|---|
| 9630 | #define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
|---|
| 9631 | #define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L |
|---|
| 9632 | #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L |
|---|
| 9633 | |
|---|
| 9634 | |
|---|
| 9635 | // addressBlock: mmhub_utcl2_vmsharedpfdec |
|---|
| 9636 | //MC_VM_NB_MMIOBASE |
|---|
| 9637 | #define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 |
|---|
| 9638 | #define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL |
|---|
| 9639 | //MC_VM_NB_MMIOLIMIT |
|---|
| 9640 | #define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 |
|---|
| 9641 | #define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL |
|---|
| 9642 | //MC_VM_NB_PCI_CTRL |
|---|
| 9643 | #define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 |
|---|
| 9644 | #define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L |
|---|
| 9645 | //MC_VM_NB_PCI_ARB |
|---|
| 9646 | #define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 |
|---|
| 9647 | #define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L |
|---|
| 9648 | //MC_VM_NB_TOP_OF_DRAM_SLOT1 |
|---|
| 9649 | #define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 |
|---|
| 9650 | #define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L |
|---|
| 9651 | //MC_VM_NB_LOWER_TOP_OF_DRAM2 |
|---|
| 9652 | #define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 |
|---|
| 9653 | #define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 |
|---|
| 9654 | #define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L |
|---|
| 9655 | #define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L |
|---|
| 9656 | //MC_VM_NB_UPPER_TOP_OF_DRAM2 |
|---|
| 9657 | #define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 |
|---|
| 9658 | #define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL |
|---|
| 9659 | //MC_VM_FB_OFFSET |
|---|
| 9660 | #define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 |
|---|
| 9661 | #define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL |
|---|
| 9662 | //MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB |
|---|
| 9663 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 |
|---|
| 9664 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL |
|---|
| 9665 | //MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB |
|---|
| 9666 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 |
|---|
| 9667 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL |
|---|
| 9668 | //MC_VM_STEERING |
|---|
| 9669 | #define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 |
|---|
| 9670 | #define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L |
|---|
| 9671 | //MC_SHARED_VIRT_RESET_REQ |
|---|
| 9672 | #define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 |
|---|
| 9673 | #define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f |
|---|
| 9674 | #define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL |
|---|
| 9675 | #define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L |
|---|
| 9676 | //MC_MEM_POWER_LS |
|---|
| 9677 | #define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 |
|---|
| 9678 | #define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 |
|---|
| 9679 | #define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL |
|---|
| 9680 | #define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L |
|---|
| 9681 | //MC_VM_CACHEABLE_DRAM_ADDRESS_START |
|---|
| 9682 | #define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 |
|---|
| 9683 | #define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL |
|---|
| 9684 | //MC_VM_CACHEABLE_DRAM_ADDRESS_END |
|---|
| 9685 | #define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 |
|---|
| 9686 | #define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL |
|---|
| 9687 | //MC_VM_APT_CNTL |
|---|
| 9688 | #define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 |
|---|
| 9689 | #define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 |
|---|
| 9690 | #define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L |
|---|
| 9691 | #define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L |
|---|
| 9692 | //MC_VM_LOCAL_HBM_ADDRESS_START |
|---|
| 9693 | #define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 |
|---|
| 9694 | #define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL |
|---|
| 9695 | //MC_VM_LOCAL_HBM_ADDRESS_END |
|---|
| 9696 | #define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 |
|---|
| 9697 | #define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL |
|---|
| 9698 | //MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL |
|---|
| 9699 | #define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 |
|---|
| 9700 | #define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L |
|---|
| 9701 | |
|---|
| 9702 | |
|---|
| 9703 | // addressBlock: mmhub_utcl2_vmsharedvcdec |
|---|
| 9704 | //MC_VM_FB_LOCATION_BASE |
|---|
| 9705 | #define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 |
|---|
| 9706 | #define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL |
|---|
| 9707 | //MC_VM_FB_LOCATION_TOP |
|---|
| 9708 | #define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 |
|---|
| 9709 | #define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL |
|---|
| 9710 | //MC_VM_AGP_TOP |
|---|
| 9711 | #define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 |
|---|
| 9712 | #define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL |
|---|
| 9713 | //MC_VM_AGP_BOT |
|---|
| 9714 | #define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 |
|---|
| 9715 | #define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL |
|---|
| 9716 | //MC_VM_AGP_BASE |
|---|
| 9717 | #define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 |
|---|
| 9718 | #define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL |
|---|
| 9719 | //MC_VM_SYSTEM_APERTURE_LOW_ADDR |
|---|
| 9720 | #define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 |
|---|
| 9721 | #define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL |
|---|
| 9722 | //MC_VM_SYSTEM_APERTURE_HIGH_ADDR |
|---|
| 9723 | #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 |
|---|
| 9724 | #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL |
|---|
| 9725 | //MC_VM_MX_L1_TLB_CNTL |
|---|
| 9726 | #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 |
|---|
| 9727 | #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 |
|---|
| 9728 | #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 |
|---|
| 9729 | #define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 |
|---|
| 9730 | #define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 |
|---|
| 9731 | #define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb |
|---|
| 9732 | #define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd |
|---|
| 9733 | #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L |
|---|
| 9734 | #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L |
|---|
| 9735 | #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L |
|---|
| 9736 | #define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L |
|---|
| 9737 | #define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L |
|---|
| 9738 | #define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L |
|---|
| 9739 | #define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L |
|---|
| 9740 | |
|---|
| 9741 | |
|---|
| 9742 | // addressBlock: mmhub_utcl2_atcl2pfcntrdec |
|---|
| 9743 | //ATC_L2_PERFCOUNTER_LO |
|---|
| 9744 | #define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
|---|
| 9745 | #define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
|---|
| 9746 | //ATC_L2_PERFCOUNTER_HI |
|---|
| 9747 | #define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
|---|
| 9748 | #define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
|---|
| 9749 | #define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
|---|
| 9750 | #define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
|---|
| 9751 | |
|---|
| 9752 | |
|---|
| 9753 | // addressBlock: mmhub_utcl2_atcl2pfcntldec |
|---|
| 9754 | //ATC_L2_PERFCOUNTER0_CFG |
|---|
| 9755 | #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
|---|
| 9756 | #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
|---|
| 9757 | #define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
|---|
| 9758 | #define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
|---|
| 9759 | #define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
|---|
| 9760 | #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
|---|
| 9761 | #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
|---|
| 9762 | #define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
|---|
| 9763 | #define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
|---|
| 9764 | #define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
|---|
| 9765 | //ATC_L2_PERFCOUNTER1_CFG |
|---|
| 9766 | #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
|---|
| 9767 | #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
|---|
| 9768 | #define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
|---|
| 9769 | #define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
|---|
| 9770 | #define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
|---|
| 9771 | #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
|---|
| 9772 | #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
|---|
| 9773 | #define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
|---|
| 9774 | #define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
|---|
| 9775 | #define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
|---|
| 9776 | //ATC_L2_PERFCOUNTER_RSLT_CNTL |
|---|
| 9777 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
|---|
| 9778 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
|---|
| 9779 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
|---|
| 9780 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
|---|
| 9781 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
|---|
| 9782 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
|---|
| 9783 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
|---|
| 9784 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
|---|
| 9785 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
|---|
| 9786 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
|---|
| 9787 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
|---|
| 9788 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
|---|
| 9789 | |
|---|
| 9790 | #endif |
|---|
| 9791 | |
|---|
