| 1 | /* |
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| 2 | * Copyright (C) 2018 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included |
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| 12 | * in all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
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| 18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 20 | */ |
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| 21 | #ifndef _mmhub_9_4_1_OFFSET_HEADER |
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| 22 | #define |
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| 23 | |
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| 24 | |
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| 25 | |
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| 26 | // addressBlock: mmhub_dagb_dagbdec0 |
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| 27 | // base address: 0x68000 |
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| 28 | #define mmDAGB0_RDCLI0 0x0000 |
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| 29 | #define mmDAGB0_RDCLI0_BASE_IDX 1 |
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| 30 | #define mmDAGB0_RDCLI1 0x0001 |
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| 31 | #define mmDAGB0_RDCLI1_BASE_IDX 1 |
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| 32 | #define mmDAGB0_RDCLI2 0x0002 |
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| 33 | #define mmDAGB0_RDCLI2_BASE_IDX 1 |
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| 34 | #define mmDAGB0_RDCLI3 0x0003 |
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| 35 | #define mmDAGB0_RDCLI3_BASE_IDX 1 |
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| 36 | #define mmDAGB0_RDCLI4 0x0004 |
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| 37 | #define mmDAGB0_RDCLI4_BASE_IDX 1 |
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| 38 | #define mmDAGB0_RDCLI5 0x0005 |
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| 39 | #define mmDAGB0_RDCLI5_BASE_IDX 1 |
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| 40 | #define mmDAGB0_RDCLI6 0x0006 |
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| 41 | #define mmDAGB0_RDCLI6_BASE_IDX 1 |
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| 42 | #define mmDAGB0_RDCLI7 0x0007 |
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| 43 | #define mmDAGB0_RDCLI7_BASE_IDX 1 |
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| 44 | #define mmDAGB0_RDCLI8 0x0008 |
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| 45 | #define mmDAGB0_RDCLI8_BASE_IDX 1 |
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| 46 | #define mmDAGB0_RDCLI9 0x0009 |
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| 47 | #define mmDAGB0_RDCLI9_BASE_IDX 1 |
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| 48 | #define mmDAGB0_RDCLI10 0x000a |
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| 49 | #define mmDAGB0_RDCLI10_BASE_IDX 1 |
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| 50 | #define mmDAGB0_RDCLI11 0x000b |
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| 51 | #define mmDAGB0_RDCLI11_BASE_IDX 1 |
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| 52 | #define mmDAGB0_RDCLI12 0x000c |
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| 53 | #define mmDAGB0_RDCLI12_BASE_IDX 1 |
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| 54 | #define mmDAGB0_RDCLI13 0x000d |
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| 55 | #define mmDAGB0_RDCLI13_BASE_IDX 1 |
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| 56 | #define mmDAGB0_RDCLI14 0x000e |
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| 57 | #define mmDAGB0_RDCLI14_BASE_IDX 1 |
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| 58 | #define mmDAGB0_RDCLI15 0x000f |
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| 59 | #define mmDAGB0_RDCLI15_BASE_IDX 1 |
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| 60 | #define mmDAGB0_RD_CNTL 0x0010 |
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| 61 | #define mmDAGB0_RD_CNTL_BASE_IDX 1 |
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| 62 | #define mmDAGB0_RD_GMI_CNTL 0x0011 |
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| 63 | #define mmDAGB0_RD_GMI_CNTL_BASE_IDX 1 |
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| 64 | #define mmDAGB0_RD_ADDR_DAGB 0x0012 |
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| 65 | #define mmDAGB0_RD_ADDR_DAGB_BASE_IDX 1 |
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| 66 | #define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0x0013 |
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| 67 | #define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 |
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| 68 | #define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0x0014 |
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| 69 | #define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 |
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| 70 | #define mmDAGB0_RD_CGTT_CLK_CTRL 0x0015 |
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| 71 | #define mmDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
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| 72 | #define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0016 |
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| 73 | #define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
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| 74 | #define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0x0017 |
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| 75 | #define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
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| 76 | #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0018 |
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| 77 | #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 |
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| 78 | #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0019 |
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| 79 | #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 |
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| 80 | #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x001a |
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| 81 | #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 |
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| 82 | #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x001b |
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| 83 | #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 |
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| 84 | #define mmDAGB0_RD_VC0_CNTL 0x001c |
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| 85 | #define mmDAGB0_RD_VC0_CNTL_BASE_IDX 1 |
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| 86 | #define mmDAGB0_RD_VC1_CNTL 0x001d |
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| 87 | #define mmDAGB0_RD_VC1_CNTL_BASE_IDX 1 |
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| 88 | #define mmDAGB0_RD_VC2_CNTL 0x001e |
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| 89 | #define mmDAGB0_RD_VC2_CNTL_BASE_IDX 1 |
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| 90 | #define mmDAGB0_RD_VC3_CNTL 0x001f |
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| 91 | #define mmDAGB0_RD_VC3_CNTL_BASE_IDX 1 |
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| 92 | #define mmDAGB0_RD_VC4_CNTL 0x0020 |
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| 93 | #define mmDAGB0_RD_VC4_CNTL_BASE_IDX 1 |
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| 94 | #define mmDAGB0_RD_VC5_CNTL 0x0021 |
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| 95 | #define mmDAGB0_RD_VC5_CNTL_BASE_IDX 1 |
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| 96 | #define mmDAGB0_RD_VC6_CNTL 0x0022 |
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| 97 | #define mmDAGB0_RD_VC6_CNTL_BASE_IDX 1 |
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| 98 | #define mmDAGB0_RD_VC7_CNTL 0x0023 |
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| 99 | #define mmDAGB0_RD_VC7_CNTL_BASE_IDX 1 |
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| 100 | #define mmDAGB0_RD_CNTL_MISC 0x0024 |
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| 101 | #define mmDAGB0_RD_CNTL_MISC_BASE_IDX 1 |
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| 102 | #define mmDAGB0_RD_TLB_CREDIT 0x0025 |
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| 103 | #define mmDAGB0_RD_TLB_CREDIT_BASE_IDX 1 |
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| 104 | #define mmDAGB0_RDCLI_ASK_PENDING 0x0026 |
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| 105 | #define mmDAGB0_RDCLI_ASK_PENDING_BASE_IDX 1 |
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| 106 | #define mmDAGB0_RDCLI_GO_PENDING 0x0027 |
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| 107 | #define mmDAGB0_RDCLI_GO_PENDING_BASE_IDX 1 |
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| 108 | #define mmDAGB0_RDCLI_GBLSEND_PENDING 0x0028 |
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| 109 | #define mmDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 1 |
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| 110 | #define mmDAGB0_RDCLI_TLB_PENDING 0x0029 |
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| 111 | #define mmDAGB0_RDCLI_TLB_PENDING_BASE_IDX 1 |
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| 112 | #define mmDAGB0_RDCLI_OARB_PENDING 0x002a |
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| 113 | #define mmDAGB0_RDCLI_OARB_PENDING_BASE_IDX 1 |
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| 114 | #define mmDAGB0_RDCLI_OSD_PENDING 0x002b |
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| 115 | #define mmDAGB0_RDCLI_OSD_PENDING_BASE_IDX 1 |
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| 116 | #define mmDAGB0_WRCLI0 0x002c |
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| 117 | #define mmDAGB0_WRCLI0_BASE_IDX 1 |
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| 118 | #define mmDAGB0_WRCLI1 0x002d |
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| 119 | #define mmDAGB0_WRCLI1_BASE_IDX 1 |
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| 120 | #define mmDAGB0_WRCLI2 0x002e |
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| 121 | #define mmDAGB0_WRCLI2_BASE_IDX 1 |
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| 122 | #define mmDAGB0_WRCLI3 0x002f |
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| 123 | #define mmDAGB0_WRCLI3_BASE_IDX 1 |
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| 124 | #define mmDAGB0_WRCLI4 0x0030 |
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| 125 | #define mmDAGB0_WRCLI4_BASE_IDX 1 |
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| 126 | #define mmDAGB0_WRCLI5 0x0031 |
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| 127 | #define mmDAGB0_WRCLI5_BASE_IDX 1 |
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| 128 | #define mmDAGB0_WRCLI6 0x0032 |
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| 129 | #define mmDAGB0_WRCLI6_BASE_IDX 1 |
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| 130 | #define mmDAGB0_WRCLI7 0x0033 |
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| 131 | #define mmDAGB0_WRCLI7_BASE_IDX 1 |
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| 132 | #define mmDAGB0_WRCLI8 0x0034 |
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| 133 | #define mmDAGB0_WRCLI8_BASE_IDX 1 |
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| 134 | #define mmDAGB0_WRCLI9 0x0035 |
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| 135 | #define mmDAGB0_WRCLI9_BASE_IDX 1 |
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| 136 | #define mmDAGB0_WRCLI10 0x0036 |
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| 137 | #define mmDAGB0_WRCLI10_BASE_IDX 1 |
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| 138 | #define mmDAGB0_WRCLI11 0x0037 |
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| 139 | #define mmDAGB0_WRCLI11_BASE_IDX 1 |
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| 140 | #define mmDAGB0_WRCLI12 0x0038 |
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| 141 | #define mmDAGB0_WRCLI12_BASE_IDX 1 |
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| 142 | #define mmDAGB0_WRCLI13 0x0039 |
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| 143 | #define mmDAGB0_WRCLI13_BASE_IDX 1 |
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| 144 | #define mmDAGB0_WRCLI14 0x003a |
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| 145 | #define mmDAGB0_WRCLI14_BASE_IDX 1 |
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| 146 | #define mmDAGB0_WRCLI15 0x003b |
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| 147 | #define mmDAGB0_WRCLI15_BASE_IDX 1 |
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| 148 | #define mmDAGB0_WR_CNTL 0x003c |
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| 149 | #define mmDAGB0_WR_CNTL_BASE_IDX 1 |
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| 150 | #define mmDAGB0_WR_GMI_CNTL 0x003d |
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| 151 | #define mmDAGB0_WR_GMI_CNTL_BASE_IDX 1 |
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| 152 | #define mmDAGB0_WR_ADDR_DAGB 0x003e |
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| 153 | #define mmDAGB0_WR_ADDR_DAGB_BASE_IDX 1 |
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| 154 | #define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0x003f |
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| 155 | #define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 |
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| 156 | #define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0x0040 |
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| 157 | #define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 |
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| 158 | #define mmDAGB0_WR_CGTT_CLK_CTRL 0x0041 |
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| 159 | #define mmDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
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| 160 | #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0042 |
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| 161 | #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
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| 162 | #define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0x0043 |
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| 163 | #define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
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| 164 | #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0044 |
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| 165 | #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 |
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| 166 | #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0045 |
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| 167 | #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 |
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| 168 | #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x0046 |
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| 169 | #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 |
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| 170 | #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x0047 |
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| 171 | #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 |
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| 172 | #define mmDAGB0_WR_DATA_DAGB 0x0048 |
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| 173 | #define mmDAGB0_WR_DATA_DAGB_BASE_IDX 1 |
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| 174 | #define mmDAGB0_WR_DATA_DAGB_MAX_BURST0 0x0049 |
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| 175 | #define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 |
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| 176 | #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x004a |
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| 177 | #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 |
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| 178 | #define mmDAGB0_WR_DATA_DAGB_MAX_BURST1 0x004b |
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| 179 | #define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 |
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| 180 | #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x004c |
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| 181 | #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 |
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| 182 | #define mmDAGB0_WR_VC0_CNTL 0x004d |
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| 183 | #define mmDAGB0_WR_VC0_CNTL_BASE_IDX 1 |
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| 184 | #define mmDAGB0_WR_VC1_CNTL 0x004e |
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| 185 | #define mmDAGB0_WR_VC1_CNTL_BASE_IDX 1 |
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| 186 | #define mmDAGB0_WR_VC2_CNTL 0x004f |
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| 187 | #define mmDAGB0_WR_VC2_CNTL_BASE_IDX 1 |
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| 188 | #define mmDAGB0_WR_VC3_CNTL 0x0050 |
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| 189 | #define mmDAGB0_WR_VC3_CNTL_BASE_IDX 1 |
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| 190 | #define mmDAGB0_WR_VC4_CNTL 0x0051 |
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| 191 | #define mmDAGB0_WR_VC4_CNTL_BASE_IDX 1 |
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| 192 | #define mmDAGB0_WR_VC5_CNTL 0x0052 |
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| 193 | #define mmDAGB0_WR_VC5_CNTL_BASE_IDX 1 |
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| 194 | #define mmDAGB0_WR_VC6_CNTL 0x0053 |
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| 195 | #define mmDAGB0_WR_VC6_CNTL_BASE_IDX 1 |
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| 196 | #define mmDAGB0_WR_VC7_CNTL 0x0054 |
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| 197 | #define mmDAGB0_WR_VC7_CNTL_BASE_IDX 1 |
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| 198 | #define mmDAGB0_WR_CNTL_MISC 0x0055 |
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| 199 | #define mmDAGB0_WR_CNTL_MISC_BASE_IDX 1 |
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| 200 | #define mmDAGB0_WR_TLB_CREDIT 0x0056 |
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| 201 | #define mmDAGB0_WR_TLB_CREDIT_BASE_IDX 1 |
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| 202 | #define mmDAGB0_WR_DATA_CREDIT 0x0057 |
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| 203 | #define mmDAGB0_WR_DATA_CREDIT_BASE_IDX 1 |
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| 204 | #define mmDAGB0_WR_MISC_CREDIT 0x0058 |
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| 205 | #define mmDAGB0_WR_MISC_CREDIT_BASE_IDX 1 |
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| 206 | #define mmDAGB0_WRCLI_ASK_PENDING 0x005d |
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| 207 | #define mmDAGB0_WRCLI_ASK_PENDING_BASE_IDX 1 |
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| 208 | #define mmDAGB0_WRCLI_GO_PENDING 0x005e |
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| 209 | #define mmDAGB0_WRCLI_GO_PENDING_BASE_IDX 1 |
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| 210 | #define mmDAGB0_WRCLI_GBLSEND_PENDING 0x005f |
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| 211 | #define mmDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 1 |
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| 212 | #define mmDAGB0_WRCLI_TLB_PENDING 0x0060 |
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| 213 | #define mmDAGB0_WRCLI_TLB_PENDING_BASE_IDX 1 |
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| 214 | #define mmDAGB0_WRCLI_OARB_PENDING 0x0061 |
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| 215 | #define mmDAGB0_WRCLI_OARB_PENDING_BASE_IDX 1 |
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| 216 | #define mmDAGB0_WRCLI_OSD_PENDING 0x0062 |
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| 217 | #define mmDAGB0_WRCLI_OSD_PENDING_BASE_IDX 1 |
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| 218 | #define mmDAGB0_WRCLI_DBUS_ASK_PENDING 0x0063 |
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| 219 | #define mmDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 |
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| 220 | #define mmDAGB0_WRCLI_DBUS_GO_PENDING 0x0064 |
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| 221 | #define mmDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 |
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| 222 | #define mmDAGB0_DAGB_DLY 0x0065 |
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| 223 | #define mmDAGB0_DAGB_DLY_BASE_IDX 1 |
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| 224 | #define mmDAGB0_CNTL_MISC 0x0066 |
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| 225 | #define mmDAGB0_CNTL_MISC_BASE_IDX 1 |
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| 226 | #define mmDAGB0_CNTL_MISC2 0x0067 |
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| 227 | #define mmDAGB0_CNTL_MISC2_BASE_IDX 1 |
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| 228 | #define mmDAGB0_FIFO_EMPTY 0x0068 |
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| 229 | #define mmDAGB0_FIFO_EMPTY_BASE_IDX 1 |
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| 230 | #define mmDAGB0_FIFO_FULL 0x0069 |
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| 231 | #define mmDAGB0_FIFO_FULL_BASE_IDX 1 |
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| 232 | #define mmDAGB0_WR_CREDITS_FULL 0x006a |
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| 233 | #define mmDAGB0_WR_CREDITS_FULL_BASE_IDX 1 |
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| 234 | #define mmDAGB0_RD_CREDITS_FULL 0x006b |
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| 235 | #define mmDAGB0_RD_CREDITS_FULL_BASE_IDX 1 |
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| 236 | #define mmDAGB0_PERFCOUNTER_LO 0x006c |
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| 237 | #define mmDAGB0_PERFCOUNTER_LO_BASE_IDX 1 |
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| 238 | #define mmDAGB0_PERFCOUNTER_HI 0x006d |
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| 239 | #define mmDAGB0_PERFCOUNTER_HI_BASE_IDX 1 |
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| 240 | #define mmDAGB0_PERFCOUNTER0_CFG 0x006e |
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| 241 | #define mmDAGB0_PERFCOUNTER0_CFG_BASE_IDX 1 |
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| 242 | #define mmDAGB0_PERFCOUNTER1_CFG 0x006f |
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| 243 | #define mmDAGB0_PERFCOUNTER1_CFG_BASE_IDX 1 |
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| 244 | #define mmDAGB0_PERFCOUNTER2_CFG 0x0070 |
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| 245 | #define mmDAGB0_PERFCOUNTER2_CFG_BASE_IDX 1 |
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| 246 | #define mmDAGB0_PERFCOUNTER_RSLT_CNTL 0x0071 |
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| 247 | #define mmDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
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| 248 | #define mmDAGB0_RESERVE0 0x0072 |
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| 249 | #define mmDAGB0_RESERVE0_BASE_IDX 1 |
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| 250 | #define mmDAGB0_RESERVE1 0x0073 |
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| 251 | #define mmDAGB0_RESERVE1_BASE_IDX 1 |
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| 252 | #define mmDAGB0_RESERVE2 0x0074 |
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| 253 | #define mmDAGB0_RESERVE2_BASE_IDX 1 |
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| 254 | #define mmDAGB0_RESERVE3 0x0075 |
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| 255 | #define mmDAGB0_RESERVE3_BASE_IDX 1 |
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| 256 | #define mmDAGB0_RESERVE4 0x0076 |
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| 257 | #define mmDAGB0_RESERVE4_BASE_IDX 1 |
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| 258 | #define mmDAGB0_RESERVE5 0x0077 |
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| 259 | #define mmDAGB0_RESERVE5_BASE_IDX 1 |
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| 260 | #define mmDAGB0_RESERVE6 0x0078 |
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| 261 | #define mmDAGB0_RESERVE6_BASE_IDX 1 |
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| 262 | #define mmDAGB0_RESERVE7 0x0079 |
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| 263 | #define mmDAGB0_RESERVE7_BASE_IDX 1 |
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| 264 | #define mmDAGB0_RESERVE8 0x007a |
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| 265 | #define mmDAGB0_RESERVE8_BASE_IDX 1 |
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| 266 | #define mmDAGB0_RESERVE9 0x007b |
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| 267 | #define mmDAGB0_RESERVE9_BASE_IDX 1 |
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| 268 | #define mmDAGB0_RESERVE10 0x007c |
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| 269 | #define mmDAGB0_RESERVE10_BASE_IDX 1 |
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| 270 | #define mmDAGB0_RESERVE11 0x007d |
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| 271 | #define mmDAGB0_RESERVE11_BASE_IDX 1 |
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| 272 | #define mmDAGB0_RESERVE12 0x007e |
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| 273 | #define mmDAGB0_RESERVE12_BASE_IDX 1 |
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| 274 | #define mmDAGB0_RESERVE13 0x007f |
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| 275 | #define mmDAGB0_RESERVE13_BASE_IDX 1 |
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| 276 | |
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| 277 | |
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| 278 | // addressBlock: mmhub_dagb_dagbdec1 |
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| 279 | // base address: 0x68200 |
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| 280 | #define mmDAGB1_RDCLI0 0x0080 |
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| 281 | #define mmDAGB1_RDCLI0_BASE_IDX 1 |
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| 282 | #define mmDAGB1_RDCLI1 0x0081 |
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| 283 | #define mmDAGB1_RDCLI1_BASE_IDX 1 |
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| 284 | #define mmDAGB1_RDCLI2 0x0082 |
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| 285 | #define mmDAGB1_RDCLI2_BASE_IDX 1 |
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| 286 | #define mmDAGB1_RDCLI3 0x0083 |
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| 287 | #define mmDAGB1_RDCLI3_BASE_IDX 1 |
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| 288 | #define mmDAGB1_RDCLI4 0x0084 |
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| 289 | #define mmDAGB1_RDCLI4_BASE_IDX 1 |
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| 290 | #define mmDAGB1_RDCLI5 0x0085 |
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| 291 | #define mmDAGB1_RDCLI5_BASE_IDX 1 |
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| 292 | #define mmDAGB1_RDCLI6 0x0086 |
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| 293 | #define mmDAGB1_RDCLI6_BASE_IDX 1 |
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| 294 | #define mmDAGB1_RDCLI7 0x0087 |
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| 295 | #define mmDAGB1_RDCLI7_BASE_IDX 1 |
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| 296 | #define mmDAGB1_RDCLI8 0x0088 |
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| 297 | #define mmDAGB1_RDCLI8_BASE_IDX 1 |
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| 298 | #define mmDAGB1_RDCLI9 0x0089 |
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| 299 | #define mmDAGB1_RDCLI9_BASE_IDX 1 |
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| 300 | #define mmDAGB1_RDCLI10 0x008a |
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| 301 | #define mmDAGB1_RDCLI10_BASE_IDX 1 |
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| 302 | #define mmDAGB1_RDCLI11 0x008b |
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| 303 | #define mmDAGB1_RDCLI11_BASE_IDX 1 |
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| 304 | #define mmDAGB1_RDCLI12 0x008c |
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| 305 | #define mmDAGB1_RDCLI12_BASE_IDX 1 |
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| 306 | #define mmDAGB1_RDCLI13 0x008d |
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| 307 | #define mmDAGB1_RDCLI13_BASE_IDX 1 |
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| 308 | #define mmDAGB1_RDCLI14 0x008e |
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| 309 | #define mmDAGB1_RDCLI14_BASE_IDX 1 |
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| 310 | #define mmDAGB1_RDCLI15 0x008f |
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| 311 | #define mmDAGB1_RDCLI15_BASE_IDX 1 |
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| 312 | #define mmDAGB1_RD_CNTL 0x0090 |
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| 313 | #define mmDAGB1_RD_CNTL_BASE_IDX 1 |
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| 314 | #define mmDAGB1_RD_GMI_CNTL 0x0091 |
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| 315 | #define mmDAGB1_RD_GMI_CNTL_BASE_IDX 1 |
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| 316 | #define mmDAGB1_RD_ADDR_DAGB 0x0092 |
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| 317 | #define mmDAGB1_RD_ADDR_DAGB_BASE_IDX 1 |
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| 318 | #define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST 0x0093 |
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| 319 | #define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 |
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| 320 | #define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER 0x0094 |
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| 321 | #define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 |
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| 322 | #define mmDAGB1_RD_CGTT_CLK_CTRL 0x0095 |
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| 323 | #define mmDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
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| 324 | #define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0x0096 |
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| 325 | #define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
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| 326 | #define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL 0x0097 |
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| 327 | #define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
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| 328 | #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0 0x0098 |
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| 329 | #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 |
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| 330 | #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0x0099 |
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| 331 | #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 |
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| 332 | #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1 0x009a |
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| 333 | #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 |
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| 334 | #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0x009b |
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| 335 | #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 |
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| 336 | #define mmDAGB1_RD_VC0_CNTL 0x009c |
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| 337 | #define mmDAGB1_RD_VC0_CNTL_BASE_IDX 1 |
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| 338 | #define mmDAGB1_RD_VC1_CNTL 0x009d |
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| 339 | #define mmDAGB1_RD_VC1_CNTL_BASE_IDX 1 |
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| 340 | #define mmDAGB1_RD_VC2_CNTL 0x009e |
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| 341 | #define mmDAGB1_RD_VC2_CNTL_BASE_IDX 1 |
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| 342 | #define mmDAGB1_RD_VC3_CNTL 0x009f |
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| 343 | #define mmDAGB1_RD_VC3_CNTL_BASE_IDX 1 |
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| 344 | #define mmDAGB1_RD_VC4_CNTL 0x00a0 |
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| 345 | #define mmDAGB1_RD_VC4_CNTL_BASE_IDX 1 |
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| 346 | #define mmDAGB1_RD_VC5_CNTL 0x00a1 |
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| 347 | #define mmDAGB1_RD_VC5_CNTL_BASE_IDX 1 |
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| 348 | #define mmDAGB1_RD_VC6_CNTL 0x00a2 |
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| 349 | #define mmDAGB1_RD_VC6_CNTL_BASE_IDX 1 |
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| 350 | #define mmDAGB1_RD_VC7_CNTL 0x00a3 |
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| 351 | #define mmDAGB1_RD_VC7_CNTL_BASE_IDX 1 |
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| 352 | #define mmDAGB1_RD_CNTL_MISC 0x00a4 |
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| 353 | #define mmDAGB1_RD_CNTL_MISC_BASE_IDX 1 |
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| 354 | #define mmDAGB1_RD_TLB_CREDIT 0x00a5 |
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| 355 | #define mmDAGB1_RD_TLB_CREDIT_BASE_IDX 1 |
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| 356 | #define mmDAGB1_RDCLI_ASK_PENDING 0x00a6 |
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| 357 | #define mmDAGB1_RDCLI_ASK_PENDING_BASE_IDX 1 |
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| 358 | #define mmDAGB1_RDCLI_GO_PENDING 0x00a7 |
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| 359 | #define mmDAGB1_RDCLI_GO_PENDING_BASE_IDX 1 |
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| 360 | #define mmDAGB1_RDCLI_GBLSEND_PENDING 0x00a8 |
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| 361 | #define mmDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX 1 |
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| 362 | #define mmDAGB1_RDCLI_TLB_PENDING 0x00a9 |
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| 363 | #define mmDAGB1_RDCLI_TLB_PENDING_BASE_IDX 1 |
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| 364 | #define mmDAGB1_RDCLI_OARB_PENDING 0x00aa |
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| 365 | #define mmDAGB1_RDCLI_OARB_PENDING_BASE_IDX 1 |
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| 366 | #define mmDAGB1_RDCLI_OSD_PENDING 0x00ab |
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| 367 | #define mmDAGB1_RDCLI_OSD_PENDING_BASE_IDX 1 |
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| 368 | #define mmDAGB1_WRCLI0 0x00ac |
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| 369 | #define mmDAGB1_WRCLI0_BASE_IDX 1 |
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| 370 | #define mmDAGB1_WRCLI1 0x00ad |
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| 371 | #define mmDAGB1_WRCLI1_BASE_IDX 1 |
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| 372 | #define mmDAGB1_WRCLI2 0x00ae |
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| 373 | #define mmDAGB1_WRCLI2_BASE_IDX 1 |
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| 374 | #define mmDAGB1_WRCLI3 0x00af |
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| 375 | #define mmDAGB1_WRCLI3_BASE_IDX 1 |
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| 376 | #define mmDAGB1_WRCLI4 0x00b0 |
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| 377 | #define mmDAGB1_WRCLI4_BASE_IDX 1 |
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| 378 | #define mmDAGB1_WRCLI5 0x00b1 |
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| 379 | #define mmDAGB1_WRCLI5_BASE_IDX 1 |
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| 380 | #define mmDAGB1_WRCLI6 0x00b2 |
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| 381 | #define mmDAGB1_WRCLI6_BASE_IDX 1 |
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| 382 | #define mmDAGB1_WRCLI7 0x00b3 |
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| 383 | #define mmDAGB1_WRCLI7_BASE_IDX 1 |
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| 384 | #define mmDAGB1_WRCLI8 0x00b4 |
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| 385 | #define mmDAGB1_WRCLI8_BASE_IDX 1 |
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| 386 | #define mmDAGB1_WRCLI9 0x00b5 |
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| 387 | #define mmDAGB1_WRCLI9_BASE_IDX 1 |
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| 388 | #define mmDAGB1_WRCLI10 0x00b6 |
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| 389 | #define mmDAGB1_WRCLI10_BASE_IDX 1 |
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| 390 | #define mmDAGB1_WRCLI11 0x00b7 |
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| 391 | #define mmDAGB1_WRCLI11_BASE_IDX 1 |
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| 392 | #define mmDAGB1_WRCLI12 0x00b8 |
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| 393 | #define mmDAGB1_WRCLI12_BASE_IDX 1 |
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| 394 | #define mmDAGB1_WRCLI13 0x00b9 |
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| 395 | #define mmDAGB1_WRCLI13_BASE_IDX 1 |
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| 396 | #define mmDAGB1_WRCLI14 0x00ba |
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| 397 | #define mmDAGB1_WRCLI14_BASE_IDX 1 |
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| 398 | #define mmDAGB1_WRCLI15 0x00bb |
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| 399 | #define mmDAGB1_WRCLI15_BASE_IDX 1 |
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| 400 | #define mmDAGB1_WR_CNTL 0x00bc |
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| 401 | #define mmDAGB1_WR_CNTL_BASE_IDX 1 |
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| 402 | #define mmDAGB1_WR_GMI_CNTL 0x00bd |
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| 403 | #define mmDAGB1_WR_GMI_CNTL_BASE_IDX 1 |
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| 404 | #define mmDAGB1_WR_ADDR_DAGB 0x00be |
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| 405 | #define mmDAGB1_WR_ADDR_DAGB_BASE_IDX 1 |
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| 406 | #define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST 0x00bf |
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| 407 | #define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 |
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| 408 | #define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER 0x00c0 |
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| 409 | #define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 |
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| 410 | #define mmDAGB1_WR_CGTT_CLK_CTRL 0x00c1 |
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| 411 | #define mmDAGB1_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
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| 412 | #define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL 0x00c2 |
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| 413 | #define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
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| 414 | #define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL 0x00c3 |
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| 415 | #define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
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| 416 | #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0 0x00c4 |
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| 417 | #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 |
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| 418 | #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0 0x00c5 |
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| 419 | #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 |
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| 420 | #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1 0x00c6 |
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| 421 | #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 |
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| 422 | #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1 0x00c7 |
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| 423 | #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 |
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| 424 | #define mmDAGB1_WR_DATA_DAGB 0x00c8 |
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| 425 | #define mmDAGB1_WR_DATA_DAGB_BASE_IDX 1 |
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| 426 | #define mmDAGB1_WR_DATA_DAGB_MAX_BURST0 0x00c9 |
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| 427 | #define mmDAGB1_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 |
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| 428 | #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0 0x00ca |
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| 429 | #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 |
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| 430 | #define mmDAGB1_WR_DATA_DAGB_MAX_BURST1 0x00cb |
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| 431 | #define mmDAGB1_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 |
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| 432 | #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1 0x00cc |
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| 433 | #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 |
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| 434 | #define mmDAGB1_WR_VC0_CNTL 0x00cd |
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| 435 | #define mmDAGB1_WR_VC0_CNTL_BASE_IDX 1 |
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| 436 | #define mmDAGB1_WR_VC1_CNTL 0x00ce |
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| 437 | #define mmDAGB1_WR_VC1_CNTL_BASE_IDX 1 |
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| 438 | #define mmDAGB1_WR_VC2_CNTL 0x00cf |
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| 439 | #define mmDAGB1_WR_VC2_CNTL_BASE_IDX 1 |
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| 440 | #define mmDAGB1_WR_VC3_CNTL 0x00d0 |
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| 441 | #define mmDAGB1_WR_VC3_CNTL_BASE_IDX 1 |
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| 442 | #define mmDAGB1_WR_VC4_CNTL 0x00d1 |
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| 443 | #define mmDAGB1_WR_VC4_CNTL_BASE_IDX 1 |
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| 444 | #define mmDAGB1_WR_VC5_CNTL 0x00d2 |
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| 445 | #define mmDAGB1_WR_VC5_CNTL_BASE_IDX 1 |
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| 446 | #define mmDAGB1_WR_VC6_CNTL 0x00d3 |
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| 447 | #define mmDAGB1_WR_VC6_CNTL_BASE_IDX 1 |
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| 448 | #define mmDAGB1_WR_VC7_CNTL 0x00d4 |
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| 449 | #define mmDAGB1_WR_VC7_CNTL_BASE_IDX 1 |
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| 450 | #define mmDAGB1_WR_CNTL_MISC 0x00d5 |
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| 451 | #define mmDAGB1_WR_CNTL_MISC_BASE_IDX 1 |
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| 452 | #define mmDAGB1_WR_TLB_CREDIT 0x00d6 |
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| 453 | #define mmDAGB1_WR_TLB_CREDIT_BASE_IDX 1 |
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| 454 | #define mmDAGB1_WR_DATA_CREDIT 0x00d7 |
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| 455 | #define mmDAGB1_WR_DATA_CREDIT_BASE_IDX 1 |
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| 456 | #define mmDAGB1_WR_MISC_CREDIT 0x00d8 |
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| 457 | #define mmDAGB1_WR_MISC_CREDIT_BASE_IDX 1 |
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| 458 | #define mmDAGB1_WRCLI_ASK_PENDING 0x00dd |
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| 459 | #define mmDAGB1_WRCLI_ASK_PENDING_BASE_IDX 1 |
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| 460 | #define mmDAGB1_WRCLI_GO_PENDING 0x00de |
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| 461 | #define mmDAGB1_WRCLI_GO_PENDING_BASE_IDX 1 |
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| 462 | #define mmDAGB1_WRCLI_GBLSEND_PENDING 0x00df |
|---|
| 463 | #define mmDAGB1_WRCLI_GBLSEND_PENDING_BASE_IDX 1 |
|---|
| 464 | #define mmDAGB1_WRCLI_TLB_PENDING 0x00e0 |
|---|
| 465 | #define mmDAGB1_WRCLI_TLB_PENDING_BASE_IDX 1 |
|---|
| 466 | #define mmDAGB1_WRCLI_OARB_PENDING 0x00e1 |
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| 467 | #define mmDAGB1_WRCLI_OARB_PENDING_BASE_IDX 1 |
|---|
| 468 | #define mmDAGB1_WRCLI_OSD_PENDING 0x00e2 |
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| 469 | #define mmDAGB1_WRCLI_OSD_PENDING_BASE_IDX 1 |
|---|
| 470 | #define mmDAGB1_WRCLI_DBUS_ASK_PENDING 0x00e3 |
|---|
| 471 | #define mmDAGB1_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 |
|---|
| 472 | #define mmDAGB1_WRCLI_DBUS_GO_PENDING 0x00e4 |
|---|
| 473 | #define mmDAGB1_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 |
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| 474 | #define mmDAGB1_DAGB_DLY 0x00e5 |
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| 475 | #define mmDAGB1_DAGB_DLY_BASE_IDX 1 |
|---|
| 476 | #define mmDAGB1_CNTL_MISC 0x00e6 |
|---|
| 477 | #define mmDAGB1_CNTL_MISC_BASE_IDX 1 |
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| 478 | #define mmDAGB1_CNTL_MISC2 0x00e7 |
|---|
| 479 | #define mmDAGB1_CNTL_MISC2_BASE_IDX 1 |
|---|
| 480 | #define mmDAGB1_FIFO_EMPTY 0x00e8 |
|---|
| 481 | #define mmDAGB1_FIFO_EMPTY_BASE_IDX 1 |
|---|
| 482 | #define mmDAGB1_FIFO_FULL 0x00e9 |
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| 483 | #define mmDAGB1_FIFO_FULL_BASE_IDX 1 |
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| 484 | #define mmDAGB1_WR_CREDITS_FULL 0x00ea |
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| 485 | #define mmDAGB1_WR_CREDITS_FULL_BASE_IDX 1 |
|---|
| 486 | #define mmDAGB1_RD_CREDITS_FULL 0x00eb |
|---|
| 487 | #define mmDAGB1_RD_CREDITS_FULL_BASE_IDX 1 |
|---|
| 488 | #define mmDAGB1_PERFCOUNTER_LO 0x00ec |
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| 489 | #define mmDAGB1_PERFCOUNTER_LO_BASE_IDX 1 |
|---|
| 490 | #define mmDAGB1_PERFCOUNTER_HI 0x00ed |
|---|
| 491 | #define mmDAGB1_PERFCOUNTER_HI_BASE_IDX 1 |
|---|
| 492 | #define mmDAGB1_PERFCOUNTER0_CFG 0x00ee |
|---|
| 493 | #define mmDAGB1_PERFCOUNTER0_CFG_BASE_IDX 1 |
|---|
| 494 | #define mmDAGB1_PERFCOUNTER1_CFG 0x00ef |
|---|
| 495 | #define mmDAGB1_PERFCOUNTER1_CFG_BASE_IDX 1 |
|---|
| 496 | #define mmDAGB1_PERFCOUNTER2_CFG 0x00f0 |
|---|
| 497 | #define mmDAGB1_PERFCOUNTER2_CFG_BASE_IDX 1 |
|---|
| 498 | #define mmDAGB1_PERFCOUNTER_RSLT_CNTL 0x00f1 |
|---|
| 499 | #define mmDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
|---|
| 500 | #define mmDAGB1_RESERVE0 0x00f2 |
|---|
| 501 | #define mmDAGB1_RESERVE0_BASE_IDX 1 |
|---|
| 502 | #define mmDAGB1_RESERVE1 0x00f3 |
|---|
| 503 | #define mmDAGB1_RESERVE1_BASE_IDX 1 |
|---|
| 504 | #define mmDAGB1_RESERVE2 0x00f4 |
|---|
| 505 | #define mmDAGB1_RESERVE2_BASE_IDX 1 |
|---|
| 506 | #define mmDAGB1_RESERVE3 0x00f5 |
|---|
| 507 | #define mmDAGB1_RESERVE3_BASE_IDX 1 |
|---|
| 508 | #define mmDAGB1_RESERVE4 0x00f6 |
|---|
| 509 | #define mmDAGB1_RESERVE4_BASE_IDX 1 |
|---|
| 510 | #define mmDAGB1_RESERVE5 0x00f7 |
|---|
| 511 | #define mmDAGB1_RESERVE5_BASE_IDX 1 |
|---|
| 512 | #define mmDAGB1_RESERVE6 0x00f8 |
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| 513 | #define mmDAGB1_RESERVE6_BASE_IDX 1 |
|---|
| 514 | #define mmDAGB1_RESERVE7 0x00f9 |
|---|
| 515 | #define mmDAGB1_RESERVE7_BASE_IDX 1 |
|---|
| 516 | #define mmDAGB1_RESERVE8 0x00fa |
|---|
| 517 | #define mmDAGB1_RESERVE8_BASE_IDX 1 |
|---|
| 518 | #define mmDAGB1_RESERVE9 0x00fb |
|---|
| 519 | #define mmDAGB1_RESERVE9_BASE_IDX 1 |
|---|
| 520 | #define mmDAGB1_RESERVE10 0x00fc |
|---|
| 521 | #define mmDAGB1_RESERVE10_BASE_IDX 1 |
|---|
| 522 | #define mmDAGB1_RESERVE11 0x00fd |
|---|
| 523 | #define mmDAGB1_RESERVE11_BASE_IDX 1 |
|---|
| 524 | #define mmDAGB1_RESERVE12 0x00fe |
|---|
| 525 | #define mmDAGB1_RESERVE12_BASE_IDX 1 |
|---|
| 526 | #define mmDAGB1_RESERVE13 0x00ff |
|---|
| 527 | #define mmDAGB1_RESERVE13_BASE_IDX 1 |
|---|
| 528 | |
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| 529 | |
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| 530 | // addressBlock: mmhub_dagb_dagbdec2 |
|---|
| 531 | // base address: 0x68400 |
|---|
| 532 | #define mmDAGB2_RDCLI0 0x0100 |
|---|
| 533 | #define mmDAGB2_RDCLI0_BASE_IDX 1 |
|---|
| 534 | #define mmDAGB2_RDCLI1 0x0101 |
|---|
| 535 | #define mmDAGB2_RDCLI1_BASE_IDX 1 |
|---|
| 536 | #define mmDAGB2_RDCLI2 0x0102 |
|---|
| 537 | #define mmDAGB2_RDCLI2_BASE_IDX 1 |
|---|
| 538 | #define mmDAGB2_RDCLI3 0x0103 |
|---|
| 539 | #define mmDAGB2_RDCLI3_BASE_IDX 1 |
|---|
| 540 | #define mmDAGB2_RDCLI4 0x0104 |
|---|
| 541 | #define mmDAGB2_RDCLI4_BASE_IDX 1 |
|---|
| 542 | #define mmDAGB2_RDCLI5 0x0105 |
|---|
| 543 | #define mmDAGB2_RDCLI5_BASE_IDX 1 |
|---|
| 544 | #define mmDAGB2_RDCLI6 0x0106 |
|---|
| 545 | #define mmDAGB2_RDCLI6_BASE_IDX 1 |
|---|
| 546 | #define mmDAGB2_RDCLI7 0x0107 |
|---|
| 547 | #define mmDAGB2_RDCLI7_BASE_IDX 1 |
|---|
| 548 | #define mmDAGB2_RDCLI8 0x0108 |
|---|
| 549 | #define mmDAGB2_RDCLI8_BASE_IDX 1 |
|---|
| 550 | #define mmDAGB2_RDCLI9 0x0109 |
|---|
| 551 | #define mmDAGB2_RDCLI9_BASE_IDX 1 |
|---|
| 552 | #define mmDAGB2_RDCLI10 0x010a |
|---|
| 553 | #define mmDAGB2_RDCLI10_BASE_IDX 1 |
|---|
| 554 | #define mmDAGB2_RDCLI11 0x010b |
|---|
| 555 | #define mmDAGB2_RDCLI11_BASE_IDX 1 |
|---|
| 556 | #define mmDAGB2_RDCLI12 0x010c |
|---|
| 557 | #define mmDAGB2_RDCLI12_BASE_IDX 1 |
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| 558 | #define mmDAGB2_RDCLI13 0x010d |
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| 559 | #define mmDAGB2_RDCLI13_BASE_IDX 1 |
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| 560 | #define mmDAGB2_RDCLI14 0x010e |
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| 561 | #define mmDAGB2_RDCLI14_BASE_IDX 1 |
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| 562 | #define mmDAGB2_RDCLI15 0x010f |
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| 563 | #define mmDAGB2_RDCLI15_BASE_IDX 1 |
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| 564 | #define mmDAGB2_RD_CNTL 0x0110 |
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| 565 | #define mmDAGB2_RD_CNTL_BASE_IDX 1 |
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| 566 | #define mmDAGB2_RD_GMI_CNTL 0x0111 |
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| 567 | #define mmDAGB2_RD_GMI_CNTL_BASE_IDX 1 |
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| 568 | #define mmDAGB2_RD_ADDR_DAGB 0x0112 |
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| 569 | #define mmDAGB2_RD_ADDR_DAGB_BASE_IDX 1 |
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| 570 | #define mmDAGB2_RD_OUTPUT_DAGB_MAX_BURST 0x0113 |
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| 571 | #define mmDAGB2_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 |
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| 572 | #define mmDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER 0x0114 |
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| 573 | #define mmDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 |
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| 574 | #define mmDAGB2_RD_CGTT_CLK_CTRL 0x0115 |
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| 575 | #define mmDAGB2_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
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| 576 | #define mmDAGB2_L1TLB_RD_CGTT_CLK_CTRL 0x0116 |
|---|
| 577 | #define mmDAGB2_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
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| 578 | #define mmDAGB2_ATCVM_RD_CGTT_CLK_CTRL 0x0117 |
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| 579 | #define mmDAGB2_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
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| 580 | #define mmDAGB2_RD_ADDR_DAGB_MAX_BURST0 0x0118 |
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| 581 | #define mmDAGB2_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 |
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| 582 | #define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER0 0x0119 |
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| 583 | #define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 |
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| 584 | #define mmDAGB2_RD_ADDR_DAGB_MAX_BURST1 0x011a |
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| 585 | #define mmDAGB2_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 |
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| 586 | #define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER1 0x011b |
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| 587 | #define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 |
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| 588 | #define mmDAGB2_RD_VC0_CNTL 0x011c |
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| 589 | #define mmDAGB2_RD_VC0_CNTL_BASE_IDX 1 |
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| 590 | #define mmDAGB2_RD_VC1_CNTL 0x011d |
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| 591 | #define mmDAGB2_RD_VC1_CNTL_BASE_IDX 1 |
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| 592 | #define mmDAGB2_RD_VC2_CNTL 0x011e |
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| 593 | #define mmDAGB2_RD_VC2_CNTL_BASE_IDX 1 |
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| 594 | #define mmDAGB2_RD_VC3_CNTL 0x011f |
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| 595 | #define mmDAGB2_RD_VC3_CNTL_BASE_IDX 1 |
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| 596 | #define mmDAGB2_RD_VC4_CNTL 0x0120 |
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| 597 | #define mmDAGB2_RD_VC4_CNTL_BASE_IDX 1 |
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| 598 | #define mmDAGB2_RD_VC5_CNTL 0x0121 |
|---|
| 599 | #define mmDAGB2_RD_VC5_CNTL_BASE_IDX 1 |
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| 600 | #define mmDAGB2_RD_VC6_CNTL 0x0122 |
|---|
| 601 | #define mmDAGB2_RD_VC6_CNTL_BASE_IDX 1 |
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| 602 | #define mmDAGB2_RD_VC7_CNTL 0x0123 |
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| 603 | #define mmDAGB2_RD_VC7_CNTL_BASE_IDX 1 |
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| 604 | #define mmDAGB2_RD_CNTL_MISC 0x0124 |
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| 605 | #define mmDAGB2_RD_CNTL_MISC_BASE_IDX 1 |
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| 606 | #define mmDAGB2_RD_TLB_CREDIT 0x0125 |
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| 607 | #define mmDAGB2_RD_TLB_CREDIT_BASE_IDX 1 |
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| 608 | #define mmDAGB2_RDCLI_ASK_PENDING 0x0126 |
|---|
| 609 | #define mmDAGB2_RDCLI_ASK_PENDING_BASE_IDX 1 |
|---|
| 610 | #define mmDAGB2_RDCLI_GO_PENDING 0x0127 |
|---|
| 611 | #define mmDAGB2_RDCLI_GO_PENDING_BASE_IDX 1 |
|---|
| 612 | #define mmDAGB2_RDCLI_GBLSEND_PENDING 0x0128 |
|---|
| 613 | #define mmDAGB2_RDCLI_GBLSEND_PENDING_BASE_IDX 1 |
|---|
| 614 | #define mmDAGB2_RDCLI_TLB_PENDING 0x0129 |
|---|
| 615 | #define mmDAGB2_RDCLI_TLB_PENDING_BASE_IDX 1 |
|---|
| 616 | #define mmDAGB2_RDCLI_OARB_PENDING 0x012a |
|---|
| 617 | #define mmDAGB2_RDCLI_OARB_PENDING_BASE_IDX 1 |
|---|
| 618 | #define mmDAGB2_RDCLI_OSD_PENDING 0x012b |
|---|
| 619 | #define mmDAGB2_RDCLI_OSD_PENDING_BASE_IDX 1 |
|---|
| 620 | #define mmDAGB2_WRCLI0 0x012c |
|---|
| 621 | #define mmDAGB2_WRCLI0_BASE_IDX 1 |
|---|
| 622 | #define mmDAGB2_WRCLI1 0x012d |
|---|
| 623 | #define mmDAGB2_WRCLI1_BASE_IDX 1 |
|---|
| 624 | #define mmDAGB2_WRCLI2 0x012e |
|---|
| 625 | #define mmDAGB2_WRCLI2_BASE_IDX 1 |
|---|
| 626 | #define mmDAGB2_WRCLI3 0x012f |
|---|
| 627 | #define mmDAGB2_WRCLI3_BASE_IDX 1 |
|---|
| 628 | #define mmDAGB2_WRCLI4 0x0130 |
|---|
| 629 | #define mmDAGB2_WRCLI4_BASE_IDX 1 |
|---|
| 630 | #define mmDAGB2_WRCLI5 0x0131 |
|---|
| 631 | #define mmDAGB2_WRCLI5_BASE_IDX 1 |
|---|
| 632 | #define mmDAGB2_WRCLI6 0x0132 |
|---|
| 633 | #define mmDAGB2_WRCLI6_BASE_IDX 1 |
|---|
| 634 | #define mmDAGB2_WRCLI7 0x0133 |
|---|
| 635 | #define mmDAGB2_WRCLI7_BASE_IDX 1 |
|---|
| 636 | #define mmDAGB2_WRCLI8 0x0134 |
|---|
| 637 | #define mmDAGB2_WRCLI8_BASE_IDX 1 |
|---|
| 638 | #define mmDAGB2_WRCLI9 0x0135 |
|---|
| 639 | #define mmDAGB2_WRCLI9_BASE_IDX 1 |
|---|
| 640 | #define mmDAGB2_WRCLI10 0x0136 |
|---|
| 641 | #define mmDAGB2_WRCLI10_BASE_IDX 1 |
|---|
| 642 | #define mmDAGB2_WRCLI11 0x0137 |
|---|
| 643 | #define mmDAGB2_WRCLI11_BASE_IDX 1 |
|---|
| 644 | #define mmDAGB2_WRCLI12 0x0138 |
|---|
| 645 | #define mmDAGB2_WRCLI12_BASE_IDX 1 |
|---|
| 646 | #define mmDAGB2_WRCLI13 0x0139 |
|---|
| 647 | #define mmDAGB2_WRCLI13_BASE_IDX 1 |
|---|
| 648 | #define mmDAGB2_WRCLI14 0x013a |
|---|
| 649 | #define mmDAGB2_WRCLI14_BASE_IDX 1 |
|---|
| 650 | #define mmDAGB2_WRCLI15 0x013b |
|---|
| 651 | #define mmDAGB2_WRCLI15_BASE_IDX 1 |
|---|
| 652 | #define mmDAGB2_WR_CNTL 0x013c |
|---|
| 653 | #define mmDAGB2_WR_CNTL_BASE_IDX 1 |
|---|
| 654 | #define mmDAGB2_WR_GMI_CNTL 0x013d |
|---|
| 655 | #define mmDAGB2_WR_GMI_CNTL_BASE_IDX 1 |
|---|
| 656 | #define mmDAGB2_WR_ADDR_DAGB 0x013e |
|---|
| 657 | #define mmDAGB2_WR_ADDR_DAGB_BASE_IDX 1 |
|---|
| 658 | #define mmDAGB2_WR_OUTPUT_DAGB_MAX_BURST 0x013f |
|---|
| 659 | #define mmDAGB2_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 |
|---|
| 660 | #define mmDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER 0x0140 |
|---|
| 661 | #define mmDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 |
|---|
| 662 | #define mmDAGB2_WR_CGTT_CLK_CTRL 0x0141 |
|---|
| 663 | #define mmDAGB2_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 664 | #define mmDAGB2_L1TLB_WR_CGTT_CLK_CTRL 0x0142 |
|---|
| 665 | #define mmDAGB2_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 666 | #define mmDAGB2_ATCVM_WR_CGTT_CLK_CTRL 0x0143 |
|---|
| 667 | #define mmDAGB2_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 668 | #define mmDAGB2_WR_ADDR_DAGB_MAX_BURST0 0x0144 |
|---|
| 669 | #define mmDAGB2_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 |
|---|
| 670 | #define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER0 0x0145 |
|---|
| 671 | #define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 |
|---|
| 672 | #define mmDAGB2_WR_ADDR_DAGB_MAX_BURST1 0x0146 |
|---|
| 673 | #define mmDAGB2_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 |
|---|
| 674 | #define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER1 0x0147 |
|---|
| 675 | #define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 |
|---|
| 676 | #define mmDAGB2_WR_DATA_DAGB 0x0148 |
|---|
| 677 | #define mmDAGB2_WR_DATA_DAGB_BASE_IDX 1 |
|---|
| 678 | #define mmDAGB2_WR_DATA_DAGB_MAX_BURST0 0x0149 |
|---|
| 679 | #define mmDAGB2_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 |
|---|
| 680 | #define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER0 0x014a |
|---|
| 681 | #define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 |
|---|
| 682 | #define mmDAGB2_WR_DATA_DAGB_MAX_BURST1 0x014b |
|---|
| 683 | #define mmDAGB2_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 |
|---|
| 684 | #define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER1 0x014c |
|---|
| 685 | #define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 |
|---|
| 686 | #define mmDAGB2_WR_VC0_CNTL 0x014d |
|---|
| 687 | #define mmDAGB2_WR_VC0_CNTL_BASE_IDX 1 |
|---|
| 688 | #define mmDAGB2_WR_VC1_CNTL 0x014e |
|---|
| 689 | #define mmDAGB2_WR_VC1_CNTL_BASE_IDX 1 |
|---|
| 690 | #define mmDAGB2_WR_VC2_CNTL 0x014f |
|---|
| 691 | #define mmDAGB2_WR_VC2_CNTL_BASE_IDX 1 |
|---|
| 692 | #define mmDAGB2_WR_VC3_CNTL 0x0150 |
|---|
| 693 | #define mmDAGB2_WR_VC3_CNTL_BASE_IDX 1 |
|---|
| 694 | #define mmDAGB2_WR_VC4_CNTL 0x0151 |
|---|
| 695 | #define mmDAGB2_WR_VC4_CNTL_BASE_IDX 1 |
|---|
| 696 | #define mmDAGB2_WR_VC5_CNTL 0x0152 |
|---|
| 697 | #define mmDAGB2_WR_VC5_CNTL_BASE_IDX 1 |
|---|
| 698 | #define mmDAGB2_WR_VC6_CNTL 0x0153 |
|---|
| 699 | #define mmDAGB2_WR_VC6_CNTL_BASE_IDX 1 |
|---|
| 700 | #define mmDAGB2_WR_VC7_CNTL 0x0154 |
|---|
| 701 | #define mmDAGB2_WR_VC7_CNTL_BASE_IDX 1 |
|---|
| 702 | #define mmDAGB2_WR_CNTL_MISC 0x0155 |
|---|
| 703 | #define mmDAGB2_WR_CNTL_MISC_BASE_IDX 1 |
|---|
| 704 | #define mmDAGB2_WR_TLB_CREDIT 0x0156 |
|---|
| 705 | #define mmDAGB2_WR_TLB_CREDIT_BASE_IDX 1 |
|---|
| 706 | #define mmDAGB2_WR_DATA_CREDIT 0x0157 |
|---|
| 707 | #define mmDAGB2_WR_DATA_CREDIT_BASE_IDX 1 |
|---|
| 708 | #define mmDAGB2_WR_MISC_CREDIT 0x0158 |
|---|
| 709 | #define mmDAGB2_WR_MISC_CREDIT_BASE_IDX 1 |
|---|
| 710 | #define mmDAGB2_WRCLI_ASK_PENDING 0x015d |
|---|
| 711 | #define mmDAGB2_WRCLI_ASK_PENDING_BASE_IDX 1 |
|---|
| 712 | #define mmDAGB2_WRCLI_GO_PENDING 0x015e |
|---|
| 713 | #define mmDAGB2_WRCLI_GO_PENDING_BASE_IDX 1 |
|---|
| 714 | #define mmDAGB2_WRCLI_GBLSEND_PENDING 0x015f |
|---|
| 715 | #define mmDAGB2_WRCLI_GBLSEND_PENDING_BASE_IDX 1 |
|---|
| 716 | #define mmDAGB2_WRCLI_TLB_PENDING 0x0160 |
|---|
| 717 | #define mmDAGB2_WRCLI_TLB_PENDING_BASE_IDX 1 |
|---|
| 718 | #define mmDAGB2_WRCLI_OARB_PENDING 0x0161 |
|---|
| 719 | #define mmDAGB2_WRCLI_OARB_PENDING_BASE_IDX 1 |
|---|
| 720 | #define mmDAGB2_WRCLI_OSD_PENDING 0x0162 |
|---|
| 721 | #define mmDAGB2_WRCLI_OSD_PENDING_BASE_IDX 1 |
|---|
| 722 | #define mmDAGB2_WRCLI_DBUS_ASK_PENDING 0x0163 |
|---|
| 723 | #define mmDAGB2_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 |
|---|
| 724 | #define mmDAGB2_WRCLI_DBUS_GO_PENDING 0x0164 |
|---|
| 725 | #define mmDAGB2_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 |
|---|
| 726 | #define mmDAGB2_DAGB_DLY 0x0165 |
|---|
| 727 | #define mmDAGB2_DAGB_DLY_BASE_IDX 1 |
|---|
| 728 | #define mmDAGB2_CNTL_MISC 0x0166 |
|---|
| 729 | #define mmDAGB2_CNTL_MISC_BASE_IDX 1 |
|---|
| 730 | #define mmDAGB2_CNTL_MISC2 0x0167 |
|---|
| 731 | #define mmDAGB2_CNTL_MISC2_BASE_IDX 1 |
|---|
| 732 | #define mmDAGB2_FIFO_EMPTY 0x0168 |
|---|
| 733 | #define mmDAGB2_FIFO_EMPTY_BASE_IDX 1 |
|---|
| 734 | #define mmDAGB2_FIFO_FULL 0x0169 |
|---|
| 735 | #define mmDAGB2_FIFO_FULL_BASE_IDX 1 |
|---|
| 736 | #define mmDAGB2_WR_CREDITS_FULL 0x016a |
|---|
| 737 | #define mmDAGB2_WR_CREDITS_FULL_BASE_IDX 1 |
|---|
| 738 | #define mmDAGB2_RD_CREDITS_FULL 0x016b |
|---|
| 739 | #define mmDAGB2_RD_CREDITS_FULL_BASE_IDX 1 |
|---|
| 740 | #define mmDAGB2_PERFCOUNTER_LO 0x016c |
|---|
| 741 | #define mmDAGB2_PERFCOUNTER_LO_BASE_IDX 1 |
|---|
| 742 | #define mmDAGB2_PERFCOUNTER_HI 0x016d |
|---|
| 743 | #define mmDAGB2_PERFCOUNTER_HI_BASE_IDX 1 |
|---|
| 744 | #define mmDAGB2_PERFCOUNTER0_CFG 0x016e |
|---|
| 745 | #define mmDAGB2_PERFCOUNTER0_CFG_BASE_IDX 1 |
|---|
| 746 | #define mmDAGB2_PERFCOUNTER1_CFG 0x016f |
|---|
| 747 | #define mmDAGB2_PERFCOUNTER1_CFG_BASE_IDX 1 |
|---|
| 748 | #define mmDAGB2_PERFCOUNTER2_CFG 0x0170 |
|---|
| 749 | #define mmDAGB2_PERFCOUNTER2_CFG_BASE_IDX 1 |
|---|
| 750 | #define mmDAGB2_PERFCOUNTER_RSLT_CNTL 0x0171 |
|---|
| 751 | #define mmDAGB2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
|---|
| 752 | #define mmDAGB2_RESERVE0 0x0172 |
|---|
| 753 | #define mmDAGB2_RESERVE0_BASE_IDX 1 |
|---|
| 754 | #define mmDAGB2_RESERVE1 0x0173 |
|---|
| 755 | #define mmDAGB2_RESERVE1_BASE_IDX 1 |
|---|
| 756 | #define mmDAGB2_RESERVE2 0x0174 |
|---|
| 757 | #define mmDAGB2_RESERVE2_BASE_IDX 1 |
|---|
| 758 | #define mmDAGB2_RESERVE3 0x0175 |
|---|
| 759 | #define mmDAGB2_RESERVE3_BASE_IDX 1 |
|---|
| 760 | #define mmDAGB2_RESERVE4 0x0176 |
|---|
| 761 | #define mmDAGB2_RESERVE4_BASE_IDX 1 |
|---|
| 762 | #define mmDAGB2_RESERVE5 0x0177 |
|---|
| 763 | #define mmDAGB2_RESERVE5_BASE_IDX 1 |
|---|
| 764 | #define mmDAGB2_RESERVE6 0x0178 |
|---|
| 765 | #define mmDAGB2_RESERVE6_BASE_IDX 1 |
|---|
| 766 | #define mmDAGB2_RESERVE7 0x0179 |
|---|
| 767 | #define mmDAGB2_RESERVE7_BASE_IDX 1 |
|---|
| 768 | #define mmDAGB2_RESERVE8 0x017a |
|---|
| 769 | #define mmDAGB2_RESERVE8_BASE_IDX 1 |
|---|
| 770 | #define mmDAGB2_RESERVE9 0x017b |
|---|
| 771 | #define mmDAGB2_RESERVE9_BASE_IDX 1 |
|---|
| 772 | #define mmDAGB2_RESERVE10 0x017c |
|---|
| 773 | #define mmDAGB2_RESERVE10_BASE_IDX 1 |
|---|
| 774 | #define mmDAGB2_RESERVE11 0x017d |
|---|
| 775 | #define mmDAGB2_RESERVE11_BASE_IDX 1 |
|---|
| 776 | #define mmDAGB2_RESERVE12 0x017e |
|---|
| 777 | #define mmDAGB2_RESERVE12_BASE_IDX 1 |
|---|
| 778 | #define mmDAGB2_RESERVE13 0x017f |
|---|
| 779 | #define mmDAGB2_RESERVE13_BASE_IDX 1 |
|---|
| 780 | |
|---|
| 781 | |
|---|
| 782 | // addressBlock: mmhub_dagb_dagbdec3 |
|---|
| 783 | // base address: 0x68600 |
|---|
| 784 | #define mmDAGB3_RDCLI0 0x0180 |
|---|
| 785 | #define mmDAGB3_RDCLI0_BASE_IDX 1 |
|---|
| 786 | #define mmDAGB3_RDCLI1 0x0181 |
|---|
| 787 | #define mmDAGB3_RDCLI1_BASE_IDX 1 |
|---|
| 788 | #define mmDAGB3_RDCLI2 0x0182 |
|---|
| 789 | #define mmDAGB3_RDCLI2_BASE_IDX 1 |
|---|
| 790 | #define mmDAGB3_RDCLI3 0x0183 |
|---|
| 791 | #define mmDAGB3_RDCLI3_BASE_IDX 1 |
|---|
| 792 | #define mmDAGB3_RDCLI4 0x0184 |
|---|
| 793 | #define mmDAGB3_RDCLI4_BASE_IDX 1 |
|---|
| 794 | #define mmDAGB3_RDCLI5 0x0185 |
|---|
| 795 | #define mmDAGB3_RDCLI5_BASE_IDX 1 |
|---|
| 796 | #define mmDAGB3_RDCLI6 0x0186 |
|---|
| 797 | #define mmDAGB3_RDCLI6_BASE_IDX 1 |
|---|
| 798 | #define mmDAGB3_RDCLI7 0x0187 |
|---|
| 799 | #define mmDAGB3_RDCLI7_BASE_IDX 1 |
|---|
| 800 | #define mmDAGB3_RDCLI8 0x0188 |
|---|
| 801 | #define mmDAGB3_RDCLI8_BASE_IDX 1 |
|---|
| 802 | #define mmDAGB3_RDCLI9 0x0189 |
|---|
| 803 | #define mmDAGB3_RDCLI9_BASE_IDX 1 |
|---|
| 804 | #define mmDAGB3_RDCLI10 0x018a |
|---|
| 805 | #define mmDAGB3_RDCLI10_BASE_IDX 1 |
|---|
| 806 | #define mmDAGB3_RDCLI11 0x018b |
|---|
| 807 | #define mmDAGB3_RDCLI11_BASE_IDX 1 |
|---|
| 808 | #define mmDAGB3_RDCLI12 0x018c |
|---|
| 809 | #define mmDAGB3_RDCLI12_BASE_IDX 1 |
|---|
| 810 | #define mmDAGB3_RDCLI13 0x018d |
|---|
| 811 | #define mmDAGB3_RDCLI13_BASE_IDX 1 |
|---|
| 812 | #define mmDAGB3_RDCLI14 0x018e |
|---|
| 813 | #define mmDAGB3_RDCLI14_BASE_IDX 1 |
|---|
| 814 | #define mmDAGB3_RDCLI15 0x018f |
|---|
| 815 | #define mmDAGB3_RDCLI15_BASE_IDX 1 |
|---|
| 816 | #define mmDAGB3_RD_CNTL 0x0190 |
|---|
| 817 | #define mmDAGB3_RD_CNTL_BASE_IDX 1 |
|---|
| 818 | #define mmDAGB3_RD_GMI_CNTL 0x0191 |
|---|
| 819 | #define mmDAGB3_RD_GMI_CNTL_BASE_IDX 1 |
|---|
| 820 | #define mmDAGB3_RD_ADDR_DAGB 0x0192 |
|---|
| 821 | #define mmDAGB3_RD_ADDR_DAGB_BASE_IDX 1 |
|---|
| 822 | #define mmDAGB3_RD_OUTPUT_DAGB_MAX_BURST 0x0193 |
|---|
| 823 | #define mmDAGB3_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 |
|---|
| 824 | #define mmDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER 0x0194 |
|---|
| 825 | #define mmDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 |
|---|
| 826 | #define mmDAGB3_RD_CGTT_CLK_CTRL 0x0195 |
|---|
| 827 | #define mmDAGB3_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 828 | #define mmDAGB3_L1TLB_RD_CGTT_CLK_CTRL 0x0196 |
|---|
| 829 | #define mmDAGB3_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 830 | #define mmDAGB3_ATCVM_RD_CGTT_CLK_CTRL 0x0197 |
|---|
| 831 | #define mmDAGB3_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 832 | #define mmDAGB3_RD_ADDR_DAGB_MAX_BURST0 0x0198 |
|---|
| 833 | #define mmDAGB3_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 |
|---|
| 834 | #define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER0 0x0199 |
|---|
| 835 | #define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 |
|---|
| 836 | #define mmDAGB3_RD_ADDR_DAGB_MAX_BURST1 0x019a |
|---|
| 837 | #define mmDAGB3_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 |
|---|
| 838 | #define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER1 0x019b |
|---|
| 839 | #define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 |
|---|
| 840 | #define mmDAGB3_RD_VC0_CNTL 0x019c |
|---|
| 841 | #define mmDAGB3_RD_VC0_CNTL_BASE_IDX 1 |
|---|
| 842 | #define mmDAGB3_RD_VC1_CNTL 0x019d |
|---|
| 843 | #define mmDAGB3_RD_VC1_CNTL_BASE_IDX 1 |
|---|
| 844 | #define mmDAGB3_RD_VC2_CNTL 0x019e |
|---|
| 845 | #define mmDAGB3_RD_VC2_CNTL_BASE_IDX 1 |
|---|
| 846 | #define mmDAGB3_RD_VC3_CNTL 0x019f |
|---|
| 847 | #define mmDAGB3_RD_VC3_CNTL_BASE_IDX 1 |
|---|
| 848 | #define mmDAGB3_RD_VC4_CNTL 0x01a0 |
|---|
| 849 | #define mmDAGB3_RD_VC4_CNTL_BASE_IDX 1 |
|---|
| 850 | #define mmDAGB3_RD_VC5_CNTL 0x01a1 |
|---|
| 851 | #define mmDAGB3_RD_VC5_CNTL_BASE_IDX 1 |
|---|
| 852 | #define mmDAGB3_RD_VC6_CNTL 0x01a2 |
|---|
| 853 | #define mmDAGB3_RD_VC6_CNTL_BASE_IDX 1 |
|---|
| 854 | #define mmDAGB3_RD_VC7_CNTL 0x01a3 |
|---|
| 855 | #define mmDAGB3_RD_VC7_CNTL_BASE_IDX 1 |
|---|
| 856 | #define mmDAGB3_RD_CNTL_MISC 0x01a4 |
|---|
| 857 | #define mmDAGB3_RD_CNTL_MISC_BASE_IDX 1 |
|---|
| 858 | #define mmDAGB3_RD_TLB_CREDIT 0x01a5 |
|---|
| 859 | #define mmDAGB3_RD_TLB_CREDIT_BASE_IDX 1 |
|---|
| 860 | #define mmDAGB3_RDCLI_ASK_PENDING 0x01a6 |
|---|
| 861 | #define mmDAGB3_RDCLI_ASK_PENDING_BASE_IDX 1 |
|---|
| 862 | #define mmDAGB3_RDCLI_GO_PENDING 0x01a7 |
|---|
| 863 | #define mmDAGB3_RDCLI_GO_PENDING_BASE_IDX 1 |
|---|
| 864 | #define mmDAGB3_RDCLI_GBLSEND_PENDING 0x01a8 |
|---|
| 865 | #define mmDAGB3_RDCLI_GBLSEND_PENDING_BASE_IDX 1 |
|---|
| 866 | #define mmDAGB3_RDCLI_TLB_PENDING 0x01a9 |
|---|
| 867 | #define mmDAGB3_RDCLI_TLB_PENDING_BASE_IDX 1 |
|---|
| 868 | #define mmDAGB3_RDCLI_OARB_PENDING 0x01aa |
|---|
| 869 | #define mmDAGB3_RDCLI_OARB_PENDING_BASE_IDX 1 |
|---|
| 870 | #define mmDAGB3_RDCLI_OSD_PENDING 0x01ab |
|---|
| 871 | #define mmDAGB3_RDCLI_OSD_PENDING_BASE_IDX 1 |
|---|
| 872 | #define mmDAGB3_WRCLI0 0x01ac |
|---|
| 873 | #define mmDAGB3_WRCLI0_BASE_IDX 1 |
|---|
| 874 | #define mmDAGB3_WRCLI1 0x01ad |
|---|
| 875 | #define mmDAGB3_WRCLI1_BASE_IDX 1 |
|---|
| 876 | #define mmDAGB3_WRCLI2 0x01ae |
|---|
| 877 | #define mmDAGB3_WRCLI2_BASE_IDX 1 |
|---|
| 878 | #define mmDAGB3_WRCLI3 0x01af |
|---|
| 879 | #define mmDAGB3_WRCLI3_BASE_IDX 1 |
|---|
| 880 | #define mmDAGB3_WRCLI4 0x01b0 |
|---|
| 881 | #define mmDAGB3_WRCLI4_BASE_IDX 1 |
|---|
| 882 | #define mmDAGB3_WRCLI5 0x01b1 |
|---|
| 883 | #define mmDAGB3_WRCLI5_BASE_IDX 1 |
|---|
| 884 | #define mmDAGB3_WRCLI6 0x01b2 |
|---|
| 885 | #define mmDAGB3_WRCLI6_BASE_IDX 1 |
|---|
| 886 | #define mmDAGB3_WRCLI7 0x01b3 |
|---|
| 887 | #define mmDAGB3_WRCLI7_BASE_IDX 1 |
|---|
| 888 | #define mmDAGB3_WRCLI8 0x01b4 |
|---|
| 889 | #define mmDAGB3_WRCLI8_BASE_IDX 1 |
|---|
| 890 | #define mmDAGB3_WRCLI9 0x01b5 |
|---|
| 891 | #define mmDAGB3_WRCLI9_BASE_IDX 1 |
|---|
| 892 | #define mmDAGB3_WRCLI10 0x01b6 |
|---|
| 893 | #define mmDAGB3_WRCLI10_BASE_IDX 1 |
|---|
| 894 | #define mmDAGB3_WRCLI11 0x01b7 |
|---|
| 895 | #define mmDAGB3_WRCLI11_BASE_IDX 1 |
|---|
| 896 | #define mmDAGB3_WRCLI12 0x01b8 |
|---|
| 897 | #define mmDAGB3_WRCLI12_BASE_IDX 1 |
|---|
| 898 | #define mmDAGB3_WRCLI13 0x01b9 |
|---|
| 899 | #define mmDAGB3_WRCLI13_BASE_IDX 1 |
|---|
| 900 | #define mmDAGB3_WRCLI14 0x01ba |
|---|
| 901 | #define mmDAGB3_WRCLI14_BASE_IDX 1 |
|---|
| 902 | #define mmDAGB3_WRCLI15 0x01bb |
|---|
| 903 | #define mmDAGB3_WRCLI15_BASE_IDX 1 |
|---|
| 904 | #define mmDAGB3_WR_CNTL 0x01bc |
|---|
| 905 | #define mmDAGB3_WR_CNTL_BASE_IDX 1 |
|---|
| 906 | #define mmDAGB3_WR_GMI_CNTL 0x01bd |
|---|
| 907 | #define mmDAGB3_WR_GMI_CNTL_BASE_IDX 1 |
|---|
| 908 | #define mmDAGB3_WR_ADDR_DAGB 0x01be |
|---|
| 909 | #define mmDAGB3_WR_ADDR_DAGB_BASE_IDX 1 |
|---|
| 910 | #define mmDAGB3_WR_OUTPUT_DAGB_MAX_BURST 0x01bf |
|---|
| 911 | #define mmDAGB3_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 |
|---|
| 912 | #define mmDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER 0x01c0 |
|---|
| 913 | #define mmDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 |
|---|
| 914 | #define mmDAGB3_WR_CGTT_CLK_CTRL 0x01c1 |
|---|
| 915 | #define mmDAGB3_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 916 | #define mmDAGB3_L1TLB_WR_CGTT_CLK_CTRL 0x01c2 |
|---|
| 917 | #define mmDAGB3_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 918 | #define mmDAGB3_ATCVM_WR_CGTT_CLK_CTRL 0x01c3 |
|---|
| 919 | #define mmDAGB3_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 920 | #define mmDAGB3_WR_ADDR_DAGB_MAX_BURST0 0x01c4 |
|---|
| 921 | #define mmDAGB3_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 |
|---|
| 922 | #define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER0 0x01c5 |
|---|
| 923 | #define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 |
|---|
| 924 | #define mmDAGB3_WR_ADDR_DAGB_MAX_BURST1 0x01c6 |
|---|
| 925 | #define mmDAGB3_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 |
|---|
| 926 | #define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER1 0x01c7 |
|---|
| 927 | #define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 |
|---|
| 928 | #define mmDAGB3_WR_DATA_DAGB 0x01c8 |
|---|
| 929 | #define mmDAGB3_WR_DATA_DAGB_BASE_IDX 1 |
|---|
| 930 | #define mmDAGB3_WR_DATA_DAGB_MAX_BURST0 0x01c9 |
|---|
| 931 | #define mmDAGB3_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 |
|---|
| 932 | #define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER0 0x01ca |
|---|
| 933 | #define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 |
|---|
| 934 | #define mmDAGB3_WR_DATA_DAGB_MAX_BURST1 0x01cb |
|---|
| 935 | #define mmDAGB3_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 |
|---|
| 936 | #define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER1 0x01cc |
|---|
| 937 | #define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 |
|---|
| 938 | #define mmDAGB3_WR_VC0_CNTL 0x01cd |
|---|
| 939 | #define mmDAGB3_WR_VC0_CNTL_BASE_IDX 1 |
|---|
| 940 | #define mmDAGB3_WR_VC1_CNTL 0x01ce |
|---|
| 941 | #define mmDAGB3_WR_VC1_CNTL_BASE_IDX 1 |
|---|
| 942 | #define mmDAGB3_WR_VC2_CNTL 0x01cf |
|---|
| 943 | #define mmDAGB3_WR_VC2_CNTL_BASE_IDX 1 |
|---|
| 944 | #define mmDAGB3_WR_VC3_CNTL 0x01d0 |
|---|
| 945 | #define mmDAGB3_WR_VC3_CNTL_BASE_IDX 1 |
|---|
| 946 | #define mmDAGB3_WR_VC4_CNTL 0x01d1 |
|---|
| 947 | #define mmDAGB3_WR_VC4_CNTL_BASE_IDX 1 |
|---|
| 948 | #define mmDAGB3_WR_VC5_CNTL 0x01d2 |
|---|
| 949 | #define mmDAGB3_WR_VC5_CNTL_BASE_IDX 1 |
|---|
| 950 | #define mmDAGB3_WR_VC6_CNTL 0x01d3 |
|---|
| 951 | #define mmDAGB3_WR_VC6_CNTL_BASE_IDX 1 |
|---|
| 952 | #define mmDAGB3_WR_VC7_CNTL 0x01d4 |
|---|
| 953 | #define mmDAGB3_WR_VC7_CNTL_BASE_IDX 1 |
|---|
| 954 | #define mmDAGB3_WR_CNTL_MISC 0x01d5 |
|---|
| 955 | #define mmDAGB3_WR_CNTL_MISC_BASE_IDX 1 |
|---|
| 956 | #define mmDAGB3_WR_TLB_CREDIT 0x01d6 |
|---|
| 957 | #define mmDAGB3_WR_TLB_CREDIT_BASE_IDX 1 |
|---|
| 958 | #define mmDAGB3_WR_DATA_CREDIT 0x01d7 |
|---|
| 959 | #define mmDAGB3_WR_DATA_CREDIT_BASE_IDX 1 |
|---|
| 960 | #define mmDAGB3_WR_MISC_CREDIT 0x01d8 |
|---|
| 961 | #define mmDAGB3_WR_MISC_CREDIT_BASE_IDX 1 |
|---|
| 962 | #define mmDAGB3_WRCLI_ASK_PENDING 0x01dd |
|---|
| 963 | #define mmDAGB3_WRCLI_ASK_PENDING_BASE_IDX 1 |
|---|
| 964 | #define mmDAGB3_WRCLI_GO_PENDING 0x01de |
|---|
| 965 | #define mmDAGB3_WRCLI_GO_PENDING_BASE_IDX 1 |
|---|
| 966 | #define mmDAGB3_WRCLI_GBLSEND_PENDING 0x01df |
|---|
| 967 | #define mmDAGB3_WRCLI_GBLSEND_PENDING_BASE_IDX 1 |
|---|
| 968 | #define mmDAGB3_WRCLI_TLB_PENDING 0x01e0 |
|---|
| 969 | #define mmDAGB3_WRCLI_TLB_PENDING_BASE_IDX 1 |
|---|
| 970 | #define mmDAGB3_WRCLI_OARB_PENDING 0x01e1 |
|---|
| 971 | #define mmDAGB3_WRCLI_OARB_PENDING_BASE_IDX 1 |
|---|
| 972 | #define mmDAGB3_WRCLI_OSD_PENDING 0x01e2 |
|---|
| 973 | #define mmDAGB3_WRCLI_OSD_PENDING_BASE_IDX 1 |
|---|
| 974 | #define mmDAGB3_WRCLI_DBUS_ASK_PENDING 0x01e3 |
|---|
| 975 | #define mmDAGB3_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 |
|---|
| 976 | #define mmDAGB3_WRCLI_DBUS_GO_PENDING 0x01e4 |
|---|
| 977 | #define mmDAGB3_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 |
|---|
| 978 | #define mmDAGB3_DAGB_DLY 0x01e5 |
|---|
| 979 | #define mmDAGB3_DAGB_DLY_BASE_IDX 1 |
|---|
| 980 | #define mmDAGB3_CNTL_MISC 0x01e6 |
|---|
| 981 | #define mmDAGB3_CNTL_MISC_BASE_IDX 1 |
|---|
| 982 | #define mmDAGB3_CNTL_MISC2 0x01e7 |
|---|
| 983 | #define mmDAGB3_CNTL_MISC2_BASE_IDX 1 |
|---|
| 984 | #define mmDAGB3_FIFO_EMPTY 0x01e8 |
|---|
| 985 | #define mmDAGB3_FIFO_EMPTY_BASE_IDX 1 |
|---|
| 986 | #define mmDAGB3_FIFO_FULL 0x01e9 |
|---|
| 987 | #define mmDAGB3_FIFO_FULL_BASE_IDX 1 |
|---|
| 988 | #define mmDAGB3_WR_CREDITS_FULL 0x01ea |
|---|
| 989 | #define mmDAGB3_WR_CREDITS_FULL_BASE_IDX 1 |
|---|
| 990 | #define mmDAGB3_RD_CREDITS_FULL 0x01eb |
|---|
| 991 | #define mmDAGB3_RD_CREDITS_FULL_BASE_IDX 1 |
|---|
| 992 | #define mmDAGB3_PERFCOUNTER_LO 0x01ec |
|---|
| 993 | #define mmDAGB3_PERFCOUNTER_LO_BASE_IDX 1 |
|---|
| 994 | #define mmDAGB3_PERFCOUNTER_HI 0x01ed |
|---|
| 995 | #define mmDAGB3_PERFCOUNTER_HI_BASE_IDX 1 |
|---|
| 996 | #define mmDAGB3_PERFCOUNTER0_CFG 0x01ee |
|---|
| 997 | #define mmDAGB3_PERFCOUNTER0_CFG_BASE_IDX 1 |
|---|
| 998 | #define mmDAGB3_PERFCOUNTER1_CFG 0x01ef |
|---|
| 999 | #define mmDAGB3_PERFCOUNTER1_CFG_BASE_IDX 1 |
|---|
| 1000 | #define mmDAGB3_PERFCOUNTER2_CFG 0x01f0 |
|---|
| 1001 | #define mmDAGB3_PERFCOUNTER2_CFG_BASE_IDX 1 |
|---|
| 1002 | #define mmDAGB3_PERFCOUNTER_RSLT_CNTL 0x01f1 |
|---|
| 1003 | #define mmDAGB3_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
|---|
| 1004 | #define mmDAGB3_RESERVE0 0x01f2 |
|---|
| 1005 | #define mmDAGB3_RESERVE0_BASE_IDX 1 |
|---|
| 1006 | #define mmDAGB3_RESERVE1 0x01f3 |
|---|
| 1007 | #define mmDAGB3_RESERVE1_BASE_IDX 1 |
|---|
| 1008 | #define mmDAGB3_RESERVE2 0x01f4 |
|---|
| 1009 | #define mmDAGB3_RESERVE2_BASE_IDX 1 |
|---|
| 1010 | #define mmDAGB3_RESERVE3 0x01f5 |
|---|
| 1011 | #define mmDAGB3_RESERVE3_BASE_IDX 1 |
|---|
| 1012 | #define mmDAGB3_RESERVE4 0x01f6 |
|---|
| 1013 | #define mmDAGB3_RESERVE4_BASE_IDX 1 |
|---|
| 1014 | #define mmDAGB3_RESERVE5 0x01f7 |
|---|
| 1015 | #define mmDAGB3_RESERVE5_BASE_IDX 1 |
|---|
| 1016 | #define mmDAGB3_RESERVE6 0x01f8 |
|---|
| 1017 | #define mmDAGB3_RESERVE6_BASE_IDX 1 |
|---|
| 1018 | #define mmDAGB3_RESERVE7 0x01f9 |
|---|
| 1019 | #define mmDAGB3_RESERVE7_BASE_IDX 1 |
|---|
| 1020 | #define mmDAGB3_RESERVE8 0x01fa |
|---|
| 1021 | #define mmDAGB3_RESERVE8_BASE_IDX 1 |
|---|
| 1022 | #define mmDAGB3_RESERVE9 0x01fb |
|---|
| 1023 | #define mmDAGB3_RESERVE9_BASE_IDX 1 |
|---|
| 1024 | #define mmDAGB3_RESERVE10 0x01fc |
|---|
| 1025 | #define mmDAGB3_RESERVE10_BASE_IDX 1 |
|---|
| 1026 | #define mmDAGB3_RESERVE11 0x01fd |
|---|
| 1027 | #define mmDAGB3_RESERVE11_BASE_IDX 1 |
|---|
| 1028 | #define mmDAGB3_RESERVE12 0x01fe |
|---|
| 1029 | #define mmDAGB3_RESERVE12_BASE_IDX 1 |
|---|
| 1030 | #define mmDAGB3_RESERVE13 0x01ff |
|---|
| 1031 | #define mmDAGB3_RESERVE13_BASE_IDX 1 |
|---|
| 1032 | |
|---|
| 1033 | |
|---|
| 1034 | // addressBlock: mmhub_dagb_dagbdec4 |
|---|
| 1035 | // base address: 0x68800 |
|---|
| 1036 | #define mmDAGB4_RDCLI0 0x0200 |
|---|
| 1037 | #define mmDAGB4_RDCLI0_BASE_IDX 1 |
|---|
| 1038 | #define mmDAGB4_RDCLI1 0x0201 |
|---|
| 1039 | #define mmDAGB4_RDCLI1_BASE_IDX 1 |
|---|
| 1040 | #define mmDAGB4_RDCLI2 0x0202 |
|---|
| 1041 | #define mmDAGB4_RDCLI2_BASE_IDX 1 |
|---|
| 1042 | #define mmDAGB4_RDCLI3 0x0203 |
|---|
| 1043 | #define mmDAGB4_RDCLI3_BASE_IDX 1 |
|---|
| 1044 | #define mmDAGB4_RDCLI4 0x0204 |
|---|
| 1045 | #define mmDAGB4_RDCLI4_BASE_IDX 1 |
|---|
| 1046 | #define mmDAGB4_RDCLI5 0x0205 |
|---|
| 1047 | #define mmDAGB4_RDCLI5_BASE_IDX 1 |
|---|
| 1048 | #define mmDAGB4_RDCLI6 0x0206 |
|---|
| 1049 | #define mmDAGB4_RDCLI6_BASE_IDX 1 |
|---|
| 1050 | #define mmDAGB4_RDCLI7 0x0207 |
|---|
| 1051 | #define mmDAGB4_RDCLI7_BASE_IDX 1 |
|---|
| 1052 | #define mmDAGB4_RDCLI8 0x0208 |
|---|
| 1053 | #define mmDAGB4_RDCLI8_BASE_IDX 1 |
|---|
| 1054 | #define mmDAGB4_RDCLI9 0x0209 |
|---|
| 1055 | #define mmDAGB4_RDCLI9_BASE_IDX 1 |
|---|
| 1056 | #define mmDAGB4_RDCLI10 0x020a |
|---|
| 1057 | #define mmDAGB4_RDCLI10_BASE_IDX 1 |
|---|
| 1058 | #define mmDAGB4_RDCLI11 0x020b |
|---|
| 1059 | #define mmDAGB4_RDCLI11_BASE_IDX 1 |
|---|
| 1060 | #define mmDAGB4_RDCLI12 0x020c |
|---|
| 1061 | #define mmDAGB4_RDCLI12_BASE_IDX 1 |
|---|
| 1062 | #define mmDAGB4_RDCLI13 0x020d |
|---|
| 1063 | #define mmDAGB4_RDCLI13_BASE_IDX 1 |
|---|
| 1064 | #define mmDAGB4_RDCLI14 0x020e |
|---|
| 1065 | #define mmDAGB4_RDCLI14_BASE_IDX 1 |
|---|
| 1066 | #define mmDAGB4_RDCLI15 0x020f |
|---|
| 1067 | #define mmDAGB4_RDCLI15_BASE_IDX 1 |
|---|
| 1068 | #define mmDAGB4_RD_CNTL 0x0210 |
|---|
| 1069 | #define mmDAGB4_RD_CNTL_BASE_IDX 1 |
|---|
| 1070 | #define mmDAGB4_RD_GMI_CNTL 0x0211 |
|---|
| 1071 | #define mmDAGB4_RD_GMI_CNTL_BASE_IDX 1 |
|---|
| 1072 | #define mmDAGB4_RD_ADDR_DAGB 0x0212 |
|---|
| 1073 | #define mmDAGB4_RD_ADDR_DAGB_BASE_IDX 1 |
|---|
| 1074 | #define mmDAGB4_RD_OUTPUT_DAGB_MAX_BURST 0x0213 |
|---|
| 1075 | #define mmDAGB4_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 |
|---|
| 1076 | #define mmDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER 0x0214 |
|---|
| 1077 | #define mmDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 |
|---|
| 1078 | #define mmDAGB4_RD_CGTT_CLK_CTRL 0x0215 |
|---|
| 1079 | #define mmDAGB4_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 1080 | #define mmDAGB4_L1TLB_RD_CGTT_CLK_CTRL 0x0216 |
|---|
| 1081 | #define mmDAGB4_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 1082 | #define mmDAGB4_ATCVM_RD_CGTT_CLK_CTRL 0x0217 |
|---|
| 1083 | #define mmDAGB4_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 1084 | #define mmDAGB4_RD_ADDR_DAGB_MAX_BURST0 0x0218 |
|---|
| 1085 | #define mmDAGB4_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 |
|---|
| 1086 | #define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER0 0x0219 |
|---|
| 1087 | #define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 |
|---|
| 1088 | #define mmDAGB4_RD_ADDR_DAGB_MAX_BURST1 0x021a |
|---|
| 1089 | #define mmDAGB4_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 |
|---|
| 1090 | #define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER1 0x021b |
|---|
| 1091 | #define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 |
|---|
| 1092 | #define mmDAGB4_RD_VC0_CNTL 0x021c |
|---|
| 1093 | #define mmDAGB4_RD_VC0_CNTL_BASE_IDX 1 |
|---|
| 1094 | #define mmDAGB4_RD_VC1_CNTL 0x021d |
|---|
| 1095 | #define mmDAGB4_RD_VC1_CNTL_BASE_IDX 1 |
|---|
| 1096 | #define mmDAGB4_RD_VC2_CNTL 0x021e |
|---|
| 1097 | #define mmDAGB4_RD_VC2_CNTL_BASE_IDX 1 |
|---|
| 1098 | #define mmDAGB4_RD_VC3_CNTL 0x021f |
|---|
| 1099 | #define mmDAGB4_RD_VC3_CNTL_BASE_IDX 1 |
|---|
| 1100 | #define mmDAGB4_RD_VC4_CNTL 0x0220 |
|---|
| 1101 | #define mmDAGB4_RD_VC4_CNTL_BASE_IDX 1 |
|---|
| 1102 | #define mmDAGB4_RD_VC5_CNTL 0x0221 |
|---|
| 1103 | #define mmDAGB4_RD_VC5_CNTL_BASE_IDX 1 |
|---|
| 1104 | #define mmDAGB4_RD_VC6_CNTL 0x0222 |
|---|
| 1105 | #define mmDAGB4_RD_VC6_CNTL_BASE_IDX 1 |
|---|
| 1106 | #define mmDAGB4_RD_VC7_CNTL 0x0223 |
|---|
| 1107 | #define mmDAGB4_RD_VC7_CNTL_BASE_IDX 1 |
|---|
| 1108 | #define mmDAGB4_RD_CNTL_MISC 0x0224 |
|---|
| 1109 | #define mmDAGB4_RD_CNTL_MISC_BASE_IDX 1 |
|---|
| 1110 | #define mmDAGB4_RD_TLB_CREDIT 0x0225 |
|---|
| 1111 | #define mmDAGB4_RD_TLB_CREDIT_BASE_IDX 1 |
|---|
| 1112 | #define mmDAGB4_RDCLI_ASK_PENDING 0x0226 |
|---|
| 1113 | #define mmDAGB4_RDCLI_ASK_PENDING_BASE_IDX 1 |
|---|
| 1114 | #define mmDAGB4_RDCLI_GO_PENDING 0x0227 |
|---|
| 1115 | #define mmDAGB4_RDCLI_GO_PENDING_BASE_IDX 1 |
|---|
| 1116 | #define mmDAGB4_RDCLI_GBLSEND_PENDING 0x0228 |
|---|
| 1117 | #define mmDAGB4_RDCLI_GBLSEND_PENDING_BASE_IDX 1 |
|---|
| 1118 | #define mmDAGB4_RDCLI_TLB_PENDING 0x0229 |
|---|
| 1119 | #define mmDAGB4_RDCLI_TLB_PENDING_BASE_IDX 1 |
|---|
| 1120 | #define mmDAGB4_RDCLI_OARB_PENDING 0x022a |
|---|
| 1121 | #define mmDAGB4_RDCLI_OARB_PENDING_BASE_IDX 1 |
|---|
| 1122 | #define mmDAGB4_RDCLI_OSD_PENDING 0x022b |
|---|
| 1123 | #define mmDAGB4_RDCLI_OSD_PENDING_BASE_IDX 1 |
|---|
| 1124 | #define mmDAGB4_WRCLI0 0x022c |
|---|
| 1125 | #define mmDAGB4_WRCLI0_BASE_IDX 1 |
|---|
| 1126 | #define mmDAGB4_WRCLI1 0x022d |
|---|
| 1127 | #define mmDAGB4_WRCLI1_BASE_IDX 1 |
|---|
| 1128 | #define mmDAGB4_WRCLI2 0x022e |
|---|
| 1129 | #define mmDAGB4_WRCLI2_BASE_IDX 1 |
|---|
| 1130 | #define mmDAGB4_WRCLI3 0x022f |
|---|
| 1131 | #define mmDAGB4_WRCLI3_BASE_IDX 1 |
|---|
| 1132 | #define mmDAGB4_WRCLI4 0x0230 |
|---|
| 1133 | #define mmDAGB4_WRCLI4_BASE_IDX 1 |
|---|
| 1134 | #define mmDAGB4_WRCLI5 0x0231 |
|---|
| 1135 | #define mmDAGB4_WRCLI5_BASE_IDX 1 |
|---|
| 1136 | #define mmDAGB4_WRCLI6 0x0232 |
|---|
| 1137 | #define mmDAGB4_WRCLI6_BASE_IDX 1 |
|---|
| 1138 | #define mmDAGB4_WRCLI7 0x0233 |
|---|
| 1139 | #define mmDAGB4_WRCLI7_BASE_IDX 1 |
|---|
| 1140 | #define mmDAGB4_WRCLI8 0x0234 |
|---|
| 1141 | #define mmDAGB4_WRCLI8_BASE_IDX 1 |
|---|
| 1142 | #define mmDAGB4_WRCLI9 0x0235 |
|---|
| 1143 | #define mmDAGB4_WRCLI9_BASE_IDX 1 |
|---|
| 1144 | #define mmDAGB4_WRCLI10 0x0236 |
|---|
| 1145 | #define mmDAGB4_WRCLI10_BASE_IDX 1 |
|---|
| 1146 | #define mmDAGB4_WRCLI11 0x0237 |
|---|
| 1147 | #define mmDAGB4_WRCLI11_BASE_IDX 1 |
|---|
| 1148 | #define mmDAGB4_WRCLI12 0x0238 |
|---|
| 1149 | #define mmDAGB4_WRCLI12_BASE_IDX 1 |
|---|
| 1150 | #define mmDAGB4_WRCLI13 0x0239 |
|---|
| 1151 | #define mmDAGB4_WRCLI13_BASE_IDX 1 |
|---|
| 1152 | #define mmDAGB4_WRCLI14 0x023a |
|---|
| 1153 | #define mmDAGB4_WRCLI14_BASE_IDX 1 |
|---|
| 1154 | #define mmDAGB4_WRCLI15 0x023b |
|---|
| 1155 | #define mmDAGB4_WRCLI15_BASE_IDX 1 |
|---|
| 1156 | #define mmDAGB4_WR_CNTL 0x023c |
|---|
| 1157 | #define mmDAGB4_WR_CNTL_BASE_IDX 1 |
|---|
| 1158 | #define mmDAGB4_WR_GMI_CNTL 0x023d |
|---|
| 1159 | #define mmDAGB4_WR_GMI_CNTL_BASE_IDX 1 |
|---|
| 1160 | #define mmDAGB4_WR_ADDR_DAGB 0x023e |
|---|
| 1161 | #define mmDAGB4_WR_ADDR_DAGB_BASE_IDX 1 |
|---|
| 1162 | #define mmDAGB4_WR_OUTPUT_DAGB_MAX_BURST 0x023f |
|---|
| 1163 | #define mmDAGB4_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 |
|---|
| 1164 | #define mmDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER 0x0240 |
|---|
| 1165 | #define mmDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 |
|---|
| 1166 | #define mmDAGB4_WR_CGTT_CLK_CTRL 0x0241 |
|---|
| 1167 | #define mmDAGB4_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 1168 | #define mmDAGB4_L1TLB_WR_CGTT_CLK_CTRL 0x0242 |
|---|
| 1169 | #define mmDAGB4_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 1170 | #define mmDAGB4_ATCVM_WR_CGTT_CLK_CTRL 0x0243 |
|---|
| 1171 | #define mmDAGB4_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 1172 | #define mmDAGB4_WR_ADDR_DAGB_MAX_BURST0 0x0244 |
|---|
| 1173 | #define mmDAGB4_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 |
|---|
| 1174 | #define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER0 0x0245 |
|---|
| 1175 | #define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 |
|---|
| 1176 | #define mmDAGB4_WR_ADDR_DAGB_MAX_BURST1 0x0246 |
|---|
| 1177 | #define mmDAGB4_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 |
|---|
| 1178 | #define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER1 0x0247 |
|---|
| 1179 | #define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 |
|---|
| 1180 | #define mmDAGB4_WR_DATA_DAGB 0x0248 |
|---|
| 1181 | #define mmDAGB4_WR_DATA_DAGB_BASE_IDX 1 |
|---|
| 1182 | #define mmDAGB4_WR_DATA_DAGB_MAX_BURST0 0x0249 |
|---|
| 1183 | #define mmDAGB4_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 |
|---|
| 1184 | #define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER0 0x024a |
|---|
| 1185 | #define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 |
|---|
| 1186 | #define mmDAGB4_WR_DATA_DAGB_MAX_BURST1 0x024b |
|---|
| 1187 | #define mmDAGB4_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 |
|---|
| 1188 | #define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER1 0x024c |
|---|
| 1189 | #define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 |
|---|
| 1190 | #define mmDAGB4_WR_VC0_CNTL 0x024d |
|---|
| 1191 | #define mmDAGB4_WR_VC0_CNTL_BASE_IDX 1 |
|---|
| 1192 | #define mmDAGB4_WR_VC1_CNTL 0x024e |
|---|
| 1193 | #define mmDAGB4_WR_VC1_CNTL_BASE_IDX 1 |
|---|
| 1194 | #define mmDAGB4_WR_VC2_CNTL 0x024f |
|---|
| 1195 | #define mmDAGB4_WR_VC2_CNTL_BASE_IDX 1 |
|---|
| 1196 | #define mmDAGB4_WR_VC3_CNTL 0x0250 |
|---|
| 1197 | #define mmDAGB4_WR_VC3_CNTL_BASE_IDX 1 |
|---|
| 1198 | #define mmDAGB4_WR_VC4_CNTL 0x0251 |
|---|
| 1199 | #define mmDAGB4_WR_VC4_CNTL_BASE_IDX 1 |
|---|
| 1200 | #define mmDAGB4_WR_VC5_CNTL 0x0252 |
|---|
| 1201 | #define mmDAGB4_WR_VC5_CNTL_BASE_IDX 1 |
|---|
| 1202 | #define mmDAGB4_WR_VC6_CNTL 0x0253 |
|---|
| 1203 | #define mmDAGB4_WR_VC6_CNTL_BASE_IDX 1 |
|---|
| 1204 | #define mmDAGB4_WR_VC7_CNTL 0x0254 |
|---|
| 1205 | #define mmDAGB4_WR_VC7_CNTL_BASE_IDX 1 |
|---|
| 1206 | #define mmDAGB4_WR_CNTL_MISC 0x0255 |
|---|
| 1207 | #define mmDAGB4_WR_CNTL_MISC_BASE_IDX 1 |
|---|
| 1208 | #define mmDAGB4_WR_TLB_CREDIT 0x0256 |
|---|
| 1209 | #define mmDAGB4_WR_TLB_CREDIT_BASE_IDX 1 |
|---|
| 1210 | #define mmDAGB4_WR_DATA_CREDIT 0x0257 |
|---|
| 1211 | #define mmDAGB4_WR_DATA_CREDIT_BASE_IDX 1 |
|---|
| 1212 | #define mmDAGB4_WR_MISC_CREDIT 0x0258 |
|---|
| 1213 | #define mmDAGB4_WR_MISC_CREDIT_BASE_IDX 1 |
|---|
| 1214 | #define mmDAGB4_WRCLI_ASK_PENDING 0x025d |
|---|
| 1215 | #define mmDAGB4_WRCLI_ASK_PENDING_BASE_IDX 1 |
|---|
| 1216 | #define mmDAGB4_WRCLI_GO_PENDING 0x025e |
|---|
| 1217 | #define mmDAGB4_WRCLI_GO_PENDING_BASE_IDX 1 |
|---|
| 1218 | #define mmDAGB4_WRCLI_GBLSEND_PENDING 0x025f |
|---|
| 1219 | #define mmDAGB4_WRCLI_GBLSEND_PENDING_BASE_IDX 1 |
|---|
| 1220 | #define mmDAGB4_WRCLI_TLB_PENDING 0x0260 |
|---|
| 1221 | #define mmDAGB4_WRCLI_TLB_PENDING_BASE_IDX 1 |
|---|
| 1222 | #define mmDAGB4_WRCLI_OARB_PENDING 0x0261 |
|---|
| 1223 | #define mmDAGB4_WRCLI_OARB_PENDING_BASE_IDX 1 |
|---|
| 1224 | #define mmDAGB4_WRCLI_OSD_PENDING 0x0262 |
|---|
| 1225 | #define mmDAGB4_WRCLI_OSD_PENDING_BASE_IDX 1 |
|---|
| 1226 | #define mmDAGB4_WRCLI_DBUS_ASK_PENDING 0x0263 |
|---|
| 1227 | #define mmDAGB4_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 |
|---|
| 1228 | #define mmDAGB4_WRCLI_DBUS_GO_PENDING 0x0264 |
|---|
| 1229 | #define mmDAGB4_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 |
|---|
| 1230 | #define mmDAGB4_DAGB_DLY 0x0265 |
|---|
| 1231 | #define mmDAGB4_DAGB_DLY_BASE_IDX 1 |
|---|
| 1232 | #define mmDAGB4_CNTL_MISC 0x0266 |
|---|
| 1233 | #define mmDAGB4_CNTL_MISC_BASE_IDX 1 |
|---|
| 1234 | #define mmDAGB4_CNTL_MISC2 0x0267 |
|---|
| 1235 | #define mmDAGB4_CNTL_MISC2_BASE_IDX 1 |
|---|
| 1236 | #define mmDAGB4_FIFO_EMPTY 0x0268 |
|---|
| 1237 | #define mmDAGB4_FIFO_EMPTY_BASE_IDX 1 |
|---|
| 1238 | #define mmDAGB4_FIFO_FULL 0x0269 |
|---|
| 1239 | #define mmDAGB4_FIFO_FULL_BASE_IDX 1 |
|---|
| 1240 | #define mmDAGB4_WR_CREDITS_FULL 0x026a |
|---|
| 1241 | #define mmDAGB4_WR_CREDITS_FULL_BASE_IDX 1 |
|---|
| 1242 | #define mmDAGB4_RD_CREDITS_FULL 0x026b |
|---|
| 1243 | #define mmDAGB4_RD_CREDITS_FULL_BASE_IDX 1 |
|---|
| 1244 | #define mmDAGB4_PERFCOUNTER_LO 0x026c |
|---|
| 1245 | #define mmDAGB4_PERFCOUNTER_LO_BASE_IDX 1 |
|---|
| 1246 | #define mmDAGB4_PERFCOUNTER_HI 0x026d |
|---|
| 1247 | #define mmDAGB4_PERFCOUNTER_HI_BASE_IDX 1 |
|---|
| 1248 | #define mmDAGB4_PERFCOUNTER0_CFG 0x026e |
|---|
| 1249 | #define mmDAGB4_PERFCOUNTER0_CFG_BASE_IDX 1 |
|---|
| 1250 | #define mmDAGB4_PERFCOUNTER1_CFG 0x026f |
|---|
| 1251 | #define mmDAGB4_PERFCOUNTER1_CFG_BASE_IDX 1 |
|---|
| 1252 | #define mmDAGB4_PERFCOUNTER2_CFG 0x0270 |
|---|
| 1253 | #define mmDAGB4_PERFCOUNTER2_CFG_BASE_IDX 1 |
|---|
| 1254 | #define mmDAGB4_PERFCOUNTER_RSLT_CNTL 0x0271 |
|---|
| 1255 | #define mmDAGB4_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
|---|
| 1256 | #define mmDAGB4_RESERVE0 0x0272 |
|---|
| 1257 | #define mmDAGB4_RESERVE0_BASE_IDX 1 |
|---|
| 1258 | #define mmDAGB4_RESERVE1 0x0273 |
|---|
| 1259 | #define mmDAGB4_RESERVE1_BASE_IDX 1 |
|---|
| 1260 | #define mmDAGB4_RESERVE2 0x0274 |
|---|
| 1261 | #define mmDAGB4_RESERVE2_BASE_IDX 1 |
|---|
| 1262 | #define mmDAGB4_RESERVE3 0x0275 |
|---|
| 1263 | #define mmDAGB4_RESERVE3_BASE_IDX 1 |
|---|
| 1264 | #define mmDAGB4_RESERVE4 0x0276 |
|---|
| 1265 | #define mmDAGB4_RESERVE4_BASE_IDX 1 |
|---|
| 1266 | #define mmDAGB4_RESERVE5 0x0277 |
|---|
| 1267 | #define mmDAGB4_RESERVE5_BASE_IDX 1 |
|---|
| 1268 | #define mmDAGB4_RESERVE6 0x0278 |
|---|
| 1269 | #define mmDAGB4_RESERVE6_BASE_IDX 1 |
|---|
| 1270 | #define mmDAGB4_RESERVE7 0x0279 |
|---|
| 1271 | #define mmDAGB4_RESERVE7_BASE_IDX 1 |
|---|
| 1272 | #define mmDAGB4_RESERVE8 0x027a |
|---|
| 1273 | #define mmDAGB4_RESERVE8_BASE_IDX 1 |
|---|
| 1274 | #define mmDAGB4_RESERVE9 0x027b |
|---|
| 1275 | #define mmDAGB4_RESERVE9_BASE_IDX 1 |
|---|
| 1276 | #define mmDAGB4_RESERVE10 0x027c |
|---|
| 1277 | #define mmDAGB4_RESERVE10_BASE_IDX 1 |
|---|
| 1278 | #define mmDAGB4_RESERVE11 0x027d |
|---|
| 1279 | #define mmDAGB4_RESERVE11_BASE_IDX 1 |
|---|
| 1280 | #define mmDAGB4_RESERVE12 0x027e |
|---|
| 1281 | #define mmDAGB4_RESERVE12_BASE_IDX 1 |
|---|
| 1282 | #define mmDAGB4_RESERVE13 0x027f |
|---|
| 1283 | #define mmDAGB4_RESERVE13_BASE_IDX 1 |
|---|
| 1284 | |
|---|
| 1285 | |
|---|
| 1286 | // addressBlock: mmhub_ea_mmeadec0 |
|---|
| 1287 | // base address: 0x68a00 |
|---|
| 1288 | #define mmMMEA0_DRAM_RD_CLI2GRP_MAP0 0x0280 |
|---|
| 1289 | #define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 1290 | #define mmMMEA0_DRAM_RD_CLI2GRP_MAP1 0x0281 |
|---|
| 1291 | #define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 1292 | #define mmMMEA0_DRAM_WR_CLI2GRP_MAP0 0x0282 |
|---|
| 1293 | #define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 1294 | #define mmMMEA0_DRAM_WR_CLI2GRP_MAP1 0x0283 |
|---|
| 1295 | #define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 1296 | #define mmMMEA0_DRAM_RD_GRP2VC_MAP 0x0284 |
|---|
| 1297 | #define mmMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 1298 | #define mmMMEA0_DRAM_WR_GRP2VC_MAP 0x0285 |
|---|
| 1299 | #define mmMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 1300 | #define mmMMEA0_DRAM_RD_LAZY 0x0286 |
|---|
| 1301 | #define mmMMEA0_DRAM_RD_LAZY_BASE_IDX 1 |
|---|
| 1302 | #define mmMMEA0_DRAM_WR_LAZY 0x0287 |
|---|
| 1303 | #define mmMMEA0_DRAM_WR_LAZY_BASE_IDX 1 |
|---|
| 1304 | #define mmMMEA0_DRAM_RD_CAM_CNTL 0x0288 |
|---|
| 1305 | #define mmMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX 1 |
|---|
| 1306 | #define mmMMEA0_DRAM_WR_CAM_CNTL 0x0289 |
|---|
| 1307 | #define mmMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX 1 |
|---|
| 1308 | #define mmMMEA0_DRAM_PAGE_BURST 0x028a |
|---|
| 1309 | #define mmMMEA0_DRAM_PAGE_BURST_BASE_IDX 1 |
|---|
| 1310 | #define mmMMEA0_DRAM_RD_PRI_AGE 0x028b |
|---|
| 1311 | #define mmMMEA0_DRAM_RD_PRI_AGE_BASE_IDX 1 |
|---|
| 1312 | #define mmMMEA0_DRAM_WR_PRI_AGE 0x028c |
|---|
| 1313 | #define mmMMEA0_DRAM_WR_PRI_AGE_BASE_IDX 1 |
|---|
| 1314 | #define mmMMEA0_DRAM_RD_PRI_QUEUING 0x028d |
|---|
| 1315 | #define mmMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX 1 |
|---|
| 1316 | #define mmMMEA0_DRAM_WR_PRI_QUEUING 0x028e |
|---|
| 1317 | #define mmMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX 1 |
|---|
| 1318 | #define mmMMEA0_DRAM_RD_PRI_FIXED 0x028f |
|---|
| 1319 | #define mmMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX 1 |
|---|
| 1320 | #define mmMMEA0_DRAM_WR_PRI_FIXED 0x0290 |
|---|
| 1321 | #define mmMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX 1 |
|---|
| 1322 | #define mmMMEA0_DRAM_RD_PRI_URGENCY 0x0291 |
|---|
| 1323 | #define mmMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX 1 |
|---|
| 1324 | #define mmMMEA0_DRAM_WR_PRI_URGENCY 0x0292 |
|---|
| 1325 | #define mmMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX 1 |
|---|
| 1326 | #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1 0x0293 |
|---|
| 1327 | #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 1328 | #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2 0x0294 |
|---|
| 1329 | #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 1330 | #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3 0x0295 |
|---|
| 1331 | #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 1332 | #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1 0x0296 |
|---|
| 1333 | #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 1334 | #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2 0x0297 |
|---|
| 1335 | #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 1336 | #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3 0x0298 |
|---|
| 1337 | #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 1338 | #define mmMMEA0_GMI_RD_CLI2GRP_MAP0 0x0299 |
|---|
| 1339 | #define mmMMEA0_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 1340 | #define mmMMEA0_GMI_RD_CLI2GRP_MAP1 0x029a |
|---|
| 1341 | #define mmMMEA0_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 1342 | #define mmMMEA0_GMI_WR_CLI2GRP_MAP0 0x029b |
|---|
| 1343 | #define mmMMEA0_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 1344 | #define mmMMEA0_GMI_WR_CLI2GRP_MAP1 0x029c |
|---|
| 1345 | #define mmMMEA0_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 1346 | #define mmMMEA0_GMI_RD_GRP2VC_MAP 0x029d |
|---|
| 1347 | #define mmMMEA0_GMI_RD_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 1348 | #define mmMMEA0_GMI_WR_GRP2VC_MAP 0x029e |
|---|
| 1349 | #define mmMMEA0_GMI_WR_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 1350 | #define mmMMEA0_GMI_RD_LAZY 0x029f |
|---|
| 1351 | #define mmMMEA0_GMI_RD_LAZY_BASE_IDX 1 |
|---|
| 1352 | #define mmMMEA0_GMI_WR_LAZY 0x02a0 |
|---|
| 1353 | #define mmMMEA0_GMI_WR_LAZY_BASE_IDX 1 |
|---|
| 1354 | #define mmMMEA0_GMI_RD_CAM_CNTL 0x02a1 |
|---|
| 1355 | #define mmMMEA0_GMI_RD_CAM_CNTL_BASE_IDX 1 |
|---|
| 1356 | #define mmMMEA0_GMI_WR_CAM_CNTL 0x02a2 |
|---|
| 1357 | #define mmMMEA0_GMI_WR_CAM_CNTL_BASE_IDX 1 |
|---|
| 1358 | #define mmMMEA0_GMI_PAGE_BURST 0x02a3 |
|---|
| 1359 | #define mmMMEA0_GMI_PAGE_BURST_BASE_IDX 1 |
|---|
| 1360 | #define mmMMEA0_GMI_RD_PRI_AGE 0x02a4 |
|---|
| 1361 | #define mmMMEA0_GMI_RD_PRI_AGE_BASE_IDX 1 |
|---|
| 1362 | #define mmMMEA0_GMI_WR_PRI_AGE 0x02a5 |
|---|
| 1363 | #define mmMMEA0_GMI_WR_PRI_AGE_BASE_IDX 1 |
|---|
| 1364 | #define mmMMEA0_GMI_RD_PRI_QUEUING 0x02a6 |
|---|
| 1365 | #define mmMMEA0_GMI_RD_PRI_QUEUING_BASE_IDX 1 |
|---|
| 1366 | #define mmMMEA0_GMI_WR_PRI_QUEUING 0x02a7 |
|---|
| 1367 | #define mmMMEA0_GMI_WR_PRI_QUEUING_BASE_IDX 1 |
|---|
| 1368 | #define mmMMEA0_GMI_RD_PRI_FIXED 0x02a8 |
|---|
| 1369 | #define mmMMEA0_GMI_RD_PRI_FIXED_BASE_IDX 1 |
|---|
| 1370 | #define mmMMEA0_GMI_WR_PRI_FIXED 0x02a9 |
|---|
| 1371 | #define mmMMEA0_GMI_WR_PRI_FIXED_BASE_IDX 1 |
|---|
| 1372 | #define mmMMEA0_GMI_RD_PRI_URGENCY 0x02aa |
|---|
| 1373 | #define mmMMEA0_GMI_RD_PRI_URGENCY_BASE_IDX 1 |
|---|
| 1374 | #define mmMMEA0_GMI_WR_PRI_URGENCY 0x02ab |
|---|
| 1375 | #define mmMMEA0_GMI_WR_PRI_URGENCY_BASE_IDX 1 |
|---|
| 1376 | #define mmMMEA0_GMI_RD_PRI_URGENCY_MASKING 0x02ac |
|---|
| 1377 | #define mmMMEA0_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 1378 | #define mmMMEA0_GMI_WR_PRI_URGENCY_MASKING 0x02ad |
|---|
| 1379 | #define mmMMEA0_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 1380 | #define mmMMEA0_GMI_RD_PRI_QUANT_PRI1 0x02ae |
|---|
| 1381 | #define mmMMEA0_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 1382 | #define mmMMEA0_GMI_RD_PRI_QUANT_PRI2 0x02af |
|---|
| 1383 | #define mmMMEA0_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 1384 | #define mmMMEA0_GMI_RD_PRI_QUANT_PRI3 0x02b0 |
|---|
| 1385 | #define mmMMEA0_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 1386 | #define mmMMEA0_GMI_WR_PRI_QUANT_PRI1 0x02b1 |
|---|
| 1387 | #define mmMMEA0_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 1388 | #define mmMMEA0_GMI_WR_PRI_QUANT_PRI2 0x02b2 |
|---|
| 1389 | #define mmMMEA0_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 1390 | #define mmMMEA0_GMI_WR_PRI_QUANT_PRI3 0x02b3 |
|---|
| 1391 | #define mmMMEA0_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 1392 | #define mmMMEA0_ADDRNORM_BASE_ADDR0 0x02b4 |
|---|
| 1393 | #define mmMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX 1 |
|---|
| 1394 | #define mmMMEA0_ADDRNORM_LIMIT_ADDR0 0x02b5 |
|---|
| 1395 | #define mmMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1 |
|---|
| 1396 | #define mmMMEA0_ADDRNORM_BASE_ADDR1 0x02b6 |
|---|
| 1397 | #define mmMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX 1 |
|---|
| 1398 | #define mmMMEA0_ADDRNORM_LIMIT_ADDR1 0x02b7 |
|---|
| 1399 | #define mmMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1 |
|---|
| 1400 | #define mmMMEA0_ADDRNORM_OFFSET_ADDR1 0x02b8 |
|---|
| 1401 | #define mmMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1 |
|---|
| 1402 | #define mmMMEA0_ADDRNORM_BASE_ADDR2 0x02b9 |
|---|
| 1403 | #define mmMMEA0_ADDRNORM_BASE_ADDR2_BASE_IDX 1 |
|---|
| 1404 | #define mmMMEA0_ADDRNORM_LIMIT_ADDR2 0x02ba |
|---|
| 1405 | #define mmMMEA0_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1 |
|---|
| 1406 | #define mmMMEA0_ADDRNORM_BASE_ADDR3 0x02bb |
|---|
| 1407 | #define mmMMEA0_ADDRNORM_BASE_ADDR3_BASE_IDX 1 |
|---|
| 1408 | #define mmMMEA0_ADDRNORM_LIMIT_ADDR3 0x02bc |
|---|
| 1409 | #define mmMMEA0_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1 |
|---|
| 1410 | #define mmMMEA0_ADDRNORM_OFFSET_ADDR3 0x02bd |
|---|
| 1411 | #define mmMMEA0_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1 |
|---|
| 1412 | #define mmMMEA0_ADDRNORM_BASE_ADDR4 0x02be |
|---|
| 1413 | #define mmMMEA0_ADDRNORM_BASE_ADDR4_BASE_IDX 1 |
|---|
| 1414 | #define mmMMEA0_ADDRNORM_LIMIT_ADDR4 0x02bf |
|---|
| 1415 | #define mmMMEA0_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1 |
|---|
| 1416 | #define mmMMEA0_ADDRNORM_BASE_ADDR5 0x02c0 |
|---|
| 1417 | #define mmMMEA0_ADDRNORM_BASE_ADDR5_BASE_IDX 1 |
|---|
| 1418 | #define mmMMEA0_ADDRNORM_LIMIT_ADDR5 0x02c1 |
|---|
| 1419 | #define mmMMEA0_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1 |
|---|
| 1420 | #define mmMMEA0_ADDRNORM_OFFSET_ADDR5 0x02c2 |
|---|
| 1421 | #define mmMMEA0_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1 |
|---|
| 1422 | #define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL 0x02c3 |
|---|
| 1423 | #define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1 |
|---|
| 1424 | #define mmMMEA0_ADDRNORMGMI_HOLE_CNTL 0x02c4 |
|---|
| 1425 | #define mmMMEA0_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1 |
|---|
| 1426 | #define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x02c5 |
|---|
| 1427 | #define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1 |
|---|
| 1428 | #define mmMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG 0x02c6 |
|---|
| 1429 | #define mmMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1 |
|---|
| 1430 | #define mmMMEA0_ADDRDEC_BANK_CFG 0x02c7 |
|---|
| 1431 | #define mmMMEA0_ADDRDEC_BANK_CFG_BASE_IDX 1 |
|---|
| 1432 | #define mmMMEA0_ADDRDEC_MISC_CFG 0x02c8 |
|---|
| 1433 | #define mmMMEA0_ADDRDEC_MISC_CFG_BASE_IDX 1 |
|---|
| 1434 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 0x02c9 |
|---|
| 1435 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1 |
|---|
| 1436 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 0x02ca |
|---|
| 1437 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1 |
|---|
| 1438 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 0x02cb |
|---|
| 1439 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1 |
|---|
| 1440 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 0x02cc |
|---|
| 1441 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1 |
|---|
| 1442 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 0x02cd |
|---|
| 1443 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1 |
|---|
| 1444 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5 0x02ce |
|---|
| 1445 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1 |
|---|
| 1446 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC 0x02cf |
|---|
| 1447 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1 |
|---|
| 1448 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2 0x02d0 |
|---|
| 1449 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1 |
|---|
| 1450 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0 0x02d1 |
|---|
| 1451 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1 |
|---|
| 1452 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1 0x02d2 |
|---|
| 1453 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1 |
|---|
| 1454 | #define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0x02d3 |
|---|
| 1455 | #define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1 |
|---|
| 1456 | #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK0 0x02d4 |
|---|
| 1457 | #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1 |
|---|
| 1458 | #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK1 0x02d5 |
|---|
| 1459 | #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1 |
|---|
| 1460 | #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK2 0x02d6 |
|---|
| 1461 | #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1 |
|---|
| 1462 | #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK3 0x02d7 |
|---|
| 1463 | #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1 |
|---|
| 1464 | #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK4 0x02d8 |
|---|
| 1465 | #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1 |
|---|
| 1466 | #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK5 0x02d9 |
|---|
| 1467 | #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1 |
|---|
| 1468 | #define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC 0x02da |
|---|
| 1469 | #define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1 |
|---|
| 1470 | #define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC2 0x02db |
|---|
| 1471 | #define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1 |
|---|
| 1472 | #define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS0 0x02dc |
|---|
| 1473 | #define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1 |
|---|
| 1474 | #define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS1 0x02dd |
|---|
| 1475 | #define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1 |
|---|
| 1476 | #define mmMMEA0_ADDRDECGMI_HARVEST_ENABLE 0x02de |
|---|
| 1477 | #define mmMMEA0_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1 |
|---|
| 1478 | #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0 0x02df |
|---|
| 1479 | #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1 |
|---|
| 1480 | #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1 0x02e0 |
|---|
| 1481 | #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1 |
|---|
| 1482 | #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2 0x02e1 |
|---|
| 1483 | #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1 |
|---|
| 1484 | #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3 0x02e2 |
|---|
| 1485 | #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1 |
|---|
| 1486 | #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0x02e3 |
|---|
| 1487 | #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1 |
|---|
| 1488 | #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0x02e4 |
|---|
| 1489 | #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1 |
|---|
| 1490 | #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0x02e5 |
|---|
| 1491 | #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1 |
|---|
| 1492 | #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0x02e6 |
|---|
| 1493 | #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1 |
|---|
| 1494 | #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01 0x02e7 |
|---|
| 1495 | #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1 |
|---|
| 1496 | #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23 0x02e8 |
|---|
| 1497 | #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1 |
|---|
| 1498 | #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0x02e9 |
|---|
| 1499 | #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1 |
|---|
| 1500 | #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0x02ea |
|---|
| 1501 | #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1 |
|---|
| 1502 | #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01 0x02eb |
|---|
| 1503 | #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1 |
|---|
| 1504 | #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23 0x02ec |
|---|
| 1505 | #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1 |
|---|
| 1506 | #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01 0x02ed |
|---|
| 1507 | #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1 |
|---|
| 1508 | #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23 0x02ee |
|---|
| 1509 | #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1 |
|---|
| 1510 | #define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01 0x02ef |
|---|
| 1511 | #define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1 |
|---|
| 1512 | #define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23 0x02f0 |
|---|
| 1513 | #define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1 |
|---|
| 1514 | #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0x02f1 |
|---|
| 1515 | #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1 |
|---|
| 1516 | #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0x02f2 |
|---|
| 1517 | #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1 |
|---|
| 1518 | #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0x02f3 |
|---|
| 1519 | #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1 |
|---|
| 1520 | #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0x02f4 |
|---|
| 1521 | #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1 |
|---|
| 1522 | #define mmMMEA0_ADDRDEC0_RM_SEL_CS01 0x02f5 |
|---|
| 1523 | #define mmMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1 |
|---|
| 1524 | #define mmMMEA0_ADDRDEC0_RM_SEL_CS23 0x02f6 |
|---|
| 1525 | #define mmMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1 |
|---|
| 1526 | #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01 0x02f7 |
|---|
| 1527 | #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1 |
|---|
| 1528 | #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23 0x02f8 |
|---|
| 1529 | #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1 |
|---|
| 1530 | #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0 0x02f9 |
|---|
| 1531 | #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1 |
|---|
| 1532 | #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1 0x02fa |
|---|
| 1533 | #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1 |
|---|
| 1534 | #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2 0x02fb |
|---|
| 1535 | #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1 |
|---|
| 1536 | #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3 0x02fc |
|---|
| 1537 | #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1 |
|---|
| 1538 | #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0x02fd |
|---|
| 1539 | #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1 |
|---|
| 1540 | #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0x02fe |
|---|
| 1541 | #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1 |
|---|
| 1542 | #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0x02ff |
|---|
| 1543 | #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1 |
|---|
| 1544 | #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0x0300 |
|---|
| 1545 | #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1 |
|---|
| 1546 | #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01 0x0301 |
|---|
| 1547 | #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1 |
|---|
| 1548 | #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23 0x0302 |
|---|
| 1549 | #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1 |
|---|
| 1550 | #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0x0303 |
|---|
| 1551 | #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1 |
|---|
| 1552 | #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0x0304 |
|---|
| 1553 | #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1 |
|---|
| 1554 | #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01 0x0305 |
|---|
| 1555 | #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1 |
|---|
| 1556 | #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23 0x0306 |
|---|
| 1557 | #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1 |
|---|
| 1558 | #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01 0x0307 |
|---|
| 1559 | #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1 |
|---|
| 1560 | #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23 0x0308 |
|---|
| 1561 | #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1 |
|---|
| 1562 | #define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01 0x0309 |
|---|
| 1563 | #define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1 |
|---|
| 1564 | #define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23 0x030a |
|---|
| 1565 | #define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1 |
|---|
| 1566 | #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0x030b |
|---|
| 1567 | #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1 |
|---|
| 1568 | #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0x030c |
|---|
| 1569 | #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1 |
|---|
| 1570 | #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0x030d |
|---|
| 1571 | #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1 |
|---|
| 1572 | #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0x030e |
|---|
| 1573 | #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1 |
|---|
| 1574 | #define mmMMEA0_ADDRDEC1_RM_SEL_CS01 0x030f |
|---|
| 1575 | #define mmMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1 |
|---|
| 1576 | #define mmMMEA0_ADDRDEC1_RM_SEL_CS23 0x0310 |
|---|
| 1577 | #define mmMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1 |
|---|
| 1578 | #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01 0x0311 |
|---|
| 1579 | #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1 |
|---|
| 1580 | #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23 0x0312 |
|---|
| 1581 | #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1 |
|---|
| 1582 | #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS0 0x0313 |
|---|
| 1583 | #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1 |
|---|
| 1584 | #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS1 0x0314 |
|---|
| 1585 | #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1 |
|---|
| 1586 | #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS2 0x0315 |
|---|
| 1587 | #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1 |
|---|
| 1588 | #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS3 0x0316 |
|---|
| 1589 | #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1 |
|---|
| 1590 | #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS0 0x0317 |
|---|
| 1591 | #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1 |
|---|
| 1592 | #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS1 0x0318 |
|---|
| 1593 | #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1 |
|---|
| 1594 | #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS2 0x0319 |
|---|
| 1595 | #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1 |
|---|
| 1596 | #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS3 0x031a |
|---|
| 1597 | #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1 |
|---|
| 1598 | #define mmMMEA0_ADDRDEC2_ADDR_MASK_CS01 0x031b |
|---|
| 1599 | #define mmMMEA0_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1 |
|---|
| 1600 | #define mmMMEA0_ADDRDEC2_ADDR_MASK_CS23 0x031c |
|---|
| 1601 | #define mmMMEA0_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1 |
|---|
| 1602 | #define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS01 0x031d |
|---|
| 1603 | #define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1 |
|---|
| 1604 | #define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS23 0x031e |
|---|
| 1605 | #define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1 |
|---|
| 1606 | #define mmMMEA0_ADDRDEC2_ADDR_CFG_CS01 0x031f |
|---|
| 1607 | #define mmMMEA0_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1 |
|---|
| 1608 | #define mmMMEA0_ADDRDEC2_ADDR_CFG_CS23 0x0320 |
|---|
| 1609 | #define mmMMEA0_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1 |
|---|
| 1610 | #define mmMMEA0_ADDRDEC2_ADDR_SEL_CS01 0x0321 |
|---|
| 1611 | #define mmMMEA0_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1 |
|---|
| 1612 | #define mmMMEA0_ADDRDEC2_ADDR_SEL_CS23 0x0322 |
|---|
| 1613 | #define mmMMEA0_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1 |
|---|
| 1614 | #define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS01 0x0323 |
|---|
| 1615 | #define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1 |
|---|
| 1616 | #define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS23 0x0324 |
|---|
| 1617 | #define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1 |
|---|
| 1618 | #define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS01 0x0325 |
|---|
| 1619 | #define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1 |
|---|
| 1620 | #define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS23 0x0326 |
|---|
| 1621 | #define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1 |
|---|
| 1622 | #define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS01 0x0327 |
|---|
| 1623 | #define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1 |
|---|
| 1624 | #define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS23 0x0328 |
|---|
| 1625 | #define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1 |
|---|
| 1626 | #define mmMMEA0_ADDRDEC2_RM_SEL_CS01 0x0329 |
|---|
| 1627 | #define mmMMEA0_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1 |
|---|
| 1628 | #define mmMMEA0_ADDRDEC2_RM_SEL_CS23 0x032a |
|---|
| 1629 | #define mmMMEA0_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1 |
|---|
| 1630 | #define mmMMEA0_ADDRDEC2_RM_SEL_SECCS01 0x032b |
|---|
| 1631 | #define mmMMEA0_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1 |
|---|
| 1632 | #define mmMMEA0_ADDRDEC2_RM_SEL_SECCS23 0x032c |
|---|
| 1633 | #define mmMMEA0_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1 |
|---|
| 1634 | #define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL 0x032d |
|---|
| 1635 | #define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1 |
|---|
| 1636 | #define mmMMEA0_ADDRNORMGMI_GLOBAL_CNTL 0x032e |
|---|
| 1637 | #define mmMMEA0_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1 |
|---|
| 1638 | #define mmMMEA0_IO_RD_CLI2GRP_MAP0 0x0355 |
|---|
| 1639 | #define mmMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 1640 | #define mmMMEA0_IO_RD_CLI2GRP_MAP1 0x0356 |
|---|
| 1641 | #define mmMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 1642 | #define mmMMEA0_IO_WR_CLI2GRP_MAP0 0x0357 |
|---|
| 1643 | #define mmMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 1644 | #define mmMMEA0_IO_WR_CLI2GRP_MAP1 0x0358 |
|---|
| 1645 | #define mmMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 1646 | #define mmMMEA0_IO_RD_COMBINE_FLUSH 0x0359 |
|---|
| 1647 | #define mmMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX 1 |
|---|
| 1648 | #define mmMMEA0_IO_WR_COMBINE_FLUSH 0x035a |
|---|
| 1649 | #define mmMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX 1 |
|---|
| 1650 | #define mmMMEA0_IO_GROUP_BURST 0x035b |
|---|
| 1651 | #define mmMMEA0_IO_GROUP_BURST_BASE_IDX 1 |
|---|
| 1652 | #define mmMMEA0_IO_RD_PRI_AGE 0x035c |
|---|
| 1653 | #define mmMMEA0_IO_RD_PRI_AGE_BASE_IDX 1 |
|---|
| 1654 | #define mmMMEA0_IO_WR_PRI_AGE 0x035d |
|---|
| 1655 | #define mmMMEA0_IO_WR_PRI_AGE_BASE_IDX 1 |
|---|
| 1656 | #define mmMMEA0_IO_RD_PRI_QUEUING 0x035e |
|---|
| 1657 | #define mmMMEA0_IO_RD_PRI_QUEUING_BASE_IDX 1 |
|---|
| 1658 | #define mmMMEA0_IO_WR_PRI_QUEUING 0x035f |
|---|
| 1659 | #define mmMMEA0_IO_WR_PRI_QUEUING_BASE_IDX 1 |
|---|
| 1660 | #define mmMMEA0_IO_RD_PRI_FIXED 0x0360 |
|---|
| 1661 | #define mmMMEA0_IO_RD_PRI_FIXED_BASE_IDX 1 |
|---|
| 1662 | #define mmMMEA0_IO_WR_PRI_FIXED 0x0361 |
|---|
| 1663 | #define mmMMEA0_IO_WR_PRI_FIXED_BASE_IDX 1 |
|---|
| 1664 | #define mmMMEA0_IO_RD_PRI_URGENCY 0x0362 |
|---|
| 1665 | #define mmMMEA0_IO_RD_PRI_URGENCY_BASE_IDX 1 |
|---|
| 1666 | #define mmMMEA0_IO_WR_PRI_URGENCY 0x0363 |
|---|
| 1667 | #define mmMMEA0_IO_WR_PRI_URGENCY_BASE_IDX 1 |
|---|
| 1668 | #define mmMMEA0_IO_RD_PRI_URGENCY_MASKING 0x0364 |
|---|
| 1669 | #define mmMMEA0_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 1670 | #define mmMMEA0_IO_WR_PRI_URGENCY_MASKING 0x0365 |
|---|
| 1671 | #define mmMMEA0_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 1672 | #define mmMMEA0_IO_RD_PRI_QUANT_PRI1 0x0366 |
|---|
| 1673 | #define mmMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 1674 | #define mmMMEA0_IO_RD_PRI_QUANT_PRI2 0x0367 |
|---|
| 1675 | #define mmMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 1676 | #define mmMMEA0_IO_RD_PRI_QUANT_PRI3 0x0368 |
|---|
| 1677 | #define mmMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 1678 | #define mmMMEA0_IO_WR_PRI_QUANT_PRI1 0x0369 |
|---|
| 1679 | #define mmMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 1680 | #define mmMMEA0_IO_WR_PRI_QUANT_PRI2 0x036a |
|---|
| 1681 | #define mmMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 1682 | #define mmMMEA0_IO_WR_PRI_QUANT_PRI3 0x036b |
|---|
| 1683 | #define mmMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 1684 | #define mmMMEA0_SDP_ARB_DRAM 0x036c |
|---|
| 1685 | #define mmMMEA0_SDP_ARB_DRAM_BASE_IDX 1 |
|---|
| 1686 | #define mmMMEA0_SDP_ARB_GMI 0x036d |
|---|
| 1687 | #define mmMMEA0_SDP_ARB_GMI_BASE_IDX 1 |
|---|
| 1688 | #define mmMMEA0_SDP_ARB_FINAL 0x036e |
|---|
| 1689 | #define mmMMEA0_SDP_ARB_FINAL_BASE_IDX 1 |
|---|
| 1690 | #define mmMMEA0_SDP_DRAM_PRIORITY 0x036f |
|---|
| 1691 | #define mmMMEA0_SDP_DRAM_PRIORITY_BASE_IDX 1 |
|---|
| 1692 | #define mmMMEA0_SDP_GMI_PRIORITY 0x0370 |
|---|
| 1693 | #define mmMMEA0_SDP_GMI_PRIORITY_BASE_IDX 1 |
|---|
| 1694 | #define mmMMEA0_SDP_IO_PRIORITY 0x0371 |
|---|
| 1695 | #define mmMMEA0_SDP_IO_PRIORITY_BASE_IDX 1 |
|---|
| 1696 | #define mmMMEA0_SDP_CREDITS 0x0372 |
|---|
| 1697 | #define mmMMEA0_SDP_CREDITS_BASE_IDX 1 |
|---|
| 1698 | #define mmMMEA0_SDP_TAG_RESERVE0 0x0373 |
|---|
| 1699 | #define mmMMEA0_SDP_TAG_RESERVE0_BASE_IDX 1 |
|---|
| 1700 | #define mmMMEA0_SDP_TAG_RESERVE1 0x0374 |
|---|
| 1701 | #define mmMMEA0_SDP_TAG_RESERVE1_BASE_IDX 1 |
|---|
| 1702 | #define mmMMEA0_SDP_VCC_RESERVE0 0x0375 |
|---|
| 1703 | #define mmMMEA0_SDP_VCC_RESERVE0_BASE_IDX 1 |
|---|
| 1704 | #define mmMMEA0_SDP_VCC_RESERVE1 0x0376 |
|---|
| 1705 | #define mmMMEA0_SDP_VCC_RESERVE1_BASE_IDX 1 |
|---|
| 1706 | #define mmMMEA0_SDP_VCD_RESERVE0 0x0377 |
|---|
| 1707 | #define mmMMEA0_SDP_VCD_RESERVE0_BASE_IDX 1 |
|---|
| 1708 | #define mmMMEA0_SDP_VCD_RESERVE1 0x0378 |
|---|
| 1709 | #define mmMMEA0_SDP_VCD_RESERVE1_BASE_IDX 1 |
|---|
| 1710 | #define mmMMEA0_SDP_REQ_CNTL 0x0379 |
|---|
| 1711 | #define mmMMEA0_SDP_REQ_CNTL_BASE_IDX 1 |
|---|
| 1712 | #define mmMMEA0_MISC 0x037a |
|---|
| 1713 | #define mmMMEA0_MISC_BASE_IDX 1 |
|---|
| 1714 | #define mmMMEA0_LATENCY_SAMPLING 0x037b |
|---|
| 1715 | #define mmMMEA0_LATENCY_SAMPLING_BASE_IDX 1 |
|---|
| 1716 | #define mmMMEA0_PERFCOUNTER_LO 0x037c |
|---|
| 1717 | #define mmMMEA0_PERFCOUNTER_LO_BASE_IDX 1 |
|---|
| 1718 | #define mmMMEA0_PERFCOUNTER_HI 0x037d |
|---|
| 1719 | #define mmMMEA0_PERFCOUNTER_HI_BASE_IDX 1 |
|---|
| 1720 | #define mmMMEA0_PERFCOUNTER0_CFG 0x037e |
|---|
| 1721 | #define mmMMEA0_PERFCOUNTER0_CFG_BASE_IDX 1 |
|---|
| 1722 | #define mmMMEA0_PERFCOUNTER1_CFG 0x037f |
|---|
| 1723 | #define mmMMEA0_PERFCOUNTER1_CFG_BASE_IDX 1 |
|---|
| 1724 | #define mmMMEA0_PERFCOUNTER_RSLT_CNTL 0x0380 |
|---|
| 1725 | #define mmMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
|---|
| 1726 | #define mmMMEA0_EDC_CNT 0x0386 |
|---|
| 1727 | #define mmMMEA0_EDC_CNT_BASE_IDX 1 |
|---|
| 1728 | #define mmMMEA0_EDC_CNT2 0x0387 |
|---|
| 1729 | #define mmMMEA0_EDC_CNT2_BASE_IDX 1 |
|---|
| 1730 | #define mmMMEA0_DSM_CNTL 0x0388 |
|---|
| 1731 | #define mmMMEA0_DSM_CNTL_BASE_IDX 1 |
|---|
| 1732 | #define mmMMEA0_DSM_CNTLA 0x0389 |
|---|
| 1733 | #define mmMMEA0_DSM_CNTLA_BASE_IDX 1 |
|---|
| 1734 | #define mmMMEA0_DSM_CNTLB 0x038a |
|---|
| 1735 | #define mmMMEA0_DSM_CNTLB_BASE_IDX 1 |
|---|
| 1736 | #define mmMMEA0_DSM_CNTL2 0x038b |
|---|
| 1737 | #define mmMMEA0_DSM_CNTL2_BASE_IDX 1 |
|---|
| 1738 | #define mmMMEA0_DSM_CNTL2A 0x038c |
|---|
| 1739 | #define mmMMEA0_DSM_CNTL2A_BASE_IDX 1 |
|---|
| 1740 | #define mmMMEA0_DSM_CNTL2B 0x038d |
|---|
| 1741 | #define mmMMEA0_DSM_CNTL2B_BASE_IDX 1 |
|---|
| 1742 | #define mmMMEA0_CGTT_CLK_CTRL 0x038f |
|---|
| 1743 | #define mmMMEA0_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 1744 | #define mmMMEA0_EDC_MODE 0x0390 |
|---|
| 1745 | #define mmMMEA0_EDC_MODE_BASE_IDX 1 |
|---|
| 1746 | #define mmMMEA0_ERR_STATUS 0x0391 |
|---|
| 1747 | #define mmMMEA0_ERR_STATUS_BASE_IDX 1 |
|---|
| 1748 | #define mmMMEA0_MISC2 0x0392 |
|---|
| 1749 | #define mmMMEA0_MISC2_BASE_IDX 1 |
|---|
| 1750 | #define mmMMEA0_ADDRDEC_SELECT 0x0393 |
|---|
| 1751 | #define mmMMEA0_ADDRDEC_SELECT_BASE_IDX 1 |
|---|
| 1752 | #define mmMMEA0_EDC_CNT3 0x0394 |
|---|
| 1753 | #define mmMMEA0_EDC_CNT3_BASE_IDX 1 |
|---|
| 1754 | |
|---|
| 1755 | |
|---|
| 1756 | // addressBlock: mmhub_ea_mmeadec1 |
|---|
| 1757 | // base address: 0x68f00 |
|---|
| 1758 | #define mmMMEA1_DRAM_RD_CLI2GRP_MAP0 0x03c0 |
|---|
| 1759 | #define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 1760 | #define mmMMEA1_DRAM_RD_CLI2GRP_MAP1 0x03c1 |
|---|
| 1761 | #define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 1762 | #define mmMMEA1_DRAM_WR_CLI2GRP_MAP0 0x03c2 |
|---|
| 1763 | #define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 1764 | #define mmMMEA1_DRAM_WR_CLI2GRP_MAP1 0x03c3 |
|---|
| 1765 | #define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 1766 | #define mmMMEA1_DRAM_RD_GRP2VC_MAP 0x03c4 |
|---|
| 1767 | #define mmMMEA1_DRAM_RD_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 1768 | #define mmMMEA1_DRAM_WR_GRP2VC_MAP 0x03c5 |
|---|
| 1769 | #define mmMMEA1_DRAM_WR_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 1770 | #define mmMMEA1_DRAM_RD_LAZY 0x03c6 |
|---|
| 1771 | #define mmMMEA1_DRAM_RD_LAZY_BASE_IDX 1 |
|---|
| 1772 | #define mmMMEA1_DRAM_WR_LAZY 0x03c7 |
|---|
| 1773 | #define mmMMEA1_DRAM_WR_LAZY_BASE_IDX 1 |
|---|
| 1774 | #define mmMMEA1_DRAM_RD_CAM_CNTL 0x03c8 |
|---|
| 1775 | #define mmMMEA1_DRAM_RD_CAM_CNTL_BASE_IDX 1 |
|---|
| 1776 | #define mmMMEA1_DRAM_WR_CAM_CNTL 0x03c9 |
|---|
| 1777 | #define mmMMEA1_DRAM_WR_CAM_CNTL_BASE_IDX 1 |
|---|
| 1778 | #define mmMMEA1_DRAM_PAGE_BURST 0x03ca |
|---|
| 1779 | #define mmMMEA1_DRAM_PAGE_BURST_BASE_IDX 1 |
|---|
| 1780 | #define mmMMEA1_DRAM_RD_PRI_AGE 0x03cb |
|---|
| 1781 | #define mmMMEA1_DRAM_RD_PRI_AGE_BASE_IDX 1 |
|---|
| 1782 | #define mmMMEA1_DRAM_WR_PRI_AGE 0x03cc |
|---|
| 1783 | #define mmMMEA1_DRAM_WR_PRI_AGE_BASE_IDX 1 |
|---|
| 1784 | #define mmMMEA1_DRAM_RD_PRI_QUEUING 0x03cd |
|---|
| 1785 | #define mmMMEA1_DRAM_RD_PRI_QUEUING_BASE_IDX 1 |
|---|
| 1786 | #define mmMMEA1_DRAM_WR_PRI_QUEUING 0x03ce |
|---|
| 1787 | #define mmMMEA1_DRAM_WR_PRI_QUEUING_BASE_IDX 1 |
|---|
| 1788 | #define mmMMEA1_DRAM_RD_PRI_FIXED 0x03cf |
|---|
| 1789 | #define mmMMEA1_DRAM_RD_PRI_FIXED_BASE_IDX 1 |
|---|
| 1790 | #define mmMMEA1_DRAM_WR_PRI_FIXED 0x03d0 |
|---|
| 1791 | #define mmMMEA1_DRAM_WR_PRI_FIXED_BASE_IDX 1 |
|---|
| 1792 | #define mmMMEA1_DRAM_RD_PRI_URGENCY 0x03d1 |
|---|
| 1793 | #define mmMMEA1_DRAM_RD_PRI_URGENCY_BASE_IDX 1 |
|---|
| 1794 | #define mmMMEA1_DRAM_WR_PRI_URGENCY 0x03d2 |
|---|
| 1795 | #define mmMMEA1_DRAM_WR_PRI_URGENCY_BASE_IDX 1 |
|---|
| 1796 | #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1 0x03d3 |
|---|
| 1797 | #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 1798 | #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2 0x03d4 |
|---|
| 1799 | #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 1800 | #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3 0x03d5 |
|---|
| 1801 | #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 1802 | #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1 0x03d6 |
|---|
| 1803 | #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 1804 | #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2 0x03d7 |
|---|
| 1805 | #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 1806 | #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3 0x03d8 |
|---|
| 1807 | #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 1808 | #define mmMMEA1_GMI_RD_CLI2GRP_MAP0 0x03d9 |
|---|
| 1809 | #define mmMMEA1_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 1810 | #define mmMMEA1_GMI_RD_CLI2GRP_MAP1 0x03da |
|---|
| 1811 | #define mmMMEA1_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1 |
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| 1812 | #define mmMMEA1_GMI_WR_CLI2GRP_MAP0 0x03db |
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| 1813 | #define mmMMEA1_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1 |
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| 1814 | #define mmMMEA1_GMI_WR_CLI2GRP_MAP1 0x03dc |
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| 1815 | #define mmMMEA1_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1 |
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| 1816 | #define mmMMEA1_GMI_RD_GRP2VC_MAP 0x03dd |
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| 1817 | #define mmMMEA1_GMI_RD_GRP2VC_MAP_BASE_IDX 1 |
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| 1818 | #define mmMMEA1_GMI_WR_GRP2VC_MAP 0x03de |
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| 1819 | #define mmMMEA1_GMI_WR_GRP2VC_MAP_BASE_IDX 1 |
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| 1820 | #define mmMMEA1_GMI_RD_LAZY 0x03df |
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| 1821 | #define mmMMEA1_GMI_RD_LAZY_BASE_IDX 1 |
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| 1822 | #define mmMMEA1_GMI_WR_LAZY 0x03e0 |
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| 1823 | #define mmMMEA1_GMI_WR_LAZY_BASE_IDX 1 |
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| 1824 | #define mmMMEA1_GMI_RD_CAM_CNTL 0x03e1 |
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| 1825 | #define mmMMEA1_GMI_RD_CAM_CNTL_BASE_IDX 1 |
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| 1826 | #define mmMMEA1_GMI_WR_CAM_CNTL 0x03e2 |
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| 1827 | #define mmMMEA1_GMI_WR_CAM_CNTL_BASE_IDX 1 |
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| 1828 | #define mmMMEA1_GMI_PAGE_BURST 0x03e3 |
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| 1829 | #define mmMMEA1_GMI_PAGE_BURST_BASE_IDX 1 |
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| 1830 | #define mmMMEA1_GMI_RD_PRI_AGE 0x03e4 |
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| 1831 | #define mmMMEA1_GMI_RD_PRI_AGE_BASE_IDX 1 |
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| 1832 | #define mmMMEA1_GMI_WR_PRI_AGE 0x03e5 |
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| 1833 | #define mmMMEA1_GMI_WR_PRI_AGE_BASE_IDX 1 |
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| 1834 | #define mmMMEA1_GMI_RD_PRI_QUEUING 0x03e6 |
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| 1835 | #define mmMMEA1_GMI_RD_PRI_QUEUING_BASE_IDX 1 |
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| 1836 | #define mmMMEA1_GMI_WR_PRI_QUEUING 0x03e7 |
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| 1837 | #define mmMMEA1_GMI_WR_PRI_QUEUING_BASE_IDX 1 |
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| 1838 | #define mmMMEA1_GMI_RD_PRI_FIXED 0x03e8 |
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| 1839 | #define mmMMEA1_GMI_RD_PRI_FIXED_BASE_IDX 1 |
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| 1840 | #define mmMMEA1_GMI_WR_PRI_FIXED 0x03e9 |
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| 1841 | #define mmMMEA1_GMI_WR_PRI_FIXED_BASE_IDX 1 |
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| 1842 | #define mmMMEA1_GMI_RD_PRI_URGENCY 0x03ea |
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| 1843 | #define mmMMEA1_GMI_RD_PRI_URGENCY_BASE_IDX 1 |
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| 1844 | #define mmMMEA1_GMI_WR_PRI_URGENCY 0x03eb |
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| 1845 | #define mmMMEA1_GMI_WR_PRI_URGENCY_BASE_IDX 1 |
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| 1846 | #define mmMMEA1_GMI_RD_PRI_URGENCY_MASKING 0x03ec |
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| 1847 | #define mmMMEA1_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1 |
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| 1848 | #define mmMMEA1_GMI_WR_PRI_URGENCY_MASKING 0x03ed |
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| 1849 | #define mmMMEA1_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1 |
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| 1850 | #define mmMMEA1_GMI_RD_PRI_QUANT_PRI1 0x03ee |
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| 1851 | #define mmMMEA1_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1 |
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| 1852 | #define mmMMEA1_GMI_RD_PRI_QUANT_PRI2 0x03ef |
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| 1853 | #define mmMMEA1_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1 |
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| 1854 | #define mmMMEA1_GMI_RD_PRI_QUANT_PRI3 0x03f0 |
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| 1855 | #define mmMMEA1_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1 |
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| 1856 | #define mmMMEA1_GMI_WR_PRI_QUANT_PRI1 0x03f1 |
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| 1857 | #define mmMMEA1_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1 |
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| 1858 | #define mmMMEA1_GMI_WR_PRI_QUANT_PRI2 0x03f2 |
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| 1859 | #define mmMMEA1_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1 |
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| 1860 | #define mmMMEA1_GMI_WR_PRI_QUANT_PRI3 0x03f3 |
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| 1861 | #define mmMMEA1_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1 |
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| 1862 | #define mmMMEA1_ADDRNORM_BASE_ADDR0 0x03f4 |
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| 1863 | #define mmMMEA1_ADDRNORM_BASE_ADDR0_BASE_IDX 1 |
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| 1864 | #define mmMMEA1_ADDRNORM_LIMIT_ADDR0 0x03f5 |
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| 1865 | #define mmMMEA1_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1 |
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| 1866 | #define mmMMEA1_ADDRNORM_BASE_ADDR1 0x03f6 |
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| 1867 | #define mmMMEA1_ADDRNORM_BASE_ADDR1_BASE_IDX 1 |
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| 1868 | #define mmMMEA1_ADDRNORM_LIMIT_ADDR1 0x03f7 |
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| 1869 | #define mmMMEA1_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1 |
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| 1870 | #define mmMMEA1_ADDRNORM_OFFSET_ADDR1 0x03f8 |
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| 1871 | #define mmMMEA1_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1 |
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| 1872 | #define mmMMEA1_ADDRNORM_BASE_ADDR2 0x03f9 |
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| 1873 | #define mmMMEA1_ADDRNORM_BASE_ADDR2_BASE_IDX 1 |
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| 1874 | #define mmMMEA1_ADDRNORM_LIMIT_ADDR2 0x03fa |
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| 1875 | #define mmMMEA1_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1 |
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| 1876 | #define mmMMEA1_ADDRNORM_BASE_ADDR3 0x03fb |
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| 1877 | #define mmMMEA1_ADDRNORM_BASE_ADDR3_BASE_IDX 1 |
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| 1878 | #define mmMMEA1_ADDRNORM_LIMIT_ADDR3 0x03fc |
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| 1879 | #define mmMMEA1_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1 |
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| 1880 | #define mmMMEA1_ADDRNORM_OFFSET_ADDR3 0x03fd |
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| 1881 | #define mmMMEA1_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1 |
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| 1882 | #define mmMMEA1_ADDRNORM_BASE_ADDR4 0x03fe |
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| 1883 | #define mmMMEA1_ADDRNORM_BASE_ADDR4_BASE_IDX 1 |
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| 1884 | #define mmMMEA1_ADDRNORM_LIMIT_ADDR4 0x03ff |
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| 1885 | #define mmMMEA1_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1 |
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| 1886 | #define mmMMEA1_ADDRNORM_BASE_ADDR5 0x0400 |
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| 1887 | #define mmMMEA1_ADDRNORM_BASE_ADDR5_BASE_IDX 1 |
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| 1888 | #define mmMMEA1_ADDRNORM_LIMIT_ADDR5 0x0401 |
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| 1889 | #define mmMMEA1_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1 |
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| 1890 | #define mmMMEA1_ADDRNORM_OFFSET_ADDR5 0x0402 |
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| 1891 | #define mmMMEA1_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1 |
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| 1892 | #define mmMMEA1_ADDRNORMDRAM_HOLE_CNTL 0x0403 |
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| 1893 | #define mmMMEA1_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1 |
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| 1894 | #define mmMMEA1_ADDRNORMGMI_HOLE_CNTL 0x0404 |
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| 1895 | #define mmMMEA1_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1 |
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| 1896 | #define mmMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0405 |
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| 1897 | #define mmMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1 |
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| 1898 | #define mmMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0406 |
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| 1899 | #define mmMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1 |
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| 1900 | #define mmMMEA1_ADDRDEC_BANK_CFG 0x0407 |
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| 1901 | #define mmMMEA1_ADDRDEC_BANK_CFG_BASE_IDX 1 |
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| 1902 | #define mmMMEA1_ADDRDEC_MISC_CFG 0x0408 |
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| 1903 | #define mmMMEA1_ADDRDEC_MISC_CFG_BASE_IDX 1 |
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| 1904 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0 0x0409 |
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| 1905 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1 |
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| 1906 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1 0x040a |
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| 1907 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1 |
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| 1908 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2 0x040b |
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| 1909 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1 |
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| 1910 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3 0x040c |
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| 1911 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1 |
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| 1912 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4 0x040d |
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| 1913 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1 |
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| 1914 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK5 0x040e |
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| 1915 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1 |
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| 1916 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC 0x040f |
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| 1917 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1 |
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| 1918 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2 0x0410 |
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| 1919 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1 |
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| 1920 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0 0x0411 |
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| 1921 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1 |
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| 1922 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1 0x0412 |
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| 1923 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1 |
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| 1924 | #define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE 0x0413 |
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| 1925 | #define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1 |
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| 1926 | #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK0 0x0414 |
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| 1927 | #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1 |
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| 1928 | #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK1 0x0415 |
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| 1929 | #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1 |
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| 1930 | #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK2 0x0416 |
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| 1931 | #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1 |
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| 1932 | #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK3 0x0417 |
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| 1933 | #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1 |
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| 1934 | #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK4 0x0418 |
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| 1935 | #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1 |
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| 1936 | #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK5 0x0419 |
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| 1937 | #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1 |
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| 1938 | #define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC 0x041a |
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| 1939 | #define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1 |
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| 1940 | #define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC2 0x041b |
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| 1941 | #define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1 |
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| 1942 | #define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS0 0x041c |
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| 1943 | #define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1 |
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| 1944 | #define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS1 0x041d |
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| 1945 | #define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1 |
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| 1946 | #define mmMMEA1_ADDRDECGMI_HARVEST_ENABLE 0x041e |
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| 1947 | #define mmMMEA1_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1 |
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| 1948 | #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0 0x041f |
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| 1949 | #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1 |
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| 1950 | #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1 0x0420 |
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| 1951 | #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1 |
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| 1952 | #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2 0x0421 |
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| 1953 | #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1 |
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| 1954 | #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3 0x0422 |
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| 1955 | #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1 |
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| 1956 | #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0 0x0423 |
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| 1957 | #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1 |
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| 1958 | #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1 0x0424 |
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| 1959 | #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1 |
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| 1960 | #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2 0x0425 |
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| 1961 | #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1 |
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| 1962 | #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3 0x0426 |
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| 1963 | #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1 |
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| 1964 | #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01 0x0427 |
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| 1965 | #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1 |
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| 1966 | #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23 0x0428 |
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| 1967 | #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1 |
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| 1968 | #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01 0x0429 |
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| 1969 | #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1 |
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| 1970 | #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23 0x042a |
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| 1971 | #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1 |
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| 1972 | #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01 0x042b |
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| 1973 | #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1 |
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| 1974 | #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23 0x042c |
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| 1975 | #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1 |
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| 1976 | #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01 0x042d |
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| 1977 | #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1 |
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| 1978 | #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23 0x042e |
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| 1979 | #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1 |
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| 1980 | #define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS01 0x042f |
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| 1981 | #define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1 |
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| 1982 | #define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS23 0x0430 |
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| 1983 | #define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1 |
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| 1984 | #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01 0x0431 |
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| 1985 | #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1 |
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| 1986 | #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23 0x0432 |
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| 1987 | #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1 |
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| 1988 | #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01 0x0433 |
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| 1989 | #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1 |
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| 1990 | #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23 0x0434 |
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| 1991 | #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1 |
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| 1992 | #define mmMMEA1_ADDRDEC0_RM_SEL_CS01 0x0435 |
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| 1993 | #define mmMMEA1_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1 |
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| 1994 | #define mmMMEA1_ADDRDEC0_RM_SEL_CS23 0x0436 |
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| 1995 | #define mmMMEA1_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1 |
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| 1996 | #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01 0x0437 |
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| 1997 | #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1 |
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| 1998 | #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23 0x0438 |
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| 1999 | #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1 |
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| 2000 | #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0 0x0439 |
|---|
| 2001 | #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1 |
|---|
| 2002 | #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1 0x043a |
|---|
| 2003 | #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1 |
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| 2004 | #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2 0x043b |
|---|
| 2005 | #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1 |
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| 2006 | #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3 0x043c |
|---|
| 2007 | #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1 |
|---|
| 2008 | #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0 0x043d |
|---|
| 2009 | #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1 |
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| 2010 | #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1 0x043e |
|---|
| 2011 | #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1 |
|---|
| 2012 | #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2 0x043f |
|---|
| 2013 | #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1 |
|---|
| 2014 | #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3 0x0440 |
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| 2015 | #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1 |
|---|
| 2016 | #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01 0x0441 |
|---|
| 2017 | #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1 |
|---|
| 2018 | #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23 0x0442 |
|---|
| 2019 | #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1 |
|---|
| 2020 | #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01 0x0443 |
|---|
| 2021 | #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1 |
|---|
| 2022 | #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23 0x0444 |
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| 2023 | #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1 |
|---|
| 2024 | #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01 0x0445 |
|---|
| 2025 | #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1 |
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| 2026 | #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23 0x0446 |
|---|
| 2027 | #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1 |
|---|
| 2028 | #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01 0x0447 |
|---|
| 2029 | #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1 |
|---|
| 2030 | #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23 0x0448 |
|---|
| 2031 | #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1 |
|---|
| 2032 | #define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS01 0x0449 |
|---|
| 2033 | #define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1 |
|---|
| 2034 | #define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS23 0x044a |
|---|
| 2035 | #define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1 |
|---|
| 2036 | #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01 0x044b |
|---|
| 2037 | #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1 |
|---|
| 2038 | #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23 0x044c |
|---|
| 2039 | #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1 |
|---|
| 2040 | #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01 0x044d |
|---|
| 2041 | #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1 |
|---|
| 2042 | #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23 0x044e |
|---|
| 2043 | #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1 |
|---|
| 2044 | #define mmMMEA1_ADDRDEC1_RM_SEL_CS01 0x044f |
|---|
| 2045 | #define mmMMEA1_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1 |
|---|
| 2046 | #define mmMMEA1_ADDRDEC1_RM_SEL_CS23 0x0450 |
|---|
| 2047 | #define mmMMEA1_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1 |
|---|
| 2048 | #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01 0x0451 |
|---|
| 2049 | #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1 |
|---|
| 2050 | #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23 0x0452 |
|---|
| 2051 | #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1 |
|---|
| 2052 | #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS0 0x0453 |
|---|
| 2053 | #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1 |
|---|
| 2054 | #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS1 0x0454 |
|---|
| 2055 | #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1 |
|---|
| 2056 | #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS2 0x0455 |
|---|
| 2057 | #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1 |
|---|
| 2058 | #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS3 0x0456 |
|---|
| 2059 | #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1 |
|---|
| 2060 | #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS0 0x0457 |
|---|
| 2061 | #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1 |
|---|
| 2062 | #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS1 0x0458 |
|---|
| 2063 | #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1 |
|---|
| 2064 | #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS2 0x0459 |
|---|
| 2065 | #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1 |
|---|
| 2066 | #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS3 0x045a |
|---|
| 2067 | #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1 |
|---|
| 2068 | #define mmMMEA1_ADDRDEC2_ADDR_MASK_CS01 0x045b |
|---|
| 2069 | #define mmMMEA1_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1 |
|---|
| 2070 | #define mmMMEA1_ADDRDEC2_ADDR_MASK_CS23 0x045c |
|---|
| 2071 | #define mmMMEA1_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1 |
|---|
| 2072 | #define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS01 0x045d |
|---|
| 2073 | #define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1 |
|---|
| 2074 | #define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS23 0x045e |
|---|
| 2075 | #define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1 |
|---|
| 2076 | #define mmMMEA1_ADDRDEC2_ADDR_CFG_CS01 0x045f |
|---|
| 2077 | #define mmMMEA1_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1 |
|---|
| 2078 | #define mmMMEA1_ADDRDEC2_ADDR_CFG_CS23 0x0460 |
|---|
| 2079 | #define mmMMEA1_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1 |
|---|
| 2080 | #define mmMMEA1_ADDRDEC2_ADDR_SEL_CS01 0x0461 |
|---|
| 2081 | #define mmMMEA1_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1 |
|---|
| 2082 | #define mmMMEA1_ADDRDEC2_ADDR_SEL_CS23 0x0462 |
|---|
| 2083 | #define mmMMEA1_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1 |
|---|
| 2084 | #define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS01 0x0463 |
|---|
| 2085 | #define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1 |
|---|
| 2086 | #define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS23 0x0464 |
|---|
| 2087 | #define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1 |
|---|
| 2088 | #define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS01 0x0465 |
|---|
| 2089 | #define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1 |
|---|
| 2090 | #define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS23 0x0466 |
|---|
| 2091 | #define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1 |
|---|
| 2092 | #define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS01 0x0467 |
|---|
| 2093 | #define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1 |
|---|
| 2094 | #define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS23 0x0468 |
|---|
| 2095 | #define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1 |
|---|
| 2096 | #define mmMMEA1_ADDRDEC2_RM_SEL_CS01 0x0469 |
|---|
| 2097 | #define mmMMEA1_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1 |
|---|
| 2098 | #define mmMMEA1_ADDRDEC2_RM_SEL_CS23 0x046a |
|---|
| 2099 | #define mmMMEA1_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1 |
|---|
| 2100 | #define mmMMEA1_ADDRDEC2_RM_SEL_SECCS01 0x046b |
|---|
| 2101 | #define mmMMEA1_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1 |
|---|
| 2102 | #define mmMMEA1_ADDRDEC2_RM_SEL_SECCS23 0x046c |
|---|
| 2103 | #define mmMMEA1_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1 |
|---|
| 2104 | #define mmMMEA1_ADDRNORMDRAM_GLOBAL_CNTL 0x046d |
|---|
| 2105 | #define mmMMEA1_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1 |
|---|
| 2106 | #define mmMMEA1_ADDRNORMGMI_GLOBAL_CNTL 0x046e |
|---|
| 2107 | #define mmMMEA1_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1 |
|---|
| 2108 | #define mmMMEA1_IO_RD_CLI2GRP_MAP0 0x0495 |
|---|
| 2109 | #define mmMMEA1_IO_RD_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 2110 | #define mmMMEA1_IO_RD_CLI2GRP_MAP1 0x0496 |
|---|
| 2111 | #define mmMMEA1_IO_RD_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 2112 | #define mmMMEA1_IO_WR_CLI2GRP_MAP0 0x0497 |
|---|
| 2113 | #define mmMMEA1_IO_WR_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 2114 | #define mmMMEA1_IO_WR_CLI2GRP_MAP1 0x0498 |
|---|
| 2115 | #define mmMMEA1_IO_WR_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 2116 | #define mmMMEA1_IO_RD_COMBINE_FLUSH 0x0499 |
|---|
| 2117 | #define mmMMEA1_IO_RD_COMBINE_FLUSH_BASE_IDX 1 |
|---|
| 2118 | #define mmMMEA1_IO_WR_COMBINE_FLUSH 0x049a |
|---|
| 2119 | #define mmMMEA1_IO_WR_COMBINE_FLUSH_BASE_IDX 1 |
|---|
| 2120 | #define mmMMEA1_IO_GROUP_BURST 0x049b |
|---|
| 2121 | #define mmMMEA1_IO_GROUP_BURST_BASE_IDX 1 |
|---|
| 2122 | #define mmMMEA1_IO_RD_PRI_AGE 0x049c |
|---|
| 2123 | #define mmMMEA1_IO_RD_PRI_AGE_BASE_IDX 1 |
|---|
| 2124 | #define mmMMEA1_IO_WR_PRI_AGE 0x049d |
|---|
| 2125 | #define mmMMEA1_IO_WR_PRI_AGE_BASE_IDX 1 |
|---|
| 2126 | #define mmMMEA1_IO_RD_PRI_QUEUING 0x049e |
|---|
| 2127 | #define mmMMEA1_IO_RD_PRI_QUEUING_BASE_IDX 1 |
|---|
| 2128 | #define mmMMEA1_IO_WR_PRI_QUEUING 0x049f |
|---|
| 2129 | #define mmMMEA1_IO_WR_PRI_QUEUING_BASE_IDX 1 |
|---|
| 2130 | #define mmMMEA1_IO_RD_PRI_FIXED 0x04a0 |
|---|
| 2131 | #define mmMMEA1_IO_RD_PRI_FIXED_BASE_IDX 1 |
|---|
| 2132 | #define mmMMEA1_IO_WR_PRI_FIXED 0x04a1 |
|---|
| 2133 | #define mmMMEA1_IO_WR_PRI_FIXED_BASE_IDX 1 |
|---|
| 2134 | #define mmMMEA1_IO_RD_PRI_URGENCY 0x04a2 |
|---|
| 2135 | #define mmMMEA1_IO_RD_PRI_URGENCY_BASE_IDX 1 |
|---|
| 2136 | #define mmMMEA1_IO_WR_PRI_URGENCY 0x04a3 |
|---|
| 2137 | #define mmMMEA1_IO_WR_PRI_URGENCY_BASE_IDX 1 |
|---|
| 2138 | #define mmMMEA1_IO_RD_PRI_URGENCY_MASKING 0x04a4 |
|---|
| 2139 | #define mmMMEA1_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 2140 | #define mmMMEA1_IO_WR_PRI_URGENCY_MASKING 0x04a5 |
|---|
| 2141 | #define mmMMEA1_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 2142 | #define mmMMEA1_IO_RD_PRI_QUANT_PRI1 0x04a6 |
|---|
| 2143 | #define mmMMEA1_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 2144 | #define mmMMEA1_IO_RD_PRI_QUANT_PRI2 0x04a7 |
|---|
| 2145 | #define mmMMEA1_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 2146 | #define mmMMEA1_IO_RD_PRI_QUANT_PRI3 0x04a8 |
|---|
| 2147 | #define mmMMEA1_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 2148 | #define mmMMEA1_IO_WR_PRI_QUANT_PRI1 0x04a9 |
|---|
| 2149 | #define mmMMEA1_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 2150 | #define mmMMEA1_IO_WR_PRI_QUANT_PRI2 0x04aa |
|---|
| 2151 | #define mmMMEA1_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 2152 | #define mmMMEA1_IO_WR_PRI_QUANT_PRI3 0x04ab |
|---|
| 2153 | #define mmMMEA1_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 2154 | #define mmMMEA1_SDP_ARB_DRAM 0x04ac |
|---|
| 2155 | #define mmMMEA1_SDP_ARB_DRAM_BASE_IDX 1 |
|---|
| 2156 | #define mmMMEA1_SDP_ARB_GMI 0x04ad |
|---|
| 2157 | #define mmMMEA1_SDP_ARB_GMI_BASE_IDX 1 |
|---|
| 2158 | #define mmMMEA1_SDP_ARB_FINAL 0x04ae |
|---|
| 2159 | #define mmMMEA1_SDP_ARB_FINAL_BASE_IDX 1 |
|---|
| 2160 | #define mmMMEA1_SDP_DRAM_PRIORITY 0x04af |
|---|
| 2161 | #define mmMMEA1_SDP_DRAM_PRIORITY_BASE_IDX 1 |
|---|
| 2162 | #define mmMMEA1_SDP_GMI_PRIORITY 0x04b0 |
|---|
| 2163 | #define mmMMEA1_SDP_GMI_PRIORITY_BASE_IDX 1 |
|---|
| 2164 | #define mmMMEA1_SDP_IO_PRIORITY 0x04b1 |
|---|
| 2165 | #define mmMMEA1_SDP_IO_PRIORITY_BASE_IDX 1 |
|---|
| 2166 | #define mmMMEA1_SDP_CREDITS 0x04b2 |
|---|
| 2167 | #define mmMMEA1_SDP_CREDITS_BASE_IDX 1 |
|---|
| 2168 | #define mmMMEA1_SDP_TAG_RESERVE0 0x04b3 |
|---|
| 2169 | #define mmMMEA1_SDP_TAG_RESERVE0_BASE_IDX 1 |
|---|
| 2170 | #define mmMMEA1_SDP_TAG_RESERVE1 0x04b4 |
|---|
| 2171 | #define mmMMEA1_SDP_TAG_RESERVE1_BASE_IDX 1 |
|---|
| 2172 | #define mmMMEA1_SDP_VCC_RESERVE0 0x04b5 |
|---|
| 2173 | #define mmMMEA1_SDP_VCC_RESERVE0_BASE_IDX 1 |
|---|
| 2174 | #define mmMMEA1_SDP_VCC_RESERVE1 0x04b6 |
|---|
| 2175 | #define mmMMEA1_SDP_VCC_RESERVE1_BASE_IDX 1 |
|---|
| 2176 | #define mmMMEA1_SDP_VCD_RESERVE0 0x04b7 |
|---|
| 2177 | #define mmMMEA1_SDP_VCD_RESERVE0_BASE_IDX 1 |
|---|
| 2178 | #define mmMMEA1_SDP_VCD_RESERVE1 0x04b8 |
|---|
| 2179 | #define mmMMEA1_SDP_VCD_RESERVE1_BASE_IDX 1 |
|---|
| 2180 | #define mmMMEA1_SDP_REQ_CNTL 0x04b9 |
|---|
| 2181 | #define mmMMEA1_SDP_REQ_CNTL_BASE_IDX 1 |
|---|
| 2182 | #define mmMMEA1_MISC 0x04ba |
|---|
| 2183 | #define mmMMEA1_MISC_BASE_IDX 1 |
|---|
| 2184 | #define mmMMEA1_LATENCY_SAMPLING 0x04bb |
|---|
| 2185 | #define mmMMEA1_LATENCY_SAMPLING_BASE_IDX 1 |
|---|
| 2186 | #define mmMMEA1_PERFCOUNTER_LO 0x04bc |
|---|
| 2187 | #define mmMMEA1_PERFCOUNTER_LO_BASE_IDX 1 |
|---|
| 2188 | #define mmMMEA1_PERFCOUNTER_HI 0x04bd |
|---|
| 2189 | #define mmMMEA1_PERFCOUNTER_HI_BASE_IDX 1 |
|---|
| 2190 | #define mmMMEA1_PERFCOUNTER0_CFG 0x04be |
|---|
| 2191 | #define mmMMEA1_PERFCOUNTER0_CFG_BASE_IDX 1 |
|---|
| 2192 | #define mmMMEA1_PERFCOUNTER1_CFG 0x04bf |
|---|
| 2193 | #define mmMMEA1_PERFCOUNTER1_CFG_BASE_IDX 1 |
|---|
| 2194 | #define mmMMEA1_PERFCOUNTER_RSLT_CNTL 0x04c0 |
|---|
| 2195 | #define mmMMEA1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
|---|
| 2196 | #define mmMMEA1_EDC_CNT 0x04c6 |
|---|
| 2197 | #define mmMMEA1_EDC_CNT_BASE_IDX 1 |
|---|
| 2198 | #define mmMMEA1_EDC_CNT2 0x04c7 |
|---|
| 2199 | #define mmMMEA1_EDC_CNT2_BASE_IDX 1 |
|---|
| 2200 | #define mmMMEA1_DSM_CNTL 0x04c8 |
|---|
| 2201 | #define mmMMEA1_DSM_CNTL_BASE_IDX 1 |
|---|
| 2202 | #define mmMMEA1_DSM_CNTLA 0x04c9 |
|---|
| 2203 | #define mmMMEA1_DSM_CNTLA_BASE_IDX 1 |
|---|
| 2204 | #define mmMMEA1_DSM_CNTLB 0x04ca |
|---|
| 2205 | #define mmMMEA1_DSM_CNTLB_BASE_IDX 1 |
|---|
| 2206 | #define mmMMEA1_DSM_CNTL2 0x04cb |
|---|
| 2207 | #define mmMMEA1_DSM_CNTL2_BASE_IDX 1 |
|---|
| 2208 | #define mmMMEA1_DSM_CNTL2A 0x04cc |
|---|
| 2209 | #define mmMMEA1_DSM_CNTL2A_BASE_IDX 1 |
|---|
| 2210 | #define mmMMEA1_DSM_CNTL2B 0x04cd |
|---|
| 2211 | #define mmMMEA1_DSM_CNTL2B_BASE_IDX 1 |
|---|
| 2212 | #define mmMMEA1_CGTT_CLK_CTRL 0x04cf |
|---|
| 2213 | #define mmMMEA1_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 2214 | #define mmMMEA1_EDC_MODE 0x04d0 |
|---|
| 2215 | #define mmMMEA1_EDC_MODE_BASE_IDX 1 |
|---|
| 2216 | #define mmMMEA1_ERR_STATUS 0x04d1 |
|---|
| 2217 | #define mmMMEA1_ERR_STATUS_BASE_IDX 1 |
|---|
| 2218 | #define mmMMEA1_MISC2 0x04d2 |
|---|
| 2219 | #define mmMMEA1_MISC2_BASE_IDX 1 |
|---|
| 2220 | #define mmMMEA1_ADDRDEC_SELECT 0x04d3 |
|---|
| 2221 | #define mmMMEA1_ADDRDEC_SELECT_BASE_IDX 1 |
|---|
| 2222 | #define mmMMEA1_EDC_CNT3 0x04d4 |
|---|
| 2223 | #define mmMMEA1_EDC_CNT3_BASE_IDX 1 |
|---|
| 2224 | |
|---|
| 2225 | |
|---|
| 2226 | // addressBlock: mmhub_ea_mmeadec2 |
|---|
| 2227 | // base address: 0x69400 |
|---|
| 2228 | #define mmMMEA2_DRAM_RD_CLI2GRP_MAP0 0x0500 |
|---|
| 2229 | #define mmMMEA2_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 2230 | #define mmMMEA2_DRAM_RD_CLI2GRP_MAP1 0x0501 |
|---|
| 2231 | #define mmMMEA2_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 2232 | #define mmMMEA2_DRAM_WR_CLI2GRP_MAP0 0x0502 |
|---|
| 2233 | #define mmMMEA2_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 2234 | #define mmMMEA2_DRAM_WR_CLI2GRP_MAP1 0x0503 |
|---|
| 2235 | #define mmMMEA2_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 2236 | #define mmMMEA2_DRAM_RD_GRP2VC_MAP 0x0504 |
|---|
| 2237 | #define mmMMEA2_DRAM_RD_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 2238 | #define mmMMEA2_DRAM_WR_GRP2VC_MAP 0x0505 |
|---|
| 2239 | #define mmMMEA2_DRAM_WR_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 2240 | #define mmMMEA2_DRAM_RD_LAZY 0x0506 |
|---|
| 2241 | #define mmMMEA2_DRAM_RD_LAZY_BASE_IDX 1 |
|---|
| 2242 | #define mmMMEA2_DRAM_WR_LAZY 0x0507 |
|---|
| 2243 | #define mmMMEA2_DRAM_WR_LAZY_BASE_IDX 1 |
|---|
| 2244 | #define mmMMEA2_DRAM_RD_CAM_CNTL 0x0508 |
|---|
| 2245 | #define mmMMEA2_DRAM_RD_CAM_CNTL_BASE_IDX 1 |
|---|
| 2246 | #define mmMMEA2_DRAM_WR_CAM_CNTL 0x0509 |
|---|
| 2247 | #define mmMMEA2_DRAM_WR_CAM_CNTL_BASE_IDX 1 |
|---|
| 2248 | #define mmMMEA2_DRAM_PAGE_BURST 0x050a |
|---|
| 2249 | #define mmMMEA2_DRAM_PAGE_BURST_BASE_IDX 1 |
|---|
| 2250 | #define mmMMEA2_DRAM_RD_PRI_AGE 0x050b |
|---|
| 2251 | #define mmMMEA2_DRAM_RD_PRI_AGE_BASE_IDX 1 |
|---|
| 2252 | #define mmMMEA2_DRAM_WR_PRI_AGE 0x050c |
|---|
| 2253 | #define mmMMEA2_DRAM_WR_PRI_AGE_BASE_IDX 1 |
|---|
| 2254 | #define mmMMEA2_DRAM_RD_PRI_QUEUING 0x050d |
|---|
| 2255 | #define mmMMEA2_DRAM_RD_PRI_QUEUING_BASE_IDX 1 |
|---|
| 2256 | #define mmMMEA2_DRAM_WR_PRI_QUEUING 0x050e |
|---|
| 2257 | #define mmMMEA2_DRAM_WR_PRI_QUEUING_BASE_IDX 1 |
|---|
| 2258 | #define mmMMEA2_DRAM_RD_PRI_FIXED 0x050f |
|---|
| 2259 | #define mmMMEA2_DRAM_RD_PRI_FIXED_BASE_IDX 1 |
|---|
| 2260 | #define mmMMEA2_DRAM_WR_PRI_FIXED 0x0510 |
|---|
| 2261 | #define mmMMEA2_DRAM_WR_PRI_FIXED_BASE_IDX 1 |
|---|
| 2262 | #define mmMMEA2_DRAM_RD_PRI_URGENCY 0x0511 |
|---|
| 2263 | #define mmMMEA2_DRAM_RD_PRI_URGENCY_BASE_IDX 1 |
|---|
| 2264 | #define mmMMEA2_DRAM_WR_PRI_URGENCY 0x0512 |
|---|
| 2265 | #define mmMMEA2_DRAM_WR_PRI_URGENCY_BASE_IDX 1 |
|---|
| 2266 | #define mmMMEA2_DRAM_RD_PRI_QUANT_PRI1 0x0513 |
|---|
| 2267 | #define mmMMEA2_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 2268 | #define mmMMEA2_DRAM_RD_PRI_QUANT_PRI2 0x0514 |
|---|
| 2269 | #define mmMMEA2_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 2270 | #define mmMMEA2_DRAM_RD_PRI_QUANT_PRI3 0x0515 |
|---|
| 2271 | #define mmMMEA2_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 2272 | #define mmMMEA2_DRAM_WR_PRI_QUANT_PRI1 0x0516 |
|---|
| 2273 | #define mmMMEA2_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 2274 | #define mmMMEA2_DRAM_WR_PRI_QUANT_PRI2 0x0517 |
|---|
| 2275 | #define mmMMEA2_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 2276 | #define mmMMEA2_DRAM_WR_PRI_QUANT_PRI3 0x0518 |
|---|
| 2277 | #define mmMMEA2_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 2278 | #define mmMMEA2_GMI_RD_CLI2GRP_MAP0 0x0519 |
|---|
| 2279 | #define mmMMEA2_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 2280 | #define mmMMEA2_GMI_RD_CLI2GRP_MAP1 0x051a |
|---|
| 2281 | #define mmMMEA2_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 2282 | #define mmMMEA2_GMI_WR_CLI2GRP_MAP0 0x051b |
|---|
| 2283 | #define mmMMEA2_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 2284 | #define mmMMEA2_GMI_WR_CLI2GRP_MAP1 0x051c |
|---|
| 2285 | #define mmMMEA2_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 2286 | #define mmMMEA2_GMI_RD_GRP2VC_MAP 0x051d |
|---|
| 2287 | #define mmMMEA2_GMI_RD_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 2288 | #define mmMMEA2_GMI_WR_GRP2VC_MAP 0x051e |
|---|
| 2289 | #define mmMMEA2_GMI_WR_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 2290 | #define mmMMEA2_GMI_RD_LAZY 0x051f |
|---|
| 2291 | #define mmMMEA2_GMI_RD_LAZY_BASE_IDX 1 |
|---|
| 2292 | #define mmMMEA2_GMI_WR_LAZY 0x0520 |
|---|
| 2293 | #define mmMMEA2_GMI_WR_LAZY_BASE_IDX 1 |
|---|
| 2294 | #define mmMMEA2_GMI_RD_CAM_CNTL 0x0521 |
|---|
| 2295 | #define mmMMEA2_GMI_RD_CAM_CNTL_BASE_IDX 1 |
|---|
| 2296 | #define mmMMEA2_GMI_WR_CAM_CNTL 0x0522 |
|---|
| 2297 | #define mmMMEA2_GMI_WR_CAM_CNTL_BASE_IDX 1 |
|---|
| 2298 | #define mmMMEA2_GMI_PAGE_BURST 0x0523 |
|---|
| 2299 | #define mmMMEA2_GMI_PAGE_BURST_BASE_IDX 1 |
|---|
| 2300 | #define mmMMEA2_GMI_RD_PRI_AGE 0x0524 |
|---|
| 2301 | #define mmMMEA2_GMI_RD_PRI_AGE_BASE_IDX 1 |
|---|
| 2302 | #define mmMMEA2_GMI_WR_PRI_AGE 0x0525 |
|---|
| 2303 | #define mmMMEA2_GMI_WR_PRI_AGE_BASE_IDX 1 |
|---|
| 2304 | #define mmMMEA2_GMI_RD_PRI_QUEUING 0x0526 |
|---|
| 2305 | #define mmMMEA2_GMI_RD_PRI_QUEUING_BASE_IDX 1 |
|---|
| 2306 | #define mmMMEA2_GMI_WR_PRI_QUEUING 0x0527 |
|---|
| 2307 | #define mmMMEA2_GMI_WR_PRI_QUEUING_BASE_IDX 1 |
|---|
| 2308 | #define mmMMEA2_GMI_RD_PRI_FIXED 0x0528 |
|---|
| 2309 | #define mmMMEA2_GMI_RD_PRI_FIXED_BASE_IDX 1 |
|---|
| 2310 | #define mmMMEA2_GMI_WR_PRI_FIXED 0x0529 |
|---|
| 2311 | #define mmMMEA2_GMI_WR_PRI_FIXED_BASE_IDX 1 |
|---|
| 2312 | #define mmMMEA2_GMI_RD_PRI_URGENCY 0x052a |
|---|
| 2313 | #define mmMMEA2_GMI_RD_PRI_URGENCY_BASE_IDX 1 |
|---|
| 2314 | #define mmMMEA2_GMI_WR_PRI_URGENCY 0x052b |
|---|
| 2315 | #define mmMMEA2_GMI_WR_PRI_URGENCY_BASE_IDX 1 |
|---|
| 2316 | #define mmMMEA2_GMI_RD_PRI_URGENCY_MASKING 0x052c |
|---|
| 2317 | #define mmMMEA2_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 2318 | #define mmMMEA2_GMI_WR_PRI_URGENCY_MASKING 0x052d |
|---|
| 2319 | #define mmMMEA2_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 2320 | #define mmMMEA2_GMI_RD_PRI_QUANT_PRI1 0x052e |
|---|
| 2321 | #define mmMMEA2_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 2322 | #define mmMMEA2_GMI_RD_PRI_QUANT_PRI2 0x052f |
|---|
| 2323 | #define mmMMEA2_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 2324 | #define mmMMEA2_GMI_RD_PRI_QUANT_PRI3 0x0530 |
|---|
| 2325 | #define mmMMEA2_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 2326 | #define mmMMEA2_GMI_WR_PRI_QUANT_PRI1 0x0531 |
|---|
| 2327 | #define mmMMEA2_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 2328 | #define mmMMEA2_GMI_WR_PRI_QUANT_PRI2 0x0532 |
|---|
| 2329 | #define mmMMEA2_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 2330 | #define mmMMEA2_GMI_WR_PRI_QUANT_PRI3 0x0533 |
|---|
| 2331 | #define mmMMEA2_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 2332 | #define mmMMEA2_ADDRNORM_BASE_ADDR0 0x0534 |
|---|
| 2333 | #define mmMMEA2_ADDRNORM_BASE_ADDR0_BASE_IDX 1 |
|---|
| 2334 | #define mmMMEA2_ADDRNORM_LIMIT_ADDR0 0x0535 |
|---|
| 2335 | #define mmMMEA2_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1 |
|---|
| 2336 | #define mmMMEA2_ADDRNORM_BASE_ADDR1 0x0536 |
|---|
| 2337 | #define mmMMEA2_ADDRNORM_BASE_ADDR1_BASE_IDX 1 |
|---|
| 2338 | #define mmMMEA2_ADDRNORM_LIMIT_ADDR1 0x0537 |
|---|
| 2339 | #define mmMMEA2_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1 |
|---|
| 2340 | #define mmMMEA2_ADDRNORM_OFFSET_ADDR1 0x0538 |
|---|
| 2341 | #define mmMMEA2_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1 |
|---|
| 2342 | #define mmMMEA2_ADDRNORM_BASE_ADDR2 0x0539 |
|---|
| 2343 | #define mmMMEA2_ADDRNORM_BASE_ADDR2_BASE_IDX 1 |
|---|
| 2344 | #define mmMMEA2_ADDRNORM_LIMIT_ADDR2 0x053a |
|---|
| 2345 | #define mmMMEA2_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1 |
|---|
| 2346 | #define mmMMEA2_ADDRNORM_BASE_ADDR3 0x053b |
|---|
| 2347 | #define mmMMEA2_ADDRNORM_BASE_ADDR3_BASE_IDX 1 |
|---|
| 2348 | #define mmMMEA2_ADDRNORM_LIMIT_ADDR3 0x053c |
|---|
| 2349 | #define mmMMEA2_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1 |
|---|
| 2350 | #define mmMMEA2_ADDRNORM_OFFSET_ADDR3 0x053d |
|---|
| 2351 | #define mmMMEA2_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1 |
|---|
| 2352 | #define mmMMEA2_ADDRNORM_BASE_ADDR4 0x053e |
|---|
| 2353 | #define mmMMEA2_ADDRNORM_BASE_ADDR4_BASE_IDX 1 |
|---|
| 2354 | #define mmMMEA2_ADDRNORM_LIMIT_ADDR4 0x053f |
|---|
| 2355 | #define mmMMEA2_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1 |
|---|
| 2356 | #define mmMMEA2_ADDRNORM_BASE_ADDR5 0x0540 |
|---|
| 2357 | #define mmMMEA2_ADDRNORM_BASE_ADDR5_BASE_IDX 1 |
|---|
| 2358 | #define mmMMEA2_ADDRNORM_LIMIT_ADDR5 0x0541 |
|---|
| 2359 | #define mmMMEA2_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1 |
|---|
| 2360 | #define mmMMEA2_ADDRNORM_OFFSET_ADDR5 0x0542 |
|---|
| 2361 | #define mmMMEA2_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1 |
|---|
| 2362 | #define mmMMEA2_ADDRNORMDRAM_HOLE_CNTL 0x0543 |
|---|
| 2363 | #define mmMMEA2_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1 |
|---|
| 2364 | #define mmMMEA2_ADDRNORMGMI_HOLE_CNTL 0x0544 |
|---|
| 2365 | #define mmMMEA2_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1 |
|---|
| 2366 | #define mmMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0545 |
|---|
| 2367 | #define mmMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1 |
|---|
| 2368 | #define mmMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0546 |
|---|
| 2369 | #define mmMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1 |
|---|
| 2370 | #define mmMMEA2_ADDRDEC_BANK_CFG 0x0547 |
|---|
| 2371 | #define mmMMEA2_ADDRDEC_BANK_CFG_BASE_IDX 1 |
|---|
| 2372 | #define mmMMEA2_ADDRDEC_MISC_CFG 0x0548 |
|---|
| 2373 | #define mmMMEA2_ADDRDEC_MISC_CFG_BASE_IDX 1 |
|---|
| 2374 | #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK0 0x0549 |
|---|
| 2375 | #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1 |
|---|
| 2376 | #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK1 0x054a |
|---|
| 2377 | #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1 |
|---|
| 2378 | #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK2 0x054b |
|---|
| 2379 | #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1 |
|---|
| 2380 | #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK3 0x054c |
|---|
| 2381 | #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1 |
|---|
| 2382 | #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK4 0x054d |
|---|
| 2383 | #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1 |
|---|
| 2384 | #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK5 0x054e |
|---|
| 2385 | #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1 |
|---|
| 2386 | #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC 0x054f |
|---|
| 2387 | #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1 |
|---|
| 2388 | #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC2 0x0550 |
|---|
| 2389 | #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1 |
|---|
| 2390 | #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS0 0x0551 |
|---|
| 2391 | #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1 |
|---|
| 2392 | #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS1 0x0552 |
|---|
| 2393 | #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1 |
|---|
| 2394 | #define mmMMEA2_ADDRDECDRAM_HARVEST_ENABLE 0x0553 |
|---|
| 2395 | #define mmMMEA2_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1 |
|---|
| 2396 | #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK0 0x0554 |
|---|
| 2397 | #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1 |
|---|
| 2398 | #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK1 0x0555 |
|---|
| 2399 | #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1 |
|---|
| 2400 | #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK2 0x0556 |
|---|
| 2401 | #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1 |
|---|
| 2402 | #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK3 0x0557 |
|---|
| 2403 | #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1 |
|---|
| 2404 | #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK4 0x0558 |
|---|
| 2405 | #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1 |
|---|
| 2406 | #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK5 0x0559 |
|---|
| 2407 | #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1 |
|---|
| 2408 | #define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC 0x055a |
|---|
| 2409 | #define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1 |
|---|
| 2410 | #define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC2 0x055b |
|---|
| 2411 | #define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1 |
|---|
| 2412 | #define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS0 0x055c |
|---|
| 2413 | #define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1 |
|---|
| 2414 | #define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS1 0x055d |
|---|
| 2415 | #define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1 |
|---|
| 2416 | #define mmMMEA2_ADDRDECGMI_HARVEST_ENABLE 0x055e |
|---|
| 2417 | #define mmMMEA2_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1 |
|---|
| 2418 | #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS0 0x055f |
|---|
| 2419 | #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1 |
|---|
| 2420 | #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS1 0x0560 |
|---|
| 2421 | #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1 |
|---|
| 2422 | #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS2 0x0561 |
|---|
| 2423 | #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1 |
|---|
| 2424 | #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS3 0x0562 |
|---|
| 2425 | #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1 |
|---|
| 2426 | #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS0 0x0563 |
|---|
| 2427 | #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1 |
|---|
| 2428 | #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS1 0x0564 |
|---|
| 2429 | #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1 |
|---|
| 2430 | #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS2 0x0565 |
|---|
| 2431 | #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1 |
|---|
| 2432 | #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS3 0x0566 |
|---|
| 2433 | #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1 |
|---|
| 2434 | #define mmMMEA2_ADDRDEC0_ADDR_MASK_CS01 0x0567 |
|---|
| 2435 | #define mmMMEA2_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1 |
|---|
| 2436 | #define mmMMEA2_ADDRDEC0_ADDR_MASK_CS23 0x0568 |
|---|
| 2437 | #define mmMMEA2_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1 |
|---|
| 2438 | #define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS01 0x0569 |
|---|
| 2439 | #define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1 |
|---|
| 2440 | #define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS23 0x056a |
|---|
| 2441 | #define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1 |
|---|
| 2442 | #define mmMMEA2_ADDRDEC0_ADDR_CFG_CS01 0x056b |
|---|
| 2443 | #define mmMMEA2_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1 |
|---|
| 2444 | #define mmMMEA2_ADDRDEC0_ADDR_CFG_CS23 0x056c |
|---|
| 2445 | #define mmMMEA2_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1 |
|---|
| 2446 | #define mmMMEA2_ADDRDEC0_ADDR_SEL_CS01 0x056d |
|---|
| 2447 | #define mmMMEA2_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1 |
|---|
| 2448 | #define mmMMEA2_ADDRDEC0_ADDR_SEL_CS23 0x056e |
|---|
| 2449 | #define mmMMEA2_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1 |
|---|
| 2450 | #define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS01 0x056f |
|---|
| 2451 | #define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1 |
|---|
| 2452 | #define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS23 0x0570 |
|---|
| 2453 | #define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1 |
|---|
| 2454 | #define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS01 0x0571 |
|---|
| 2455 | #define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1 |
|---|
| 2456 | #define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS23 0x0572 |
|---|
| 2457 | #define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1 |
|---|
| 2458 | #define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS01 0x0573 |
|---|
| 2459 | #define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1 |
|---|
| 2460 | #define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS23 0x0574 |
|---|
| 2461 | #define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1 |
|---|
| 2462 | #define mmMMEA2_ADDRDEC0_RM_SEL_CS01 0x0575 |
|---|
| 2463 | #define mmMMEA2_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1 |
|---|
| 2464 | #define mmMMEA2_ADDRDEC0_RM_SEL_CS23 0x0576 |
|---|
| 2465 | #define mmMMEA2_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1 |
|---|
| 2466 | #define mmMMEA2_ADDRDEC0_RM_SEL_SECCS01 0x0577 |
|---|
| 2467 | #define mmMMEA2_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1 |
|---|
| 2468 | #define mmMMEA2_ADDRDEC0_RM_SEL_SECCS23 0x0578 |
|---|
| 2469 | #define mmMMEA2_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1 |
|---|
| 2470 | #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS0 0x0579 |
|---|
| 2471 | #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1 |
|---|
| 2472 | #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS1 0x057a |
|---|
| 2473 | #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1 |
|---|
| 2474 | #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS2 0x057b |
|---|
| 2475 | #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1 |
|---|
| 2476 | #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS3 0x057c |
|---|
| 2477 | #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1 |
|---|
| 2478 | #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS0 0x057d |
|---|
| 2479 | #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1 |
|---|
| 2480 | #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS1 0x057e |
|---|
| 2481 | #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1 |
|---|
| 2482 | #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS2 0x057f |
|---|
| 2483 | #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1 |
|---|
| 2484 | #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS3 0x0580 |
|---|
| 2485 | #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1 |
|---|
| 2486 | #define mmMMEA2_ADDRDEC1_ADDR_MASK_CS01 0x0581 |
|---|
| 2487 | #define mmMMEA2_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1 |
|---|
| 2488 | #define mmMMEA2_ADDRDEC1_ADDR_MASK_CS23 0x0582 |
|---|
| 2489 | #define mmMMEA2_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1 |
|---|
| 2490 | #define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS01 0x0583 |
|---|
| 2491 | #define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1 |
|---|
| 2492 | #define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS23 0x0584 |
|---|
| 2493 | #define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1 |
|---|
| 2494 | #define mmMMEA2_ADDRDEC1_ADDR_CFG_CS01 0x0585 |
|---|
| 2495 | #define mmMMEA2_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1 |
|---|
| 2496 | #define mmMMEA2_ADDRDEC1_ADDR_CFG_CS23 0x0586 |
|---|
| 2497 | #define mmMMEA2_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1 |
|---|
| 2498 | #define mmMMEA2_ADDRDEC1_ADDR_SEL_CS01 0x0587 |
|---|
| 2499 | #define mmMMEA2_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1 |
|---|
| 2500 | #define mmMMEA2_ADDRDEC1_ADDR_SEL_CS23 0x0588 |
|---|
| 2501 | #define mmMMEA2_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1 |
|---|
| 2502 | #define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS01 0x0589 |
|---|
| 2503 | #define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1 |
|---|
| 2504 | #define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS23 0x058a |
|---|
| 2505 | #define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1 |
|---|
| 2506 | #define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS01 0x058b |
|---|
| 2507 | #define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1 |
|---|
| 2508 | #define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS23 0x058c |
|---|
| 2509 | #define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1 |
|---|
| 2510 | #define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS01 0x058d |
|---|
| 2511 | #define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1 |
|---|
| 2512 | #define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS23 0x058e |
|---|
| 2513 | #define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1 |
|---|
| 2514 | #define mmMMEA2_ADDRDEC1_RM_SEL_CS01 0x058f |
|---|
| 2515 | #define mmMMEA2_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1 |
|---|
| 2516 | #define mmMMEA2_ADDRDEC1_RM_SEL_CS23 0x0590 |
|---|
| 2517 | #define mmMMEA2_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1 |
|---|
| 2518 | #define mmMMEA2_ADDRDEC1_RM_SEL_SECCS01 0x0591 |
|---|
| 2519 | #define mmMMEA2_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1 |
|---|
| 2520 | #define mmMMEA2_ADDRDEC1_RM_SEL_SECCS23 0x0592 |
|---|
| 2521 | #define mmMMEA2_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1 |
|---|
| 2522 | #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS0 0x0593 |
|---|
| 2523 | #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1 |
|---|
| 2524 | #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS1 0x0594 |
|---|
| 2525 | #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1 |
|---|
| 2526 | #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS2 0x0595 |
|---|
| 2527 | #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1 |
|---|
| 2528 | #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS3 0x0596 |
|---|
| 2529 | #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1 |
|---|
| 2530 | #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS0 0x0597 |
|---|
| 2531 | #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1 |
|---|
| 2532 | #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS1 0x0598 |
|---|
| 2533 | #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1 |
|---|
| 2534 | #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS2 0x0599 |
|---|
| 2535 | #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1 |
|---|
| 2536 | #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS3 0x059a |
|---|
| 2537 | #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1 |
|---|
| 2538 | #define mmMMEA2_ADDRDEC2_ADDR_MASK_CS01 0x059b |
|---|
| 2539 | #define mmMMEA2_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1 |
|---|
| 2540 | #define mmMMEA2_ADDRDEC2_ADDR_MASK_CS23 0x059c |
|---|
| 2541 | #define mmMMEA2_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1 |
|---|
| 2542 | #define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS01 0x059d |
|---|
| 2543 | #define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1 |
|---|
| 2544 | #define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS23 0x059e |
|---|
| 2545 | #define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1 |
|---|
| 2546 | #define mmMMEA2_ADDRDEC2_ADDR_CFG_CS01 0x059f |
|---|
| 2547 | #define mmMMEA2_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1 |
|---|
| 2548 | #define mmMMEA2_ADDRDEC2_ADDR_CFG_CS23 0x05a0 |
|---|
| 2549 | #define mmMMEA2_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1 |
|---|
| 2550 | #define mmMMEA2_ADDRDEC2_ADDR_SEL_CS01 0x05a1 |
|---|
| 2551 | #define mmMMEA2_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1 |
|---|
| 2552 | #define mmMMEA2_ADDRDEC2_ADDR_SEL_CS23 0x05a2 |
|---|
| 2553 | #define mmMMEA2_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1 |
|---|
| 2554 | #define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS01 0x05a3 |
|---|
| 2555 | #define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1 |
|---|
| 2556 | #define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS23 0x05a4 |
|---|
| 2557 | #define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1 |
|---|
| 2558 | #define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS01 0x05a5 |
|---|
| 2559 | #define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1 |
|---|
| 2560 | #define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS23 0x05a6 |
|---|
| 2561 | #define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1 |
|---|
| 2562 | #define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS01 0x05a7 |
|---|
| 2563 | #define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1 |
|---|
| 2564 | #define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS23 0x05a8 |
|---|
| 2565 | #define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1 |
|---|
| 2566 | #define mmMMEA2_ADDRDEC2_RM_SEL_CS01 0x05a9 |
|---|
| 2567 | #define mmMMEA2_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1 |
|---|
| 2568 | #define mmMMEA2_ADDRDEC2_RM_SEL_CS23 0x05aa |
|---|
| 2569 | #define mmMMEA2_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1 |
|---|
| 2570 | #define mmMMEA2_ADDRDEC2_RM_SEL_SECCS01 0x05ab |
|---|
| 2571 | #define mmMMEA2_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1 |
|---|
| 2572 | #define mmMMEA2_ADDRDEC2_RM_SEL_SECCS23 0x05ac |
|---|
| 2573 | #define mmMMEA2_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1 |
|---|
| 2574 | #define mmMMEA2_ADDRNORMDRAM_GLOBAL_CNTL 0x05ad |
|---|
| 2575 | #define mmMMEA2_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1 |
|---|
| 2576 | #define mmMMEA2_ADDRNORMGMI_GLOBAL_CNTL 0x05ae |
|---|
| 2577 | #define mmMMEA2_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1 |
|---|
| 2578 | #define mmMMEA2_IO_RD_CLI2GRP_MAP0 0x05d5 |
|---|
| 2579 | #define mmMMEA2_IO_RD_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 2580 | #define mmMMEA2_IO_RD_CLI2GRP_MAP1 0x05d6 |
|---|
| 2581 | #define mmMMEA2_IO_RD_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 2582 | #define mmMMEA2_IO_WR_CLI2GRP_MAP0 0x05d7 |
|---|
| 2583 | #define mmMMEA2_IO_WR_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 2584 | #define mmMMEA2_IO_WR_CLI2GRP_MAP1 0x05d8 |
|---|
| 2585 | #define mmMMEA2_IO_WR_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 2586 | #define mmMMEA2_IO_RD_COMBINE_FLUSH 0x05d9 |
|---|
| 2587 | #define mmMMEA2_IO_RD_COMBINE_FLUSH_BASE_IDX 1 |
|---|
| 2588 | #define mmMMEA2_IO_WR_COMBINE_FLUSH 0x05da |
|---|
| 2589 | #define mmMMEA2_IO_WR_COMBINE_FLUSH_BASE_IDX 1 |
|---|
| 2590 | #define mmMMEA2_IO_GROUP_BURST 0x05db |
|---|
| 2591 | #define mmMMEA2_IO_GROUP_BURST_BASE_IDX 1 |
|---|
| 2592 | #define mmMMEA2_IO_RD_PRI_AGE 0x05dc |
|---|
| 2593 | #define mmMMEA2_IO_RD_PRI_AGE_BASE_IDX 1 |
|---|
| 2594 | #define mmMMEA2_IO_WR_PRI_AGE 0x05dd |
|---|
| 2595 | #define mmMMEA2_IO_WR_PRI_AGE_BASE_IDX 1 |
|---|
| 2596 | #define mmMMEA2_IO_RD_PRI_QUEUING 0x05de |
|---|
| 2597 | #define mmMMEA2_IO_RD_PRI_QUEUING_BASE_IDX 1 |
|---|
| 2598 | #define mmMMEA2_IO_WR_PRI_QUEUING 0x05df |
|---|
| 2599 | #define mmMMEA2_IO_WR_PRI_QUEUING_BASE_IDX 1 |
|---|
| 2600 | #define mmMMEA2_IO_RD_PRI_FIXED 0x05e0 |
|---|
| 2601 | #define mmMMEA2_IO_RD_PRI_FIXED_BASE_IDX 1 |
|---|
| 2602 | #define mmMMEA2_IO_WR_PRI_FIXED 0x05e1 |
|---|
| 2603 | #define mmMMEA2_IO_WR_PRI_FIXED_BASE_IDX 1 |
|---|
| 2604 | #define mmMMEA2_IO_RD_PRI_URGENCY 0x05e2 |
|---|
| 2605 | #define mmMMEA2_IO_RD_PRI_URGENCY_BASE_IDX 1 |
|---|
| 2606 | #define mmMMEA2_IO_WR_PRI_URGENCY 0x05e3 |
|---|
| 2607 | #define mmMMEA2_IO_WR_PRI_URGENCY_BASE_IDX 1 |
|---|
| 2608 | #define mmMMEA2_IO_RD_PRI_URGENCY_MASKING 0x05e4 |
|---|
| 2609 | #define mmMMEA2_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 2610 | #define mmMMEA2_IO_WR_PRI_URGENCY_MASKING 0x05e5 |
|---|
| 2611 | #define mmMMEA2_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 2612 | #define mmMMEA2_IO_RD_PRI_QUANT_PRI1 0x05e6 |
|---|
| 2613 | #define mmMMEA2_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 2614 | #define mmMMEA2_IO_RD_PRI_QUANT_PRI2 0x05e7 |
|---|
| 2615 | #define mmMMEA2_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 2616 | #define mmMMEA2_IO_RD_PRI_QUANT_PRI3 0x05e8 |
|---|
| 2617 | #define mmMMEA2_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 2618 | #define mmMMEA2_IO_WR_PRI_QUANT_PRI1 0x05e9 |
|---|
| 2619 | #define mmMMEA2_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 2620 | #define mmMMEA2_IO_WR_PRI_QUANT_PRI2 0x05ea |
|---|
| 2621 | #define mmMMEA2_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 2622 | #define mmMMEA2_IO_WR_PRI_QUANT_PRI3 0x05eb |
|---|
| 2623 | #define mmMMEA2_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 2624 | #define mmMMEA2_SDP_ARB_DRAM 0x05ec |
|---|
| 2625 | #define mmMMEA2_SDP_ARB_DRAM_BASE_IDX 1 |
|---|
| 2626 | #define mmMMEA2_SDP_ARB_GMI 0x05ed |
|---|
| 2627 | #define mmMMEA2_SDP_ARB_GMI_BASE_IDX 1 |
|---|
| 2628 | #define mmMMEA2_SDP_ARB_FINAL 0x05ee |
|---|
| 2629 | #define mmMMEA2_SDP_ARB_FINAL_BASE_IDX 1 |
|---|
| 2630 | #define mmMMEA2_SDP_DRAM_PRIORITY 0x05ef |
|---|
| 2631 | #define mmMMEA2_SDP_DRAM_PRIORITY_BASE_IDX 1 |
|---|
| 2632 | #define mmMMEA2_SDP_GMI_PRIORITY 0x05f0 |
|---|
| 2633 | #define mmMMEA2_SDP_GMI_PRIORITY_BASE_IDX 1 |
|---|
| 2634 | #define mmMMEA2_SDP_IO_PRIORITY 0x05f1 |
|---|
| 2635 | #define mmMMEA2_SDP_IO_PRIORITY_BASE_IDX 1 |
|---|
| 2636 | #define mmMMEA2_SDP_CREDITS 0x05f2 |
|---|
| 2637 | #define mmMMEA2_SDP_CREDITS_BASE_IDX 1 |
|---|
| 2638 | #define mmMMEA2_SDP_TAG_RESERVE0 0x05f3 |
|---|
| 2639 | #define mmMMEA2_SDP_TAG_RESERVE0_BASE_IDX 1 |
|---|
| 2640 | #define mmMMEA2_SDP_TAG_RESERVE1 0x05f4 |
|---|
| 2641 | #define mmMMEA2_SDP_TAG_RESERVE1_BASE_IDX 1 |
|---|
| 2642 | #define mmMMEA2_SDP_VCC_RESERVE0 0x05f5 |
|---|
| 2643 | #define mmMMEA2_SDP_VCC_RESERVE0_BASE_IDX 1 |
|---|
| 2644 | #define mmMMEA2_SDP_VCC_RESERVE1 0x05f6 |
|---|
| 2645 | #define mmMMEA2_SDP_VCC_RESERVE1_BASE_IDX 1 |
|---|
| 2646 | #define mmMMEA2_SDP_VCD_RESERVE0 0x05f7 |
|---|
| 2647 | #define mmMMEA2_SDP_VCD_RESERVE0_BASE_IDX 1 |
|---|
| 2648 | #define mmMMEA2_SDP_VCD_RESERVE1 0x05f8 |
|---|
| 2649 | #define mmMMEA2_SDP_VCD_RESERVE1_BASE_IDX 1 |
|---|
| 2650 | #define mmMMEA2_SDP_REQ_CNTL 0x05f9 |
|---|
| 2651 | #define mmMMEA2_SDP_REQ_CNTL_BASE_IDX 1 |
|---|
| 2652 | #define mmMMEA2_MISC 0x05fa |
|---|
| 2653 | #define mmMMEA2_MISC_BASE_IDX 1 |
|---|
| 2654 | #define mmMMEA2_LATENCY_SAMPLING 0x05fb |
|---|
| 2655 | #define mmMMEA2_LATENCY_SAMPLING_BASE_IDX 1 |
|---|
| 2656 | #define mmMMEA2_PERFCOUNTER_LO 0x05fc |
|---|
| 2657 | #define mmMMEA2_PERFCOUNTER_LO_BASE_IDX 1 |
|---|
| 2658 | #define mmMMEA2_PERFCOUNTER_HI 0x05fd |
|---|
| 2659 | #define mmMMEA2_PERFCOUNTER_HI_BASE_IDX 1 |
|---|
| 2660 | #define mmMMEA2_PERFCOUNTER0_CFG 0x05fe |
|---|
| 2661 | #define mmMMEA2_PERFCOUNTER0_CFG_BASE_IDX 1 |
|---|
| 2662 | #define mmMMEA2_PERFCOUNTER1_CFG 0x05ff |
|---|
| 2663 | #define mmMMEA2_PERFCOUNTER1_CFG_BASE_IDX 1 |
|---|
| 2664 | #define mmMMEA2_PERFCOUNTER_RSLT_CNTL 0x0600 |
|---|
| 2665 | #define mmMMEA2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
|---|
| 2666 | #define mmMMEA2_EDC_CNT 0x0606 |
|---|
| 2667 | #define mmMMEA2_EDC_CNT_BASE_IDX 1 |
|---|
| 2668 | #define mmMMEA2_EDC_CNT2 0x0607 |
|---|
| 2669 | #define mmMMEA2_EDC_CNT2_BASE_IDX 1 |
|---|
| 2670 | #define mmMMEA2_DSM_CNTL 0x0608 |
|---|
| 2671 | #define mmMMEA2_DSM_CNTL_BASE_IDX 1 |
|---|
| 2672 | #define mmMMEA2_DSM_CNTLA 0x0609 |
|---|
| 2673 | #define mmMMEA2_DSM_CNTLA_BASE_IDX 1 |
|---|
| 2674 | #define mmMMEA2_DSM_CNTLB 0x060a |
|---|
| 2675 | #define mmMMEA2_DSM_CNTLB_BASE_IDX 1 |
|---|
| 2676 | #define mmMMEA2_DSM_CNTL2 0x060b |
|---|
| 2677 | #define mmMMEA2_DSM_CNTL2_BASE_IDX 1 |
|---|
| 2678 | #define mmMMEA2_DSM_CNTL2A 0x060c |
|---|
| 2679 | #define mmMMEA2_DSM_CNTL2A_BASE_IDX 1 |
|---|
| 2680 | #define mmMMEA2_DSM_CNTL2B 0x060d |
|---|
| 2681 | #define mmMMEA2_DSM_CNTL2B_BASE_IDX 1 |
|---|
| 2682 | #define mmMMEA2_CGTT_CLK_CTRL 0x060f |
|---|
| 2683 | #define mmMMEA2_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 2684 | #define mmMMEA2_EDC_MODE 0x0610 |
|---|
| 2685 | #define mmMMEA2_EDC_MODE_BASE_IDX 1 |
|---|
| 2686 | #define mmMMEA2_ERR_STATUS 0x0611 |
|---|
| 2687 | #define mmMMEA2_ERR_STATUS_BASE_IDX 1 |
|---|
| 2688 | #define mmMMEA2_MISC2 0x0612 |
|---|
| 2689 | #define mmMMEA2_MISC2_BASE_IDX 1 |
|---|
| 2690 | #define mmMMEA2_ADDRDEC_SELECT 0x0613 |
|---|
| 2691 | #define mmMMEA2_ADDRDEC_SELECT_BASE_IDX 1 |
|---|
| 2692 | #define mmMMEA2_EDC_CNT3 0x0614 |
|---|
| 2693 | #define mmMMEA2_EDC_CNT3_BASE_IDX 1 |
|---|
| 2694 | |
|---|
| 2695 | |
|---|
| 2696 | // addressBlock: mmhub_ea_mmeadec3 |
|---|
| 2697 | // base address: 0x69900 |
|---|
| 2698 | #define mmMMEA3_DRAM_RD_CLI2GRP_MAP0 0x0640 |
|---|
| 2699 | #define mmMMEA3_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 2700 | #define mmMMEA3_DRAM_RD_CLI2GRP_MAP1 0x0641 |
|---|
| 2701 | #define mmMMEA3_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 2702 | #define mmMMEA3_DRAM_WR_CLI2GRP_MAP0 0x0642 |
|---|
| 2703 | #define mmMMEA3_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 2704 | #define mmMMEA3_DRAM_WR_CLI2GRP_MAP1 0x0643 |
|---|
| 2705 | #define mmMMEA3_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 2706 | #define mmMMEA3_DRAM_RD_GRP2VC_MAP 0x0644 |
|---|
| 2707 | #define mmMMEA3_DRAM_RD_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 2708 | #define mmMMEA3_DRAM_WR_GRP2VC_MAP 0x0645 |
|---|
| 2709 | #define mmMMEA3_DRAM_WR_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 2710 | #define mmMMEA3_DRAM_RD_LAZY 0x0646 |
|---|
| 2711 | #define mmMMEA3_DRAM_RD_LAZY_BASE_IDX 1 |
|---|
| 2712 | #define mmMMEA3_DRAM_WR_LAZY 0x0647 |
|---|
| 2713 | #define mmMMEA3_DRAM_WR_LAZY_BASE_IDX 1 |
|---|
| 2714 | #define mmMMEA3_DRAM_RD_CAM_CNTL 0x0648 |
|---|
| 2715 | #define mmMMEA3_DRAM_RD_CAM_CNTL_BASE_IDX 1 |
|---|
| 2716 | #define mmMMEA3_DRAM_WR_CAM_CNTL 0x0649 |
|---|
| 2717 | #define mmMMEA3_DRAM_WR_CAM_CNTL_BASE_IDX 1 |
|---|
| 2718 | #define mmMMEA3_DRAM_PAGE_BURST 0x064a |
|---|
| 2719 | #define mmMMEA3_DRAM_PAGE_BURST_BASE_IDX 1 |
|---|
| 2720 | #define mmMMEA3_DRAM_RD_PRI_AGE 0x064b |
|---|
| 2721 | #define mmMMEA3_DRAM_RD_PRI_AGE_BASE_IDX 1 |
|---|
| 2722 | #define mmMMEA3_DRAM_WR_PRI_AGE 0x064c |
|---|
| 2723 | #define mmMMEA3_DRAM_WR_PRI_AGE_BASE_IDX 1 |
|---|
| 2724 | #define mmMMEA3_DRAM_RD_PRI_QUEUING 0x064d |
|---|
| 2725 | #define mmMMEA3_DRAM_RD_PRI_QUEUING_BASE_IDX 1 |
|---|
| 2726 | #define mmMMEA3_DRAM_WR_PRI_QUEUING 0x064e |
|---|
| 2727 | #define mmMMEA3_DRAM_WR_PRI_QUEUING_BASE_IDX 1 |
|---|
| 2728 | #define mmMMEA3_DRAM_RD_PRI_FIXED 0x064f |
|---|
| 2729 | #define mmMMEA3_DRAM_RD_PRI_FIXED_BASE_IDX 1 |
|---|
| 2730 | #define mmMMEA3_DRAM_WR_PRI_FIXED 0x0650 |
|---|
| 2731 | #define mmMMEA3_DRAM_WR_PRI_FIXED_BASE_IDX 1 |
|---|
| 2732 | #define mmMMEA3_DRAM_RD_PRI_URGENCY 0x0651 |
|---|
| 2733 | #define mmMMEA3_DRAM_RD_PRI_URGENCY_BASE_IDX 1 |
|---|
| 2734 | #define mmMMEA3_DRAM_WR_PRI_URGENCY 0x0652 |
|---|
| 2735 | #define mmMMEA3_DRAM_WR_PRI_URGENCY_BASE_IDX 1 |
|---|
| 2736 | #define mmMMEA3_DRAM_RD_PRI_QUANT_PRI1 0x0653 |
|---|
| 2737 | #define mmMMEA3_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 2738 | #define mmMMEA3_DRAM_RD_PRI_QUANT_PRI2 0x0654 |
|---|
| 2739 | #define mmMMEA3_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 2740 | #define mmMMEA3_DRAM_RD_PRI_QUANT_PRI3 0x0655 |
|---|
| 2741 | #define mmMMEA3_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 2742 | #define mmMMEA3_DRAM_WR_PRI_QUANT_PRI1 0x0656 |
|---|
| 2743 | #define mmMMEA3_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 2744 | #define mmMMEA3_DRAM_WR_PRI_QUANT_PRI2 0x0657 |
|---|
| 2745 | #define mmMMEA3_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 2746 | #define mmMMEA3_DRAM_WR_PRI_QUANT_PRI3 0x0658 |
|---|
| 2747 | #define mmMMEA3_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 2748 | #define mmMMEA3_GMI_RD_CLI2GRP_MAP0 0x0659 |
|---|
| 2749 | #define mmMMEA3_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 2750 | #define mmMMEA3_GMI_RD_CLI2GRP_MAP1 0x065a |
|---|
| 2751 | #define mmMMEA3_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 2752 | #define mmMMEA3_GMI_WR_CLI2GRP_MAP0 0x065b |
|---|
| 2753 | #define mmMMEA3_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 2754 | #define mmMMEA3_GMI_WR_CLI2GRP_MAP1 0x065c |
|---|
| 2755 | #define mmMMEA3_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 2756 | #define mmMMEA3_GMI_RD_GRP2VC_MAP 0x065d |
|---|
| 2757 | #define mmMMEA3_GMI_RD_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 2758 | #define mmMMEA3_GMI_WR_GRP2VC_MAP 0x065e |
|---|
| 2759 | #define mmMMEA3_GMI_WR_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 2760 | #define mmMMEA3_GMI_RD_LAZY 0x065f |
|---|
| 2761 | #define mmMMEA3_GMI_RD_LAZY_BASE_IDX 1 |
|---|
| 2762 | #define mmMMEA3_GMI_WR_LAZY 0x0660 |
|---|
| 2763 | #define mmMMEA3_GMI_WR_LAZY_BASE_IDX 1 |
|---|
| 2764 | #define mmMMEA3_GMI_RD_CAM_CNTL 0x0661 |
|---|
| 2765 | #define mmMMEA3_GMI_RD_CAM_CNTL_BASE_IDX 1 |
|---|
| 2766 | #define mmMMEA3_GMI_WR_CAM_CNTL 0x0662 |
|---|
| 2767 | #define mmMMEA3_GMI_WR_CAM_CNTL_BASE_IDX 1 |
|---|
| 2768 | #define mmMMEA3_GMI_PAGE_BURST 0x0663 |
|---|
| 2769 | #define mmMMEA3_GMI_PAGE_BURST_BASE_IDX 1 |
|---|
| 2770 | #define mmMMEA3_GMI_RD_PRI_AGE 0x0664 |
|---|
| 2771 | #define mmMMEA3_GMI_RD_PRI_AGE_BASE_IDX 1 |
|---|
| 2772 | #define mmMMEA3_GMI_WR_PRI_AGE 0x0665 |
|---|
| 2773 | #define mmMMEA3_GMI_WR_PRI_AGE_BASE_IDX 1 |
|---|
| 2774 | #define mmMMEA3_GMI_RD_PRI_QUEUING 0x0666 |
|---|
| 2775 | #define mmMMEA3_GMI_RD_PRI_QUEUING_BASE_IDX 1 |
|---|
| 2776 | #define mmMMEA3_GMI_WR_PRI_QUEUING 0x0667 |
|---|
| 2777 | #define mmMMEA3_GMI_WR_PRI_QUEUING_BASE_IDX 1 |
|---|
| 2778 | #define mmMMEA3_GMI_RD_PRI_FIXED 0x0668 |
|---|
| 2779 | #define mmMMEA3_GMI_RD_PRI_FIXED_BASE_IDX 1 |
|---|
| 2780 | #define mmMMEA3_GMI_WR_PRI_FIXED 0x0669 |
|---|
| 2781 | #define mmMMEA3_GMI_WR_PRI_FIXED_BASE_IDX 1 |
|---|
| 2782 | #define mmMMEA3_GMI_RD_PRI_URGENCY 0x066a |
|---|
| 2783 | #define mmMMEA3_GMI_RD_PRI_URGENCY_BASE_IDX 1 |
|---|
| 2784 | #define mmMMEA3_GMI_WR_PRI_URGENCY 0x066b |
|---|
| 2785 | #define mmMMEA3_GMI_WR_PRI_URGENCY_BASE_IDX 1 |
|---|
| 2786 | #define mmMMEA3_GMI_RD_PRI_URGENCY_MASKING 0x066c |
|---|
| 2787 | #define mmMMEA3_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 2788 | #define mmMMEA3_GMI_WR_PRI_URGENCY_MASKING 0x066d |
|---|
| 2789 | #define mmMMEA3_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 2790 | #define mmMMEA3_GMI_RD_PRI_QUANT_PRI1 0x066e |
|---|
| 2791 | #define mmMMEA3_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 2792 | #define mmMMEA3_GMI_RD_PRI_QUANT_PRI2 0x066f |
|---|
| 2793 | #define mmMMEA3_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 2794 | #define mmMMEA3_GMI_RD_PRI_QUANT_PRI3 0x0670 |
|---|
| 2795 | #define mmMMEA3_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 2796 | #define mmMMEA3_GMI_WR_PRI_QUANT_PRI1 0x0671 |
|---|
| 2797 | #define mmMMEA3_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 2798 | #define mmMMEA3_GMI_WR_PRI_QUANT_PRI2 0x0672 |
|---|
| 2799 | #define mmMMEA3_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 2800 | #define mmMMEA3_GMI_WR_PRI_QUANT_PRI3 0x0673 |
|---|
| 2801 | #define mmMMEA3_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 2802 | #define mmMMEA3_ADDRNORM_BASE_ADDR0 0x0674 |
|---|
| 2803 | #define mmMMEA3_ADDRNORM_BASE_ADDR0_BASE_IDX 1 |
|---|
| 2804 | #define mmMMEA3_ADDRNORM_LIMIT_ADDR0 0x0675 |
|---|
| 2805 | #define mmMMEA3_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1 |
|---|
| 2806 | #define mmMMEA3_ADDRNORM_BASE_ADDR1 0x0676 |
|---|
| 2807 | #define mmMMEA3_ADDRNORM_BASE_ADDR1_BASE_IDX 1 |
|---|
| 2808 | #define mmMMEA3_ADDRNORM_LIMIT_ADDR1 0x0677 |
|---|
| 2809 | #define mmMMEA3_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1 |
|---|
| 2810 | #define mmMMEA3_ADDRNORM_OFFSET_ADDR1 0x0678 |
|---|
| 2811 | #define mmMMEA3_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1 |
|---|
| 2812 | #define mmMMEA3_ADDRNORM_BASE_ADDR2 0x0679 |
|---|
| 2813 | #define mmMMEA3_ADDRNORM_BASE_ADDR2_BASE_IDX 1 |
|---|
| 2814 | #define mmMMEA3_ADDRNORM_LIMIT_ADDR2 0x067a |
|---|
| 2815 | #define mmMMEA3_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1 |
|---|
| 2816 | #define mmMMEA3_ADDRNORM_BASE_ADDR3 0x067b |
|---|
| 2817 | #define mmMMEA3_ADDRNORM_BASE_ADDR3_BASE_IDX 1 |
|---|
| 2818 | #define mmMMEA3_ADDRNORM_LIMIT_ADDR3 0x067c |
|---|
| 2819 | #define mmMMEA3_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1 |
|---|
| 2820 | #define mmMMEA3_ADDRNORM_OFFSET_ADDR3 0x067d |
|---|
| 2821 | #define mmMMEA3_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1 |
|---|
| 2822 | #define mmMMEA3_ADDRNORM_BASE_ADDR4 0x067e |
|---|
| 2823 | #define mmMMEA3_ADDRNORM_BASE_ADDR4_BASE_IDX 1 |
|---|
| 2824 | #define mmMMEA3_ADDRNORM_LIMIT_ADDR4 0x067f |
|---|
| 2825 | #define mmMMEA3_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1 |
|---|
| 2826 | #define mmMMEA3_ADDRNORM_BASE_ADDR5 0x0680 |
|---|
| 2827 | #define mmMMEA3_ADDRNORM_BASE_ADDR5_BASE_IDX 1 |
|---|
| 2828 | #define mmMMEA3_ADDRNORM_LIMIT_ADDR5 0x0681 |
|---|
| 2829 | #define mmMMEA3_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1 |
|---|
| 2830 | #define mmMMEA3_ADDRNORM_OFFSET_ADDR5 0x0682 |
|---|
| 2831 | #define mmMMEA3_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1 |
|---|
| 2832 | #define mmMMEA3_ADDRNORMDRAM_HOLE_CNTL 0x0683 |
|---|
| 2833 | #define mmMMEA3_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1 |
|---|
| 2834 | #define mmMMEA3_ADDRNORMGMI_HOLE_CNTL 0x0684 |
|---|
| 2835 | #define mmMMEA3_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1 |
|---|
| 2836 | #define mmMMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0685 |
|---|
| 2837 | #define mmMMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1 |
|---|
| 2838 | #define mmMMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0686 |
|---|
| 2839 | #define mmMMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1 |
|---|
| 2840 | #define mmMMEA3_ADDRDEC_BANK_CFG 0x0687 |
|---|
| 2841 | #define mmMMEA3_ADDRDEC_BANK_CFG_BASE_IDX 1 |
|---|
| 2842 | #define mmMMEA3_ADDRDEC_MISC_CFG 0x0688 |
|---|
| 2843 | #define mmMMEA3_ADDRDEC_MISC_CFG_BASE_IDX 1 |
|---|
| 2844 | #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK0 0x0689 |
|---|
| 2845 | #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1 |
|---|
| 2846 | #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK1 0x068a |
|---|
| 2847 | #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1 |
|---|
| 2848 | #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK2 0x068b |
|---|
| 2849 | #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1 |
|---|
| 2850 | #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK3 0x068c |
|---|
| 2851 | #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1 |
|---|
| 2852 | #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK4 0x068d |
|---|
| 2853 | #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1 |
|---|
| 2854 | #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK5 0x068e |
|---|
| 2855 | #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1 |
|---|
| 2856 | #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC 0x068f |
|---|
| 2857 | #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1 |
|---|
| 2858 | #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC2 0x0690 |
|---|
| 2859 | #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1 |
|---|
| 2860 | #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS0 0x0691 |
|---|
| 2861 | #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1 |
|---|
| 2862 | #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS1 0x0692 |
|---|
| 2863 | #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1 |
|---|
| 2864 | #define mmMMEA3_ADDRDECDRAM_HARVEST_ENABLE 0x0693 |
|---|
| 2865 | #define mmMMEA3_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1 |
|---|
| 2866 | #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK0 0x0694 |
|---|
| 2867 | #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1 |
|---|
| 2868 | #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK1 0x0695 |
|---|
| 2869 | #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1 |
|---|
| 2870 | #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK2 0x0696 |
|---|
| 2871 | #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1 |
|---|
| 2872 | #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK3 0x0697 |
|---|
| 2873 | #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1 |
|---|
| 2874 | #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK4 0x0698 |
|---|
| 2875 | #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1 |
|---|
| 2876 | #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK5 0x0699 |
|---|
| 2877 | #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1 |
|---|
| 2878 | #define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC 0x069a |
|---|
| 2879 | #define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1 |
|---|
| 2880 | #define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC2 0x069b |
|---|
| 2881 | #define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1 |
|---|
| 2882 | #define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS0 0x069c |
|---|
| 2883 | #define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1 |
|---|
| 2884 | #define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS1 0x069d |
|---|
| 2885 | #define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1 |
|---|
| 2886 | #define mmMMEA3_ADDRDECGMI_HARVEST_ENABLE 0x069e |
|---|
| 2887 | #define mmMMEA3_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1 |
|---|
| 2888 | #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS0 0x069f |
|---|
| 2889 | #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1 |
|---|
| 2890 | #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS1 0x06a0 |
|---|
| 2891 | #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1 |
|---|
| 2892 | #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS2 0x06a1 |
|---|
| 2893 | #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1 |
|---|
| 2894 | #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS3 0x06a2 |
|---|
| 2895 | #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1 |
|---|
| 2896 | #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS0 0x06a3 |
|---|
| 2897 | #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1 |
|---|
| 2898 | #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS1 0x06a4 |
|---|
| 2899 | #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1 |
|---|
| 2900 | #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS2 0x06a5 |
|---|
| 2901 | #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1 |
|---|
| 2902 | #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS3 0x06a6 |
|---|
| 2903 | #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1 |
|---|
| 2904 | #define mmMMEA3_ADDRDEC0_ADDR_MASK_CS01 0x06a7 |
|---|
| 2905 | #define mmMMEA3_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1 |
|---|
| 2906 | #define mmMMEA3_ADDRDEC0_ADDR_MASK_CS23 0x06a8 |
|---|
| 2907 | #define mmMMEA3_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1 |
|---|
| 2908 | #define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS01 0x06a9 |
|---|
| 2909 | #define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1 |
|---|
| 2910 | #define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS23 0x06aa |
|---|
| 2911 | #define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1 |
|---|
| 2912 | #define mmMMEA3_ADDRDEC0_ADDR_CFG_CS01 0x06ab |
|---|
| 2913 | #define mmMMEA3_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1 |
|---|
| 2914 | #define mmMMEA3_ADDRDEC0_ADDR_CFG_CS23 0x06ac |
|---|
| 2915 | #define mmMMEA3_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1 |
|---|
| 2916 | #define mmMMEA3_ADDRDEC0_ADDR_SEL_CS01 0x06ad |
|---|
| 2917 | #define mmMMEA3_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1 |
|---|
| 2918 | #define mmMMEA3_ADDRDEC0_ADDR_SEL_CS23 0x06ae |
|---|
| 2919 | #define mmMMEA3_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1 |
|---|
| 2920 | #define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS01 0x06af |
|---|
| 2921 | #define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1 |
|---|
| 2922 | #define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS23 0x06b0 |
|---|
| 2923 | #define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1 |
|---|
| 2924 | #define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS01 0x06b1 |
|---|
| 2925 | #define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1 |
|---|
| 2926 | #define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS23 0x06b2 |
|---|
| 2927 | #define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1 |
|---|
| 2928 | #define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS01 0x06b3 |
|---|
| 2929 | #define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1 |
|---|
| 2930 | #define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS23 0x06b4 |
|---|
| 2931 | #define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1 |
|---|
| 2932 | #define mmMMEA3_ADDRDEC0_RM_SEL_CS01 0x06b5 |
|---|
| 2933 | #define mmMMEA3_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1 |
|---|
| 2934 | #define mmMMEA3_ADDRDEC0_RM_SEL_CS23 0x06b6 |
|---|
| 2935 | #define mmMMEA3_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1 |
|---|
| 2936 | #define mmMMEA3_ADDRDEC0_RM_SEL_SECCS01 0x06b7 |
|---|
| 2937 | #define mmMMEA3_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1 |
|---|
| 2938 | #define mmMMEA3_ADDRDEC0_RM_SEL_SECCS23 0x06b8 |
|---|
| 2939 | #define mmMMEA3_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1 |
|---|
| 2940 | #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS0 0x06b9 |
|---|
| 2941 | #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1 |
|---|
| 2942 | #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS1 0x06ba |
|---|
| 2943 | #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1 |
|---|
| 2944 | #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS2 0x06bb |
|---|
| 2945 | #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1 |
|---|
| 2946 | #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS3 0x06bc |
|---|
| 2947 | #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1 |
|---|
| 2948 | #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS0 0x06bd |
|---|
| 2949 | #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1 |
|---|
| 2950 | #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS1 0x06be |
|---|
| 2951 | #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1 |
|---|
| 2952 | #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS2 0x06bf |
|---|
| 2953 | #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1 |
|---|
| 2954 | #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS3 0x06c0 |
|---|
| 2955 | #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1 |
|---|
| 2956 | #define mmMMEA3_ADDRDEC1_ADDR_MASK_CS01 0x06c1 |
|---|
| 2957 | #define mmMMEA3_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1 |
|---|
| 2958 | #define mmMMEA3_ADDRDEC1_ADDR_MASK_CS23 0x06c2 |
|---|
| 2959 | #define mmMMEA3_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1 |
|---|
| 2960 | #define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS01 0x06c3 |
|---|
| 2961 | #define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1 |
|---|
| 2962 | #define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS23 0x06c4 |
|---|
| 2963 | #define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1 |
|---|
| 2964 | #define mmMMEA3_ADDRDEC1_ADDR_CFG_CS01 0x06c5 |
|---|
| 2965 | #define mmMMEA3_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1 |
|---|
| 2966 | #define mmMMEA3_ADDRDEC1_ADDR_CFG_CS23 0x06c6 |
|---|
| 2967 | #define mmMMEA3_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1 |
|---|
| 2968 | #define mmMMEA3_ADDRDEC1_ADDR_SEL_CS01 0x06c7 |
|---|
| 2969 | #define mmMMEA3_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1 |
|---|
| 2970 | #define mmMMEA3_ADDRDEC1_ADDR_SEL_CS23 0x06c8 |
|---|
| 2971 | #define mmMMEA3_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1 |
|---|
| 2972 | #define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS01 0x06c9 |
|---|
| 2973 | #define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1 |
|---|
| 2974 | #define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS23 0x06ca |
|---|
| 2975 | #define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1 |
|---|
| 2976 | #define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS01 0x06cb |
|---|
| 2977 | #define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1 |
|---|
| 2978 | #define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS23 0x06cc |
|---|
| 2979 | #define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1 |
|---|
| 2980 | #define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS01 0x06cd |
|---|
| 2981 | #define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1 |
|---|
| 2982 | #define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS23 0x06ce |
|---|
| 2983 | #define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1 |
|---|
| 2984 | #define mmMMEA3_ADDRDEC1_RM_SEL_CS01 0x06cf |
|---|
| 2985 | #define mmMMEA3_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1 |
|---|
| 2986 | #define mmMMEA3_ADDRDEC1_RM_SEL_CS23 0x06d0 |
|---|
| 2987 | #define mmMMEA3_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1 |
|---|
| 2988 | #define mmMMEA3_ADDRDEC1_RM_SEL_SECCS01 0x06d1 |
|---|
| 2989 | #define mmMMEA3_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1 |
|---|
| 2990 | #define mmMMEA3_ADDRDEC1_RM_SEL_SECCS23 0x06d2 |
|---|
| 2991 | #define mmMMEA3_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1 |
|---|
| 2992 | #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS0 0x06d3 |
|---|
| 2993 | #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1 |
|---|
| 2994 | #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS1 0x06d4 |
|---|
| 2995 | #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1 |
|---|
| 2996 | #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS2 0x06d5 |
|---|
| 2997 | #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1 |
|---|
| 2998 | #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS3 0x06d6 |
|---|
| 2999 | #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1 |
|---|
| 3000 | #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS0 0x06d7 |
|---|
| 3001 | #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1 |
|---|
| 3002 | #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS1 0x06d8 |
|---|
| 3003 | #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1 |
|---|
| 3004 | #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS2 0x06d9 |
|---|
| 3005 | #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1 |
|---|
| 3006 | #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS3 0x06da |
|---|
| 3007 | #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1 |
|---|
| 3008 | #define mmMMEA3_ADDRDEC2_ADDR_MASK_CS01 0x06db |
|---|
| 3009 | #define mmMMEA3_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1 |
|---|
| 3010 | #define mmMMEA3_ADDRDEC2_ADDR_MASK_CS23 0x06dc |
|---|
| 3011 | #define mmMMEA3_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1 |
|---|
| 3012 | #define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS01 0x06dd |
|---|
| 3013 | #define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1 |
|---|
| 3014 | #define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS23 0x06de |
|---|
| 3015 | #define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1 |
|---|
| 3016 | #define mmMMEA3_ADDRDEC2_ADDR_CFG_CS01 0x06df |
|---|
| 3017 | #define mmMMEA3_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1 |
|---|
| 3018 | #define mmMMEA3_ADDRDEC2_ADDR_CFG_CS23 0x06e0 |
|---|
| 3019 | #define mmMMEA3_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1 |
|---|
| 3020 | #define mmMMEA3_ADDRDEC2_ADDR_SEL_CS01 0x06e1 |
|---|
| 3021 | #define mmMMEA3_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1 |
|---|
| 3022 | #define mmMMEA3_ADDRDEC2_ADDR_SEL_CS23 0x06e2 |
|---|
| 3023 | #define mmMMEA3_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1 |
|---|
| 3024 | #define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS01 0x06e3 |
|---|
| 3025 | #define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1 |
|---|
| 3026 | #define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS23 0x06e4 |
|---|
| 3027 | #define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1 |
|---|
| 3028 | #define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS01 0x06e5 |
|---|
| 3029 | #define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1 |
|---|
| 3030 | #define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS23 0x06e6 |
|---|
| 3031 | #define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1 |
|---|
| 3032 | #define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS01 0x06e7 |
|---|
| 3033 | #define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1 |
|---|
| 3034 | #define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS23 0x06e8 |
|---|
| 3035 | #define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1 |
|---|
| 3036 | #define mmMMEA3_ADDRDEC2_RM_SEL_CS01 0x06e9 |
|---|
| 3037 | #define mmMMEA3_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1 |
|---|
| 3038 | #define mmMMEA3_ADDRDEC2_RM_SEL_CS23 0x06ea |
|---|
| 3039 | #define mmMMEA3_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1 |
|---|
| 3040 | #define mmMMEA3_ADDRDEC2_RM_SEL_SECCS01 0x06eb |
|---|
| 3041 | #define mmMMEA3_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1 |
|---|
| 3042 | #define mmMMEA3_ADDRDEC2_RM_SEL_SECCS23 0x06ec |
|---|
| 3043 | #define mmMMEA3_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1 |
|---|
| 3044 | #define mmMMEA3_ADDRNORMDRAM_GLOBAL_CNTL 0x06ed |
|---|
| 3045 | #define mmMMEA3_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1 |
|---|
| 3046 | #define mmMMEA3_ADDRNORMGMI_GLOBAL_CNTL 0x06ee |
|---|
| 3047 | #define mmMMEA3_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1 |
|---|
| 3048 | #define mmMMEA3_IO_RD_CLI2GRP_MAP0 0x0715 |
|---|
| 3049 | #define mmMMEA3_IO_RD_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 3050 | #define mmMMEA3_IO_RD_CLI2GRP_MAP1 0x0716 |
|---|
| 3051 | #define mmMMEA3_IO_RD_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 3052 | #define mmMMEA3_IO_WR_CLI2GRP_MAP0 0x0717 |
|---|
| 3053 | #define mmMMEA3_IO_WR_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 3054 | #define mmMMEA3_IO_WR_CLI2GRP_MAP1 0x0718 |
|---|
| 3055 | #define mmMMEA3_IO_WR_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 3056 | #define mmMMEA3_IO_RD_COMBINE_FLUSH 0x0719 |
|---|
| 3057 | #define mmMMEA3_IO_RD_COMBINE_FLUSH_BASE_IDX 1 |
|---|
| 3058 | #define mmMMEA3_IO_WR_COMBINE_FLUSH 0x071a |
|---|
| 3059 | #define mmMMEA3_IO_WR_COMBINE_FLUSH_BASE_IDX 1 |
|---|
| 3060 | #define mmMMEA3_IO_GROUP_BURST 0x071b |
|---|
| 3061 | #define mmMMEA3_IO_GROUP_BURST_BASE_IDX 1 |
|---|
| 3062 | #define mmMMEA3_IO_RD_PRI_AGE 0x071c |
|---|
| 3063 | #define mmMMEA3_IO_RD_PRI_AGE_BASE_IDX 1 |
|---|
| 3064 | #define mmMMEA3_IO_WR_PRI_AGE 0x071d |
|---|
| 3065 | #define mmMMEA3_IO_WR_PRI_AGE_BASE_IDX 1 |
|---|
| 3066 | #define mmMMEA3_IO_RD_PRI_QUEUING 0x071e |
|---|
| 3067 | #define mmMMEA3_IO_RD_PRI_QUEUING_BASE_IDX 1 |
|---|
| 3068 | #define mmMMEA3_IO_WR_PRI_QUEUING 0x071f |
|---|
| 3069 | #define mmMMEA3_IO_WR_PRI_QUEUING_BASE_IDX 1 |
|---|
| 3070 | #define mmMMEA3_IO_RD_PRI_FIXED 0x0720 |
|---|
| 3071 | #define mmMMEA3_IO_RD_PRI_FIXED_BASE_IDX 1 |
|---|
| 3072 | #define mmMMEA3_IO_WR_PRI_FIXED 0x0721 |
|---|
| 3073 | #define mmMMEA3_IO_WR_PRI_FIXED_BASE_IDX 1 |
|---|
| 3074 | #define mmMMEA3_IO_RD_PRI_URGENCY 0x0722 |
|---|
| 3075 | #define mmMMEA3_IO_RD_PRI_URGENCY_BASE_IDX 1 |
|---|
| 3076 | #define mmMMEA3_IO_WR_PRI_URGENCY 0x0723 |
|---|
| 3077 | #define mmMMEA3_IO_WR_PRI_URGENCY_BASE_IDX 1 |
|---|
| 3078 | #define mmMMEA3_IO_RD_PRI_URGENCY_MASKING 0x0724 |
|---|
| 3079 | #define mmMMEA3_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 3080 | #define mmMMEA3_IO_WR_PRI_URGENCY_MASKING 0x0725 |
|---|
| 3081 | #define mmMMEA3_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 3082 | #define mmMMEA3_IO_RD_PRI_QUANT_PRI1 0x0726 |
|---|
| 3083 | #define mmMMEA3_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 3084 | #define mmMMEA3_IO_RD_PRI_QUANT_PRI2 0x0727 |
|---|
| 3085 | #define mmMMEA3_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 3086 | #define mmMMEA3_IO_RD_PRI_QUANT_PRI3 0x0728 |
|---|
| 3087 | #define mmMMEA3_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 3088 | #define mmMMEA3_IO_WR_PRI_QUANT_PRI1 0x0729 |
|---|
| 3089 | #define mmMMEA3_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 3090 | #define mmMMEA3_IO_WR_PRI_QUANT_PRI2 0x072a |
|---|
| 3091 | #define mmMMEA3_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 3092 | #define mmMMEA3_IO_WR_PRI_QUANT_PRI3 0x072b |
|---|
| 3093 | #define mmMMEA3_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 3094 | #define mmMMEA3_SDP_ARB_DRAM 0x072c |
|---|
| 3095 | #define mmMMEA3_SDP_ARB_DRAM_BASE_IDX 1 |
|---|
| 3096 | #define mmMMEA3_SDP_ARB_GMI 0x072d |
|---|
| 3097 | #define mmMMEA3_SDP_ARB_GMI_BASE_IDX 1 |
|---|
| 3098 | #define mmMMEA3_SDP_ARB_FINAL 0x072e |
|---|
| 3099 | #define mmMMEA3_SDP_ARB_FINAL_BASE_IDX 1 |
|---|
| 3100 | #define mmMMEA3_SDP_DRAM_PRIORITY 0x072f |
|---|
| 3101 | #define mmMMEA3_SDP_DRAM_PRIORITY_BASE_IDX 1 |
|---|
| 3102 | #define mmMMEA3_SDP_GMI_PRIORITY 0x0730 |
|---|
| 3103 | #define mmMMEA3_SDP_GMI_PRIORITY_BASE_IDX 1 |
|---|
| 3104 | #define mmMMEA3_SDP_IO_PRIORITY 0x0731 |
|---|
| 3105 | #define mmMMEA3_SDP_IO_PRIORITY_BASE_IDX 1 |
|---|
| 3106 | #define mmMMEA3_SDP_CREDITS 0x0732 |
|---|
| 3107 | #define mmMMEA3_SDP_CREDITS_BASE_IDX 1 |
|---|
| 3108 | #define mmMMEA3_SDP_TAG_RESERVE0 0x0733 |
|---|
| 3109 | #define mmMMEA3_SDP_TAG_RESERVE0_BASE_IDX 1 |
|---|
| 3110 | #define mmMMEA3_SDP_TAG_RESERVE1 0x0734 |
|---|
| 3111 | #define mmMMEA3_SDP_TAG_RESERVE1_BASE_IDX 1 |
|---|
| 3112 | #define mmMMEA3_SDP_VCC_RESERVE0 0x0735 |
|---|
| 3113 | #define mmMMEA3_SDP_VCC_RESERVE0_BASE_IDX 1 |
|---|
| 3114 | #define mmMMEA3_SDP_VCC_RESERVE1 0x0736 |
|---|
| 3115 | #define mmMMEA3_SDP_VCC_RESERVE1_BASE_IDX 1 |
|---|
| 3116 | #define mmMMEA3_SDP_VCD_RESERVE0 0x0737 |
|---|
| 3117 | #define mmMMEA3_SDP_VCD_RESERVE0_BASE_IDX 1 |
|---|
| 3118 | #define mmMMEA3_SDP_VCD_RESERVE1 0x0738 |
|---|
| 3119 | #define mmMMEA3_SDP_VCD_RESERVE1_BASE_IDX 1 |
|---|
| 3120 | #define mmMMEA3_SDP_REQ_CNTL 0x0739 |
|---|
| 3121 | #define mmMMEA3_SDP_REQ_CNTL_BASE_IDX 1 |
|---|
| 3122 | #define mmMMEA3_MISC 0x073a |
|---|
| 3123 | #define mmMMEA3_MISC_BASE_IDX 1 |
|---|
| 3124 | #define mmMMEA3_LATENCY_SAMPLING 0x073b |
|---|
| 3125 | #define mmMMEA3_LATENCY_SAMPLING_BASE_IDX 1 |
|---|
| 3126 | #define mmMMEA3_PERFCOUNTER_LO 0x073c |
|---|
| 3127 | #define mmMMEA3_PERFCOUNTER_LO_BASE_IDX 1 |
|---|
| 3128 | #define mmMMEA3_PERFCOUNTER_HI 0x073d |
|---|
| 3129 | #define mmMMEA3_PERFCOUNTER_HI_BASE_IDX 1 |
|---|
| 3130 | #define mmMMEA3_PERFCOUNTER0_CFG 0x073e |
|---|
| 3131 | #define mmMMEA3_PERFCOUNTER0_CFG_BASE_IDX 1 |
|---|
| 3132 | #define mmMMEA3_PERFCOUNTER1_CFG 0x073f |
|---|
| 3133 | #define mmMMEA3_PERFCOUNTER1_CFG_BASE_IDX 1 |
|---|
| 3134 | #define mmMMEA3_PERFCOUNTER_RSLT_CNTL 0x0740 |
|---|
| 3135 | #define mmMMEA3_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
|---|
| 3136 | #define mmMMEA3_EDC_CNT 0x0746 |
|---|
| 3137 | #define mmMMEA3_EDC_CNT_BASE_IDX 1 |
|---|
| 3138 | #define mmMMEA3_EDC_CNT2 0x0747 |
|---|
| 3139 | #define mmMMEA3_EDC_CNT2_BASE_IDX 1 |
|---|
| 3140 | #define mmMMEA3_DSM_CNTL 0x0748 |
|---|
| 3141 | #define mmMMEA3_DSM_CNTL_BASE_IDX 1 |
|---|
| 3142 | #define mmMMEA3_DSM_CNTLA 0x0749 |
|---|
| 3143 | #define mmMMEA3_DSM_CNTLA_BASE_IDX 1 |
|---|
| 3144 | #define mmMMEA3_DSM_CNTLB 0x074a |
|---|
| 3145 | #define mmMMEA3_DSM_CNTLB_BASE_IDX 1 |
|---|
| 3146 | #define mmMMEA3_DSM_CNTL2 0x074b |
|---|
| 3147 | #define mmMMEA3_DSM_CNTL2_BASE_IDX 1 |
|---|
| 3148 | #define mmMMEA3_DSM_CNTL2A 0x074c |
|---|
| 3149 | #define mmMMEA3_DSM_CNTL2A_BASE_IDX 1 |
|---|
| 3150 | #define mmMMEA3_DSM_CNTL2B 0x074d |
|---|
| 3151 | #define mmMMEA3_DSM_CNTL2B_BASE_IDX 1 |
|---|
| 3152 | #define mmMMEA3_CGTT_CLK_CTRL 0x074f |
|---|
| 3153 | #define mmMMEA3_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 3154 | #define mmMMEA3_EDC_MODE 0x0750 |
|---|
| 3155 | #define mmMMEA3_EDC_MODE_BASE_IDX 1 |
|---|
| 3156 | #define mmMMEA3_ERR_STATUS 0x0751 |
|---|
| 3157 | #define mmMMEA3_ERR_STATUS_BASE_IDX 1 |
|---|
| 3158 | #define mmMMEA3_MISC2 0x0752 |
|---|
| 3159 | #define mmMMEA3_MISC2_BASE_IDX 1 |
|---|
| 3160 | #define mmMMEA3_ADDRDEC_SELECT 0x0753 |
|---|
| 3161 | #define mmMMEA3_ADDRDEC_SELECT_BASE_IDX 1 |
|---|
| 3162 | #define mmMMEA3_EDC_CNT3 0x0754 |
|---|
| 3163 | #define mmMMEA3_EDC_CNT3_BASE_IDX 1 |
|---|
| 3164 | |
|---|
| 3165 | |
|---|
| 3166 | // addressBlock: mmhub_ea_mmeadec4 |
|---|
| 3167 | // base address: 0x69e00 |
|---|
| 3168 | #define mmMMEA4_DRAM_RD_CLI2GRP_MAP0 0x0780 |
|---|
| 3169 | #define mmMMEA4_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 3170 | #define mmMMEA4_DRAM_RD_CLI2GRP_MAP1 0x0781 |
|---|
| 3171 | #define mmMMEA4_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 3172 | #define mmMMEA4_DRAM_WR_CLI2GRP_MAP0 0x0782 |
|---|
| 3173 | #define mmMMEA4_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 3174 | #define mmMMEA4_DRAM_WR_CLI2GRP_MAP1 0x0783 |
|---|
| 3175 | #define mmMMEA4_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 3176 | #define mmMMEA4_DRAM_RD_GRP2VC_MAP 0x0784 |
|---|
| 3177 | #define mmMMEA4_DRAM_RD_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 3178 | #define mmMMEA4_DRAM_WR_GRP2VC_MAP 0x0785 |
|---|
| 3179 | #define mmMMEA4_DRAM_WR_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 3180 | #define mmMMEA4_DRAM_RD_LAZY 0x0786 |
|---|
| 3181 | #define mmMMEA4_DRAM_RD_LAZY_BASE_IDX 1 |
|---|
| 3182 | #define mmMMEA4_DRAM_WR_LAZY 0x0787 |
|---|
| 3183 | #define mmMMEA4_DRAM_WR_LAZY_BASE_IDX 1 |
|---|
| 3184 | #define mmMMEA4_DRAM_RD_CAM_CNTL 0x0788 |
|---|
| 3185 | #define mmMMEA4_DRAM_RD_CAM_CNTL_BASE_IDX 1 |
|---|
| 3186 | #define mmMMEA4_DRAM_WR_CAM_CNTL 0x0789 |
|---|
| 3187 | #define mmMMEA4_DRAM_WR_CAM_CNTL_BASE_IDX 1 |
|---|
| 3188 | #define mmMMEA4_DRAM_PAGE_BURST 0x078a |
|---|
| 3189 | #define mmMMEA4_DRAM_PAGE_BURST_BASE_IDX 1 |
|---|
| 3190 | #define mmMMEA4_DRAM_RD_PRI_AGE 0x078b |
|---|
| 3191 | #define mmMMEA4_DRAM_RD_PRI_AGE_BASE_IDX 1 |
|---|
| 3192 | #define mmMMEA4_DRAM_WR_PRI_AGE 0x078c |
|---|
| 3193 | #define mmMMEA4_DRAM_WR_PRI_AGE_BASE_IDX 1 |
|---|
| 3194 | #define mmMMEA4_DRAM_RD_PRI_QUEUING 0x078d |
|---|
| 3195 | #define mmMMEA4_DRAM_RD_PRI_QUEUING_BASE_IDX 1 |
|---|
| 3196 | #define mmMMEA4_DRAM_WR_PRI_QUEUING 0x078e |
|---|
| 3197 | #define mmMMEA4_DRAM_WR_PRI_QUEUING_BASE_IDX 1 |
|---|
| 3198 | #define mmMMEA4_DRAM_RD_PRI_FIXED 0x078f |
|---|
| 3199 | #define mmMMEA4_DRAM_RD_PRI_FIXED_BASE_IDX 1 |
|---|
| 3200 | #define mmMMEA4_DRAM_WR_PRI_FIXED 0x0790 |
|---|
| 3201 | #define mmMMEA4_DRAM_WR_PRI_FIXED_BASE_IDX 1 |
|---|
| 3202 | #define mmMMEA4_DRAM_RD_PRI_URGENCY 0x0791 |
|---|
| 3203 | #define mmMMEA4_DRAM_RD_PRI_URGENCY_BASE_IDX 1 |
|---|
| 3204 | #define mmMMEA4_DRAM_WR_PRI_URGENCY 0x0792 |
|---|
| 3205 | #define mmMMEA4_DRAM_WR_PRI_URGENCY_BASE_IDX 1 |
|---|
| 3206 | #define mmMMEA4_DRAM_RD_PRI_QUANT_PRI1 0x0793 |
|---|
| 3207 | #define mmMMEA4_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 3208 | #define mmMMEA4_DRAM_RD_PRI_QUANT_PRI2 0x0794 |
|---|
| 3209 | #define mmMMEA4_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 3210 | #define mmMMEA4_DRAM_RD_PRI_QUANT_PRI3 0x0795 |
|---|
| 3211 | #define mmMMEA4_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 3212 | #define mmMMEA4_DRAM_WR_PRI_QUANT_PRI1 0x0796 |
|---|
| 3213 | #define mmMMEA4_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 3214 | #define mmMMEA4_DRAM_WR_PRI_QUANT_PRI2 0x0797 |
|---|
| 3215 | #define mmMMEA4_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 3216 | #define mmMMEA4_DRAM_WR_PRI_QUANT_PRI3 0x0798 |
|---|
| 3217 | #define mmMMEA4_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 3218 | #define mmMMEA4_GMI_RD_CLI2GRP_MAP0 0x0799 |
|---|
| 3219 | #define mmMMEA4_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 3220 | #define mmMMEA4_GMI_RD_CLI2GRP_MAP1 0x079a |
|---|
| 3221 | #define mmMMEA4_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 3222 | #define mmMMEA4_GMI_WR_CLI2GRP_MAP0 0x079b |
|---|
| 3223 | #define mmMMEA4_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 3224 | #define mmMMEA4_GMI_WR_CLI2GRP_MAP1 0x079c |
|---|
| 3225 | #define mmMMEA4_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 3226 | #define mmMMEA4_GMI_RD_GRP2VC_MAP 0x079d |
|---|
| 3227 | #define mmMMEA4_GMI_RD_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 3228 | #define mmMMEA4_GMI_WR_GRP2VC_MAP 0x079e |
|---|
| 3229 | #define mmMMEA4_GMI_WR_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 3230 | #define mmMMEA4_GMI_RD_LAZY 0x079f |
|---|
| 3231 | #define mmMMEA4_GMI_RD_LAZY_BASE_IDX 1 |
|---|
| 3232 | #define mmMMEA4_GMI_WR_LAZY 0x07a0 |
|---|
| 3233 | #define mmMMEA4_GMI_WR_LAZY_BASE_IDX 1 |
|---|
| 3234 | #define mmMMEA4_GMI_RD_CAM_CNTL 0x07a1 |
|---|
| 3235 | #define mmMMEA4_GMI_RD_CAM_CNTL_BASE_IDX 1 |
|---|
| 3236 | #define mmMMEA4_GMI_WR_CAM_CNTL 0x07a2 |
|---|
| 3237 | #define mmMMEA4_GMI_WR_CAM_CNTL_BASE_IDX 1 |
|---|
| 3238 | #define mmMMEA4_GMI_PAGE_BURST 0x07a3 |
|---|
| 3239 | #define mmMMEA4_GMI_PAGE_BURST_BASE_IDX 1 |
|---|
| 3240 | #define mmMMEA4_GMI_RD_PRI_AGE 0x07a4 |
|---|
| 3241 | #define mmMMEA4_GMI_RD_PRI_AGE_BASE_IDX 1 |
|---|
| 3242 | #define mmMMEA4_GMI_WR_PRI_AGE 0x07a5 |
|---|
| 3243 | #define mmMMEA4_GMI_WR_PRI_AGE_BASE_IDX 1 |
|---|
| 3244 | #define mmMMEA4_GMI_RD_PRI_QUEUING 0x07a6 |
|---|
| 3245 | #define mmMMEA4_GMI_RD_PRI_QUEUING_BASE_IDX 1 |
|---|
| 3246 | #define mmMMEA4_GMI_WR_PRI_QUEUING 0x07a7 |
|---|
| 3247 | #define mmMMEA4_GMI_WR_PRI_QUEUING_BASE_IDX 1 |
|---|
| 3248 | #define mmMMEA4_GMI_RD_PRI_FIXED 0x07a8 |
|---|
| 3249 | #define mmMMEA4_GMI_RD_PRI_FIXED_BASE_IDX 1 |
|---|
| 3250 | #define mmMMEA4_GMI_WR_PRI_FIXED 0x07a9 |
|---|
| 3251 | #define mmMMEA4_GMI_WR_PRI_FIXED_BASE_IDX 1 |
|---|
| 3252 | #define mmMMEA4_GMI_RD_PRI_URGENCY 0x07aa |
|---|
| 3253 | #define mmMMEA4_GMI_RD_PRI_URGENCY_BASE_IDX 1 |
|---|
| 3254 | #define mmMMEA4_GMI_WR_PRI_URGENCY 0x07ab |
|---|
| 3255 | #define mmMMEA4_GMI_WR_PRI_URGENCY_BASE_IDX 1 |
|---|
| 3256 | #define mmMMEA4_GMI_RD_PRI_URGENCY_MASKING 0x07ac |
|---|
| 3257 | #define mmMMEA4_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 3258 | #define mmMMEA4_GMI_WR_PRI_URGENCY_MASKING 0x07ad |
|---|
| 3259 | #define mmMMEA4_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 3260 | #define mmMMEA4_GMI_RD_PRI_QUANT_PRI1 0x07ae |
|---|
| 3261 | #define mmMMEA4_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 3262 | #define mmMMEA4_GMI_RD_PRI_QUANT_PRI2 0x07af |
|---|
| 3263 | #define mmMMEA4_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 3264 | #define mmMMEA4_GMI_RD_PRI_QUANT_PRI3 0x07b0 |
|---|
| 3265 | #define mmMMEA4_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 3266 | #define mmMMEA4_GMI_WR_PRI_QUANT_PRI1 0x07b1 |
|---|
| 3267 | #define mmMMEA4_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 3268 | #define mmMMEA4_GMI_WR_PRI_QUANT_PRI2 0x07b2 |
|---|
| 3269 | #define mmMMEA4_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 3270 | #define mmMMEA4_GMI_WR_PRI_QUANT_PRI3 0x07b3 |
|---|
| 3271 | #define mmMMEA4_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 3272 | #define mmMMEA4_ADDRNORM_BASE_ADDR0 0x07b4 |
|---|
| 3273 | #define mmMMEA4_ADDRNORM_BASE_ADDR0_BASE_IDX 1 |
|---|
| 3274 | #define mmMMEA4_ADDRNORM_LIMIT_ADDR0 0x07b5 |
|---|
| 3275 | #define mmMMEA4_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1 |
|---|
| 3276 | #define mmMMEA4_ADDRNORM_BASE_ADDR1 0x07b6 |
|---|
| 3277 | #define mmMMEA4_ADDRNORM_BASE_ADDR1_BASE_IDX 1 |
|---|
| 3278 | #define mmMMEA4_ADDRNORM_LIMIT_ADDR1 0x07b7 |
|---|
| 3279 | #define mmMMEA4_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1 |
|---|
| 3280 | #define mmMMEA4_ADDRNORM_OFFSET_ADDR1 0x07b8 |
|---|
| 3281 | #define mmMMEA4_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1 |
|---|
| 3282 | #define mmMMEA4_ADDRNORM_BASE_ADDR2 0x07b9 |
|---|
| 3283 | #define mmMMEA4_ADDRNORM_BASE_ADDR2_BASE_IDX 1 |
|---|
| 3284 | #define mmMMEA4_ADDRNORM_LIMIT_ADDR2 0x07ba |
|---|
| 3285 | #define mmMMEA4_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1 |
|---|
| 3286 | #define mmMMEA4_ADDRNORM_BASE_ADDR3 0x07bb |
|---|
| 3287 | #define mmMMEA4_ADDRNORM_BASE_ADDR3_BASE_IDX 1 |
|---|
| 3288 | #define mmMMEA4_ADDRNORM_LIMIT_ADDR3 0x07bc |
|---|
| 3289 | #define mmMMEA4_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1 |
|---|
| 3290 | #define mmMMEA4_ADDRNORM_OFFSET_ADDR3 0x07bd |
|---|
| 3291 | #define mmMMEA4_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1 |
|---|
| 3292 | #define mmMMEA4_ADDRNORM_BASE_ADDR4 0x07be |
|---|
| 3293 | #define mmMMEA4_ADDRNORM_BASE_ADDR4_BASE_IDX 1 |
|---|
| 3294 | #define mmMMEA4_ADDRNORM_LIMIT_ADDR4 0x07bf |
|---|
| 3295 | #define mmMMEA4_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1 |
|---|
| 3296 | #define mmMMEA4_ADDRNORM_BASE_ADDR5 0x07c0 |
|---|
| 3297 | #define mmMMEA4_ADDRNORM_BASE_ADDR5_BASE_IDX 1 |
|---|
| 3298 | #define mmMMEA4_ADDRNORM_LIMIT_ADDR5 0x07c1 |
|---|
| 3299 | #define mmMMEA4_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1 |
|---|
| 3300 | #define mmMMEA4_ADDRNORM_OFFSET_ADDR5 0x07c2 |
|---|
| 3301 | #define mmMMEA4_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1 |
|---|
| 3302 | #define mmMMEA4_ADDRNORMDRAM_HOLE_CNTL 0x07c3 |
|---|
| 3303 | #define mmMMEA4_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1 |
|---|
| 3304 | #define mmMMEA4_ADDRNORMGMI_HOLE_CNTL 0x07c4 |
|---|
| 3305 | #define mmMMEA4_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1 |
|---|
| 3306 | #define mmMMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x07c5 |
|---|
| 3307 | #define mmMMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1 |
|---|
| 3308 | #define mmMMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG 0x07c6 |
|---|
| 3309 | #define mmMMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1 |
|---|
| 3310 | #define mmMMEA4_ADDRDEC_BANK_CFG 0x07c7 |
|---|
| 3311 | #define mmMMEA4_ADDRDEC_BANK_CFG_BASE_IDX 1 |
|---|
| 3312 | #define mmMMEA4_ADDRDEC_MISC_CFG 0x07c8 |
|---|
| 3313 | #define mmMMEA4_ADDRDEC_MISC_CFG_BASE_IDX 1 |
|---|
| 3314 | #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK0 0x07c9 |
|---|
| 3315 | #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1 |
|---|
| 3316 | #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK1 0x07ca |
|---|
| 3317 | #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1 |
|---|
| 3318 | #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK2 0x07cb |
|---|
| 3319 | #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1 |
|---|
| 3320 | #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK3 0x07cc |
|---|
| 3321 | #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1 |
|---|
| 3322 | #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK4 0x07cd |
|---|
| 3323 | #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1 |
|---|
| 3324 | #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK5 0x07ce |
|---|
| 3325 | #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1 |
|---|
| 3326 | #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC 0x07cf |
|---|
| 3327 | #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1 |
|---|
| 3328 | #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC2 0x07d0 |
|---|
| 3329 | #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1 |
|---|
| 3330 | #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS0 0x07d1 |
|---|
| 3331 | #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1 |
|---|
| 3332 | #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS1 0x07d2 |
|---|
| 3333 | #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1 |
|---|
| 3334 | #define mmMMEA4_ADDRDECDRAM_HARVEST_ENABLE 0x07d3 |
|---|
| 3335 | #define mmMMEA4_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1 |
|---|
| 3336 | #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK0 0x07d4 |
|---|
| 3337 | #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1 |
|---|
| 3338 | #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK1 0x07d5 |
|---|
| 3339 | #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1 |
|---|
| 3340 | #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK2 0x07d6 |
|---|
| 3341 | #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1 |
|---|
| 3342 | #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK3 0x07d7 |
|---|
| 3343 | #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1 |
|---|
| 3344 | #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK4 0x07d8 |
|---|
| 3345 | #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1 |
|---|
| 3346 | #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK5 0x07d9 |
|---|
| 3347 | #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1 |
|---|
| 3348 | #define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC 0x07da |
|---|
| 3349 | #define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1 |
|---|
| 3350 | #define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC2 0x07db |
|---|
| 3351 | #define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1 |
|---|
| 3352 | #define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS0 0x07dc |
|---|
| 3353 | #define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1 |
|---|
| 3354 | #define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS1 0x07dd |
|---|
| 3355 | #define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1 |
|---|
| 3356 | #define mmMMEA4_ADDRDECGMI_HARVEST_ENABLE 0x07de |
|---|
| 3357 | #define mmMMEA4_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1 |
|---|
| 3358 | #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS0 0x07df |
|---|
| 3359 | #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1 |
|---|
| 3360 | #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS1 0x07e0 |
|---|
| 3361 | #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1 |
|---|
| 3362 | #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS2 0x07e1 |
|---|
| 3363 | #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1 |
|---|
| 3364 | #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS3 0x07e2 |
|---|
| 3365 | #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1 |
|---|
| 3366 | #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS0 0x07e3 |
|---|
| 3367 | #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1 |
|---|
| 3368 | #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS1 0x07e4 |
|---|
| 3369 | #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1 |
|---|
| 3370 | #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS2 0x07e5 |
|---|
| 3371 | #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1 |
|---|
| 3372 | #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS3 0x07e6 |
|---|
| 3373 | #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1 |
|---|
| 3374 | #define mmMMEA4_ADDRDEC0_ADDR_MASK_CS01 0x07e7 |
|---|
| 3375 | #define mmMMEA4_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1 |
|---|
| 3376 | #define mmMMEA4_ADDRDEC0_ADDR_MASK_CS23 0x07e8 |
|---|
| 3377 | #define mmMMEA4_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1 |
|---|
| 3378 | #define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS01 0x07e9 |
|---|
| 3379 | #define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1 |
|---|
| 3380 | #define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS23 0x07ea |
|---|
| 3381 | #define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1 |
|---|
| 3382 | #define mmMMEA4_ADDRDEC0_ADDR_CFG_CS01 0x07eb |
|---|
| 3383 | #define mmMMEA4_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1 |
|---|
| 3384 | #define mmMMEA4_ADDRDEC0_ADDR_CFG_CS23 0x07ec |
|---|
| 3385 | #define mmMMEA4_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1 |
|---|
| 3386 | #define mmMMEA4_ADDRDEC0_ADDR_SEL_CS01 0x07ed |
|---|
| 3387 | #define mmMMEA4_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1 |
|---|
| 3388 | #define mmMMEA4_ADDRDEC0_ADDR_SEL_CS23 0x07ee |
|---|
| 3389 | #define mmMMEA4_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1 |
|---|
| 3390 | #define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS01 0x07ef |
|---|
| 3391 | #define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1 |
|---|
| 3392 | #define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS23 0x07f0 |
|---|
| 3393 | #define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1 |
|---|
| 3394 | #define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS01 0x07f1 |
|---|
| 3395 | #define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1 |
|---|
| 3396 | #define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS23 0x07f2 |
|---|
| 3397 | #define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1 |
|---|
| 3398 | #define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS01 0x07f3 |
|---|
| 3399 | #define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1 |
|---|
| 3400 | #define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS23 0x07f4 |
|---|
| 3401 | #define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1 |
|---|
| 3402 | #define mmMMEA4_ADDRDEC0_RM_SEL_CS01 0x07f5 |
|---|
| 3403 | #define mmMMEA4_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1 |
|---|
| 3404 | #define mmMMEA4_ADDRDEC0_RM_SEL_CS23 0x07f6 |
|---|
| 3405 | #define mmMMEA4_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1 |
|---|
| 3406 | #define mmMMEA4_ADDRDEC0_RM_SEL_SECCS01 0x07f7 |
|---|
| 3407 | #define mmMMEA4_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1 |
|---|
| 3408 | #define mmMMEA4_ADDRDEC0_RM_SEL_SECCS23 0x07f8 |
|---|
| 3409 | #define mmMMEA4_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1 |
|---|
| 3410 | #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS0 0x07f9 |
|---|
| 3411 | #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1 |
|---|
| 3412 | #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS1 0x07fa |
|---|
| 3413 | #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1 |
|---|
| 3414 | #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS2 0x07fb |
|---|
| 3415 | #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1 |
|---|
| 3416 | #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS3 0x07fc |
|---|
| 3417 | #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1 |
|---|
| 3418 | #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS0 0x07fd |
|---|
| 3419 | #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1 |
|---|
| 3420 | #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS1 0x07fe |
|---|
| 3421 | #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1 |
|---|
| 3422 | #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS2 0x07ff |
|---|
| 3423 | #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1 |
|---|
| 3424 | #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS3 0x0800 |
|---|
| 3425 | #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1 |
|---|
| 3426 | #define mmMMEA4_ADDRDEC1_ADDR_MASK_CS01 0x0801 |
|---|
| 3427 | #define mmMMEA4_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1 |
|---|
| 3428 | #define mmMMEA4_ADDRDEC1_ADDR_MASK_CS23 0x0802 |
|---|
| 3429 | #define mmMMEA4_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1 |
|---|
| 3430 | #define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS01 0x0803 |
|---|
| 3431 | #define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1 |
|---|
| 3432 | #define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS23 0x0804 |
|---|
| 3433 | #define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1 |
|---|
| 3434 | #define mmMMEA4_ADDRDEC1_ADDR_CFG_CS01 0x0805 |
|---|
| 3435 | #define mmMMEA4_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1 |
|---|
| 3436 | #define mmMMEA4_ADDRDEC1_ADDR_CFG_CS23 0x0806 |
|---|
| 3437 | #define mmMMEA4_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1 |
|---|
| 3438 | #define mmMMEA4_ADDRDEC1_ADDR_SEL_CS01 0x0807 |
|---|
| 3439 | #define mmMMEA4_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1 |
|---|
| 3440 | #define mmMMEA4_ADDRDEC1_ADDR_SEL_CS23 0x0808 |
|---|
| 3441 | #define mmMMEA4_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1 |
|---|
| 3442 | #define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS01 0x0809 |
|---|
| 3443 | #define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1 |
|---|
| 3444 | #define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS23 0x080a |
|---|
| 3445 | #define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1 |
|---|
| 3446 | #define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS01 0x080b |
|---|
| 3447 | #define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1 |
|---|
| 3448 | #define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS23 0x080c |
|---|
| 3449 | #define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1 |
|---|
| 3450 | #define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS01 0x080d |
|---|
| 3451 | #define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1 |
|---|
| 3452 | #define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS23 0x080e |
|---|
| 3453 | #define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1 |
|---|
| 3454 | #define mmMMEA4_ADDRDEC1_RM_SEL_CS01 0x080f |
|---|
| 3455 | #define mmMMEA4_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1 |
|---|
| 3456 | #define mmMMEA4_ADDRDEC1_RM_SEL_CS23 0x0810 |
|---|
| 3457 | #define mmMMEA4_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1 |
|---|
| 3458 | #define mmMMEA4_ADDRDEC1_RM_SEL_SECCS01 0x0811 |
|---|
| 3459 | #define mmMMEA4_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1 |
|---|
| 3460 | #define mmMMEA4_ADDRDEC1_RM_SEL_SECCS23 0x0812 |
|---|
| 3461 | #define mmMMEA4_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1 |
|---|
| 3462 | #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS0 0x0813 |
|---|
| 3463 | #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1 |
|---|
| 3464 | #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS1 0x0814 |
|---|
| 3465 | #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1 |
|---|
| 3466 | #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS2 0x0815 |
|---|
| 3467 | #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1 |
|---|
| 3468 | #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS3 0x0816 |
|---|
| 3469 | #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1 |
|---|
| 3470 | #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS0 0x0817 |
|---|
| 3471 | #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1 |
|---|
| 3472 | #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS1 0x0818 |
|---|
| 3473 | #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1 |
|---|
| 3474 | #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS2 0x0819 |
|---|
| 3475 | #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1 |
|---|
| 3476 | #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS3 0x081a |
|---|
| 3477 | #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1 |
|---|
| 3478 | #define mmMMEA4_ADDRDEC2_ADDR_MASK_CS01 0x081b |
|---|
| 3479 | #define mmMMEA4_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1 |
|---|
| 3480 | #define mmMMEA4_ADDRDEC2_ADDR_MASK_CS23 0x081c |
|---|
| 3481 | #define mmMMEA4_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1 |
|---|
| 3482 | #define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS01 0x081d |
|---|
| 3483 | #define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1 |
|---|
| 3484 | #define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS23 0x081e |
|---|
| 3485 | #define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1 |
|---|
| 3486 | #define mmMMEA4_ADDRDEC2_ADDR_CFG_CS01 0x081f |
|---|
| 3487 | #define mmMMEA4_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1 |
|---|
| 3488 | #define mmMMEA4_ADDRDEC2_ADDR_CFG_CS23 0x0820 |
|---|
| 3489 | #define mmMMEA4_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1 |
|---|
| 3490 | #define mmMMEA4_ADDRDEC2_ADDR_SEL_CS01 0x0821 |
|---|
| 3491 | #define mmMMEA4_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1 |
|---|
| 3492 | #define mmMMEA4_ADDRDEC2_ADDR_SEL_CS23 0x0822 |
|---|
| 3493 | #define mmMMEA4_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1 |
|---|
| 3494 | #define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS01 0x0823 |
|---|
| 3495 | #define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1 |
|---|
| 3496 | #define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS23 0x0824 |
|---|
| 3497 | #define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1 |
|---|
| 3498 | #define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS01 0x0825 |
|---|
| 3499 | #define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1 |
|---|
| 3500 | #define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS23 0x0826 |
|---|
| 3501 | #define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1 |
|---|
| 3502 | #define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS01 0x0827 |
|---|
| 3503 | #define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1 |
|---|
| 3504 | #define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS23 0x0828 |
|---|
| 3505 | #define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1 |
|---|
| 3506 | #define mmMMEA4_ADDRDEC2_RM_SEL_CS01 0x0829 |
|---|
| 3507 | #define mmMMEA4_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1 |
|---|
| 3508 | #define mmMMEA4_ADDRDEC2_RM_SEL_CS23 0x082a |
|---|
| 3509 | #define mmMMEA4_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1 |
|---|
| 3510 | #define mmMMEA4_ADDRDEC2_RM_SEL_SECCS01 0x082b |
|---|
| 3511 | #define mmMMEA4_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1 |
|---|
| 3512 | #define mmMMEA4_ADDRDEC2_RM_SEL_SECCS23 0x082c |
|---|
| 3513 | #define mmMMEA4_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1 |
|---|
| 3514 | #define mmMMEA4_ADDRNORMDRAM_GLOBAL_CNTL 0x082d |
|---|
| 3515 | #define mmMMEA4_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1 |
|---|
| 3516 | #define mmMMEA4_ADDRNORMGMI_GLOBAL_CNTL 0x082e |
|---|
| 3517 | #define mmMMEA4_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1 |
|---|
| 3518 | #define mmMMEA4_IO_RD_CLI2GRP_MAP0 0x0855 |
|---|
| 3519 | #define mmMMEA4_IO_RD_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 3520 | #define mmMMEA4_IO_RD_CLI2GRP_MAP1 0x0856 |
|---|
| 3521 | #define mmMMEA4_IO_RD_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 3522 | #define mmMMEA4_IO_WR_CLI2GRP_MAP0 0x0857 |
|---|
| 3523 | #define mmMMEA4_IO_WR_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 3524 | #define mmMMEA4_IO_WR_CLI2GRP_MAP1 0x0858 |
|---|
| 3525 | #define mmMMEA4_IO_WR_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 3526 | #define mmMMEA4_IO_RD_COMBINE_FLUSH 0x0859 |
|---|
| 3527 | #define mmMMEA4_IO_RD_COMBINE_FLUSH_BASE_IDX 1 |
|---|
| 3528 | #define mmMMEA4_IO_WR_COMBINE_FLUSH 0x085a |
|---|
| 3529 | #define mmMMEA4_IO_WR_COMBINE_FLUSH_BASE_IDX 1 |
|---|
| 3530 | #define mmMMEA4_IO_GROUP_BURST 0x085b |
|---|
| 3531 | #define mmMMEA4_IO_GROUP_BURST_BASE_IDX 1 |
|---|
| 3532 | #define mmMMEA4_IO_RD_PRI_AGE 0x085c |
|---|
| 3533 | #define mmMMEA4_IO_RD_PRI_AGE_BASE_IDX 1 |
|---|
| 3534 | #define mmMMEA4_IO_WR_PRI_AGE 0x085d |
|---|
| 3535 | #define mmMMEA4_IO_WR_PRI_AGE_BASE_IDX 1 |
|---|
| 3536 | #define mmMMEA4_IO_RD_PRI_QUEUING 0x085e |
|---|
| 3537 | #define mmMMEA4_IO_RD_PRI_QUEUING_BASE_IDX 1 |
|---|
| 3538 | #define mmMMEA4_IO_WR_PRI_QUEUING 0x085f |
|---|
| 3539 | #define mmMMEA4_IO_WR_PRI_QUEUING_BASE_IDX 1 |
|---|
| 3540 | #define mmMMEA4_IO_RD_PRI_FIXED 0x0860 |
|---|
| 3541 | #define mmMMEA4_IO_RD_PRI_FIXED_BASE_IDX 1 |
|---|
| 3542 | #define mmMMEA4_IO_WR_PRI_FIXED 0x0861 |
|---|
| 3543 | #define mmMMEA4_IO_WR_PRI_FIXED_BASE_IDX 1 |
|---|
| 3544 | #define mmMMEA4_IO_RD_PRI_URGENCY 0x0862 |
|---|
| 3545 | #define mmMMEA4_IO_RD_PRI_URGENCY_BASE_IDX 1 |
|---|
| 3546 | #define mmMMEA4_IO_WR_PRI_URGENCY 0x0863 |
|---|
| 3547 | #define mmMMEA4_IO_WR_PRI_URGENCY_BASE_IDX 1 |
|---|
| 3548 | #define mmMMEA4_IO_RD_PRI_URGENCY_MASKING 0x0864 |
|---|
| 3549 | #define mmMMEA4_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 3550 | #define mmMMEA4_IO_WR_PRI_URGENCY_MASKING 0x0865 |
|---|
| 3551 | #define mmMMEA4_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 3552 | #define mmMMEA4_IO_RD_PRI_QUANT_PRI1 0x0866 |
|---|
| 3553 | #define mmMMEA4_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 3554 | #define mmMMEA4_IO_RD_PRI_QUANT_PRI2 0x0867 |
|---|
| 3555 | #define mmMMEA4_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 3556 | #define mmMMEA4_IO_RD_PRI_QUANT_PRI3 0x0868 |
|---|
| 3557 | #define mmMMEA4_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 3558 | #define mmMMEA4_IO_WR_PRI_QUANT_PRI1 0x0869 |
|---|
| 3559 | #define mmMMEA4_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 3560 | #define mmMMEA4_IO_WR_PRI_QUANT_PRI2 0x086a |
|---|
| 3561 | #define mmMMEA4_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 3562 | #define mmMMEA4_IO_WR_PRI_QUANT_PRI3 0x086b |
|---|
| 3563 | #define mmMMEA4_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 3564 | #define mmMMEA4_SDP_ARB_DRAM 0x086c |
|---|
| 3565 | #define mmMMEA4_SDP_ARB_DRAM_BASE_IDX 1 |
|---|
| 3566 | #define mmMMEA4_SDP_ARB_GMI 0x086d |
|---|
| 3567 | #define mmMMEA4_SDP_ARB_GMI_BASE_IDX 1 |
|---|
| 3568 | #define mmMMEA4_SDP_ARB_FINAL 0x086e |
|---|
| 3569 | #define mmMMEA4_SDP_ARB_FINAL_BASE_IDX 1 |
|---|
| 3570 | #define mmMMEA4_SDP_DRAM_PRIORITY 0x086f |
|---|
| 3571 | #define mmMMEA4_SDP_DRAM_PRIORITY_BASE_IDX 1 |
|---|
| 3572 | #define mmMMEA4_SDP_GMI_PRIORITY 0x0870 |
|---|
| 3573 | #define mmMMEA4_SDP_GMI_PRIORITY_BASE_IDX 1 |
|---|
| 3574 | #define mmMMEA4_SDP_IO_PRIORITY 0x0871 |
|---|
| 3575 | #define mmMMEA4_SDP_IO_PRIORITY_BASE_IDX 1 |
|---|
| 3576 | #define mmMMEA4_SDP_CREDITS 0x0872 |
|---|
| 3577 | #define mmMMEA4_SDP_CREDITS_BASE_IDX 1 |
|---|
| 3578 | #define mmMMEA4_SDP_TAG_RESERVE0 0x0873 |
|---|
| 3579 | #define mmMMEA4_SDP_TAG_RESERVE0_BASE_IDX 1 |
|---|
| 3580 | #define mmMMEA4_SDP_TAG_RESERVE1 0x0874 |
|---|
| 3581 | #define mmMMEA4_SDP_TAG_RESERVE1_BASE_IDX 1 |
|---|
| 3582 | #define mmMMEA4_SDP_VCC_RESERVE0 0x0875 |
|---|
| 3583 | #define mmMMEA4_SDP_VCC_RESERVE0_BASE_IDX 1 |
|---|
| 3584 | #define mmMMEA4_SDP_VCC_RESERVE1 0x0876 |
|---|
| 3585 | #define mmMMEA4_SDP_VCC_RESERVE1_BASE_IDX 1 |
|---|
| 3586 | #define mmMMEA4_SDP_VCD_RESERVE0 0x0877 |
|---|
| 3587 | #define mmMMEA4_SDP_VCD_RESERVE0_BASE_IDX 1 |
|---|
| 3588 | #define mmMMEA4_SDP_VCD_RESERVE1 0x0878 |
|---|
| 3589 | #define mmMMEA4_SDP_VCD_RESERVE1_BASE_IDX 1 |
|---|
| 3590 | #define mmMMEA4_SDP_REQ_CNTL 0x0879 |
|---|
| 3591 | #define mmMMEA4_SDP_REQ_CNTL_BASE_IDX 1 |
|---|
| 3592 | #define mmMMEA4_MISC 0x087a |
|---|
| 3593 | #define mmMMEA4_MISC_BASE_IDX 1 |
|---|
| 3594 | #define mmMMEA4_LATENCY_SAMPLING 0x087b |
|---|
| 3595 | #define mmMMEA4_LATENCY_SAMPLING_BASE_IDX 1 |
|---|
| 3596 | #define mmMMEA4_PERFCOUNTER_LO 0x087c |
|---|
| 3597 | #define mmMMEA4_PERFCOUNTER_LO_BASE_IDX 1 |
|---|
| 3598 | #define mmMMEA4_PERFCOUNTER_HI 0x087d |
|---|
| 3599 | #define mmMMEA4_PERFCOUNTER_HI_BASE_IDX 1 |
|---|
| 3600 | #define mmMMEA4_PERFCOUNTER0_CFG 0x087e |
|---|
| 3601 | #define mmMMEA4_PERFCOUNTER0_CFG_BASE_IDX 1 |
|---|
| 3602 | #define mmMMEA4_PERFCOUNTER1_CFG 0x087f |
|---|
| 3603 | #define mmMMEA4_PERFCOUNTER1_CFG_BASE_IDX 1 |
|---|
| 3604 | #define mmMMEA4_PERFCOUNTER_RSLT_CNTL 0x0880 |
|---|
| 3605 | #define mmMMEA4_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
|---|
| 3606 | #define mmMMEA4_EDC_CNT 0x0886 |
|---|
| 3607 | #define mmMMEA4_EDC_CNT_BASE_IDX 1 |
|---|
| 3608 | #define mmMMEA4_EDC_CNT2 0x0887 |
|---|
| 3609 | #define mmMMEA4_EDC_CNT2_BASE_IDX 1 |
|---|
| 3610 | #define mmMMEA4_DSM_CNTL 0x0888 |
|---|
| 3611 | #define mmMMEA4_DSM_CNTL_BASE_IDX 1 |
|---|
| 3612 | #define mmMMEA4_DSM_CNTLA 0x0889 |
|---|
| 3613 | #define mmMMEA4_DSM_CNTLA_BASE_IDX 1 |
|---|
| 3614 | #define mmMMEA4_DSM_CNTLB 0x088a |
|---|
| 3615 | #define mmMMEA4_DSM_CNTLB_BASE_IDX 1 |
|---|
| 3616 | #define mmMMEA4_DSM_CNTL2 0x088b |
|---|
| 3617 | #define mmMMEA4_DSM_CNTL2_BASE_IDX 1 |
|---|
| 3618 | #define mmMMEA4_DSM_CNTL2A 0x088c |
|---|
| 3619 | #define mmMMEA4_DSM_CNTL2A_BASE_IDX 1 |
|---|
| 3620 | #define mmMMEA4_DSM_CNTL2B 0x088d |
|---|
| 3621 | #define mmMMEA4_DSM_CNTL2B_BASE_IDX 1 |
|---|
| 3622 | #define mmMMEA4_CGTT_CLK_CTRL 0x088f |
|---|
| 3623 | #define mmMMEA4_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 3624 | #define mmMMEA4_EDC_MODE 0x0890 |
|---|
| 3625 | #define mmMMEA4_EDC_MODE_BASE_IDX 1 |
|---|
| 3626 | #define mmMMEA4_ERR_STATUS 0x0891 |
|---|
| 3627 | #define mmMMEA4_ERR_STATUS_BASE_IDX 1 |
|---|
| 3628 | #define mmMMEA4_MISC2 0x0892 |
|---|
| 3629 | #define mmMMEA4_MISC2_BASE_IDX 1 |
|---|
| 3630 | #define mmMMEA4_ADDRDEC_SELECT 0x0893 |
|---|
| 3631 | #define mmMMEA4_ADDRDEC_SELECT_BASE_IDX 1 |
|---|
| 3632 | #define mmMMEA4_EDC_CNT3 0x0894 |
|---|
| 3633 | #define mmMMEA4_EDC_CNT3_BASE_IDX 1 |
|---|
| 3634 | |
|---|
| 3635 | |
|---|
| 3636 | // addressBlock: mmhub_pctldec0 |
|---|
| 3637 | // base address: 0x6a300 |
|---|
| 3638 | #define mmPCTL0_CTRL 0x08c0 |
|---|
| 3639 | #define mmPCTL0_CTRL_BASE_IDX 1 |
|---|
| 3640 | #define mmPCTL0_MMHUB_DEEPSLEEP_IB 0x08c1 |
|---|
| 3641 | #define mmPCTL0_MMHUB_DEEPSLEEP_IB_BASE_IDX 1 |
|---|
| 3642 | #define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE 0x08c2 |
|---|
| 3643 | #define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 1 |
|---|
| 3644 | #define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB 0x08c3 |
|---|
| 3645 | #define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX 1 |
|---|
| 3646 | #define mmPCTL0_PG_IGNORE_DEEPSLEEP 0x08c4 |
|---|
| 3647 | #define mmPCTL0_PG_IGNORE_DEEPSLEEP_BASE_IDX 1 |
|---|
| 3648 | #define mmPCTL0_PG_IGNORE_DEEPSLEEP_IB 0x08c5 |
|---|
| 3649 | #define mmPCTL0_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX 1 |
|---|
| 3650 | #define mmPCTL0_SLICE0_CFG_DAGB_BUSY 0x08c6 |
|---|
| 3651 | #define mmPCTL0_SLICE0_CFG_DAGB_BUSY_BASE_IDX 1 |
|---|
| 3652 | #define mmPCTL0_SLICE0_CFG_DS_ALLOW 0x08c7 |
|---|
| 3653 | #define mmPCTL0_SLICE0_CFG_DS_ALLOW_BASE_IDX 1 |
|---|
| 3654 | #define mmPCTL0_SLICE0_CFG_DS_ALLOW_IB 0x08c8 |
|---|
| 3655 | #define mmPCTL0_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX 1 |
|---|
| 3656 | #define mmPCTL0_SLICE1_CFG_DAGB_BUSY 0x08c9 |
|---|
| 3657 | #define mmPCTL0_SLICE1_CFG_DAGB_BUSY_BASE_IDX 1 |
|---|
| 3658 | #define mmPCTL0_SLICE1_CFG_DS_ALLOW 0x08ca |
|---|
| 3659 | #define mmPCTL0_SLICE1_CFG_DS_ALLOW_BASE_IDX 1 |
|---|
| 3660 | #define mmPCTL0_SLICE1_CFG_DS_ALLOW_IB 0x08cb |
|---|
| 3661 | #define mmPCTL0_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX 1 |
|---|
| 3662 | #define mmPCTL0_SLICE2_CFG_DAGB_BUSY 0x08cc |
|---|
| 3663 | #define mmPCTL0_SLICE2_CFG_DAGB_BUSY_BASE_IDX 1 |
|---|
| 3664 | #define mmPCTL0_SLICE2_CFG_DS_ALLOW 0x08cd |
|---|
| 3665 | #define mmPCTL0_SLICE2_CFG_DS_ALLOW_BASE_IDX 1 |
|---|
| 3666 | #define mmPCTL0_SLICE2_CFG_DS_ALLOW_IB 0x08ce |
|---|
| 3667 | #define mmPCTL0_SLICE2_CFG_DS_ALLOW_IB_BASE_IDX 1 |
|---|
| 3668 | #define mmPCTL0_SLICE3_CFG_DAGB_BUSY 0x08cf |
|---|
| 3669 | #define mmPCTL0_SLICE3_CFG_DAGB_BUSY_BASE_IDX 1 |
|---|
| 3670 | #define mmPCTL0_SLICE3_CFG_DS_ALLOW 0x08d0 |
|---|
| 3671 | #define mmPCTL0_SLICE3_CFG_DS_ALLOW_BASE_IDX 1 |
|---|
| 3672 | #define mmPCTL0_SLICE3_CFG_DS_ALLOW_IB 0x08d1 |
|---|
| 3673 | #define mmPCTL0_SLICE3_CFG_DS_ALLOW_IB_BASE_IDX 1 |
|---|
| 3674 | #define mmPCTL0_SLICE4_CFG_DAGB_BUSY 0x08d2 |
|---|
| 3675 | #define mmPCTL0_SLICE4_CFG_DAGB_BUSY_BASE_IDX 1 |
|---|
| 3676 | #define mmPCTL0_SLICE4_CFG_DS_ALLOW 0x08d3 |
|---|
| 3677 | #define mmPCTL0_SLICE4_CFG_DS_ALLOW_BASE_IDX 1 |
|---|
| 3678 | #define mmPCTL0_SLICE4_CFG_DS_ALLOW_IB 0x08d4 |
|---|
| 3679 | #define mmPCTL0_SLICE4_CFG_DS_ALLOW_IB_BASE_IDX 1 |
|---|
| 3680 | #define mmPCTL0_UTCL2_MISC 0x08d5 |
|---|
| 3681 | #define mmPCTL0_UTCL2_MISC_BASE_IDX 1 |
|---|
| 3682 | #define mmPCTL0_SLICE0_MISC 0x08d6 |
|---|
| 3683 | #define mmPCTL0_SLICE0_MISC_BASE_IDX 1 |
|---|
| 3684 | #define mmPCTL0_SLICE1_MISC 0x08d7 |
|---|
| 3685 | #define mmPCTL0_SLICE1_MISC_BASE_IDX 1 |
|---|
| 3686 | #define mmPCTL0_SLICE2_MISC 0x08d8 |
|---|
| 3687 | #define mmPCTL0_SLICE2_MISC_BASE_IDX 1 |
|---|
| 3688 | #define mmPCTL0_SLICE3_MISC 0x08d9 |
|---|
| 3689 | #define mmPCTL0_SLICE3_MISC_BASE_IDX 1 |
|---|
| 3690 | #define mmPCTL0_SLICE4_MISC 0x08da |
|---|
| 3691 | #define mmPCTL0_SLICE4_MISC_BASE_IDX 1 |
|---|
| 3692 | #define mmPCTL0_UTCL2_RENG_EXECUTE 0x08db |
|---|
| 3693 | #define mmPCTL0_UTCL2_RENG_EXECUTE_BASE_IDX 1 |
|---|
| 3694 | #define mmPCTL0_SLICE0_RENG_EXECUTE 0x08dc |
|---|
| 3695 | #define mmPCTL0_SLICE0_RENG_EXECUTE_BASE_IDX 1 |
|---|
| 3696 | #define mmPCTL0_SLICE1_RENG_EXECUTE 0x08dd |
|---|
| 3697 | #define mmPCTL0_SLICE1_RENG_EXECUTE_BASE_IDX 1 |
|---|
| 3698 | #define mmPCTL0_SLICE2_RENG_EXECUTE 0x08de |
|---|
| 3699 | #define mmPCTL0_SLICE2_RENG_EXECUTE_BASE_IDX 1 |
|---|
| 3700 | #define mmPCTL0_SLICE3_RENG_EXECUTE 0x08df |
|---|
| 3701 | #define mmPCTL0_SLICE3_RENG_EXECUTE_BASE_IDX 1 |
|---|
| 3702 | #define mmPCTL0_SLICE4_RENG_EXECUTE 0x08e0 |
|---|
| 3703 | #define mmPCTL0_SLICE4_RENG_EXECUTE_BASE_IDX 1 |
|---|
| 3704 | #define mmPCTL0_UTCL2_RENG_RAM_INDEX 0x08e1 |
|---|
| 3705 | #define mmPCTL0_UTCL2_RENG_RAM_INDEX_BASE_IDX 1 |
|---|
| 3706 | #define mmPCTL0_UTCL2_RENG_RAM_DATA 0x08e2 |
|---|
| 3707 | #define mmPCTL0_UTCL2_RENG_RAM_DATA_BASE_IDX 1 |
|---|
| 3708 | #define mmPCTL0_SLICE0_RENG_RAM_INDEX 0x08e3 |
|---|
| 3709 | #define mmPCTL0_SLICE0_RENG_RAM_INDEX_BASE_IDX 1 |
|---|
| 3710 | #define mmPCTL0_SLICE0_RENG_RAM_DATA 0x08e4 |
|---|
| 3711 | #define mmPCTL0_SLICE0_RENG_RAM_DATA_BASE_IDX 1 |
|---|
| 3712 | #define mmPCTL0_SLICE1_RENG_RAM_INDEX 0x08e5 |
|---|
| 3713 | #define mmPCTL0_SLICE1_RENG_RAM_INDEX_BASE_IDX 1 |
|---|
| 3714 | #define mmPCTL0_SLICE1_RENG_RAM_DATA 0x08e6 |
|---|
| 3715 | #define mmPCTL0_SLICE1_RENG_RAM_DATA_BASE_IDX 1 |
|---|
| 3716 | #define mmPCTL0_SLICE2_RENG_RAM_INDEX 0x08e7 |
|---|
| 3717 | #define mmPCTL0_SLICE2_RENG_RAM_INDEX_BASE_IDX 1 |
|---|
| 3718 | #define mmPCTL0_SLICE2_RENG_RAM_DATA 0x08e8 |
|---|
| 3719 | #define mmPCTL0_SLICE2_RENG_RAM_DATA_BASE_IDX 1 |
|---|
| 3720 | #define mmPCTL0_SLICE3_RENG_RAM_INDEX 0x08e9 |
|---|
| 3721 | #define mmPCTL0_SLICE3_RENG_RAM_INDEX_BASE_IDX 1 |
|---|
| 3722 | #define mmPCTL0_SLICE3_RENG_RAM_DATA 0x08ea |
|---|
| 3723 | #define mmPCTL0_SLICE3_RENG_RAM_DATA_BASE_IDX 1 |
|---|
| 3724 | #define mmPCTL0_SLICE4_RENG_RAM_INDEX 0x08eb |
|---|
| 3725 | #define mmPCTL0_SLICE4_RENG_RAM_INDEX_BASE_IDX 1 |
|---|
| 3726 | #define mmPCTL0_SLICE4_RENG_RAM_DATA 0x08ec |
|---|
| 3727 | #define mmPCTL0_SLICE4_RENG_RAM_DATA_BASE_IDX 1 |
|---|
| 3728 | #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 0x08ed |
|---|
| 3729 | #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 |
|---|
| 3730 | #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 0x08ee |
|---|
| 3731 | #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 |
|---|
| 3732 | #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 0x08ef |
|---|
| 3733 | #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 |
|---|
| 3734 | #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 0x08f0 |
|---|
| 3735 | #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 |
|---|
| 3736 | #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 0x08f1 |
|---|
| 3737 | #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 |
|---|
| 3738 | #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x08f2 |
|---|
| 3739 | #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 |
|---|
| 3740 | #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x08f3 |
|---|
| 3741 | #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 |
|---|
| 3742 | #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 0x08f4 |
|---|
| 3743 | #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 |
|---|
| 3744 | #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 0x08f5 |
|---|
| 3745 | #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 |
|---|
| 3746 | #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 0x08f6 |
|---|
| 3747 | #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 |
|---|
| 3748 | #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 0x08f7 |
|---|
| 3749 | #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 |
|---|
| 3750 | #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 0x08f8 |
|---|
| 3751 | #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 |
|---|
| 3752 | #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 0x08f9 |
|---|
| 3753 | #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 |
|---|
| 3754 | #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x08fa |
|---|
| 3755 | #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 |
|---|
| 3756 | #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 0x08fb |
|---|
| 3757 | #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 |
|---|
| 3758 | #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 0x08fc |
|---|
| 3759 | #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 |
|---|
| 3760 | #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 0x08fd |
|---|
| 3761 | #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 |
|---|
| 3762 | #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 0x08fe |
|---|
| 3763 | #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 |
|---|
| 3764 | #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 0x08ff |
|---|
| 3765 | #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 |
|---|
| 3766 | #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 0x0900 |
|---|
| 3767 | #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 |
|---|
| 3768 | #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0901 |
|---|
| 3769 | #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 |
|---|
| 3770 | #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0 0x0902 |
|---|
| 3771 | #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 |
|---|
| 3772 | #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1 0x0903 |
|---|
| 3773 | #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 |
|---|
| 3774 | #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2 0x0904 |
|---|
| 3775 | #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 |
|---|
| 3776 | #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3 0x0905 |
|---|
| 3777 | #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 |
|---|
| 3778 | #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4 0x0906 |
|---|
| 3779 | #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 |
|---|
| 3780 | #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x0907 |
|---|
| 3781 | #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 |
|---|
| 3782 | #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0908 |
|---|
| 3783 | #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 |
|---|
| 3784 | #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0 0x0909 |
|---|
| 3785 | #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 |
|---|
| 3786 | #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1 0x090a |
|---|
| 3787 | #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 |
|---|
| 3788 | #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2 0x090b |
|---|
| 3789 | #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 |
|---|
| 3790 | #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3 0x090c |
|---|
| 3791 | #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 |
|---|
| 3792 | #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4 0x090d |
|---|
| 3793 | #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 |
|---|
| 3794 | #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0 0x090e |
|---|
| 3795 | #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 |
|---|
| 3796 | #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1 0x090f |
|---|
| 3797 | #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 |
|---|
| 3798 | #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0 0x0910 |
|---|
| 3799 | #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 |
|---|
| 3800 | #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1 0x0911 |
|---|
| 3801 | #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 |
|---|
| 3802 | #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2 0x0912 |
|---|
| 3803 | #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 |
|---|
| 3804 | #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3 0x0913 |
|---|
| 3805 | #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 |
|---|
| 3806 | #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4 0x0914 |
|---|
| 3807 | #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 |
|---|
| 3808 | #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0 0x0915 |
|---|
| 3809 | #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 |
|---|
| 3810 | #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0916 |
|---|
| 3811 | #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 |
|---|
| 3812 | |
|---|
| 3813 | |
|---|
| 3814 | // addressBlock: mmhub_l1tlb_vml1dec |
|---|
| 3815 | // base address: 0x6a500 |
|---|
| 3816 | #define mmVML1_0_MC_VM_MX_L1_TLB0_STATUS 0x0948 |
|---|
| 3817 | #define mmVML1_0_MC_VM_MX_L1_TLB0_STATUS_BASE_IDX 1 |
|---|
| 3818 | #define mmVML1_0_MC_VM_MX_L1_TLB1_STATUS 0x0949 |
|---|
| 3819 | #define mmVML1_0_MC_VM_MX_L1_TLB1_STATUS_BASE_IDX 1 |
|---|
| 3820 | #define mmVML1_0_MC_VM_MX_L1_TLB2_STATUS 0x094a |
|---|
| 3821 | #define mmVML1_0_MC_VM_MX_L1_TLB2_STATUS_BASE_IDX 1 |
|---|
| 3822 | #define mmVML1_0_MC_VM_MX_L1_TLB3_STATUS 0x094b |
|---|
| 3823 | #define mmVML1_0_MC_VM_MX_L1_TLB3_STATUS_BASE_IDX 1 |
|---|
| 3824 | #define mmVML1_0_MC_VM_MX_L1_TLB4_STATUS 0x094c |
|---|
| 3825 | #define mmVML1_0_MC_VM_MX_L1_TLB4_STATUS_BASE_IDX 1 |
|---|
| 3826 | #define mmVML1_0_MC_VM_MX_L1_TLB5_STATUS 0x094d |
|---|
| 3827 | #define mmVML1_0_MC_VM_MX_L1_TLB5_STATUS_BASE_IDX 1 |
|---|
| 3828 | #define mmVML1_0_MC_VM_MX_L1_TLB6_STATUS 0x094e |
|---|
| 3829 | #define mmVML1_0_MC_VM_MX_L1_TLB6_STATUS_BASE_IDX 1 |
|---|
| 3830 | #define mmVML1_0_MC_VM_MX_L1_TLB7_STATUS 0x094f |
|---|
| 3831 | #define mmVML1_0_MC_VM_MX_L1_TLB7_STATUS_BASE_IDX 1 |
|---|
| 3832 | |
|---|
| 3833 | |
|---|
| 3834 | // addressBlock: mmhub_l1tlb_vml1pldec |
|---|
| 3835 | // base address: 0x6a580 |
|---|
| 3836 | #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG 0x0960 |
|---|
| 3837 | #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 1 |
|---|
| 3838 | #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG 0x0961 |
|---|
| 3839 | #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 1 |
|---|
| 3840 | #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG 0x0962 |
|---|
| 3841 | #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 1 |
|---|
| 3842 | #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG 0x0963 |
|---|
| 3843 | #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 1 |
|---|
| 3844 | #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x0964 |
|---|
| 3845 | #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
|---|
| 3846 | |
|---|
| 3847 | |
|---|
| 3848 | // addressBlock: mmhub_l1tlb_vml1prdec |
|---|
| 3849 | // base address: 0x6a5c0 |
|---|
| 3850 | #define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO 0x0970 |
|---|
| 3851 | #define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 1 |
|---|
| 3852 | #define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI 0x0971 |
|---|
| 3853 | #define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 1 |
|---|
| 3854 | |
|---|
| 3855 | |
|---|
| 3856 | // addressBlock: mmhub_utcl2_atcl2dec |
|---|
| 3857 | // base address: 0x6a600 |
|---|
| 3858 | #define mmATCL2_0_ATC_L2_CNTL 0x0980 |
|---|
| 3859 | #define mmATCL2_0_ATC_L2_CNTL_BASE_IDX 1 |
|---|
| 3860 | #define mmATCL2_0_ATC_L2_CNTL2 0x0981 |
|---|
| 3861 | #define mmATCL2_0_ATC_L2_CNTL2_BASE_IDX 1 |
|---|
| 3862 | #define mmATCL2_0_ATC_L2_CACHE_DATA0 0x0984 |
|---|
| 3863 | #define mmATCL2_0_ATC_L2_CACHE_DATA0_BASE_IDX 1 |
|---|
| 3864 | #define mmATCL2_0_ATC_L2_CACHE_DATA1 0x0985 |
|---|
| 3865 | #define mmATCL2_0_ATC_L2_CACHE_DATA1_BASE_IDX 1 |
|---|
| 3866 | #define mmATCL2_0_ATC_L2_CACHE_DATA2 0x0986 |
|---|
| 3867 | #define mmATCL2_0_ATC_L2_CACHE_DATA2_BASE_IDX 1 |
|---|
| 3868 | #define mmATCL2_0_ATC_L2_CNTL3 0x0987 |
|---|
| 3869 | #define mmATCL2_0_ATC_L2_CNTL3_BASE_IDX 1 |
|---|
| 3870 | #define mmATCL2_0_ATC_L2_STATUS 0x0988 |
|---|
| 3871 | #define mmATCL2_0_ATC_L2_STATUS_BASE_IDX 1 |
|---|
| 3872 | #define mmATCL2_0_ATC_L2_STATUS2 0x0989 |
|---|
| 3873 | #define mmATCL2_0_ATC_L2_STATUS2_BASE_IDX 1 |
|---|
| 3874 | #define mmATCL2_0_ATC_L2_STATUS3 0x098a |
|---|
| 3875 | #define mmATCL2_0_ATC_L2_STATUS3_BASE_IDX 1 |
|---|
| 3876 | #define mmATCL2_0_ATC_L2_MISC_CG 0x098b |
|---|
| 3877 | #define mmATCL2_0_ATC_L2_MISC_CG_BASE_IDX 1 |
|---|
| 3878 | #define mmATCL2_0_ATC_L2_MEM_POWER_LS 0x098c |
|---|
| 3879 | #define mmATCL2_0_ATC_L2_MEM_POWER_LS_BASE_IDX 1 |
|---|
| 3880 | #define mmATCL2_0_ATC_L2_CGTT_CLK_CTRL 0x098d |
|---|
| 3881 | #define mmATCL2_0_ATC_L2_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 3882 | #define mmATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX 0x098e |
|---|
| 3883 | #define mmATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX 1 |
|---|
| 3884 | #define mmATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX 0x098f |
|---|
| 3885 | #define mmATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX 1 |
|---|
| 3886 | #define mmATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL 0x0990 |
|---|
| 3887 | #define mmATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX 1 |
|---|
| 3888 | #define mmATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL 0x0991 |
|---|
| 3889 | #define mmATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX 1 |
|---|
| 3890 | #define mmATCL2_0_ATC_L2_CNTL4 0x0992 |
|---|
| 3891 | #define mmATCL2_0_ATC_L2_CNTL4_BASE_IDX 1 |
|---|
| 3892 | #define mmATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES 0x0993 |
|---|
| 3893 | #define mmATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1 |
|---|
| 3894 | |
|---|
| 3895 | |
|---|
| 3896 | // addressBlock: mmhub_utcl2_vml2pfdec |
|---|
| 3897 | // base address: 0x6a700 |
|---|
| 3898 | #define mmVML2PF0_VM_L2_CNTL 0x09c0 |
|---|
| 3899 | #define mmVML2PF0_VM_L2_CNTL_BASE_IDX 1 |
|---|
| 3900 | #define mmVML2PF0_VM_L2_CNTL2 0x09c1 |
|---|
| 3901 | #define mmVML2PF0_VM_L2_CNTL2_BASE_IDX 1 |
|---|
| 3902 | #define mmVML2PF0_VM_L2_CNTL3 0x09c2 |
|---|
| 3903 | #define mmVML2PF0_VM_L2_CNTL3_BASE_IDX 1 |
|---|
| 3904 | #define mmVML2PF0_VM_L2_STATUS 0x09c3 |
|---|
| 3905 | #define mmVML2PF0_VM_L2_STATUS_BASE_IDX 1 |
|---|
| 3906 | #define mmVML2PF0_VM_DUMMY_PAGE_FAULT_CNTL 0x09c4 |
|---|
| 3907 | #define mmVML2PF0_VM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 1 |
|---|
| 3908 | #define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32 0x09c5 |
|---|
| 3909 | #define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 1 |
|---|
| 3910 | #define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32 0x09c6 |
|---|
| 3911 | #define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 1 |
|---|
| 3912 | #define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL 0x09c7 |
|---|
| 3913 | #define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 1 |
|---|
| 3914 | #define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2 0x09c8 |
|---|
| 3915 | #define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 1 |
|---|
| 3916 | #define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3 0x09c9 |
|---|
| 3917 | #define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 1 |
|---|
| 3918 | #define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4 0x09ca |
|---|
| 3919 | #define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 1 |
|---|
| 3920 | #define mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS 0x09cb |
|---|
| 3921 | #define mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 1 |
|---|
| 3922 | #define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32 0x09cc |
|---|
| 3923 | #define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 1 |
|---|
| 3924 | #define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32 0x09cd |
|---|
| 3925 | #define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 1 |
|---|
| 3926 | #define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x09ce |
|---|
| 3927 | #define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 1 |
|---|
| 3928 | #define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x09cf |
|---|
| 3929 | #define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 1 |
|---|
| 3930 | #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x09d1 |
|---|
| 3931 | #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 1 |
|---|
| 3932 | #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x09d2 |
|---|
| 3933 | #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 1 |
|---|
| 3934 | #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x09d3 |
|---|
| 3935 | #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 1 |
|---|
| 3936 | #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x09d4 |
|---|
| 3937 | #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 1 |
|---|
| 3938 | #define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x09d5 |
|---|
| 3939 | #define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 1 |
|---|
| 3940 | #define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x09d6 |
|---|
| 3941 | #define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 1 |
|---|
| 3942 | #define mmVML2PF0_VM_L2_CNTL4 0x09d7 |
|---|
| 3943 | #define mmVML2PF0_VM_L2_CNTL4_BASE_IDX 1 |
|---|
| 3944 | #define mmVML2PF0_VM_L2_MM_GROUP_RT_CLASSES 0x09d8 |
|---|
| 3945 | #define mmVML2PF0_VM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1 |
|---|
| 3946 | #define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID 0x09d9 |
|---|
| 3947 | #define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 1 |
|---|
| 3948 | #define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2 0x09da |
|---|
| 3949 | #define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 1 |
|---|
| 3950 | #define mmVML2PF0_VM_L2_CACHE_PARITY_CNTL 0x09db |
|---|
| 3951 | #define mmVML2PF0_VM_L2_CACHE_PARITY_CNTL_BASE_IDX 1 |
|---|
| 3952 | #define mmVML2PF0_VM_L2_CGTT_CLK_CTRL 0x09de |
|---|
| 3953 | #define mmVML2PF0_VM_L2_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 3954 | |
|---|
| 3955 | |
|---|
| 3956 | // addressBlock: mmhub_utcl2_vml2vcdec |
|---|
| 3957 | // base address: 0x6a800 |
|---|
| 3958 | #define mmVML2VC0_VM_CONTEXT0_CNTL 0x0a00 |
|---|
| 3959 | #define mmVML2VC0_VM_CONTEXT0_CNTL_BASE_IDX 1 |
|---|
| 3960 | #define mmVML2VC0_VM_CONTEXT1_CNTL 0x0a01 |
|---|
| 3961 | #define mmVML2VC0_VM_CONTEXT1_CNTL_BASE_IDX 1 |
|---|
| 3962 | #define mmVML2VC0_VM_CONTEXT2_CNTL 0x0a02 |
|---|
| 3963 | #define mmVML2VC0_VM_CONTEXT2_CNTL_BASE_IDX 1 |
|---|
| 3964 | #define mmVML2VC0_VM_CONTEXT3_CNTL 0x0a03 |
|---|
| 3965 | #define mmVML2VC0_VM_CONTEXT3_CNTL_BASE_IDX 1 |
|---|
| 3966 | #define mmVML2VC0_VM_CONTEXT4_CNTL 0x0a04 |
|---|
| 3967 | #define mmVML2VC0_VM_CONTEXT4_CNTL_BASE_IDX 1 |
|---|
| 3968 | #define mmVML2VC0_VM_CONTEXT5_CNTL 0x0a05 |
|---|
| 3969 | #define mmVML2VC0_VM_CONTEXT5_CNTL_BASE_IDX 1 |
|---|
| 3970 | #define mmVML2VC0_VM_CONTEXT6_CNTL 0x0a06 |
|---|
| 3971 | #define mmVML2VC0_VM_CONTEXT6_CNTL_BASE_IDX 1 |
|---|
| 3972 | #define mmVML2VC0_VM_CONTEXT7_CNTL 0x0a07 |
|---|
| 3973 | #define mmVML2VC0_VM_CONTEXT7_CNTL_BASE_IDX 1 |
|---|
| 3974 | #define mmVML2VC0_VM_CONTEXT8_CNTL 0x0a08 |
|---|
| 3975 | #define mmVML2VC0_VM_CONTEXT8_CNTL_BASE_IDX 1 |
|---|
| 3976 | #define mmVML2VC0_VM_CONTEXT9_CNTL 0x0a09 |
|---|
| 3977 | #define mmVML2VC0_VM_CONTEXT9_CNTL_BASE_IDX 1 |
|---|
| 3978 | #define mmVML2VC0_VM_CONTEXT10_CNTL 0x0a0a |
|---|
| 3979 | #define mmVML2VC0_VM_CONTEXT10_CNTL_BASE_IDX 1 |
|---|
| 3980 | #define mmVML2VC0_VM_CONTEXT11_CNTL 0x0a0b |
|---|
| 3981 | #define mmVML2VC0_VM_CONTEXT11_CNTL_BASE_IDX 1 |
|---|
| 3982 | #define mmVML2VC0_VM_CONTEXT12_CNTL 0x0a0c |
|---|
| 3983 | #define mmVML2VC0_VM_CONTEXT12_CNTL_BASE_IDX 1 |
|---|
| 3984 | #define mmVML2VC0_VM_CONTEXT13_CNTL 0x0a0d |
|---|
| 3985 | #define mmVML2VC0_VM_CONTEXT13_CNTL_BASE_IDX 1 |
|---|
| 3986 | #define mmVML2VC0_VM_CONTEXT14_CNTL 0x0a0e |
|---|
| 3987 | #define mmVML2VC0_VM_CONTEXT14_CNTL_BASE_IDX 1 |
|---|
| 3988 | #define mmVML2VC0_VM_CONTEXT15_CNTL 0x0a0f |
|---|
| 3989 | #define mmVML2VC0_VM_CONTEXT15_CNTL_BASE_IDX 1 |
|---|
| 3990 | #define mmVML2VC0_VM_CONTEXTS_DISABLE 0x0a10 |
|---|
| 3991 | #define mmVML2VC0_VM_CONTEXTS_DISABLE_BASE_IDX 1 |
|---|
| 3992 | #define mmVML2VC0_VM_INVALIDATE_ENG0_SEM 0x0a11 |
|---|
| 3993 | #define mmVML2VC0_VM_INVALIDATE_ENG0_SEM_BASE_IDX 1 |
|---|
| 3994 | #define mmVML2VC0_VM_INVALIDATE_ENG1_SEM 0x0a12 |
|---|
| 3995 | #define mmVML2VC0_VM_INVALIDATE_ENG1_SEM_BASE_IDX 1 |
|---|
| 3996 | #define mmVML2VC0_VM_INVALIDATE_ENG2_SEM 0x0a13 |
|---|
| 3997 | #define mmVML2VC0_VM_INVALIDATE_ENG2_SEM_BASE_IDX 1 |
|---|
| 3998 | #define mmVML2VC0_VM_INVALIDATE_ENG3_SEM 0x0a14 |
|---|
| 3999 | #define mmVML2VC0_VM_INVALIDATE_ENG3_SEM_BASE_IDX 1 |
|---|
| 4000 | #define mmVML2VC0_VM_INVALIDATE_ENG4_SEM 0x0a15 |
|---|
| 4001 | #define mmVML2VC0_VM_INVALIDATE_ENG4_SEM_BASE_IDX 1 |
|---|
| 4002 | #define mmVML2VC0_VM_INVALIDATE_ENG5_SEM 0x0a16 |
|---|
| 4003 | #define mmVML2VC0_VM_INVALIDATE_ENG5_SEM_BASE_IDX 1 |
|---|
| 4004 | #define mmVML2VC0_VM_INVALIDATE_ENG6_SEM 0x0a17 |
|---|
| 4005 | #define mmVML2VC0_VM_INVALIDATE_ENG6_SEM_BASE_IDX 1 |
|---|
| 4006 | #define mmVML2VC0_VM_INVALIDATE_ENG7_SEM 0x0a18 |
|---|
| 4007 | #define mmVML2VC0_VM_INVALIDATE_ENG7_SEM_BASE_IDX 1 |
|---|
| 4008 | #define mmVML2VC0_VM_INVALIDATE_ENG8_SEM 0x0a19 |
|---|
| 4009 | #define mmVML2VC0_VM_INVALIDATE_ENG8_SEM_BASE_IDX 1 |
|---|
| 4010 | #define mmVML2VC0_VM_INVALIDATE_ENG9_SEM 0x0a1a |
|---|
| 4011 | #define mmVML2VC0_VM_INVALIDATE_ENG9_SEM_BASE_IDX 1 |
|---|
| 4012 | #define mmVML2VC0_VM_INVALIDATE_ENG10_SEM 0x0a1b |
|---|
| 4013 | #define mmVML2VC0_VM_INVALIDATE_ENG10_SEM_BASE_IDX 1 |
|---|
| 4014 | #define mmVML2VC0_VM_INVALIDATE_ENG11_SEM 0x0a1c |
|---|
| 4015 | #define mmVML2VC0_VM_INVALIDATE_ENG11_SEM_BASE_IDX 1 |
|---|
| 4016 | #define mmVML2VC0_VM_INVALIDATE_ENG12_SEM 0x0a1d |
|---|
| 4017 | #define mmVML2VC0_VM_INVALIDATE_ENG12_SEM_BASE_IDX 1 |
|---|
| 4018 | #define mmVML2VC0_VM_INVALIDATE_ENG13_SEM 0x0a1e |
|---|
| 4019 | #define mmVML2VC0_VM_INVALIDATE_ENG13_SEM_BASE_IDX 1 |
|---|
| 4020 | #define mmVML2VC0_VM_INVALIDATE_ENG14_SEM 0x0a1f |
|---|
| 4021 | #define mmVML2VC0_VM_INVALIDATE_ENG14_SEM_BASE_IDX 1 |
|---|
| 4022 | #define mmVML2VC0_VM_INVALIDATE_ENG15_SEM 0x0a20 |
|---|
| 4023 | #define mmVML2VC0_VM_INVALIDATE_ENG15_SEM_BASE_IDX 1 |
|---|
| 4024 | #define mmVML2VC0_VM_INVALIDATE_ENG16_SEM 0x0a21 |
|---|
| 4025 | #define mmVML2VC0_VM_INVALIDATE_ENG16_SEM_BASE_IDX 1 |
|---|
| 4026 | #define mmVML2VC0_VM_INVALIDATE_ENG17_SEM 0x0a22 |
|---|
| 4027 | #define mmVML2VC0_VM_INVALIDATE_ENG17_SEM_BASE_IDX 1 |
|---|
| 4028 | #define mmVML2VC0_VM_INVALIDATE_ENG0_REQ 0x0a23 |
|---|
| 4029 | #define mmVML2VC0_VM_INVALIDATE_ENG0_REQ_BASE_IDX 1 |
|---|
| 4030 | #define mmVML2VC0_VM_INVALIDATE_ENG1_REQ 0x0a24 |
|---|
| 4031 | #define mmVML2VC0_VM_INVALIDATE_ENG1_REQ_BASE_IDX 1 |
|---|
| 4032 | #define mmVML2VC0_VM_INVALIDATE_ENG2_REQ 0x0a25 |
|---|
| 4033 | #define mmVML2VC0_VM_INVALIDATE_ENG2_REQ_BASE_IDX 1 |
|---|
| 4034 | #define mmVML2VC0_VM_INVALIDATE_ENG3_REQ 0x0a26 |
|---|
| 4035 | #define mmVML2VC0_VM_INVALIDATE_ENG3_REQ_BASE_IDX 1 |
|---|
| 4036 | #define mmVML2VC0_VM_INVALIDATE_ENG4_REQ 0x0a27 |
|---|
| 4037 | #define mmVML2VC0_VM_INVALIDATE_ENG4_REQ_BASE_IDX 1 |
|---|
| 4038 | #define mmVML2VC0_VM_INVALIDATE_ENG5_REQ 0x0a28 |
|---|
| 4039 | #define mmVML2VC0_VM_INVALIDATE_ENG5_REQ_BASE_IDX 1 |
|---|
| 4040 | #define mmVML2VC0_VM_INVALIDATE_ENG6_REQ 0x0a29 |
|---|
| 4041 | #define mmVML2VC0_VM_INVALIDATE_ENG6_REQ_BASE_IDX 1 |
|---|
| 4042 | #define mmVML2VC0_VM_INVALIDATE_ENG7_REQ 0x0a2a |
|---|
| 4043 | #define mmVML2VC0_VM_INVALIDATE_ENG7_REQ_BASE_IDX 1 |
|---|
| 4044 | #define mmVML2VC0_VM_INVALIDATE_ENG8_REQ 0x0a2b |
|---|
| 4045 | #define mmVML2VC0_VM_INVALIDATE_ENG8_REQ_BASE_IDX 1 |
|---|
| 4046 | #define mmVML2VC0_VM_INVALIDATE_ENG9_REQ 0x0a2c |
|---|
| 4047 | #define mmVML2VC0_VM_INVALIDATE_ENG9_REQ_BASE_IDX 1 |
|---|
| 4048 | #define mmVML2VC0_VM_INVALIDATE_ENG10_REQ 0x0a2d |
|---|
| 4049 | #define mmVML2VC0_VM_INVALIDATE_ENG10_REQ_BASE_IDX 1 |
|---|
| 4050 | #define mmVML2VC0_VM_INVALIDATE_ENG11_REQ 0x0a2e |
|---|
| 4051 | #define mmVML2VC0_VM_INVALIDATE_ENG11_REQ_BASE_IDX 1 |
|---|
| 4052 | #define mmVML2VC0_VM_INVALIDATE_ENG12_REQ 0x0a2f |
|---|
| 4053 | #define mmVML2VC0_VM_INVALIDATE_ENG12_REQ_BASE_IDX 1 |
|---|
| 4054 | #define mmVML2VC0_VM_INVALIDATE_ENG13_REQ 0x0a30 |
|---|
| 4055 | #define mmVML2VC0_VM_INVALIDATE_ENG13_REQ_BASE_IDX 1 |
|---|
| 4056 | #define mmVML2VC0_VM_INVALIDATE_ENG14_REQ 0x0a31 |
|---|
| 4057 | #define mmVML2VC0_VM_INVALIDATE_ENG14_REQ_BASE_IDX 1 |
|---|
| 4058 | #define mmVML2VC0_VM_INVALIDATE_ENG15_REQ 0x0a32 |
|---|
| 4059 | #define mmVML2VC0_VM_INVALIDATE_ENG15_REQ_BASE_IDX 1 |
|---|
| 4060 | #define mmVML2VC0_VM_INVALIDATE_ENG16_REQ 0x0a33 |
|---|
| 4061 | #define mmVML2VC0_VM_INVALIDATE_ENG16_REQ_BASE_IDX 1 |
|---|
| 4062 | #define mmVML2VC0_VM_INVALIDATE_ENG17_REQ 0x0a34 |
|---|
| 4063 | #define mmVML2VC0_VM_INVALIDATE_ENG17_REQ_BASE_IDX 1 |
|---|
| 4064 | #define mmVML2VC0_VM_INVALIDATE_ENG0_ACK 0x0a35 |
|---|
| 4065 | #define mmVML2VC0_VM_INVALIDATE_ENG0_ACK_BASE_IDX 1 |
|---|
| 4066 | #define mmVML2VC0_VM_INVALIDATE_ENG1_ACK 0x0a36 |
|---|
| 4067 | #define mmVML2VC0_VM_INVALIDATE_ENG1_ACK_BASE_IDX 1 |
|---|
| 4068 | #define mmVML2VC0_VM_INVALIDATE_ENG2_ACK 0x0a37 |
|---|
| 4069 | #define mmVML2VC0_VM_INVALIDATE_ENG2_ACK_BASE_IDX 1 |
|---|
| 4070 | #define mmVML2VC0_VM_INVALIDATE_ENG3_ACK 0x0a38 |
|---|
| 4071 | #define mmVML2VC0_VM_INVALIDATE_ENG3_ACK_BASE_IDX 1 |
|---|
| 4072 | #define mmVML2VC0_VM_INVALIDATE_ENG4_ACK 0x0a39 |
|---|
| 4073 | #define mmVML2VC0_VM_INVALIDATE_ENG4_ACK_BASE_IDX 1 |
|---|
| 4074 | #define mmVML2VC0_VM_INVALIDATE_ENG5_ACK 0x0a3a |
|---|
| 4075 | #define mmVML2VC0_VM_INVALIDATE_ENG5_ACK_BASE_IDX 1 |
|---|
| 4076 | #define mmVML2VC0_VM_INVALIDATE_ENG6_ACK 0x0a3b |
|---|
| 4077 | #define mmVML2VC0_VM_INVALIDATE_ENG6_ACK_BASE_IDX 1 |
|---|
| 4078 | #define mmVML2VC0_VM_INVALIDATE_ENG7_ACK 0x0a3c |
|---|
| 4079 | #define mmVML2VC0_VM_INVALIDATE_ENG7_ACK_BASE_IDX 1 |
|---|
| 4080 | #define mmVML2VC0_VM_INVALIDATE_ENG8_ACK 0x0a3d |
|---|
| 4081 | #define mmVML2VC0_VM_INVALIDATE_ENG8_ACK_BASE_IDX 1 |
|---|
| 4082 | #define mmVML2VC0_VM_INVALIDATE_ENG9_ACK 0x0a3e |
|---|
| 4083 | #define mmVML2VC0_VM_INVALIDATE_ENG9_ACK_BASE_IDX 1 |
|---|
| 4084 | #define mmVML2VC0_VM_INVALIDATE_ENG10_ACK 0x0a3f |
|---|
| 4085 | #define mmVML2VC0_VM_INVALIDATE_ENG10_ACK_BASE_IDX 1 |
|---|
| 4086 | #define mmVML2VC0_VM_INVALIDATE_ENG11_ACK 0x0a40 |
|---|
| 4087 | #define mmVML2VC0_VM_INVALIDATE_ENG11_ACK_BASE_IDX 1 |
|---|
| 4088 | #define mmVML2VC0_VM_INVALIDATE_ENG12_ACK 0x0a41 |
|---|
| 4089 | #define mmVML2VC0_VM_INVALIDATE_ENG12_ACK_BASE_IDX 1 |
|---|
| 4090 | #define mmVML2VC0_VM_INVALIDATE_ENG13_ACK 0x0a42 |
|---|
| 4091 | #define mmVML2VC0_VM_INVALIDATE_ENG13_ACK_BASE_IDX 1 |
|---|
| 4092 | #define mmVML2VC0_VM_INVALIDATE_ENG14_ACK 0x0a43 |
|---|
| 4093 | #define mmVML2VC0_VM_INVALIDATE_ENG14_ACK_BASE_IDX 1 |
|---|
| 4094 | #define mmVML2VC0_VM_INVALIDATE_ENG15_ACK 0x0a44 |
|---|
| 4095 | #define mmVML2VC0_VM_INVALIDATE_ENG15_ACK_BASE_IDX 1 |
|---|
| 4096 | #define mmVML2VC0_VM_INVALIDATE_ENG16_ACK 0x0a45 |
|---|
| 4097 | #define mmVML2VC0_VM_INVALIDATE_ENG16_ACK_BASE_IDX 1 |
|---|
| 4098 | #define mmVML2VC0_VM_INVALIDATE_ENG17_ACK 0x0a46 |
|---|
| 4099 | #define mmVML2VC0_VM_INVALIDATE_ENG17_ACK_BASE_IDX 1 |
|---|
| 4100 | #define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0a47 |
|---|
| 4101 | #define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 4102 | #define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0a48 |
|---|
| 4103 | #define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 4104 | #define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0a49 |
|---|
| 4105 | #define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 4106 | #define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x0a4a |
|---|
| 4107 | #define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 4108 | #define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x0a4b |
|---|
| 4109 | #define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 4110 | #define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x0a4c |
|---|
| 4111 | #define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 4112 | #define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x0a4d |
|---|
| 4113 | #define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 4114 | #define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x0a4e |
|---|
| 4115 | #define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 4116 | #define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x0a4f |
|---|
| 4117 | #define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 4118 | #define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0a50 |
|---|
| 4119 | #define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 4120 | #define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0a51 |
|---|
| 4121 | #define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 4122 | #define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0a52 |
|---|
| 4123 | #define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 4124 | #define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0a53 |
|---|
| 4125 | #define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 4126 | #define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0a54 |
|---|
| 4127 | #define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 4128 | #define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0a55 |
|---|
| 4129 | #define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 4130 | #define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0a56 |
|---|
| 4131 | #define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 4132 | #define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0a57 |
|---|
| 4133 | #define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 4134 | #define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0a58 |
|---|
| 4135 | #define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 4136 | #define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0a59 |
|---|
| 4137 | #define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 4138 | #define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x0a5a |
|---|
| 4139 | #define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 4140 | #define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x0a5b |
|---|
| 4141 | #define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 4142 | #define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x0a5c |
|---|
| 4143 | #define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 4144 | #define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x0a5d |
|---|
| 4145 | #define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 4146 | #define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x0a5e |
|---|
| 4147 | #define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 4148 | #define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x0a5f |
|---|
| 4149 | #define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 4150 | #define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x0a60 |
|---|
| 4151 | #define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 4152 | #define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x0a61 |
|---|
| 4153 | #define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 4154 | #define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x0a62 |
|---|
| 4155 | #define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 4156 | #define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x0a63 |
|---|
| 4157 | #define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 4158 | #define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x0a64 |
|---|
| 4159 | #define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 4160 | #define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x0a65 |
|---|
| 4161 | #define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 4162 | #define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x0a66 |
|---|
| 4163 | #define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 4164 | #define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0a67 |
|---|
| 4165 | #define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 4166 | #define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0a68 |
|---|
| 4167 | #define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 4168 | #define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x0a69 |
|---|
| 4169 | #define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 4170 | #define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x0a6a |
|---|
| 4171 | #define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 4172 | #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x0a6b |
|---|
| 4173 | #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 4174 | #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x0a6c |
|---|
| 4175 | #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 4176 | #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0a6d |
|---|
| 4177 | #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 4178 | #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0a6e |
|---|
| 4179 | #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 4180 | #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0a6f |
|---|
| 4181 | #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 4182 | #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0a70 |
|---|
| 4183 | #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 4184 | #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0a71 |
|---|
| 4185 | #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 4186 | #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x0a72 |
|---|
| 4187 | #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 4188 | #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0a73 |
|---|
| 4189 | #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 4190 | #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0a74 |
|---|
| 4191 | #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 4192 | #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x0a75 |
|---|
| 4193 | #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 4194 | #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x0a76 |
|---|
| 4195 | #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 4196 | #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0a77 |
|---|
| 4197 | #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 4198 | #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0a78 |
|---|
| 4199 | #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 4200 | #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x0a79 |
|---|
| 4201 | #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 4202 | #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x0a7a |
|---|
| 4203 | #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 4204 | #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0a7b |
|---|
| 4205 | #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 4206 | #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0a7c |
|---|
| 4207 | #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 4208 | #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x0a7d |
|---|
| 4209 | #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 4210 | #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0a7e |
|---|
| 4211 | #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 4212 | #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x0a7f |
|---|
| 4213 | #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 4214 | #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0a80 |
|---|
| 4215 | #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 4216 | #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0a81 |
|---|
| 4217 | #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 4218 | #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0a82 |
|---|
| 4219 | #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 4220 | #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0a83 |
|---|
| 4221 | #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 4222 | #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0a84 |
|---|
| 4223 | #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 4224 | #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0a85 |
|---|
| 4225 | #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 4226 | #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0a86 |
|---|
| 4227 | #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 4228 | #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0a87 |
|---|
| 4229 | #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 4230 | #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0a88 |
|---|
| 4231 | #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 4232 | #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0a89 |
|---|
| 4233 | #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 4234 | #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x0a8a |
|---|
| 4235 | #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 4236 | #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x0a8b |
|---|
| 4237 | #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 4238 | #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x0a8c |
|---|
| 4239 | #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 4240 | #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0a8d |
|---|
| 4241 | #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 4242 | #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0a8e |
|---|
| 4243 | #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 4244 | #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x0a8f |
|---|
| 4245 | #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 4246 | #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0a90 |
|---|
| 4247 | #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 4248 | #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0a91 |
|---|
| 4249 | #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 4250 | #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0a92 |
|---|
| 4251 | #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 4252 | #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0a93 |
|---|
| 4253 | #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 4254 | #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0a94 |
|---|
| 4255 | #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 4256 | #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0a95 |
|---|
| 4257 | #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 4258 | #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0a96 |
|---|
| 4259 | #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 4260 | #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0a97 |
|---|
| 4261 | #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 4262 | #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0a98 |
|---|
| 4263 | #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 4264 | #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0a99 |
|---|
| 4265 | #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 4266 | #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x0a9a |
|---|
| 4267 | #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 4268 | #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0a9b |
|---|
| 4269 | #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 4270 | #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0a9c |
|---|
| 4271 | #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 4272 | #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x0a9d |
|---|
| 4273 | #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 4274 | #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x0a9e |
|---|
| 4275 | #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 4276 | #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x0a9f |
|---|
| 4277 | #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 4278 | #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0aa0 |
|---|
| 4279 | #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 4280 | #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0aa1 |
|---|
| 4281 | #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 4282 | #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0aa2 |
|---|
| 4283 | #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 4284 | #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0aa3 |
|---|
| 4285 | #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 4286 | #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0aa4 |
|---|
| 4287 | #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 4288 | #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0aa5 |
|---|
| 4289 | #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 4290 | #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0aa6 |
|---|
| 4291 | #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 4292 | #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0aa7 |
|---|
| 4293 | #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 4294 | #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0aa8 |
|---|
| 4295 | #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 4296 | #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0aa9 |
|---|
| 4297 | #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 4298 | #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x0aaa |
|---|
| 4299 | #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 4300 | #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x0aab |
|---|
| 4301 | #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 4302 | #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x0aac |
|---|
| 4303 | #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 4304 | #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0aad |
|---|
| 4305 | #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 4306 | #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0aae |
|---|
| 4307 | #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 4308 | #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x0aaf |
|---|
| 4309 | #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 4310 | #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0ab0 |
|---|
| 4311 | #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 4312 | #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0ab1 |
|---|
| 4313 | #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 4314 | #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0ab2 |
|---|
| 4315 | #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 4316 | #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0ab3 |
|---|
| 4317 | #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 4318 | #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0ab4 |
|---|
| 4319 | #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 4320 | #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0ab5 |
|---|
| 4321 | #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 4322 | #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0ab6 |
|---|
| 4323 | #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 4324 | #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0ab7 |
|---|
| 4325 | #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 4326 | #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0ab8 |
|---|
| 4327 | #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 4328 | #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0ab9 |
|---|
| 4329 | #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 4330 | #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x0aba |
|---|
| 4331 | #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 4332 | #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0abb |
|---|
| 4333 | #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 4334 | #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0abc |
|---|
| 4335 | #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 4336 | #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x0abd |
|---|
| 4337 | #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 4338 | #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x0abe |
|---|
| 4339 | #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 4340 | #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x0abf |
|---|
| 4341 | #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 4342 | #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0ac0 |
|---|
| 4343 | #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 4344 | #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0ac1 |
|---|
| 4345 | #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 4346 | #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0ac2 |
|---|
| 4347 | #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 4348 | #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0ac3 |
|---|
| 4349 | #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 4350 | #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0ac4 |
|---|
| 4351 | #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 4352 | #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0ac5 |
|---|
| 4353 | #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 4354 | #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0ac6 |
|---|
| 4355 | #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 4356 | #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0ac7 |
|---|
| 4357 | #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 4358 | #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0ac8 |
|---|
| 4359 | #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 4360 | #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0ac9 |
|---|
| 4361 | #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 4362 | #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x0aca |
|---|
| 4363 | #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 4364 | |
|---|
| 4365 | |
|---|
| 4366 | // addressBlock: mmhub_utcl2_vmsharedpfdec |
|---|
| 4367 | // base address: 0x6ab90 |
|---|
| 4368 | #define mmVMSHAREDPF0_MC_VM_NB_MMIOBASE 0x0ae4 |
|---|
| 4369 | #define mmVMSHAREDPF0_MC_VM_NB_MMIOBASE_BASE_IDX 1 |
|---|
| 4370 | #define mmVMSHAREDPF0_MC_VM_NB_MMIOLIMIT 0x0ae5 |
|---|
| 4371 | #define mmVMSHAREDPF0_MC_VM_NB_MMIOLIMIT_BASE_IDX 1 |
|---|
| 4372 | #define mmVMSHAREDPF0_MC_VM_NB_PCI_CTRL 0x0ae6 |
|---|
| 4373 | #define mmVMSHAREDPF0_MC_VM_NB_PCI_CTRL_BASE_IDX 1 |
|---|
| 4374 | #define mmVMSHAREDPF0_MC_VM_NB_PCI_ARB 0x0ae7 |
|---|
| 4375 | #define mmVMSHAREDPF0_MC_VM_NB_PCI_ARB_BASE_IDX 1 |
|---|
| 4376 | #define mmVMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1 0x0ae8 |
|---|
| 4377 | #define mmVMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 1 |
|---|
| 4378 | #define mmVMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2 0x0ae9 |
|---|
| 4379 | #define mmVMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 1 |
|---|
| 4380 | #define mmVMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2 0x0aea |
|---|
| 4381 | #define mmVMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 1 |
|---|
| 4382 | #define mmVMSHAREDPF0_MC_VM_FB_OFFSET 0x0aeb |
|---|
| 4383 | #define mmVMSHAREDPF0_MC_VM_FB_OFFSET_BASE_IDX 1 |
|---|
| 4384 | #define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0aec |
|---|
| 4385 | #define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 1 |
|---|
| 4386 | #define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0aed |
|---|
| 4387 | #define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 1 |
|---|
| 4388 | #define mmVMSHAREDPF0_MC_VM_STEERING 0x0aee |
|---|
| 4389 | #define mmVMSHAREDPF0_MC_VM_STEERING_BASE_IDX 1 |
|---|
| 4390 | #define mmVMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ 0x0aef |
|---|
| 4391 | #define mmVMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ_BASE_IDX 1 |
|---|
| 4392 | #define mmVMSHAREDPF0_MC_MEM_POWER_LS 0x0af0 |
|---|
| 4393 | #define mmVMSHAREDPF0_MC_MEM_POWER_LS_BASE_IDX 1 |
|---|
| 4394 | #define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START 0x0af1 |
|---|
| 4395 | #define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 1 |
|---|
| 4396 | #define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END 0x0af2 |
|---|
| 4397 | #define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 1 |
|---|
| 4398 | #define mmVMSHAREDPF0_MC_VM_APT_CNTL 0x0af3 |
|---|
| 4399 | #define mmVMSHAREDPF0_MC_VM_APT_CNTL_BASE_IDX 1 |
|---|
| 4400 | #define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START 0x0af4 |
|---|
| 4401 | #define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 1 |
|---|
| 4402 | #define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END 0x0af5 |
|---|
| 4403 | #define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 1 |
|---|
| 4404 | #define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0af6 |
|---|
| 4405 | #define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 1 |
|---|
| 4406 | #define mmVMSHAREDPF0_MC_VM_XGMI_LFB_CNTL 0x0af7 |
|---|
| 4407 | #define mmVMSHAREDPF0_MC_VM_XGMI_LFB_CNTL_BASE_IDX 1 |
|---|
| 4408 | #define mmVMSHAREDPF0_MC_VM_XGMI_LFB_SIZE 0x0af8 |
|---|
| 4409 | #define mmVMSHAREDPF0_MC_VM_XGMI_LFB_SIZE_BASE_IDX 1 |
|---|
| 4410 | #define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL 0x0af9 |
|---|
| 4411 | #define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX 1 |
|---|
| 4412 | #define mmMC_VM_XGMI_LFB_CNTL 0x0823 |
|---|
| 4413 | #define mmMC_VM_XGMI_LFB_CNTL_BASE_IDX 0 |
|---|
| 4414 | #define mmMC_VM_XGMI_LFB_SIZE 0x0824 |
|---|
| 4415 | #define mmMC_VM_XGMI_LFB_SIZE_BASE_IDX 0 |
|---|
| 4416 | |
|---|
| 4417 | |
|---|
| 4418 | // addressBlock: mmhub_utcl2_vmsharedvcdec |
|---|
| 4419 | // base address: 0x6ac00 |
|---|
| 4420 | #define mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE 0x0b00 |
|---|
| 4421 | #define mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE_BASE_IDX 1 |
|---|
| 4422 | #define mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP 0x0b01 |
|---|
| 4423 | #define mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP_BASE_IDX 1 |
|---|
| 4424 | #define mmVMSHAREDVC0_MC_VM_AGP_TOP 0x0b02 |
|---|
| 4425 | #define mmVMSHAREDVC0_MC_VM_AGP_TOP_BASE_IDX 1 |
|---|
| 4426 | #define mmVMSHAREDVC0_MC_VM_AGP_BOT 0x0b03 |
|---|
| 4427 | #define mmVMSHAREDVC0_MC_VM_AGP_BOT_BASE_IDX 1 |
|---|
| 4428 | #define mmVMSHAREDVC0_MC_VM_AGP_BASE 0x0b04 |
|---|
| 4429 | #define mmVMSHAREDVC0_MC_VM_AGP_BASE_BASE_IDX 1 |
|---|
| 4430 | #define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0b05 |
|---|
| 4431 | #define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 1 |
|---|
| 4432 | #define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0b06 |
|---|
| 4433 | #define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 1 |
|---|
| 4434 | #define mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL 0x0b07 |
|---|
| 4435 | #define mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL_BASE_IDX 1 |
|---|
| 4436 | |
|---|
| 4437 | |
|---|
| 4438 | // addressBlock: mmhub_utcl2_vmsharedhvdec |
|---|
| 4439 | // base address: 0x6ac80 |
|---|
| 4440 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0 0x0b20 |
|---|
| 4441 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1 |
|---|
| 4442 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1 0x0b21 |
|---|
| 4443 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1 |
|---|
| 4444 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2 0x0b22 |
|---|
| 4445 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1 |
|---|
| 4446 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3 0x0b23 |
|---|
| 4447 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1 |
|---|
| 4448 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4 0x0b24 |
|---|
| 4449 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1 |
|---|
| 4450 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5 0x0b25 |
|---|
| 4451 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1 |
|---|
| 4452 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6 0x0b26 |
|---|
| 4453 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1 |
|---|
| 4454 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7 0x0b27 |
|---|
| 4455 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1 |
|---|
| 4456 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8 0x0b28 |
|---|
| 4457 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1 |
|---|
| 4458 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9 0x0b29 |
|---|
| 4459 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1 |
|---|
| 4460 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10 0x0b2a |
|---|
| 4461 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1 |
|---|
| 4462 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11 0x0b2b |
|---|
| 4463 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1 |
|---|
| 4464 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12 0x0b2c |
|---|
| 4465 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1 |
|---|
| 4466 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13 0x0b2d |
|---|
| 4467 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1 |
|---|
| 4468 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14 0x0b2e |
|---|
| 4469 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1 |
|---|
| 4470 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15 0x0b2f |
|---|
| 4471 | #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1 |
|---|
| 4472 | #define mmVMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1 0x0b30 |
|---|
| 4473 | #define mmVMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1_BASE_IDX 1 |
|---|
| 4474 | #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_0 0x0b31 |
|---|
| 4475 | #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_0_BASE_IDX 1 |
|---|
| 4476 | #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_1 0x0b32 |
|---|
| 4477 | #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_1_BASE_IDX 1 |
|---|
| 4478 | #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_2 0x0b33 |
|---|
| 4479 | #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_2_BASE_IDX 1 |
|---|
| 4480 | #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_3 0x0b34 |
|---|
| 4481 | #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_3_BASE_IDX 1 |
|---|
| 4482 | #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_0 0x0b35 |
|---|
| 4483 | #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_0_BASE_IDX 1 |
|---|
| 4484 | #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_1 0x0b36 |
|---|
| 4485 | #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_1_BASE_IDX 1 |
|---|
| 4486 | #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_2 0x0b37 |
|---|
| 4487 | #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_2_BASE_IDX 1 |
|---|
| 4488 | #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_3 0x0b38 |
|---|
| 4489 | #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_3_BASE_IDX 1 |
|---|
| 4490 | #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_0 0x0b39 |
|---|
| 4491 | #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_0_BASE_IDX 1 |
|---|
| 4492 | #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_1 0x0b3a |
|---|
| 4493 | #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_1_BASE_IDX 1 |
|---|
| 4494 | #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_2 0x0b3b |
|---|
| 4495 | #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_2_BASE_IDX 1 |
|---|
| 4496 | #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_3 0x0b3c |
|---|
| 4497 | #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_3_BASE_IDX 1 |
|---|
| 4498 | #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_0 0x0b3d |
|---|
| 4499 | #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_0_BASE_IDX 1 |
|---|
| 4500 | #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_1 0x0b3e |
|---|
| 4501 | #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_1_BASE_IDX 1 |
|---|
| 4502 | #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_2 0x0b3f |
|---|
| 4503 | #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_2_BASE_IDX 1 |
|---|
| 4504 | #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_3 0x0b40 |
|---|
| 4505 | #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_3_BASE_IDX 1 |
|---|
| 4506 | #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_0 0x0b41 |
|---|
| 4507 | #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_0_BASE_IDX 1 |
|---|
| 4508 | #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_1 0x0b42 |
|---|
| 4509 | #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_1_BASE_IDX 1 |
|---|
| 4510 | #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_2 0x0b43 |
|---|
| 4511 | #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_2_BASE_IDX 1 |
|---|
| 4512 | #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_3 0x0b44 |
|---|
| 4513 | #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_3_BASE_IDX 1 |
|---|
| 4514 | #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_0 0x0b45 |
|---|
| 4515 | #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_0_BASE_IDX 1 |
|---|
| 4516 | #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_1 0x0b46 |
|---|
| 4517 | #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_1_BASE_IDX 1 |
|---|
| 4518 | #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_2 0x0b47 |
|---|
| 4519 | #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_2_BASE_IDX 1 |
|---|
| 4520 | #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_3 0x0b48 |
|---|
| 4521 | #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_3_BASE_IDX 1 |
|---|
| 4522 | #define mmVMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER 0x0b49 |
|---|
| 4523 | #define mmVMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER_BASE_IDX 1 |
|---|
| 4524 | #define mmVMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x0b4a |
|---|
| 4525 | #define mmVMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1 |
|---|
| 4526 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL 0x0b4b |
|---|
| 4527 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_BASE_IDX 1 |
|---|
| 4528 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0 0x0b4c |
|---|
| 4529 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0_BASE_IDX 1 |
|---|
| 4530 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1 0x0b4d |
|---|
| 4531 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1_BASE_IDX 1 |
|---|
| 4532 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2 0x0b4e |
|---|
| 4533 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2_BASE_IDX 1 |
|---|
| 4534 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3 0x0b4f |
|---|
| 4535 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3_BASE_IDX 1 |
|---|
| 4536 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4 0x0b50 |
|---|
| 4537 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4_BASE_IDX 1 |
|---|
| 4538 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5 0x0b51 |
|---|
| 4539 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5_BASE_IDX 1 |
|---|
| 4540 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6 0x0b52 |
|---|
| 4541 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6_BASE_IDX 1 |
|---|
| 4542 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7 0x0b53 |
|---|
| 4543 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7_BASE_IDX 1 |
|---|
| 4544 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8 0x0b54 |
|---|
| 4545 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8_BASE_IDX 1 |
|---|
| 4546 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9 0x0b55 |
|---|
| 4547 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9_BASE_IDX 1 |
|---|
| 4548 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10 0x0b56 |
|---|
| 4549 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10_BASE_IDX 1 |
|---|
| 4550 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11 0x0b57 |
|---|
| 4551 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11_BASE_IDX 1 |
|---|
| 4552 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12 0x0b58 |
|---|
| 4553 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12_BASE_IDX 1 |
|---|
| 4554 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13 0x0b59 |
|---|
| 4555 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13_BASE_IDX 1 |
|---|
| 4556 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14 0x0b5a |
|---|
| 4557 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14_BASE_IDX 1 |
|---|
| 4558 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15 0x0b5b |
|---|
| 4559 | #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15_BASE_IDX 1 |
|---|
| 4560 | #define mmVMSHAREDHV0_UTCL2_CGTT_CLK_CTRL 0x0b5c |
|---|
| 4561 | #define mmVMSHAREDHV0_UTCL2_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 4562 | #define mmVMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID 0x0b5d |
|---|
| 4563 | #define mmVMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID_BASE_IDX 1 |
|---|
| 4564 | #define mmVMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE 0x0b5e |
|---|
| 4565 | #define mmVMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 1 |
|---|
| 4566 | |
|---|
| 4567 | |
|---|
| 4568 | // addressBlock: mmhub_utcl2_atcl2pfcntrdec |
|---|
| 4569 | // base address: 0x6adc0 |
|---|
| 4570 | #define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO 0x0b70 |
|---|
| 4571 | #define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO_BASE_IDX 1 |
|---|
| 4572 | #define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI 0x0b71 |
|---|
| 4573 | #define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI_BASE_IDX 1 |
|---|
| 4574 | |
|---|
| 4575 | |
|---|
| 4576 | // addressBlock: mmhub_utcl2_atcl2pfcntldec |
|---|
| 4577 | // base address: 0x6add0 |
|---|
| 4578 | #define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG 0x0b74 |
|---|
| 4579 | #define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1 |
|---|
| 4580 | #define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG 0x0b75 |
|---|
| 4581 | #define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1 |
|---|
| 4582 | #define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x0b76 |
|---|
| 4583 | #define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
|---|
| 4584 | |
|---|
| 4585 | |
|---|
| 4586 | // addressBlock: mmhub_utcl2_vml2pldec |
|---|
| 4587 | // base address: 0x6ae00 |
|---|
| 4588 | #define mmVML2PL0_MC_VM_L2_PERFCOUNTER0_CFG 0x0b80 |
|---|
| 4589 | #define mmVML2PL0_MC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 |
|---|
| 4590 | #define mmVML2PL0_MC_VM_L2_PERFCOUNTER1_CFG 0x0b81 |
|---|
| 4591 | #define mmVML2PL0_MC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 |
|---|
| 4592 | #define mmVML2PL0_MC_VM_L2_PERFCOUNTER2_CFG 0x0b82 |
|---|
| 4593 | #define mmVML2PL0_MC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 |
|---|
| 4594 | #define mmVML2PL0_MC_VM_L2_PERFCOUNTER3_CFG 0x0b83 |
|---|
| 4595 | #define mmVML2PL0_MC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 |
|---|
| 4596 | #define mmVML2PL0_MC_VM_L2_PERFCOUNTER4_CFG 0x0b84 |
|---|
| 4597 | #define mmVML2PL0_MC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 |
|---|
| 4598 | #define mmVML2PL0_MC_VM_L2_PERFCOUNTER5_CFG 0x0b85 |
|---|
| 4599 | #define mmVML2PL0_MC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 |
|---|
| 4600 | #define mmVML2PL0_MC_VM_L2_PERFCOUNTER6_CFG 0x0b86 |
|---|
| 4601 | #define mmVML2PL0_MC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 |
|---|
| 4602 | #define mmVML2PL0_MC_VM_L2_PERFCOUNTER7_CFG 0x0b87 |
|---|
| 4603 | #define mmVML2PL0_MC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 |
|---|
| 4604 | #define mmVML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x0b88 |
|---|
| 4605 | #define mmVML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
|---|
| 4606 | |
|---|
| 4607 | |
|---|
| 4608 | // addressBlock: mmhub_utcl2_vml2prdec |
|---|
| 4609 | // base address: 0x6ae40 |
|---|
| 4610 | #define mmVML2PR0_MC_VM_L2_PERFCOUNTER_LO 0x0b90 |
|---|
| 4611 | #define mmVML2PR0_MC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 |
|---|
| 4612 | #define mmVML2PR0_MC_VM_L2_PERFCOUNTER_HI 0x0b91 |
|---|
| 4613 | #define mmVML2PR0_MC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 |
|---|
| 4614 | |
|---|
| 4615 | |
|---|
| 4616 | // addressBlock: mmhub_dagb_dagbdec5 |
|---|
| 4617 | // base address: 0x74000 |
|---|
| 4618 | #define mmDAGB5_RDCLI0 0x3000 |
|---|
| 4619 | #define mmDAGB5_RDCLI0_BASE_IDX 1 |
|---|
| 4620 | #define mmDAGB5_RDCLI1 0x3001 |
|---|
| 4621 | #define mmDAGB5_RDCLI1_BASE_IDX 1 |
|---|
| 4622 | #define mmDAGB5_RDCLI2 0x3002 |
|---|
| 4623 | #define mmDAGB5_RDCLI2_BASE_IDX 1 |
|---|
| 4624 | #define mmDAGB5_RDCLI3 0x3003 |
|---|
| 4625 | #define mmDAGB5_RDCLI3_BASE_IDX 1 |
|---|
| 4626 | #define mmDAGB5_RDCLI4 0x3004 |
|---|
| 4627 | #define mmDAGB5_RDCLI4_BASE_IDX 1 |
|---|
| 4628 | #define mmDAGB5_RDCLI5 0x3005 |
|---|
| 4629 | #define mmDAGB5_RDCLI5_BASE_IDX 1 |
|---|
| 4630 | #define mmDAGB5_RDCLI6 0x3006 |
|---|
| 4631 | #define mmDAGB5_RDCLI6_BASE_IDX 1 |
|---|
| 4632 | #define mmDAGB5_RDCLI7 0x3007 |
|---|
| 4633 | #define mmDAGB5_RDCLI7_BASE_IDX 1 |
|---|
| 4634 | #define mmDAGB5_RDCLI8 0x3008 |
|---|
| 4635 | #define mmDAGB5_RDCLI8_BASE_IDX 1 |
|---|
| 4636 | #define mmDAGB5_RDCLI9 0x3009 |
|---|
| 4637 | #define mmDAGB5_RDCLI9_BASE_IDX 1 |
|---|
| 4638 | #define mmDAGB5_RDCLI10 0x300a |
|---|
| 4639 | #define mmDAGB5_RDCLI10_BASE_IDX 1 |
|---|
| 4640 | #define mmDAGB5_RDCLI11 0x300b |
|---|
| 4641 | #define mmDAGB5_RDCLI11_BASE_IDX 1 |
|---|
| 4642 | #define mmDAGB5_RDCLI12 0x300c |
|---|
| 4643 | #define mmDAGB5_RDCLI12_BASE_IDX 1 |
|---|
| 4644 | #define mmDAGB5_RDCLI13 0x300d |
|---|
| 4645 | #define mmDAGB5_RDCLI13_BASE_IDX 1 |
|---|
| 4646 | #define mmDAGB5_RDCLI14 0x300e |
|---|
| 4647 | #define mmDAGB5_RDCLI14_BASE_IDX 1 |
|---|
| 4648 | #define mmDAGB5_RDCLI15 0x300f |
|---|
| 4649 | #define mmDAGB5_RDCLI15_BASE_IDX 1 |
|---|
| 4650 | #define mmDAGB5_RD_CNTL 0x3010 |
|---|
| 4651 | #define mmDAGB5_RD_CNTL_BASE_IDX 1 |
|---|
| 4652 | #define mmDAGB5_RD_GMI_CNTL 0x3011 |
|---|
| 4653 | #define mmDAGB5_RD_GMI_CNTL_BASE_IDX 1 |
|---|
| 4654 | #define mmDAGB5_RD_ADDR_DAGB 0x3012 |
|---|
| 4655 | #define mmDAGB5_RD_ADDR_DAGB_BASE_IDX 1 |
|---|
| 4656 | #define mmDAGB5_RD_OUTPUT_DAGB_MAX_BURST 0x3013 |
|---|
| 4657 | #define mmDAGB5_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 |
|---|
| 4658 | #define mmDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER 0x3014 |
|---|
| 4659 | #define mmDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 |
|---|
| 4660 | #define mmDAGB5_RD_CGTT_CLK_CTRL 0x3015 |
|---|
| 4661 | #define mmDAGB5_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 4662 | #define mmDAGB5_L1TLB_RD_CGTT_CLK_CTRL 0x3016 |
|---|
| 4663 | #define mmDAGB5_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 4664 | #define mmDAGB5_ATCVM_RD_CGTT_CLK_CTRL 0x3017 |
|---|
| 4665 | #define mmDAGB5_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 4666 | #define mmDAGB5_RD_ADDR_DAGB_MAX_BURST0 0x3018 |
|---|
| 4667 | #define mmDAGB5_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 |
|---|
| 4668 | #define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER0 0x3019 |
|---|
| 4669 | #define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 |
|---|
| 4670 | #define mmDAGB5_RD_ADDR_DAGB_MAX_BURST1 0x301a |
|---|
| 4671 | #define mmDAGB5_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 |
|---|
| 4672 | #define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER1 0x301b |
|---|
| 4673 | #define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 |
|---|
| 4674 | #define mmDAGB5_RD_VC0_CNTL 0x301c |
|---|
| 4675 | #define mmDAGB5_RD_VC0_CNTL_BASE_IDX 1 |
|---|
| 4676 | #define mmDAGB5_RD_VC1_CNTL 0x301d |
|---|
| 4677 | #define mmDAGB5_RD_VC1_CNTL_BASE_IDX 1 |
|---|
| 4678 | #define mmDAGB5_RD_VC2_CNTL 0x301e |
|---|
| 4679 | #define mmDAGB5_RD_VC2_CNTL_BASE_IDX 1 |
|---|
| 4680 | #define mmDAGB5_RD_VC3_CNTL 0x301f |
|---|
| 4681 | #define mmDAGB5_RD_VC3_CNTL_BASE_IDX 1 |
|---|
| 4682 | #define mmDAGB5_RD_VC4_CNTL 0x3020 |
|---|
| 4683 | #define mmDAGB5_RD_VC4_CNTL_BASE_IDX 1 |
|---|
| 4684 | #define mmDAGB5_RD_VC5_CNTL 0x3021 |
|---|
| 4685 | #define mmDAGB5_RD_VC5_CNTL_BASE_IDX 1 |
|---|
| 4686 | #define mmDAGB5_RD_VC6_CNTL 0x3022 |
|---|
| 4687 | #define mmDAGB5_RD_VC6_CNTL_BASE_IDX 1 |
|---|
| 4688 | #define mmDAGB5_RD_VC7_CNTL 0x3023 |
|---|
| 4689 | #define mmDAGB5_RD_VC7_CNTL_BASE_IDX 1 |
|---|
| 4690 | #define mmDAGB5_RD_CNTL_MISC 0x3024 |
|---|
| 4691 | #define mmDAGB5_RD_CNTL_MISC_BASE_IDX 1 |
|---|
| 4692 | #define mmDAGB5_RD_TLB_CREDIT 0x3025 |
|---|
| 4693 | #define mmDAGB5_RD_TLB_CREDIT_BASE_IDX 1 |
|---|
| 4694 | #define mmDAGB5_RDCLI_ASK_PENDING 0x3026 |
|---|
| 4695 | #define mmDAGB5_RDCLI_ASK_PENDING_BASE_IDX 1 |
|---|
| 4696 | #define mmDAGB5_RDCLI_GO_PENDING 0x3027 |
|---|
| 4697 | #define mmDAGB5_RDCLI_GO_PENDING_BASE_IDX 1 |
|---|
| 4698 | #define mmDAGB5_RDCLI_GBLSEND_PENDING 0x3028 |
|---|
| 4699 | #define mmDAGB5_RDCLI_GBLSEND_PENDING_BASE_IDX 1 |
|---|
| 4700 | #define mmDAGB5_RDCLI_TLB_PENDING 0x3029 |
|---|
| 4701 | #define mmDAGB5_RDCLI_TLB_PENDING_BASE_IDX 1 |
|---|
| 4702 | #define mmDAGB5_RDCLI_OARB_PENDING 0x302a |
|---|
| 4703 | #define mmDAGB5_RDCLI_OARB_PENDING_BASE_IDX 1 |
|---|
| 4704 | #define mmDAGB5_RDCLI_OSD_PENDING 0x302b |
|---|
| 4705 | #define mmDAGB5_RDCLI_OSD_PENDING_BASE_IDX 1 |
|---|
| 4706 | #define mmDAGB5_WRCLI0 0x302c |
|---|
| 4707 | #define mmDAGB5_WRCLI0_BASE_IDX 1 |
|---|
| 4708 | #define mmDAGB5_WRCLI1 0x302d |
|---|
| 4709 | #define mmDAGB5_WRCLI1_BASE_IDX 1 |
|---|
| 4710 | #define mmDAGB5_WRCLI2 0x302e |
|---|
| 4711 | #define mmDAGB5_WRCLI2_BASE_IDX 1 |
|---|
| 4712 | #define mmDAGB5_WRCLI3 0x302f |
|---|
| 4713 | #define mmDAGB5_WRCLI3_BASE_IDX 1 |
|---|
| 4714 | #define mmDAGB5_WRCLI4 0x3030 |
|---|
| 4715 | #define mmDAGB5_WRCLI4_BASE_IDX 1 |
|---|
| 4716 | #define mmDAGB5_WRCLI5 0x3031 |
|---|
| 4717 | #define mmDAGB5_WRCLI5_BASE_IDX 1 |
|---|
| 4718 | #define mmDAGB5_WRCLI6 0x3032 |
|---|
| 4719 | #define mmDAGB5_WRCLI6_BASE_IDX 1 |
|---|
| 4720 | #define mmDAGB5_WRCLI7 0x3033 |
|---|
| 4721 | #define mmDAGB5_WRCLI7_BASE_IDX 1 |
|---|
| 4722 | #define mmDAGB5_WRCLI8 0x3034 |
|---|
| 4723 | #define mmDAGB5_WRCLI8_BASE_IDX 1 |
|---|
| 4724 | #define mmDAGB5_WRCLI9 0x3035 |
|---|
| 4725 | #define mmDAGB5_WRCLI9_BASE_IDX 1 |
|---|
| 4726 | #define mmDAGB5_WRCLI10 0x3036 |
|---|
| 4727 | #define mmDAGB5_WRCLI10_BASE_IDX 1 |
|---|
| 4728 | #define mmDAGB5_WRCLI11 0x3037 |
|---|
| 4729 | #define mmDAGB5_WRCLI11_BASE_IDX 1 |
|---|
| 4730 | #define mmDAGB5_WRCLI12 0x3038 |
|---|
| 4731 | #define mmDAGB5_WRCLI12_BASE_IDX 1 |
|---|
| 4732 | #define mmDAGB5_WRCLI13 0x3039 |
|---|
| 4733 | #define mmDAGB5_WRCLI13_BASE_IDX 1 |
|---|
| 4734 | #define mmDAGB5_WRCLI14 0x303a |
|---|
| 4735 | #define mmDAGB5_WRCLI14_BASE_IDX 1 |
|---|
| 4736 | #define mmDAGB5_WRCLI15 0x303b |
|---|
| 4737 | #define mmDAGB5_WRCLI15_BASE_IDX 1 |
|---|
| 4738 | #define mmDAGB5_WR_CNTL 0x303c |
|---|
| 4739 | #define mmDAGB5_WR_CNTL_BASE_IDX 1 |
|---|
| 4740 | #define mmDAGB5_WR_GMI_CNTL 0x303d |
|---|
| 4741 | #define mmDAGB5_WR_GMI_CNTL_BASE_IDX 1 |
|---|
| 4742 | #define mmDAGB5_WR_ADDR_DAGB 0x303e |
|---|
| 4743 | #define mmDAGB5_WR_ADDR_DAGB_BASE_IDX 1 |
|---|
| 4744 | #define mmDAGB5_WR_OUTPUT_DAGB_MAX_BURST 0x303f |
|---|
| 4745 | #define mmDAGB5_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 |
|---|
| 4746 | #define mmDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER 0x3040 |
|---|
| 4747 | #define mmDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 |
|---|
| 4748 | #define mmDAGB5_WR_CGTT_CLK_CTRL 0x3041 |
|---|
| 4749 | #define mmDAGB5_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 4750 | #define mmDAGB5_L1TLB_WR_CGTT_CLK_CTRL 0x3042 |
|---|
| 4751 | #define mmDAGB5_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 4752 | #define mmDAGB5_ATCVM_WR_CGTT_CLK_CTRL 0x3043 |
|---|
| 4753 | #define mmDAGB5_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 4754 | #define mmDAGB5_WR_ADDR_DAGB_MAX_BURST0 0x3044 |
|---|
| 4755 | #define mmDAGB5_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 |
|---|
| 4756 | #define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER0 0x3045 |
|---|
| 4757 | #define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 |
|---|
| 4758 | #define mmDAGB5_WR_ADDR_DAGB_MAX_BURST1 0x3046 |
|---|
| 4759 | #define mmDAGB5_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 |
|---|
| 4760 | #define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER1 0x3047 |
|---|
| 4761 | #define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 |
|---|
| 4762 | #define mmDAGB5_WR_DATA_DAGB 0x3048 |
|---|
| 4763 | #define mmDAGB5_WR_DATA_DAGB_BASE_IDX 1 |
|---|
| 4764 | #define mmDAGB5_WR_DATA_DAGB_MAX_BURST0 0x3049 |
|---|
| 4765 | #define mmDAGB5_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 |
|---|
| 4766 | #define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER0 0x304a |
|---|
| 4767 | #define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 |
|---|
| 4768 | #define mmDAGB5_WR_DATA_DAGB_MAX_BURST1 0x304b |
|---|
| 4769 | #define mmDAGB5_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 |
|---|
| 4770 | #define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER1 0x304c |
|---|
| 4771 | #define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 |
|---|
| 4772 | #define mmDAGB5_WR_VC0_CNTL 0x304d |
|---|
| 4773 | #define mmDAGB5_WR_VC0_CNTL_BASE_IDX 1 |
|---|
| 4774 | #define mmDAGB5_WR_VC1_CNTL 0x304e |
|---|
| 4775 | #define mmDAGB5_WR_VC1_CNTL_BASE_IDX 1 |
|---|
| 4776 | #define mmDAGB5_WR_VC2_CNTL 0x304f |
|---|
| 4777 | #define mmDAGB5_WR_VC2_CNTL_BASE_IDX 1 |
|---|
| 4778 | #define mmDAGB5_WR_VC3_CNTL 0x3050 |
|---|
| 4779 | #define mmDAGB5_WR_VC3_CNTL_BASE_IDX 1 |
|---|
| 4780 | #define mmDAGB5_WR_VC4_CNTL 0x3051 |
|---|
| 4781 | #define mmDAGB5_WR_VC4_CNTL_BASE_IDX 1 |
|---|
| 4782 | #define mmDAGB5_WR_VC5_CNTL 0x3052 |
|---|
| 4783 | #define mmDAGB5_WR_VC5_CNTL_BASE_IDX 1 |
|---|
| 4784 | #define mmDAGB5_WR_VC6_CNTL 0x3053 |
|---|
| 4785 | #define mmDAGB5_WR_VC6_CNTL_BASE_IDX 1 |
|---|
| 4786 | #define mmDAGB5_WR_VC7_CNTL 0x3054 |
|---|
| 4787 | #define mmDAGB5_WR_VC7_CNTL_BASE_IDX 1 |
|---|
| 4788 | #define mmDAGB5_WR_CNTL_MISC 0x3055 |
|---|
| 4789 | #define mmDAGB5_WR_CNTL_MISC_BASE_IDX 1 |
|---|
| 4790 | #define mmDAGB5_WR_TLB_CREDIT 0x3056 |
|---|
| 4791 | #define mmDAGB5_WR_TLB_CREDIT_BASE_IDX 1 |
|---|
| 4792 | #define mmDAGB5_WR_DATA_CREDIT 0x3057 |
|---|
| 4793 | #define mmDAGB5_WR_DATA_CREDIT_BASE_IDX 1 |
|---|
| 4794 | #define mmDAGB5_WR_MISC_CREDIT 0x3058 |
|---|
| 4795 | #define mmDAGB5_WR_MISC_CREDIT_BASE_IDX 1 |
|---|
| 4796 | #define mmDAGB5_WRCLI_ASK_PENDING 0x305d |
|---|
| 4797 | #define mmDAGB5_WRCLI_ASK_PENDING_BASE_IDX 1 |
|---|
| 4798 | #define mmDAGB5_WRCLI_GO_PENDING 0x305e |
|---|
| 4799 | #define mmDAGB5_WRCLI_GO_PENDING_BASE_IDX 1 |
|---|
| 4800 | #define mmDAGB5_WRCLI_GBLSEND_PENDING 0x305f |
|---|
| 4801 | #define mmDAGB5_WRCLI_GBLSEND_PENDING_BASE_IDX 1 |
|---|
| 4802 | #define mmDAGB5_WRCLI_TLB_PENDING 0x3060 |
|---|
| 4803 | #define mmDAGB5_WRCLI_TLB_PENDING_BASE_IDX 1 |
|---|
| 4804 | #define mmDAGB5_WRCLI_OARB_PENDING 0x3061 |
|---|
| 4805 | #define mmDAGB5_WRCLI_OARB_PENDING_BASE_IDX 1 |
|---|
| 4806 | #define mmDAGB5_WRCLI_OSD_PENDING 0x3062 |
|---|
| 4807 | #define mmDAGB5_WRCLI_OSD_PENDING_BASE_IDX 1 |
|---|
| 4808 | #define mmDAGB5_WRCLI_DBUS_ASK_PENDING 0x3063 |
|---|
| 4809 | #define mmDAGB5_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 |
|---|
| 4810 | #define mmDAGB5_WRCLI_DBUS_GO_PENDING 0x3064 |
|---|
| 4811 | #define mmDAGB5_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 |
|---|
| 4812 | #define mmDAGB5_DAGB_DLY 0x3065 |
|---|
| 4813 | #define mmDAGB5_DAGB_DLY_BASE_IDX 1 |
|---|
| 4814 | #define mmDAGB5_CNTL_MISC 0x3066 |
|---|
| 4815 | #define mmDAGB5_CNTL_MISC_BASE_IDX 1 |
|---|
| 4816 | #define mmDAGB5_CNTL_MISC2 0x3067 |
|---|
| 4817 | #define mmDAGB5_CNTL_MISC2_BASE_IDX 1 |
|---|
| 4818 | #define mmDAGB5_FIFO_EMPTY 0x3068 |
|---|
| 4819 | #define mmDAGB5_FIFO_EMPTY_BASE_IDX 1 |
|---|
| 4820 | #define mmDAGB5_FIFO_FULL 0x3069 |
|---|
| 4821 | #define mmDAGB5_FIFO_FULL_BASE_IDX 1 |
|---|
| 4822 | #define mmDAGB5_WR_CREDITS_FULL 0x306a |
|---|
| 4823 | #define mmDAGB5_WR_CREDITS_FULL_BASE_IDX 1 |
|---|
| 4824 | #define mmDAGB5_RD_CREDITS_FULL 0x306b |
|---|
| 4825 | #define mmDAGB5_RD_CREDITS_FULL_BASE_IDX 1 |
|---|
| 4826 | #define mmDAGB5_PERFCOUNTER_LO 0x306c |
|---|
| 4827 | #define mmDAGB5_PERFCOUNTER_LO_BASE_IDX 1 |
|---|
| 4828 | #define mmDAGB5_PERFCOUNTER_HI 0x306d |
|---|
| 4829 | #define mmDAGB5_PERFCOUNTER_HI_BASE_IDX 1 |
|---|
| 4830 | #define mmDAGB5_PERFCOUNTER0_CFG 0x306e |
|---|
| 4831 | #define mmDAGB5_PERFCOUNTER0_CFG_BASE_IDX 1 |
|---|
| 4832 | #define mmDAGB5_PERFCOUNTER1_CFG 0x306f |
|---|
| 4833 | #define mmDAGB5_PERFCOUNTER1_CFG_BASE_IDX 1 |
|---|
| 4834 | #define mmDAGB5_PERFCOUNTER2_CFG 0x3070 |
|---|
| 4835 | #define mmDAGB5_PERFCOUNTER2_CFG_BASE_IDX 1 |
|---|
| 4836 | #define mmDAGB5_PERFCOUNTER_RSLT_CNTL 0x3071 |
|---|
| 4837 | #define mmDAGB5_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
|---|
| 4838 | #define mmDAGB5_RESERVE0 0x3072 |
|---|
| 4839 | #define mmDAGB5_RESERVE0_BASE_IDX 1 |
|---|
| 4840 | #define mmDAGB5_RESERVE1 0x3073 |
|---|
| 4841 | #define mmDAGB5_RESERVE1_BASE_IDX 1 |
|---|
| 4842 | #define mmDAGB5_RESERVE2 0x3074 |
|---|
| 4843 | #define mmDAGB5_RESERVE2_BASE_IDX 1 |
|---|
| 4844 | #define mmDAGB5_RESERVE3 0x3075 |
|---|
| 4845 | #define mmDAGB5_RESERVE3_BASE_IDX 1 |
|---|
| 4846 | #define mmDAGB5_RESERVE4 0x3076 |
|---|
| 4847 | #define mmDAGB5_RESERVE4_BASE_IDX 1 |
|---|
| 4848 | #define mmDAGB5_RESERVE5 0x3077 |
|---|
| 4849 | #define mmDAGB5_RESERVE5_BASE_IDX 1 |
|---|
| 4850 | #define mmDAGB5_RESERVE6 0x3078 |
|---|
| 4851 | #define mmDAGB5_RESERVE6_BASE_IDX 1 |
|---|
| 4852 | #define mmDAGB5_RESERVE7 0x3079 |
|---|
| 4853 | #define mmDAGB5_RESERVE7_BASE_IDX 1 |
|---|
| 4854 | #define mmDAGB5_RESERVE8 0x307a |
|---|
| 4855 | #define mmDAGB5_RESERVE8_BASE_IDX 1 |
|---|
| 4856 | #define mmDAGB5_RESERVE9 0x307b |
|---|
| 4857 | #define mmDAGB5_RESERVE9_BASE_IDX 1 |
|---|
| 4858 | #define mmDAGB5_RESERVE10 0x307c |
|---|
| 4859 | #define mmDAGB5_RESERVE10_BASE_IDX 1 |
|---|
| 4860 | #define mmDAGB5_RESERVE11 0x307d |
|---|
| 4861 | #define mmDAGB5_RESERVE11_BASE_IDX 1 |
|---|
| 4862 | #define mmDAGB5_RESERVE12 0x307e |
|---|
| 4863 | #define mmDAGB5_RESERVE12_BASE_IDX 1 |
|---|
| 4864 | #define mmDAGB5_RESERVE13 0x307f |
|---|
| 4865 | #define mmDAGB5_RESERVE13_BASE_IDX 1 |
|---|
| 4866 | |
|---|
| 4867 | |
|---|
| 4868 | // addressBlock: mmhub_dagb_dagbdec6 |
|---|
| 4869 | // base address: 0x74200 |
|---|
| 4870 | #define mmDAGB6_RDCLI0 0x3080 |
|---|
| 4871 | #define mmDAGB6_RDCLI0_BASE_IDX 1 |
|---|
| 4872 | #define mmDAGB6_RDCLI1 0x3081 |
|---|
| 4873 | #define mmDAGB6_RDCLI1_BASE_IDX 1 |
|---|
| 4874 | #define mmDAGB6_RDCLI2 0x3082 |
|---|
| 4875 | #define mmDAGB6_RDCLI2_BASE_IDX 1 |
|---|
| 4876 | #define mmDAGB6_RDCLI3 0x3083 |
|---|
| 4877 | #define mmDAGB6_RDCLI3_BASE_IDX 1 |
|---|
| 4878 | #define mmDAGB6_RDCLI4 0x3084 |
|---|
| 4879 | #define mmDAGB6_RDCLI4_BASE_IDX 1 |
|---|
| 4880 | #define mmDAGB6_RDCLI5 0x3085 |
|---|
| 4881 | #define mmDAGB6_RDCLI5_BASE_IDX 1 |
|---|
| 4882 | #define mmDAGB6_RDCLI6 0x3086 |
|---|
| 4883 | #define mmDAGB6_RDCLI6_BASE_IDX 1 |
|---|
| 4884 | #define mmDAGB6_RDCLI7 0x3087 |
|---|
| 4885 | #define mmDAGB6_RDCLI7_BASE_IDX 1 |
|---|
| 4886 | #define mmDAGB6_RDCLI8 0x3088 |
|---|
| 4887 | #define mmDAGB6_RDCLI8_BASE_IDX 1 |
|---|
| 4888 | #define mmDAGB6_RDCLI9 0x3089 |
|---|
| 4889 | #define mmDAGB6_RDCLI9_BASE_IDX 1 |
|---|
| 4890 | #define mmDAGB6_RDCLI10 0x308a |
|---|
| 4891 | #define mmDAGB6_RDCLI10_BASE_IDX 1 |
|---|
| 4892 | #define mmDAGB6_RDCLI11 0x308b |
|---|
| 4893 | #define mmDAGB6_RDCLI11_BASE_IDX 1 |
|---|
| 4894 | #define mmDAGB6_RDCLI12 0x308c |
|---|
| 4895 | #define mmDAGB6_RDCLI12_BASE_IDX 1 |
|---|
| 4896 | #define mmDAGB6_RDCLI13 0x308d |
|---|
| 4897 | #define mmDAGB6_RDCLI13_BASE_IDX 1 |
|---|
| 4898 | #define mmDAGB6_RDCLI14 0x308e |
|---|
| 4899 | #define mmDAGB6_RDCLI14_BASE_IDX 1 |
|---|
| 4900 | #define mmDAGB6_RDCLI15 0x308f |
|---|
| 4901 | #define mmDAGB6_RDCLI15_BASE_IDX 1 |
|---|
| 4902 | #define mmDAGB6_RD_CNTL 0x3090 |
|---|
| 4903 | #define mmDAGB6_RD_CNTL_BASE_IDX 1 |
|---|
| 4904 | #define mmDAGB6_RD_GMI_CNTL 0x3091 |
|---|
| 4905 | #define mmDAGB6_RD_GMI_CNTL_BASE_IDX 1 |
|---|
| 4906 | #define mmDAGB6_RD_ADDR_DAGB 0x3092 |
|---|
| 4907 | #define mmDAGB6_RD_ADDR_DAGB_BASE_IDX 1 |
|---|
| 4908 | #define mmDAGB6_RD_OUTPUT_DAGB_MAX_BURST 0x3093 |
|---|
| 4909 | #define mmDAGB6_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 |
|---|
| 4910 | #define mmDAGB6_RD_OUTPUT_DAGB_LAZY_TIMER 0x3094 |
|---|
| 4911 | #define mmDAGB6_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 |
|---|
| 4912 | #define mmDAGB6_RD_CGTT_CLK_CTRL 0x3095 |
|---|
| 4913 | #define mmDAGB6_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 4914 | #define mmDAGB6_L1TLB_RD_CGTT_CLK_CTRL 0x3096 |
|---|
| 4915 | #define mmDAGB6_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 4916 | #define mmDAGB6_ATCVM_RD_CGTT_CLK_CTRL 0x3097 |
|---|
| 4917 | #define mmDAGB6_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 4918 | #define mmDAGB6_RD_ADDR_DAGB_MAX_BURST0 0x3098 |
|---|
| 4919 | #define mmDAGB6_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 |
|---|
| 4920 | #define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER0 0x3099 |
|---|
| 4921 | #define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 |
|---|
| 4922 | #define mmDAGB6_RD_ADDR_DAGB_MAX_BURST1 0x309a |
|---|
| 4923 | #define mmDAGB6_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 |
|---|
| 4924 | #define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER1 0x309b |
|---|
| 4925 | #define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 |
|---|
| 4926 | #define mmDAGB6_RD_VC0_CNTL 0x309c |
|---|
| 4927 | #define mmDAGB6_RD_VC0_CNTL_BASE_IDX 1 |
|---|
| 4928 | #define mmDAGB6_RD_VC1_CNTL 0x309d |
|---|
| 4929 | #define mmDAGB6_RD_VC1_CNTL_BASE_IDX 1 |
|---|
| 4930 | #define mmDAGB6_RD_VC2_CNTL 0x309e |
|---|
| 4931 | #define mmDAGB6_RD_VC2_CNTL_BASE_IDX 1 |
|---|
| 4932 | #define mmDAGB6_RD_VC3_CNTL 0x309f |
|---|
| 4933 | #define mmDAGB6_RD_VC3_CNTL_BASE_IDX 1 |
|---|
| 4934 | #define mmDAGB6_RD_VC4_CNTL 0x30a0 |
|---|
| 4935 | #define mmDAGB6_RD_VC4_CNTL_BASE_IDX 1 |
|---|
| 4936 | #define mmDAGB6_RD_VC5_CNTL 0x30a1 |
|---|
| 4937 | #define mmDAGB6_RD_VC5_CNTL_BASE_IDX 1 |
|---|
| 4938 | #define mmDAGB6_RD_VC6_CNTL 0x30a2 |
|---|
| 4939 | #define mmDAGB6_RD_VC6_CNTL_BASE_IDX 1 |
|---|
| 4940 | #define mmDAGB6_RD_VC7_CNTL 0x30a3 |
|---|
| 4941 | #define mmDAGB6_RD_VC7_CNTL_BASE_IDX 1 |
|---|
| 4942 | #define mmDAGB6_RD_CNTL_MISC 0x30a4 |
|---|
| 4943 | #define mmDAGB6_RD_CNTL_MISC_BASE_IDX 1 |
|---|
| 4944 | #define mmDAGB6_RD_TLB_CREDIT 0x30a5 |
|---|
| 4945 | #define mmDAGB6_RD_TLB_CREDIT_BASE_IDX 1 |
|---|
| 4946 | #define mmDAGB6_RDCLI_ASK_PENDING 0x30a6 |
|---|
| 4947 | #define mmDAGB6_RDCLI_ASK_PENDING_BASE_IDX 1 |
|---|
| 4948 | #define mmDAGB6_RDCLI_GO_PENDING 0x30a7 |
|---|
| 4949 | #define mmDAGB6_RDCLI_GO_PENDING_BASE_IDX 1 |
|---|
| 4950 | #define mmDAGB6_RDCLI_GBLSEND_PENDING 0x30a8 |
|---|
| 4951 | #define mmDAGB6_RDCLI_GBLSEND_PENDING_BASE_IDX 1 |
|---|
| 4952 | #define mmDAGB6_RDCLI_TLB_PENDING 0x30a9 |
|---|
| 4953 | #define mmDAGB6_RDCLI_TLB_PENDING_BASE_IDX 1 |
|---|
| 4954 | #define mmDAGB6_RDCLI_OARB_PENDING 0x30aa |
|---|
| 4955 | #define mmDAGB6_RDCLI_OARB_PENDING_BASE_IDX 1 |
|---|
| 4956 | #define mmDAGB6_RDCLI_OSD_PENDING 0x30ab |
|---|
| 4957 | #define mmDAGB6_RDCLI_OSD_PENDING_BASE_IDX 1 |
|---|
| 4958 | #define mmDAGB6_WRCLI0 0x30ac |
|---|
| 4959 | #define mmDAGB6_WRCLI0_BASE_IDX 1 |
|---|
| 4960 | #define mmDAGB6_WRCLI1 0x30ad |
|---|
| 4961 | #define mmDAGB6_WRCLI1_BASE_IDX 1 |
|---|
| 4962 | #define mmDAGB6_WRCLI2 0x30ae |
|---|
| 4963 | #define mmDAGB6_WRCLI2_BASE_IDX 1 |
|---|
| 4964 | #define mmDAGB6_WRCLI3 0x30af |
|---|
| 4965 | #define mmDAGB6_WRCLI3_BASE_IDX 1 |
|---|
| 4966 | #define mmDAGB6_WRCLI4 0x30b0 |
|---|
| 4967 | #define mmDAGB6_WRCLI4_BASE_IDX 1 |
|---|
| 4968 | #define mmDAGB6_WRCLI5 0x30b1 |
|---|
| 4969 | #define mmDAGB6_WRCLI5_BASE_IDX 1 |
|---|
| 4970 | #define mmDAGB6_WRCLI6 0x30b2 |
|---|
| 4971 | #define mmDAGB6_WRCLI6_BASE_IDX 1 |
|---|
| 4972 | #define mmDAGB6_WRCLI7 0x30b3 |
|---|
| 4973 | #define mmDAGB6_WRCLI7_BASE_IDX 1 |
|---|
| 4974 | #define mmDAGB6_WRCLI8 0x30b4 |
|---|
| 4975 | #define mmDAGB6_WRCLI8_BASE_IDX 1 |
|---|
| 4976 | #define mmDAGB6_WRCLI9 0x30b5 |
|---|
| 4977 | #define mmDAGB6_WRCLI9_BASE_IDX 1 |
|---|
| 4978 | #define mmDAGB6_WRCLI10 0x30b6 |
|---|
| 4979 | #define mmDAGB6_WRCLI10_BASE_IDX 1 |
|---|
| 4980 | #define mmDAGB6_WRCLI11 0x30b7 |
|---|
| 4981 | #define mmDAGB6_WRCLI11_BASE_IDX 1 |
|---|
| 4982 | #define mmDAGB6_WRCLI12 0x30b8 |
|---|
| 4983 | #define mmDAGB6_WRCLI12_BASE_IDX 1 |
|---|
| 4984 | #define mmDAGB6_WRCLI13 0x30b9 |
|---|
| 4985 | #define mmDAGB6_WRCLI13_BASE_IDX 1 |
|---|
| 4986 | #define mmDAGB6_WRCLI14 0x30ba |
|---|
| 4987 | #define mmDAGB6_WRCLI14_BASE_IDX 1 |
|---|
| 4988 | #define mmDAGB6_WRCLI15 0x30bb |
|---|
| 4989 | #define mmDAGB6_WRCLI15_BASE_IDX 1 |
|---|
| 4990 | #define mmDAGB6_WR_CNTL 0x30bc |
|---|
| 4991 | #define mmDAGB6_WR_CNTL_BASE_IDX 1 |
|---|
| 4992 | #define mmDAGB6_WR_GMI_CNTL 0x30bd |
|---|
| 4993 | #define mmDAGB6_WR_GMI_CNTL_BASE_IDX 1 |
|---|
| 4994 | #define mmDAGB6_WR_ADDR_DAGB 0x30be |
|---|
| 4995 | #define mmDAGB6_WR_ADDR_DAGB_BASE_IDX 1 |
|---|
| 4996 | #define mmDAGB6_WR_OUTPUT_DAGB_MAX_BURST 0x30bf |
|---|
| 4997 | #define mmDAGB6_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 |
|---|
| 4998 | #define mmDAGB6_WR_OUTPUT_DAGB_LAZY_TIMER 0x30c0 |
|---|
| 4999 | #define mmDAGB6_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 |
|---|
| 5000 | #define mmDAGB6_WR_CGTT_CLK_CTRL 0x30c1 |
|---|
| 5001 | #define mmDAGB6_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 5002 | #define mmDAGB6_L1TLB_WR_CGTT_CLK_CTRL 0x30c2 |
|---|
| 5003 | #define mmDAGB6_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 5004 | #define mmDAGB6_ATCVM_WR_CGTT_CLK_CTRL 0x30c3 |
|---|
| 5005 | #define mmDAGB6_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 5006 | #define mmDAGB6_WR_ADDR_DAGB_MAX_BURST0 0x30c4 |
|---|
| 5007 | #define mmDAGB6_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 |
|---|
| 5008 | #define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER0 0x30c5 |
|---|
| 5009 | #define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 |
|---|
| 5010 | #define mmDAGB6_WR_ADDR_DAGB_MAX_BURST1 0x30c6 |
|---|
| 5011 | #define mmDAGB6_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 |
|---|
| 5012 | #define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER1 0x30c7 |
|---|
| 5013 | #define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 |
|---|
| 5014 | #define mmDAGB6_WR_DATA_DAGB 0x30c8 |
|---|
| 5015 | #define mmDAGB6_WR_DATA_DAGB_BASE_IDX 1 |
|---|
| 5016 | #define mmDAGB6_WR_DATA_DAGB_MAX_BURST0 0x30c9 |
|---|
| 5017 | #define mmDAGB6_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 |
|---|
| 5018 | #define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER0 0x30ca |
|---|
| 5019 | #define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 |
|---|
| 5020 | #define mmDAGB6_WR_DATA_DAGB_MAX_BURST1 0x30cb |
|---|
| 5021 | #define mmDAGB6_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 |
|---|
| 5022 | #define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER1 0x30cc |
|---|
| 5023 | #define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 |
|---|
| 5024 | #define mmDAGB6_WR_VC0_CNTL 0x30cd |
|---|
| 5025 | #define mmDAGB6_WR_VC0_CNTL_BASE_IDX 1 |
|---|
| 5026 | #define mmDAGB6_WR_VC1_CNTL 0x30ce |
|---|
| 5027 | #define mmDAGB6_WR_VC1_CNTL_BASE_IDX 1 |
|---|
| 5028 | #define mmDAGB6_WR_VC2_CNTL 0x30cf |
|---|
| 5029 | #define mmDAGB6_WR_VC2_CNTL_BASE_IDX 1 |
|---|
| 5030 | #define mmDAGB6_WR_VC3_CNTL 0x30d0 |
|---|
| 5031 | #define mmDAGB6_WR_VC3_CNTL_BASE_IDX 1 |
|---|
| 5032 | #define mmDAGB6_WR_VC4_CNTL 0x30d1 |
|---|
| 5033 | #define mmDAGB6_WR_VC4_CNTL_BASE_IDX 1 |
|---|
| 5034 | #define mmDAGB6_WR_VC5_CNTL 0x30d2 |
|---|
| 5035 | #define mmDAGB6_WR_VC5_CNTL_BASE_IDX 1 |
|---|
| 5036 | #define mmDAGB6_WR_VC6_CNTL 0x30d3 |
|---|
| 5037 | #define mmDAGB6_WR_VC6_CNTL_BASE_IDX 1 |
|---|
| 5038 | #define mmDAGB6_WR_VC7_CNTL 0x30d4 |
|---|
| 5039 | #define mmDAGB6_WR_VC7_CNTL_BASE_IDX 1 |
|---|
| 5040 | #define mmDAGB6_WR_CNTL_MISC 0x30d5 |
|---|
| 5041 | #define mmDAGB6_WR_CNTL_MISC_BASE_IDX 1 |
|---|
| 5042 | #define mmDAGB6_WR_TLB_CREDIT 0x30d6 |
|---|
| 5043 | #define mmDAGB6_WR_TLB_CREDIT_BASE_IDX 1 |
|---|
| 5044 | #define mmDAGB6_WR_DATA_CREDIT 0x30d7 |
|---|
| 5045 | #define mmDAGB6_WR_DATA_CREDIT_BASE_IDX 1 |
|---|
| 5046 | #define mmDAGB6_WR_MISC_CREDIT 0x30d8 |
|---|
| 5047 | #define mmDAGB6_WR_MISC_CREDIT_BASE_IDX 1 |
|---|
| 5048 | #define mmDAGB6_WRCLI_ASK_PENDING 0x30dd |
|---|
| 5049 | #define mmDAGB6_WRCLI_ASK_PENDING_BASE_IDX 1 |
|---|
| 5050 | #define mmDAGB6_WRCLI_GO_PENDING 0x30de |
|---|
| 5051 | #define mmDAGB6_WRCLI_GO_PENDING_BASE_IDX 1 |
|---|
| 5052 | #define mmDAGB6_WRCLI_GBLSEND_PENDING 0x30df |
|---|
| 5053 | #define mmDAGB6_WRCLI_GBLSEND_PENDING_BASE_IDX 1 |
|---|
| 5054 | #define mmDAGB6_WRCLI_TLB_PENDING 0x30e0 |
|---|
| 5055 | #define mmDAGB6_WRCLI_TLB_PENDING_BASE_IDX 1 |
|---|
| 5056 | #define mmDAGB6_WRCLI_OARB_PENDING 0x30e1 |
|---|
| 5057 | #define mmDAGB6_WRCLI_OARB_PENDING_BASE_IDX 1 |
|---|
| 5058 | #define mmDAGB6_WRCLI_OSD_PENDING 0x30e2 |
|---|
| 5059 | #define mmDAGB6_WRCLI_OSD_PENDING_BASE_IDX 1 |
|---|
| 5060 | #define mmDAGB6_WRCLI_DBUS_ASK_PENDING 0x30e3 |
|---|
| 5061 | #define mmDAGB6_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 |
|---|
| 5062 | #define mmDAGB6_WRCLI_DBUS_GO_PENDING 0x30e4 |
|---|
| 5063 | #define mmDAGB6_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 |
|---|
| 5064 | #define mmDAGB6_DAGB_DLY 0x30e5 |
|---|
| 5065 | #define mmDAGB6_DAGB_DLY_BASE_IDX 1 |
|---|
| 5066 | #define mmDAGB6_CNTL_MISC 0x30e6 |
|---|
| 5067 | #define mmDAGB6_CNTL_MISC_BASE_IDX 1 |
|---|
| 5068 | #define mmDAGB6_CNTL_MISC2 0x30e7 |
|---|
| 5069 | #define mmDAGB6_CNTL_MISC2_BASE_IDX 1 |
|---|
| 5070 | #define mmDAGB6_FIFO_EMPTY 0x30e8 |
|---|
| 5071 | #define mmDAGB6_FIFO_EMPTY_BASE_IDX 1 |
|---|
| 5072 | #define mmDAGB6_FIFO_FULL 0x30e9 |
|---|
| 5073 | #define mmDAGB6_FIFO_FULL_BASE_IDX 1 |
|---|
| 5074 | #define mmDAGB6_WR_CREDITS_FULL 0x30ea |
|---|
| 5075 | #define mmDAGB6_WR_CREDITS_FULL_BASE_IDX 1 |
|---|
| 5076 | #define mmDAGB6_RD_CREDITS_FULL 0x30eb |
|---|
| 5077 | #define mmDAGB6_RD_CREDITS_FULL_BASE_IDX 1 |
|---|
| 5078 | #define mmDAGB6_PERFCOUNTER_LO 0x30ec |
|---|
| 5079 | #define mmDAGB6_PERFCOUNTER_LO_BASE_IDX 1 |
|---|
| 5080 | #define mmDAGB6_PERFCOUNTER_HI 0x30ed |
|---|
| 5081 | #define mmDAGB6_PERFCOUNTER_HI_BASE_IDX 1 |
|---|
| 5082 | #define mmDAGB6_PERFCOUNTER0_CFG 0x30ee |
|---|
| 5083 | #define mmDAGB6_PERFCOUNTER0_CFG_BASE_IDX 1 |
|---|
| 5084 | #define mmDAGB6_PERFCOUNTER1_CFG 0x30ef |
|---|
| 5085 | #define mmDAGB6_PERFCOUNTER1_CFG_BASE_IDX 1 |
|---|
| 5086 | #define mmDAGB6_PERFCOUNTER2_CFG 0x30f0 |
|---|
| 5087 | #define mmDAGB6_PERFCOUNTER2_CFG_BASE_IDX 1 |
|---|
| 5088 | #define mmDAGB6_PERFCOUNTER_RSLT_CNTL 0x30f1 |
|---|
| 5089 | #define mmDAGB6_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
|---|
| 5090 | #define mmDAGB6_RESERVE0 0x30f2 |
|---|
| 5091 | #define mmDAGB6_RESERVE0_BASE_IDX 1 |
|---|
| 5092 | #define mmDAGB6_RESERVE1 0x30f3 |
|---|
| 5093 | #define mmDAGB6_RESERVE1_BASE_IDX 1 |
|---|
| 5094 | #define mmDAGB6_RESERVE2 0x30f4 |
|---|
| 5095 | #define mmDAGB6_RESERVE2_BASE_IDX 1 |
|---|
| 5096 | #define mmDAGB6_RESERVE3 0x30f5 |
|---|
| 5097 | #define mmDAGB6_RESERVE3_BASE_IDX 1 |
|---|
| 5098 | #define mmDAGB6_RESERVE4 0x30f6 |
|---|
| 5099 | #define mmDAGB6_RESERVE4_BASE_IDX 1 |
|---|
| 5100 | #define mmDAGB6_RESERVE5 0x30f7 |
|---|
| 5101 | #define mmDAGB6_RESERVE5_BASE_IDX 1 |
|---|
| 5102 | #define mmDAGB6_RESERVE6 0x30f8 |
|---|
| 5103 | #define mmDAGB6_RESERVE6_BASE_IDX 1 |
|---|
| 5104 | #define mmDAGB6_RESERVE7 0x30f9 |
|---|
| 5105 | #define mmDAGB6_RESERVE7_BASE_IDX 1 |
|---|
| 5106 | #define mmDAGB6_RESERVE8 0x30fa |
|---|
| 5107 | #define mmDAGB6_RESERVE8_BASE_IDX 1 |
|---|
| 5108 | #define mmDAGB6_RESERVE9 0x30fb |
|---|
| 5109 | #define mmDAGB6_RESERVE9_BASE_IDX 1 |
|---|
| 5110 | #define mmDAGB6_RESERVE10 0x30fc |
|---|
| 5111 | #define mmDAGB6_RESERVE10_BASE_IDX 1 |
|---|
| 5112 | #define mmDAGB6_RESERVE11 0x30fd |
|---|
| 5113 | #define mmDAGB6_RESERVE11_BASE_IDX 1 |
|---|
| 5114 | #define mmDAGB6_RESERVE12 0x30fe |
|---|
| 5115 | #define mmDAGB6_RESERVE12_BASE_IDX 1 |
|---|
| 5116 | #define mmDAGB6_RESERVE13 0x30ff |
|---|
| 5117 | #define mmDAGB6_RESERVE13_BASE_IDX 1 |
|---|
| 5118 | |
|---|
| 5119 | |
|---|
| 5120 | // addressBlock: mmhub_dagb_dagbdec7 |
|---|
| 5121 | // base address: 0x74400 |
|---|
| 5122 | #define mmDAGB7_RDCLI0 0x3100 |
|---|
| 5123 | #define mmDAGB7_RDCLI0_BASE_IDX 1 |
|---|
| 5124 | #define mmDAGB7_RDCLI1 0x3101 |
|---|
| 5125 | #define mmDAGB7_RDCLI1_BASE_IDX 1 |
|---|
| 5126 | #define mmDAGB7_RDCLI2 0x3102 |
|---|
| 5127 | #define mmDAGB7_RDCLI2_BASE_IDX 1 |
|---|
| 5128 | #define mmDAGB7_RDCLI3 0x3103 |
|---|
| 5129 | #define mmDAGB7_RDCLI3_BASE_IDX 1 |
|---|
| 5130 | #define mmDAGB7_RDCLI4 0x3104 |
|---|
| 5131 | #define mmDAGB7_RDCLI4_BASE_IDX 1 |
|---|
| 5132 | #define mmDAGB7_RDCLI5 0x3105 |
|---|
| 5133 | #define mmDAGB7_RDCLI5_BASE_IDX 1 |
|---|
| 5134 | #define mmDAGB7_RDCLI6 0x3106 |
|---|
| 5135 | #define mmDAGB7_RDCLI6_BASE_IDX 1 |
|---|
| 5136 | #define mmDAGB7_RDCLI7 0x3107 |
|---|
| 5137 | #define mmDAGB7_RDCLI7_BASE_IDX 1 |
|---|
| 5138 | #define mmDAGB7_RDCLI8 0x3108 |
|---|
| 5139 | #define mmDAGB7_RDCLI8_BASE_IDX 1 |
|---|
| 5140 | #define mmDAGB7_RDCLI9 0x3109 |
|---|
| 5141 | #define mmDAGB7_RDCLI9_BASE_IDX 1 |
|---|
| 5142 | #define mmDAGB7_RDCLI10 0x310a |
|---|
| 5143 | #define mmDAGB7_RDCLI10_BASE_IDX 1 |
|---|
| 5144 | #define mmDAGB7_RDCLI11 0x310b |
|---|
| 5145 | #define mmDAGB7_RDCLI11_BASE_IDX 1 |
|---|
| 5146 | #define mmDAGB7_RDCLI12 0x310c |
|---|
| 5147 | #define mmDAGB7_RDCLI12_BASE_IDX 1 |
|---|
| 5148 | #define mmDAGB7_RDCLI13 0x310d |
|---|
| 5149 | #define mmDAGB7_RDCLI13_BASE_IDX 1 |
|---|
| 5150 | #define mmDAGB7_RDCLI14 0x310e |
|---|
| 5151 | #define mmDAGB7_RDCLI14_BASE_IDX 1 |
|---|
| 5152 | #define mmDAGB7_RDCLI15 0x310f |
|---|
| 5153 | #define mmDAGB7_RDCLI15_BASE_IDX 1 |
|---|
| 5154 | #define mmDAGB7_RD_CNTL 0x3110 |
|---|
| 5155 | #define mmDAGB7_RD_CNTL_BASE_IDX 1 |
|---|
| 5156 | #define mmDAGB7_RD_GMI_CNTL 0x3111 |
|---|
| 5157 | #define mmDAGB7_RD_GMI_CNTL_BASE_IDX 1 |
|---|
| 5158 | #define mmDAGB7_RD_ADDR_DAGB 0x3112 |
|---|
| 5159 | #define mmDAGB7_RD_ADDR_DAGB_BASE_IDX 1 |
|---|
| 5160 | #define mmDAGB7_RD_OUTPUT_DAGB_MAX_BURST 0x3113 |
|---|
| 5161 | #define mmDAGB7_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 |
|---|
| 5162 | #define mmDAGB7_RD_OUTPUT_DAGB_LAZY_TIMER 0x3114 |
|---|
| 5163 | #define mmDAGB7_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 |
|---|
| 5164 | #define mmDAGB7_RD_CGTT_CLK_CTRL 0x3115 |
|---|
| 5165 | #define mmDAGB7_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 5166 | #define mmDAGB7_L1TLB_RD_CGTT_CLK_CTRL 0x3116 |
|---|
| 5167 | #define mmDAGB7_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 5168 | #define mmDAGB7_ATCVM_RD_CGTT_CLK_CTRL 0x3117 |
|---|
| 5169 | #define mmDAGB7_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 5170 | #define mmDAGB7_RD_ADDR_DAGB_MAX_BURST0 0x3118 |
|---|
| 5171 | #define mmDAGB7_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 |
|---|
| 5172 | #define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER0 0x3119 |
|---|
| 5173 | #define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 |
|---|
| 5174 | #define mmDAGB7_RD_ADDR_DAGB_MAX_BURST1 0x311a |
|---|
| 5175 | #define mmDAGB7_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 |
|---|
| 5176 | #define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER1 0x311b |
|---|
| 5177 | #define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 |
|---|
| 5178 | #define mmDAGB7_RD_VC0_CNTL 0x311c |
|---|
| 5179 | #define mmDAGB7_RD_VC0_CNTL_BASE_IDX 1 |
|---|
| 5180 | #define mmDAGB7_RD_VC1_CNTL 0x311d |
|---|
| 5181 | #define mmDAGB7_RD_VC1_CNTL_BASE_IDX 1 |
|---|
| 5182 | #define mmDAGB7_RD_VC2_CNTL 0x311e |
|---|
| 5183 | #define mmDAGB7_RD_VC2_CNTL_BASE_IDX 1 |
|---|
| 5184 | #define mmDAGB7_RD_VC3_CNTL 0x311f |
|---|
| 5185 | #define mmDAGB7_RD_VC3_CNTL_BASE_IDX 1 |
|---|
| 5186 | #define mmDAGB7_RD_VC4_CNTL 0x3120 |
|---|
| 5187 | #define mmDAGB7_RD_VC4_CNTL_BASE_IDX 1 |
|---|
| 5188 | #define mmDAGB7_RD_VC5_CNTL 0x3121 |
|---|
| 5189 | #define mmDAGB7_RD_VC5_CNTL_BASE_IDX 1 |
|---|
| 5190 | #define mmDAGB7_RD_VC6_CNTL 0x3122 |
|---|
| 5191 | #define mmDAGB7_RD_VC6_CNTL_BASE_IDX 1 |
|---|
| 5192 | #define mmDAGB7_RD_VC7_CNTL 0x3123 |
|---|
| 5193 | #define mmDAGB7_RD_VC7_CNTL_BASE_IDX 1 |
|---|
| 5194 | #define mmDAGB7_RD_CNTL_MISC 0x3124 |
|---|
| 5195 | #define mmDAGB7_RD_CNTL_MISC_BASE_IDX 1 |
|---|
| 5196 | #define mmDAGB7_RD_TLB_CREDIT 0x3125 |
|---|
| 5197 | #define mmDAGB7_RD_TLB_CREDIT_BASE_IDX 1 |
|---|
| 5198 | #define mmDAGB7_RDCLI_ASK_PENDING 0x3126 |
|---|
| 5199 | #define mmDAGB7_RDCLI_ASK_PENDING_BASE_IDX 1 |
|---|
| 5200 | #define mmDAGB7_RDCLI_GO_PENDING 0x3127 |
|---|
| 5201 | #define mmDAGB7_RDCLI_GO_PENDING_BASE_IDX 1 |
|---|
| 5202 | #define mmDAGB7_RDCLI_GBLSEND_PENDING 0x3128 |
|---|
| 5203 | #define mmDAGB7_RDCLI_GBLSEND_PENDING_BASE_IDX 1 |
|---|
| 5204 | #define mmDAGB7_RDCLI_TLB_PENDING 0x3129 |
|---|
| 5205 | #define mmDAGB7_RDCLI_TLB_PENDING_BASE_IDX 1 |
|---|
| 5206 | #define mmDAGB7_RDCLI_OARB_PENDING 0x312a |
|---|
| 5207 | #define mmDAGB7_RDCLI_OARB_PENDING_BASE_IDX 1 |
|---|
| 5208 | #define mmDAGB7_RDCLI_OSD_PENDING 0x312b |
|---|
| 5209 | #define mmDAGB7_RDCLI_OSD_PENDING_BASE_IDX 1 |
|---|
| 5210 | #define mmDAGB7_WRCLI0 0x312c |
|---|
| 5211 | #define mmDAGB7_WRCLI0_BASE_IDX 1 |
|---|
| 5212 | #define mmDAGB7_WRCLI1 0x312d |
|---|
| 5213 | #define mmDAGB7_WRCLI1_BASE_IDX 1 |
|---|
| 5214 | #define mmDAGB7_WRCLI2 0x312e |
|---|
| 5215 | #define mmDAGB7_WRCLI2_BASE_IDX 1 |
|---|
| 5216 | #define mmDAGB7_WRCLI3 0x312f |
|---|
| 5217 | #define mmDAGB7_WRCLI3_BASE_IDX 1 |
|---|
| 5218 | #define mmDAGB7_WRCLI4 0x3130 |
|---|
| 5219 | #define mmDAGB7_WRCLI4_BASE_IDX 1 |
|---|
| 5220 | #define mmDAGB7_WRCLI5 0x3131 |
|---|
| 5221 | #define mmDAGB7_WRCLI5_BASE_IDX 1 |
|---|
| 5222 | #define mmDAGB7_WRCLI6 0x3132 |
|---|
| 5223 | #define mmDAGB7_WRCLI6_BASE_IDX 1 |
|---|
| 5224 | #define mmDAGB7_WRCLI7 0x3133 |
|---|
| 5225 | #define mmDAGB7_WRCLI7_BASE_IDX 1 |
|---|
| 5226 | #define mmDAGB7_WRCLI8 0x3134 |
|---|
| 5227 | #define mmDAGB7_WRCLI8_BASE_IDX 1 |
|---|
| 5228 | #define mmDAGB7_WRCLI9 0x3135 |
|---|
| 5229 | #define mmDAGB7_WRCLI9_BASE_IDX 1 |
|---|
| 5230 | #define mmDAGB7_WRCLI10 0x3136 |
|---|
| 5231 | #define mmDAGB7_WRCLI10_BASE_IDX 1 |
|---|
| 5232 | #define mmDAGB7_WRCLI11 0x3137 |
|---|
| 5233 | #define mmDAGB7_WRCLI11_BASE_IDX 1 |
|---|
| 5234 | #define mmDAGB7_WRCLI12 0x3138 |
|---|
| 5235 | #define mmDAGB7_WRCLI12_BASE_IDX 1 |
|---|
| 5236 | #define mmDAGB7_WRCLI13 0x3139 |
|---|
| 5237 | #define mmDAGB7_WRCLI13_BASE_IDX 1 |
|---|
| 5238 | #define mmDAGB7_WRCLI14 0x313a |
|---|
| 5239 | #define mmDAGB7_WRCLI14_BASE_IDX 1 |
|---|
| 5240 | #define mmDAGB7_WRCLI15 0x313b |
|---|
| 5241 | #define mmDAGB7_WRCLI15_BASE_IDX 1 |
|---|
| 5242 | #define mmDAGB7_WR_CNTL 0x313c |
|---|
| 5243 | #define mmDAGB7_WR_CNTL_BASE_IDX 1 |
|---|
| 5244 | #define mmDAGB7_WR_GMI_CNTL 0x313d |
|---|
| 5245 | #define mmDAGB7_WR_GMI_CNTL_BASE_IDX 1 |
|---|
| 5246 | #define mmDAGB7_WR_ADDR_DAGB 0x313e |
|---|
| 5247 | #define mmDAGB7_WR_ADDR_DAGB_BASE_IDX 1 |
|---|
| 5248 | #define mmDAGB7_WR_OUTPUT_DAGB_MAX_BURST 0x313f |
|---|
| 5249 | #define mmDAGB7_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 |
|---|
| 5250 | #define mmDAGB7_WR_OUTPUT_DAGB_LAZY_TIMER 0x3140 |
|---|
| 5251 | #define mmDAGB7_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 |
|---|
| 5252 | #define mmDAGB7_WR_CGTT_CLK_CTRL 0x3141 |
|---|
| 5253 | #define mmDAGB7_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 5254 | #define mmDAGB7_L1TLB_WR_CGTT_CLK_CTRL 0x3142 |
|---|
| 5255 | #define mmDAGB7_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 5256 | #define mmDAGB7_ATCVM_WR_CGTT_CLK_CTRL 0x3143 |
|---|
| 5257 | #define mmDAGB7_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 5258 | #define mmDAGB7_WR_ADDR_DAGB_MAX_BURST0 0x3144 |
|---|
| 5259 | #define mmDAGB7_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 |
|---|
| 5260 | #define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER0 0x3145 |
|---|
| 5261 | #define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 |
|---|
| 5262 | #define mmDAGB7_WR_ADDR_DAGB_MAX_BURST1 0x3146 |
|---|
| 5263 | #define mmDAGB7_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 |
|---|
| 5264 | #define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER1 0x3147 |
|---|
| 5265 | #define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 |
|---|
| 5266 | #define mmDAGB7_WR_DATA_DAGB 0x3148 |
|---|
| 5267 | #define mmDAGB7_WR_DATA_DAGB_BASE_IDX 1 |
|---|
| 5268 | #define mmDAGB7_WR_DATA_DAGB_MAX_BURST0 0x3149 |
|---|
| 5269 | #define mmDAGB7_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 |
|---|
| 5270 | #define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER0 0x314a |
|---|
| 5271 | #define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 |
|---|
| 5272 | #define mmDAGB7_WR_DATA_DAGB_MAX_BURST1 0x314b |
|---|
| 5273 | #define mmDAGB7_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 |
|---|
| 5274 | #define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER1 0x314c |
|---|
| 5275 | #define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 |
|---|
| 5276 | #define mmDAGB7_WR_VC0_CNTL 0x314d |
|---|
| 5277 | #define mmDAGB7_WR_VC0_CNTL_BASE_IDX 1 |
|---|
| 5278 | #define mmDAGB7_WR_VC1_CNTL 0x314e |
|---|
| 5279 | #define mmDAGB7_WR_VC1_CNTL_BASE_IDX 1 |
|---|
| 5280 | #define mmDAGB7_WR_VC2_CNTL 0x314f |
|---|
| 5281 | #define mmDAGB7_WR_VC2_CNTL_BASE_IDX 1 |
|---|
| 5282 | #define mmDAGB7_WR_VC3_CNTL 0x3150 |
|---|
| 5283 | #define mmDAGB7_WR_VC3_CNTL_BASE_IDX 1 |
|---|
| 5284 | #define mmDAGB7_WR_VC4_CNTL 0x3151 |
|---|
| 5285 | #define mmDAGB7_WR_VC4_CNTL_BASE_IDX 1 |
|---|
| 5286 | #define mmDAGB7_WR_VC5_CNTL 0x3152 |
|---|
| 5287 | #define mmDAGB7_WR_VC5_CNTL_BASE_IDX 1 |
|---|
| 5288 | #define mmDAGB7_WR_VC6_CNTL 0x3153 |
|---|
| 5289 | #define mmDAGB7_WR_VC6_CNTL_BASE_IDX 1 |
|---|
| 5290 | #define mmDAGB7_WR_VC7_CNTL 0x3154 |
|---|
| 5291 | #define mmDAGB7_WR_VC7_CNTL_BASE_IDX 1 |
|---|
| 5292 | #define mmDAGB7_WR_CNTL_MISC 0x3155 |
|---|
| 5293 | #define mmDAGB7_WR_CNTL_MISC_BASE_IDX 1 |
|---|
| 5294 | #define mmDAGB7_WR_TLB_CREDIT 0x3156 |
|---|
| 5295 | #define mmDAGB7_WR_TLB_CREDIT_BASE_IDX 1 |
|---|
| 5296 | #define mmDAGB7_WR_DATA_CREDIT 0x3157 |
|---|
| 5297 | #define mmDAGB7_WR_DATA_CREDIT_BASE_IDX 1 |
|---|
| 5298 | #define mmDAGB7_WR_MISC_CREDIT 0x3158 |
|---|
| 5299 | #define mmDAGB7_WR_MISC_CREDIT_BASE_IDX 1 |
|---|
| 5300 | #define mmDAGB7_WRCLI_ASK_PENDING 0x315d |
|---|
| 5301 | #define mmDAGB7_WRCLI_ASK_PENDING_BASE_IDX 1 |
|---|
| 5302 | #define mmDAGB7_WRCLI_GO_PENDING 0x315e |
|---|
| 5303 | #define mmDAGB7_WRCLI_GO_PENDING_BASE_IDX 1 |
|---|
| 5304 | #define mmDAGB7_WRCLI_GBLSEND_PENDING 0x315f |
|---|
| 5305 | #define mmDAGB7_WRCLI_GBLSEND_PENDING_BASE_IDX 1 |
|---|
| 5306 | #define mmDAGB7_WRCLI_TLB_PENDING 0x3160 |
|---|
| 5307 | #define mmDAGB7_WRCLI_TLB_PENDING_BASE_IDX 1 |
|---|
| 5308 | #define mmDAGB7_WRCLI_OARB_PENDING 0x3161 |
|---|
| 5309 | #define mmDAGB7_WRCLI_OARB_PENDING_BASE_IDX 1 |
|---|
| 5310 | #define mmDAGB7_WRCLI_OSD_PENDING 0x3162 |
|---|
| 5311 | #define mmDAGB7_WRCLI_OSD_PENDING_BASE_IDX 1 |
|---|
| 5312 | #define mmDAGB7_WRCLI_DBUS_ASK_PENDING 0x3163 |
|---|
| 5313 | #define mmDAGB7_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 |
|---|
| 5314 | #define mmDAGB7_WRCLI_DBUS_GO_PENDING 0x3164 |
|---|
| 5315 | #define mmDAGB7_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 |
|---|
| 5316 | #define mmDAGB7_DAGB_DLY 0x3165 |
|---|
| 5317 | #define mmDAGB7_DAGB_DLY_BASE_IDX 1 |
|---|
| 5318 | #define mmDAGB7_CNTL_MISC 0x3166 |
|---|
| 5319 | #define mmDAGB7_CNTL_MISC_BASE_IDX 1 |
|---|
| 5320 | #define mmDAGB7_CNTL_MISC2 0x3167 |
|---|
| 5321 | #define mmDAGB7_CNTL_MISC2_BASE_IDX 1 |
|---|
| 5322 | #define mmDAGB7_FIFO_EMPTY 0x3168 |
|---|
| 5323 | #define mmDAGB7_FIFO_EMPTY_BASE_IDX 1 |
|---|
| 5324 | #define mmDAGB7_FIFO_FULL 0x3169 |
|---|
| 5325 | #define mmDAGB7_FIFO_FULL_BASE_IDX 1 |
|---|
| 5326 | #define mmDAGB7_WR_CREDITS_FULL 0x316a |
|---|
| 5327 | #define mmDAGB7_WR_CREDITS_FULL_BASE_IDX 1 |
|---|
| 5328 | #define mmDAGB7_RD_CREDITS_FULL 0x316b |
|---|
| 5329 | #define mmDAGB7_RD_CREDITS_FULL_BASE_IDX 1 |
|---|
| 5330 | #define mmDAGB7_PERFCOUNTER_LO 0x316c |
|---|
| 5331 | #define mmDAGB7_PERFCOUNTER_LO_BASE_IDX 1 |
|---|
| 5332 | #define mmDAGB7_PERFCOUNTER_HI 0x316d |
|---|
| 5333 | #define mmDAGB7_PERFCOUNTER_HI_BASE_IDX 1 |
|---|
| 5334 | #define mmDAGB7_PERFCOUNTER0_CFG 0x316e |
|---|
| 5335 | #define mmDAGB7_PERFCOUNTER0_CFG_BASE_IDX 1 |
|---|
| 5336 | #define mmDAGB7_PERFCOUNTER1_CFG 0x316f |
|---|
| 5337 | #define mmDAGB7_PERFCOUNTER1_CFG_BASE_IDX 1 |
|---|
| 5338 | #define mmDAGB7_PERFCOUNTER2_CFG 0x3170 |
|---|
| 5339 | #define mmDAGB7_PERFCOUNTER2_CFG_BASE_IDX 1 |
|---|
| 5340 | #define mmDAGB7_PERFCOUNTER_RSLT_CNTL 0x3171 |
|---|
| 5341 | #define mmDAGB7_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
|---|
| 5342 | #define mmDAGB7_RESERVE0 0x3172 |
|---|
| 5343 | #define mmDAGB7_RESERVE0_BASE_IDX 1 |
|---|
| 5344 | #define mmDAGB7_RESERVE1 0x3173 |
|---|
| 5345 | #define mmDAGB7_RESERVE1_BASE_IDX 1 |
|---|
| 5346 | #define mmDAGB7_RESERVE2 0x3174 |
|---|
| 5347 | #define mmDAGB7_RESERVE2_BASE_IDX 1 |
|---|
| 5348 | #define mmDAGB7_RESERVE3 0x3175 |
|---|
| 5349 | #define mmDAGB7_RESERVE3_BASE_IDX 1 |
|---|
| 5350 | #define mmDAGB7_RESERVE4 0x3176 |
|---|
| 5351 | #define mmDAGB7_RESERVE4_BASE_IDX 1 |
|---|
| 5352 | #define mmDAGB7_RESERVE5 0x3177 |
|---|
| 5353 | #define mmDAGB7_RESERVE5_BASE_IDX 1 |
|---|
| 5354 | #define mmDAGB7_RESERVE6 0x3178 |
|---|
| 5355 | #define mmDAGB7_RESERVE6_BASE_IDX 1 |
|---|
| 5356 | #define mmDAGB7_RESERVE7 0x3179 |
|---|
| 5357 | #define mmDAGB7_RESERVE7_BASE_IDX 1 |
|---|
| 5358 | #define mmDAGB7_RESERVE8 0x317a |
|---|
| 5359 | #define mmDAGB7_RESERVE8_BASE_IDX 1 |
|---|
| 5360 | #define mmDAGB7_RESERVE9 0x317b |
|---|
| 5361 | #define mmDAGB7_RESERVE9_BASE_IDX 1 |
|---|
| 5362 | #define mmDAGB7_RESERVE10 0x317c |
|---|
| 5363 | #define mmDAGB7_RESERVE10_BASE_IDX 1 |
|---|
| 5364 | #define mmDAGB7_RESERVE11 0x317d |
|---|
| 5365 | #define mmDAGB7_RESERVE11_BASE_IDX 1 |
|---|
| 5366 | #define mmDAGB7_RESERVE12 0x317e |
|---|
| 5367 | #define mmDAGB7_RESERVE12_BASE_IDX 1 |
|---|
| 5368 | #define mmDAGB7_RESERVE13 0x317f |
|---|
| 5369 | #define mmDAGB7_RESERVE13_BASE_IDX 1 |
|---|
| 5370 | |
|---|
| 5371 | |
|---|
| 5372 | // addressBlock: mmhub_ea_mmeadec5 |
|---|
| 5373 | // base address: 0x74a00 |
|---|
| 5374 | #define mmMMEA5_DRAM_RD_CLI2GRP_MAP0 0x3280 |
|---|
| 5375 | #define mmMMEA5_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 5376 | #define mmMMEA5_DRAM_RD_CLI2GRP_MAP1 0x3281 |
|---|
| 5377 | #define mmMMEA5_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 5378 | #define mmMMEA5_DRAM_WR_CLI2GRP_MAP0 0x3282 |
|---|
| 5379 | #define mmMMEA5_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 5380 | #define mmMMEA5_DRAM_WR_CLI2GRP_MAP1 0x3283 |
|---|
| 5381 | #define mmMMEA5_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 5382 | #define mmMMEA5_DRAM_RD_GRP2VC_MAP 0x3284 |
|---|
| 5383 | #define mmMMEA5_DRAM_RD_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 5384 | #define mmMMEA5_DRAM_WR_GRP2VC_MAP 0x3285 |
|---|
| 5385 | #define mmMMEA5_DRAM_WR_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 5386 | #define mmMMEA5_DRAM_RD_LAZY 0x3286 |
|---|
| 5387 | #define mmMMEA5_DRAM_RD_LAZY_BASE_IDX 1 |
|---|
| 5388 | #define mmMMEA5_DRAM_WR_LAZY 0x3287 |
|---|
| 5389 | #define mmMMEA5_DRAM_WR_LAZY_BASE_IDX 1 |
|---|
| 5390 | #define mmMMEA5_DRAM_RD_CAM_CNTL 0x3288 |
|---|
| 5391 | #define mmMMEA5_DRAM_RD_CAM_CNTL_BASE_IDX 1 |
|---|
| 5392 | #define mmMMEA5_DRAM_WR_CAM_CNTL 0x3289 |
|---|
| 5393 | #define mmMMEA5_DRAM_WR_CAM_CNTL_BASE_IDX 1 |
|---|
| 5394 | #define mmMMEA5_DRAM_PAGE_BURST 0x328a |
|---|
| 5395 | #define mmMMEA5_DRAM_PAGE_BURST_BASE_IDX 1 |
|---|
| 5396 | #define mmMMEA5_DRAM_RD_PRI_AGE 0x328b |
|---|
| 5397 | #define mmMMEA5_DRAM_RD_PRI_AGE_BASE_IDX 1 |
|---|
| 5398 | #define mmMMEA5_DRAM_WR_PRI_AGE 0x328c |
|---|
| 5399 | #define mmMMEA5_DRAM_WR_PRI_AGE_BASE_IDX 1 |
|---|
| 5400 | #define mmMMEA5_DRAM_RD_PRI_QUEUING 0x328d |
|---|
| 5401 | #define mmMMEA5_DRAM_RD_PRI_QUEUING_BASE_IDX 1 |
|---|
| 5402 | #define mmMMEA5_DRAM_WR_PRI_QUEUING 0x328e |
|---|
| 5403 | #define mmMMEA5_DRAM_WR_PRI_QUEUING_BASE_IDX 1 |
|---|
| 5404 | #define mmMMEA5_DRAM_RD_PRI_FIXED 0x328f |
|---|
| 5405 | #define mmMMEA5_DRAM_RD_PRI_FIXED_BASE_IDX 1 |
|---|
| 5406 | #define mmMMEA5_DRAM_WR_PRI_FIXED 0x3290 |
|---|
| 5407 | #define mmMMEA5_DRAM_WR_PRI_FIXED_BASE_IDX 1 |
|---|
| 5408 | #define mmMMEA5_DRAM_RD_PRI_URGENCY 0x3291 |
|---|
| 5409 | #define mmMMEA5_DRAM_RD_PRI_URGENCY_BASE_IDX 1 |
|---|
| 5410 | #define mmMMEA5_DRAM_WR_PRI_URGENCY 0x3292 |
|---|
| 5411 | #define mmMMEA5_DRAM_WR_PRI_URGENCY_BASE_IDX 1 |
|---|
| 5412 | #define mmMMEA5_DRAM_RD_PRI_QUANT_PRI1 0x3293 |
|---|
| 5413 | #define mmMMEA5_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 5414 | #define mmMMEA5_DRAM_RD_PRI_QUANT_PRI2 0x3294 |
|---|
| 5415 | #define mmMMEA5_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 5416 | #define mmMMEA5_DRAM_RD_PRI_QUANT_PRI3 0x3295 |
|---|
| 5417 | #define mmMMEA5_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 5418 | #define mmMMEA5_DRAM_WR_PRI_QUANT_PRI1 0x3296 |
|---|
| 5419 | #define mmMMEA5_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 5420 | #define mmMMEA5_DRAM_WR_PRI_QUANT_PRI2 0x3297 |
|---|
| 5421 | #define mmMMEA5_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 5422 | #define mmMMEA5_DRAM_WR_PRI_QUANT_PRI3 0x3298 |
|---|
| 5423 | #define mmMMEA5_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 5424 | #define mmMMEA5_GMI_RD_CLI2GRP_MAP0 0x3299 |
|---|
| 5425 | #define mmMMEA5_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 5426 | #define mmMMEA5_GMI_RD_CLI2GRP_MAP1 0x329a |
|---|
| 5427 | #define mmMMEA5_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 5428 | #define mmMMEA5_GMI_WR_CLI2GRP_MAP0 0x329b |
|---|
| 5429 | #define mmMMEA5_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 5430 | #define mmMMEA5_GMI_WR_CLI2GRP_MAP1 0x329c |
|---|
| 5431 | #define mmMMEA5_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 5432 | #define mmMMEA5_GMI_RD_GRP2VC_MAP 0x329d |
|---|
| 5433 | #define mmMMEA5_GMI_RD_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 5434 | #define mmMMEA5_GMI_WR_GRP2VC_MAP 0x329e |
|---|
| 5435 | #define mmMMEA5_GMI_WR_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 5436 | #define mmMMEA5_GMI_RD_LAZY 0x329f |
|---|
| 5437 | #define mmMMEA5_GMI_RD_LAZY_BASE_IDX 1 |
|---|
| 5438 | #define mmMMEA5_GMI_WR_LAZY 0x32a0 |
|---|
| 5439 | #define mmMMEA5_GMI_WR_LAZY_BASE_IDX 1 |
|---|
| 5440 | #define mmMMEA5_GMI_RD_CAM_CNTL 0x32a1 |
|---|
| 5441 | #define mmMMEA5_GMI_RD_CAM_CNTL_BASE_IDX 1 |
|---|
| 5442 | #define mmMMEA5_GMI_WR_CAM_CNTL 0x32a2 |
|---|
| 5443 | #define mmMMEA5_GMI_WR_CAM_CNTL_BASE_IDX 1 |
|---|
| 5444 | #define mmMMEA5_GMI_PAGE_BURST 0x32a3 |
|---|
| 5445 | #define mmMMEA5_GMI_PAGE_BURST_BASE_IDX 1 |
|---|
| 5446 | #define mmMMEA5_GMI_RD_PRI_AGE 0x32a4 |
|---|
| 5447 | #define mmMMEA5_GMI_RD_PRI_AGE_BASE_IDX 1 |
|---|
| 5448 | #define mmMMEA5_GMI_WR_PRI_AGE 0x32a5 |
|---|
| 5449 | #define mmMMEA5_GMI_WR_PRI_AGE_BASE_IDX 1 |
|---|
| 5450 | #define mmMMEA5_GMI_RD_PRI_QUEUING 0x32a6 |
|---|
| 5451 | #define mmMMEA5_GMI_RD_PRI_QUEUING_BASE_IDX 1 |
|---|
| 5452 | #define mmMMEA5_GMI_WR_PRI_QUEUING 0x32a7 |
|---|
| 5453 | #define mmMMEA5_GMI_WR_PRI_QUEUING_BASE_IDX 1 |
|---|
| 5454 | #define mmMMEA5_GMI_RD_PRI_FIXED 0x32a8 |
|---|
| 5455 | #define mmMMEA5_GMI_RD_PRI_FIXED_BASE_IDX 1 |
|---|
| 5456 | #define mmMMEA5_GMI_WR_PRI_FIXED 0x32a9 |
|---|
| 5457 | #define mmMMEA5_GMI_WR_PRI_FIXED_BASE_IDX 1 |
|---|
| 5458 | #define mmMMEA5_GMI_RD_PRI_URGENCY 0x32aa |
|---|
| 5459 | #define mmMMEA5_GMI_RD_PRI_URGENCY_BASE_IDX 1 |
|---|
| 5460 | #define mmMMEA5_GMI_WR_PRI_URGENCY 0x32ab |
|---|
| 5461 | #define mmMMEA5_GMI_WR_PRI_URGENCY_BASE_IDX 1 |
|---|
| 5462 | #define mmMMEA5_GMI_RD_PRI_URGENCY_MASKING 0x32ac |
|---|
| 5463 | #define mmMMEA5_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 5464 | #define mmMMEA5_GMI_WR_PRI_URGENCY_MASKING 0x32ad |
|---|
| 5465 | #define mmMMEA5_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 5466 | #define mmMMEA5_GMI_RD_PRI_QUANT_PRI1 0x32ae |
|---|
| 5467 | #define mmMMEA5_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 5468 | #define mmMMEA5_GMI_RD_PRI_QUANT_PRI2 0x32af |
|---|
| 5469 | #define mmMMEA5_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 5470 | #define mmMMEA5_GMI_RD_PRI_QUANT_PRI3 0x32b0 |
|---|
| 5471 | #define mmMMEA5_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 5472 | #define mmMMEA5_GMI_WR_PRI_QUANT_PRI1 0x32b1 |
|---|
| 5473 | #define mmMMEA5_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 5474 | #define mmMMEA5_GMI_WR_PRI_QUANT_PRI2 0x32b2 |
|---|
| 5475 | #define mmMMEA5_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 5476 | #define mmMMEA5_GMI_WR_PRI_QUANT_PRI3 0x32b3 |
|---|
| 5477 | #define mmMMEA5_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 5478 | #define mmMMEA5_ADDRNORM_BASE_ADDR0 0x32b4 |
|---|
| 5479 | #define mmMMEA5_ADDRNORM_BASE_ADDR0_BASE_IDX 1 |
|---|
| 5480 | #define mmMMEA5_ADDRNORM_LIMIT_ADDR0 0x32b5 |
|---|
| 5481 | #define mmMMEA5_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1 |
|---|
| 5482 | #define mmMMEA5_ADDRNORM_BASE_ADDR1 0x32b6 |
|---|
| 5483 | #define mmMMEA5_ADDRNORM_BASE_ADDR1_BASE_IDX 1 |
|---|
| 5484 | #define mmMMEA5_ADDRNORM_LIMIT_ADDR1 0x32b7 |
|---|
| 5485 | #define mmMMEA5_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1 |
|---|
| 5486 | #define mmMMEA5_ADDRNORM_OFFSET_ADDR1 0x32b8 |
|---|
| 5487 | #define mmMMEA5_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1 |
|---|
| 5488 | #define mmMMEA5_ADDRNORM_BASE_ADDR2 0x32b9 |
|---|
| 5489 | #define mmMMEA5_ADDRNORM_BASE_ADDR2_BASE_IDX 1 |
|---|
| 5490 | #define mmMMEA5_ADDRNORM_LIMIT_ADDR2 0x32ba |
|---|
| 5491 | #define mmMMEA5_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1 |
|---|
| 5492 | #define mmMMEA5_ADDRNORM_BASE_ADDR3 0x32bb |
|---|
| 5493 | #define mmMMEA5_ADDRNORM_BASE_ADDR3_BASE_IDX 1 |
|---|
| 5494 | #define mmMMEA5_ADDRNORM_LIMIT_ADDR3 0x32bc |
|---|
| 5495 | #define mmMMEA5_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1 |
|---|
| 5496 | #define mmMMEA5_ADDRNORM_OFFSET_ADDR3 0x32bd |
|---|
| 5497 | #define mmMMEA5_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1 |
|---|
| 5498 | #define mmMMEA5_ADDRNORM_BASE_ADDR4 0x32be |
|---|
| 5499 | #define mmMMEA5_ADDRNORM_BASE_ADDR4_BASE_IDX 1 |
|---|
| 5500 | #define mmMMEA5_ADDRNORM_LIMIT_ADDR4 0x32bf |
|---|
| 5501 | #define mmMMEA5_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1 |
|---|
| 5502 | #define mmMMEA5_ADDRNORM_BASE_ADDR5 0x32c0 |
|---|
| 5503 | #define mmMMEA5_ADDRNORM_BASE_ADDR5_BASE_IDX 1 |
|---|
| 5504 | #define mmMMEA5_ADDRNORM_LIMIT_ADDR5 0x32c1 |
|---|
| 5505 | #define mmMMEA5_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1 |
|---|
| 5506 | #define mmMMEA5_ADDRNORM_OFFSET_ADDR5 0x32c2 |
|---|
| 5507 | #define mmMMEA5_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1 |
|---|
| 5508 | #define mmMMEA5_ADDRNORMDRAM_HOLE_CNTL 0x32c3 |
|---|
| 5509 | #define mmMMEA5_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1 |
|---|
| 5510 | #define mmMMEA5_ADDRNORMGMI_HOLE_CNTL 0x32c4 |
|---|
| 5511 | #define mmMMEA5_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1 |
|---|
| 5512 | #define mmMMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x32c5 |
|---|
| 5513 | #define mmMMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1 |
|---|
| 5514 | #define mmMMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG 0x32c6 |
|---|
| 5515 | #define mmMMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1 |
|---|
| 5516 | #define mmMMEA5_ADDRDEC_BANK_CFG 0x32c7 |
|---|
| 5517 | #define mmMMEA5_ADDRDEC_BANK_CFG_BASE_IDX 1 |
|---|
| 5518 | #define mmMMEA5_ADDRDEC_MISC_CFG 0x32c8 |
|---|
| 5519 | #define mmMMEA5_ADDRDEC_MISC_CFG_BASE_IDX 1 |
|---|
| 5520 | #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK0 0x32c9 |
|---|
| 5521 | #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1 |
|---|
| 5522 | #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK1 0x32ca |
|---|
| 5523 | #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1 |
|---|
| 5524 | #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK2 0x32cb |
|---|
| 5525 | #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1 |
|---|
| 5526 | #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK3 0x32cc |
|---|
| 5527 | #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1 |
|---|
| 5528 | #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK4 0x32cd |
|---|
| 5529 | #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1 |
|---|
| 5530 | #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK5 0x32ce |
|---|
| 5531 | #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1 |
|---|
| 5532 | #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC 0x32cf |
|---|
| 5533 | #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1 |
|---|
| 5534 | #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC2 0x32d0 |
|---|
| 5535 | #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1 |
|---|
| 5536 | #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS0 0x32d1 |
|---|
| 5537 | #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1 |
|---|
| 5538 | #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS1 0x32d2 |
|---|
| 5539 | #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1 |
|---|
| 5540 | #define mmMMEA5_ADDRDECDRAM_HARVEST_ENABLE 0x32d3 |
|---|
| 5541 | #define mmMMEA5_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1 |
|---|
| 5542 | #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK0 0x32d4 |
|---|
| 5543 | #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1 |
|---|
| 5544 | #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK1 0x32d5 |
|---|
| 5545 | #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1 |
|---|
| 5546 | #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK2 0x32d6 |
|---|
| 5547 | #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1 |
|---|
| 5548 | #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK3 0x32d7 |
|---|
| 5549 | #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1 |
|---|
| 5550 | #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK4 0x32d8 |
|---|
| 5551 | #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1 |
|---|
| 5552 | #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK5 0x32d9 |
|---|
| 5553 | #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1 |
|---|
| 5554 | #define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC 0x32da |
|---|
| 5555 | #define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1 |
|---|
| 5556 | #define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC2 0x32db |
|---|
| 5557 | #define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1 |
|---|
| 5558 | #define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS0 0x32dc |
|---|
| 5559 | #define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1 |
|---|
| 5560 | #define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS1 0x32dd |
|---|
| 5561 | #define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1 |
|---|
| 5562 | #define mmMMEA5_ADDRDECGMI_HARVEST_ENABLE 0x32de |
|---|
| 5563 | #define mmMMEA5_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1 |
|---|
| 5564 | #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS0 0x32df |
|---|
| 5565 | #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1 |
|---|
| 5566 | #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS1 0x32e0 |
|---|
| 5567 | #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1 |
|---|
| 5568 | #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS2 0x32e1 |
|---|
| 5569 | #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1 |
|---|
| 5570 | #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS3 0x32e2 |
|---|
| 5571 | #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1 |
|---|
| 5572 | #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS0 0x32e3 |
|---|
| 5573 | #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1 |
|---|
| 5574 | #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS1 0x32e4 |
|---|
| 5575 | #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1 |
|---|
| 5576 | #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS2 0x32e5 |
|---|
| 5577 | #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1 |
|---|
| 5578 | #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS3 0x32e6 |
|---|
| 5579 | #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1 |
|---|
| 5580 | #define mmMMEA5_ADDRDEC0_ADDR_MASK_CS01 0x32e7 |
|---|
| 5581 | #define mmMMEA5_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1 |
|---|
| 5582 | #define mmMMEA5_ADDRDEC0_ADDR_MASK_CS23 0x32e8 |
|---|
| 5583 | #define mmMMEA5_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1 |
|---|
| 5584 | #define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS01 0x32e9 |
|---|
| 5585 | #define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1 |
|---|
| 5586 | #define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS23 0x32ea |
|---|
| 5587 | #define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1 |
|---|
| 5588 | #define mmMMEA5_ADDRDEC0_ADDR_CFG_CS01 0x32eb |
|---|
| 5589 | #define mmMMEA5_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1 |
|---|
| 5590 | #define mmMMEA5_ADDRDEC0_ADDR_CFG_CS23 0x32ec |
|---|
| 5591 | #define mmMMEA5_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1 |
|---|
| 5592 | #define mmMMEA5_ADDRDEC0_ADDR_SEL_CS01 0x32ed |
|---|
| 5593 | #define mmMMEA5_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1 |
|---|
| 5594 | #define mmMMEA5_ADDRDEC0_ADDR_SEL_CS23 0x32ee |
|---|
| 5595 | #define mmMMEA5_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1 |
|---|
| 5596 | #define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS01 0x32ef |
|---|
| 5597 | #define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1 |
|---|
| 5598 | #define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS23 0x32f0 |
|---|
| 5599 | #define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1 |
|---|
| 5600 | #define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS01 0x32f1 |
|---|
| 5601 | #define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1 |
|---|
| 5602 | #define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS23 0x32f2 |
|---|
| 5603 | #define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1 |
|---|
| 5604 | #define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS01 0x32f3 |
|---|
| 5605 | #define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1 |
|---|
| 5606 | #define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS23 0x32f4 |
|---|
| 5607 | #define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1 |
|---|
| 5608 | #define mmMMEA5_ADDRDEC0_RM_SEL_CS01 0x32f5 |
|---|
| 5609 | #define mmMMEA5_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1 |
|---|
| 5610 | #define mmMMEA5_ADDRDEC0_RM_SEL_CS23 0x32f6 |
|---|
| 5611 | #define mmMMEA5_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1 |
|---|
| 5612 | #define mmMMEA5_ADDRDEC0_RM_SEL_SECCS01 0x32f7 |
|---|
| 5613 | #define mmMMEA5_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1 |
|---|
| 5614 | #define mmMMEA5_ADDRDEC0_RM_SEL_SECCS23 0x32f8 |
|---|
| 5615 | #define mmMMEA5_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1 |
|---|
| 5616 | #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS0 0x32f9 |
|---|
| 5617 | #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1 |
|---|
| 5618 | #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS1 0x32fa |
|---|
| 5619 | #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1 |
|---|
| 5620 | #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS2 0x32fb |
|---|
| 5621 | #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1 |
|---|
| 5622 | #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS3 0x32fc |
|---|
| 5623 | #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1 |
|---|
| 5624 | #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS0 0x32fd |
|---|
| 5625 | #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1 |
|---|
| 5626 | #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS1 0x32fe |
|---|
| 5627 | #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1 |
|---|
| 5628 | #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS2 0x32ff |
|---|
| 5629 | #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1 |
|---|
| 5630 | #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS3 0x3300 |
|---|
| 5631 | #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1 |
|---|
| 5632 | #define mmMMEA5_ADDRDEC1_ADDR_MASK_CS01 0x3301 |
|---|
| 5633 | #define mmMMEA5_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1 |
|---|
| 5634 | #define mmMMEA5_ADDRDEC1_ADDR_MASK_CS23 0x3302 |
|---|
| 5635 | #define mmMMEA5_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1 |
|---|
| 5636 | #define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS01 0x3303 |
|---|
| 5637 | #define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1 |
|---|
| 5638 | #define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS23 0x3304 |
|---|
| 5639 | #define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1 |
|---|
| 5640 | #define mmMMEA5_ADDRDEC1_ADDR_CFG_CS01 0x3305 |
|---|
| 5641 | #define mmMMEA5_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1 |
|---|
| 5642 | #define mmMMEA5_ADDRDEC1_ADDR_CFG_CS23 0x3306 |
|---|
| 5643 | #define mmMMEA5_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1 |
|---|
| 5644 | #define mmMMEA5_ADDRDEC1_ADDR_SEL_CS01 0x3307 |
|---|
| 5645 | #define mmMMEA5_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1 |
|---|
| 5646 | #define mmMMEA5_ADDRDEC1_ADDR_SEL_CS23 0x3308 |
|---|
| 5647 | #define mmMMEA5_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1 |
|---|
| 5648 | #define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS01 0x3309 |
|---|
| 5649 | #define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1 |
|---|
| 5650 | #define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS23 0x330a |
|---|
| 5651 | #define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1 |
|---|
| 5652 | #define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS01 0x330b |
|---|
| 5653 | #define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1 |
|---|
| 5654 | #define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS23 0x330c |
|---|
| 5655 | #define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1 |
|---|
| 5656 | #define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS01 0x330d |
|---|
| 5657 | #define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1 |
|---|
| 5658 | #define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS23 0x330e |
|---|
| 5659 | #define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1 |
|---|
| 5660 | #define mmMMEA5_ADDRDEC1_RM_SEL_CS01 0x330f |
|---|
| 5661 | #define mmMMEA5_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1 |
|---|
| 5662 | #define mmMMEA5_ADDRDEC1_RM_SEL_CS23 0x3310 |
|---|
| 5663 | #define mmMMEA5_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1 |
|---|
| 5664 | #define mmMMEA5_ADDRDEC1_RM_SEL_SECCS01 0x3311 |
|---|
| 5665 | #define mmMMEA5_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1 |
|---|
| 5666 | #define mmMMEA5_ADDRDEC1_RM_SEL_SECCS23 0x3312 |
|---|
| 5667 | #define mmMMEA5_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1 |
|---|
| 5668 | #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS0 0x3313 |
|---|
| 5669 | #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1 |
|---|
| 5670 | #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS1 0x3314 |
|---|
| 5671 | #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1 |
|---|
| 5672 | #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS2 0x3315 |
|---|
| 5673 | #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1 |
|---|
| 5674 | #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS3 0x3316 |
|---|
| 5675 | #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1 |
|---|
| 5676 | #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS0 0x3317 |
|---|
| 5677 | #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1 |
|---|
| 5678 | #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS1 0x3318 |
|---|
| 5679 | #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1 |
|---|
| 5680 | #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS2 0x3319 |
|---|
| 5681 | #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1 |
|---|
| 5682 | #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS3 0x331a |
|---|
| 5683 | #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1 |
|---|
| 5684 | #define mmMMEA5_ADDRDEC2_ADDR_MASK_CS01 0x331b |
|---|
| 5685 | #define mmMMEA5_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1 |
|---|
| 5686 | #define mmMMEA5_ADDRDEC2_ADDR_MASK_CS23 0x331c |
|---|
| 5687 | #define mmMMEA5_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1 |
|---|
| 5688 | #define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS01 0x331d |
|---|
| 5689 | #define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1 |
|---|
| 5690 | #define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS23 0x331e |
|---|
| 5691 | #define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1 |
|---|
| 5692 | #define mmMMEA5_ADDRDEC2_ADDR_CFG_CS01 0x331f |
|---|
| 5693 | #define mmMMEA5_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1 |
|---|
| 5694 | #define mmMMEA5_ADDRDEC2_ADDR_CFG_CS23 0x3320 |
|---|
| 5695 | #define mmMMEA5_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1 |
|---|
| 5696 | #define mmMMEA5_ADDRDEC2_ADDR_SEL_CS01 0x3321 |
|---|
| 5697 | #define mmMMEA5_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1 |
|---|
| 5698 | #define mmMMEA5_ADDRDEC2_ADDR_SEL_CS23 0x3322 |
|---|
| 5699 | #define mmMMEA5_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1 |
|---|
| 5700 | #define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS01 0x3323 |
|---|
| 5701 | #define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1 |
|---|
| 5702 | #define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS23 0x3324 |
|---|
| 5703 | #define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1 |
|---|
| 5704 | #define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS01 0x3325 |
|---|
| 5705 | #define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1 |
|---|
| 5706 | #define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS23 0x3326 |
|---|
| 5707 | #define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1 |
|---|
| 5708 | #define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS01 0x3327 |
|---|
| 5709 | #define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1 |
|---|
| 5710 | #define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS23 0x3328 |
|---|
| 5711 | #define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1 |
|---|
| 5712 | #define mmMMEA5_ADDRDEC2_RM_SEL_CS01 0x3329 |
|---|
| 5713 | #define mmMMEA5_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1 |
|---|
| 5714 | #define mmMMEA5_ADDRDEC2_RM_SEL_CS23 0x332a |
|---|
| 5715 | #define mmMMEA5_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1 |
|---|
| 5716 | #define mmMMEA5_ADDRDEC2_RM_SEL_SECCS01 0x332b |
|---|
| 5717 | #define mmMMEA5_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1 |
|---|
| 5718 | #define mmMMEA5_ADDRDEC2_RM_SEL_SECCS23 0x332c |
|---|
| 5719 | #define mmMMEA5_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1 |
|---|
| 5720 | #define mmMMEA5_ADDRNORMDRAM_GLOBAL_CNTL 0x332d |
|---|
| 5721 | #define mmMMEA5_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1 |
|---|
| 5722 | #define mmMMEA5_ADDRNORMGMI_GLOBAL_CNTL 0x332e |
|---|
| 5723 | #define mmMMEA5_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1 |
|---|
| 5724 | #define mmMMEA5_IO_RD_CLI2GRP_MAP0 0x3355 |
|---|
| 5725 | #define mmMMEA5_IO_RD_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 5726 | #define mmMMEA5_IO_RD_CLI2GRP_MAP1 0x3356 |
|---|
| 5727 | #define mmMMEA5_IO_RD_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 5728 | #define mmMMEA5_IO_WR_CLI2GRP_MAP0 0x3357 |
|---|
| 5729 | #define mmMMEA5_IO_WR_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 5730 | #define mmMMEA5_IO_WR_CLI2GRP_MAP1 0x3358 |
|---|
| 5731 | #define mmMMEA5_IO_WR_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 5732 | #define mmMMEA5_IO_RD_COMBINE_FLUSH 0x3359 |
|---|
| 5733 | #define mmMMEA5_IO_RD_COMBINE_FLUSH_BASE_IDX 1 |
|---|
| 5734 | #define mmMMEA5_IO_WR_COMBINE_FLUSH 0x335a |
|---|
| 5735 | #define mmMMEA5_IO_WR_COMBINE_FLUSH_BASE_IDX 1 |
|---|
| 5736 | #define mmMMEA5_IO_GROUP_BURST 0x335b |
|---|
| 5737 | #define mmMMEA5_IO_GROUP_BURST_BASE_IDX 1 |
|---|
| 5738 | #define mmMMEA5_IO_RD_PRI_AGE 0x335c |
|---|
| 5739 | #define mmMMEA5_IO_RD_PRI_AGE_BASE_IDX 1 |
|---|
| 5740 | #define mmMMEA5_IO_WR_PRI_AGE 0x335d |
|---|
| 5741 | #define mmMMEA5_IO_WR_PRI_AGE_BASE_IDX 1 |
|---|
| 5742 | #define mmMMEA5_IO_RD_PRI_QUEUING 0x335e |
|---|
| 5743 | #define mmMMEA5_IO_RD_PRI_QUEUING_BASE_IDX 1 |
|---|
| 5744 | #define mmMMEA5_IO_WR_PRI_QUEUING 0x335f |
|---|
| 5745 | #define mmMMEA5_IO_WR_PRI_QUEUING_BASE_IDX 1 |
|---|
| 5746 | #define mmMMEA5_IO_RD_PRI_FIXED 0x3360 |
|---|
| 5747 | #define mmMMEA5_IO_RD_PRI_FIXED_BASE_IDX 1 |
|---|
| 5748 | #define mmMMEA5_IO_WR_PRI_FIXED 0x3361 |
|---|
| 5749 | #define mmMMEA5_IO_WR_PRI_FIXED_BASE_IDX 1 |
|---|
| 5750 | #define mmMMEA5_IO_RD_PRI_URGENCY 0x3362 |
|---|
| 5751 | #define mmMMEA5_IO_RD_PRI_URGENCY_BASE_IDX 1 |
|---|
| 5752 | #define mmMMEA5_IO_WR_PRI_URGENCY 0x3363 |
|---|
| 5753 | #define mmMMEA5_IO_WR_PRI_URGENCY_BASE_IDX 1 |
|---|
| 5754 | #define mmMMEA5_IO_RD_PRI_URGENCY_MASKING 0x3364 |
|---|
| 5755 | #define mmMMEA5_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 5756 | #define mmMMEA5_IO_WR_PRI_URGENCY_MASKING 0x3365 |
|---|
| 5757 | #define mmMMEA5_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 5758 | #define mmMMEA5_IO_RD_PRI_QUANT_PRI1 0x3366 |
|---|
| 5759 | #define mmMMEA5_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 5760 | #define mmMMEA5_IO_RD_PRI_QUANT_PRI2 0x3367 |
|---|
| 5761 | #define mmMMEA5_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 5762 | #define mmMMEA5_IO_RD_PRI_QUANT_PRI3 0x3368 |
|---|
| 5763 | #define mmMMEA5_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 5764 | #define mmMMEA5_IO_WR_PRI_QUANT_PRI1 0x3369 |
|---|
| 5765 | #define mmMMEA5_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 5766 | #define mmMMEA5_IO_WR_PRI_QUANT_PRI2 0x336a |
|---|
| 5767 | #define mmMMEA5_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 5768 | #define mmMMEA5_IO_WR_PRI_QUANT_PRI3 0x336b |
|---|
| 5769 | #define mmMMEA5_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 5770 | #define mmMMEA5_SDP_ARB_DRAM 0x336c |
|---|
| 5771 | #define mmMMEA5_SDP_ARB_DRAM_BASE_IDX 1 |
|---|
| 5772 | #define mmMMEA5_SDP_ARB_GMI 0x336d |
|---|
| 5773 | #define mmMMEA5_SDP_ARB_GMI_BASE_IDX 1 |
|---|
| 5774 | #define mmMMEA5_SDP_ARB_FINAL 0x336e |
|---|
| 5775 | #define mmMMEA5_SDP_ARB_FINAL_BASE_IDX 1 |
|---|
| 5776 | #define mmMMEA5_SDP_DRAM_PRIORITY 0x336f |
|---|
| 5777 | #define mmMMEA5_SDP_DRAM_PRIORITY_BASE_IDX 1 |
|---|
| 5778 | #define mmMMEA5_SDP_GMI_PRIORITY 0x3370 |
|---|
| 5779 | #define mmMMEA5_SDP_GMI_PRIORITY_BASE_IDX 1 |
|---|
| 5780 | #define mmMMEA5_SDP_IO_PRIORITY 0x3371 |
|---|
| 5781 | #define mmMMEA5_SDP_IO_PRIORITY_BASE_IDX 1 |
|---|
| 5782 | #define mmMMEA5_SDP_CREDITS 0x3372 |
|---|
| 5783 | #define mmMMEA5_SDP_CREDITS_BASE_IDX 1 |
|---|
| 5784 | #define mmMMEA5_SDP_TAG_RESERVE0 0x3373 |
|---|
| 5785 | #define mmMMEA5_SDP_TAG_RESERVE0_BASE_IDX 1 |
|---|
| 5786 | #define mmMMEA5_SDP_TAG_RESERVE1 0x3374 |
|---|
| 5787 | #define mmMMEA5_SDP_TAG_RESERVE1_BASE_IDX 1 |
|---|
| 5788 | #define mmMMEA5_SDP_VCC_RESERVE0 0x3375 |
|---|
| 5789 | #define mmMMEA5_SDP_VCC_RESERVE0_BASE_IDX 1 |
|---|
| 5790 | #define mmMMEA5_SDP_VCC_RESERVE1 0x3376 |
|---|
| 5791 | #define mmMMEA5_SDP_VCC_RESERVE1_BASE_IDX 1 |
|---|
| 5792 | #define mmMMEA5_SDP_VCD_RESERVE0 0x3377 |
|---|
| 5793 | #define mmMMEA5_SDP_VCD_RESERVE0_BASE_IDX 1 |
|---|
| 5794 | #define mmMMEA5_SDP_VCD_RESERVE1 0x3378 |
|---|
| 5795 | #define mmMMEA5_SDP_VCD_RESERVE1_BASE_IDX 1 |
|---|
| 5796 | #define mmMMEA5_SDP_REQ_CNTL 0x3379 |
|---|
| 5797 | #define mmMMEA5_SDP_REQ_CNTL_BASE_IDX 1 |
|---|
| 5798 | #define mmMMEA5_MISC 0x337a |
|---|
| 5799 | #define mmMMEA5_MISC_BASE_IDX 1 |
|---|
| 5800 | #define mmMMEA5_LATENCY_SAMPLING 0x337b |
|---|
| 5801 | #define mmMMEA5_LATENCY_SAMPLING_BASE_IDX 1 |
|---|
| 5802 | #define mmMMEA5_PERFCOUNTER_LO 0x337c |
|---|
| 5803 | #define mmMMEA5_PERFCOUNTER_LO_BASE_IDX 1 |
|---|
| 5804 | #define mmMMEA5_PERFCOUNTER_HI 0x337d |
|---|
| 5805 | #define mmMMEA5_PERFCOUNTER_HI_BASE_IDX 1 |
|---|
| 5806 | #define mmMMEA5_PERFCOUNTER0_CFG 0x337e |
|---|
| 5807 | #define mmMMEA5_PERFCOUNTER0_CFG_BASE_IDX 1 |
|---|
| 5808 | #define mmMMEA5_PERFCOUNTER1_CFG 0x337f |
|---|
| 5809 | #define mmMMEA5_PERFCOUNTER1_CFG_BASE_IDX 1 |
|---|
| 5810 | #define mmMMEA5_PERFCOUNTER_RSLT_CNTL 0x3380 |
|---|
| 5811 | #define mmMMEA5_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
|---|
| 5812 | #define mmMMEA5_EDC_CNT 0x3386 |
|---|
| 5813 | #define mmMMEA5_EDC_CNT_BASE_IDX 1 |
|---|
| 5814 | #define mmMMEA5_EDC_CNT2 0x3387 |
|---|
| 5815 | #define mmMMEA5_EDC_CNT2_BASE_IDX 1 |
|---|
| 5816 | #define mmMMEA5_DSM_CNTL 0x3388 |
|---|
| 5817 | #define mmMMEA5_DSM_CNTL_BASE_IDX 1 |
|---|
| 5818 | #define mmMMEA5_DSM_CNTLA 0x3389 |
|---|
| 5819 | #define mmMMEA5_DSM_CNTLA_BASE_IDX 1 |
|---|
| 5820 | #define mmMMEA5_DSM_CNTLB 0x338a |
|---|
| 5821 | #define mmMMEA5_DSM_CNTLB_BASE_IDX 1 |
|---|
| 5822 | #define mmMMEA5_DSM_CNTL2 0x338b |
|---|
| 5823 | #define mmMMEA5_DSM_CNTL2_BASE_IDX 1 |
|---|
| 5824 | #define mmMMEA5_DSM_CNTL2A 0x338c |
|---|
| 5825 | #define mmMMEA5_DSM_CNTL2A_BASE_IDX 1 |
|---|
| 5826 | #define mmMMEA5_DSM_CNTL2B 0x338d |
|---|
| 5827 | #define mmMMEA5_DSM_CNTL2B_BASE_IDX 1 |
|---|
| 5828 | #define mmMMEA5_CGTT_CLK_CTRL 0x338f |
|---|
| 5829 | #define mmMMEA5_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 5830 | #define mmMMEA5_EDC_MODE 0x3390 |
|---|
| 5831 | #define mmMMEA5_EDC_MODE_BASE_IDX 1 |
|---|
| 5832 | #define mmMMEA5_ERR_STATUS 0x3391 |
|---|
| 5833 | #define mmMMEA5_ERR_STATUS_BASE_IDX 1 |
|---|
| 5834 | #define mmMMEA5_MISC2 0x3392 |
|---|
| 5835 | #define mmMMEA5_MISC2_BASE_IDX 1 |
|---|
| 5836 | #define mmMMEA5_ADDRDEC_SELECT 0x3393 |
|---|
| 5837 | #define mmMMEA5_ADDRDEC_SELECT_BASE_IDX 1 |
|---|
| 5838 | #define mmMMEA5_EDC_CNT3 0x3394 |
|---|
| 5839 | #define mmMMEA5_EDC_CNT3_BASE_IDX 1 |
|---|
| 5840 | |
|---|
| 5841 | |
|---|
| 5842 | // addressBlock: mmhub_ea_mmeadec6 |
|---|
| 5843 | // base address: 0x74f00 |
|---|
| 5844 | #define mmMMEA6_DRAM_RD_CLI2GRP_MAP0 0x33c0 |
|---|
| 5845 | #define mmMMEA6_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 5846 | #define mmMMEA6_DRAM_RD_CLI2GRP_MAP1 0x33c1 |
|---|
| 5847 | #define mmMMEA6_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 5848 | #define mmMMEA6_DRAM_WR_CLI2GRP_MAP0 0x33c2 |
|---|
| 5849 | #define mmMMEA6_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 5850 | #define mmMMEA6_DRAM_WR_CLI2GRP_MAP1 0x33c3 |
|---|
| 5851 | #define mmMMEA6_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 5852 | #define mmMMEA6_DRAM_RD_GRP2VC_MAP 0x33c4 |
|---|
| 5853 | #define mmMMEA6_DRAM_RD_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 5854 | #define mmMMEA6_DRAM_WR_GRP2VC_MAP 0x33c5 |
|---|
| 5855 | #define mmMMEA6_DRAM_WR_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 5856 | #define mmMMEA6_DRAM_RD_LAZY 0x33c6 |
|---|
| 5857 | #define mmMMEA6_DRAM_RD_LAZY_BASE_IDX 1 |
|---|
| 5858 | #define mmMMEA6_DRAM_WR_LAZY 0x33c7 |
|---|
| 5859 | #define mmMMEA6_DRAM_WR_LAZY_BASE_IDX 1 |
|---|
| 5860 | #define mmMMEA6_DRAM_RD_CAM_CNTL 0x33c8 |
|---|
| 5861 | #define mmMMEA6_DRAM_RD_CAM_CNTL_BASE_IDX 1 |
|---|
| 5862 | #define mmMMEA6_DRAM_WR_CAM_CNTL 0x33c9 |
|---|
| 5863 | #define mmMMEA6_DRAM_WR_CAM_CNTL_BASE_IDX 1 |
|---|
| 5864 | #define mmMMEA6_DRAM_PAGE_BURST 0x33ca |
|---|
| 5865 | #define mmMMEA6_DRAM_PAGE_BURST_BASE_IDX 1 |
|---|
| 5866 | #define mmMMEA6_DRAM_RD_PRI_AGE 0x33cb |
|---|
| 5867 | #define mmMMEA6_DRAM_RD_PRI_AGE_BASE_IDX 1 |
|---|
| 5868 | #define mmMMEA6_DRAM_WR_PRI_AGE 0x33cc |
|---|
| 5869 | #define mmMMEA6_DRAM_WR_PRI_AGE_BASE_IDX 1 |
|---|
| 5870 | #define mmMMEA6_DRAM_RD_PRI_QUEUING 0x33cd |
|---|
| 5871 | #define mmMMEA6_DRAM_RD_PRI_QUEUING_BASE_IDX 1 |
|---|
| 5872 | #define mmMMEA6_DRAM_WR_PRI_QUEUING 0x33ce |
|---|
| 5873 | #define mmMMEA6_DRAM_WR_PRI_QUEUING_BASE_IDX 1 |
|---|
| 5874 | #define mmMMEA6_DRAM_RD_PRI_FIXED 0x33cf |
|---|
| 5875 | #define mmMMEA6_DRAM_RD_PRI_FIXED_BASE_IDX 1 |
|---|
| 5876 | #define mmMMEA6_DRAM_WR_PRI_FIXED 0x33d0 |
|---|
| 5877 | #define mmMMEA6_DRAM_WR_PRI_FIXED_BASE_IDX 1 |
|---|
| 5878 | #define mmMMEA6_DRAM_RD_PRI_URGENCY 0x33d1 |
|---|
| 5879 | #define mmMMEA6_DRAM_RD_PRI_URGENCY_BASE_IDX 1 |
|---|
| 5880 | #define mmMMEA6_DRAM_WR_PRI_URGENCY 0x33d2 |
|---|
| 5881 | #define mmMMEA6_DRAM_WR_PRI_URGENCY_BASE_IDX 1 |
|---|
| 5882 | #define mmMMEA6_DRAM_RD_PRI_QUANT_PRI1 0x33d3 |
|---|
| 5883 | #define mmMMEA6_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 5884 | #define mmMMEA6_DRAM_RD_PRI_QUANT_PRI2 0x33d4 |
|---|
| 5885 | #define mmMMEA6_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 5886 | #define mmMMEA6_DRAM_RD_PRI_QUANT_PRI3 0x33d5 |
|---|
| 5887 | #define mmMMEA6_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 5888 | #define mmMMEA6_DRAM_WR_PRI_QUANT_PRI1 0x33d6 |
|---|
| 5889 | #define mmMMEA6_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 5890 | #define mmMMEA6_DRAM_WR_PRI_QUANT_PRI2 0x33d7 |
|---|
| 5891 | #define mmMMEA6_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 5892 | #define mmMMEA6_DRAM_WR_PRI_QUANT_PRI3 0x33d8 |
|---|
| 5893 | #define mmMMEA6_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 5894 | #define mmMMEA6_GMI_RD_CLI2GRP_MAP0 0x33d9 |
|---|
| 5895 | #define mmMMEA6_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 5896 | #define mmMMEA6_GMI_RD_CLI2GRP_MAP1 0x33da |
|---|
| 5897 | #define mmMMEA6_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 5898 | #define mmMMEA6_GMI_WR_CLI2GRP_MAP0 0x33db |
|---|
| 5899 | #define mmMMEA6_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 5900 | #define mmMMEA6_GMI_WR_CLI2GRP_MAP1 0x33dc |
|---|
| 5901 | #define mmMMEA6_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 5902 | #define mmMMEA6_GMI_RD_GRP2VC_MAP 0x33dd |
|---|
| 5903 | #define mmMMEA6_GMI_RD_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 5904 | #define mmMMEA6_GMI_WR_GRP2VC_MAP 0x33de |
|---|
| 5905 | #define mmMMEA6_GMI_WR_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 5906 | #define mmMMEA6_GMI_RD_LAZY 0x33df |
|---|
| 5907 | #define mmMMEA6_GMI_RD_LAZY_BASE_IDX 1 |
|---|
| 5908 | #define mmMMEA6_GMI_WR_LAZY 0x33e0 |
|---|
| 5909 | #define mmMMEA6_GMI_WR_LAZY_BASE_IDX 1 |
|---|
| 5910 | #define mmMMEA6_GMI_RD_CAM_CNTL 0x33e1 |
|---|
| 5911 | #define mmMMEA6_GMI_RD_CAM_CNTL_BASE_IDX 1 |
|---|
| 5912 | #define mmMMEA6_GMI_WR_CAM_CNTL 0x33e2 |
|---|
| 5913 | #define mmMMEA6_GMI_WR_CAM_CNTL_BASE_IDX 1 |
|---|
| 5914 | #define mmMMEA6_GMI_PAGE_BURST 0x33e3 |
|---|
| 5915 | #define mmMMEA6_GMI_PAGE_BURST_BASE_IDX 1 |
|---|
| 5916 | #define mmMMEA6_GMI_RD_PRI_AGE 0x33e4 |
|---|
| 5917 | #define mmMMEA6_GMI_RD_PRI_AGE_BASE_IDX 1 |
|---|
| 5918 | #define mmMMEA6_GMI_WR_PRI_AGE 0x33e5 |
|---|
| 5919 | #define mmMMEA6_GMI_WR_PRI_AGE_BASE_IDX 1 |
|---|
| 5920 | #define mmMMEA6_GMI_RD_PRI_QUEUING 0x33e6 |
|---|
| 5921 | #define mmMMEA6_GMI_RD_PRI_QUEUING_BASE_IDX 1 |
|---|
| 5922 | #define mmMMEA6_GMI_WR_PRI_QUEUING 0x33e7 |
|---|
| 5923 | #define mmMMEA6_GMI_WR_PRI_QUEUING_BASE_IDX 1 |
|---|
| 5924 | #define mmMMEA6_GMI_RD_PRI_FIXED 0x33e8 |
|---|
| 5925 | #define mmMMEA6_GMI_RD_PRI_FIXED_BASE_IDX 1 |
|---|
| 5926 | #define mmMMEA6_GMI_WR_PRI_FIXED 0x33e9 |
|---|
| 5927 | #define mmMMEA6_GMI_WR_PRI_FIXED_BASE_IDX 1 |
|---|
| 5928 | #define mmMMEA6_GMI_RD_PRI_URGENCY 0x33ea |
|---|
| 5929 | #define mmMMEA6_GMI_RD_PRI_URGENCY_BASE_IDX 1 |
|---|
| 5930 | #define mmMMEA6_GMI_WR_PRI_URGENCY 0x33eb |
|---|
| 5931 | #define mmMMEA6_GMI_WR_PRI_URGENCY_BASE_IDX 1 |
|---|
| 5932 | #define mmMMEA6_GMI_RD_PRI_URGENCY_MASKING 0x33ec |
|---|
| 5933 | #define mmMMEA6_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 5934 | #define mmMMEA6_GMI_WR_PRI_URGENCY_MASKING 0x33ed |
|---|
| 5935 | #define mmMMEA6_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 5936 | #define mmMMEA6_GMI_RD_PRI_QUANT_PRI1 0x33ee |
|---|
| 5937 | #define mmMMEA6_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 5938 | #define mmMMEA6_GMI_RD_PRI_QUANT_PRI2 0x33ef |
|---|
| 5939 | #define mmMMEA6_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 5940 | #define mmMMEA6_GMI_RD_PRI_QUANT_PRI3 0x33f0 |
|---|
| 5941 | #define mmMMEA6_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 5942 | #define mmMMEA6_GMI_WR_PRI_QUANT_PRI1 0x33f1 |
|---|
| 5943 | #define mmMMEA6_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 5944 | #define mmMMEA6_GMI_WR_PRI_QUANT_PRI2 0x33f2 |
|---|
| 5945 | #define mmMMEA6_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 5946 | #define mmMMEA6_GMI_WR_PRI_QUANT_PRI3 0x33f3 |
|---|
| 5947 | #define mmMMEA6_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 5948 | #define mmMMEA6_ADDRNORM_BASE_ADDR0 0x33f4 |
|---|
| 5949 | #define mmMMEA6_ADDRNORM_BASE_ADDR0_BASE_IDX 1 |
|---|
| 5950 | #define mmMMEA6_ADDRNORM_LIMIT_ADDR0 0x33f5 |
|---|
| 5951 | #define mmMMEA6_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1 |
|---|
| 5952 | #define mmMMEA6_ADDRNORM_BASE_ADDR1 0x33f6 |
|---|
| 5953 | #define mmMMEA6_ADDRNORM_BASE_ADDR1_BASE_IDX 1 |
|---|
| 5954 | #define mmMMEA6_ADDRNORM_LIMIT_ADDR1 0x33f7 |
|---|
| 5955 | #define mmMMEA6_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1 |
|---|
| 5956 | #define mmMMEA6_ADDRNORM_OFFSET_ADDR1 0x33f8 |
|---|
| 5957 | #define mmMMEA6_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1 |
|---|
| 5958 | #define mmMMEA6_ADDRNORM_BASE_ADDR2 0x33f9 |
|---|
| 5959 | #define mmMMEA6_ADDRNORM_BASE_ADDR2_BASE_IDX 1 |
|---|
| 5960 | #define mmMMEA6_ADDRNORM_LIMIT_ADDR2 0x33fa |
|---|
| 5961 | #define mmMMEA6_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1 |
|---|
| 5962 | #define mmMMEA6_ADDRNORM_BASE_ADDR3 0x33fb |
|---|
| 5963 | #define mmMMEA6_ADDRNORM_BASE_ADDR3_BASE_IDX 1 |
|---|
| 5964 | #define mmMMEA6_ADDRNORM_LIMIT_ADDR3 0x33fc |
|---|
| 5965 | #define mmMMEA6_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1 |
|---|
| 5966 | #define mmMMEA6_ADDRNORM_OFFSET_ADDR3 0x33fd |
|---|
| 5967 | #define mmMMEA6_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1 |
|---|
| 5968 | #define mmMMEA6_ADDRNORM_BASE_ADDR4 0x33fe |
|---|
| 5969 | #define mmMMEA6_ADDRNORM_BASE_ADDR4_BASE_IDX 1 |
|---|
| 5970 | #define mmMMEA6_ADDRNORM_LIMIT_ADDR4 0x33ff |
|---|
| 5971 | #define mmMMEA6_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1 |
|---|
| 5972 | #define mmMMEA6_ADDRNORM_BASE_ADDR5 0x3400 |
|---|
| 5973 | #define mmMMEA6_ADDRNORM_BASE_ADDR5_BASE_IDX 1 |
|---|
| 5974 | #define mmMMEA6_ADDRNORM_LIMIT_ADDR5 0x3401 |
|---|
| 5975 | #define mmMMEA6_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1 |
|---|
| 5976 | #define mmMMEA6_ADDRNORM_OFFSET_ADDR5 0x3402 |
|---|
| 5977 | #define mmMMEA6_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1 |
|---|
| 5978 | #define mmMMEA6_ADDRNORMDRAM_HOLE_CNTL 0x3403 |
|---|
| 5979 | #define mmMMEA6_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1 |
|---|
| 5980 | #define mmMMEA6_ADDRNORMGMI_HOLE_CNTL 0x3404 |
|---|
| 5981 | #define mmMMEA6_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1 |
|---|
| 5982 | #define mmMMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x3405 |
|---|
| 5983 | #define mmMMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1 |
|---|
| 5984 | #define mmMMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG 0x3406 |
|---|
| 5985 | #define mmMMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1 |
|---|
| 5986 | #define mmMMEA6_ADDRDEC_BANK_CFG 0x3407 |
|---|
| 5987 | #define mmMMEA6_ADDRDEC_BANK_CFG_BASE_IDX 1 |
|---|
| 5988 | #define mmMMEA6_ADDRDEC_MISC_CFG 0x3408 |
|---|
| 5989 | #define mmMMEA6_ADDRDEC_MISC_CFG_BASE_IDX 1 |
|---|
| 5990 | #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK0 0x3409 |
|---|
| 5991 | #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1 |
|---|
| 5992 | #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK1 0x340a |
|---|
| 5993 | #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1 |
|---|
| 5994 | #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK2 0x340b |
|---|
| 5995 | #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1 |
|---|
| 5996 | #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK3 0x340c |
|---|
| 5997 | #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1 |
|---|
| 5998 | #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK4 0x340d |
|---|
| 5999 | #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1 |
|---|
| 6000 | #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK5 0x340e |
|---|
| 6001 | #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1 |
|---|
| 6002 | #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC 0x340f |
|---|
| 6003 | #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1 |
|---|
| 6004 | #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC2 0x3410 |
|---|
| 6005 | #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1 |
|---|
| 6006 | #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS0 0x3411 |
|---|
| 6007 | #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1 |
|---|
| 6008 | #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS1 0x3412 |
|---|
| 6009 | #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1 |
|---|
| 6010 | #define mmMMEA6_ADDRDECDRAM_HARVEST_ENABLE 0x3413 |
|---|
| 6011 | #define mmMMEA6_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1 |
|---|
| 6012 | #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK0 0x3414 |
|---|
| 6013 | #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1 |
|---|
| 6014 | #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK1 0x3415 |
|---|
| 6015 | #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1 |
|---|
| 6016 | #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK2 0x3416 |
|---|
| 6017 | #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1 |
|---|
| 6018 | #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK3 0x3417 |
|---|
| 6019 | #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1 |
|---|
| 6020 | #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK4 0x3418 |
|---|
| 6021 | #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1 |
|---|
| 6022 | #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK5 0x3419 |
|---|
| 6023 | #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1 |
|---|
| 6024 | #define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC 0x341a |
|---|
| 6025 | #define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1 |
|---|
| 6026 | #define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC2 0x341b |
|---|
| 6027 | #define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1 |
|---|
| 6028 | #define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS0 0x341c |
|---|
| 6029 | #define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1 |
|---|
| 6030 | #define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS1 0x341d |
|---|
| 6031 | #define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1 |
|---|
| 6032 | #define mmMMEA6_ADDRDECGMI_HARVEST_ENABLE 0x341e |
|---|
| 6033 | #define mmMMEA6_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1 |
|---|
| 6034 | #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS0 0x341f |
|---|
| 6035 | #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1 |
|---|
| 6036 | #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS1 0x3420 |
|---|
| 6037 | #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1 |
|---|
| 6038 | #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS2 0x3421 |
|---|
| 6039 | #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1 |
|---|
| 6040 | #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS3 0x3422 |
|---|
| 6041 | #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1 |
|---|
| 6042 | #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS0 0x3423 |
|---|
| 6043 | #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1 |
|---|
| 6044 | #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS1 0x3424 |
|---|
| 6045 | #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1 |
|---|
| 6046 | #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS2 0x3425 |
|---|
| 6047 | #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1 |
|---|
| 6048 | #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS3 0x3426 |
|---|
| 6049 | #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1 |
|---|
| 6050 | #define mmMMEA6_ADDRDEC0_ADDR_MASK_CS01 0x3427 |
|---|
| 6051 | #define mmMMEA6_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1 |
|---|
| 6052 | #define mmMMEA6_ADDRDEC0_ADDR_MASK_CS23 0x3428 |
|---|
| 6053 | #define mmMMEA6_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1 |
|---|
| 6054 | #define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS01 0x3429 |
|---|
| 6055 | #define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1 |
|---|
| 6056 | #define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS23 0x342a |
|---|
| 6057 | #define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1 |
|---|
| 6058 | #define mmMMEA6_ADDRDEC0_ADDR_CFG_CS01 0x342b |
|---|
| 6059 | #define mmMMEA6_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1 |
|---|
| 6060 | #define mmMMEA6_ADDRDEC0_ADDR_CFG_CS23 0x342c |
|---|
| 6061 | #define mmMMEA6_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1 |
|---|
| 6062 | #define mmMMEA6_ADDRDEC0_ADDR_SEL_CS01 0x342d |
|---|
| 6063 | #define mmMMEA6_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1 |
|---|
| 6064 | #define mmMMEA6_ADDRDEC0_ADDR_SEL_CS23 0x342e |
|---|
| 6065 | #define mmMMEA6_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1 |
|---|
| 6066 | #define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS01 0x342f |
|---|
| 6067 | #define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1 |
|---|
| 6068 | #define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS23 0x3430 |
|---|
| 6069 | #define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1 |
|---|
| 6070 | #define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS01 0x3431 |
|---|
| 6071 | #define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1 |
|---|
| 6072 | #define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS23 0x3432 |
|---|
| 6073 | #define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1 |
|---|
| 6074 | #define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS01 0x3433 |
|---|
| 6075 | #define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1 |
|---|
| 6076 | #define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS23 0x3434 |
|---|
| 6077 | #define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1 |
|---|
| 6078 | #define mmMMEA6_ADDRDEC0_RM_SEL_CS01 0x3435 |
|---|
| 6079 | #define mmMMEA6_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1 |
|---|
| 6080 | #define mmMMEA6_ADDRDEC0_RM_SEL_CS23 0x3436 |
|---|
| 6081 | #define mmMMEA6_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1 |
|---|
| 6082 | #define mmMMEA6_ADDRDEC0_RM_SEL_SECCS01 0x3437 |
|---|
| 6083 | #define mmMMEA6_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1 |
|---|
| 6084 | #define mmMMEA6_ADDRDEC0_RM_SEL_SECCS23 0x3438 |
|---|
| 6085 | #define mmMMEA6_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1 |
|---|
| 6086 | #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS0 0x3439 |
|---|
| 6087 | #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1 |
|---|
| 6088 | #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS1 0x343a |
|---|
| 6089 | #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1 |
|---|
| 6090 | #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS2 0x343b |
|---|
| 6091 | #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1 |
|---|
| 6092 | #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS3 0x343c |
|---|
| 6093 | #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1 |
|---|
| 6094 | #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS0 0x343d |
|---|
| 6095 | #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1 |
|---|
| 6096 | #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS1 0x343e |
|---|
| 6097 | #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1 |
|---|
| 6098 | #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS2 0x343f |
|---|
| 6099 | #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1 |
|---|
| 6100 | #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS3 0x3440 |
|---|
| 6101 | #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1 |
|---|
| 6102 | #define mmMMEA6_ADDRDEC1_ADDR_MASK_CS01 0x3441 |
|---|
| 6103 | #define mmMMEA6_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1 |
|---|
| 6104 | #define mmMMEA6_ADDRDEC1_ADDR_MASK_CS23 0x3442 |
|---|
| 6105 | #define mmMMEA6_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1 |
|---|
| 6106 | #define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS01 0x3443 |
|---|
| 6107 | #define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1 |
|---|
| 6108 | #define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS23 0x3444 |
|---|
| 6109 | #define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1 |
|---|
| 6110 | #define mmMMEA6_ADDRDEC1_ADDR_CFG_CS01 0x3445 |
|---|
| 6111 | #define mmMMEA6_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1 |
|---|
| 6112 | #define mmMMEA6_ADDRDEC1_ADDR_CFG_CS23 0x3446 |
|---|
| 6113 | #define mmMMEA6_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1 |
|---|
| 6114 | #define mmMMEA6_ADDRDEC1_ADDR_SEL_CS01 0x3447 |
|---|
| 6115 | #define mmMMEA6_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1 |
|---|
| 6116 | #define mmMMEA6_ADDRDEC1_ADDR_SEL_CS23 0x3448 |
|---|
| 6117 | #define mmMMEA6_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1 |
|---|
| 6118 | #define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS01 0x3449 |
|---|
| 6119 | #define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1 |
|---|
| 6120 | #define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS23 0x344a |
|---|
| 6121 | #define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1 |
|---|
| 6122 | #define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS01 0x344b |
|---|
| 6123 | #define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1 |
|---|
| 6124 | #define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS23 0x344c |
|---|
| 6125 | #define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1 |
|---|
| 6126 | #define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS01 0x344d |
|---|
| 6127 | #define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1 |
|---|
| 6128 | #define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS23 0x344e |
|---|
| 6129 | #define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1 |
|---|
| 6130 | #define mmMMEA6_ADDRDEC1_RM_SEL_CS01 0x344f |
|---|
| 6131 | #define mmMMEA6_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1 |
|---|
| 6132 | #define mmMMEA6_ADDRDEC1_RM_SEL_CS23 0x3450 |
|---|
| 6133 | #define mmMMEA6_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1 |
|---|
| 6134 | #define mmMMEA6_ADDRDEC1_RM_SEL_SECCS01 0x3451 |
|---|
| 6135 | #define mmMMEA6_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1 |
|---|
| 6136 | #define mmMMEA6_ADDRDEC1_RM_SEL_SECCS23 0x3452 |
|---|
| 6137 | #define mmMMEA6_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1 |
|---|
| 6138 | #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS0 0x3453 |
|---|
| 6139 | #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1 |
|---|
| 6140 | #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS1 0x3454 |
|---|
| 6141 | #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1 |
|---|
| 6142 | #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS2 0x3455 |
|---|
| 6143 | #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1 |
|---|
| 6144 | #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS3 0x3456 |
|---|
| 6145 | #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1 |
|---|
| 6146 | #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS0 0x3457 |
|---|
| 6147 | #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1 |
|---|
| 6148 | #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS1 0x3458 |
|---|
| 6149 | #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1 |
|---|
| 6150 | #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS2 0x3459 |
|---|
| 6151 | #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1 |
|---|
| 6152 | #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS3 0x345a |
|---|
| 6153 | #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1 |
|---|
| 6154 | #define mmMMEA6_ADDRDEC2_ADDR_MASK_CS01 0x345b |
|---|
| 6155 | #define mmMMEA6_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1 |
|---|
| 6156 | #define mmMMEA6_ADDRDEC2_ADDR_MASK_CS23 0x345c |
|---|
| 6157 | #define mmMMEA6_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1 |
|---|
| 6158 | #define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS01 0x345d |
|---|
| 6159 | #define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1 |
|---|
| 6160 | #define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS23 0x345e |
|---|
| 6161 | #define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1 |
|---|
| 6162 | #define mmMMEA6_ADDRDEC2_ADDR_CFG_CS01 0x345f |
|---|
| 6163 | #define mmMMEA6_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1 |
|---|
| 6164 | #define mmMMEA6_ADDRDEC2_ADDR_CFG_CS23 0x3460 |
|---|
| 6165 | #define mmMMEA6_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1 |
|---|
| 6166 | #define mmMMEA6_ADDRDEC2_ADDR_SEL_CS01 0x3461 |
|---|
| 6167 | #define mmMMEA6_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1 |
|---|
| 6168 | #define mmMMEA6_ADDRDEC2_ADDR_SEL_CS23 0x3462 |
|---|
| 6169 | #define mmMMEA6_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1 |
|---|
| 6170 | #define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS01 0x3463 |
|---|
| 6171 | #define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1 |
|---|
| 6172 | #define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS23 0x3464 |
|---|
| 6173 | #define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1 |
|---|
| 6174 | #define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS01 0x3465 |
|---|
| 6175 | #define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1 |
|---|
| 6176 | #define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS23 0x3466 |
|---|
| 6177 | #define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1 |
|---|
| 6178 | #define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS01 0x3467 |
|---|
| 6179 | #define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1 |
|---|
| 6180 | #define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS23 0x3468 |
|---|
| 6181 | #define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1 |
|---|
| 6182 | #define mmMMEA6_ADDRDEC2_RM_SEL_CS01 0x3469 |
|---|
| 6183 | #define mmMMEA6_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1 |
|---|
| 6184 | #define mmMMEA6_ADDRDEC2_RM_SEL_CS23 0x346a |
|---|
| 6185 | #define mmMMEA6_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1 |
|---|
| 6186 | #define mmMMEA6_ADDRDEC2_RM_SEL_SECCS01 0x346b |
|---|
| 6187 | #define mmMMEA6_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1 |
|---|
| 6188 | #define mmMMEA6_ADDRDEC2_RM_SEL_SECCS23 0x346c |
|---|
| 6189 | #define mmMMEA6_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1 |
|---|
| 6190 | #define mmMMEA6_ADDRNORMDRAM_GLOBAL_CNTL 0x346d |
|---|
| 6191 | #define mmMMEA6_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1 |
|---|
| 6192 | #define mmMMEA6_ADDRNORMGMI_GLOBAL_CNTL 0x346e |
|---|
| 6193 | #define mmMMEA6_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1 |
|---|
| 6194 | #define mmMMEA6_IO_RD_CLI2GRP_MAP0 0x3495 |
|---|
| 6195 | #define mmMMEA6_IO_RD_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 6196 | #define mmMMEA6_IO_RD_CLI2GRP_MAP1 0x3496 |
|---|
| 6197 | #define mmMMEA6_IO_RD_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 6198 | #define mmMMEA6_IO_WR_CLI2GRP_MAP0 0x3497 |
|---|
| 6199 | #define mmMMEA6_IO_WR_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 6200 | #define mmMMEA6_IO_WR_CLI2GRP_MAP1 0x3498 |
|---|
| 6201 | #define mmMMEA6_IO_WR_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 6202 | #define mmMMEA6_IO_RD_COMBINE_FLUSH 0x3499 |
|---|
| 6203 | #define mmMMEA6_IO_RD_COMBINE_FLUSH_BASE_IDX 1 |
|---|
| 6204 | #define mmMMEA6_IO_WR_COMBINE_FLUSH 0x349a |
|---|
| 6205 | #define mmMMEA6_IO_WR_COMBINE_FLUSH_BASE_IDX 1 |
|---|
| 6206 | #define mmMMEA6_IO_GROUP_BURST 0x349b |
|---|
| 6207 | #define mmMMEA6_IO_GROUP_BURST_BASE_IDX 1 |
|---|
| 6208 | #define mmMMEA6_IO_RD_PRI_AGE 0x349c |
|---|
| 6209 | #define mmMMEA6_IO_RD_PRI_AGE_BASE_IDX 1 |
|---|
| 6210 | #define mmMMEA6_IO_WR_PRI_AGE 0x349d |
|---|
| 6211 | #define mmMMEA6_IO_WR_PRI_AGE_BASE_IDX 1 |
|---|
| 6212 | #define mmMMEA6_IO_RD_PRI_QUEUING 0x349e |
|---|
| 6213 | #define mmMMEA6_IO_RD_PRI_QUEUING_BASE_IDX 1 |
|---|
| 6214 | #define mmMMEA6_IO_WR_PRI_QUEUING 0x349f |
|---|
| 6215 | #define mmMMEA6_IO_WR_PRI_QUEUING_BASE_IDX 1 |
|---|
| 6216 | #define mmMMEA6_IO_RD_PRI_FIXED 0x34a0 |
|---|
| 6217 | #define mmMMEA6_IO_RD_PRI_FIXED_BASE_IDX 1 |
|---|
| 6218 | #define mmMMEA6_IO_WR_PRI_FIXED 0x34a1 |
|---|
| 6219 | #define mmMMEA6_IO_WR_PRI_FIXED_BASE_IDX 1 |
|---|
| 6220 | #define mmMMEA6_IO_RD_PRI_URGENCY 0x34a2 |
|---|
| 6221 | #define mmMMEA6_IO_RD_PRI_URGENCY_BASE_IDX 1 |
|---|
| 6222 | #define mmMMEA6_IO_WR_PRI_URGENCY 0x34a3 |
|---|
| 6223 | #define mmMMEA6_IO_WR_PRI_URGENCY_BASE_IDX 1 |
|---|
| 6224 | #define mmMMEA6_IO_RD_PRI_URGENCY_MASKING 0x34a4 |
|---|
| 6225 | #define mmMMEA6_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 6226 | #define mmMMEA6_IO_WR_PRI_URGENCY_MASKING 0x34a5 |
|---|
| 6227 | #define mmMMEA6_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 6228 | #define mmMMEA6_IO_RD_PRI_QUANT_PRI1 0x34a6 |
|---|
| 6229 | #define mmMMEA6_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 6230 | #define mmMMEA6_IO_RD_PRI_QUANT_PRI2 0x34a7 |
|---|
| 6231 | #define mmMMEA6_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 6232 | #define mmMMEA6_IO_RD_PRI_QUANT_PRI3 0x34a8 |
|---|
| 6233 | #define mmMMEA6_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 6234 | #define mmMMEA6_IO_WR_PRI_QUANT_PRI1 0x34a9 |
|---|
| 6235 | #define mmMMEA6_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 6236 | #define mmMMEA6_IO_WR_PRI_QUANT_PRI2 0x34aa |
|---|
| 6237 | #define mmMMEA6_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 6238 | #define mmMMEA6_IO_WR_PRI_QUANT_PRI3 0x34ab |
|---|
| 6239 | #define mmMMEA6_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 6240 | #define mmMMEA6_SDP_ARB_DRAM 0x34ac |
|---|
| 6241 | #define mmMMEA6_SDP_ARB_DRAM_BASE_IDX 1 |
|---|
| 6242 | #define mmMMEA6_SDP_ARB_GMI 0x34ad |
|---|
| 6243 | #define mmMMEA6_SDP_ARB_GMI_BASE_IDX 1 |
|---|
| 6244 | #define mmMMEA6_SDP_ARB_FINAL 0x34ae |
|---|
| 6245 | #define mmMMEA6_SDP_ARB_FINAL_BASE_IDX 1 |
|---|
| 6246 | #define mmMMEA6_SDP_DRAM_PRIORITY 0x34af |
|---|
| 6247 | #define mmMMEA6_SDP_DRAM_PRIORITY_BASE_IDX 1 |
|---|
| 6248 | #define mmMMEA6_SDP_GMI_PRIORITY 0x34b0 |
|---|
| 6249 | #define mmMMEA6_SDP_GMI_PRIORITY_BASE_IDX 1 |
|---|
| 6250 | #define mmMMEA6_SDP_IO_PRIORITY 0x34b1 |
|---|
| 6251 | #define mmMMEA6_SDP_IO_PRIORITY_BASE_IDX 1 |
|---|
| 6252 | #define mmMMEA6_SDP_CREDITS 0x34b2 |
|---|
| 6253 | #define mmMMEA6_SDP_CREDITS_BASE_IDX 1 |
|---|
| 6254 | #define mmMMEA6_SDP_TAG_RESERVE0 0x34b3 |
|---|
| 6255 | #define mmMMEA6_SDP_TAG_RESERVE0_BASE_IDX 1 |
|---|
| 6256 | #define mmMMEA6_SDP_TAG_RESERVE1 0x34b4 |
|---|
| 6257 | #define mmMMEA6_SDP_TAG_RESERVE1_BASE_IDX 1 |
|---|
| 6258 | #define mmMMEA6_SDP_VCC_RESERVE0 0x34b5 |
|---|
| 6259 | #define mmMMEA6_SDP_VCC_RESERVE0_BASE_IDX 1 |
|---|
| 6260 | #define mmMMEA6_SDP_VCC_RESERVE1 0x34b6 |
|---|
| 6261 | #define mmMMEA6_SDP_VCC_RESERVE1_BASE_IDX 1 |
|---|
| 6262 | #define mmMMEA6_SDP_VCD_RESERVE0 0x34b7 |
|---|
| 6263 | #define mmMMEA6_SDP_VCD_RESERVE0_BASE_IDX 1 |
|---|
| 6264 | #define mmMMEA6_SDP_VCD_RESERVE1 0x34b8 |
|---|
| 6265 | #define mmMMEA6_SDP_VCD_RESERVE1_BASE_IDX 1 |
|---|
| 6266 | #define mmMMEA6_SDP_REQ_CNTL 0x34b9 |
|---|
| 6267 | #define mmMMEA6_SDP_REQ_CNTL_BASE_IDX 1 |
|---|
| 6268 | #define mmMMEA6_MISC 0x34ba |
|---|
| 6269 | #define mmMMEA6_MISC_BASE_IDX 1 |
|---|
| 6270 | #define mmMMEA6_LATENCY_SAMPLING 0x34bb |
|---|
| 6271 | #define mmMMEA6_LATENCY_SAMPLING_BASE_IDX 1 |
|---|
| 6272 | #define mmMMEA6_PERFCOUNTER_LO 0x34bc |
|---|
| 6273 | #define mmMMEA6_PERFCOUNTER_LO_BASE_IDX 1 |
|---|
| 6274 | #define mmMMEA6_PERFCOUNTER_HI 0x34bd |
|---|
| 6275 | #define mmMMEA6_PERFCOUNTER_HI_BASE_IDX 1 |
|---|
| 6276 | #define mmMMEA6_PERFCOUNTER0_CFG 0x34be |
|---|
| 6277 | #define mmMMEA6_PERFCOUNTER0_CFG_BASE_IDX 1 |
|---|
| 6278 | #define mmMMEA6_PERFCOUNTER1_CFG 0x34bf |
|---|
| 6279 | #define mmMMEA6_PERFCOUNTER1_CFG_BASE_IDX 1 |
|---|
| 6280 | #define mmMMEA6_PERFCOUNTER_RSLT_CNTL 0x34c0 |
|---|
| 6281 | #define mmMMEA6_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
|---|
| 6282 | #define mmMMEA6_EDC_CNT 0x34c6 |
|---|
| 6283 | #define mmMMEA6_EDC_CNT_BASE_IDX 1 |
|---|
| 6284 | #define mmMMEA6_EDC_CNT2 0x34c7 |
|---|
| 6285 | #define mmMMEA6_EDC_CNT2_BASE_IDX 1 |
|---|
| 6286 | #define mmMMEA6_DSM_CNTL 0x34c8 |
|---|
| 6287 | #define mmMMEA6_DSM_CNTL_BASE_IDX 1 |
|---|
| 6288 | #define mmMMEA6_DSM_CNTLA 0x34c9 |
|---|
| 6289 | #define mmMMEA6_DSM_CNTLA_BASE_IDX 1 |
|---|
| 6290 | #define mmMMEA6_DSM_CNTLB 0x34ca |
|---|
| 6291 | #define mmMMEA6_DSM_CNTLB_BASE_IDX 1 |
|---|
| 6292 | #define mmMMEA6_DSM_CNTL2 0x34cb |
|---|
| 6293 | #define mmMMEA6_DSM_CNTL2_BASE_IDX 1 |
|---|
| 6294 | #define mmMMEA6_DSM_CNTL2A 0x34cc |
|---|
| 6295 | #define mmMMEA6_DSM_CNTL2A_BASE_IDX 1 |
|---|
| 6296 | #define mmMMEA6_DSM_CNTL2B 0x34cd |
|---|
| 6297 | #define mmMMEA6_DSM_CNTL2B_BASE_IDX 1 |
|---|
| 6298 | #define mmMMEA6_CGTT_CLK_CTRL 0x34cf |
|---|
| 6299 | #define mmMMEA6_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 6300 | #define mmMMEA6_EDC_MODE 0x34d0 |
|---|
| 6301 | #define mmMMEA6_EDC_MODE_BASE_IDX 1 |
|---|
| 6302 | #define mmMMEA6_ERR_STATUS 0x34d1 |
|---|
| 6303 | #define mmMMEA6_ERR_STATUS_BASE_IDX 1 |
|---|
| 6304 | #define mmMMEA6_MISC2 0x34d2 |
|---|
| 6305 | #define mmMMEA6_MISC2_BASE_IDX 1 |
|---|
| 6306 | #define mmMMEA6_ADDRDEC_SELECT 0x34d3 |
|---|
| 6307 | #define mmMMEA6_ADDRDEC_SELECT_BASE_IDX 1 |
|---|
| 6308 | #define mmMMEA6_EDC_CNT3 0x34d4 |
|---|
| 6309 | #define mmMMEA6_EDC_CNT3_BASE_IDX 1 |
|---|
| 6310 | |
|---|
| 6311 | |
|---|
| 6312 | // addressBlock: mmhub_ea_mmeadec7 |
|---|
| 6313 | // base address: 0x75400 |
|---|
| 6314 | #define mmMMEA7_DRAM_RD_CLI2GRP_MAP0 0x3500 |
|---|
| 6315 | #define mmMMEA7_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 6316 | #define mmMMEA7_DRAM_RD_CLI2GRP_MAP1 0x3501 |
|---|
| 6317 | #define mmMMEA7_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 6318 | #define mmMMEA7_DRAM_WR_CLI2GRP_MAP0 0x3502 |
|---|
| 6319 | #define mmMMEA7_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 6320 | #define mmMMEA7_DRAM_WR_CLI2GRP_MAP1 0x3503 |
|---|
| 6321 | #define mmMMEA7_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 6322 | #define mmMMEA7_DRAM_RD_GRP2VC_MAP 0x3504 |
|---|
| 6323 | #define mmMMEA7_DRAM_RD_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 6324 | #define mmMMEA7_DRAM_WR_GRP2VC_MAP 0x3505 |
|---|
| 6325 | #define mmMMEA7_DRAM_WR_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 6326 | #define mmMMEA7_DRAM_RD_LAZY 0x3506 |
|---|
| 6327 | #define mmMMEA7_DRAM_RD_LAZY_BASE_IDX 1 |
|---|
| 6328 | #define mmMMEA7_DRAM_WR_LAZY 0x3507 |
|---|
| 6329 | #define mmMMEA7_DRAM_WR_LAZY_BASE_IDX 1 |
|---|
| 6330 | #define mmMMEA7_DRAM_RD_CAM_CNTL 0x3508 |
|---|
| 6331 | #define mmMMEA7_DRAM_RD_CAM_CNTL_BASE_IDX 1 |
|---|
| 6332 | #define mmMMEA7_DRAM_WR_CAM_CNTL 0x3509 |
|---|
| 6333 | #define mmMMEA7_DRAM_WR_CAM_CNTL_BASE_IDX 1 |
|---|
| 6334 | #define mmMMEA7_DRAM_PAGE_BURST 0x350a |
|---|
| 6335 | #define mmMMEA7_DRAM_PAGE_BURST_BASE_IDX 1 |
|---|
| 6336 | #define mmMMEA7_DRAM_RD_PRI_AGE 0x350b |
|---|
| 6337 | #define mmMMEA7_DRAM_RD_PRI_AGE_BASE_IDX 1 |
|---|
| 6338 | #define mmMMEA7_DRAM_WR_PRI_AGE 0x350c |
|---|
| 6339 | #define mmMMEA7_DRAM_WR_PRI_AGE_BASE_IDX 1 |
|---|
| 6340 | #define mmMMEA7_DRAM_RD_PRI_QUEUING 0x350d |
|---|
| 6341 | #define mmMMEA7_DRAM_RD_PRI_QUEUING_BASE_IDX 1 |
|---|
| 6342 | #define mmMMEA7_DRAM_WR_PRI_QUEUING 0x350e |
|---|
| 6343 | #define mmMMEA7_DRAM_WR_PRI_QUEUING_BASE_IDX 1 |
|---|
| 6344 | #define mmMMEA7_DRAM_RD_PRI_FIXED 0x350f |
|---|
| 6345 | #define mmMMEA7_DRAM_RD_PRI_FIXED_BASE_IDX 1 |
|---|
| 6346 | #define mmMMEA7_DRAM_WR_PRI_FIXED 0x3510 |
|---|
| 6347 | #define mmMMEA7_DRAM_WR_PRI_FIXED_BASE_IDX 1 |
|---|
| 6348 | #define mmMMEA7_DRAM_RD_PRI_URGENCY 0x3511 |
|---|
| 6349 | #define mmMMEA7_DRAM_RD_PRI_URGENCY_BASE_IDX 1 |
|---|
| 6350 | #define mmMMEA7_DRAM_WR_PRI_URGENCY 0x3512 |
|---|
| 6351 | #define mmMMEA7_DRAM_WR_PRI_URGENCY_BASE_IDX 1 |
|---|
| 6352 | #define mmMMEA7_DRAM_RD_PRI_QUANT_PRI1 0x3513 |
|---|
| 6353 | #define mmMMEA7_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 6354 | #define mmMMEA7_DRAM_RD_PRI_QUANT_PRI2 0x3514 |
|---|
| 6355 | #define mmMMEA7_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 6356 | #define mmMMEA7_DRAM_RD_PRI_QUANT_PRI3 0x3515 |
|---|
| 6357 | #define mmMMEA7_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 6358 | #define mmMMEA7_DRAM_WR_PRI_QUANT_PRI1 0x3516 |
|---|
| 6359 | #define mmMMEA7_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 6360 | #define mmMMEA7_DRAM_WR_PRI_QUANT_PRI2 0x3517 |
|---|
| 6361 | #define mmMMEA7_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 6362 | #define mmMMEA7_DRAM_WR_PRI_QUANT_PRI3 0x3518 |
|---|
| 6363 | #define mmMMEA7_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 6364 | #define mmMMEA7_GMI_RD_CLI2GRP_MAP0 0x3519 |
|---|
| 6365 | #define mmMMEA7_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 6366 | #define mmMMEA7_GMI_RD_CLI2GRP_MAP1 0x351a |
|---|
| 6367 | #define mmMMEA7_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 6368 | #define mmMMEA7_GMI_WR_CLI2GRP_MAP0 0x351b |
|---|
| 6369 | #define mmMMEA7_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 6370 | #define mmMMEA7_GMI_WR_CLI2GRP_MAP1 0x351c |
|---|
| 6371 | #define mmMMEA7_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 6372 | #define mmMMEA7_GMI_RD_GRP2VC_MAP 0x351d |
|---|
| 6373 | #define mmMMEA7_GMI_RD_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 6374 | #define mmMMEA7_GMI_WR_GRP2VC_MAP 0x351e |
|---|
| 6375 | #define mmMMEA7_GMI_WR_GRP2VC_MAP_BASE_IDX 1 |
|---|
| 6376 | #define mmMMEA7_GMI_RD_LAZY 0x351f |
|---|
| 6377 | #define mmMMEA7_GMI_RD_LAZY_BASE_IDX 1 |
|---|
| 6378 | #define mmMMEA7_GMI_WR_LAZY 0x3520 |
|---|
| 6379 | #define mmMMEA7_GMI_WR_LAZY_BASE_IDX 1 |
|---|
| 6380 | #define mmMMEA7_GMI_RD_CAM_CNTL 0x3521 |
|---|
| 6381 | #define mmMMEA7_GMI_RD_CAM_CNTL_BASE_IDX 1 |
|---|
| 6382 | #define mmMMEA7_GMI_WR_CAM_CNTL 0x3522 |
|---|
| 6383 | #define mmMMEA7_GMI_WR_CAM_CNTL_BASE_IDX 1 |
|---|
| 6384 | #define mmMMEA7_GMI_PAGE_BURST 0x3523 |
|---|
| 6385 | #define mmMMEA7_GMI_PAGE_BURST_BASE_IDX 1 |
|---|
| 6386 | #define mmMMEA7_GMI_RD_PRI_AGE 0x3524 |
|---|
| 6387 | #define mmMMEA7_GMI_RD_PRI_AGE_BASE_IDX 1 |
|---|
| 6388 | #define mmMMEA7_GMI_WR_PRI_AGE 0x3525 |
|---|
| 6389 | #define mmMMEA7_GMI_WR_PRI_AGE_BASE_IDX 1 |
|---|
| 6390 | #define mmMMEA7_GMI_RD_PRI_QUEUING 0x3526 |
|---|
| 6391 | #define mmMMEA7_GMI_RD_PRI_QUEUING_BASE_IDX 1 |
|---|
| 6392 | #define mmMMEA7_GMI_WR_PRI_QUEUING 0x3527 |
|---|
| 6393 | #define mmMMEA7_GMI_WR_PRI_QUEUING_BASE_IDX 1 |
|---|
| 6394 | #define mmMMEA7_GMI_RD_PRI_FIXED 0x3528 |
|---|
| 6395 | #define mmMMEA7_GMI_RD_PRI_FIXED_BASE_IDX 1 |
|---|
| 6396 | #define mmMMEA7_GMI_WR_PRI_FIXED 0x3529 |
|---|
| 6397 | #define mmMMEA7_GMI_WR_PRI_FIXED_BASE_IDX 1 |
|---|
| 6398 | #define mmMMEA7_GMI_RD_PRI_URGENCY 0x352a |
|---|
| 6399 | #define mmMMEA7_GMI_RD_PRI_URGENCY_BASE_IDX 1 |
|---|
| 6400 | #define mmMMEA7_GMI_WR_PRI_URGENCY 0x352b |
|---|
| 6401 | #define mmMMEA7_GMI_WR_PRI_URGENCY_BASE_IDX 1 |
|---|
| 6402 | #define mmMMEA7_GMI_RD_PRI_URGENCY_MASKING 0x352c |
|---|
| 6403 | #define mmMMEA7_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 6404 | #define mmMMEA7_GMI_WR_PRI_URGENCY_MASKING 0x352d |
|---|
| 6405 | #define mmMMEA7_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 6406 | #define mmMMEA7_GMI_RD_PRI_QUANT_PRI1 0x352e |
|---|
| 6407 | #define mmMMEA7_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 6408 | #define mmMMEA7_GMI_RD_PRI_QUANT_PRI2 0x352f |
|---|
| 6409 | #define mmMMEA7_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 6410 | #define mmMMEA7_GMI_RD_PRI_QUANT_PRI3 0x3530 |
|---|
| 6411 | #define mmMMEA7_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 6412 | #define mmMMEA7_GMI_WR_PRI_QUANT_PRI1 0x3531 |
|---|
| 6413 | #define mmMMEA7_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 6414 | #define mmMMEA7_GMI_WR_PRI_QUANT_PRI2 0x3532 |
|---|
| 6415 | #define mmMMEA7_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 6416 | #define mmMMEA7_GMI_WR_PRI_QUANT_PRI3 0x3533 |
|---|
| 6417 | #define mmMMEA7_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 6418 | #define mmMMEA7_ADDRNORM_BASE_ADDR0 0x3534 |
|---|
| 6419 | #define mmMMEA7_ADDRNORM_BASE_ADDR0_BASE_IDX 1 |
|---|
| 6420 | #define mmMMEA7_ADDRNORM_LIMIT_ADDR0 0x3535 |
|---|
| 6421 | #define mmMMEA7_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1 |
|---|
| 6422 | #define mmMMEA7_ADDRNORM_BASE_ADDR1 0x3536 |
|---|
| 6423 | #define mmMMEA7_ADDRNORM_BASE_ADDR1_BASE_IDX 1 |
|---|
| 6424 | #define mmMMEA7_ADDRNORM_LIMIT_ADDR1 0x3537 |
|---|
| 6425 | #define mmMMEA7_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1 |
|---|
| 6426 | #define mmMMEA7_ADDRNORM_OFFSET_ADDR1 0x3538 |
|---|
| 6427 | #define mmMMEA7_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1 |
|---|
| 6428 | #define mmMMEA7_ADDRNORM_BASE_ADDR2 0x3539 |
|---|
| 6429 | #define mmMMEA7_ADDRNORM_BASE_ADDR2_BASE_IDX 1 |
|---|
| 6430 | #define mmMMEA7_ADDRNORM_LIMIT_ADDR2 0x353a |
|---|
| 6431 | #define mmMMEA7_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1 |
|---|
| 6432 | #define mmMMEA7_ADDRNORM_BASE_ADDR3 0x353b |
|---|
| 6433 | #define mmMMEA7_ADDRNORM_BASE_ADDR3_BASE_IDX 1 |
|---|
| 6434 | #define mmMMEA7_ADDRNORM_LIMIT_ADDR3 0x353c |
|---|
| 6435 | #define mmMMEA7_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1 |
|---|
| 6436 | #define mmMMEA7_ADDRNORM_OFFSET_ADDR3 0x353d |
|---|
| 6437 | #define mmMMEA7_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1 |
|---|
| 6438 | #define mmMMEA7_ADDRNORM_BASE_ADDR4 0x353e |
|---|
| 6439 | #define mmMMEA7_ADDRNORM_BASE_ADDR4_BASE_IDX 1 |
|---|
| 6440 | #define mmMMEA7_ADDRNORM_LIMIT_ADDR4 0x353f |
|---|
| 6441 | #define mmMMEA7_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1 |
|---|
| 6442 | #define mmMMEA7_ADDRNORM_BASE_ADDR5 0x3540 |
|---|
| 6443 | #define mmMMEA7_ADDRNORM_BASE_ADDR5_BASE_IDX 1 |
|---|
| 6444 | #define mmMMEA7_ADDRNORM_LIMIT_ADDR5 0x3541 |
|---|
| 6445 | #define mmMMEA7_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1 |
|---|
| 6446 | #define mmMMEA7_ADDRNORM_OFFSET_ADDR5 0x3542 |
|---|
| 6447 | #define mmMMEA7_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1 |
|---|
| 6448 | #define mmMMEA7_ADDRNORMDRAM_HOLE_CNTL 0x3543 |
|---|
| 6449 | #define mmMMEA7_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1 |
|---|
| 6450 | #define mmMMEA7_ADDRNORMGMI_HOLE_CNTL 0x3544 |
|---|
| 6451 | #define mmMMEA7_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1 |
|---|
| 6452 | #define mmMMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x3545 |
|---|
| 6453 | #define mmMMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1 |
|---|
| 6454 | #define mmMMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG 0x3546 |
|---|
| 6455 | #define mmMMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1 |
|---|
| 6456 | #define mmMMEA7_ADDRDEC_BANK_CFG 0x3547 |
|---|
| 6457 | #define mmMMEA7_ADDRDEC_BANK_CFG_BASE_IDX 1 |
|---|
| 6458 | #define mmMMEA7_ADDRDEC_MISC_CFG 0x3548 |
|---|
| 6459 | #define mmMMEA7_ADDRDEC_MISC_CFG_BASE_IDX 1 |
|---|
| 6460 | #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK0 0x3549 |
|---|
| 6461 | #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1 |
|---|
| 6462 | #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK1 0x354a |
|---|
| 6463 | #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1 |
|---|
| 6464 | #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK2 0x354b |
|---|
| 6465 | #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1 |
|---|
| 6466 | #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK3 0x354c |
|---|
| 6467 | #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1 |
|---|
| 6468 | #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK4 0x354d |
|---|
| 6469 | #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1 |
|---|
| 6470 | #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK5 0x354e |
|---|
| 6471 | #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1 |
|---|
| 6472 | #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC 0x354f |
|---|
| 6473 | #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1 |
|---|
| 6474 | #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC2 0x3550 |
|---|
| 6475 | #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1 |
|---|
| 6476 | #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS0 0x3551 |
|---|
| 6477 | #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1 |
|---|
| 6478 | #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS1 0x3552 |
|---|
| 6479 | #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1 |
|---|
| 6480 | #define mmMMEA7_ADDRDECDRAM_HARVEST_ENABLE 0x3553 |
|---|
| 6481 | #define mmMMEA7_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1 |
|---|
| 6482 | #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK0 0x3554 |
|---|
| 6483 | #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1 |
|---|
| 6484 | #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK1 0x3555 |
|---|
| 6485 | #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1 |
|---|
| 6486 | #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK2 0x3556 |
|---|
| 6487 | #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1 |
|---|
| 6488 | #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK3 0x3557 |
|---|
| 6489 | #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1 |
|---|
| 6490 | #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK4 0x3558 |
|---|
| 6491 | #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1 |
|---|
| 6492 | #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK5 0x3559 |
|---|
| 6493 | #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1 |
|---|
| 6494 | #define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC 0x355a |
|---|
| 6495 | #define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1 |
|---|
| 6496 | #define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC2 0x355b |
|---|
| 6497 | #define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1 |
|---|
| 6498 | #define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS0 0x355c |
|---|
| 6499 | #define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1 |
|---|
| 6500 | #define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS1 0x355d |
|---|
| 6501 | #define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1 |
|---|
| 6502 | #define mmMMEA7_ADDRDECGMI_HARVEST_ENABLE 0x355e |
|---|
| 6503 | #define mmMMEA7_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1 |
|---|
| 6504 | #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS0 0x355f |
|---|
| 6505 | #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1 |
|---|
| 6506 | #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS1 0x3560 |
|---|
| 6507 | #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1 |
|---|
| 6508 | #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS2 0x3561 |
|---|
| 6509 | #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1 |
|---|
| 6510 | #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS3 0x3562 |
|---|
| 6511 | #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1 |
|---|
| 6512 | #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS0 0x3563 |
|---|
| 6513 | #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1 |
|---|
| 6514 | #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS1 0x3564 |
|---|
| 6515 | #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1 |
|---|
| 6516 | #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS2 0x3565 |
|---|
| 6517 | #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1 |
|---|
| 6518 | #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS3 0x3566 |
|---|
| 6519 | #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1 |
|---|
| 6520 | #define mmMMEA7_ADDRDEC0_ADDR_MASK_CS01 0x3567 |
|---|
| 6521 | #define mmMMEA7_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1 |
|---|
| 6522 | #define mmMMEA7_ADDRDEC0_ADDR_MASK_CS23 0x3568 |
|---|
| 6523 | #define mmMMEA7_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1 |
|---|
| 6524 | #define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS01 0x3569 |
|---|
| 6525 | #define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1 |
|---|
| 6526 | #define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS23 0x356a |
|---|
| 6527 | #define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1 |
|---|
| 6528 | #define mmMMEA7_ADDRDEC0_ADDR_CFG_CS01 0x356b |
|---|
| 6529 | #define mmMMEA7_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1 |
|---|
| 6530 | #define mmMMEA7_ADDRDEC0_ADDR_CFG_CS23 0x356c |
|---|
| 6531 | #define mmMMEA7_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1 |
|---|
| 6532 | #define mmMMEA7_ADDRDEC0_ADDR_SEL_CS01 0x356d |
|---|
| 6533 | #define mmMMEA7_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1 |
|---|
| 6534 | #define mmMMEA7_ADDRDEC0_ADDR_SEL_CS23 0x356e |
|---|
| 6535 | #define mmMMEA7_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1 |
|---|
| 6536 | #define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS01 0x356f |
|---|
| 6537 | #define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1 |
|---|
| 6538 | #define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS23 0x3570 |
|---|
| 6539 | #define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1 |
|---|
| 6540 | #define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS01 0x3571 |
|---|
| 6541 | #define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1 |
|---|
| 6542 | #define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS23 0x3572 |
|---|
| 6543 | #define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1 |
|---|
| 6544 | #define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS01 0x3573 |
|---|
| 6545 | #define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1 |
|---|
| 6546 | #define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS23 0x3574 |
|---|
| 6547 | #define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1 |
|---|
| 6548 | #define mmMMEA7_ADDRDEC0_RM_SEL_CS01 0x3575 |
|---|
| 6549 | #define mmMMEA7_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1 |
|---|
| 6550 | #define mmMMEA7_ADDRDEC0_RM_SEL_CS23 0x3576 |
|---|
| 6551 | #define mmMMEA7_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1 |
|---|
| 6552 | #define mmMMEA7_ADDRDEC0_RM_SEL_SECCS01 0x3577 |
|---|
| 6553 | #define mmMMEA7_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1 |
|---|
| 6554 | #define mmMMEA7_ADDRDEC0_RM_SEL_SECCS23 0x3578 |
|---|
| 6555 | #define mmMMEA7_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1 |
|---|
| 6556 | #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS0 0x3579 |
|---|
| 6557 | #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1 |
|---|
| 6558 | #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS1 0x357a |
|---|
| 6559 | #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1 |
|---|
| 6560 | #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS2 0x357b |
|---|
| 6561 | #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1 |
|---|
| 6562 | #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS3 0x357c |
|---|
| 6563 | #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1 |
|---|
| 6564 | #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS0 0x357d |
|---|
| 6565 | #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1 |
|---|
| 6566 | #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS1 0x357e |
|---|
| 6567 | #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1 |
|---|
| 6568 | #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS2 0x357f |
|---|
| 6569 | #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1 |
|---|
| 6570 | #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS3 0x3580 |
|---|
| 6571 | #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1 |
|---|
| 6572 | #define mmMMEA7_ADDRDEC1_ADDR_MASK_CS01 0x3581 |
|---|
| 6573 | #define mmMMEA7_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1 |
|---|
| 6574 | #define mmMMEA7_ADDRDEC1_ADDR_MASK_CS23 0x3582 |
|---|
| 6575 | #define mmMMEA7_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1 |
|---|
| 6576 | #define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS01 0x3583 |
|---|
| 6577 | #define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1 |
|---|
| 6578 | #define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS23 0x3584 |
|---|
| 6579 | #define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1 |
|---|
| 6580 | #define mmMMEA7_ADDRDEC1_ADDR_CFG_CS01 0x3585 |
|---|
| 6581 | #define mmMMEA7_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1 |
|---|
| 6582 | #define mmMMEA7_ADDRDEC1_ADDR_CFG_CS23 0x3586 |
|---|
| 6583 | #define mmMMEA7_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1 |
|---|
| 6584 | #define mmMMEA7_ADDRDEC1_ADDR_SEL_CS01 0x3587 |
|---|
| 6585 | #define mmMMEA7_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1 |
|---|
| 6586 | #define mmMMEA7_ADDRDEC1_ADDR_SEL_CS23 0x3588 |
|---|
| 6587 | #define mmMMEA7_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1 |
|---|
| 6588 | #define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS01 0x3589 |
|---|
| 6589 | #define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1 |
|---|
| 6590 | #define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS23 0x358a |
|---|
| 6591 | #define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1 |
|---|
| 6592 | #define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS01 0x358b |
|---|
| 6593 | #define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1 |
|---|
| 6594 | #define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS23 0x358c |
|---|
| 6595 | #define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1 |
|---|
| 6596 | #define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS01 0x358d |
|---|
| 6597 | #define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1 |
|---|
| 6598 | #define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS23 0x358e |
|---|
| 6599 | #define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1 |
|---|
| 6600 | #define mmMMEA7_ADDRDEC1_RM_SEL_CS01 0x358f |
|---|
| 6601 | #define mmMMEA7_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1 |
|---|
| 6602 | #define mmMMEA7_ADDRDEC1_RM_SEL_CS23 0x3590 |
|---|
| 6603 | #define mmMMEA7_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1 |
|---|
| 6604 | #define mmMMEA7_ADDRDEC1_RM_SEL_SECCS01 0x3591 |
|---|
| 6605 | #define mmMMEA7_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1 |
|---|
| 6606 | #define mmMMEA7_ADDRDEC1_RM_SEL_SECCS23 0x3592 |
|---|
| 6607 | #define mmMMEA7_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1 |
|---|
| 6608 | #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS0 0x3593 |
|---|
| 6609 | #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1 |
|---|
| 6610 | #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS1 0x3594 |
|---|
| 6611 | #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1 |
|---|
| 6612 | #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS2 0x3595 |
|---|
| 6613 | #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1 |
|---|
| 6614 | #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS3 0x3596 |
|---|
| 6615 | #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1 |
|---|
| 6616 | #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS0 0x3597 |
|---|
| 6617 | #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1 |
|---|
| 6618 | #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS1 0x3598 |
|---|
| 6619 | #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1 |
|---|
| 6620 | #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS2 0x3599 |
|---|
| 6621 | #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1 |
|---|
| 6622 | #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS3 0x359a |
|---|
| 6623 | #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1 |
|---|
| 6624 | #define mmMMEA7_ADDRDEC2_ADDR_MASK_CS01 0x359b |
|---|
| 6625 | #define mmMMEA7_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1 |
|---|
| 6626 | #define mmMMEA7_ADDRDEC2_ADDR_MASK_CS23 0x359c |
|---|
| 6627 | #define mmMMEA7_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1 |
|---|
| 6628 | #define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS01 0x359d |
|---|
| 6629 | #define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1 |
|---|
| 6630 | #define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS23 0x359e |
|---|
| 6631 | #define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1 |
|---|
| 6632 | #define mmMMEA7_ADDRDEC2_ADDR_CFG_CS01 0x359f |
|---|
| 6633 | #define mmMMEA7_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1 |
|---|
| 6634 | #define mmMMEA7_ADDRDEC2_ADDR_CFG_CS23 0x35a0 |
|---|
| 6635 | #define mmMMEA7_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1 |
|---|
| 6636 | #define mmMMEA7_ADDRDEC2_ADDR_SEL_CS01 0x35a1 |
|---|
| 6637 | #define mmMMEA7_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1 |
|---|
| 6638 | #define mmMMEA7_ADDRDEC2_ADDR_SEL_CS23 0x35a2 |
|---|
| 6639 | #define mmMMEA7_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1 |
|---|
| 6640 | #define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS01 0x35a3 |
|---|
| 6641 | #define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1 |
|---|
| 6642 | #define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS23 0x35a4 |
|---|
| 6643 | #define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1 |
|---|
| 6644 | #define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS01 0x35a5 |
|---|
| 6645 | #define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1 |
|---|
| 6646 | #define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS23 0x35a6 |
|---|
| 6647 | #define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1 |
|---|
| 6648 | #define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS01 0x35a7 |
|---|
| 6649 | #define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1 |
|---|
| 6650 | #define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS23 0x35a8 |
|---|
| 6651 | #define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1 |
|---|
| 6652 | #define mmMMEA7_ADDRDEC2_RM_SEL_CS01 0x35a9 |
|---|
| 6653 | #define mmMMEA7_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1 |
|---|
| 6654 | #define mmMMEA7_ADDRDEC2_RM_SEL_CS23 0x35aa |
|---|
| 6655 | #define mmMMEA7_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1 |
|---|
| 6656 | #define mmMMEA7_ADDRDEC2_RM_SEL_SECCS01 0x35ab |
|---|
| 6657 | #define mmMMEA7_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1 |
|---|
| 6658 | #define mmMMEA7_ADDRDEC2_RM_SEL_SECCS23 0x35ac |
|---|
| 6659 | #define mmMMEA7_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1 |
|---|
| 6660 | #define mmMMEA7_ADDRNORMDRAM_GLOBAL_CNTL 0x35ad |
|---|
| 6661 | #define mmMMEA7_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1 |
|---|
| 6662 | #define mmMMEA7_ADDRNORMGMI_GLOBAL_CNTL 0x35ae |
|---|
| 6663 | #define mmMMEA7_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1 |
|---|
| 6664 | #define mmMMEA7_IO_RD_CLI2GRP_MAP0 0x35d5 |
|---|
| 6665 | #define mmMMEA7_IO_RD_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 6666 | #define mmMMEA7_IO_RD_CLI2GRP_MAP1 0x35d6 |
|---|
| 6667 | #define mmMMEA7_IO_RD_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 6668 | #define mmMMEA7_IO_WR_CLI2GRP_MAP0 0x35d7 |
|---|
| 6669 | #define mmMMEA7_IO_WR_CLI2GRP_MAP0_BASE_IDX 1 |
|---|
| 6670 | #define mmMMEA7_IO_WR_CLI2GRP_MAP1 0x35d8 |
|---|
| 6671 | #define mmMMEA7_IO_WR_CLI2GRP_MAP1_BASE_IDX 1 |
|---|
| 6672 | #define mmMMEA7_IO_RD_COMBINE_FLUSH 0x35d9 |
|---|
| 6673 | #define mmMMEA7_IO_RD_COMBINE_FLUSH_BASE_IDX 1 |
|---|
| 6674 | #define mmMMEA7_IO_WR_COMBINE_FLUSH 0x35da |
|---|
| 6675 | #define mmMMEA7_IO_WR_COMBINE_FLUSH_BASE_IDX 1 |
|---|
| 6676 | #define mmMMEA7_IO_GROUP_BURST 0x35db |
|---|
| 6677 | #define mmMMEA7_IO_GROUP_BURST_BASE_IDX 1 |
|---|
| 6678 | #define mmMMEA7_IO_RD_PRI_AGE 0x35dc |
|---|
| 6679 | #define mmMMEA7_IO_RD_PRI_AGE_BASE_IDX 1 |
|---|
| 6680 | #define mmMMEA7_IO_WR_PRI_AGE 0x35dd |
|---|
| 6681 | #define mmMMEA7_IO_WR_PRI_AGE_BASE_IDX 1 |
|---|
| 6682 | #define mmMMEA7_IO_RD_PRI_QUEUING 0x35de |
|---|
| 6683 | #define mmMMEA7_IO_RD_PRI_QUEUING_BASE_IDX 1 |
|---|
| 6684 | #define mmMMEA7_IO_WR_PRI_QUEUING 0x35df |
|---|
| 6685 | #define mmMMEA7_IO_WR_PRI_QUEUING_BASE_IDX 1 |
|---|
| 6686 | #define mmMMEA7_IO_RD_PRI_FIXED 0x35e0 |
|---|
| 6687 | #define mmMMEA7_IO_RD_PRI_FIXED_BASE_IDX 1 |
|---|
| 6688 | #define mmMMEA7_IO_WR_PRI_FIXED 0x35e1 |
|---|
| 6689 | #define mmMMEA7_IO_WR_PRI_FIXED_BASE_IDX 1 |
|---|
| 6690 | #define mmMMEA7_IO_RD_PRI_URGENCY 0x35e2 |
|---|
| 6691 | #define mmMMEA7_IO_RD_PRI_URGENCY_BASE_IDX 1 |
|---|
| 6692 | #define mmMMEA7_IO_WR_PRI_URGENCY 0x35e3 |
|---|
| 6693 | #define mmMMEA7_IO_WR_PRI_URGENCY_BASE_IDX 1 |
|---|
| 6694 | #define mmMMEA7_IO_RD_PRI_URGENCY_MASKING 0x35e4 |
|---|
| 6695 | #define mmMMEA7_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 6696 | #define mmMMEA7_IO_WR_PRI_URGENCY_MASKING 0x35e5 |
|---|
| 6697 | #define mmMMEA7_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1 |
|---|
| 6698 | #define mmMMEA7_IO_RD_PRI_QUANT_PRI1 0x35e6 |
|---|
| 6699 | #define mmMMEA7_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 6700 | #define mmMMEA7_IO_RD_PRI_QUANT_PRI2 0x35e7 |
|---|
| 6701 | #define mmMMEA7_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 6702 | #define mmMMEA7_IO_RD_PRI_QUANT_PRI3 0x35e8 |
|---|
| 6703 | #define mmMMEA7_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 6704 | #define mmMMEA7_IO_WR_PRI_QUANT_PRI1 0x35e9 |
|---|
| 6705 | #define mmMMEA7_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 |
|---|
| 6706 | #define mmMMEA7_IO_WR_PRI_QUANT_PRI2 0x35ea |
|---|
| 6707 | #define mmMMEA7_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 |
|---|
| 6708 | #define mmMMEA7_IO_WR_PRI_QUANT_PRI3 0x35eb |
|---|
| 6709 | #define mmMMEA7_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 |
|---|
| 6710 | #define mmMMEA7_SDP_ARB_DRAM 0x35ec |
|---|
| 6711 | #define mmMMEA7_SDP_ARB_DRAM_BASE_IDX 1 |
|---|
| 6712 | #define mmMMEA7_SDP_ARB_GMI 0x35ed |
|---|
| 6713 | #define mmMMEA7_SDP_ARB_GMI_BASE_IDX 1 |
|---|
| 6714 | #define mmMMEA7_SDP_ARB_FINAL 0x35ee |
|---|
| 6715 | #define mmMMEA7_SDP_ARB_FINAL_BASE_IDX 1 |
|---|
| 6716 | #define mmMMEA7_SDP_DRAM_PRIORITY 0x35ef |
|---|
| 6717 | #define mmMMEA7_SDP_DRAM_PRIORITY_BASE_IDX 1 |
|---|
| 6718 | #define mmMMEA7_SDP_GMI_PRIORITY 0x35f0 |
|---|
| 6719 | #define mmMMEA7_SDP_GMI_PRIORITY_BASE_IDX 1 |
|---|
| 6720 | #define mmMMEA7_SDP_IO_PRIORITY 0x35f1 |
|---|
| 6721 | #define mmMMEA7_SDP_IO_PRIORITY_BASE_IDX 1 |
|---|
| 6722 | #define mmMMEA7_SDP_CREDITS 0x35f2 |
|---|
| 6723 | #define mmMMEA7_SDP_CREDITS_BASE_IDX 1 |
|---|
| 6724 | #define mmMMEA7_SDP_TAG_RESERVE0 0x35f3 |
|---|
| 6725 | #define mmMMEA7_SDP_TAG_RESERVE0_BASE_IDX 1 |
|---|
| 6726 | #define mmMMEA7_SDP_TAG_RESERVE1 0x35f4 |
|---|
| 6727 | #define mmMMEA7_SDP_TAG_RESERVE1_BASE_IDX 1 |
|---|
| 6728 | #define mmMMEA7_SDP_VCC_RESERVE0 0x35f5 |
|---|
| 6729 | #define mmMMEA7_SDP_VCC_RESERVE0_BASE_IDX 1 |
|---|
| 6730 | #define mmMMEA7_SDP_VCC_RESERVE1 0x35f6 |
|---|
| 6731 | #define mmMMEA7_SDP_VCC_RESERVE1_BASE_IDX 1 |
|---|
| 6732 | #define mmMMEA7_SDP_VCD_RESERVE0 0x35f7 |
|---|
| 6733 | #define mmMMEA7_SDP_VCD_RESERVE0_BASE_IDX 1 |
|---|
| 6734 | #define mmMMEA7_SDP_VCD_RESERVE1 0x35f8 |
|---|
| 6735 | #define mmMMEA7_SDP_VCD_RESERVE1_BASE_IDX 1 |
|---|
| 6736 | #define mmMMEA7_SDP_REQ_CNTL 0x35f9 |
|---|
| 6737 | #define mmMMEA7_SDP_REQ_CNTL_BASE_IDX 1 |
|---|
| 6738 | #define mmMMEA7_MISC 0x35fa |
|---|
| 6739 | #define mmMMEA7_MISC_BASE_IDX 1 |
|---|
| 6740 | #define mmMMEA7_LATENCY_SAMPLING 0x35fb |
|---|
| 6741 | #define mmMMEA7_LATENCY_SAMPLING_BASE_IDX 1 |
|---|
| 6742 | #define mmMMEA7_PERFCOUNTER_LO 0x35fc |
|---|
| 6743 | #define mmMMEA7_PERFCOUNTER_LO_BASE_IDX 1 |
|---|
| 6744 | #define mmMMEA7_PERFCOUNTER_HI 0x35fd |
|---|
| 6745 | #define mmMMEA7_PERFCOUNTER_HI_BASE_IDX 1 |
|---|
| 6746 | #define mmMMEA7_PERFCOUNTER0_CFG 0x35fe |
|---|
| 6747 | #define mmMMEA7_PERFCOUNTER0_CFG_BASE_IDX 1 |
|---|
| 6748 | #define mmMMEA7_PERFCOUNTER1_CFG 0x35ff |
|---|
| 6749 | #define mmMMEA7_PERFCOUNTER1_CFG_BASE_IDX 1 |
|---|
| 6750 | #define mmMMEA7_PERFCOUNTER_RSLT_CNTL 0x3600 |
|---|
| 6751 | #define mmMMEA7_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
|---|
| 6752 | #define mmMMEA7_EDC_CNT 0x3606 |
|---|
| 6753 | #define mmMMEA7_EDC_CNT_BASE_IDX 1 |
|---|
| 6754 | #define mmMMEA7_EDC_CNT2 0x3607 |
|---|
| 6755 | #define mmMMEA7_EDC_CNT2_BASE_IDX 1 |
|---|
| 6756 | #define mmMMEA7_DSM_CNTL 0x3608 |
|---|
| 6757 | #define mmMMEA7_DSM_CNTL_BASE_IDX 1 |
|---|
| 6758 | #define mmMMEA7_DSM_CNTLA 0x3609 |
|---|
| 6759 | #define mmMMEA7_DSM_CNTLA_BASE_IDX 1 |
|---|
| 6760 | #define mmMMEA7_DSM_CNTLB 0x360a |
|---|
| 6761 | #define mmMMEA7_DSM_CNTLB_BASE_IDX 1 |
|---|
| 6762 | #define mmMMEA7_DSM_CNTL2 0x360b |
|---|
| 6763 | #define mmMMEA7_DSM_CNTL2_BASE_IDX 1 |
|---|
| 6764 | #define mmMMEA7_DSM_CNTL2A 0x360c |
|---|
| 6765 | #define mmMMEA7_DSM_CNTL2A_BASE_IDX 1 |
|---|
| 6766 | #define mmMMEA7_DSM_CNTL2B 0x360d |
|---|
| 6767 | #define mmMMEA7_DSM_CNTL2B_BASE_IDX 1 |
|---|
| 6768 | #define mmMMEA7_CGTT_CLK_CTRL 0x360f |
|---|
| 6769 | #define mmMMEA7_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 6770 | #define mmMMEA7_EDC_MODE 0x3610 |
|---|
| 6771 | #define mmMMEA7_EDC_MODE_BASE_IDX 1 |
|---|
| 6772 | #define mmMMEA7_ERR_STATUS 0x3611 |
|---|
| 6773 | #define mmMMEA7_ERR_STATUS_BASE_IDX 1 |
|---|
| 6774 | #define mmMMEA7_MISC2 0x3612 |
|---|
| 6775 | #define mmMMEA7_MISC2_BASE_IDX 1 |
|---|
| 6776 | #define mmMMEA7_ADDRDEC_SELECT 0x3613 |
|---|
| 6777 | #define mmMMEA7_ADDRDEC_SELECT_BASE_IDX 1 |
|---|
| 6778 | #define mmMMEA7_EDC_CNT3 0x3614 |
|---|
| 6779 | #define mmMMEA7_EDC_CNT3_BASE_IDX 1 |
|---|
| 6780 | |
|---|
| 6781 | |
|---|
| 6782 | // addressBlock: mmhub_pctldec1 |
|---|
| 6783 | // base address: 0x76300 |
|---|
| 6784 | #define mmPCTL1_CTRL 0x38c0 |
|---|
| 6785 | #define mmPCTL1_CTRL_BASE_IDX 1 |
|---|
| 6786 | #define mmPCTL1_MMHUB_DEEPSLEEP_IB 0x38c1 |
|---|
| 6787 | #define mmPCTL1_MMHUB_DEEPSLEEP_IB_BASE_IDX 1 |
|---|
| 6788 | #define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE 0x38c2 |
|---|
| 6789 | #define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 1 |
|---|
| 6790 | #define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB 0x38c3 |
|---|
| 6791 | #define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX 1 |
|---|
| 6792 | #define mmPCTL1_PG_IGNORE_DEEPSLEEP 0x38c4 |
|---|
| 6793 | #define mmPCTL1_PG_IGNORE_DEEPSLEEP_BASE_IDX 1 |
|---|
| 6794 | #define mmPCTL1_PG_IGNORE_DEEPSLEEP_IB 0x38c5 |
|---|
| 6795 | #define mmPCTL1_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX 1 |
|---|
| 6796 | #define mmPCTL1_SLICE0_CFG_DAGB_BUSY 0x38c6 |
|---|
| 6797 | #define mmPCTL1_SLICE0_CFG_DAGB_BUSY_BASE_IDX 1 |
|---|
| 6798 | #define mmPCTL1_SLICE0_CFG_DS_ALLOW 0x38c7 |
|---|
| 6799 | #define mmPCTL1_SLICE0_CFG_DS_ALLOW_BASE_IDX 1 |
|---|
| 6800 | #define mmPCTL1_SLICE0_CFG_DS_ALLOW_IB 0x38c8 |
|---|
| 6801 | #define mmPCTL1_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX 1 |
|---|
| 6802 | #define mmPCTL1_SLICE1_CFG_DAGB_BUSY 0x38c9 |
|---|
| 6803 | #define mmPCTL1_SLICE1_CFG_DAGB_BUSY_BASE_IDX 1 |
|---|
| 6804 | #define mmPCTL1_SLICE1_CFG_DS_ALLOW 0x38ca |
|---|
| 6805 | #define mmPCTL1_SLICE1_CFG_DS_ALLOW_BASE_IDX 1 |
|---|
| 6806 | #define mmPCTL1_SLICE1_CFG_DS_ALLOW_IB 0x38cb |
|---|
| 6807 | #define mmPCTL1_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX 1 |
|---|
| 6808 | #define mmPCTL1_SLICE2_CFG_DAGB_BUSY 0x38cc |
|---|
| 6809 | #define mmPCTL1_SLICE2_CFG_DAGB_BUSY_BASE_IDX 1 |
|---|
| 6810 | #define mmPCTL1_SLICE2_CFG_DS_ALLOW 0x38cd |
|---|
| 6811 | #define mmPCTL1_SLICE2_CFG_DS_ALLOW_BASE_IDX 1 |
|---|
| 6812 | #define mmPCTL1_SLICE2_CFG_DS_ALLOW_IB 0x38ce |
|---|
| 6813 | #define mmPCTL1_SLICE2_CFG_DS_ALLOW_IB_BASE_IDX 1 |
|---|
| 6814 | #define mmPCTL1_SLICE3_CFG_DAGB_BUSY 0x38cf |
|---|
| 6815 | #define mmPCTL1_SLICE3_CFG_DAGB_BUSY_BASE_IDX 1 |
|---|
| 6816 | #define mmPCTL1_SLICE3_CFG_DS_ALLOW 0x38d0 |
|---|
| 6817 | #define mmPCTL1_SLICE3_CFG_DS_ALLOW_BASE_IDX 1 |
|---|
| 6818 | #define mmPCTL1_SLICE3_CFG_DS_ALLOW_IB 0x38d1 |
|---|
| 6819 | #define mmPCTL1_SLICE3_CFG_DS_ALLOW_IB_BASE_IDX 1 |
|---|
| 6820 | #define mmPCTL1_SLICE4_CFG_DAGB_BUSY 0x38d2 |
|---|
| 6821 | #define mmPCTL1_SLICE4_CFG_DAGB_BUSY_BASE_IDX 1 |
|---|
| 6822 | #define mmPCTL1_SLICE4_CFG_DS_ALLOW 0x38d3 |
|---|
| 6823 | #define mmPCTL1_SLICE4_CFG_DS_ALLOW_BASE_IDX 1 |
|---|
| 6824 | #define mmPCTL1_SLICE4_CFG_DS_ALLOW_IB 0x38d4 |
|---|
| 6825 | #define mmPCTL1_SLICE4_CFG_DS_ALLOW_IB_BASE_IDX 1 |
|---|
| 6826 | #define mmPCTL1_UTCL2_MISC 0x38d5 |
|---|
| 6827 | #define mmPCTL1_UTCL2_MISC_BASE_IDX 1 |
|---|
| 6828 | #define mmPCTL1_SLICE0_MISC 0x38d6 |
|---|
| 6829 | #define mmPCTL1_SLICE0_MISC_BASE_IDX 1 |
|---|
| 6830 | #define mmPCTL1_SLICE1_MISC 0x38d7 |
|---|
| 6831 | #define mmPCTL1_SLICE1_MISC_BASE_IDX 1 |
|---|
| 6832 | #define mmPCTL1_SLICE2_MISC 0x38d8 |
|---|
| 6833 | #define mmPCTL1_SLICE2_MISC_BASE_IDX 1 |
|---|
| 6834 | #define mmPCTL1_SLICE3_MISC 0x38d9 |
|---|
| 6835 | #define mmPCTL1_SLICE3_MISC_BASE_IDX 1 |
|---|
| 6836 | #define mmPCTL1_SLICE4_MISC 0x38da |
|---|
| 6837 | #define mmPCTL1_SLICE4_MISC_BASE_IDX 1 |
|---|
| 6838 | #define mmPCTL1_UTCL2_RENG_EXECUTE 0x38db |
|---|
| 6839 | #define mmPCTL1_UTCL2_RENG_EXECUTE_BASE_IDX 1 |
|---|
| 6840 | #define mmPCTL1_SLICE0_RENG_EXECUTE 0x38dc |
|---|
| 6841 | #define mmPCTL1_SLICE0_RENG_EXECUTE_BASE_IDX 1 |
|---|
| 6842 | #define mmPCTL1_SLICE1_RENG_EXECUTE 0x38dd |
|---|
| 6843 | #define mmPCTL1_SLICE1_RENG_EXECUTE_BASE_IDX 1 |
|---|
| 6844 | #define mmPCTL1_SLICE2_RENG_EXECUTE 0x38de |
|---|
| 6845 | #define mmPCTL1_SLICE2_RENG_EXECUTE_BASE_IDX 1 |
|---|
| 6846 | #define mmPCTL1_SLICE3_RENG_EXECUTE 0x38df |
|---|
| 6847 | #define mmPCTL1_SLICE3_RENG_EXECUTE_BASE_IDX 1 |
|---|
| 6848 | #define mmPCTL1_SLICE4_RENG_EXECUTE 0x38e0 |
|---|
| 6849 | #define mmPCTL1_SLICE4_RENG_EXECUTE_BASE_IDX 1 |
|---|
| 6850 | #define mmPCTL1_UTCL2_RENG_RAM_INDEX 0x38e1 |
|---|
| 6851 | #define mmPCTL1_UTCL2_RENG_RAM_INDEX_BASE_IDX 1 |
|---|
| 6852 | #define mmPCTL1_UTCL2_RENG_RAM_DATA 0x38e2 |
|---|
| 6853 | #define mmPCTL1_UTCL2_RENG_RAM_DATA_BASE_IDX 1 |
|---|
| 6854 | #define mmPCTL1_SLICE0_RENG_RAM_INDEX 0x38e3 |
|---|
| 6855 | #define mmPCTL1_SLICE0_RENG_RAM_INDEX_BASE_IDX 1 |
|---|
| 6856 | #define mmPCTL1_SLICE0_RENG_RAM_DATA 0x38e4 |
|---|
| 6857 | #define mmPCTL1_SLICE0_RENG_RAM_DATA_BASE_IDX 1 |
|---|
| 6858 | #define mmPCTL1_SLICE1_RENG_RAM_INDEX 0x38e5 |
|---|
| 6859 | #define mmPCTL1_SLICE1_RENG_RAM_INDEX_BASE_IDX 1 |
|---|
| 6860 | #define mmPCTL1_SLICE1_RENG_RAM_DATA 0x38e6 |
|---|
| 6861 | #define mmPCTL1_SLICE1_RENG_RAM_DATA_BASE_IDX 1 |
|---|
| 6862 | #define mmPCTL1_SLICE2_RENG_RAM_INDEX 0x38e7 |
|---|
| 6863 | #define mmPCTL1_SLICE2_RENG_RAM_INDEX_BASE_IDX 1 |
|---|
| 6864 | #define mmPCTL1_SLICE2_RENG_RAM_DATA 0x38e8 |
|---|
| 6865 | #define mmPCTL1_SLICE2_RENG_RAM_DATA_BASE_IDX 1 |
|---|
| 6866 | #define mmPCTL1_SLICE3_RENG_RAM_INDEX 0x38e9 |
|---|
| 6867 | #define mmPCTL1_SLICE3_RENG_RAM_INDEX_BASE_IDX 1 |
|---|
| 6868 | #define mmPCTL1_SLICE3_RENG_RAM_DATA 0x38ea |
|---|
| 6869 | #define mmPCTL1_SLICE3_RENG_RAM_DATA_BASE_IDX 1 |
|---|
| 6870 | #define mmPCTL1_SLICE4_RENG_RAM_INDEX 0x38eb |
|---|
| 6871 | #define mmPCTL1_SLICE4_RENG_RAM_INDEX_BASE_IDX 1 |
|---|
| 6872 | #define mmPCTL1_SLICE4_RENG_RAM_DATA 0x38ec |
|---|
| 6873 | #define mmPCTL1_SLICE4_RENG_RAM_DATA_BASE_IDX 1 |
|---|
| 6874 | #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 0x38ed |
|---|
| 6875 | #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 |
|---|
| 6876 | #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 0x38ee |
|---|
| 6877 | #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 |
|---|
| 6878 | #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 0x38ef |
|---|
| 6879 | #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 |
|---|
| 6880 | #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 0x38f0 |
|---|
| 6881 | #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 |
|---|
| 6882 | #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 0x38f1 |
|---|
| 6883 | #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 |
|---|
| 6884 | #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x38f2 |
|---|
| 6885 | #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 |
|---|
| 6886 | #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x38f3 |
|---|
| 6887 | #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 |
|---|
| 6888 | #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 0x38f4 |
|---|
| 6889 | #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 |
|---|
| 6890 | #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 0x38f5 |
|---|
| 6891 | #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 |
|---|
| 6892 | #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 0x38f6 |
|---|
| 6893 | #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 |
|---|
| 6894 | #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 0x38f7 |
|---|
| 6895 | #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 |
|---|
| 6896 | #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 0x38f8 |
|---|
| 6897 | #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 |
|---|
| 6898 | #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 0x38f9 |
|---|
| 6899 | #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 |
|---|
| 6900 | #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x38fa |
|---|
| 6901 | #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 |
|---|
| 6902 | #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 0x38fb |
|---|
| 6903 | #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 |
|---|
| 6904 | #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 0x38fc |
|---|
| 6905 | #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 |
|---|
| 6906 | #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 0x38fd |
|---|
| 6907 | #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 |
|---|
| 6908 | #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 0x38fe |
|---|
| 6909 | #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 |
|---|
| 6910 | #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 0x38ff |
|---|
| 6911 | #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 |
|---|
| 6912 | #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 0x3900 |
|---|
| 6913 | #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 |
|---|
| 6914 | #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x3901 |
|---|
| 6915 | #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 |
|---|
| 6916 | #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0 0x3902 |
|---|
| 6917 | #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 |
|---|
| 6918 | #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1 0x3903 |
|---|
| 6919 | #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 |
|---|
| 6920 | #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2 0x3904 |
|---|
| 6921 | #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 |
|---|
| 6922 | #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3 0x3905 |
|---|
| 6923 | #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 |
|---|
| 6924 | #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4 0x3906 |
|---|
| 6925 | #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 |
|---|
| 6926 | #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x3907 |
|---|
| 6927 | #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 |
|---|
| 6928 | #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x3908 |
|---|
| 6929 | #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 |
|---|
| 6930 | #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0 0x3909 |
|---|
| 6931 | #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 |
|---|
| 6932 | #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1 0x390a |
|---|
| 6933 | #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 |
|---|
| 6934 | #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2 0x390b |
|---|
| 6935 | #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 |
|---|
| 6936 | #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3 0x390c |
|---|
| 6937 | #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 |
|---|
| 6938 | #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4 0x390d |
|---|
| 6939 | #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 |
|---|
| 6940 | #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0 0x390e |
|---|
| 6941 | #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 |
|---|
| 6942 | #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1 0x390f |
|---|
| 6943 | #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 |
|---|
| 6944 | #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0 0x3910 |
|---|
| 6945 | #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 |
|---|
| 6946 | #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1 0x3911 |
|---|
| 6947 | #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 |
|---|
| 6948 | #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2 0x3912 |
|---|
| 6949 | #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 |
|---|
| 6950 | #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3 0x3913 |
|---|
| 6951 | #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 |
|---|
| 6952 | #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4 0x3914 |
|---|
| 6953 | #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 |
|---|
| 6954 | #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0 0x3915 |
|---|
| 6955 | #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 |
|---|
| 6956 | #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1 0x3916 |
|---|
| 6957 | #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 |
|---|
| 6958 | |
|---|
| 6959 | |
|---|
| 6960 | // addressBlock: mmhub_l1tlb_vml1dec:1 |
|---|
| 6961 | // base address: 0x76500 |
|---|
| 6962 | #define mmVML1_1_MC_VM_MX_L1_TLB0_STATUS 0x3948 |
|---|
| 6963 | #define mmVML1_1_MC_VM_MX_L1_TLB0_STATUS_BASE_IDX 1 |
|---|
| 6964 | #define mmVML1_1_MC_VM_MX_L1_TLB1_STATUS 0x3949 |
|---|
| 6965 | #define mmVML1_1_MC_VM_MX_L1_TLB1_STATUS_BASE_IDX 1 |
|---|
| 6966 | #define mmVML1_1_MC_VM_MX_L1_TLB2_STATUS 0x394a |
|---|
| 6967 | #define mmVML1_1_MC_VM_MX_L1_TLB2_STATUS_BASE_IDX 1 |
|---|
| 6968 | #define mmVML1_1_MC_VM_MX_L1_TLB3_STATUS 0x394b |
|---|
| 6969 | #define mmVML1_1_MC_VM_MX_L1_TLB3_STATUS_BASE_IDX 1 |
|---|
| 6970 | #define mmVML1_1_MC_VM_MX_L1_TLB4_STATUS 0x394c |
|---|
| 6971 | #define mmVML1_1_MC_VM_MX_L1_TLB4_STATUS_BASE_IDX 1 |
|---|
| 6972 | #define mmVML1_1_MC_VM_MX_L1_TLB5_STATUS 0x394d |
|---|
| 6973 | #define mmVML1_1_MC_VM_MX_L1_TLB5_STATUS_BASE_IDX 1 |
|---|
| 6974 | #define mmVML1_1_MC_VM_MX_L1_TLB6_STATUS 0x394e |
|---|
| 6975 | #define mmVML1_1_MC_VM_MX_L1_TLB6_STATUS_BASE_IDX 1 |
|---|
| 6976 | #define mmVML1_1_MC_VM_MX_L1_TLB7_STATUS 0x394f |
|---|
| 6977 | #define mmVML1_1_MC_VM_MX_L1_TLB7_STATUS_BASE_IDX 1 |
|---|
| 6978 | |
|---|
| 6979 | |
|---|
| 6980 | // addressBlock: mmhub_l1tlb_vml1pldec:1 |
|---|
| 6981 | // base address: 0x76580 |
|---|
| 6982 | #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG 0x3960 |
|---|
| 6983 | #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 1 |
|---|
| 6984 | #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG 0x3961 |
|---|
| 6985 | #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 1 |
|---|
| 6986 | #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG 0x3962 |
|---|
| 6987 | #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 1 |
|---|
| 6988 | #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG 0x3963 |
|---|
| 6989 | #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 1 |
|---|
| 6990 | #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x3964 |
|---|
| 6991 | #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
|---|
| 6992 | |
|---|
| 6993 | |
|---|
| 6994 | // addressBlock: mmhub_l1tlb_vml1prdec:1 |
|---|
| 6995 | // base address: 0x765c0 |
|---|
| 6996 | #define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO 0x3970 |
|---|
| 6997 | #define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 1 |
|---|
| 6998 | #define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI 0x3971 |
|---|
| 6999 | #define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 1 |
|---|
| 7000 | |
|---|
| 7001 | |
|---|
| 7002 | // addressBlock: mmhub_utcl2_atcl2dec:1 |
|---|
| 7003 | // base address: 0x76600 |
|---|
| 7004 | #define mmATCL2_1_ATC_L2_CNTL 0x3980 |
|---|
| 7005 | #define mmATCL2_1_ATC_L2_CNTL_BASE_IDX 1 |
|---|
| 7006 | #define mmATCL2_1_ATC_L2_CNTL2 0x3981 |
|---|
| 7007 | #define mmATCL2_1_ATC_L2_CNTL2_BASE_IDX 1 |
|---|
| 7008 | #define mmATCL2_1_ATC_L2_CACHE_DATA0 0x3984 |
|---|
| 7009 | #define mmATCL2_1_ATC_L2_CACHE_DATA0_BASE_IDX 1 |
|---|
| 7010 | #define mmATCL2_1_ATC_L2_CACHE_DATA1 0x3985 |
|---|
| 7011 | #define mmATCL2_1_ATC_L2_CACHE_DATA1_BASE_IDX 1 |
|---|
| 7012 | #define mmATCL2_1_ATC_L2_CACHE_DATA2 0x3986 |
|---|
| 7013 | #define mmATCL2_1_ATC_L2_CACHE_DATA2_BASE_IDX 1 |
|---|
| 7014 | #define mmATCL2_1_ATC_L2_CNTL3 0x3987 |
|---|
| 7015 | #define mmATCL2_1_ATC_L2_CNTL3_BASE_IDX 1 |
|---|
| 7016 | #define mmATCL2_1_ATC_L2_STATUS 0x3988 |
|---|
| 7017 | #define mmATCL2_1_ATC_L2_STATUS_BASE_IDX 1 |
|---|
| 7018 | #define mmATCL2_1_ATC_L2_STATUS2 0x3989 |
|---|
| 7019 | #define mmATCL2_1_ATC_L2_STATUS2_BASE_IDX 1 |
|---|
| 7020 | #define mmATCL2_1_ATC_L2_STATUS3 0x398a |
|---|
| 7021 | #define mmATCL2_1_ATC_L2_STATUS3_BASE_IDX 1 |
|---|
| 7022 | #define mmATCL2_1_ATC_L2_MISC_CG 0x398b |
|---|
| 7023 | #define mmATCL2_1_ATC_L2_MISC_CG_BASE_IDX 1 |
|---|
| 7024 | #define mmATCL2_1_ATC_L2_MEM_POWER_LS 0x398c |
|---|
| 7025 | #define mmATCL2_1_ATC_L2_MEM_POWER_LS_BASE_IDX 1 |
|---|
| 7026 | #define mmATCL2_1_ATC_L2_CGTT_CLK_CTRL 0x398d |
|---|
| 7027 | #define mmATCL2_1_ATC_L2_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 7028 | #define mmATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX 0x398e |
|---|
| 7029 | #define mmATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX 1 |
|---|
| 7030 | #define mmATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX 0x398f |
|---|
| 7031 | #define mmATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX 1 |
|---|
| 7032 | #define mmATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL 0x3990 |
|---|
| 7033 | #define mmATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX 1 |
|---|
| 7034 | #define mmATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL 0x3991 |
|---|
| 7035 | #define mmATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX 1 |
|---|
| 7036 | #define mmATCL2_1_ATC_L2_CNTL4 0x3992 |
|---|
| 7037 | #define mmATCL2_1_ATC_L2_CNTL4_BASE_IDX 1 |
|---|
| 7038 | #define mmATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES 0x3993 |
|---|
| 7039 | #define mmATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1 |
|---|
| 7040 | |
|---|
| 7041 | |
|---|
| 7042 | // addressBlock: mmhub_utcl2_vml2pfdec:1 |
|---|
| 7043 | // base address: 0x76700 |
|---|
| 7044 | #define mmVML2PF1_VM_L2_CNTL 0x39c0 |
|---|
| 7045 | #define mmVML2PF1_VM_L2_CNTL_BASE_IDX 1 |
|---|
| 7046 | #define mmVML2PF1_VM_L2_CNTL2 0x39c1 |
|---|
| 7047 | #define mmVML2PF1_VM_L2_CNTL2_BASE_IDX 1 |
|---|
| 7048 | #define mmVML2PF1_VM_L2_CNTL3 0x39c2 |
|---|
| 7049 | #define mmVML2PF1_VM_L2_CNTL3_BASE_IDX 1 |
|---|
| 7050 | #define mmVML2PF1_VM_L2_STATUS 0x39c3 |
|---|
| 7051 | #define mmVML2PF1_VM_L2_STATUS_BASE_IDX 1 |
|---|
| 7052 | #define mmVML2PF1_VM_DUMMY_PAGE_FAULT_CNTL 0x39c4 |
|---|
| 7053 | #define mmVML2PF1_VM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 1 |
|---|
| 7054 | #define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32 0x39c5 |
|---|
| 7055 | #define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 1 |
|---|
| 7056 | #define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32 0x39c6 |
|---|
| 7057 | #define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 1 |
|---|
| 7058 | #define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL 0x39c7 |
|---|
| 7059 | #define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 1 |
|---|
| 7060 | #define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL2 0x39c8 |
|---|
| 7061 | #define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 1 |
|---|
| 7062 | #define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3 0x39c9 |
|---|
| 7063 | #define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 1 |
|---|
| 7064 | #define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4 0x39ca |
|---|
| 7065 | #define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 1 |
|---|
| 7066 | #define mmVML2PF1_VM_L2_PROTECTION_FAULT_STATUS 0x39cb |
|---|
| 7067 | #define mmVML2PF1_VM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 1 |
|---|
| 7068 | #define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32 0x39cc |
|---|
| 7069 | #define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 1 |
|---|
| 7070 | #define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32 0x39cd |
|---|
| 7071 | #define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 1 |
|---|
| 7072 | #define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x39ce |
|---|
| 7073 | #define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 1 |
|---|
| 7074 | #define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x39cf |
|---|
| 7075 | #define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 1 |
|---|
| 7076 | #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x39d1 |
|---|
| 7077 | #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 1 |
|---|
| 7078 | #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x39d2 |
|---|
| 7079 | #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 1 |
|---|
| 7080 | #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x39d3 |
|---|
| 7081 | #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 1 |
|---|
| 7082 | #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x39d4 |
|---|
| 7083 | #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 1 |
|---|
| 7084 | #define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x39d5 |
|---|
| 7085 | #define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 1 |
|---|
| 7086 | #define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x39d6 |
|---|
| 7087 | #define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 1 |
|---|
| 7088 | #define mmVML2PF1_VM_L2_CNTL4 0x39d7 |
|---|
| 7089 | #define mmVML2PF1_VM_L2_CNTL4_BASE_IDX 1 |
|---|
| 7090 | #define mmVML2PF1_VM_L2_MM_GROUP_RT_CLASSES 0x39d8 |
|---|
| 7091 | #define mmVML2PF1_VM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1 |
|---|
| 7092 | #define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID 0x39d9 |
|---|
| 7093 | #define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 1 |
|---|
| 7094 | #define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2 0x39da |
|---|
| 7095 | #define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 1 |
|---|
| 7096 | #define mmVML2PF1_VM_L2_CACHE_PARITY_CNTL 0x39db |
|---|
| 7097 | #define mmVML2PF1_VM_L2_CACHE_PARITY_CNTL_BASE_IDX 1 |
|---|
| 7098 | #define mmVML2PF1_VM_L2_CGTT_CLK_CTRL 0x39de |
|---|
| 7099 | #define mmVML2PF1_VM_L2_CGTT_CLK_CTRL_BASE_IDX 1 |
|---|
| 7100 | |
|---|
| 7101 | |
|---|
| 7102 | // addressBlock: mmhub_utcl2_vml2vcdec:1 |
|---|
| 7103 | // base address: 0x76800 |
|---|
| 7104 | #define mmVML2VC1_VM_CONTEXT0_CNTL 0x3a00 |
|---|
| 7105 | #define mmVML2VC1_VM_CONTEXT0_CNTL_BASE_IDX 1 |
|---|
| 7106 | #define mmVML2VC1_VM_CONTEXT1_CNTL 0x3a01 |
|---|
| 7107 | #define mmVML2VC1_VM_CONTEXT1_CNTL_BASE_IDX 1 |
|---|
| 7108 | #define mmVML2VC1_VM_CONTEXT2_CNTL 0x3a02 |
|---|
| 7109 | #define mmVML2VC1_VM_CONTEXT2_CNTL_BASE_IDX 1 |
|---|
| 7110 | #define mmVML2VC1_VM_CONTEXT3_CNTL 0x3a03 |
|---|
| 7111 | #define mmVML2VC1_VM_CONTEXT3_CNTL_BASE_IDX 1 |
|---|
| 7112 | #define mmVML2VC1_VM_CONTEXT4_CNTL 0x3a04 |
|---|
| 7113 | #define mmVML2VC1_VM_CONTEXT4_CNTL_BASE_IDX 1 |
|---|
| 7114 | #define mmVML2VC1_VM_CONTEXT5_CNTL 0x3a05 |
|---|
| 7115 | #define mmVML2VC1_VM_CONTEXT5_CNTL_BASE_IDX 1 |
|---|
| 7116 | #define mmVML2VC1_VM_CONTEXT6_CNTL 0x3a06 |
|---|
| 7117 | #define mmVML2VC1_VM_CONTEXT6_CNTL_BASE_IDX 1 |
|---|
| 7118 | #define mmVML2VC1_VM_CONTEXT7_CNTL 0x3a07 |
|---|
| 7119 | #define mmVML2VC1_VM_CONTEXT7_CNTL_BASE_IDX 1 |
|---|
| 7120 | #define mmVML2VC1_VM_CONTEXT8_CNTL 0x3a08 |
|---|
| 7121 | #define mmVML2VC1_VM_CONTEXT8_CNTL_BASE_IDX 1 |
|---|
| 7122 | #define mmVML2VC1_VM_CONTEXT9_CNTL 0x3a09 |
|---|
| 7123 | #define mmVML2VC1_VM_CONTEXT9_CNTL_BASE_IDX 1 |
|---|
| 7124 | #define mmVML2VC1_VM_CONTEXT10_CNTL 0x3a0a |
|---|
| 7125 | #define mmVML2VC1_VM_CONTEXT10_CNTL_BASE_IDX 1 |
|---|
| 7126 | #define mmVML2VC1_VM_CONTEXT11_CNTL 0x3a0b |
|---|
| 7127 | #define mmVML2VC1_VM_CONTEXT11_CNTL_BASE_IDX 1 |
|---|
| 7128 | #define mmVML2VC1_VM_CONTEXT12_CNTL 0x3a0c |
|---|
| 7129 | #define mmVML2VC1_VM_CONTEXT12_CNTL_BASE_IDX 1 |
|---|
| 7130 | #define mmVML2VC1_VM_CONTEXT13_CNTL 0x3a0d |
|---|
| 7131 | #define mmVML2VC1_VM_CONTEXT13_CNTL_BASE_IDX 1 |
|---|
| 7132 | #define mmVML2VC1_VM_CONTEXT14_CNTL 0x3a0e |
|---|
| 7133 | #define mmVML2VC1_VM_CONTEXT14_CNTL_BASE_IDX 1 |
|---|
| 7134 | #define mmVML2VC1_VM_CONTEXT15_CNTL 0x3a0f |
|---|
| 7135 | #define mmVML2VC1_VM_CONTEXT15_CNTL_BASE_IDX 1 |
|---|
| 7136 | #define mmVML2VC1_VM_CONTEXTS_DISABLE 0x3a10 |
|---|
| 7137 | #define mmVML2VC1_VM_CONTEXTS_DISABLE_BASE_IDX 1 |
|---|
| 7138 | #define mmVML2VC1_VM_INVALIDATE_ENG0_SEM 0x3a11 |
|---|
| 7139 | #define mmVML2VC1_VM_INVALIDATE_ENG0_SEM_BASE_IDX 1 |
|---|
| 7140 | #define mmVML2VC1_VM_INVALIDATE_ENG1_SEM 0x3a12 |
|---|
| 7141 | #define mmVML2VC1_VM_INVALIDATE_ENG1_SEM_BASE_IDX 1 |
|---|
| 7142 | #define mmVML2VC1_VM_INVALIDATE_ENG2_SEM 0x3a13 |
|---|
| 7143 | #define mmVML2VC1_VM_INVALIDATE_ENG2_SEM_BASE_IDX 1 |
|---|
| 7144 | #define mmVML2VC1_VM_INVALIDATE_ENG3_SEM 0x3a14 |
|---|
| 7145 | #define mmVML2VC1_VM_INVALIDATE_ENG3_SEM_BASE_IDX 1 |
|---|
| 7146 | #define mmVML2VC1_VM_INVALIDATE_ENG4_SEM 0x3a15 |
|---|
| 7147 | #define mmVML2VC1_VM_INVALIDATE_ENG4_SEM_BASE_IDX 1 |
|---|
| 7148 | #define mmVML2VC1_VM_INVALIDATE_ENG5_SEM 0x3a16 |
|---|
| 7149 | #define mmVML2VC1_VM_INVALIDATE_ENG5_SEM_BASE_IDX 1 |
|---|
| 7150 | #define mmVML2VC1_VM_INVALIDATE_ENG6_SEM 0x3a17 |
|---|
| 7151 | #define mmVML2VC1_VM_INVALIDATE_ENG6_SEM_BASE_IDX 1 |
|---|
| 7152 | #define mmVML2VC1_VM_INVALIDATE_ENG7_SEM 0x3a18 |
|---|
| 7153 | #define mmVML2VC1_VM_INVALIDATE_ENG7_SEM_BASE_IDX 1 |
|---|
| 7154 | #define mmVML2VC1_VM_INVALIDATE_ENG8_SEM 0x3a19 |
|---|
| 7155 | #define mmVML2VC1_VM_INVALIDATE_ENG8_SEM_BASE_IDX 1 |
|---|
| 7156 | #define mmVML2VC1_VM_INVALIDATE_ENG9_SEM 0x3a1a |
|---|
| 7157 | #define mmVML2VC1_VM_INVALIDATE_ENG9_SEM_BASE_IDX 1 |
|---|
| 7158 | #define mmVML2VC1_VM_INVALIDATE_ENG10_SEM 0x3a1b |
|---|
| 7159 | #define mmVML2VC1_VM_INVALIDATE_ENG10_SEM_BASE_IDX 1 |
|---|
| 7160 | #define mmVML2VC1_VM_INVALIDATE_ENG11_SEM 0x3a1c |
|---|
| 7161 | #define mmVML2VC1_VM_INVALIDATE_ENG11_SEM_BASE_IDX 1 |
|---|
| 7162 | #define mmVML2VC1_VM_INVALIDATE_ENG12_SEM 0x3a1d |
|---|
| 7163 | #define mmVML2VC1_VM_INVALIDATE_ENG12_SEM_BASE_IDX 1 |
|---|
| 7164 | #define mmVML2VC1_VM_INVALIDATE_ENG13_SEM 0x3a1e |
|---|
| 7165 | #define mmVML2VC1_VM_INVALIDATE_ENG13_SEM_BASE_IDX 1 |
|---|
| 7166 | #define mmVML2VC1_VM_INVALIDATE_ENG14_SEM 0x3a1f |
|---|
| 7167 | #define mmVML2VC1_VM_INVALIDATE_ENG14_SEM_BASE_IDX 1 |
|---|
| 7168 | #define mmVML2VC1_VM_INVALIDATE_ENG15_SEM 0x3a20 |
|---|
| 7169 | #define mmVML2VC1_VM_INVALIDATE_ENG15_SEM_BASE_IDX 1 |
|---|
| 7170 | #define mmVML2VC1_VM_INVALIDATE_ENG16_SEM 0x3a21 |
|---|
| 7171 | #define mmVML2VC1_VM_INVALIDATE_ENG16_SEM_BASE_IDX 1 |
|---|
| 7172 | #define mmVML2VC1_VM_INVALIDATE_ENG17_SEM 0x3a22 |
|---|
| 7173 | #define mmVML2VC1_VM_INVALIDATE_ENG17_SEM_BASE_IDX 1 |
|---|
| 7174 | #define mmVML2VC1_VM_INVALIDATE_ENG0_REQ 0x3a23 |
|---|
| 7175 | #define mmVML2VC1_VM_INVALIDATE_ENG0_REQ_BASE_IDX 1 |
|---|
| 7176 | #define mmVML2VC1_VM_INVALIDATE_ENG1_REQ 0x3a24 |
|---|
| 7177 | #define mmVML2VC1_VM_INVALIDATE_ENG1_REQ_BASE_IDX 1 |
|---|
| 7178 | #define mmVML2VC1_VM_INVALIDATE_ENG2_REQ 0x3a25 |
|---|
| 7179 | #define mmVML2VC1_VM_INVALIDATE_ENG2_REQ_BASE_IDX 1 |
|---|
| 7180 | #define mmVML2VC1_VM_INVALIDATE_ENG3_REQ 0x3a26 |
|---|
| 7181 | #define mmVML2VC1_VM_INVALIDATE_ENG3_REQ_BASE_IDX 1 |
|---|
| 7182 | #define mmVML2VC1_VM_INVALIDATE_ENG4_REQ 0x3a27 |
|---|
| 7183 | #define mmVML2VC1_VM_INVALIDATE_ENG4_REQ_BASE_IDX 1 |
|---|
| 7184 | #define mmVML2VC1_VM_INVALIDATE_ENG5_REQ 0x3a28 |
|---|
| 7185 | #define mmVML2VC1_VM_INVALIDATE_ENG5_REQ_BASE_IDX 1 |
|---|
| 7186 | #define mmVML2VC1_VM_INVALIDATE_ENG6_REQ 0x3a29 |
|---|
| 7187 | #define mmVML2VC1_VM_INVALIDATE_ENG6_REQ_BASE_IDX 1 |
|---|
| 7188 | #define mmVML2VC1_VM_INVALIDATE_ENG7_REQ 0x3a2a |
|---|
| 7189 | #define mmVML2VC1_VM_INVALIDATE_ENG7_REQ_BASE_IDX 1 |
|---|
| 7190 | #define mmVML2VC1_VM_INVALIDATE_ENG8_REQ 0x3a2b |
|---|
| 7191 | #define mmVML2VC1_VM_INVALIDATE_ENG8_REQ_BASE_IDX 1 |
|---|
| 7192 | #define mmVML2VC1_VM_INVALIDATE_ENG9_REQ 0x3a2c |
|---|
| 7193 | #define mmVML2VC1_VM_INVALIDATE_ENG9_REQ_BASE_IDX 1 |
|---|
| 7194 | #define mmVML2VC1_VM_INVALIDATE_ENG10_REQ 0x3a2d |
|---|
| 7195 | #define mmVML2VC1_VM_INVALIDATE_ENG10_REQ_BASE_IDX 1 |
|---|
| 7196 | #define mmVML2VC1_VM_INVALIDATE_ENG11_REQ 0x3a2e |
|---|
| 7197 | #define mmVML2VC1_VM_INVALIDATE_ENG11_REQ_BASE_IDX 1 |
|---|
| 7198 | #define mmVML2VC1_VM_INVALIDATE_ENG12_REQ 0x3a2f |
|---|
| 7199 | #define mmVML2VC1_VM_INVALIDATE_ENG12_REQ_BASE_IDX 1 |
|---|
| 7200 | #define mmVML2VC1_VM_INVALIDATE_ENG13_REQ 0x3a30 |
|---|
| 7201 | #define mmVML2VC1_VM_INVALIDATE_ENG13_REQ_BASE_IDX 1 |
|---|
| 7202 | #define mmVML2VC1_VM_INVALIDATE_ENG14_REQ 0x3a31 |
|---|
| 7203 | #define mmVML2VC1_VM_INVALIDATE_ENG14_REQ_BASE_IDX 1 |
|---|
| 7204 | #define mmVML2VC1_VM_INVALIDATE_ENG15_REQ 0x3a32 |
|---|
| 7205 | #define mmVML2VC1_VM_INVALIDATE_ENG15_REQ_BASE_IDX 1 |
|---|
| 7206 | #define mmVML2VC1_VM_INVALIDATE_ENG16_REQ 0x3a33 |
|---|
| 7207 | #define mmVML2VC1_VM_INVALIDATE_ENG16_REQ_BASE_IDX 1 |
|---|
| 7208 | #define mmVML2VC1_VM_INVALIDATE_ENG17_REQ 0x3a34 |
|---|
| 7209 | #define mmVML2VC1_VM_INVALIDATE_ENG17_REQ_BASE_IDX 1 |
|---|
| 7210 | #define mmVML2VC1_VM_INVALIDATE_ENG0_ACK 0x3a35 |
|---|
| 7211 | #define mmVML2VC1_VM_INVALIDATE_ENG0_ACK_BASE_IDX 1 |
|---|
| 7212 | #define mmVML2VC1_VM_INVALIDATE_ENG1_ACK 0x3a36 |
|---|
| 7213 | #define mmVML2VC1_VM_INVALIDATE_ENG1_ACK_BASE_IDX 1 |
|---|
| 7214 | #define mmVML2VC1_VM_INVALIDATE_ENG2_ACK 0x3a37 |
|---|
| 7215 | #define mmVML2VC1_VM_INVALIDATE_ENG2_ACK_BASE_IDX 1 |
|---|
| 7216 | #define mmVML2VC1_VM_INVALIDATE_ENG3_ACK 0x3a38 |
|---|
| 7217 | #define mmVML2VC1_VM_INVALIDATE_ENG3_ACK_BASE_IDX 1 |
|---|
| 7218 | #define mmVML2VC1_VM_INVALIDATE_ENG4_ACK 0x3a39 |
|---|
| 7219 | #define mmVML2VC1_VM_INVALIDATE_ENG4_ACK_BASE_IDX 1 |
|---|
| 7220 | #define mmVML2VC1_VM_INVALIDATE_ENG5_ACK 0x3a3a |
|---|
| 7221 | #define mmVML2VC1_VM_INVALIDATE_ENG5_ACK_BASE_IDX 1 |
|---|
| 7222 | #define mmVML2VC1_VM_INVALIDATE_ENG6_ACK 0x3a3b |
|---|
| 7223 | #define mmVML2VC1_VM_INVALIDATE_ENG6_ACK_BASE_IDX 1 |
|---|
| 7224 | #define mmVML2VC1_VM_INVALIDATE_ENG7_ACK 0x3a3c |
|---|
| 7225 | #define mmVML2VC1_VM_INVALIDATE_ENG7_ACK_BASE_IDX 1 |
|---|
| 7226 | #define mmVML2VC1_VM_INVALIDATE_ENG8_ACK 0x3a3d |
|---|
| 7227 | #define mmVML2VC1_VM_INVALIDATE_ENG8_ACK_BASE_IDX 1 |
|---|
| 7228 | #define mmVML2VC1_VM_INVALIDATE_ENG9_ACK 0x3a3e |
|---|
| 7229 | #define mmVML2VC1_VM_INVALIDATE_ENG9_ACK_BASE_IDX 1 |
|---|
| 7230 | #define mmVML2VC1_VM_INVALIDATE_ENG10_ACK 0x3a3f |
|---|
| 7231 | #define mmVML2VC1_VM_INVALIDATE_ENG10_ACK_BASE_IDX 1 |
|---|
| 7232 | #define mmVML2VC1_VM_INVALIDATE_ENG11_ACK 0x3a40 |
|---|
| 7233 | #define mmVML2VC1_VM_INVALIDATE_ENG11_ACK_BASE_IDX 1 |
|---|
| 7234 | #define mmVML2VC1_VM_INVALIDATE_ENG12_ACK 0x3a41 |
|---|
| 7235 | #define mmVML2VC1_VM_INVALIDATE_ENG12_ACK_BASE_IDX 1 |
|---|
| 7236 | #define mmVML2VC1_VM_INVALIDATE_ENG13_ACK 0x3a42 |
|---|
| 7237 | #define mmVML2VC1_VM_INVALIDATE_ENG13_ACK_BASE_IDX 1 |
|---|
| 7238 | #define mmVML2VC1_VM_INVALIDATE_ENG14_ACK 0x3a43 |
|---|
| 7239 | #define mmVML2VC1_VM_INVALIDATE_ENG14_ACK_BASE_IDX 1 |
|---|
| 7240 | #define mmVML2VC1_VM_INVALIDATE_ENG15_ACK 0x3a44 |
|---|
| 7241 | #define mmVML2VC1_VM_INVALIDATE_ENG15_ACK_BASE_IDX 1 |
|---|
| 7242 | #define mmVML2VC1_VM_INVALIDATE_ENG16_ACK 0x3a45 |
|---|
| 7243 | #define mmVML2VC1_VM_INVALIDATE_ENG16_ACK_BASE_IDX 1 |
|---|
| 7244 | #define mmVML2VC1_VM_INVALIDATE_ENG17_ACK 0x3a46 |
|---|
| 7245 | #define mmVML2VC1_VM_INVALIDATE_ENG17_ACK_BASE_IDX 1 |
|---|
| 7246 | #define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x3a47 |
|---|
| 7247 | #define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 7248 | #define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x3a48 |
|---|
| 7249 | #define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 7250 | #define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x3a49 |
|---|
| 7251 | #define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 7252 | #define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x3a4a |
|---|
| 7253 | #define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 7254 | #define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x3a4b |
|---|
| 7255 | #define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 7256 | #define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x3a4c |
|---|
| 7257 | #define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 7258 | #define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x3a4d |
|---|
| 7259 | #define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 7260 | #define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x3a4e |
|---|
| 7261 | #define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 7262 | #define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x3a4f |
|---|
| 7263 | #define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 7264 | #define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x3a50 |
|---|
| 7265 | #define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 7266 | #define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x3a51 |
|---|
| 7267 | #define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 7268 | #define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x3a52 |
|---|
| 7269 | #define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 7270 | #define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x3a53 |
|---|
| 7271 | #define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 7272 | #define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x3a54 |
|---|
| 7273 | #define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 7274 | #define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x3a55 |
|---|
| 7275 | #define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 7276 | #define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x3a56 |
|---|
| 7277 | #define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 7278 | #define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x3a57 |
|---|
| 7279 | #define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 7280 | #define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x3a58 |
|---|
| 7281 | #define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 7282 | #define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x3a59 |
|---|
| 7283 | #define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 7284 | #define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x3a5a |
|---|
| 7285 | #define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 7286 | #define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x3a5b |
|---|
| 7287 | #define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 7288 | #define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x3a5c |
|---|
| 7289 | #define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 7290 | #define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x3a5d |
|---|
| 7291 | #define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 7292 | #define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x3a5e |
|---|
| 7293 | #define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 7294 | #define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x3a5f |
|---|
| 7295 | #define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 7296 | #define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x3a60 |
|---|
| 7297 | #define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 7298 | #define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x3a61 |
|---|
| 7299 | #define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 7300 | #define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x3a62 |
|---|
| 7301 | #define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 7302 | #define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x3a63 |
|---|
| 7303 | #define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 7304 | #define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x3a64 |
|---|
| 7305 | #define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 7306 | #define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x3a65 |
|---|
| 7307 | #define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 7308 | #define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x3a66 |
|---|
| 7309 | #define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 7310 | #define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x3a67 |
|---|
| 7311 | #define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 7312 | #define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x3a68 |
|---|
| 7313 | #define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 7314 | #define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x3a69 |
|---|
| 7315 | #define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 1 |
|---|
| 7316 | #define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x3a6a |
|---|
| 7317 | #define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 1 |
|---|
| 7318 | #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x3a6b |
|---|
| 7319 | #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 7320 | #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x3a6c |
|---|
| 7321 | #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 7322 | #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x3a6d |
|---|
| 7323 | #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 7324 | #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x3a6e |
|---|
| 7325 | #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 7326 | #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x3a6f |
|---|
| 7327 | #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 7328 | #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x3a70 |
|---|
| 7329 | #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 7330 | #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x3a71 |
|---|
| 7331 | #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 7332 | #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x3a72 |
|---|
| 7333 | #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 7334 | #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x3a73 |
|---|
| 7335 | #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 7336 | #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x3a74 |
|---|
| 7337 | #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 7338 | #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x3a75 |
|---|
| 7339 | #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 7340 | #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x3a76 |
|---|
| 7341 | #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 7342 | #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x3a77 |
|---|
| 7343 | #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 7344 | #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x3a78 |
|---|
| 7345 | #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 7346 | #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x3a79 |
|---|
| 7347 | #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 7348 | #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x3a7a |
|---|
| 7349 | #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 7350 | #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x3a7b |
|---|
| 7351 | #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 7352 | #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x3a7c |
|---|
| 7353 | #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 7354 | #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x3a7d |
|---|
| 7355 | #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 7356 | #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x3a7e |
|---|
| 7357 | #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 7358 | #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x3a7f |
|---|
| 7359 | #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 7360 | #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x3a80 |
|---|
| 7361 | #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 7362 | #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x3a81 |
|---|
| 7363 | #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 7364 | #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x3a82 |
|---|
| 7365 | #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 7366 | #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x3a83 |
|---|
| 7367 | #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 7368 | #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x3a84 |
|---|
| 7369 | #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 7370 | #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x3a85 |
|---|
| 7371 | #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 7372 | #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x3a86 |
|---|
| 7373 | #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 7374 | #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x3a87 |
|---|
| 7375 | #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 7376 | #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x3a88 |
|---|
| 7377 | #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 7378 | #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x3a89 |
|---|
| 7379 | #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
|---|
| 7380 | #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x3a8a |
|---|
| 7381 | #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
|---|
| 7382 | #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x3a8b |
|---|
| 7383 | #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 7384 | #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x3a8c |
|---|
| 7385 | #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 7386 | #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x3a8d |
|---|
| 7387 | #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 7388 | #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x3a8e |
|---|
| 7389 | #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 7390 | #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x3a8f |
|---|
| 7391 | #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 7392 | #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x3a90 |
|---|
| 7393 | #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 7394 | #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x3a91 |
|---|
| 7395 | #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 7396 | #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x3a92 |
|---|
| 7397 | #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 7398 | #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x3a93 |
|---|
| 7399 | #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 7400 | #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x3a94 |
|---|
| 7401 | #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 7402 | #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x3a95 |
|---|
| 7403 | #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 7404 | #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x3a96 |
|---|
| 7405 | #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 7406 | #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x3a97 |
|---|
| 7407 | #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 7408 | #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x3a98 |
|---|
| 7409 | #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 7410 | #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x3a99 |
|---|
| 7411 | #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 7412 | #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x3a9a |
|---|
| 7413 | #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 7414 | #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x3a9b |
|---|
| 7415 | #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 7416 | #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x3a9c |
|---|
| 7417 | #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 7418 | #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x3a9d |
|---|
| 7419 | #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 7420 | #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x3a9e |
|---|
| 7421 | #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 7422 | #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x3a9f |
|---|
| 7423 | #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 7424 | #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x3aa0 |
|---|
| 7425 | #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 7426 | #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x3aa1 |
|---|
| 7427 | #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 7428 | #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x3aa2 |
|---|
| 7429 | #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 7430 | #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x3aa3 |
|---|
| 7431 | #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 7432 | #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x3aa4 |
|---|
| 7433 | #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 7434 | #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x3aa5 |
|---|
| 7435 | #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 7436 | #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x3aa6 |
|---|
| 7437 | #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 7438 | #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x3aa7 |
|---|
| 7439 | #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 7440 | #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x3aa8 |
|---|
| 7441 | #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 7442 | #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x3aa9 |
|---|
| 7443 | #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
|---|
| 7444 | #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x3aaa |
|---|
| 7445 | #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
|---|
| 7446 | #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x3aab |
|---|
| 7447 | #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 7448 | #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x3aac |
|---|
| 7449 | #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 7450 | #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x3aad |
|---|
| 7451 | #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 7452 | #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x3aae |
|---|
| 7453 | #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 7454 | #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x3aaf |
|---|
| 7455 | #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 7456 | #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x3ab0 |
|---|
| 7457 | #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 7458 | #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x3ab1 |
|---|
| 7459 | #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 7460 | #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x3ab2 |
|---|
| 7461 | #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 7462 | #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x3ab3 |
|---|
| 7463 | #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 7464 | #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x3ab4 |
|---|
| 7465 | #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 7466 | #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x3ab5 |
|---|
| 7467 | #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 7468 | #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x3ab6 |
|---|
| 7469 | #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 7470 | #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x3ab7 |
|---|
| 7471 | #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 7472 | #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x3ab8 |
|---|
| 7473 | #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 7474 | #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x3ab9 |
|---|
| 7475 | #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 7476 | #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x3aba |
|---|
| 7477 | #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 7478 | #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x3abb |
|---|
| 7479 | #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 7480 | #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x3abc |
|---|
| 7481 | #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 7482 | #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x3abd |
|---|
| 7483 | #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 7484 | #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x3abe |
|---|
| 7485 | #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 7486 | #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x3abf |
|---|
| 7487 | #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 7488 | #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x3ac0 |
|---|
| 7489 | #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 7490 | #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x3ac1 |
|---|
| 7491 | #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 7492 | #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x3ac2 |
|---|
| 7493 | #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 7494 | #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x3ac3 |
|---|
| 7495 | #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 7496 | #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x3ac4 |
|---|
| 7497 | #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 7498 | #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x3ac5 |
|---|
| 7499 | #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 7500 | #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x3ac6 |
|---|
| 7501 | #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 7502 | #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x3ac7 |
|---|
| 7503 | #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 7504 | #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x3ac8 |
|---|
| 7505 | #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 7506 | #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x3ac9 |
|---|
| 7507 | #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
|---|
| 7508 | #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x3aca |
|---|
| 7509 | #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
|---|
| 7510 | |
|---|
| 7511 | |
|---|
| 7512 | // addressBlock: mmhub_utcl2_vmsharedpfdec:1 |
|---|
| 7513 | // base address: 0x76b90 |
|---|
| 7514 | #define mmVMSHAREDPF1_MC_VM_NB_MMIOBASE 0x3ae4 |
|---|
| 7515 | #define mmVMSHAREDPF1_MC_VM_NB_MMIOBASE_BASE_IDX 1 |
|---|
| 7516 | #define mmVMSHAREDPF1_MC_VM_NB_MMIOLIMIT 0x3ae5 |
|---|
| 7517 | #define mmVMSHAREDPF1_MC_VM_NB_MMIOLIMIT_BASE_IDX 1 |
|---|
| 7518 | #define mmVMSHAREDPF1_MC_VM_NB_PCI_CTRL 0x3ae6 |
|---|
| 7519 | #define mmVMSHAREDPF1_MC_VM_NB_PCI_CTRL_BASE_IDX 1 |
|---|
| 7520 | #define mmVMSHAREDPF1_MC_VM_NB_PCI_ARB 0x3ae7 |
|---|
| 7521 | #define mmVMSHAREDPF1_MC_VM_NB_PCI_ARB_BASE_IDX 1 |
|---|
| 7522 | #define mmVMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1 0x3ae8 |
|---|
| 7523 | #define mmVMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 1 |
|---|
| 7524 | #define mmVMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2 0x3ae9 |
|---|
| 7525 | #define mmVMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 1 |
|---|
| 7526 | #define mmVMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2 0x3aea |
|---|
| 7527 | #define mmVMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 1 |
|---|
| 7528 | #define mmVMSHAREDPF1_MC_VM_FB_OFFSET 0x3aeb |
|---|
| 7529 | #define mmVMSHAREDPF1_MC_VM_FB_OFFSET_BASE_IDX 1 |
|---|
| 7530 | #define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x3aec |
|---|
| 7531 | #define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 1 |
|---|
| 7532 | #define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x3aed |
|---|
| 7533 | #define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 1 |
|---|
| 7534 | #define mmVMSHAREDPF1_MC_VM_STEERING 0x3aee |
|---|
| 7535 | #define mmVMSHAREDPF1_MC_VM_STEERING_BASE_IDX 1 |
|---|
| 7536 | #define mmVMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ 0x3aef |
|---|
| 7537 | #define mmVMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ_BASE_IDX 1 |
|---|
| 7538 | #define mmVMSHAREDPF1_MC_MEM_POWER_LS 0x3af0 |
|---|
| 7539 | #define mmVMSHAREDPF1_MC_MEM_POWER_LS_BASE_IDX 1 |
|---|
| 7540 | #define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START 0x3af1 |
|---|
| 7541 | #define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 1 |
|---|
| 7542 | #define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END 0x3af2 |
|---|
| 7543 | #define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 1 |
|---|
| 7544 | #define mmVMSHAREDPF1_MC_VM_APT_CNTL 0x3af3 |
|---|
| 7545 | #define mmVMSHAREDPF1_MC_VM_APT_CNTL_BASE_IDX 1 |
|---|
| 7546 | #define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START 0x3af4 |
|---|
| 7547 | #define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 1 |
|---|
| 7548 | #define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END 0x3af5 |
|---|
| 7549 | #define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 1 |
|---|
| 7550 | #define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x3af6 |
|---|
| 7551 | #define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 1 |
|---|
| 7552 | #define mmVMSHAREDPF1_MC_VM_XGMI_LFB_CNTL 0x3af7 |
|---|
| 7553 | #define mmVMSHAREDPF1_MC_VM_XGMI_LFB_CNTL_BASE_IDX 1 |
|---|
| 7554 | #define mmVMSHAREDPF1_MC_VM_XGMI_LFB_SIZE 0x3af8 |
|---|
| 7555 | #define mmVMSHAREDPF1_MC_VM_XGMI_LFB_SIZE_BASE_IDX 1 |
|---|
| 7556 | #define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL 0x3af9 |
|---|
| 7557 | #define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX 1 |
|---|
| 7558 | |
|---|
| 7559 | |
|---|
| 7560 | // addressBlock: mmhub_utcl2_vmsharedvcdec:1 |
|---|
| 7561 | // base address: 0x76c00 |
|---|
| 7562 | #define mmVMSHAREDVC1_MC_VM_FB_LOCATION_BASE 0x3b00 |
|---|
| 7563 | #define mmVMSHAREDVC1_MC_VM_FB_LOCATION_BASE_BASE_IDX 1 |
|---|
| 7564 | #define mmVMSHAREDVC1_MC_VM_FB_LOCATION_TOP 0x3b01 |
|---|
| 7565 | #define mmVMSHAREDVC1_MC_VM_FB_LOCATION_TOP_BASE_IDX 1 |
|---|
| 7566 | #define mmVMSHAREDVC1_MC_VM_AGP_TOP 0x3b02 |
|---|
| 7567 | #define mmVMSHAREDVC1_MC_VM_AGP_TOP_BASE_IDX 1 |
|---|
| 7568 | #define mmVMSHAREDVC1_MC_VM_AGP_BOT 0x3b03 |
|---|
| 7569 | #define mmVMSHAREDVC1_MC_VM_AGP_BOT_BASE_IDX 1 |
|---|
| 7570 | #define mmVMSHAREDVC1_MC_VM_AGP_BASE 0x3b04 |
|---|
| 7571 | #define mmVMSHAREDVC1_MC_VM_AGP_BASE_BASE_IDX 1 |
|---|
| 7572 | #define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x3b05 |
|---|
| 7573 | #define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 1 |
|---|
| 7574 | #define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x3b06 |
|---|
| 7575 | #define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 1 |
|---|
| 7576 | #define mmVMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL 0x3b07 |
|---|
| 7577 | #define mmVMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL_BASE_IDX 1 |
|---|
| 7578 | |
|---|
| 7579 | |
|---|
| 7580 | // addressBlock: mmhub_utcl2_vmsharedhvdec:1 |
|---|
| 7581 | // base address: 0x76c80 |
|---|
| 7582 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0 0x3b20 |
|---|
| 7583 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1 |
|---|
| 7584 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1 0x3b21 |
|---|
| 7585 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1 |
|---|
| 7586 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2 0x3b22 |
|---|
| 7587 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1 |
|---|
| 7588 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3 0x3b23 |
|---|
| 7589 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1 |
|---|
| 7590 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4 0x3b24 |
|---|
| 7591 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1 |
|---|
| 7592 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5 0x3b25 |
|---|
| 7593 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1 |
|---|
| 7594 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6 0x3b26 |
|---|
| 7595 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1 |
|---|
| 7596 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7 0x3b27 |
|---|
| 7597 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1 |
|---|
| 7598 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8 0x3b28 |
|---|
| 7599 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1 |
|---|
| 7600 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9 0x3b29 |
|---|
| 7601 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1 |
|---|
| 7602 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10 0x3b2a |
|---|
| 7603 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1 |
|---|
| 7604 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11 0x3b2b |
|---|
| 7605 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1 |
|---|
| 7606 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12 0x3b2c |
|---|
| 7607 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1 |
|---|
| 7608 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13 0x3b2d |
|---|
| 7609 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1 |
|---|
| 7610 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14 0x3b2e |
|---|
| 7611 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1 |
|---|
| 7612 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15 0x3b2f |
|---|
| 7613 | #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1 |
|---|
| 7614 | #define mmVMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1 0x3b30 |
|---|
| 7615 | #define mmVMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1_BASE_IDX 1 |
|---|
| 7616 | #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_0 0x3b31 |
|---|
| 7617 | #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_0_BASE_IDX 1 |
|---|
| 7618 | #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_1 0x3b32 |
|---|
| 7619 | #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_1_BASE_IDX 1 |
|---|
| 7620 | #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_2 0x3b33 |
|---|
| 7621 | #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_2_BASE_IDX 1 |
|---|
| 7622 | #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_3 0x3b34 |
|---|
| 7623 | #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_3_BASE_IDX 1 |
|---|
| 7624 | #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_0 0x3b35 |
|---|
| 7625 | #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_0_BASE_IDX 1 |
|---|
| 7626 | #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_1 0x3b36 |
|---|
| 7627 | #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_1_BASE_IDX 1 |
|---|
| 7628 | #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_2 0x3b37 |
|---|
| 7629 | #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_2_BASE_IDX 1 |
|---|
| 7630 | #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_3 0x3b38 |
|---|
| 7631 | #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_3_BASE_IDX 1 |
|---|
| 7632 | #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_0 0x3b39 |
|---|
| 7633 | #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_0_BASE_IDX 1 |
|---|
| 7634 | #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_1 0x3b3a |
|---|
| 7635 | #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_1_BASE_IDX 1 |
|---|
| 7636 | #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_2 0x3b3b |
|---|
| 7637 | #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_2_BASE_IDX 1 |
|---|
| 7638 | #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_3 0x3b3c |
|---|
| 7639 | #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_3_BASE_IDX 1 |
|---|
| 7640 | #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_0 0x3b3d |
|---|
| 7641 | #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_0_BASE_IDX 1 |
|---|
| 7642 | #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_1 0x3b3e |
|---|
| 7643 | #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_1_BASE_IDX 1 |
|---|
| 7644 | #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_2 0x3b3f |
|---|
| 7645 | #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_2_BASE_IDX 1 |
|---|
| 7646 | #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_3 0x3b40 |
|---|
| 7647 | #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_3_BASE_IDX 1 |
|---|
| 7648 | #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_0 0x3b41 |
|---|
| 7649 | #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_0_BASE_IDX 1 |
|---|
| 7650 | #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_1 0x3b42 |
|---|
| 7651 | #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_1_BASE_IDX 1 |
|---|
| 7652 | #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_2 0x3b43 |
|---|
| 7653 | #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_2_BASE_IDX 1 |
|---|
| 7654 | #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_3 0x3b44 |
|---|
| 7655 | #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_3_BASE_IDX 1 |
|---|
| 7656 | #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_0 0x3b45 |
|---|
| 7657 | #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_0_BASE_IDX 1 |
|---|
| 7658 | #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_1 0x3b46 |
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| 7659 | #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_1_BASE_IDX 1 |
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| 7660 | #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_2 0x3b47 |
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| 7661 | #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_2_BASE_IDX 1 |
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| 7662 | #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_3 0x3b48 |
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| 7663 | #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_3_BASE_IDX 1 |
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| 7664 | #define mmVMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER 0x3b49 |
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| 7665 | #define mmVMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER_BASE_IDX 1 |
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| 7666 | #define mmVMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x3b4a |
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| 7667 | #define mmVMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1 |
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| 7668 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL 0x3b4b |
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| 7669 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_BASE_IDX 1 |
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| 7670 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0 0x3b4c |
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| 7671 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0_BASE_IDX 1 |
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| 7672 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1 0x3b4d |
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| 7673 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1_BASE_IDX 1 |
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| 7674 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2 0x3b4e |
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| 7675 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2_BASE_IDX 1 |
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| 7676 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3 0x3b4f |
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| 7677 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3_BASE_IDX 1 |
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| 7678 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4 0x3b50 |
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| 7679 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4_BASE_IDX 1 |
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| 7680 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5 0x3b51 |
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| 7681 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5_BASE_IDX 1 |
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| 7682 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6 0x3b52 |
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| 7683 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6_BASE_IDX 1 |
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| 7684 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7 0x3b53 |
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| 7685 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7_BASE_IDX 1 |
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| 7686 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8 0x3b54 |
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| 7687 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8_BASE_IDX 1 |
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| 7688 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9 0x3b55 |
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| 7689 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9_BASE_IDX 1 |
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| 7690 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10 0x3b56 |
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| 7691 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10_BASE_IDX 1 |
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| 7692 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11 0x3b57 |
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| 7693 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11_BASE_IDX 1 |
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| 7694 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12 0x3b58 |
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| 7695 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12_BASE_IDX 1 |
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| 7696 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13 0x3b59 |
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| 7697 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13_BASE_IDX 1 |
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| 7698 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14 0x3b5a |
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| 7699 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14_BASE_IDX 1 |
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| 7700 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15 0x3b5b |
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| 7701 | #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15_BASE_IDX 1 |
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| 7702 | #define mmVMSHAREDHV1_UTCL2_CGTT_CLK_CTRL 0x3b5c |
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| 7703 | #define mmVMSHAREDHV1_UTCL2_CGTT_CLK_CTRL_BASE_IDX 1 |
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| 7704 | #define mmVMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID 0x3b5d |
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| 7705 | #define mmVMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID_BASE_IDX 1 |
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| 7706 | #define mmVMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE 0x3b5e |
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| 7707 | #define mmVMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 1 |
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| 7708 | |
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| 7709 | |
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| 7710 | // addressBlock: mmhub_utcl2_atcl2pfcntrdec:1 |
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| 7711 | // base address: 0x76dc0 |
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| 7712 | #define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO 0x3b70 |
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| 7713 | #define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO_BASE_IDX 1 |
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| 7714 | #define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI 0x3b71 |
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| 7715 | #define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI_BASE_IDX 1 |
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| 7716 | |
|---|
| 7717 | |
|---|
| 7718 | // addressBlock: mmhub_utcl2_atcl2pfcntldec:1 |
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| 7719 | // base address: 0x76dd0 |
|---|
| 7720 | #define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG 0x3b74 |
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| 7721 | #define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1 |
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| 7722 | #define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG 0x3b75 |
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| 7723 | #define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1 |
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| 7724 | #define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x3b76 |
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| 7725 | #define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
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| 7726 | |
|---|
| 7727 | |
|---|
| 7728 | // addressBlock: mmhub_utcl2_vml2pldec:1 |
|---|
| 7729 | // base address: 0x76e00 |
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| 7730 | #define mmVML2PL1_MC_VM_L2_PERFCOUNTER0_CFG 0x3b80 |
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| 7731 | #define mmVML2PL1_MC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 |
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| 7732 | #define mmVML2PL1_MC_VM_L2_PERFCOUNTER1_CFG 0x3b81 |
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| 7733 | #define mmVML2PL1_MC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 |
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| 7734 | #define mmVML2PL1_MC_VM_L2_PERFCOUNTER2_CFG 0x3b82 |
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| 7735 | #define mmVML2PL1_MC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 |
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| 7736 | #define mmVML2PL1_MC_VM_L2_PERFCOUNTER3_CFG 0x3b83 |
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| 7737 | #define mmVML2PL1_MC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 |
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| 7738 | #define mmVML2PL1_MC_VM_L2_PERFCOUNTER4_CFG 0x3b84 |
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| 7739 | #define mmVML2PL1_MC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 |
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| 7740 | #define mmVML2PL1_MC_VM_L2_PERFCOUNTER5_CFG 0x3b85 |
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| 7741 | #define mmVML2PL1_MC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 |
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| 7742 | #define mmVML2PL1_MC_VM_L2_PERFCOUNTER6_CFG 0x3b86 |
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| 7743 | #define mmVML2PL1_MC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 |
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| 7744 | #define mmVML2PL1_MC_VM_L2_PERFCOUNTER7_CFG 0x3b87 |
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| 7745 | #define mmVML2PL1_MC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 |
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| 7746 | #define mmVML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x3b88 |
|---|
| 7747 | #define mmVML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
|---|
| 7748 | |
|---|
| 7749 | |
|---|
| 7750 | // addressBlock: mmhub_utcl2_vml2prdec:1 |
|---|
| 7751 | // base address: 0x76e40 |
|---|
| 7752 | #define mmVML2PR1_MC_VM_L2_PERFCOUNTER_LO 0x3b90 |
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| 7753 | #define mmVML2PR1_MC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 |
|---|
| 7754 | #define mmVML2PR1_MC_VM_L2_PERFCOUNTER_HI 0x3b91 |
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| 7755 | #define mmVML2PR1_MC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 |
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| 7756 | |
|---|
| 7757 | #endif |
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| 7758 | |
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