1 | /* |
2 | * Copyright (C) 2017 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included |
12 | * in all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
20 | */ |
21 | #ifndef _mp_10_0_SH_MASK_HEADER |
22 | #define |
23 | |
24 | |
25 | // addressBlock: mp_SmuMp0_SmnDec |
26 | //MP0_SMN_C2PMSG_32 |
27 | #define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 |
28 | #define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL |
29 | //MP0_SMN_C2PMSG_33 |
30 | #define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 |
31 | #define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL |
32 | //MP0_SMN_C2PMSG_34 |
33 | #define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 |
34 | #define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL |
35 | //MP0_SMN_C2PMSG_35 |
36 | #define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 |
37 | #define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL |
38 | //MP0_SMN_C2PMSG_36 |
39 | #define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 |
40 | #define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL |
41 | //MP0_SMN_C2PMSG_37 |
42 | #define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 |
43 | #define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL |
44 | //MP0_SMN_C2PMSG_38 |
45 | #define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 |
46 | #define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL |
47 | //MP0_SMN_C2PMSG_39 |
48 | #define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 |
49 | #define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL |
50 | //MP0_SMN_C2PMSG_40 |
51 | #define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 |
52 | #define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL |
53 | //MP0_SMN_C2PMSG_41 |
54 | #define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 |
55 | #define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL |
56 | //MP0_SMN_C2PMSG_42 |
57 | #define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 |
58 | #define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL |
59 | //MP0_SMN_C2PMSG_43 |
60 | #define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 |
61 | #define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL |
62 | //MP0_SMN_C2PMSG_44 |
63 | #define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 |
64 | #define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL |
65 | //MP0_SMN_C2PMSG_45 |
66 | #define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 |
67 | #define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL |
68 | //MP0_SMN_C2PMSG_46 |
69 | #define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 |
70 | #define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL |
71 | //MP0_SMN_C2PMSG_47 |
72 | #define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 |
73 | #define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL |
74 | //MP0_SMN_C2PMSG_48 |
75 | #define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 |
76 | #define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL |
77 | //MP0_SMN_C2PMSG_49 |
78 | #define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 |
79 | #define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL |
80 | //MP0_SMN_C2PMSG_50 |
81 | #define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 |
82 | #define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL |
83 | //MP0_SMN_C2PMSG_51 |
84 | #define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 |
85 | #define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL |
86 | //MP0_SMN_C2PMSG_52 |
87 | #define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 |
88 | #define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL |
89 | //MP0_SMN_C2PMSG_53 |
90 | #define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 |
91 | #define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL |
92 | //MP0_SMN_C2PMSG_54 |
93 | #define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 |
94 | #define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL |
95 | //MP0_SMN_C2PMSG_55 |
96 | #define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 |
97 | #define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL |
98 | //MP0_SMN_C2PMSG_56 |
99 | #define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 |
100 | #define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL |
101 | //MP0_SMN_C2PMSG_57 |
102 | #define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 |
103 | #define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL |
104 | //MP0_SMN_C2PMSG_58 |
105 | #define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 |
106 | #define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL |
107 | //MP0_SMN_C2PMSG_59 |
108 | #define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 |
109 | #define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL |
110 | //MP0_SMN_C2PMSG_60 |
111 | #define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 |
112 | #define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL |
113 | //MP0_SMN_C2PMSG_61 |
114 | #define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 |
115 | #define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL |
116 | //MP0_SMN_C2PMSG_62 |
117 | #define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 |
118 | #define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL |
119 | //MP0_SMN_C2PMSG_63 |
120 | #define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 |
121 | #define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL |
122 | //MP0_SMN_C2PMSG_64 |
123 | #define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 |
124 | #define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL |
125 | //MP0_SMN_C2PMSG_65 |
126 | #define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 |
127 | #define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL |
128 | //MP0_SMN_C2PMSG_66 |
129 | #define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 |
130 | #define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL |
131 | //MP0_SMN_C2PMSG_67 |
132 | #define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 |
133 | #define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL |
134 | //MP0_SMN_C2PMSG_68 |
135 | #define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 |
136 | #define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL |
137 | //MP0_SMN_C2PMSG_69 |
138 | #define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 |
139 | #define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL |
140 | //MP0_SMN_C2PMSG_70 |
141 | #define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 |
142 | #define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL |
143 | //MP0_SMN_C2PMSG_71 |
144 | #define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 |
145 | #define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL |
146 | //MP0_SMN_C2PMSG_72 |
147 | #define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 |
148 | #define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL |
149 | //MP0_SMN_C2PMSG_73 |
150 | #define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 |
151 | #define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL |
152 | //MP0_SMN_C2PMSG_74 |
153 | #define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 |
154 | #define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL |
155 | //MP0_SMN_C2PMSG_75 |
156 | #define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 |
157 | #define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL |
158 | //MP0_SMN_C2PMSG_76 |
159 | #define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 |
160 | #define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL |
161 | //MP0_SMN_C2PMSG_77 |
162 | #define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 |
163 | #define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL |
164 | //MP0_SMN_C2PMSG_78 |
165 | #define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 |
166 | #define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL |
167 | //MP0_SMN_C2PMSG_79 |
168 | #define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 |
169 | #define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL |
170 | //MP0_SMN_C2PMSG_80 |
171 | #define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 |
172 | #define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL |
173 | //MP0_SMN_C2PMSG_81 |
174 | #define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 |
175 | #define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL |
176 | //MP0_SMN_C2PMSG_82 |
177 | #define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 |
178 | #define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL |
179 | //MP0_SMN_C2PMSG_83 |
180 | #define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 |
181 | #define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL |
182 | //MP0_SMN_C2PMSG_84 |
183 | #define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 |
184 | #define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL |
185 | //MP0_SMN_C2PMSG_85 |
186 | #define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 |
187 | #define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL |
188 | //MP0_SMN_C2PMSG_86 |
189 | #define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 |
190 | #define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL |
191 | //MP0_SMN_C2PMSG_87 |
192 | #define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 |
193 | #define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL |
194 | //MP0_SMN_C2PMSG_88 |
195 | #define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 |
196 | #define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL |
197 | //MP0_SMN_C2PMSG_89 |
198 | #define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 |
199 | #define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL |
200 | //MP0_SMN_C2PMSG_90 |
201 | #define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 |
202 | #define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL |
203 | //MP0_SMN_C2PMSG_91 |
204 | #define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 |
205 | #define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL |
206 | //MP0_SMN_C2PMSG_92 |
207 | #define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 |
208 | #define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL |
209 | //MP0_SMN_C2PMSG_93 |
210 | #define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 |
211 | #define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL |
212 | //MP0_SMN_C2PMSG_94 |
213 | #define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 |
214 | #define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL |
215 | //MP0_SMN_C2PMSG_95 |
216 | #define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 |
217 | #define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL |
218 | //MP0_SMN_C2PMSG_96 |
219 | #define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 |
220 | #define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL |
221 | //MP0_SMN_C2PMSG_97 |
222 | #define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 |
223 | #define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL |
224 | //MP0_SMN_C2PMSG_98 |
225 | #define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 |
226 | #define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL |
227 | //MP0_SMN_C2PMSG_99 |
228 | #define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 |
229 | #define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL |
230 | //MP0_SMN_C2PMSG_100 |
231 | #define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 |
232 | #define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL |
233 | //MP0_SMN_C2PMSG_101 |
234 | #define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 |
235 | #define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL |
236 | //MP0_SMN_C2PMSG_102 |
237 | #define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 |
238 | #define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL |
239 | //MP0_SMN_C2PMSG_103 |
240 | #define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 |
241 | #define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL |
242 | //MP0_SMN_IH_CREDIT |
243 | #define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 |
244 | #define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 |
245 | #define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L |
246 | #define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L |
247 | //MP0_SMN_IH_SW_INT |
248 | #define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x0 |
249 | #define MP0_SMN_IH_SW_INT__ID__SHIFT 0x1 |
250 | #define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000001L |
251 | #define MP0_SMN_IH_SW_INT__ID_MASK 0x000001FEL |
252 | //MP0_SMN_IH_SW_INT_CTRL |
253 | #define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0 |
254 | #define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8 |
255 | #define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L |
256 | #define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L |
257 | |
258 | |
259 | // addressBlock: mp_SmuMp1_SmnDec |
260 | //MP1_SMN_C2PMSG_32 |
261 | #define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 |
262 | #define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL |
263 | //MP1_SMN_C2PMSG_33 |
264 | #define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 |
265 | #define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL |
266 | //MP1_SMN_C2PMSG_34 |
267 | #define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 |
268 | #define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL |
269 | //MP1_SMN_C2PMSG_35 |
270 | #define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 |
271 | #define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL |
272 | //MP1_SMN_C2PMSG_36 |
273 | #define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 |
274 | #define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL |
275 | //MP1_SMN_C2PMSG_37 |
276 | #define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 |
277 | #define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL |
278 | //MP1_SMN_C2PMSG_38 |
279 | #define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 |
280 | #define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL |
281 | //MP1_SMN_C2PMSG_39 |
282 | #define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 |
283 | #define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL |
284 | //MP1_SMN_C2PMSG_40 |
285 | #define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 |
286 | #define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL |
287 | //MP1_SMN_C2PMSG_41 |
288 | #define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 |
289 | #define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL |
290 | //MP1_SMN_C2PMSG_42 |
291 | #define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 |
292 | #define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL |
293 | //MP1_SMN_C2PMSG_43 |
294 | #define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 |
295 | #define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL |
296 | //MP1_SMN_C2PMSG_44 |
297 | #define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 |
298 | #define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL |
299 | //MP1_SMN_C2PMSG_45 |
300 | #define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 |
301 | #define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL |
302 | //MP1_SMN_C2PMSG_46 |
303 | #define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 |
304 | #define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL |
305 | //MP1_SMN_C2PMSG_47 |
306 | #define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 |
307 | #define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL |
308 | //MP1_SMN_C2PMSG_48 |
309 | #define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 |
310 | #define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL |
311 | //MP1_SMN_C2PMSG_49 |
312 | #define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 |
313 | #define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL |
314 | //MP1_SMN_C2PMSG_50 |
315 | #define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 |
316 | #define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL |
317 | //MP1_SMN_C2PMSG_51 |
318 | #define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 |
319 | #define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL |
320 | //MP1_SMN_C2PMSG_52 |
321 | #define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 |
322 | #define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL |
323 | //MP1_SMN_C2PMSG_53 |
324 | #define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 |
325 | #define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL |
326 | //MP1_SMN_C2PMSG_54 |
327 | #define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 |
328 | #define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL |
329 | //MP1_SMN_C2PMSG_55 |
330 | #define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 |
331 | #define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL |
332 | //MP1_SMN_C2PMSG_56 |
333 | #define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 |
334 | #define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL |
335 | //MP1_SMN_C2PMSG_57 |
336 | #define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 |
337 | #define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL |
338 | //MP1_SMN_C2PMSG_58 |
339 | #define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 |
340 | #define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL |
341 | //MP1_SMN_C2PMSG_59 |
342 | #define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 |
343 | #define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL |
344 | //MP1_SMN_C2PMSG_60 |
345 | #define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 |
346 | #define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL |
347 | //MP1_SMN_C2PMSG_61 |
348 | #define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 |
349 | #define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL |
350 | //MP1_SMN_C2PMSG_62 |
351 | #define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 |
352 | #define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL |
353 | //MP1_SMN_C2PMSG_63 |
354 | #define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 |
355 | #define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL |
356 | //MP1_SMN_C2PMSG_64 |
357 | #define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 |
358 | #define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL |
359 | //MP1_SMN_C2PMSG_65 |
360 | #define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 |
361 | #define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL |
362 | //MP1_SMN_C2PMSG_66 |
363 | #define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 |
364 | #define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL |
365 | //MP1_SMN_C2PMSG_67 |
366 | #define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 |
367 | #define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL |
368 | //MP1_SMN_C2PMSG_68 |
369 | #define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 |
370 | #define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL |
371 | //MP1_SMN_C2PMSG_69 |
372 | #define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 |
373 | #define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL |
374 | //MP1_SMN_C2PMSG_70 |
375 | #define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 |
376 | #define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL |
377 | //MP1_SMN_C2PMSG_71 |
378 | #define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 |
379 | #define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL |
380 | //MP1_SMN_C2PMSG_72 |
381 | #define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 |
382 | #define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL |
383 | //MP1_SMN_C2PMSG_73 |
384 | #define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 |
385 | #define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL |
386 | //MP1_SMN_C2PMSG_74 |
387 | #define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 |
388 | #define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL |
389 | //MP1_SMN_C2PMSG_75 |
390 | #define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 |
391 | #define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL |
392 | //MP1_SMN_C2PMSG_76 |
393 | #define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 |
394 | #define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL |
395 | //MP1_SMN_C2PMSG_77 |
396 | #define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 |
397 | #define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL |
398 | //MP1_SMN_C2PMSG_78 |
399 | #define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 |
400 | #define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL |
401 | //MP1_SMN_C2PMSG_79 |
402 | #define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 |
403 | #define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL |
404 | //MP1_SMN_C2PMSG_80 |
405 | #define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 |
406 | #define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL |
407 | //MP1_SMN_C2PMSG_81 |
408 | #define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 |
409 | #define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL |
410 | //MP1_SMN_C2PMSG_82 |
411 | #define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 |
412 | #define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL |
413 | //MP1_SMN_C2PMSG_83 |
414 | #define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 |
415 | #define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL |
416 | //MP1_SMN_C2PMSG_84 |
417 | #define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 |
418 | #define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL |
419 | //MP1_SMN_C2PMSG_85 |
420 | #define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 |
421 | #define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL |
422 | //MP1_SMN_C2PMSG_86 |
423 | #define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 |
424 | #define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL |
425 | //MP1_SMN_C2PMSG_87 |
426 | #define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 |
427 | #define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL |
428 | //MP1_SMN_C2PMSG_88 |
429 | #define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 |
430 | #define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL |
431 | //MP1_SMN_C2PMSG_89 |
432 | #define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 |
433 | #define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL |
434 | //MP1_SMN_C2PMSG_90 |
435 | #define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 |
436 | #define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL |
437 | //MP1_SMN_C2PMSG_91 |
438 | #define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 |
439 | #define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL |
440 | //MP1_SMN_C2PMSG_92 |
441 | #define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 |
442 | #define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL |
443 | //MP1_SMN_C2PMSG_93 |
444 | #define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 |
445 | #define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL |
446 | //MP1_SMN_C2PMSG_94 |
447 | #define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 |
448 | #define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL |
449 | //MP1_SMN_C2PMSG_95 |
450 | #define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 |
451 | #define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL |
452 | //MP1_SMN_C2PMSG_96 |
453 | #define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 |
454 | #define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL |
455 | //MP1_SMN_C2PMSG_97 |
456 | #define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 |
457 | #define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL |
458 | //MP1_SMN_C2PMSG_98 |
459 | #define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 |
460 | #define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL |
461 | //MP1_SMN_C2PMSG_99 |
462 | #define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 |
463 | #define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL |
464 | //MP1_SMN_C2PMSG_100 |
465 | #define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 |
466 | #define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL |
467 | //MP1_SMN_C2PMSG_101 |
468 | #define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 |
469 | #define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL |
470 | //MP1_SMN_C2PMSG_102 |
471 | #define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 |
472 | #define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL |
473 | //MP1_SMN_C2PMSG_103 |
474 | #define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 |
475 | #define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL |
476 | //MP1_SMN_IH_CREDIT |
477 | #define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 |
478 | #define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 |
479 | #define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L |
480 | #define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L |
481 | //MP1_SMN_IH_SW_INT |
482 | #define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x0 |
483 | #define MP1_SMN_IH_SW_INT__ID__SHIFT 0x1 |
484 | #define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000001L |
485 | #define MP1_SMN_IH_SW_INT__ID_MASK 0x000001FEL |
486 | //MP1_SMN_IH_SW_INT_CTRL |
487 | #define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0 |
488 | #define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8 |
489 | #define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L |
490 | #define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L |
491 | //MP1_SMN_FPS_CNT |
492 | #define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 |
493 | #define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL |
494 | |
495 | |
496 | // addressBlock: mp_SmuMp0Pub_CruDec |
497 | //MP0_ACTIVE_FCN_ID |
498 | #define MP0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 |
499 | #define MP0_ACTIVE_FCN_ID__VF__SHIFT 0x1f |
500 | #define MP0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL |
501 | #define MP0_ACTIVE_FCN_ID__VF_MASK 0x80000000L |
502 | //MP0_IH_CREDIT |
503 | #define MP0_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 |
504 | #define MP0_IH_CREDIT__CLIENT_ID__SHIFT 0x10 |
505 | #define MP0_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L |
506 | #define MP0_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L |
507 | //MP0_IH_SW_INT |
508 | #define MP0_IH_SW_INT__ID__SHIFT 0x0 |
509 | #define MP0_IH_SW_INT__VALID__SHIFT 0x8 |
510 | #define MP0_IH_SW_INT__ID_MASK 0x000000FFL |
511 | #define MP0_IH_SW_INT__VALID_MASK 0x00000100L |
512 | //MP0_IH_SW_INT_CTRL |
513 | #define MP0_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 |
514 | #define MP0_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 |
515 | #define MP0_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L |
516 | #define MP0_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L |
517 | |
518 | |
519 | // addressBlock: mp_SmuMp1Pub_CruDec |
520 | //MP1_FIRMWARE_FLAGS |
521 | #define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 |
522 | #define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 |
523 | #define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L |
524 | #define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL |
525 | //MP1_C2PMSG_0 |
526 | #define MP1_C2PMSG_0__CONTENT__SHIFT 0x0 |
527 | #define MP1_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL |
528 | //MP1_C2PMSG_1 |
529 | #define MP1_C2PMSG_1__CONTENT__SHIFT 0x0 |
530 | #define MP1_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL |
531 | //MP1_C2PMSG_2 |
532 | #define MP1_C2PMSG_2__CONTENT__SHIFT 0x0 |
533 | #define MP1_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL |
534 | //MP1_C2PMSG_3 |
535 | #define MP1_C2PMSG_3__CONTENT__SHIFT 0x0 |
536 | #define MP1_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL |
537 | //MP1_C2PMSG_4 |
538 | #define MP1_C2PMSG_4__CONTENT__SHIFT 0x0 |
539 | #define MP1_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL |
540 | //MP1_C2PMSG_5 |
541 | #define MP1_C2PMSG_5__CONTENT__SHIFT 0x0 |
542 | #define MP1_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL |
543 | //MP1_C2PMSG_6 |
544 | #define MP1_C2PMSG_6__CONTENT__SHIFT 0x0 |
545 | #define MP1_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL |
546 | //MP1_C2PMSG_7 |
547 | #define MP1_C2PMSG_7__CONTENT__SHIFT 0x0 |
548 | #define MP1_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL |
549 | //MP1_C2PMSG_8 |
550 | #define MP1_C2PMSG_8__CONTENT__SHIFT 0x0 |
551 | #define MP1_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL |
552 | //MP1_C2PMSG_9 |
553 | #define MP1_C2PMSG_9__CONTENT__SHIFT 0x0 |
554 | #define MP1_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL |
555 | //MP1_C2PMSG_10 |
556 | #define MP1_C2PMSG_10__CONTENT__SHIFT 0x0 |
557 | #define MP1_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL |
558 | //MP1_C2PMSG_11 |
559 | #define MP1_C2PMSG_11__CONTENT__SHIFT 0x0 |
560 | #define MP1_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL |
561 | //MP1_C2PMSG_12 |
562 | #define MP1_C2PMSG_12__CONTENT__SHIFT 0x0 |
563 | #define MP1_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL |
564 | //MP1_C2PMSG_13 |
565 | #define MP1_C2PMSG_13__CONTENT__SHIFT 0x0 |
566 | #define MP1_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL |
567 | //MP1_C2PMSG_14 |
568 | #define MP1_C2PMSG_14__CONTENT__SHIFT 0x0 |
569 | #define MP1_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL |
570 | //MP1_C2PMSG_15 |
571 | #define MP1_C2PMSG_15__CONTENT__SHIFT 0x0 |
572 | #define MP1_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL |
573 | //MP1_C2PMSG_16 |
574 | #define MP1_C2PMSG_16__CONTENT__SHIFT 0x0 |
575 | #define MP1_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL |
576 | //MP1_C2PMSG_17 |
577 | #define MP1_C2PMSG_17__CONTENT__SHIFT 0x0 |
578 | #define MP1_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL |
579 | //MP1_C2PMSG_18 |
580 | #define MP1_C2PMSG_18__CONTENT__SHIFT 0x0 |
581 | #define MP1_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL |
582 | //MP1_C2PMSG_19 |
583 | #define MP1_C2PMSG_19__CONTENT__SHIFT 0x0 |
584 | #define MP1_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL |
585 | //MP1_C2PMSG_20 |
586 | #define MP1_C2PMSG_20__CONTENT__SHIFT 0x0 |
587 | #define MP1_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL |
588 | //MP1_C2PMSG_21 |
589 | #define MP1_C2PMSG_21__CONTENT__SHIFT 0x0 |
590 | #define MP1_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL |
591 | //MP1_C2PMSG_22 |
592 | #define MP1_C2PMSG_22__CONTENT__SHIFT 0x0 |
593 | #define MP1_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL |
594 | //MP1_C2PMSG_23 |
595 | #define MP1_C2PMSG_23__CONTENT__SHIFT 0x0 |
596 | #define MP1_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL |
597 | //MP1_C2PMSG_24 |
598 | #define MP1_C2PMSG_24__CONTENT__SHIFT 0x0 |
599 | #define MP1_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL |
600 | //MP1_C2PMSG_25 |
601 | #define MP1_C2PMSG_25__CONTENT__SHIFT 0x0 |
602 | #define MP1_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL |
603 | //MP1_C2PMSG_26 |
604 | #define MP1_C2PMSG_26__CONTENT__SHIFT 0x0 |
605 | #define MP1_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL |
606 | //MP1_C2PMSG_27 |
607 | #define MP1_C2PMSG_27__CONTENT__SHIFT 0x0 |
608 | #define MP1_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL |
609 | //MP1_C2PMSG_28 |
610 | #define MP1_C2PMSG_28__CONTENT__SHIFT 0x0 |
611 | #define MP1_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL |
612 | //MP1_C2PMSG_29 |
613 | #define MP1_C2PMSG_29__CONTENT__SHIFT 0x0 |
614 | #define MP1_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL |
615 | //MP1_C2PMSG_30 |
616 | #define MP1_C2PMSG_30__CONTENT__SHIFT 0x0 |
617 | #define MP1_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL |
618 | //MP1_C2PMSG_31 |
619 | #define MP1_C2PMSG_31__CONTENT__SHIFT 0x0 |
620 | #define MP1_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL |
621 | //MP1_P2CMSG_0 |
622 | #define MP1_P2CMSG_0__CONTENT__SHIFT 0x0 |
623 | #define MP1_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL |
624 | //MP1_P2CMSG_1 |
625 | #define MP1_P2CMSG_1__CONTENT__SHIFT 0x0 |
626 | #define MP1_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL |
627 | //MP1_P2CMSG_2 |
628 | #define MP1_P2CMSG_2__CONTENT__SHIFT 0x0 |
629 | #define MP1_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL |
630 | //MP1_P2CMSG_3 |
631 | #define MP1_P2CMSG_3__CONTENT__SHIFT 0x0 |
632 | #define MP1_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL |
633 | //MP1_P2CMSG_INTEN |
634 | #define MP1_P2CMSG_INTEN__INTEN__SHIFT 0x0 |
635 | #define MP1_P2CMSG_INTEN__INTEN_MASK 0x0000000FL |
636 | //MP1_P2CMSG_INTSTS |
637 | #define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0 |
638 | #define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1 |
639 | #define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2 |
640 | #define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3 |
641 | #define MP1_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L |
642 | #define MP1_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L |
643 | #define MP1_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L |
644 | #define MP1_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L |
645 | //MP1_C2PMSG_32 |
646 | #define MP1_C2PMSG_32__CONTENT__SHIFT 0x0 |
647 | #define MP1_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL |
648 | //MP1_C2PMSG_33 |
649 | #define MP1_C2PMSG_33__CONTENT__SHIFT 0x0 |
650 | #define MP1_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL |
651 | //MP1_C2PMSG_34 |
652 | #define MP1_C2PMSG_34__CONTENT__SHIFT 0x0 |
653 | #define MP1_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL |
654 | //MP1_C2PMSG_35 |
655 | #define MP1_C2PMSG_35__CONTENT__SHIFT 0x0 |
656 | #define MP1_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL |
657 | //MP1_C2PMSG_36 |
658 | #define MP1_C2PMSG_36__CONTENT__SHIFT 0x0 |
659 | #define MP1_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL |
660 | //MP1_C2PMSG_37 |
661 | #define MP1_C2PMSG_37__CONTENT__SHIFT 0x0 |
662 | #define MP1_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL |
663 | //MP1_C2PMSG_38 |
664 | #define MP1_C2PMSG_38__CONTENT__SHIFT 0x0 |
665 | #define MP1_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL |
666 | //MP1_C2PMSG_39 |
667 | #define MP1_C2PMSG_39__CONTENT__SHIFT 0x0 |
668 | #define MP1_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL |
669 | //MP1_C2PMSG_40 |
670 | #define MP1_C2PMSG_40__CONTENT__SHIFT 0x0 |
671 | #define MP1_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL |
672 | //MP1_C2PMSG_41 |
673 | #define MP1_C2PMSG_41__CONTENT__SHIFT 0x0 |
674 | #define MP1_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL |
675 | //MP1_C2PMSG_42 |
676 | #define MP1_C2PMSG_42__CONTENT__SHIFT 0x0 |
677 | #define MP1_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL |
678 | //MP1_C2PMSG_43 |
679 | #define MP1_C2PMSG_43__CONTENT__SHIFT 0x0 |
680 | #define MP1_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL |
681 | //MP1_C2PMSG_44 |
682 | #define MP1_C2PMSG_44__CONTENT__SHIFT 0x0 |
683 | #define MP1_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL |
684 | //MP1_C2PMSG_45 |
685 | #define MP1_C2PMSG_45__CONTENT__SHIFT 0x0 |
686 | #define MP1_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL |
687 | //MP1_C2PMSG_46 |
688 | #define MP1_C2PMSG_46__CONTENT__SHIFT 0x0 |
689 | #define MP1_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL |
690 | //MP1_C2PMSG_47 |
691 | #define MP1_C2PMSG_47__CONTENT__SHIFT 0x0 |
692 | #define MP1_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL |
693 | //MP1_C2PMSG_48 |
694 | #define MP1_C2PMSG_48__CONTENT__SHIFT 0x0 |
695 | #define MP1_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL |
696 | //MP1_C2PMSG_49 |
697 | #define MP1_C2PMSG_49__CONTENT__SHIFT 0x0 |
698 | #define MP1_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL |
699 | //MP1_C2PMSG_50 |
700 | #define MP1_C2PMSG_50__CONTENT__SHIFT 0x0 |
701 | #define MP1_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL |
702 | //MP1_C2PMSG_51 |
703 | #define MP1_C2PMSG_51__CONTENT__SHIFT 0x0 |
704 | #define MP1_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL |
705 | //MP1_C2PMSG_52 |
706 | #define MP1_C2PMSG_52__CONTENT__SHIFT 0x0 |
707 | #define MP1_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL |
708 | //MP1_C2PMSG_53 |
709 | #define MP1_C2PMSG_53__CONTENT__SHIFT 0x0 |
710 | #define MP1_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL |
711 | //MP1_C2PMSG_54 |
712 | #define MP1_C2PMSG_54__CONTENT__SHIFT 0x0 |
713 | #define MP1_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL |
714 | //MP1_C2PMSG_55 |
715 | #define MP1_C2PMSG_55__CONTENT__SHIFT 0x0 |
716 | #define MP1_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL |
717 | //MP1_C2PMSG_56 |
718 | #define MP1_C2PMSG_56__CONTENT__SHIFT 0x0 |
719 | #define MP1_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL |
720 | //MP1_C2PMSG_57 |
721 | #define MP1_C2PMSG_57__CONTENT__SHIFT 0x0 |
722 | #define MP1_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL |
723 | //MP1_C2PMSG_58 |
724 | #define MP1_C2PMSG_58__CONTENT__SHIFT 0x0 |
725 | #define MP1_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL |
726 | //MP1_C2PMSG_59 |
727 | #define MP1_C2PMSG_59__CONTENT__SHIFT 0x0 |
728 | #define MP1_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL |
729 | //MP1_C2PMSG_60 |
730 | #define MP1_C2PMSG_60__CONTENT__SHIFT 0x0 |
731 | #define MP1_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL |
732 | //MP1_C2PMSG_61 |
733 | #define MP1_C2PMSG_61__CONTENT__SHIFT 0x0 |
734 | #define MP1_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL |
735 | //MP1_C2PMSG_62 |
736 | #define MP1_C2PMSG_62__CONTENT__SHIFT 0x0 |
737 | #define MP1_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL |
738 | //MP1_C2PMSG_63 |
739 | #define MP1_C2PMSG_63__CONTENT__SHIFT 0x0 |
740 | #define MP1_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL |
741 | //MP1_C2PMSG_64 |
742 | #define MP1_C2PMSG_64__CONTENT__SHIFT 0x0 |
743 | #define MP1_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL |
744 | //MP1_C2PMSG_65 |
745 | #define MP1_C2PMSG_65__CONTENT__SHIFT 0x0 |
746 | #define MP1_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL |
747 | //MP1_C2PMSG_66 |
748 | #define MP1_C2PMSG_66__CONTENT__SHIFT 0x0 |
749 | #define MP1_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL |
750 | //MP1_C2PMSG_67 |
751 | #define MP1_C2PMSG_67__CONTENT__SHIFT 0x0 |
752 | #define MP1_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL |
753 | //MP1_C2PMSG_68 |
754 | #define MP1_C2PMSG_68__CONTENT__SHIFT 0x0 |
755 | #define MP1_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL |
756 | //MP1_C2PMSG_69 |
757 | #define MP1_C2PMSG_69__CONTENT__SHIFT 0x0 |
758 | #define MP1_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL |
759 | //MP1_C2PMSG_70 |
760 | #define MP1_C2PMSG_70__CONTENT__SHIFT 0x0 |
761 | #define MP1_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL |
762 | //MP1_C2PMSG_71 |
763 | #define MP1_C2PMSG_71__CONTENT__SHIFT 0x0 |
764 | #define MP1_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL |
765 | //MP1_C2PMSG_72 |
766 | #define MP1_C2PMSG_72__CONTENT__SHIFT 0x0 |
767 | #define MP1_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL |
768 | //MP1_C2PMSG_73 |
769 | #define MP1_C2PMSG_73__CONTENT__SHIFT 0x0 |
770 | #define MP1_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL |
771 | //MP1_C2PMSG_74 |
772 | #define MP1_C2PMSG_74__CONTENT__SHIFT 0x0 |
773 | #define MP1_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL |
774 | //MP1_C2PMSG_75 |
775 | #define MP1_C2PMSG_75__CONTENT__SHIFT 0x0 |
776 | #define MP1_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL |
777 | //MP1_C2PMSG_76 |
778 | #define MP1_C2PMSG_76__CONTENT__SHIFT 0x0 |
779 | #define MP1_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL |
780 | //MP1_C2PMSG_77 |
781 | #define MP1_C2PMSG_77__CONTENT__SHIFT 0x0 |
782 | #define MP1_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL |
783 | //MP1_C2PMSG_78 |
784 | #define MP1_C2PMSG_78__CONTENT__SHIFT 0x0 |
785 | #define MP1_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL |
786 | //MP1_C2PMSG_79 |
787 | #define MP1_C2PMSG_79__CONTENT__SHIFT 0x0 |
788 | #define MP1_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL |
789 | //MP1_C2PMSG_80 |
790 | #define MP1_C2PMSG_80__CONTENT__SHIFT 0x0 |
791 | #define MP1_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL |
792 | //MP1_C2PMSG_81 |
793 | #define MP1_C2PMSG_81__CONTENT__SHIFT 0x0 |
794 | #define MP1_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL |
795 | //MP1_C2PMSG_82 |
796 | #define MP1_C2PMSG_82__CONTENT__SHIFT 0x0 |
797 | #define MP1_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL |
798 | //MP1_C2PMSG_83 |
799 | #define MP1_C2PMSG_83__CONTENT__SHIFT 0x0 |
800 | #define MP1_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL |
801 | //MP1_C2PMSG_84 |
802 | #define MP1_C2PMSG_84__CONTENT__SHIFT 0x0 |
803 | #define MP1_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL |
804 | //MP1_C2PMSG_85 |
805 | #define MP1_C2PMSG_85__CONTENT__SHIFT 0x0 |
806 | #define MP1_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL |
807 | //MP1_C2PMSG_86 |
808 | #define MP1_C2PMSG_86__CONTENT__SHIFT 0x0 |
809 | #define MP1_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL |
810 | //MP1_C2PMSG_87 |
811 | #define MP1_C2PMSG_87__CONTENT__SHIFT 0x0 |
812 | #define MP1_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL |
813 | //MP1_C2PMSG_88 |
814 | #define MP1_C2PMSG_88__CONTENT__SHIFT 0x0 |
815 | #define MP1_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL |
816 | //MP1_C2PMSG_89 |
817 | #define MP1_C2PMSG_89__CONTENT__SHIFT 0x0 |
818 | #define MP1_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL |
819 | //MP1_C2PMSG_90 |
820 | #define MP1_C2PMSG_90__CONTENT__SHIFT 0x0 |
821 | #define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL |
822 | //MP1_C2PMSG_91 |
823 | #define MP1_C2PMSG_91__CONTENT__SHIFT 0x0 |
824 | #define MP1_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL |
825 | //MP1_C2PMSG_92 |
826 | #define MP1_C2PMSG_92__CONTENT__SHIFT 0x0 |
827 | #define MP1_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL |
828 | //MP1_C2PMSG_93 |
829 | #define MP1_C2PMSG_93__CONTENT__SHIFT 0x0 |
830 | #define MP1_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL |
831 | //MP1_C2PMSG_94 |
832 | #define MP1_C2PMSG_94__CONTENT__SHIFT 0x0 |
833 | #define MP1_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL |
834 | //MP1_C2PMSG_95 |
835 | #define MP1_C2PMSG_95__CONTENT__SHIFT 0x0 |
836 | #define MP1_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL |
837 | //MP1_C2PMSG_96 |
838 | #define MP1_C2PMSG_96__CONTENT__SHIFT 0x0 |
839 | #define MP1_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL |
840 | //MP1_C2PMSG_97 |
841 | #define MP1_C2PMSG_97__CONTENT__SHIFT 0x0 |
842 | #define MP1_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL |
843 | //MP1_C2PMSG_98 |
844 | #define MP1_C2PMSG_98__CONTENT__SHIFT 0x0 |
845 | #define MP1_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL |
846 | //MP1_C2PMSG_99 |
847 | #define MP1_C2PMSG_99__CONTENT__SHIFT 0x0 |
848 | #define MP1_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL |
849 | //MP1_C2PMSG_100 |
850 | #define MP1_C2PMSG_100__CONTENT__SHIFT 0x0 |
851 | #define MP1_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL |
852 | //MP1_C2PMSG_101 |
853 | #define MP1_C2PMSG_101__CONTENT__SHIFT 0x0 |
854 | #define MP1_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL |
855 | //MP1_C2PMSG_102 |
856 | #define MP1_C2PMSG_102__CONTENT__SHIFT 0x0 |
857 | #define MP1_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL |
858 | //MP1_C2PMSG_103 |
859 | #define MP1_C2PMSG_103__CONTENT__SHIFT 0x0 |
860 | #define MP1_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL |
861 | //MP1_ACTIVE_FCN_ID |
862 | #define MP1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 |
863 | #define MP1_ACTIVE_FCN_ID__VF__SHIFT 0x1f |
864 | #define MP1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL |
865 | #define MP1_ACTIVE_FCN_ID__VF_MASK 0x80000000L |
866 | //MP1_IH_CREDIT |
867 | #define MP1_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 |
868 | #define MP1_IH_CREDIT__CLIENT_ID__SHIFT 0x10 |
869 | #define MP1_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L |
870 | #define MP1_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L |
871 | //MP1_IH_SW_INT |
872 | #define MP1_IH_SW_INT__ID__SHIFT 0x0 |
873 | #define MP1_IH_SW_INT__VALID__SHIFT 0x8 |
874 | #define MP1_IH_SW_INT__ID_MASK 0x000000FFL |
875 | #define MP1_IH_SW_INT__VALID_MASK 0x00000100L |
876 | //MP1_IH_SW_INT_CTRL |
877 | #define MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 |
878 | #define MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 |
879 | #define MP1_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L |
880 | #define MP1_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L |
881 | //MP1_FPS_CNT |
882 | #define MP1_FPS_CNT__COUNT__SHIFT 0x0 |
883 | #define MP1_FPS_CNT__COUNT_MASK 0xFFFFFFFFL |
884 | |
885 | |
886 | #endif |
887 | |