| 1 | /* |
|---|
| 2 | * |
|---|
| 3 | * Copyright (C) 2016 Advanced Micro Devices, Inc. |
|---|
| 4 | * |
|---|
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
|---|
| 6 | * copy of this software and associated documentation files (the "Software"), |
|---|
| 7 | * to deal in the Software without restriction, including without limitation |
|---|
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
|---|
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
|---|
| 10 | * Software is furnished to do so, subject to the following conditions: |
|---|
| 11 | * |
|---|
| 12 | * The above copyright notice and this permission notice shall be included |
|---|
| 13 | * in all copies or substantial portions of the Software. |
|---|
| 14 | * |
|---|
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
|---|
| 16 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
|---|
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
|---|
| 18 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
|---|
| 19 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
|---|
| 20 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
|---|
| 21 | */ |
|---|
| 22 | |
|---|
| 23 | #ifndef OSS_1_0_SH_MASK_H |
|---|
| 24 | #define OSS_1_0_SH_MASK_H |
|---|
| 25 | |
|---|
| 26 | #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000L |
|---|
| 27 | #define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x0000001c |
|---|
| 28 | #define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0x000ffff0L |
|---|
| 29 | #define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x00000004 |
|---|
| 30 | #define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0x00f00000L |
|---|
| 31 | #define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x00000014 |
|---|
| 32 | #define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0x0f000000L |
|---|
| 33 | #define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x00000018 |
|---|
| 34 | #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L |
|---|
| 35 | #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010 |
|---|
| 36 | #define CLIENT0_BM__RESERVED_MASK 0xffffffffL |
|---|
| 37 | #define CLIENT0_BM__RESERVED__SHIFT 0x00000000 |
|---|
| 38 | #define CLIENT0_CD0__RESERVED_MASK 0xffffffffL |
|---|
| 39 | #define CLIENT0_CD0__RESERVED__SHIFT 0x00000000 |
|---|
| 40 | #define CLIENT0_CD1__RESERVED_MASK 0xffffffffL |
|---|
| 41 | #define CLIENT0_CD1__RESERVED__SHIFT 0x00000000 |
|---|
| 42 | #define CLIENT0_CD2__RESERVED_MASK 0xffffffffL |
|---|
| 43 | #define CLIENT0_CD2__RESERVED__SHIFT 0x00000000 |
|---|
| 44 | #define CLIENT0_CD3__RESERVED_MASK 0xffffffffL |
|---|
| 45 | #define CLIENT0_CD3__RESERVED__SHIFT 0x00000000 |
|---|
| 46 | #define CLIENT0_CK0__RESERVED_MASK 0xffffffffL |
|---|
| 47 | #define CLIENT0_CK0__RESERVED__SHIFT 0x00000000 |
|---|
| 48 | #define CLIENT0_CK1__RESERVED_MASK 0xffffffffL |
|---|
| 49 | #define CLIENT0_CK1__RESERVED__SHIFT 0x00000000 |
|---|
| 50 | #define CLIENT0_CK2__RESERVED_MASK 0xffffffffL |
|---|
| 51 | #define CLIENT0_CK2__RESERVED__SHIFT 0x00000000 |
|---|
| 52 | #define CLIENT0_CK3__RESERVED_MASK 0xffffffffL |
|---|
| 53 | #define CLIENT0_CK3__RESERVED__SHIFT 0x00000000 |
|---|
| 54 | #define CLIENT0_K0__RESERVED_MASK 0xffffffffL |
|---|
| 55 | #define CLIENT0_K0__RESERVED__SHIFT 0x00000000 |
|---|
| 56 | #define CLIENT0_K1__RESERVED_MASK 0xffffffffL |
|---|
| 57 | #define CLIENT0_K1__RESERVED__SHIFT 0x00000000 |
|---|
| 58 | #define CLIENT0_K2__RESERVED_MASK 0xffffffffL |
|---|
| 59 | #define CLIENT0_K2__RESERVED__SHIFT 0x00000000 |
|---|
| 60 | #define CLIENT0_K3__RESERVED_MASK 0xffffffffL |
|---|
| 61 | #define CLIENT0_K3__RESERVED__SHIFT 0x00000000 |
|---|
| 62 | #define CLIENT0_OFFSET_HI__RESERVED_MASK 0xffffffffL |
|---|
| 63 | #define CLIENT0_OFFSET_HI__RESERVED__SHIFT 0x00000000 |
|---|
| 64 | #define CLIENT0_OFFSET__RESERVED_MASK 0xffffffffL |
|---|
| 65 | #define CLIENT0_OFFSET__RESERVED__SHIFT 0x00000000 |
|---|
| 66 | #define CLIENT0_STATUS__RESERVED_MASK 0xffffffffL |
|---|
| 67 | #define CLIENT0_STATUS__RESERVED__SHIFT 0x00000000 |
|---|
| 68 | #define CLIENT1_BM__RESERVED_MASK 0xffffffffL |
|---|
| 69 | #define CLIENT1_BM__RESERVED__SHIFT 0x00000000 |
|---|
| 70 | #define CLIENT1_CD0__RESERVED_MASK 0xffffffffL |
|---|
| 71 | #define CLIENT1_CD0__RESERVED__SHIFT 0x00000000 |
|---|
| 72 | #define CLIENT1_CD1__RESERVED_MASK 0xffffffffL |
|---|
| 73 | #define CLIENT1_CD1__RESERVED__SHIFT 0x00000000 |
|---|
| 74 | #define CLIENT1_CD2__RESERVED_MASK 0xffffffffL |
|---|
| 75 | #define CLIENT1_CD2__RESERVED__SHIFT 0x00000000 |
|---|
| 76 | #define CLIENT1_CD3__RESERVED_MASK 0xffffffffL |
|---|
| 77 | #define CLIENT1_CD3__RESERVED__SHIFT 0x00000000 |
|---|
| 78 | #define CLIENT1_CK0__RESERVED_MASK 0xffffffffL |
|---|
| 79 | #define CLIENT1_CK0__RESERVED__SHIFT 0x00000000 |
|---|
| 80 | #define CLIENT1_CK1__RESERVED_MASK 0xffffffffL |
|---|
| 81 | #define CLIENT1_CK1__RESERVED__SHIFT 0x00000000 |
|---|
| 82 | #define CLIENT1_CK2__RESERVED_MASK 0xffffffffL |
|---|
| 83 | #define CLIENT1_CK2__RESERVED__SHIFT 0x00000000 |
|---|
| 84 | #define CLIENT1_CK3__RESERVED_MASK 0xffffffffL |
|---|
| 85 | #define CLIENT1_CK3__RESERVED__SHIFT 0x00000000 |
|---|
| 86 | #define CLIENT1_K0__RESERVED_MASK 0xffffffffL |
|---|
| 87 | #define CLIENT1_K0__RESERVED__SHIFT 0x00000000 |
|---|
| 88 | #define CLIENT1_K1__RESERVED_MASK 0xffffffffL |
|---|
| 89 | #define CLIENT1_K1__RESERVED__SHIFT 0x00000000 |
|---|
| 90 | #define CLIENT1_K2__RESERVED_MASK 0xffffffffL |
|---|
| 91 | #define CLIENT1_K2__RESERVED__SHIFT 0x00000000 |
|---|
| 92 | #define CLIENT1_K3__RESERVED_MASK 0xffffffffL |
|---|
| 93 | #define CLIENT1_K3__RESERVED__SHIFT 0x00000000 |
|---|
| 94 | #define CLIENT1_OFFSET_HI__RESERVED_MASK 0xffffffffL |
|---|
| 95 | #define CLIENT1_OFFSET_HI__RESERVED__SHIFT 0x00000000 |
|---|
| 96 | #define CLIENT1_OFFSET__RESERVED_MASK 0xffffffffL |
|---|
| 97 | #define CLIENT1_OFFSET__RESERVED__SHIFT 0x00000000 |
|---|
| 98 | #define CLIENT1_PORT_STATUS__RESERVED_MASK 0xffffffffL |
|---|
| 99 | #define CLIENT1_PORT_STATUS__RESERVED__SHIFT 0x00000000 |
|---|
| 100 | #define CLIENT2_BM__RESERVED_MASK 0xffffffffL |
|---|
| 101 | #define CLIENT2_BM__RESERVED__SHIFT 0x00000000 |
|---|
| 102 | #define CLIENT2_CD0__RESERVED_MASK 0xffffffffL |
|---|
| 103 | #define CLIENT2_CD0__RESERVED__SHIFT 0x00000000 |
|---|
| 104 | #define CLIENT2_CD1__RESERVED_MASK 0xffffffffL |
|---|
| 105 | #define CLIENT2_CD1__RESERVED__SHIFT 0x00000000 |
|---|
| 106 | #define CLIENT2_CD2__RESERVED_MASK 0xffffffffL |
|---|
| 107 | #define CLIENT2_CD2__RESERVED__SHIFT 0x00000000 |
|---|
| 108 | #define CLIENT2_CD3__RESERVED_MASK 0xffffffffL |
|---|
| 109 | #define CLIENT2_CD3__RESERVED__SHIFT 0x00000000 |
|---|
| 110 | #define CLIENT2_CK0__RESERVED_MASK 0xffffffffL |
|---|
| 111 | #define CLIENT2_CK0__RESERVED__SHIFT 0x00000000 |
|---|
| 112 | #define CLIENT2_CK1__RESERVED_MASK 0xffffffffL |
|---|
| 113 | #define CLIENT2_CK1__RESERVED__SHIFT 0x00000000 |
|---|
| 114 | #define CLIENT2_CK2__RESERVED_MASK 0xffffffffL |
|---|
| 115 | #define CLIENT2_CK2__RESERVED__SHIFT 0x00000000 |
|---|
| 116 | #define CLIENT2_CK3__RESERVED_MASK 0xffffffffL |
|---|
| 117 | #define CLIENT2_CK3__RESERVED__SHIFT 0x00000000 |
|---|
| 118 | #define CLIENT2_K0__RESERVED_MASK 0xffffffffL |
|---|
| 119 | #define CLIENT2_K0__RESERVED__SHIFT 0x00000000 |
|---|
| 120 | #define CLIENT2_K1__RESERVED_MASK 0xffffffffL |
|---|
| 121 | #define CLIENT2_K1__RESERVED__SHIFT 0x00000000 |
|---|
| 122 | #define CLIENT2_K2__RESERVED_MASK 0xffffffffL |
|---|
| 123 | #define CLIENT2_K2__RESERVED__SHIFT 0x00000000 |
|---|
| 124 | #define CLIENT2_K3__RESERVED_MASK 0xffffffffL |
|---|
| 125 | #define CLIENT2_K3__RESERVED__SHIFT 0x00000000 |
|---|
| 126 | #define CLIENT2_OFFSET_HI__RESERVED_MASK 0xffffffffL |
|---|
| 127 | #define CLIENT2_OFFSET_HI__RESERVED__SHIFT 0x00000000 |
|---|
| 128 | #define CLIENT2_OFFSET__RESERVED_MASK 0xffffffffL |
|---|
| 129 | #define CLIENT2_OFFSET__RESERVED__SHIFT 0x00000000 |
|---|
| 130 | #define CLIENT2_STATUS__RESERVED_MASK 0xffffffffL |
|---|
| 131 | #define CLIENT2_STATUS__RESERVED__SHIFT 0x00000000 |
|---|
| 132 | #define CLIENT3_BM__RESERVED_MASK 0xffffffffL |
|---|
| 133 | #define CLIENT3_BM__RESERVED__SHIFT 0x00000000 |
|---|
| 134 | #define CLIENT3_CD0__RESERVED_MASK 0xffffffffL |
|---|
| 135 | #define CLIENT3_CD0__RESERVED__SHIFT 0x00000000 |
|---|
| 136 | #define CLIENT3_CD1__RESERVED_MASK 0xffffffffL |
|---|
| 137 | #define CLIENT3_CD1__RESERVED__SHIFT 0x00000000 |
|---|
| 138 | #define CLIENT3_CD2__RESERVED_MASK 0xffffffffL |
|---|
| 139 | #define CLIENT3_CD2__RESERVED__SHIFT 0x00000000 |
|---|
| 140 | #define CLIENT3_CD3__RESERVED_MASK 0xffffffffL |
|---|
| 141 | #define CLIENT3_CD3__RESERVED__SHIFT 0x00000000 |
|---|
| 142 | #define CLIENT3_CK0__RESERVED_MASK 0xffffffffL |
|---|
| 143 | #define CLIENT3_CK0__RESERVED__SHIFT 0x00000000 |
|---|
| 144 | #define CLIENT3_CK1__RESERVED_MASK 0xffffffffL |
|---|
| 145 | #define CLIENT3_CK1__RESERVED__SHIFT 0x00000000 |
|---|
| 146 | #define CLIENT3_CK2__RESERVED_MASK 0xffffffffL |
|---|
| 147 | #define CLIENT3_CK2__RESERVED__SHIFT 0x00000000 |
|---|
| 148 | #define CLIENT3_CK3__RESERVED_MASK 0xffffffffL |
|---|
| 149 | #define CLIENT3_CK3__RESERVED__SHIFT 0x00000000 |
|---|
| 150 | #define CLIENT3_K0__RESERVED_MASK 0xffffffffL |
|---|
| 151 | #define CLIENT3_K0__RESERVED__SHIFT 0x00000000 |
|---|
| 152 | #define CLIENT3_K1__RESERVED_MASK 0xffffffffL |
|---|
| 153 | #define CLIENT3_K1__RESERVED__SHIFT 0x00000000 |
|---|
| 154 | #define CLIENT3_K2__RESERVED_MASK 0xffffffffL |
|---|
| 155 | #define CLIENT3_K2__RESERVED__SHIFT 0x00000000 |
|---|
| 156 | #define CLIENT3_K3__RESERVED_MASK 0xffffffffL |
|---|
| 157 | #define CLIENT3_K3__RESERVED__SHIFT 0x00000000 |
|---|
| 158 | #define CLIENT3_OFFSET_HI__RESERVED_MASK 0xffffffffL |
|---|
| 159 | #define CLIENT3_OFFSET_HI__RESERVED__SHIFT 0x00000000 |
|---|
| 160 | #define CLIENT3_OFFSET__RESERVED_MASK 0xffffffffL |
|---|
| 161 | #define CLIENT3_OFFSET__RESERVED__SHIFT 0x00000000 |
|---|
| 162 | #define CLIENT3_STATUS__RESERVED_MASK 0xffffffffL |
|---|
| 163 | #define CLIENT3_STATUS__RESERVED__SHIFT 0x00000000 |
|---|
| 164 | #define CP_CONFIG__CP_RDREQ_URG_MASK 0x00000f00L |
|---|
| 165 | #define CP_CONFIG__CP_RDREQ_URG__SHIFT 0x00000008 |
|---|
| 166 | #define CP_CONFIG__CP_REQ_TRAN_MASK 0x00010000L |
|---|
| 167 | #define CP_CONFIG__CP_REQ_TRAN__SHIFT 0x00000010 |
|---|
| 168 | #define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA_MASK 0xffffffffL |
|---|
| 169 | #define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA__SHIFT 0x00000000 |
|---|
| 170 | #define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX_MASK 0x000000ffL |
|---|
| 171 | #define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX__SHIFT 0x00000000 |
|---|
| 172 | #define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN_MASK 0x00000100L |
|---|
| 173 | #define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 |
|---|
| 174 | #define DH_TEST__DH_TEST_MASK 0x00000001L |
|---|
| 175 | #define DH_TEST__DH_TEST__SHIFT 0x00000000 |
|---|
| 176 | #define EXP0__RESERVED_MASK 0xffffffffL |
|---|
| 177 | #define EXP0__RESERVED__SHIFT 0x00000000 |
|---|
| 178 | #define EXP1__RESERVED_MASK 0xffffffffL |
|---|
| 179 | #define EXP1__RESERVED__SHIFT 0x00000000 |
|---|
| 180 | #define EXP2__RESERVED_MASK 0xffffffffL |
|---|
| 181 | #define EXP2__RESERVED__SHIFT 0x00000000 |
|---|
| 182 | #define EXP3__RESERVED_MASK 0xffffffffL |
|---|
| 183 | #define EXP3__RESERVED__SHIFT 0x00000000 |
|---|
| 184 | #define EXP4__RESERVED_MASK 0xffffffffL |
|---|
| 185 | #define EXP4__RESERVED__SHIFT 0x00000000 |
|---|
| 186 | #define EXP5__RESERVED_MASK 0xffffffffL |
|---|
| 187 | #define EXP5__RESERVED__SHIFT 0x00000000 |
|---|
| 188 | #define EXP6__RESERVED_MASK 0xffffffffL |
|---|
| 189 | #define EXP6__RESERVED__SHIFT 0x00000000 |
|---|
| 190 | #define EXP7__RESERVED_MASK 0xffffffffL |
|---|
| 191 | #define EXP7__RESERVED__SHIFT 0x00000000 |
|---|
| 192 | #define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L |
|---|
| 193 | #define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010 |
|---|
| 194 | #define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L |
|---|
| 195 | #define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 |
|---|
| 196 | #define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L |
|---|
| 197 | #define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018 |
|---|
| 198 | #define HDP_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L |
|---|
| 199 | #define HDP_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014 |
|---|
| 200 | #define HDP_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L |
|---|
| 201 | #define HDP_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e |
|---|
| 202 | #define HDP_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L |
|---|
| 203 | #define HDP_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 |
|---|
| 204 | #define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L |
|---|
| 205 | #define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c |
|---|
| 206 | #define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L |
|---|
| 207 | #define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 |
|---|
| 208 | #define HDP_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L |
|---|
| 209 | #define HDP_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c |
|---|
| 210 | #define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L |
|---|
| 211 | #define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 |
|---|
| 212 | #define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x00000000 |
|---|
| 213 | #define HDP_DEBUG1__HDP_DEBUG__SHIFT 0x00000000 |
|---|
| 214 | #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000L |
|---|
| 215 | #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x0000001d |
|---|
| 216 | #define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK 0x00000007L |
|---|
| 217 | #define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT 0x00000000 |
|---|
| 218 | #define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK 0x00400000L |
|---|
| 219 | #define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT 0x00000016 |
|---|
| 220 | #define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK 0x00800000L |
|---|
| 221 | #define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT 0x00000017 |
|---|
| 222 | #define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000L |
|---|
| 223 | #define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x0000001f |
|---|
| 224 | #define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK 0x000001f8L |
|---|
| 225 | #define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x00000003 |
|---|
| 226 | #define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x00001800L |
|---|
| 227 | #define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0x0000000b |
|---|
| 228 | #define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK 0x0f000000L |
|---|
| 229 | #define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x00000018 |
|---|
| 230 | #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x00200000L |
|---|
| 231 | #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x00000015 |
|---|
| 232 | #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x00180000L |
|---|
| 233 | #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x00000013 |
|---|
| 234 | #define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000L |
|---|
| 235 | #define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x0000001e |
|---|
| 236 | #define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x00000600L |
|---|
| 237 | #define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x00000009 |
|---|
| 238 | #define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x0000003fL |
|---|
| 239 | #define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x00000000 |
|---|
| 240 | #define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xffffffffL |
|---|
| 241 | #define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x00000000 |
|---|
| 242 | #define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x00003f00L |
|---|
| 243 | #define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x00000008 |
|---|
| 244 | #define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x0000003cL |
|---|
| 245 | #define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x00000002 |
|---|
| 246 | #define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x00008000L |
|---|
| 247 | #define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0x0000000f |
|---|
| 248 | #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x00004000L |
|---|
| 249 | #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0x0000000e |
|---|
| 250 | #define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x00000002L |
|---|
| 251 | #define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x00000001 |
|---|
| 252 | #define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x00000080L |
|---|
| 253 | #define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x00000007 |
|---|
| 254 | #define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x00000001L |
|---|
| 255 | #define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x00000000 |
|---|
| 256 | #define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x00000040L |
|---|
| 257 | #define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x00000006 |
|---|
| 258 | #define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xffffffffL |
|---|
| 259 | #define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x00000000 |
|---|
| 260 | #define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x00000008L |
|---|
| 261 | #define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x00000003 |
|---|
| 262 | #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x00000002L |
|---|
| 263 | #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x00000001 |
|---|
| 264 | #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x00000004L |
|---|
| 265 | #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x00000002 |
|---|
| 266 | #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x00000001L |
|---|
| 267 | #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x00000000 |
|---|
| 268 | #define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xffffffffL |
|---|
| 269 | #define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x00000000 |
|---|
| 270 | #define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x00000001L |
|---|
| 271 | #define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x00000000 |
|---|
| 272 | #define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x00001f80L |
|---|
| 273 | #define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x00000007 |
|---|
| 274 | #define HDP_MEM_POWER_LS__LS_SETUP_MASK 0x0000007eL |
|---|
| 275 | #define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x00000001 |
|---|
| 276 | #define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS_MASK 0x00100000L |
|---|
| 277 | #define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS__SHIFT 0x00000014 |
|---|
| 278 | #define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L |
|---|
| 279 | #define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x00000015 |
|---|
| 280 | #define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x00000001L |
|---|
| 281 | #define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x00000000 |
|---|
| 282 | #define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT_MASK 0x00000780L |
|---|
| 283 | #define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT__SHIFT 0x00000007 |
|---|
| 284 | #define HDP_MISC_CNTL__MC_RDREQ_CREDIT_MASK 0x0007e000L |
|---|
| 285 | #define HDP_MISC_CNTL__MC_RDREQ_CREDIT__SHIFT 0x0000000d |
|---|
| 286 | #define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x00000040L |
|---|
| 287 | #define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x00000006 |
|---|
| 288 | #define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR_MASK 0x00001000L |
|---|
| 289 | #define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR__SHIFT 0x0000000c |
|---|
| 290 | #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L |
|---|
| 291 | #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x00000005 |
|---|
| 292 | #define HDP_MISC_CNTL__READ_CACHE_INVALIDATE_MASK 0x00080000L |
|---|
| 293 | #define HDP_MISC_CNTL__READ_CACHE_INVALIDATE__SHIFT 0x00000013 |
|---|
| 294 | #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L |
|---|
| 295 | #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0x0000000b |
|---|
| 296 | #define HDP_MISC_CNTL__VM_ID_MASK 0x0000001eL |
|---|
| 297 | #define HDP_MISC_CNTL__VM_ID__SHIFT 0x00000001 |
|---|
| 298 | #define HDP_NONSURFACE_BASE__NONSURF_BASE_MASK 0xffffffffL |
|---|
| 299 | #define HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT 0x00000000 |
|---|
| 300 | #define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x00000001L |
|---|
| 301 | #define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT 0x00000000 |
|---|
| 302 | #define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK 0x0000001eL |
|---|
| 303 | #define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x00000001 |
|---|
| 304 | #define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT_MASK 0x03000000L |
|---|
| 305 | #define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT__SHIFT 0x00000018 |
|---|
| 306 | #define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH_MASK 0x00c00000L |
|---|
| 307 | #define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH__SHIFT 0x00000016 |
|---|
| 308 | #define HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK 0x00000060L |
|---|
| 309 | #define HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT 0x00000005 |
|---|
| 310 | #define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT_MASK 0x0c000000L |
|---|
| 311 | #define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT__SHIFT 0x0000001a |
|---|
| 312 | #define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE_MASK 0x30000000L |
|---|
| 313 | #define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE__SHIFT 0x0000001c |
|---|
| 314 | #define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS_MASK 0x00300000L |
|---|
| 315 | #define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS__SHIFT 0x00000014 |
|---|
| 316 | #define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK 0x00000380L |
|---|
| 317 | #define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT 0x00000007 |
|---|
| 318 | #define HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK 0x00008000L |
|---|
| 319 | #define HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT 0x0000000f |
|---|
| 320 | #define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK 0x00001c00L |
|---|
| 321 | #define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0x0000000a |
|---|
| 322 | #define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK 0x00006000L |
|---|
| 323 | #define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT 0x0000000d |
|---|
| 324 | #define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB_MASK 0x40000000L |
|---|
| 325 | #define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB__SHIFT 0x0000001e |
|---|
| 326 | #define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK 0x00010000L |
|---|
| 327 | #define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT 0x00000010 |
|---|
| 328 | #define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT_MASK 0x000e0000L |
|---|
| 329 | #define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT__SHIFT 0x00000011 |
|---|
| 330 | #define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG_MASK 0xf8000000L |
|---|
| 331 | #define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG__SHIFT 0x0000001b |
|---|
| 332 | #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR_MASK 0x00000038L |
|---|
| 333 | #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR__SHIFT 0x00000003 |
|---|
| 334 | #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z_MASK 0x000ffe00L |
|---|
| 335 | #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z__SHIFT 0x00000009 |
|---|
| 336 | #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM_MASK 0x000001c0L |
|---|
| 337 | #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM__SHIFT 0x00000006 |
|---|
| 338 | #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI_MASK 0x00000007L |
|---|
| 339 | #define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI__SHIFT 0x00000000 |
|---|
| 340 | #define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK 0x000007ffL |
|---|
| 341 | #define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT 0x00000000 |
|---|
| 342 | #define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK 0xfffff800L |
|---|
| 343 | #define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT 0x0000000b |
|---|
| 344 | #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x00000002L |
|---|
| 345 | #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x00000001 |
|---|
| 346 | #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x00000001L |
|---|
| 347 | #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x00000000 |
|---|
| 348 | #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x00000002L |
|---|
| 349 | #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x00000001 |
|---|
| 350 | #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x00000001L |
|---|
| 351 | #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x00000000 |
|---|
| 352 | #define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0x0000ff00L |
|---|
| 353 | #define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x00000008 |
|---|
| 354 | #define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0x000000ffL |
|---|
| 355 | #define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x00000000 |
|---|
| 356 | #define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK 0x00000007L |
|---|
| 357 | #define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT 0x00000000 |
|---|
| 358 | #define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK 0x00000018L |
|---|
| 359 | #define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT 0x00000003 |
|---|
| 360 | #define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xffffffffL |
|---|
| 361 | #define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x00000000 |
|---|
| 362 | #define HDP_TILING_CONFIG__BANK_SWAPS_MASK 0x00003800L |
|---|
| 363 | #define HDP_TILING_CONFIG__BANK_SWAPS__SHIFT 0x0000000b |
|---|
| 364 | #define HDP_TILING_CONFIG__BANK_TILING_MASK 0x00000030L |
|---|
| 365 | #define HDP_TILING_CONFIG__BANK_TILING__SHIFT 0x00000004 |
|---|
| 366 | #define HDP_TILING_CONFIG__GROUP_SIZE_MASK 0x000000c0L |
|---|
| 367 | #define HDP_TILING_CONFIG__GROUP_SIZE__SHIFT 0x00000006 |
|---|
| 368 | #define HDP_TILING_CONFIG__PIPE_TILING_MASK 0x0000000eL |
|---|
| 369 | #define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x00000001 |
|---|
| 370 | #define HDP_TILING_CONFIG__ROW_TILING_MASK 0x00000700L |
|---|
| 371 | #define HDP_TILING_CONFIG__ROW_TILING__SHIFT 0x00000008 |
|---|
| 372 | #define HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK 0x0000c000L |
|---|
| 373 | #define HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT 0x0000000e |
|---|
| 374 | #define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0x0000000fL |
|---|
| 375 | #define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x00000000 |
|---|
| 376 | #define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0x000000f0L |
|---|
| 377 | #define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x00000004 |
|---|
| 378 | #define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0x00000f00L |
|---|
| 379 | #define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x00000008 |
|---|
| 380 | #define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0x0000f000L |
|---|
| 381 | #define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0x0000000c |
|---|
| 382 | #define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0x000f0000L |
|---|
| 383 | #define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x00000010 |
|---|
| 384 | #define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0x00f00000L |
|---|
| 385 | #define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x00000014 |
|---|
| 386 | #define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0x0f000000L |
|---|
| 387 | #define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x00000018 |
|---|
| 388 | #define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xf0000000L |
|---|
| 389 | #define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x0000001c |
|---|
| 390 | #define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x0003ffffL |
|---|
| 391 | #define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x00000000 |
|---|
| 392 | #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK 0x0000000fL |
|---|
| 393 | #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT 0x00000000 |
|---|
| 394 | #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK 0x00000ff0L |
|---|
| 395 | #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT 0x00000004 |
|---|
| 396 | #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK 0x3ffff000L |
|---|
| 397 | #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT 0x0000000c |
|---|
| 398 | #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK 0x40000000L |
|---|
| 399 | #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT 0x0000001e |
|---|
| 400 | #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK 0x80000000L |
|---|
| 401 | #define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT 0x0000001f |
|---|
| 402 | #define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0x000000ffL |
|---|
| 403 | #define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x00000000 |
|---|
| 404 | #define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0x0000ff00L |
|---|
| 405 | #define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x00000008 |
|---|
| 406 | #define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0x00ff0000L |
|---|
| 407 | #define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x00000010 |
|---|
| 408 | #define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xff000000L |
|---|
| 409 | #define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x00000018 |
|---|
| 410 | #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0x0000ffffL |
|---|
| 411 | #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x00000000 |
|---|
| 412 | #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x00700000L |
|---|
| 413 | #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x00000014 |
|---|
| 414 | #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0x000f0000L |
|---|
| 415 | #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x00000010 |
|---|
| 416 | #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x00040000L |
|---|
| 417 | #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x00000012 |
|---|
| 418 | #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0x0000000fL |
|---|
| 419 | #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x00000000 |
|---|
| 420 | #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x00000700L |
|---|
| 421 | #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x00000008 |
|---|
| 422 | #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0x000000f0L |
|---|
| 423 | #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x00000004 |
|---|
| 424 | #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x00080000L |
|---|
| 425 | #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x00000013 |
|---|
| 426 | #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x00100000L |
|---|
| 427 | #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x00000014 |
|---|
| 428 | #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x00010000L |
|---|
| 429 | #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x00000010 |
|---|
| 430 | #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK 0x00020000L |
|---|
| 431 | #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT 0x00000011 |
|---|
| 432 | #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0x0000f800L |
|---|
| 433 | #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0x0000000b |
|---|
| 434 | #define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xffffffffL |
|---|
| 435 | #define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x00000000 |
|---|
| 436 | #define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xffffffffL |
|---|
| 437 | #define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x00000000 |
|---|
| 438 | #define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xffffffffL |
|---|
| 439 | #define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x00000000 |
|---|
| 440 | #define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xffffffffL |
|---|
| 441 | #define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x00000000 |
|---|
| 442 | #define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xffffffffL |
|---|
| 443 | #define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x00000000 |
|---|
| 444 | #define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xffffffffL |
|---|
| 445 | #define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x00000000 |
|---|
| 446 | #define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xffffffffL |
|---|
| 447 | #define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x00000000 |
|---|
| 448 | #define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xffffffffL |
|---|
| 449 | #define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x00000000 |
|---|
| 450 | #define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xffffffffL |
|---|
| 451 | #define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x00000000 |
|---|
| 452 | #define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xffffffffL |
|---|
| 453 | #define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x00000000 |
|---|
| 454 | #define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xffffffffL |
|---|
| 455 | #define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x00000000 |
|---|
| 456 | #define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xffffffffL |
|---|
| 457 | #define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x00000000 |
|---|
| 458 | #define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xffffffffL |
|---|
| 459 | #define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x00000000 |
|---|
| 460 | #define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xffffffffL |
|---|
| 461 | #define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x00000000 |
|---|
| 462 | #define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xffffffffL |
|---|
| 463 | #define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x00000000 |
|---|
| 464 | #define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xffffffffL |
|---|
| 465 | #define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x00000000 |
|---|
| 466 | #define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xffffffffL |
|---|
| 467 | #define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x00000000 |
|---|
| 468 | #define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xffffffffL |
|---|
| 469 | #define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x00000000 |
|---|
| 470 | #define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xffffffffL |
|---|
| 471 | #define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x00000000 |
|---|
| 472 | #define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xffffffffL |
|---|
| 473 | #define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x00000000 |
|---|
| 474 | #define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xffffffffL |
|---|
| 475 | #define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x00000000 |
|---|
| 476 | #define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xffffffffL |
|---|
| 477 | #define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x00000000 |
|---|
| 478 | #define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xffffffffL |
|---|
| 479 | #define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x00000000 |
|---|
| 480 | #define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xffffffffL |
|---|
| 481 | #define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x00000000 |
|---|
| 482 | #define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xffffffffL |
|---|
| 483 | #define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x00000000 |
|---|
| 484 | #define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xffffffffL |
|---|
| 485 | #define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x00000000 |
|---|
| 486 | #define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xffffffffL |
|---|
| 487 | #define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x00000000 |
|---|
| 488 | #define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xffffffffL |
|---|
| 489 | #define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x00000000 |
|---|
| 490 | #define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xffffffffL |
|---|
| 491 | #define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x00000000 |
|---|
| 492 | #define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xffffffffL |
|---|
| 493 | #define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x00000000 |
|---|
| 494 | #define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xffffffffL |
|---|
| 495 | #define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x00000000 |
|---|
| 496 | #define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xffffffffL |
|---|
| 497 | #define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x00000000 |
|---|
| 498 | #define HDP_XDP_DBG_ADDR__CTRL_MASK 0xffff0000L |
|---|
| 499 | #define HDP_XDP_DBG_ADDR__CTRL__SHIFT 0x00000010 |
|---|
| 500 | #define HDP_XDP_DBG_ADDR__STS_MASK 0x0000ffffL |
|---|
| 501 | #define HDP_XDP_DBG_ADDR__STS__SHIFT 0x00000000 |
|---|
| 502 | #define HDP_XDP_DBG_DATA__CTRL_MASK 0xffff0000L |
|---|
| 503 | #define HDP_XDP_DBG_DATA__CTRL__SHIFT 0x00000010 |
|---|
| 504 | #define HDP_XDP_DBG_DATA__STS_MASK 0x0000ffffL |
|---|
| 505 | #define HDP_XDP_DBG_DATA__STS__SHIFT 0x00000000 |
|---|
| 506 | #define HDP_XDP_DBG_MASK__CTRL_MASK 0xffff0000L |
|---|
| 507 | #define HDP_XDP_DBG_MASK__CTRL__SHIFT 0x00000010 |
|---|
| 508 | #define HDP_XDP_DBG_MASK__STS_MASK 0x0000ffffL |
|---|
| 509 | #define HDP_XDP_DBG_MASK__STS__SHIFT 0x00000000 |
|---|
| 510 | #define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xffffffffL |
|---|
| 511 | #define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x00000000 |
|---|
| 512 | #define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xffffffffL |
|---|
| 513 | #define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x00000000 |
|---|
| 514 | #define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xffffffffL |
|---|
| 515 | #define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x00000000 |
|---|
| 516 | #define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x03ffffffL |
|---|
| 517 | #define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x00000000 |
|---|
| 518 | #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x00001000L |
|---|
| 519 | #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0x0000000c |
|---|
| 520 | #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x00002000L |
|---|
| 521 | #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0x0000000d |
|---|
| 522 | #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x0000003fL |
|---|
| 523 | #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x00000000 |
|---|
| 524 | #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0x00000fc0L |
|---|
| 525 | #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x00000006 |
|---|
| 526 | #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x00000001L |
|---|
| 527 | #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT 0x00000000 |
|---|
| 528 | #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x00000006L |
|---|
| 529 | #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x00000001 |
|---|
| 530 | #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK 0x00000008L |
|---|
| 531 | #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT 0x00000003 |
|---|
| 532 | #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0x000000f0L |
|---|
| 533 | #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x00000004 |
|---|
| 534 | #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x00000001L |
|---|
| 535 | #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT 0x00000000 |
|---|
| 536 | #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK 0x00000006L |
|---|
| 537 | #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x00000001 |
|---|
| 538 | #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK 0x00000008L |
|---|
| 539 | #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT 0x00000003 |
|---|
| 540 | #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID_MASK 0x07800000L |
|---|
| 541 | #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID__SHIFT 0x00000017 |
|---|
| 542 | #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK 0x00700000L |
|---|
| 543 | #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT 0x00000014 |
|---|
| 544 | #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK 0x00000010L |
|---|
| 545 | #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT 0x00000004 |
|---|
| 546 | #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK 0x00000060L |
|---|
| 547 | #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT 0x00000005 |
|---|
| 548 | #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK 0x00000080L |
|---|
| 549 | #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT 0x00000007 |
|---|
| 550 | #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID_MASK 0x78000000L |
|---|
| 551 | #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID__SHIFT 0x0000001b |
|---|
| 552 | #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0x000fc000L |
|---|
| 553 | #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0x0000000e |
|---|
| 554 | #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK 0x00003f00L |
|---|
| 555 | #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT 0x00000008 |
|---|
| 556 | #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x00000001L |
|---|
| 557 | #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x00000000 |
|---|
| 558 | #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x00000006L |
|---|
| 559 | #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x00000001 |
|---|
| 560 | #define HDP_XDP_P2P_BAR0__ADDR_MASK 0x0000ffffL |
|---|
| 561 | #define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x00000000 |
|---|
| 562 | #define HDP_XDP_P2P_BAR0__FLUSH_MASK 0x000f0000L |
|---|
| 563 | #define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x00000010 |
|---|
| 564 | #define HDP_XDP_P2P_BAR0__VALID_MASK 0x00100000L |
|---|
| 565 | #define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x00000014 |
|---|
| 566 | #define HDP_XDP_P2P_BAR1__ADDR_MASK 0x0000ffffL |
|---|
| 567 | #define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x00000000 |
|---|
| 568 | #define HDP_XDP_P2P_BAR1__FLUSH_MASK 0x000f0000L |
|---|
| 569 | #define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x00000010 |
|---|
| 570 | #define HDP_XDP_P2P_BAR1__VALID_MASK 0x00100000L |
|---|
| 571 | #define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x00000014 |
|---|
| 572 | #define HDP_XDP_P2P_BAR2__ADDR_MASK 0x0000ffffL |
|---|
| 573 | #define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x00000000 |
|---|
| 574 | #define HDP_XDP_P2P_BAR2__FLUSH_MASK 0x000f0000L |
|---|
| 575 | #define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x00000010 |
|---|
| 576 | #define HDP_XDP_P2P_BAR2__VALID_MASK 0x00100000L |
|---|
| 577 | #define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x00000014 |
|---|
| 578 | #define HDP_XDP_P2P_BAR3__ADDR_MASK 0x0000ffffL |
|---|
| 579 | #define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x00000000 |
|---|
| 580 | #define HDP_XDP_P2P_BAR3__FLUSH_MASK 0x000f0000L |
|---|
| 581 | #define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x00000010 |
|---|
| 582 | #define HDP_XDP_P2P_BAR3__VALID_MASK 0x00100000L |
|---|
| 583 | #define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x00000014 |
|---|
| 584 | #define HDP_XDP_P2P_BAR4__ADDR_MASK 0x0000ffffL |
|---|
| 585 | #define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x00000000 |
|---|
| 586 | #define HDP_XDP_P2P_BAR4__FLUSH_MASK 0x000f0000L |
|---|
| 587 | #define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x00000010 |
|---|
| 588 | #define HDP_XDP_P2P_BAR4__VALID_MASK 0x00100000L |
|---|
| 589 | #define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x00000014 |
|---|
| 590 | #define HDP_XDP_P2P_BAR5__ADDR_MASK 0x0000ffffL |
|---|
| 591 | #define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x00000000 |
|---|
| 592 | #define HDP_XDP_P2P_BAR5__FLUSH_MASK 0x000f0000L |
|---|
| 593 | #define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x00000010 |
|---|
| 594 | #define HDP_XDP_P2P_BAR5__VALID_MASK 0x00100000L |
|---|
| 595 | #define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x00000014 |
|---|
| 596 | #define HDP_XDP_P2P_BAR6__ADDR_MASK 0x0000ffffL |
|---|
| 597 | #define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x00000000 |
|---|
| 598 | #define HDP_XDP_P2P_BAR6__FLUSH_MASK 0x000f0000L |
|---|
| 599 | #define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x00000010 |
|---|
| 600 | #define HDP_XDP_P2P_BAR6__VALID_MASK 0x00100000L |
|---|
| 601 | #define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x00000014 |
|---|
| 602 | #define HDP_XDP_P2P_BAR7__ADDR_MASK 0x0000ffffL |
|---|
| 603 | #define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x00000000 |
|---|
| 604 | #define HDP_XDP_P2P_BAR7__FLUSH_MASK 0x000f0000L |
|---|
| 605 | #define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x00000010 |
|---|
| 606 | #define HDP_XDP_P2P_BAR7__VALID_MASK 0x00100000L |
|---|
| 607 | #define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x00000014 |
|---|
| 608 | #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0x0000000fL |
|---|
| 609 | #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x00000000 |
|---|
| 610 | #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x00000030L |
|---|
| 611 | #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x00000004 |
|---|
| 612 | #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x01e00000L |
|---|
| 613 | #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x00000015 |
|---|
| 614 | #define HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK 0x001ffffeL |
|---|
| 615 | #define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x00000001 |
|---|
| 616 | #define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x00000001L |
|---|
| 617 | #define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x00000000 |
|---|
| 618 | #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x01e00000L |
|---|
| 619 | #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x00000015 |
|---|
| 620 | #define HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK 0x001ffffeL |
|---|
| 621 | #define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x00000001 |
|---|
| 622 | #define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x00000001L |
|---|
| 623 | #define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x00000000 |
|---|
| 624 | #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x01e00000L |
|---|
| 625 | #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x00000015 |
|---|
| 626 | #define HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK 0x001ffffeL |
|---|
| 627 | #define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x00000001 |
|---|
| 628 | #define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x00000001L |
|---|
| 629 | #define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x00000000 |
|---|
| 630 | #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x01e00000L |
|---|
| 631 | #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x00000015 |
|---|
| 632 | #define HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK 0x001ffffeL |
|---|
| 633 | #define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x00000001 |
|---|
| 634 | #define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x00000001L |
|---|
| 635 | #define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x00000000 |
|---|
| 636 | #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x01e00000L |
|---|
| 637 | #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x00000015 |
|---|
| 638 | #define HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK 0x001ffffeL |
|---|
| 639 | #define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x00000001 |
|---|
| 640 | #define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x00000001L |
|---|
| 641 | #define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x00000000 |
|---|
| 642 | #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x01e00000L |
|---|
| 643 | #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x00000015 |
|---|
| 644 | #define HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK 0x001ffffeL |
|---|
| 645 | #define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x00000001 |
|---|
| 646 | #define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x00000001L |
|---|
| 647 | #define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x00000000 |
|---|
| 648 | #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x01e00000L |
|---|
| 649 | #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x00000015 |
|---|
| 650 | #define HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK 0x001ffffeL |
|---|
| 651 | #define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x00000001 |
|---|
| 652 | #define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x00000001L |
|---|
| 653 | #define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x00000000 |
|---|
| 654 | #define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x00003fffL |
|---|
| 655 | #define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x00000000 |
|---|
| 656 | #define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK 0x00000018L |
|---|
| 657 | #define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT 0x00000003 |
|---|
| 658 | #define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x00000001L |
|---|
| 659 | #define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT 0x00000000 |
|---|
| 660 | #define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK 0x00000006L |
|---|
| 661 | #define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x00000001 |
|---|
| 662 | #define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK 0x0000003fL |
|---|
| 663 | #define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT 0x00000000 |
|---|
| 664 | #define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK 0x00000040L |
|---|
| 665 | #define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT 0x00000006 |
|---|
| 666 | #define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK 0x00000080L |
|---|
| 667 | #define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT 0x00000007 |
|---|
| 668 | #define HDP_XDP_STICKY__STICKY_STS_MASK 0x0000ffffL |
|---|
| 669 | #define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x00000000 |
|---|
| 670 | #define HDP_XDP_STICKY__STICKY_W1C_MASK 0xffff0000L |
|---|
| 671 | #define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x00000010 |
|---|
| 672 | #define HFS_SEED0__RESERVED_MASK 0xffffffffL |
|---|
| 673 | #define HFS_SEED0__RESERVED__SHIFT 0x00000000 |
|---|
| 674 | #define HFS_SEED1__RESERVED_MASK 0xffffffffL |
|---|
| 675 | #define HFS_SEED1__RESERVED__SHIFT 0x00000000 |
|---|
| 676 | #define HFS_SEED2__RESERVED_MASK 0xffffffffL |
|---|
| 677 | #define HFS_SEED2__RESERVED__SHIFT 0x00000000 |
|---|
| 678 | #define HFS_SEED3__RESERVED_MASK 0xffffffffL |
|---|
| 679 | #define HFS_SEED3__RESERVED__SHIFT 0x00000000 |
|---|
| 680 | #define IH_ADVFAULT_CNTL__NUM_FAULTS_DROPPED_MASK 0x0000ff00L |
|---|
| 681 | #define IH_ADVFAULT_CNTL__NUM_FAULTS_DROPPED__SHIFT 0x00000008 |
|---|
| 682 | #define IH_ADVFAULT_CNTL__WAIT_TIMER_MASK 0x3fff0000L |
|---|
| 683 | #define IH_ADVFAULT_CNTL__WAIT_TIMER__SHIFT 0x00000010 |
|---|
| 684 | #define IH_ADVFAULT_CNTL__WATERMARK_ENABLE_MASK 0x00000008L |
|---|
| 685 | #define IH_ADVFAULT_CNTL__WATERMARK_ENABLE__SHIFT 0x00000003 |
|---|
| 686 | #define IH_ADVFAULT_CNTL__WATERMARK_MASK 0x00000007L |
|---|
| 687 | #define IH_ADVFAULT_CNTL__WATERMARK_REACHED_MASK 0x00000010L |
|---|
| 688 | #define IH_ADVFAULT_CNTL__WATERMARK_REACHED__SHIFT 0x00000004 |
|---|
| 689 | #define IH_ADVFAULT_CNTL__WATERMARK__SHIFT 0x00000000 |
|---|
| 690 | #define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x00000300L |
|---|
| 691 | #define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x00000008 |
|---|
| 692 | #define IH_CNTL__ENABLE_INTR_MASK 0x00000001L |
|---|
| 693 | #define IH_CNTL__ENABLE_INTR__SHIFT 0x00000000 |
|---|
| 694 | #define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x00007c00L |
|---|
| 695 | #define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0x0000000a |
|---|
| 696 | #define IH_CNTL__MC_SWAP_MASK 0x00000006L |
|---|
| 697 | #define IH_CNTL__MC_SWAP__SHIFT 0x00000001 |
|---|
| 698 | #define IH_CNTL__MC_TRAN_MASK 0x00000008L |
|---|
| 699 | #define IH_CNTL__MC_TRAN__SHIFT 0x00000003 |
|---|
| 700 | #define IH_CNTL__MC_VMID_MASK 0x1e000000L |
|---|
| 701 | #define IH_CNTL__MC_VMID__SHIFT 0x00000019 |
|---|
| 702 | #define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x01f00000L |
|---|
| 703 | #define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x00000014 |
|---|
| 704 | #define IH_CNTL__MC_WRREQ_CREDIT_MASK 0x000f8000L |
|---|
| 705 | #define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x0000000f |
|---|
| 706 | #define IH_CNTL__RPTR_REARM_MASK 0x00000010L |
|---|
| 707 | #define IH_CNTL__RPTR_REARM__SHIFT 0x00000004 |
|---|
| 708 | #define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x00000010L |
|---|
| 709 | #define IH_LEVEL_STATUS__BIF_STATUS__SHIFT 0x00000004 |
|---|
| 710 | #define IH_LEVEL_STATUS__DC_STATUS_MASK 0x00000001L |
|---|
| 711 | #define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x00000000 |
|---|
| 712 | #define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x00000004L |
|---|
| 713 | #define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x00000002 |
|---|
| 714 | #define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x00000008L |
|---|
| 715 | #define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x00000003 |
|---|
| 716 | #define IH_LEVEL_STATUS__XDMA_STATUS_MASK 0x00000020L |
|---|
| 717 | #define IH_LEVEL_STATUS__XDMA_STATUS__SHIFT 0x00000005 |
|---|
| 718 | #define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffffL |
|---|
| 719 | #define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x00000000 |
|---|
| 720 | #define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffffL |
|---|
| 721 | #define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x00000000 |
|---|
| 722 | #define IH_PERFMON_CNTL__CLEAR0_MASK 0x00000002L |
|---|
| 723 | #define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x00000001 |
|---|
| 724 | #define IH_PERFMON_CNTL__CLEAR1_MASK 0x00000200L |
|---|
| 725 | #define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x00000009 |
|---|
| 726 | #define IH_PERFMON_CNTL__ENABLE0_MASK 0x00000001L |
|---|
| 727 | #define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x00000000 |
|---|
| 728 | #define IH_PERFMON_CNTL__ENABLE1_MASK 0x00000100L |
|---|
| 729 | #define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x00000008 |
|---|
| 730 | #define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x000000fcL |
|---|
| 731 | #define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x00000002 |
|---|
| 732 | #define IH_PERFMON_CNTL__PERF_SEL1_MASK 0x0000fc00L |
|---|
| 733 | #define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0x0000000a |
|---|
| 734 | #define IH_RB_BASE__ADDR_MASK 0xffffffffL |
|---|
| 735 | #define IH_RB_BASE__ADDR__SHIFT 0x00000000 |
|---|
| 736 | #define IH_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
|---|
| 737 | #define IH_RB_CNTL__RB_ENABLE__SHIFT 0x00000000 |
|---|
| 738 | #define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x00000040L |
|---|
| 739 | #define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x00000006 |
|---|
| 740 | #define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x00000080L |
|---|
| 741 | #define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x00000007 |
|---|
| 742 | #define IH_RB_CNTL__RB_SIZE_MASK 0x0000003eL |
|---|
| 743 | #define IH_RB_CNTL__RB_SIZE__SHIFT 0x00000001 |
|---|
| 744 | #define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L |
|---|
| 745 | #define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x0000001f |
|---|
| 746 | #define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L |
|---|
| 747 | #define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x00000010 |
|---|
| 748 | #define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L |
|---|
| 749 | #define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x00000008 |
|---|
| 750 | #define IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003e00L |
|---|
| 751 | #define IH_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x00000009 |
|---|
| 752 | #define IH_RB_RPTR__OFFSET_MASK 0x0003fffcL |
|---|
| 753 | #define IH_RB_RPTR__OFFSET__SHIFT 0x00000002 |
|---|
| 754 | #define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000ffL |
|---|
| 755 | #define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x00000000 |
|---|
| 756 | #define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffcL |
|---|
| 757 | #define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x00000002 |
|---|
| 758 | #define IH_RB_WPTR__OFFSET_MASK 0x0003fffcL |
|---|
| 759 | #define IH_RB_WPTR__OFFSET__SHIFT 0x00000002 |
|---|
| 760 | #define IH_RB_WPTR__RB_OVERFLOW_MASK 0x00000001L |
|---|
| 761 | #define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x00000000 |
|---|
| 762 | #define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x00000400L |
|---|
| 763 | #define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0x0000000a |
|---|
| 764 | #define IH_STATUS__IDLE_MASK 0x00000001L |
|---|
| 765 | #define IH_STATUS__IDLE__SHIFT 0x00000000 |
|---|
| 766 | #define IH_STATUS__INPUT_IDLE_MASK 0x00000002L |
|---|
| 767 | #define IH_STATUS__INPUT_IDLE__SHIFT 0x00000001 |
|---|
| 768 | #define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x00000100L |
|---|
| 769 | #define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x00000008 |
|---|
| 770 | #define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x00000200L |
|---|
| 771 | #define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x00000009 |
|---|
| 772 | #define IH_STATUS__MC_WR_IDLE_MASK 0x00000040L |
|---|
| 773 | #define IH_STATUS__MC_WR_IDLE__SHIFT 0x00000006 |
|---|
| 774 | #define IH_STATUS__MC_WR_STALL_MASK 0x00000080L |
|---|
| 775 | #define IH_STATUS__MC_WR_STALL__SHIFT 0x00000007 |
|---|
| 776 | #define IH_STATUS__RB_FULL_DRAIN_MASK 0x00000010L |
|---|
| 777 | #define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x00000004 |
|---|
| 778 | #define IH_STATUS__RB_FULL_MASK 0x00000008L |
|---|
| 779 | #define IH_STATUS__RB_FULL__SHIFT 0x00000003 |
|---|
| 780 | #define IH_STATUS__RB_IDLE_MASK 0x00000004L |
|---|
| 781 | #define IH_STATUS__RB_IDLE__SHIFT 0x00000002 |
|---|
| 782 | #define IH_STATUS__RB_OVERFLOW_MASK 0x00000020L |
|---|
| 783 | #define IH_STATUS__RB_OVERFLOW__SHIFT 0x00000005 |
|---|
| 784 | #define KEFUSE0__RESERVED_MASK 0xffffffffL |
|---|
| 785 | #define KEFUSE0__RESERVED__SHIFT 0x00000000 |
|---|
| 786 | #define KEFUSE1__RESERVED_MASK 0xffffffffL |
|---|
| 787 | #define KEFUSE1__RESERVED__SHIFT 0x00000000 |
|---|
| 788 | #define KEFUSE2__RESERVED_MASK 0xffffffffL |
|---|
| 789 | #define KEFUSE2__RESERVED__SHIFT 0x00000000 |
|---|
| 790 | #define KEFUSE3__RESERVED_MASK 0xffffffffL |
|---|
| 791 | #define KEFUSE3__RESERVED__SHIFT 0x00000000 |
|---|
| 792 | #define KHFS0__RESERVED_MASK 0xffffffffL |
|---|
| 793 | #define KHFS0__RESERVED__SHIFT 0x00000000 |
|---|
| 794 | #define KHFS1__RESERVED_MASK 0xffffffffL |
|---|
| 795 | #define KHFS1__RESERVED__SHIFT 0x00000000 |
|---|
| 796 | #define KHFS2__RESERVED_MASK 0xffffffffL |
|---|
| 797 | #define KHFS2__RESERVED__SHIFT 0x00000000 |
|---|
| 798 | #define KHFS3__RESERVED_MASK 0xffffffffL |
|---|
| 799 | #define KHFS3__RESERVED__SHIFT 0x00000000 |
|---|
| 800 | #define KSESSION0__RESERVED_MASK 0xffffffffL |
|---|
| 801 | #define KSESSION0__RESERVED__SHIFT 0x00000000 |
|---|
| 802 | #define KSESSION1__RESERVED_MASK 0xffffffffL |
|---|
| 803 | #define KSESSION1__RESERVED__SHIFT 0x00000000 |
|---|
| 804 | #define KSESSION2__RESERVED_MASK 0xffffffffL |
|---|
| 805 | #define KSESSION2__RESERVED__SHIFT 0x00000000 |
|---|
| 806 | #define KSESSION3__RESERVED_MASK 0xffffffffL |
|---|
| 807 | #define KSESSION3__RESERVED__SHIFT 0x00000000 |
|---|
| 808 | #define KSIG0__RESERVED_MASK 0xffffffffL |
|---|
| 809 | #define KSIG0__RESERVED__SHIFT 0x00000000 |
|---|
| 810 | #define KSIG1__RESERVED_MASK 0xffffffffL |
|---|
| 811 | #define KSIG1__RESERVED__SHIFT 0x00000000 |
|---|
| 812 | #define KSIG2__RESERVED_MASK 0xffffffffL |
|---|
| 813 | #define KSIG2__RESERVED__SHIFT 0x00000000 |
|---|
| 814 | #define KSIG3__RESERVED_MASK 0xffffffffL |
|---|
| 815 | #define KSIG3__RESERVED__SHIFT 0x00000000 |
|---|
| 816 | #define LX0__RESERVED_MASK 0xffffffffL |
|---|
| 817 | #define LX0__RESERVED__SHIFT 0x00000000 |
|---|
| 818 | #define LX1__RESERVED_MASK 0xffffffffL |
|---|
| 819 | #define LX1__RESERVED__SHIFT 0x00000000 |
|---|
| 820 | #define LX2__RESERVED_MASK 0xffffffffL |
|---|
| 821 | #define LX2__RESERVED__SHIFT 0x00000000 |
|---|
| 822 | #define LX3__RESERVED_MASK 0xffffffffL |
|---|
| 823 | #define LX3__RESERVED__SHIFT 0x00000000 |
|---|
| 824 | #define RINGOSC_MASK__MASK_MASK 0x0000ffffL |
|---|
| 825 | #define RINGOSC_MASK__MASK__SHIFT 0x00000000 |
|---|
| 826 | #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x00000007L |
|---|
| 827 | #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x00000000 |
|---|
| 828 | #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x00000038L |
|---|
| 829 | #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x00000003 |
|---|
| 830 | #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x000001c0L |
|---|
| 831 | #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x00000006 |
|---|
| 832 | #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0x00000e00L |
|---|
| 833 | #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x00000009 |
|---|
| 834 | #define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x00038000L |
|---|
| 835 | #define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0x0000000f |
|---|
| 836 | #define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0x00e00000L |
|---|
| 837 | #define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x00000015 |
|---|
| 838 | #define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0x0000ff00L |
|---|
| 839 | #define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x00000008 |
|---|
| 840 | #define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_MASK 0x000000ffL |
|---|
| 841 | #define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE__SHIFT 0x00000000 |
|---|
| 842 | #define SEM_MAILBOX__HOSTPORT_MASK 0x0000ff00L |
|---|
| 843 | #define SEM_MAILBOX__HOSTPORT__SHIFT 0x00000008 |
|---|
| 844 | #define SEM_MAILBOX__SIDEPORT_MASK 0x000000ffL |
|---|
| 845 | #define SEM_MAILBOX__SIDEPORT__SHIFT 0x00000000 |
|---|
| 846 | #define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x00000003L |
|---|
| 847 | #define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x00000000 |
|---|
| 848 | #define SPU_PORT_STATUS__RESERVED_MASK 0xffffffffL |
|---|
| 849 | #define SPU_PORT_STATUS__RESERVED__SHIFT 0x00000000 |
|---|
| 850 | #define SRBM_CAM_DATA__CAM_ADDR_MASK 0x0000ffffL |
|---|
| 851 | #define SRBM_CAM_DATA__CAM_ADDR__SHIFT 0x00000000 |
|---|
| 852 | #define SRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000L |
|---|
| 853 | #define SRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x00000010 |
|---|
| 854 | #define SRBM_CAM_INDEX__CAM_INDEX_MASK 0x00000007L |
|---|
| 855 | #define SRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x00000000 |
|---|
| 856 | #define SRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000ffL |
|---|
| 857 | #define SRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x00000000 |
|---|
| 858 | #define SRBM_CNTL__COMBINE_SYSTEM_MC_MASK 0x00020000L |
|---|
| 859 | #define SRBM_CNTL__COMBINE_SYSTEM_MC__SHIFT 0x00000011 |
|---|
| 860 | #define SRBM_CNTL__PWR_REQUEST_HALT_MASK 0x00010000L |
|---|
| 861 | #define SRBM_CNTL__PWR_REQUEST_HALT__SHIFT 0x00000010 |
|---|
| 862 | #define SRBM_CNTL__READ_TIMEOUT_MASK 0x000003ffL |
|---|
| 863 | #define SRBM_CNTL__READ_TIMEOUT__SHIFT 0x00000000 |
|---|
| 864 | #define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX_MASK 0x0000003fL |
|---|
| 865 | #define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX__SHIFT 0x00000000 |
|---|
| 866 | #define SRBM_DEBUG_DATA__DATA_MASK 0xffffffffL |
|---|
| 867 | #define SRBM_DEBUG_DATA__DATA__SHIFT 0x00000000 |
|---|
| 868 | #define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x00000002L |
|---|
| 869 | #define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x00000001 |
|---|
| 870 | #define SRBM_DEBUG__IGNORE_RDY_MASK 0x00000001L |
|---|
| 871 | #define SRBM_DEBUG__IGNORE_RDY__SHIFT 0x00000000 |
|---|
| 872 | #define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000100L |
|---|
| 873 | #define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000008 |
|---|
| 874 | #define SRBM_DEBUG_SNAPSHOT__BIF_RDY_MASK 0x00000080L |
|---|
| 875 | #define SRBM_DEBUG_SNAPSHOT__BIF_RDY__SHIFT 0x00000007 |
|---|
| 876 | #define SRBM_DEBUG_SNAPSHOT__DC_RDY_MASK 0x00000040L |
|---|
| 877 | #define SRBM_DEBUG_SNAPSHOT__DC_RDY__SHIFT 0x00000006 |
|---|
| 878 | #define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x00000004L |
|---|
| 879 | #define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x00000002 |
|---|
| 880 | #define SRBM_DEBUG_SNAPSHOT__GRBM_RDY_MASK 0x00000020L |
|---|
| 881 | #define SRBM_DEBUG_SNAPSHOT__GRBM_RDY__SHIFT 0x00000005 |
|---|
| 882 | #define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x00000001L |
|---|
| 883 | #define SRBM_DEBUG_SNAPSHOT__MCB_RDY__SHIFT 0x00000000 |
|---|
| 884 | #define SRBM_DEBUG_SNAPSHOT__MCC0_RDY_MASK 0x10000000L |
|---|
| 885 | #define SRBM_DEBUG_SNAPSHOT__MCC0_RDY__SHIFT 0x0000001c |
|---|
| 886 | #define SRBM_DEBUG_SNAPSHOT__MCC1_RDY_MASK 0x08000000L |
|---|
| 887 | #define SRBM_DEBUG_SNAPSHOT__MCC1_RDY__SHIFT 0x0000001b |
|---|
| 888 | #define SRBM_DEBUG_SNAPSHOT__MCC2_RDY_MASK 0x04000000L |
|---|
| 889 | #define SRBM_DEBUG_SNAPSHOT__MCC2_RDY__SHIFT 0x0000001a |
|---|
| 890 | #define SRBM_DEBUG_SNAPSHOT__MCC3_RDY_MASK 0x02000000L |
|---|
| 891 | #define SRBM_DEBUG_SNAPSHOT__MCC3_RDY__SHIFT 0x00000019 |
|---|
| 892 | #define SRBM_DEBUG_SNAPSHOT__MCC4_RDY_MASK 0x01000000L |
|---|
| 893 | #define SRBM_DEBUG_SNAPSHOT__MCC4_RDY__SHIFT 0x00000018 |
|---|
| 894 | #define SRBM_DEBUG_SNAPSHOT__MCC5_RDY_MASK 0x00800000L |
|---|
| 895 | #define SRBM_DEBUG_SNAPSHOT__MCC5_RDY__SHIFT 0x00000017 |
|---|
| 896 | #define SRBM_DEBUG_SNAPSHOT__MCC6_RDY_MASK 0x00400000L |
|---|
| 897 | #define SRBM_DEBUG_SNAPSHOT__MCC6_RDY__SHIFT 0x00000016 |
|---|
| 898 | #define SRBM_DEBUG_SNAPSHOT__MCC7_RDY_MASK 0x00200000L |
|---|
| 899 | #define SRBM_DEBUG_SNAPSHOT__MCC7_RDY__SHIFT 0x00000015 |
|---|
| 900 | #define SRBM_DEBUG_SNAPSHOT__MCD0_RDY_MASK 0x00100000L |
|---|
| 901 | #define SRBM_DEBUG_SNAPSHOT__MCD0_RDY__SHIFT 0x00000014 |
|---|
| 902 | #define SRBM_DEBUG_SNAPSHOT__MCD1_RDY_MASK 0x00080000L |
|---|
| 903 | #define SRBM_DEBUG_SNAPSHOT__MCD1_RDY__SHIFT 0x00000013 |
|---|
| 904 | #define SRBM_DEBUG_SNAPSHOT__MCD2_RDY_MASK 0x00040000L |
|---|
| 905 | #define SRBM_DEBUG_SNAPSHOT__MCD2_RDY__SHIFT 0x00000012 |
|---|
| 906 | #define SRBM_DEBUG_SNAPSHOT__MCD3_RDY_MASK 0x00020000L |
|---|
| 907 | #define SRBM_DEBUG_SNAPSHOT__MCD3_RDY__SHIFT 0x00000011 |
|---|
| 908 | #define SRBM_DEBUG_SNAPSHOT__MCD4_RDY_MASK 0x00010000L |
|---|
| 909 | #define SRBM_DEBUG_SNAPSHOT__MCD4_RDY__SHIFT 0x00000010 |
|---|
| 910 | #define SRBM_DEBUG_SNAPSHOT__MCD5_RDY_MASK 0x00008000L |
|---|
| 911 | #define SRBM_DEBUG_SNAPSHOT__MCD5_RDY__SHIFT 0x0000000f |
|---|
| 912 | #define SRBM_DEBUG_SNAPSHOT__MCD6_RDY_MASK 0x00004000L |
|---|
| 913 | #define SRBM_DEBUG_SNAPSHOT__MCD6_RDY__SHIFT 0x0000000e |
|---|
| 914 | #define SRBM_DEBUG_SNAPSHOT__MCD7_RDY_MASK 0x00002000L |
|---|
| 915 | #define SRBM_DEBUG_SNAPSHOT__MCD7_RDY__SHIFT 0x0000000d |
|---|
| 916 | #define SRBM_DEBUG_SNAPSHOT__ORB_RDY_MASK 0x00001000L |
|---|
| 917 | #define SRBM_DEBUG_SNAPSHOT__ORB_RDY__SHIFT 0x0000000c |
|---|
| 918 | #define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x00000800L |
|---|
| 919 | #define SRBM_DEBUG_SNAPSHOT__REGBB_RDY__SHIFT 0x0000000b |
|---|
| 920 | #define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x00000200L |
|---|
| 921 | #define SRBM_DEBUG_SNAPSHOT__UVD_RDY__SHIFT 0x00000009 |
|---|
| 922 | #define SRBM_DEBUG_SNAPSHOT__VCE_RDY_MASK 0x20000000L |
|---|
| 923 | #define SRBM_DEBUG_SNAPSHOT__VCE_RDY__SHIFT 0x0000001d |
|---|
| 924 | #define SRBM_DEBUG_SNAPSHOT__XDMA_RDY_MASK 0x00000100L |
|---|
| 925 | #define SRBM_DEBUG_SNAPSHOT__XDMA_RDY__SHIFT 0x00000008 |
|---|
| 926 | #define SRBM_DEBUG_SNAPSHOT__XSP_RDY_MASK 0x00000400L |
|---|
| 927 | #define SRBM_DEBUG_SNAPSHOT__XSP_RDY__SHIFT 0x0000000a |
|---|
| 928 | #define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000010L |
|---|
| 929 | #define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000004 |
|---|
| 930 | #define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000040L |
|---|
| 931 | #define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000006 |
|---|
| 932 | #define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000020L |
|---|
| 933 | #define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000005 |
|---|
| 934 | #define SRBM_GFX_CNTL__VMID_MASK 0x000000f0L |
|---|
| 935 | #define SRBM_GFX_CNTL__VMID__SHIFT 0x00000004 |
|---|
| 936 | #define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x00000001L |
|---|
| 937 | #define SRBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x00000000 |
|---|
| 938 | #define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x00000001L |
|---|
| 939 | #define SRBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x00000000 |
|---|
| 940 | #define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x00000001L |
|---|
| 941 | #define SRBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x00000000 |
|---|
| 942 | #define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L |
|---|
| 943 | #define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008 |
|---|
| 944 | #define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL |
|---|
| 945 | #define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000 |
|---|
| 946 | #define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI_MASK 0xffffffffL |
|---|
| 947 | #define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI__SHIFT 0x00000000 |
|---|
| 948 | #define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO_MASK 0xffffffffL |
|---|
| 949 | #define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO__SHIFT 0x00000000 |
|---|
| 950 | #define SRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003fL |
|---|
| 951 | #define SRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 |
|---|
| 952 | #define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0xffffffffL |
|---|
| 953 | #define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x00000000 |
|---|
| 954 | #define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffffL |
|---|
| 955 | #define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x00000000 |
|---|
| 956 | #define SRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003fL |
|---|
| 957 | #define SRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 |
|---|
| 958 | #define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L |
|---|
| 959 | #define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x00000008 |
|---|
| 960 | #define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L |
|---|
| 961 | #define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0x0000000a |
|---|
| 962 | #define SRBM_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000fL |
|---|
| 963 | #define SRBM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000 |
|---|
| 964 | #define SRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003fffcL |
|---|
| 965 | #define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x00000002 |
|---|
| 966 | #define SRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L |
|---|
| 967 | #define SRBM_READ_ERROR__READ_ERROR__SHIFT 0x0000001f |
|---|
| 968 | #define SRBM_READ_ERROR__READ_REQUESTER_GRBM_MASK 0x02000000L |
|---|
| 969 | #define SRBM_READ_ERROR__READ_REQUESTER_GRBM__SHIFT 0x00000019 |
|---|
| 970 | #define SRBM_READ_ERROR__READ_REQUESTER_HI_MASK 0x01000000L |
|---|
| 971 | #define SRBM_READ_ERROR__READ_REQUESTER_HI__SHIFT 0x00000018 |
|---|
| 972 | #define SRBM_READ_ERROR__READ_REQUESTER_SMU_MASK 0x04000000L |
|---|
| 973 | #define SRBM_READ_ERROR__READ_REQUESTER_SMU__SHIFT 0x0000001a |
|---|
| 974 | #define SRBM_READ_ERROR__READ_REQUESTER_TST_MASK 0x00400000L |
|---|
| 975 | #define SRBM_READ_ERROR__READ_REQUESTER_TST__SHIFT 0x00000016 |
|---|
| 976 | #define SRBM_READ_ERROR__READ_REQUESTER_UVD_MASK 0x20000000L |
|---|
| 977 | #define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x0000001d |
|---|
| 978 | #define SRBM_READ_ERROR__READ_REQUESTER_VCE_MASK 0x00100000L |
|---|
| 979 | #define SRBM_READ_ERROR__READ_REQUESTER_VCE__SHIFT 0x00000014 |
|---|
| 980 | #define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x00000002L |
|---|
| 981 | #define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x00000001 |
|---|
| 982 | #define SRBM_SOFT_RESET__SOFT_RESET_DC_MASK 0x00000020L |
|---|
| 983 | #define SRBM_SOFT_RESET__SOFT_RESET_DC__SHIFT 0x00000005 |
|---|
| 984 | #define SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK 0x00000100L |
|---|
| 985 | #define SRBM_SOFT_RESET__SOFT_RESET_GRBM__SHIFT 0x00000008 |
|---|
| 986 | #define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x00000200L |
|---|
| 987 | #define SRBM_SOFT_RESET__SOFT_RESET_HDP__SHIFT 0x00000009 |
|---|
| 988 | #define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x00000400L |
|---|
| 989 | #define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0x0000000a |
|---|
| 990 | #define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x00000800L |
|---|
| 991 | #define SRBM_SOFT_RESET__SOFT_RESET_MC__SHIFT 0x0000000b |
|---|
| 992 | #define SRBM_SOFT_RESET__SOFT_RESET_ORB_MASK 0x00800000L |
|---|
| 993 | #define SRBM_SOFT_RESET__SOFT_RESET_ORB__SHIFT 0x00000017 |
|---|
| 994 | #define SRBM_SOFT_RESET__SOFT_RESET_REGBB_MASK 0x00400000L |
|---|
| 995 | #define SRBM_SOFT_RESET__SOFT_RESET_REGBB__SHIFT 0x00000016 |
|---|
| 996 | #define SRBM_SOFT_RESET__SOFT_RESET_ROM_MASK 0x00004000L |
|---|
| 997 | #define SRBM_SOFT_RESET__SOFT_RESET_ROM__SHIFT 0x0000000e |
|---|
| 998 | #define SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK 0x00008000L |
|---|
| 999 | #define SRBM_SOFT_RESET__SOFT_RESET_SEM__SHIFT 0x0000000f |
|---|
| 1000 | #define SRBM_SOFT_RESET__SOFT_RESET_TST_MASK 0x00200000L |
|---|
| 1001 | #define SRBM_SOFT_RESET__SOFT_RESET_TST__SHIFT 0x00000015 |
|---|
| 1002 | #define SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK 0x00040000L |
|---|
| 1003 | #define SRBM_SOFT_RESET__SOFT_RESET_UVD__SHIFT 0x00000012 |
|---|
| 1004 | #define SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK 0x01000000L |
|---|
| 1005 | #define SRBM_SOFT_RESET__SOFT_RESET_VCE__SHIFT 0x00000018 |
|---|
| 1006 | #define SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK 0x00020000L |
|---|
| 1007 | #define SRBM_SOFT_RESET__SOFT_RESET_VMC__SHIFT 0x00000011 |
|---|
| 1008 | #define SRBM_SOFT_RESET__SOFT_RESET_XDMA_MASK 0x02000000L |
|---|
| 1009 | #define SRBM_SOFT_RESET__SOFT_RESET_XDMA__SHIFT 0x00000019 |
|---|
| 1010 | #define SRBM_SOFT_RESET__SOFT_RESET_XSP_MASK 0x00080000L |
|---|
| 1011 | #define SRBM_SOFT_RESET__SOFT_RESET_XSP__SHIFT 0x00000013 |
|---|
| 1012 | #define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x00000002L |
|---|
| 1013 | #define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x00000001 |
|---|
| 1014 | #define SRBM_STATUS2__VCE_BUSY_MASK 0x00000080L |
|---|
| 1015 | #define SRBM_STATUS2__VCE_BUSY__SHIFT 0x00000007 |
|---|
| 1016 | #define SRBM_STATUS2__VCE_RQ_PENDING_MASK 0x00000008L |
|---|
| 1017 | #define SRBM_STATUS2__VCE_RQ_PENDING__SHIFT 0x00000003 |
|---|
| 1018 | #define SRBM_STATUS2__XDMA_BUSY_MASK 0x00000100L |
|---|
| 1019 | #define SRBM_STATUS2__XDMA_BUSY__SHIFT 0x00000008 |
|---|
| 1020 | #define SRBM_STATUS2__XSP_BUSY_MASK 0x00000010L |
|---|
| 1021 | #define SRBM_STATUS2__XSP_BUSY__SHIFT 0x00000004 |
|---|
| 1022 | #define SRBM_STATUS__BIF_BUSY_MASK 0x20000000L |
|---|
| 1023 | #define SRBM_STATUS__BIF_BUSY__SHIFT 0x0000001d |
|---|
| 1024 | #define SRBM_STATUS__GRBM_RQ_PENDING_MASK 0x00000020L |
|---|
| 1025 | #define SRBM_STATUS__GRBM_RQ_PENDING__SHIFT 0x00000005 |
|---|
| 1026 | #define SRBM_STATUS__HI_RQ_PENDING_MASK 0x00000040L |
|---|
| 1027 | #define SRBM_STATUS__HI_RQ_PENDING__SHIFT 0x00000006 |
|---|
| 1028 | #define SRBM_STATUS__IH_BUSY_MASK 0x00020000L |
|---|
| 1029 | #define SRBM_STATUS__IH_BUSY__SHIFT 0x00000011 |
|---|
| 1030 | #define SRBM_STATUS__IO_EXTERN_SIGNAL_MASK 0x00000080L |
|---|
| 1031 | #define SRBM_STATUS__IO_EXTERN_SIGNAL__SHIFT 0x00000007 |
|---|
| 1032 | #define SRBM_STATUS__MCB_BUSY_MASK 0x00000200L |
|---|
| 1033 | #define SRBM_STATUS__MCB_BUSY__SHIFT 0x00000009 |
|---|
| 1034 | #define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x00000400L |
|---|
| 1035 | #define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0x0000000a |
|---|
| 1036 | #define SRBM_STATUS__MCC_BUSY_MASK 0x00000800L |
|---|
| 1037 | #define SRBM_STATUS__MCC_BUSY__SHIFT 0x0000000b |
|---|
| 1038 | #define SRBM_STATUS__MCD_BUSY_MASK 0x00001000L |
|---|
| 1039 | #define SRBM_STATUS__MCD_BUSY__SHIFT 0x0000000c |
|---|
| 1040 | #define SRBM_STATUS__SEM_BUSY_MASK 0x00004000L |
|---|
| 1041 | #define SRBM_STATUS__SEM_BUSY__SHIFT 0x0000000e |
|---|
| 1042 | #define SRBM_STATUS__SMU_RQ_PENDING_MASK 0x00000010L |
|---|
| 1043 | #define SRBM_STATUS__SMU_RQ_PENDING__SHIFT 0x00000004 |
|---|
| 1044 | #define SRBM_STATUS__UVD_BUSY_MASK 0x00080000L |
|---|
| 1045 | #define SRBM_STATUS__UVD_BUSY__SHIFT 0x00000013 |
|---|
| 1046 | #define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x00000002L |
|---|
| 1047 | #define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x00000001 |
|---|
| 1048 | #define SRBM_STATUS__VMC_BUSY_MASK 0x00000100L |
|---|
| 1049 | #define SRBM_STATUS__VMC_BUSY__SHIFT 0x00000008 |
|---|
| 1050 | #define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L |
|---|
| 1051 | #define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008 |
|---|
| 1052 | #define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL |
|---|
| 1053 | #define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000 |
|---|
| 1054 | #define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L |
|---|
| 1055 | #define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008 |
|---|
| 1056 | #define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL |
|---|
| 1057 | #define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000 |
|---|
| 1058 | #define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L |
|---|
| 1059 | #define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008 |
|---|
| 1060 | #define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL |
|---|
| 1061 | #define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000 |
|---|
| 1062 | #define UVD_CONFIG__UVD_RDREQ_URG_MASK 0x00000f00L |
|---|
| 1063 | #define UVD_CONFIG__UVD_RDREQ_URG__SHIFT 0x00000008 |
|---|
| 1064 | #define UVD_CONFIG__UVD_REQ_TRAN_MASK 0x00010000L |
|---|
| 1065 | #define UVD_CONFIG__UVD_REQ_TRAN__SHIFT 0x00000010 |
|---|
| 1066 | #define VCE_CONFIG__VCE_RDREQ_URG_MASK 0x00000f00L |
|---|
| 1067 | #define VCE_CONFIG__VCE_RDREQ_URG__SHIFT 0x00000008 |
|---|
| 1068 | #define VCE_CONFIG__VCE_REQ_TRAN_MASK 0x00010000L |
|---|
| 1069 | #define VCE_CONFIG__VCE_REQ_TRAN__SHIFT 0x00000010 |
|---|
| 1070 | #define XDMA_MSTR_CNTL__XDMA_MSTR_LAT_TEST_EN_MASK 0x00080000L |
|---|
| 1071 | #define XDMA_MSTR_CNTL__XDMA_MSTR_LAT_TEST_EN__SHIFT 0x00000013 |
|---|
| 1072 | #define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_ENABLE_MASK 0x80000000L |
|---|
| 1073 | #define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_ENABLE__SHIFT 0x0000001f |
|---|
| 1074 | #define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_MASK 0x0000ffffL |
|---|
| 1075 | #define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT__SHIFT 0x00000000 |
|---|
| 1076 | #define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_THRESHOLD_MASK 0x3fff0000L |
|---|
| 1077 | #define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_THRESHOLD__SHIFT 0x00000010 |
|---|
| 1078 | |
|---|
| 1079 | #endif |
|---|
| 1080 | |
|---|
