| 1 | /* |
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| 2 | * Copyright 2023 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | */ |
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| 23 | #ifndef _osssys_6_1_0_SH_MASK_HEADER |
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| 24 | #define |
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| 25 | |
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| 26 | |
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| 27 | // addressBlock: osssys_osssysdec |
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| 28 | //IH_VMID_0_LUT |
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| 29 | #define IH_VMID_0_LUT__PASID__SHIFT 0x0 |
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| 30 | #define IH_VMID_0_LUT__PASID_MASK 0x0000FFFFL |
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| 31 | //IH_VMID_1_LUT |
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| 32 | #define IH_VMID_1_LUT__PASID__SHIFT 0x0 |
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| 33 | #define IH_VMID_1_LUT__PASID_MASK 0x0000FFFFL |
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| 34 | //IH_VMID_2_LUT |
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| 35 | #define IH_VMID_2_LUT__PASID__SHIFT 0x0 |
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| 36 | #define IH_VMID_2_LUT__PASID_MASK 0x0000FFFFL |
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| 37 | //IH_VMID_3_LUT |
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| 38 | #define IH_VMID_3_LUT__PASID__SHIFT 0x0 |
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| 39 | #define IH_VMID_3_LUT__PASID_MASK 0x0000FFFFL |
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| 40 | //IH_VMID_4_LUT |
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| 41 | #define IH_VMID_4_LUT__PASID__SHIFT 0x0 |
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| 42 | #define IH_VMID_4_LUT__PASID_MASK 0x0000FFFFL |
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| 43 | //IH_VMID_5_LUT |
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| 44 | #define IH_VMID_5_LUT__PASID__SHIFT 0x0 |
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| 45 | #define IH_VMID_5_LUT__PASID_MASK 0x0000FFFFL |
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| 46 | //IH_VMID_6_LUT |
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| 47 | #define IH_VMID_6_LUT__PASID__SHIFT 0x0 |
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| 48 | #define IH_VMID_6_LUT__PASID_MASK 0x0000FFFFL |
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| 49 | //IH_VMID_7_LUT |
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| 50 | #define IH_VMID_7_LUT__PASID__SHIFT 0x0 |
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| 51 | #define IH_VMID_7_LUT__PASID_MASK 0x0000FFFFL |
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| 52 | //IH_VMID_8_LUT |
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| 53 | #define IH_VMID_8_LUT__PASID__SHIFT 0x0 |
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| 54 | #define IH_VMID_8_LUT__PASID_MASK 0x0000FFFFL |
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| 55 | //IH_VMID_9_LUT |
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| 56 | #define IH_VMID_9_LUT__PASID__SHIFT 0x0 |
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| 57 | #define IH_VMID_9_LUT__PASID_MASK 0x0000FFFFL |
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| 58 | //IH_VMID_10_LUT |
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| 59 | #define IH_VMID_10_LUT__PASID__SHIFT 0x0 |
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| 60 | #define IH_VMID_10_LUT__PASID_MASK 0x0000FFFFL |
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| 61 | //IH_VMID_11_LUT |
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| 62 | #define IH_VMID_11_LUT__PASID__SHIFT 0x0 |
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| 63 | #define IH_VMID_11_LUT__PASID_MASK 0x0000FFFFL |
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| 64 | //IH_VMID_12_LUT |
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| 65 | #define IH_VMID_12_LUT__PASID__SHIFT 0x0 |
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| 66 | #define IH_VMID_12_LUT__PASID_MASK 0x0000FFFFL |
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| 67 | //IH_VMID_13_LUT |
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| 68 | #define IH_VMID_13_LUT__PASID__SHIFT 0x0 |
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| 69 | #define IH_VMID_13_LUT__PASID_MASK 0x0000FFFFL |
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| 70 | //IH_VMID_14_LUT |
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| 71 | #define IH_VMID_14_LUT__PASID__SHIFT 0x0 |
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| 72 | #define IH_VMID_14_LUT__PASID_MASK 0x0000FFFFL |
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| 73 | //IH_VMID_15_LUT |
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| 74 | #define IH_VMID_15_LUT__PASID__SHIFT 0x0 |
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| 75 | #define IH_VMID_15_LUT__PASID_MASK 0x0000FFFFL |
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| 76 | //IH_VMID_0_LUT_MM |
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| 77 | #define IH_VMID_0_LUT_MM__PASID__SHIFT 0x0 |
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| 78 | #define IH_VMID_0_LUT_MM__PASID_MASK 0x0000FFFFL |
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| 79 | //IH_VMID_1_LUT_MM |
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| 80 | #define IH_VMID_1_LUT_MM__PASID__SHIFT 0x0 |
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| 81 | #define IH_VMID_1_LUT_MM__PASID_MASK 0x0000FFFFL |
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| 82 | //IH_VMID_2_LUT_MM |
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| 83 | #define IH_VMID_2_LUT_MM__PASID__SHIFT 0x0 |
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| 84 | #define IH_VMID_2_LUT_MM__PASID_MASK 0x0000FFFFL |
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| 85 | //IH_VMID_3_LUT_MM |
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| 86 | #define IH_VMID_3_LUT_MM__PASID__SHIFT 0x0 |
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| 87 | #define IH_VMID_3_LUT_MM__PASID_MASK 0x0000FFFFL |
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| 88 | //IH_VMID_4_LUT_MM |
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| 89 | #define IH_VMID_4_LUT_MM__PASID__SHIFT 0x0 |
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| 90 | #define IH_VMID_4_LUT_MM__PASID_MASK 0x0000FFFFL |
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| 91 | //IH_VMID_5_LUT_MM |
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| 92 | #define IH_VMID_5_LUT_MM__PASID__SHIFT 0x0 |
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| 93 | #define IH_VMID_5_LUT_MM__PASID_MASK 0x0000FFFFL |
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| 94 | //IH_VMID_6_LUT_MM |
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| 95 | #define IH_VMID_6_LUT_MM__PASID__SHIFT 0x0 |
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| 96 | #define IH_VMID_6_LUT_MM__PASID_MASK 0x0000FFFFL |
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| 97 | //IH_VMID_7_LUT_MM |
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| 98 | #define IH_VMID_7_LUT_MM__PASID__SHIFT 0x0 |
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| 99 | #define IH_VMID_7_LUT_MM__PASID_MASK 0x0000FFFFL |
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| 100 | //IH_VMID_8_LUT_MM |
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| 101 | #define IH_VMID_8_LUT_MM__PASID__SHIFT 0x0 |
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| 102 | #define IH_VMID_8_LUT_MM__PASID_MASK 0x0000FFFFL |
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| 103 | //IH_VMID_9_LUT_MM |
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| 104 | #define IH_VMID_9_LUT_MM__PASID__SHIFT 0x0 |
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| 105 | #define IH_VMID_9_LUT_MM__PASID_MASK 0x0000FFFFL |
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| 106 | //IH_VMID_10_LUT_MM |
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| 107 | #define IH_VMID_10_LUT_MM__PASID__SHIFT 0x0 |
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| 108 | #define IH_VMID_10_LUT_MM__PASID_MASK 0x0000FFFFL |
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| 109 | //IH_VMID_11_LUT_MM |
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| 110 | #define IH_VMID_11_LUT_MM__PASID__SHIFT 0x0 |
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| 111 | #define IH_VMID_11_LUT_MM__PASID_MASK 0x0000FFFFL |
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| 112 | //IH_VMID_12_LUT_MM |
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| 113 | #define IH_VMID_12_LUT_MM__PASID__SHIFT 0x0 |
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| 114 | #define IH_VMID_12_LUT_MM__PASID_MASK 0x0000FFFFL |
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| 115 | //IH_VMID_13_LUT_MM |
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| 116 | #define IH_VMID_13_LUT_MM__PASID__SHIFT 0x0 |
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| 117 | #define IH_VMID_13_LUT_MM__PASID_MASK 0x0000FFFFL |
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| 118 | //IH_VMID_14_LUT_MM |
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| 119 | #define IH_VMID_14_LUT_MM__PASID__SHIFT 0x0 |
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| 120 | #define IH_VMID_14_LUT_MM__PASID_MASK 0x0000FFFFL |
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| 121 | //IH_VMID_15_LUT_MM |
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| 122 | #define IH_VMID_15_LUT_MM__PASID__SHIFT 0x0 |
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| 123 | #define IH_VMID_15_LUT_MM__PASID_MASK 0x0000FFFFL |
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| 124 | //IH_COOKIE_0 |
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| 125 | #define IH_COOKIE_0__CLIENT_ID__SHIFT 0x0 |
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| 126 | #define IH_COOKIE_0__SOURCE_ID__SHIFT 0x8 |
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| 127 | #define IH_COOKIE_0__RING_ID__SHIFT 0x10 |
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| 128 | #define IH_COOKIE_0__VM_ID__SHIFT 0x18 |
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| 129 | #define IH_COOKIE_0__RESERVED__SHIFT 0x1c |
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| 130 | #define IH_COOKIE_0__VMID_TYPE__SHIFT 0x1f |
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| 131 | #define IH_COOKIE_0__CLIENT_ID_MASK 0x000000FFL |
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| 132 | #define IH_COOKIE_0__SOURCE_ID_MASK 0x0000FF00L |
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| 133 | #define IH_COOKIE_0__RING_ID_MASK 0x00FF0000L |
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| 134 | #define IH_COOKIE_0__VM_ID_MASK 0x0F000000L |
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| 135 | #define IH_COOKIE_0__RESERVED_MASK 0x70000000L |
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| 136 | #define IH_COOKIE_0__VMID_TYPE_MASK 0x80000000L |
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| 137 | //IH_COOKIE_1 |
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| 138 | #define IH_COOKIE_1__TIMESTAMP_31_0__SHIFT 0x0 |
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| 139 | #define IH_COOKIE_1__TIMESTAMP_31_0_MASK 0xFFFFFFFFL |
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| 140 | //IH_COOKIE_2 |
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| 141 | #define IH_COOKIE_2__TIMESTAMP_47_32__SHIFT 0x0 |
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| 142 | #define IH_COOKIE_2__RESERVED__SHIFT 0x10 |
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| 143 | #define IH_COOKIE_2__TIMESTAMP_SRC__SHIFT 0x1f |
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| 144 | #define IH_COOKIE_2__TIMESTAMP_47_32_MASK 0x0000FFFFL |
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| 145 | #define IH_COOKIE_2__RESERVED_MASK 0x7FFF0000L |
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| 146 | #define IH_COOKIE_2__TIMESTAMP_SRC_MASK 0x80000000L |
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| 147 | //IH_COOKIE_3 |
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| 148 | #define IH_COOKIE_3__PAS_ID__SHIFT 0x0 |
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| 149 | #define IH_COOKIE_3__RESERVED__SHIFT 0x10 |
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| 150 | #define IH_COOKIE_3__PASID_SRC__SHIFT 0x1f |
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| 151 | #define IH_COOKIE_3__PAS_ID_MASK 0x0000FFFFL |
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| 152 | #define IH_COOKIE_3__RESERVED_MASK 0x7FFF0000L |
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| 153 | #define IH_COOKIE_3__PASID_SRC_MASK 0x80000000L |
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| 154 | //IH_COOKIE_4 |
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| 155 | #define IH_COOKIE_4__CONTEXT_ID_31_0__SHIFT 0x0 |
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| 156 | #define IH_COOKIE_4__CONTEXT_ID_31_0_MASK 0xFFFFFFFFL |
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| 157 | //IH_COOKIE_5 |
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| 158 | #define IH_COOKIE_5__CONTEXT_ID_63_32__SHIFT 0x0 |
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| 159 | #define IH_COOKIE_5__CONTEXT_ID_63_32_MASK 0xFFFFFFFFL |
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| 160 | //IH_COOKIE_6 |
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| 161 | #define IH_COOKIE_6__CONTEXT_ID_95_64__SHIFT 0x0 |
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| 162 | #define IH_COOKIE_6__CONTEXT_ID_95_64_MASK 0xFFFFFFFFL |
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| 163 | //IH_COOKIE_7 |
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| 164 | #define IH_COOKIE_7__CONTEXT_ID_128_96__SHIFT 0x0 |
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| 165 | #define IH_COOKIE_7__CONTEXT_ID_128_96_MASK 0xFFFFFFFFL |
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| 166 | //IH_REGISTER_LAST_PART0 |
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| 167 | #define IH_REGISTER_LAST_PART0__RESERVED__SHIFT 0x0 |
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| 168 | #define IH_REGISTER_LAST_PART0__RESERVED_MASK 0xFFFFFFFFL |
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| 169 | //IH_RB_CNTL |
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| 170 | #define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
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| 171 | #define IH_RB_CNTL__RB_SIZE__SHIFT 0x1 |
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| 172 | #define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 |
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| 173 | #define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x9 |
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| 174 | #define IH_RB_CNTL__FULL_DRAIN_CLEAR__SHIFT 0xa |
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| 175 | #define IH_RB_CNTL__PAGE_RB_CLEAR__SHIFT 0xb |
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| 176 | #define IH_RB_CNTL__RB_USED_INT_THRESHOLD__SHIFT 0xc |
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| 177 | #define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 |
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| 178 | #define IH_RB_CNTL__ENABLE_INTR__SHIFT 0x11 |
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| 179 | #define IH_RB_CNTL__MC_SWAP__SHIFT 0x12 |
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| 180 | #define IH_RB_CNTL__MC_SNOOP__SHIFT 0x14 |
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| 181 | #define IH_RB_CNTL__RPTR_REARM__SHIFT 0x15 |
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| 182 | #define IH_RB_CNTL__MC_RO__SHIFT 0x16 |
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| 183 | #define IH_RB_CNTL__MC_VMID__SHIFT 0x18 |
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| 184 | #define IH_RB_CNTL__MC_SPACE__SHIFT 0x1c |
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| 185 | #define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f |
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| 186 | #define IH_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
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| 187 | #define IH_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
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| 188 | #define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L |
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| 189 | #define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L |
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| 190 | #define IH_RB_CNTL__FULL_DRAIN_CLEAR_MASK 0x00000400L |
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| 191 | #define IH_RB_CNTL__PAGE_RB_CLEAR_MASK 0x00000800L |
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| 192 | #define IH_RB_CNTL__RB_USED_INT_THRESHOLD_MASK 0x0000F000L |
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| 193 | #define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L |
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| 194 | #define IH_RB_CNTL__ENABLE_INTR_MASK 0x00020000L |
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| 195 | #define IH_RB_CNTL__MC_SWAP_MASK 0x000C0000L |
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| 196 | #define IH_RB_CNTL__MC_SNOOP_MASK 0x00100000L |
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| 197 | #define IH_RB_CNTL__RPTR_REARM_MASK 0x00200000L |
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| 198 | #define IH_RB_CNTL__MC_RO_MASK 0x00400000L |
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| 199 | #define IH_RB_CNTL__MC_VMID_MASK 0x0F000000L |
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| 200 | #define IH_RB_CNTL__MC_SPACE_MASK 0x70000000L |
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| 201 | #define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L |
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| 202 | //IH_RB_RPTR |
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| 203 | #define IH_RB_RPTR__OFFSET__SHIFT 0x2 |
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| 204 | #define IH_RB_RPTR__OFFSET_MASK 0x0003FFFCL |
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| 205 | //IH_RB_WPTR |
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| 206 | #define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0 |
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| 207 | #define IH_RB_WPTR__OFFSET__SHIFT 0x2 |
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| 208 | #define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12 |
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| 209 | #define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13 |
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| 210 | #define IH_RB_WPTR__RB_OVERFLOW_MASK 0x00000001L |
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| 211 | #define IH_RB_WPTR__OFFSET_MASK 0x0003FFFCL |
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| 212 | #define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x00040000L |
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| 213 | #define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x00080000L |
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| 214 | //IH_RB_BASE |
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| 215 | #define IH_RB_BASE__ADDR__SHIFT 0x0 |
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| 216 | #define IH_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
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| 217 | //IH_RB_BASE_HI |
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| 218 | #define IH_RB_BASE_HI__ADDR__SHIFT 0x0 |
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| 219 | #define IH_RB_BASE_HI__ADDR_MASK 0x000000FFL |
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| 220 | //IH_RB_WPTR_ADDR_HI |
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| 221 | #define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 |
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| 222 | #define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0x0000FFFFL |
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| 223 | //IH_RB_WPTR_ADDR_LO |
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| 224 | #define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 |
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| 225 | #define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
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| 226 | //IH_DOORBELL_RPTR |
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| 227 | #define IH_DOORBELL_RPTR__OFFSET__SHIFT 0x0 |
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| 228 | #define IH_DOORBELL_RPTR__ENABLE__SHIFT 0x1c |
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| 229 | #define IH_DOORBELL_RPTR__OFFSET_MASK 0x03FFFFFFL |
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| 230 | #define IH_DOORBELL_RPTR__ENABLE_MASK 0x10000000L |
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| 231 | //IH_DOORBELL_RETRY_CAM |
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| 232 | #define IH_DOORBELL_RETRY_CAM__OFFSET__SHIFT 0x0 |
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| 233 | #define IH_DOORBELL_RETRY_CAM__ENABLE__SHIFT 0x1c |
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| 234 | #define IH_DOORBELL_RETRY_CAM__OFFSET_MASK 0x03FFFFFFL |
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| 235 | #define IH_DOORBELL_RETRY_CAM__ENABLE_MASK 0x10000000L |
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| 236 | //IH_RB_CNTL_RING1 |
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| 237 | #define IH_RB_CNTL_RING1__RB_ENABLE__SHIFT 0x0 |
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| 238 | #define IH_RB_CNTL_RING1__RB_SIZE__SHIFT 0x1 |
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| 239 | #define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE__SHIFT 0x9 |
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| 240 | #define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR__SHIFT 0xa |
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| 241 | #define IH_RB_CNTL_RING1__PAGE_RB_CLEAR__SHIFT 0xb |
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| 242 | #define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD__SHIFT 0xc |
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| 243 | #define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 |
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| 244 | #define IH_RB_CNTL_RING1__MC_SWAP__SHIFT 0x12 |
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| 245 | #define IH_RB_CNTL_RING1__MC_SNOOP__SHIFT 0x14 |
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| 246 | #define IH_RB_CNTL_RING1__MC_RO__SHIFT 0x16 |
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| 247 | #define IH_RB_CNTL_RING1__MC_VMID__SHIFT 0x18 |
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| 248 | #define IH_RB_CNTL_RING1__MC_SPACE__SHIFT 0x1c |
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| 249 | #define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f |
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| 250 | #define IH_RB_CNTL_RING1__RB_ENABLE_MASK 0x00000001L |
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| 251 | #define IH_RB_CNTL_RING1__RB_SIZE_MASK 0x0000003EL |
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| 252 | #define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L |
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| 253 | #define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR_MASK 0x00000400L |
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| 254 | #define IH_RB_CNTL_RING1__PAGE_RB_CLEAR_MASK 0x00000800L |
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| 255 | #define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD_MASK 0x0000F000L |
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| 256 | #define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L |
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| 257 | #define IH_RB_CNTL_RING1__MC_SWAP_MASK 0x000C0000L |
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| 258 | #define IH_RB_CNTL_RING1__MC_SNOOP_MASK 0x00100000L |
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| 259 | #define IH_RB_CNTL_RING1__MC_RO_MASK 0x00400000L |
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| 260 | #define IH_RB_CNTL_RING1__MC_VMID_MASK 0x0F000000L |
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| 261 | #define IH_RB_CNTL_RING1__MC_SPACE_MASK 0x70000000L |
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| 262 | #define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L |
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| 263 | //IH_RB_RPTR_RING1 |
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| 264 | #define IH_RB_RPTR_RING1__OFFSET__SHIFT 0x2 |
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| 265 | #define IH_RB_RPTR_RING1__OFFSET_MASK 0x0003FFFCL |
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| 266 | //IH_RB_WPTR_RING1 |
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| 267 | #define IH_RB_WPTR_RING1__RB_OVERFLOW__SHIFT 0x0 |
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| 268 | #define IH_RB_WPTR_RING1__OFFSET__SHIFT 0x2 |
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| 269 | #define IH_RB_WPTR_RING1__RB_LEFT_NONE__SHIFT 0x12 |
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| 270 | #define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW__SHIFT 0x13 |
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| 271 | #define IH_RB_WPTR_RING1__RB_OVERFLOW_MASK 0x00000001L |
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| 272 | #define IH_RB_WPTR_RING1__OFFSET_MASK 0x0003FFFCL |
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| 273 | #define IH_RB_WPTR_RING1__RB_LEFT_NONE_MASK 0x00040000L |
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| 274 | #define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW_MASK 0x00080000L |
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| 275 | //IH_RB_BASE_RING1 |
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| 276 | #define IH_RB_BASE_RING1__ADDR__SHIFT 0x0 |
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| 277 | #define IH_RB_BASE_RING1__ADDR_MASK 0xFFFFFFFFL |
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| 278 | //IH_RB_BASE_HI_RING1 |
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| 279 | #define IH_RB_BASE_HI_RING1__ADDR__SHIFT 0x0 |
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| 280 | #define IH_RB_BASE_HI_RING1__ADDR_MASK 0x000000FFL |
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| 281 | //IH_DOORBELL_RPTR_RING1 |
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| 282 | #define IH_DOORBELL_RPTR_RING1__OFFSET__SHIFT 0x0 |
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| 283 | #define IH_DOORBELL_RPTR_RING1__ENABLE__SHIFT 0x1c |
|---|
| 284 | #define IH_DOORBELL_RPTR_RING1__OFFSET_MASK 0x03FFFFFFL |
|---|
| 285 | #define IH_DOORBELL_RPTR_RING1__ENABLE_MASK 0x10000000L |
|---|
| 286 | //IH_RETRY_CAM_ACK |
|---|
| 287 | #define IH_RETRY_CAM_ACK__INDEX__SHIFT 0x0 |
|---|
| 288 | #define IH_RETRY_CAM_ACK__INDEX_MASK 0x000003FFL |
|---|
| 289 | //IH_VERSION |
|---|
| 290 | #define IH_VERSION__MINVER__SHIFT 0x0 |
|---|
| 291 | #define IH_VERSION__MAJVER__SHIFT 0x8 |
|---|
| 292 | #define IH_VERSION__REV__SHIFT 0x10 |
|---|
| 293 | #define IH_VERSION__MINVER_MASK 0x0000007FL |
|---|
| 294 | #define IH_VERSION__MAJVER_MASK 0x00007F00L |
|---|
| 295 | #define IH_VERSION__REV_MASK 0x003F0000L |
|---|
| 296 | //IH_CNTL |
|---|
| 297 | #define IH_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x0 |
|---|
| 298 | #define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL__SHIFT 0x6 |
|---|
| 299 | #define IH_CNTL__IH_FIFO_HIGHWATER__SHIFT 0x8 |
|---|
| 300 | #define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14 |
|---|
| 301 | #define IH_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x0000001FL |
|---|
| 302 | #define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL_MASK 0x000000C0L |
|---|
| 303 | #define IH_CNTL__IH_FIFO_HIGHWATER_MASK 0x00007F00L |
|---|
| 304 | #define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x01F00000L |
|---|
| 305 | //IH_CLK_CTRL |
|---|
| 306 | #define IH_CLK_CTRL__IH_PASID_LUT_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x17 |
|---|
| 307 | #define IH_CLK_CTRL__MSI_STORM_COUNTER_CLK_SOFT_OVERRIDE__SHIFT 0x18 |
|---|
| 308 | #define IH_CLK_CTRL__IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x19 |
|---|
| 309 | #define IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1a |
|---|
| 310 | #define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE__SHIFT 0x1b |
|---|
| 311 | #define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE__SHIFT 0x1c |
|---|
| 312 | #define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE__SHIFT 0x1d |
|---|
| 313 | #define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1e |
|---|
| 314 | #define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f |
|---|
| 315 | #define IH_CLK_CTRL__IH_PASID_LUT_MEM_CLK_SOFT_OVERRIDE_MASK 0x00800000L |
|---|
| 316 | #define IH_CLK_CTRL__MSI_STORM_COUNTER_CLK_SOFT_OVERRIDE_MASK 0x01000000L |
|---|
| 317 | #define IH_CLK_CTRL__IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE_MASK 0x02000000L |
|---|
| 318 | #define IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE_MASK 0x04000000L |
|---|
| 319 | #define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE_MASK 0x08000000L |
|---|
| 320 | #define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE_MASK 0x10000000L |
|---|
| 321 | #define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE_MASK 0x20000000L |
|---|
| 322 | #define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE_MASK 0x40000000L |
|---|
| 323 | #define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L |
|---|
| 324 | //IH_STORM_CLIENT_LIST_CNTL |
|---|
| 325 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT__SHIFT 0x1 |
|---|
| 326 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT__SHIFT 0x2 |
|---|
| 327 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT__SHIFT 0x3 |
|---|
| 328 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT__SHIFT 0x4 |
|---|
| 329 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT__SHIFT 0x5 |
|---|
| 330 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT__SHIFT 0x6 |
|---|
| 331 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT__SHIFT 0x7 |
|---|
| 332 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT__SHIFT 0x8 |
|---|
| 333 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT__SHIFT 0x9 |
|---|
| 334 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT__SHIFT 0xa |
|---|
| 335 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT__SHIFT 0xb |
|---|
| 336 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT__SHIFT 0xc |
|---|
| 337 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT__SHIFT 0xd |
|---|
| 338 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT__SHIFT 0xe |
|---|
| 339 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT__SHIFT 0xf |
|---|
| 340 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT__SHIFT 0x10 |
|---|
| 341 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT__SHIFT 0x11 |
|---|
| 342 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT__SHIFT 0x12 |
|---|
| 343 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT__SHIFT 0x13 |
|---|
| 344 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT__SHIFT 0x14 |
|---|
| 345 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT__SHIFT 0x15 |
|---|
| 346 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT__SHIFT 0x16 |
|---|
| 347 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT__SHIFT 0x17 |
|---|
| 348 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT__SHIFT 0x18 |
|---|
| 349 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT__SHIFT 0x19 |
|---|
| 350 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT__SHIFT 0x1a |
|---|
| 351 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT__SHIFT 0x1b |
|---|
| 352 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT__SHIFT 0x1c |
|---|
| 353 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT__SHIFT 0x1d |
|---|
| 354 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT__SHIFT 0x1e |
|---|
| 355 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT__SHIFT 0x1f |
|---|
| 356 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT_MASK 0x00000002L |
|---|
| 357 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT_MASK 0x00000004L |
|---|
| 358 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT_MASK 0x00000008L |
|---|
| 359 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT_MASK 0x00000010L |
|---|
| 360 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT_MASK 0x00000020L |
|---|
| 361 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT_MASK 0x00000040L |
|---|
| 362 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT_MASK 0x00000080L |
|---|
| 363 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT_MASK 0x00000100L |
|---|
| 364 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT_MASK 0x00000200L |
|---|
| 365 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT_MASK 0x00000400L |
|---|
| 366 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT_MASK 0x00000800L |
|---|
| 367 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT_MASK 0x00001000L |
|---|
| 368 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT_MASK 0x00002000L |
|---|
| 369 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT_MASK 0x00004000L |
|---|
| 370 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT_MASK 0x00008000L |
|---|
| 371 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT_MASK 0x00010000L |
|---|
| 372 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT_MASK 0x00020000L |
|---|
| 373 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT_MASK 0x00040000L |
|---|
| 374 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT_MASK 0x00080000L |
|---|
| 375 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT_MASK 0x00100000L |
|---|
| 376 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT_MASK 0x00200000L |
|---|
| 377 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT_MASK 0x00400000L |
|---|
| 378 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT_MASK 0x00800000L |
|---|
| 379 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT_MASK 0x01000000L |
|---|
| 380 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT_MASK 0x02000000L |
|---|
| 381 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT_MASK 0x04000000L |
|---|
| 382 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT_MASK 0x08000000L |
|---|
| 383 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT_MASK 0x10000000L |
|---|
| 384 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT_MASK 0x20000000L |
|---|
| 385 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT_MASK 0x40000000L |
|---|
| 386 | #define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT_MASK 0x80000000L |
|---|
| 387 | //IH_LIMIT_INT_RATE_CNTL |
|---|
| 388 | #define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE__SHIFT 0x0 |
|---|
| 389 | #define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL__SHIFT 0x1 |
|---|
| 390 | #define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD__SHIFT 0x5 |
|---|
| 391 | #define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY__SHIFT 0x11 |
|---|
| 392 | #define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT__SHIFT 0x15 |
|---|
| 393 | #define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE_MASK 0x00000001L |
|---|
| 394 | #define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL_MASK 0x0000001EL |
|---|
| 395 | #define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD_MASK 0x0000FFE0L |
|---|
| 396 | #define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY_MASK 0x001E0000L |
|---|
| 397 | #define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT_MASK 0xFFE00000L |
|---|
| 398 | //IH_RETRY_INT_CAM_CNTL |
|---|
| 399 | #define IH_RETRY_INT_CAM_CNTL__CAM_SIZE__SHIFT 0x0 |
|---|
| 400 | #define IH_RETRY_INT_CAM_CNTL__BACK_PRESSURE_SKID_VALUE__SHIFT 0x8 |
|---|
| 401 | #define IH_RETRY_INT_CAM_CNTL__PER_VF_ENTRY_SIZE__SHIFT 0x14 |
|---|
| 402 | #define IH_RETRY_INT_CAM_CNTL__CAM_SIZE_MASK 0x0000001FL |
|---|
| 403 | #define IH_RETRY_INT_CAM_CNTL__BACK_PRESSURE_SKID_VALUE_MASK 0x00003F00L |
|---|
| 404 | #define IH_RETRY_INT_CAM_CNTL__PER_VF_ENTRY_SIZE_MASK 0x00300000L |
|---|
| 405 | //IH_MEM_POWER_CTRL |
|---|
| 406 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_CTRL_EN__SHIFT 0x0 |
|---|
| 407 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_LS_EN__SHIFT 0x1 |
|---|
| 408 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DS_EN__SHIFT 0x2 |
|---|
| 409 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_SD_EN__SHIFT 0x3 |
|---|
| 410 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_IDLE_HYSTERESIS__SHIFT 0x4 |
|---|
| 411 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x8 |
|---|
| 412 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0xe |
|---|
| 413 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_CTRL_EN__SHIFT 0x10 |
|---|
| 414 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_LS_EN__SHIFT 0x11 |
|---|
| 415 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DS_EN__SHIFT 0x12 |
|---|
| 416 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_SD_EN__SHIFT 0x13 |
|---|
| 417 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_IDLE_HYSTERESIS__SHIFT 0x14 |
|---|
| 418 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x18 |
|---|
| 419 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0x1e |
|---|
| 420 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_CTRL_EN_MASK 0x00000001L |
|---|
| 421 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_LS_EN_MASK 0x00000002L |
|---|
| 422 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DS_EN_MASK 0x00000004L |
|---|
| 423 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_SD_EN_MASK 0x00000008L |
|---|
| 424 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_IDLE_HYSTERESIS_MASK 0x00000070L |
|---|
| 425 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F00L |
|---|
| 426 | #define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DOWN_ENTER_DELAY_MASK 0x0000C000L |
|---|
| 427 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_CTRL_EN_MASK 0x00010000L |
|---|
| 428 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_LS_EN_MASK 0x00020000L |
|---|
| 429 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DS_EN_MASK 0x00040000L |
|---|
| 430 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_SD_EN_MASK 0x00080000L |
|---|
| 431 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_IDLE_HYSTERESIS_MASK 0x00700000L |
|---|
| 432 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_UP_RECOVER_DELAY_MASK 0x3F000000L |
|---|
| 433 | #define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DOWN_ENTER_DELAY_MASK 0xC0000000L |
|---|
| 434 | //IH_MEM_POWER_CTRL2 |
|---|
| 435 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_CTRL_EN__SHIFT 0x0 |
|---|
| 436 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_LS_EN__SHIFT 0x1 |
|---|
| 437 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DS_EN__SHIFT 0x2 |
|---|
| 438 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_SD_EN__SHIFT 0x3 |
|---|
| 439 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_IDLE_HYSTERESIS__SHIFT 0x4 |
|---|
| 440 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x8 |
|---|
| 441 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0xe |
|---|
| 442 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_CTRL_EN_MASK 0x00000001L |
|---|
| 443 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_LS_EN_MASK 0x00000002L |
|---|
| 444 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DS_EN_MASK 0x00000004L |
|---|
| 445 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_SD_EN_MASK 0x00000008L |
|---|
| 446 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_IDLE_HYSTERESIS_MASK 0x00000070L |
|---|
| 447 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F00L |
|---|
| 448 | #define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DOWN_ENTER_DELAY_MASK 0x0000C000L |
|---|
| 449 | //IH_CNTL2 |
|---|
| 450 | #define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT__SHIFT 0x0 |
|---|
| 451 | #define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE__SHIFT 0x8 |
|---|
| 452 | #define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT_MASK 0x0000001FL |
|---|
| 453 | #define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE_MASK 0x00000100L |
|---|
| 454 | //IH_STATUS |
|---|
| 455 | #define IH_STATUS__IDLE__SHIFT 0x0 |
|---|
| 456 | #define IH_STATUS__INPUT_IDLE__SHIFT 0x1 |
|---|
| 457 | #define IH_STATUS__BUFFER_IDLE__SHIFT 0x2 |
|---|
| 458 | #define IH_STATUS__RB_FULL__SHIFT 0x3 |
|---|
| 459 | #define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4 |
|---|
| 460 | #define IH_STATUS__RB_OVERFLOW__SHIFT 0x5 |
|---|
| 461 | #define IH_STATUS__MC_WR_IDLE__SHIFT 0x6 |
|---|
| 462 | #define IH_STATUS__MC_WR_STALL__SHIFT 0x7 |
|---|
| 463 | #define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8 |
|---|
| 464 | #define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9 |
|---|
| 465 | #define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa |
|---|
| 466 | #define IH_STATUS__SWITCH_READY__SHIFT 0xb |
|---|
| 467 | #define IH_STATUS__RB1_FULL__SHIFT 0xc |
|---|
| 468 | #define IH_STATUS__RB1_FULL_DRAIN__SHIFT 0xd |
|---|
| 469 | #define IH_STATUS__RB1_OVERFLOW__SHIFT 0xe |
|---|
| 470 | #define IH_STATUS__SELF_INT_GEN_IDLE__SHIFT 0x12 |
|---|
| 471 | #define IH_STATUS__RETRY_INT_CAM_IDLE__SHIFT 0x13 |
|---|
| 472 | #define IH_STATUS__ZSTATES_FENCE__SHIFT 0x14 |
|---|
| 473 | #define IH_STATUS__IH_BUFFER_MEM_POWER_GATED__SHIFT 0x15 |
|---|
| 474 | #define IH_STATUS__IH_RETRY_INT_CAM_MEM_POWER_GATED__SHIFT 0x16 |
|---|
| 475 | #define IH_STATUS__IH_PASID_LUT_MEM_POWER_GATED__SHIFT 0x17 |
|---|
| 476 | #define IH_STATUS__IDLE_MASK 0x00000001L |
|---|
| 477 | #define IH_STATUS__INPUT_IDLE_MASK 0x00000002L |
|---|
| 478 | #define IH_STATUS__BUFFER_IDLE_MASK 0x00000004L |
|---|
| 479 | #define IH_STATUS__RB_FULL_MASK 0x00000008L |
|---|
| 480 | #define IH_STATUS__RB_FULL_DRAIN_MASK 0x00000010L |
|---|
| 481 | #define IH_STATUS__RB_OVERFLOW_MASK 0x00000020L |
|---|
| 482 | #define IH_STATUS__MC_WR_IDLE_MASK 0x00000040L |
|---|
| 483 | #define IH_STATUS__MC_WR_STALL_MASK 0x00000080L |
|---|
| 484 | #define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x00000100L |
|---|
| 485 | #define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x00000200L |
|---|
| 486 | #define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x00000400L |
|---|
| 487 | #define IH_STATUS__SWITCH_READY_MASK 0x00000800L |
|---|
| 488 | #define IH_STATUS__RB1_FULL_MASK 0x00001000L |
|---|
| 489 | #define IH_STATUS__RB1_FULL_DRAIN_MASK 0x00002000L |
|---|
| 490 | #define IH_STATUS__RB1_OVERFLOW_MASK 0x00004000L |
|---|
| 491 | #define IH_STATUS__SELF_INT_GEN_IDLE_MASK 0x00040000L |
|---|
| 492 | #define IH_STATUS__RETRY_INT_CAM_IDLE_MASK 0x00080000L |
|---|
| 493 | #define IH_STATUS__ZSTATES_FENCE_MASK 0x00100000L |
|---|
| 494 | #define IH_STATUS__IH_BUFFER_MEM_POWER_GATED_MASK 0x00200000L |
|---|
| 495 | #define IH_STATUS__IH_RETRY_INT_CAM_MEM_POWER_GATED_MASK 0x00400000L |
|---|
| 496 | #define IH_STATUS__IH_PASID_LUT_MEM_POWER_GATED_MASK 0x00800000L |
|---|
| 497 | //IH_PERFMON_CNTL |
|---|
| 498 | #define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0 |
|---|
| 499 | #define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1 |
|---|
| 500 | #define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 |
|---|
| 501 | #define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x10 |
|---|
| 502 | #define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x11 |
|---|
| 503 | #define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0x12 |
|---|
| 504 | #define IH_PERFMON_CNTL__ENABLE0_MASK 0x00000001L |
|---|
| 505 | #define IH_PERFMON_CNTL__CLEAR0_MASK 0x00000002L |
|---|
| 506 | #define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x00000FFCL |
|---|
| 507 | #define IH_PERFMON_CNTL__ENABLE1_MASK 0x00010000L |
|---|
| 508 | #define IH_PERFMON_CNTL__CLEAR1_MASK 0x00020000L |
|---|
| 509 | #define IH_PERFMON_CNTL__PERF_SEL1_MASK 0x0FFC0000L |
|---|
| 510 | //IH_PERFCOUNTER0_RESULT |
|---|
| 511 | #define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 |
|---|
| 512 | #define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL |
|---|
| 513 | //IH_PERFCOUNTER1_RESULT |
|---|
| 514 | #define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 |
|---|
| 515 | #define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL |
|---|
| 516 | //IH_DSM_MATCH_VALUE_BIT_31_0 |
|---|
| 517 | #define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0 |
|---|
| 518 | #define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xFFFFFFFFL |
|---|
| 519 | //IH_DSM_MATCH_VALUE_BIT_63_32 |
|---|
| 520 | #define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0 |
|---|
| 521 | #define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xFFFFFFFFL |
|---|
| 522 | //IH_DSM_MATCH_VALUE_BIT_95_64 |
|---|
| 523 | #define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0 |
|---|
| 524 | #define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xFFFFFFFFL |
|---|
| 525 | //IH_DSM_MATCH_FIELD_CONTROL |
|---|
| 526 | #define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0 |
|---|
| 527 | #define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN__SHIFT 0x1 |
|---|
| 528 | #define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2 |
|---|
| 529 | #define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3 |
|---|
| 530 | #define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4 |
|---|
| 531 | #define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5 |
|---|
| 532 | #define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN__SHIFT 0x6 |
|---|
| 533 | #define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x00000001L |
|---|
| 534 | #define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN_MASK 0x00000002L |
|---|
| 535 | #define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x00000004L |
|---|
| 536 | #define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x00000008L |
|---|
| 537 | #define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x00000010L |
|---|
| 538 | #define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x00000020L |
|---|
| 539 | #define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN_MASK 0x00000040L |
|---|
| 540 | //IH_DSM_MATCH_DATA_CONTROL |
|---|
| 541 | #define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0 |
|---|
| 542 | #define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0x0FFFFFFFL |
|---|
| 543 | //IH_DSM_MATCH_FCN_ID |
|---|
| 544 | #define IH_DSM_MATCH_FCN_ID__VF_ID__SHIFT 0x0 |
|---|
| 545 | #define IH_DSM_MATCH_FCN_ID__PF_VF__SHIFT 0x7 |
|---|
| 546 | #define IH_DSM_MATCH_FCN_ID__VF_ID_MASK 0x0000000FL |
|---|
| 547 | #define IH_DSM_MATCH_FCN_ID__PF_VF_MASK 0x00000080L |
|---|
| 548 | //IH_VF_RB_STATUS |
|---|
| 549 | #define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 |
|---|
| 550 | #define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000FFFFL |
|---|
| 551 | //IH_VF_RB_STATUS2 |
|---|
| 552 | #define IH_VF_RB_STATUS2__RB_FULL_VF__SHIFT 0x0 |
|---|
| 553 | #define IH_VF_RB_STATUS2__RB_FULL_VF_MASK 0x0000FFFFL |
|---|
| 554 | //IH_VF_RB1_STATUS |
|---|
| 555 | #define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 |
|---|
| 556 | #define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000FFFFL |
|---|
| 557 | //IH_VF_RB1_STATUS2 |
|---|
| 558 | #define IH_VF_RB1_STATUS2__RB_FULL_VF__SHIFT 0x0 |
|---|
| 559 | #define IH_VF_RB1_STATUS2__RB_FULL_VF_MASK 0x0000FFFFL |
|---|
| 560 | //IH_RB_STATUS |
|---|
| 561 | #define IH_RB_STATUS__RB_FULL__SHIFT 0x0 |
|---|
| 562 | #define IH_RB_STATUS__RB_FULL_DRAIN__SHIFT 0x1 |
|---|
| 563 | #define IH_RB_STATUS__RB_OVERFLOW__SHIFT 0x2 |
|---|
| 564 | #define IH_RB_STATUS__RB1_FULL__SHIFT 0x4 |
|---|
| 565 | #define IH_RB_STATUS__RB1_FULL_DRAIN__SHIFT 0x5 |
|---|
| 566 | #define IH_RB_STATUS__RB1_OVERFLOW__SHIFT 0x6 |
|---|
| 567 | #define IH_RB_STATUS__RB_FULL_MASK 0x00000001L |
|---|
| 568 | #define IH_RB_STATUS__RB_FULL_DRAIN_MASK 0x00000002L |
|---|
| 569 | #define IH_RB_STATUS__RB_OVERFLOW_MASK 0x00000004L |
|---|
| 570 | #define IH_RB_STATUS__RB1_FULL_MASK 0x00000010L |
|---|
| 571 | #define IH_RB_STATUS__RB1_FULL_DRAIN_MASK 0x00000020L |
|---|
| 572 | #define IH_RB_STATUS__RB1_OVERFLOW_MASK 0x00000040L |
|---|
| 573 | //IH_INT_FLOOD_CNTL |
|---|
| 574 | #define IH_INT_FLOOD_CNTL__HIGHWATER__SHIFT 0x0 |
|---|
| 575 | #define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE__SHIFT 0x3 |
|---|
| 576 | #define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS__SHIFT 0x4 |
|---|
| 577 | #define IH_INT_FLOOD_CNTL__HIGHWATER_MASK 0x00000007L |
|---|
| 578 | #define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE_MASK 0x00000008L |
|---|
| 579 | #define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS_MASK 0x00000010L |
|---|
| 580 | //IH_RB0_INT_FLOOD_STATUS |
|---|
| 581 | #define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0 |
|---|
| 582 | #define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f |
|---|
| 583 | #define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000FFFFL |
|---|
| 584 | #define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L |
|---|
| 585 | //IH_RB1_INT_FLOOD_STATUS |
|---|
| 586 | #define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0 |
|---|
| 587 | #define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f |
|---|
| 588 | #define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000FFFFL |
|---|
| 589 | #define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L |
|---|
| 590 | //IH_INT_FLOOD_STATUS |
|---|
| 591 | #define IH_INT_FLOOD_STATUS__INT_DROP_CNT__SHIFT 0x0 |
|---|
| 592 | #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID__SHIFT 0x8 |
|---|
| 593 | #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID__SHIFT 0x10 |
|---|
| 594 | #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID__SHIFT 0x18 |
|---|
| 595 | #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF__SHIFT 0x1d |
|---|
| 596 | #define IH_INT_FLOOD_STATUS__INT_DROPPED__SHIFT 0x1e |
|---|
| 597 | #define IH_INT_FLOOD_STATUS__INT_DROP_CNT_MASK 0x000000FFL |
|---|
| 598 | #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID_MASK 0x0000FF00L |
|---|
| 599 | #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID_MASK 0x00FF0000L |
|---|
| 600 | #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID_MASK 0x0F000000L |
|---|
| 601 | #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_MASK 0x20000000L |
|---|
| 602 | #define IH_INT_FLOOD_STATUS__INT_DROPPED_MASK 0x40000000L |
|---|
| 603 | //IH_INT_FLAGS |
|---|
| 604 | #define IH_INT_FLAGS__CLIENT_0_FLAG__SHIFT 0x0 |
|---|
| 605 | #define IH_INT_FLAGS__CLIENT_1_FLAG__SHIFT 0x1 |
|---|
| 606 | #define IH_INT_FLAGS__CLIENT_2_FLAG__SHIFT 0x2 |
|---|
| 607 | #define IH_INT_FLAGS__CLIENT_3_FLAG__SHIFT 0x3 |
|---|
| 608 | #define IH_INT_FLAGS__CLIENT_4_FLAG__SHIFT 0x4 |
|---|
| 609 | #define IH_INT_FLAGS__CLIENT_5_FLAG__SHIFT 0x5 |
|---|
| 610 | #define IH_INT_FLAGS__CLIENT_6_FLAG__SHIFT 0x6 |
|---|
| 611 | #define IH_INT_FLAGS__CLIENT_7_FLAG__SHIFT 0x7 |
|---|
| 612 | #define IH_INT_FLAGS__CLIENT_8_FLAG__SHIFT 0x8 |
|---|
| 613 | #define IH_INT_FLAGS__CLIENT_9_FLAG__SHIFT 0x9 |
|---|
| 614 | #define IH_INT_FLAGS__CLIENT_10_FLAG__SHIFT 0xa |
|---|
| 615 | #define IH_INT_FLAGS__CLIENT_11_FLAG__SHIFT 0xb |
|---|
| 616 | #define IH_INT_FLAGS__CLIENT_12_FLAG__SHIFT 0xc |
|---|
| 617 | #define IH_INT_FLAGS__CLIENT_13_FLAG__SHIFT 0xd |
|---|
| 618 | #define IH_INT_FLAGS__CLIENT_14_FLAG__SHIFT 0xe |
|---|
| 619 | #define IH_INT_FLAGS__CLIENT_15_FLAG__SHIFT 0xf |
|---|
| 620 | #define IH_INT_FLAGS__CLIENT_16_FLAG__SHIFT 0x10 |
|---|
| 621 | #define IH_INT_FLAGS__CLIENT_17_FLAG__SHIFT 0x11 |
|---|
| 622 | #define IH_INT_FLAGS__CLIENT_18_FLAG__SHIFT 0x12 |
|---|
| 623 | #define IH_INT_FLAGS__CLIENT_19_FLAG__SHIFT 0x13 |
|---|
| 624 | #define IH_INT_FLAGS__CLIENT_20_FLAG__SHIFT 0x14 |
|---|
| 625 | #define IH_INT_FLAGS__CLIENT_21_FLAG__SHIFT 0x15 |
|---|
| 626 | #define IH_INT_FLAGS__CLIENT_22_FLAG__SHIFT 0x16 |
|---|
| 627 | #define IH_INT_FLAGS__CLIENT_23_FLAG__SHIFT 0x17 |
|---|
| 628 | #define IH_INT_FLAGS__CLIENT_24_FLAG__SHIFT 0x18 |
|---|
| 629 | #define IH_INT_FLAGS__CLIENT_25_FLAG__SHIFT 0x19 |
|---|
| 630 | #define IH_INT_FLAGS__CLIENT_26_FLAG__SHIFT 0x1a |
|---|
| 631 | #define IH_INT_FLAGS__CLIENT_27_FLAG__SHIFT 0x1b |
|---|
| 632 | #define IH_INT_FLAGS__CLIENT_28_FLAG__SHIFT 0x1c |
|---|
| 633 | #define IH_INT_FLAGS__CLIENT_29_FLAG__SHIFT 0x1d |
|---|
| 634 | #define IH_INT_FLAGS__CLIENT_30_FLAG__SHIFT 0x1e |
|---|
| 635 | #define IH_INT_FLAGS__CLIENT_31_FLAG__SHIFT 0x1f |
|---|
| 636 | #define IH_INT_FLAGS__CLIENT_0_FLAG_MASK 0x00000001L |
|---|
| 637 | #define IH_INT_FLAGS__CLIENT_1_FLAG_MASK 0x00000002L |
|---|
| 638 | #define IH_INT_FLAGS__CLIENT_2_FLAG_MASK 0x00000004L |
|---|
| 639 | #define IH_INT_FLAGS__CLIENT_3_FLAG_MASK 0x00000008L |
|---|
| 640 | #define IH_INT_FLAGS__CLIENT_4_FLAG_MASK 0x00000010L |
|---|
| 641 | #define IH_INT_FLAGS__CLIENT_5_FLAG_MASK 0x00000020L |
|---|
| 642 | #define IH_INT_FLAGS__CLIENT_6_FLAG_MASK 0x00000040L |
|---|
| 643 | #define IH_INT_FLAGS__CLIENT_7_FLAG_MASK 0x00000080L |
|---|
| 644 | #define IH_INT_FLAGS__CLIENT_8_FLAG_MASK 0x00000100L |
|---|
| 645 | #define IH_INT_FLAGS__CLIENT_9_FLAG_MASK 0x00000200L |
|---|
| 646 | #define IH_INT_FLAGS__CLIENT_10_FLAG_MASK 0x00000400L |
|---|
| 647 | #define IH_INT_FLAGS__CLIENT_11_FLAG_MASK 0x00000800L |
|---|
| 648 | #define IH_INT_FLAGS__CLIENT_12_FLAG_MASK 0x00001000L |
|---|
| 649 | #define IH_INT_FLAGS__CLIENT_13_FLAG_MASK 0x00002000L |
|---|
| 650 | #define IH_INT_FLAGS__CLIENT_14_FLAG_MASK 0x00004000L |
|---|
| 651 | #define IH_INT_FLAGS__CLIENT_15_FLAG_MASK 0x00008000L |
|---|
| 652 | #define IH_INT_FLAGS__CLIENT_16_FLAG_MASK 0x00010000L |
|---|
| 653 | #define IH_INT_FLAGS__CLIENT_17_FLAG_MASK 0x00020000L |
|---|
| 654 | #define IH_INT_FLAGS__CLIENT_18_FLAG_MASK 0x00040000L |
|---|
| 655 | #define IH_INT_FLAGS__CLIENT_19_FLAG_MASK 0x00080000L |
|---|
| 656 | #define IH_INT_FLAGS__CLIENT_20_FLAG_MASK 0x00100000L |
|---|
| 657 | #define IH_INT_FLAGS__CLIENT_21_FLAG_MASK 0x00200000L |
|---|
| 658 | #define IH_INT_FLAGS__CLIENT_22_FLAG_MASK 0x00400000L |
|---|
| 659 | #define IH_INT_FLAGS__CLIENT_23_FLAG_MASK 0x00800000L |
|---|
| 660 | #define IH_INT_FLAGS__CLIENT_24_FLAG_MASK 0x01000000L |
|---|
| 661 | #define IH_INT_FLAGS__CLIENT_25_FLAG_MASK 0x02000000L |
|---|
| 662 | #define IH_INT_FLAGS__CLIENT_26_FLAG_MASK 0x04000000L |
|---|
| 663 | #define IH_INT_FLAGS__CLIENT_27_FLAG_MASK 0x08000000L |
|---|
| 664 | #define IH_INT_FLAGS__CLIENT_28_FLAG_MASK 0x10000000L |
|---|
| 665 | #define IH_INT_FLAGS__CLIENT_29_FLAG_MASK 0x20000000L |
|---|
| 666 | #define IH_INT_FLAGS__CLIENT_30_FLAG_MASK 0x40000000L |
|---|
| 667 | #define IH_INT_FLAGS__CLIENT_31_FLAG_MASK 0x80000000L |
|---|
| 668 | //IH_LAST_INT_INFO0 |
|---|
| 669 | #define IH_LAST_INT_INFO0__CLIENT_ID__SHIFT 0x0 |
|---|
| 670 | #define IH_LAST_INT_INFO0__SOURCE_ID__SHIFT 0x8 |
|---|
| 671 | #define IH_LAST_INT_INFO0__RING_ID__SHIFT 0x10 |
|---|
| 672 | #define IH_LAST_INT_INFO0__VM_ID__SHIFT 0x18 |
|---|
| 673 | #define IH_LAST_INT_INFO0__VMID_TYPE__SHIFT 0x1f |
|---|
| 674 | #define IH_LAST_INT_INFO0__CLIENT_ID_MASK 0x000000FFL |
|---|
| 675 | #define IH_LAST_INT_INFO0__SOURCE_ID_MASK 0x0000FF00L |
|---|
| 676 | #define IH_LAST_INT_INFO0__RING_ID_MASK 0x00FF0000L |
|---|
| 677 | #define IH_LAST_INT_INFO0__VM_ID_MASK 0x0F000000L |
|---|
| 678 | #define IH_LAST_INT_INFO0__VMID_TYPE_MASK 0x80000000L |
|---|
| 679 | //IH_LAST_INT_INFO1 |
|---|
| 680 | #define IH_LAST_INT_INFO1__CONTEXT_ID__SHIFT 0x0 |
|---|
| 681 | #define IH_LAST_INT_INFO1__CONTEXT_ID_MASK 0xFFFFFFFFL |
|---|
| 682 | //IH_LAST_INT_INFO2 |
|---|
| 683 | #define IH_LAST_INT_INFO2__PAS_ID__SHIFT 0x0 |
|---|
| 684 | #define IH_LAST_INT_INFO2__VF_ID__SHIFT 0x10 |
|---|
| 685 | #define IH_LAST_INT_INFO2__VF__SHIFT 0x17 |
|---|
| 686 | #define IH_LAST_INT_INFO2__PAS_ID_MASK 0x0000FFFFL |
|---|
| 687 | #define IH_LAST_INT_INFO2__VF_ID_MASK 0x000F0000L |
|---|
| 688 | #define IH_LAST_INT_INFO2__VF_MASK 0x00800000L |
|---|
| 689 | //IH_SCRATCH |
|---|
| 690 | #define IH_SCRATCH__DATA__SHIFT 0x0 |
|---|
| 691 | #define IH_SCRATCH__DATA_MASK 0xFFFFFFFFL |
|---|
| 692 | //IH_CLIENT_CREDIT_ERROR |
|---|
| 693 | #define IH_CLIENT_CREDIT_ERROR__CLEAR__SHIFT 0x0 |
|---|
| 694 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR__SHIFT 0x1 |
|---|
| 695 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR__SHIFT 0x2 |
|---|
| 696 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR__SHIFT 0x3 |
|---|
| 697 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR__SHIFT 0x4 |
|---|
| 698 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR__SHIFT 0x5 |
|---|
| 699 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR__SHIFT 0x6 |
|---|
| 700 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR__SHIFT 0x7 |
|---|
| 701 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR__SHIFT 0x8 |
|---|
| 702 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR__SHIFT 0x9 |
|---|
| 703 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR__SHIFT 0xa |
|---|
| 704 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR__SHIFT 0xb |
|---|
| 705 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR__SHIFT 0xc |
|---|
| 706 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR__SHIFT 0xd |
|---|
| 707 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR__SHIFT 0xe |
|---|
| 708 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR__SHIFT 0xf |
|---|
| 709 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR__SHIFT 0x10 |
|---|
| 710 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR__SHIFT 0x11 |
|---|
| 711 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR__SHIFT 0x12 |
|---|
| 712 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR__SHIFT 0x13 |
|---|
| 713 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR__SHIFT 0x14 |
|---|
| 714 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR__SHIFT 0x15 |
|---|
| 715 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR__SHIFT 0x16 |
|---|
| 716 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR__SHIFT 0x17 |
|---|
| 717 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR__SHIFT 0x18 |
|---|
| 718 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR__SHIFT 0x19 |
|---|
| 719 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR__SHIFT 0x1a |
|---|
| 720 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR__SHIFT 0x1b |
|---|
| 721 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR__SHIFT 0x1c |
|---|
| 722 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR__SHIFT 0x1d |
|---|
| 723 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR__SHIFT 0x1e |
|---|
| 724 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR__SHIFT 0x1f |
|---|
| 725 | #define IH_CLIENT_CREDIT_ERROR__CLEAR_MASK 0x00000001L |
|---|
| 726 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR_MASK 0x00000002L |
|---|
| 727 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR_MASK 0x00000004L |
|---|
| 728 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR_MASK 0x00000008L |
|---|
| 729 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR_MASK 0x00000010L |
|---|
| 730 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR_MASK 0x00000020L |
|---|
| 731 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR_MASK 0x00000040L |
|---|
| 732 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR_MASK 0x00000080L |
|---|
| 733 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR_MASK 0x00000100L |
|---|
| 734 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR_MASK 0x00000200L |
|---|
| 735 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR_MASK 0x00000400L |
|---|
| 736 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR_MASK 0x00000800L |
|---|
| 737 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR_MASK 0x00001000L |
|---|
| 738 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR_MASK 0x00002000L |
|---|
| 739 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR_MASK 0x00004000L |
|---|
| 740 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR_MASK 0x00008000L |
|---|
| 741 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR_MASK 0x00010000L |
|---|
| 742 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR_MASK 0x00020000L |
|---|
| 743 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR_MASK 0x00040000L |
|---|
| 744 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR_MASK 0x00080000L |
|---|
| 745 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR_MASK 0x00100000L |
|---|
| 746 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR_MASK 0x00200000L |
|---|
| 747 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR_MASK 0x00400000L |
|---|
| 748 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR_MASK 0x00800000L |
|---|
| 749 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR_MASK 0x01000000L |
|---|
| 750 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR_MASK 0x02000000L |
|---|
| 751 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR_MASK 0x04000000L |
|---|
| 752 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR_MASK 0x08000000L |
|---|
| 753 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR_MASK 0x10000000L |
|---|
| 754 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR_MASK 0x20000000L |
|---|
| 755 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR_MASK 0x40000000L |
|---|
| 756 | #define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR_MASK 0x80000000L |
|---|
| 757 | //IH_GPU_IOV_VIOLATION_LOG |
|---|
| 758 | #define IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 |
|---|
| 759 | #define IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 |
|---|
| 760 | #define IH_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 |
|---|
| 761 | #define IH_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x16 |
|---|
| 762 | #define IH_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x17 |
|---|
| 763 | #define IH_GPU_IOV_VIOLATION_LOG__VF_ID__SHIFT 0x18 |
|---|
| 764 | #define IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L |
|---|
| 765 | #define IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L |
|---|
| 766 | #define IH_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL |
|---|
| 767 | #define IH_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00400000L |
|---|
| 768 | #define IH_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00800000L |
|---|
| 769 | #define IH_GPU_IOV_VIOLATION_LOG__VF_ID_MASK 0x0F000000L |
|---|
| 770 | //IH_GPU_IOV_VIOLATION_LOG2 |
|---|
| 771 | #define IH_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 |
|---|
| 772 | #define IH_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL |
|---|
| 773 | //IH_COOKIE_REC_VIOLATION_LOG |
|---|
| 774 | #define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 |
|---|
| 775 | #define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID__SHIFT 0x8 |
|---|
| 776 | #define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x10 |
|---|
| 777 | #define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L |
|---|
| 778 | #define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID_MASK 0x0000FF00L |
|---|
| 779 | #define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID_MASK 0x03FF0000L |
|---|
| 780 | //IH_CREDIT_STATUS |
|---|
| 781 | #define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED__SHIFT 0x1 |
|---|
| 782 | #define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED__SHIFT 0x2 |
|---|
| 783 | #define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED__SHIFT 0x3 |
|---|
| 784 | #define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED__SHIFT 0x4 |
|---|
| 785 | #define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED__SHIFT 0x5 |
|---|
| 786 | #define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED__SHIFT 0x6 |
|---|
| 787 | #define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED__SHIFT 0x7 |
|---|
| 788 | #define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED__SHIFT 0x8 |
|---|
| 789 | #define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED__SHIFT 0x9 |
|---|
| 790 | #define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED__SHIFT 0xa |
|---|
| 791 | #define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED__SHIFT 0xb |
|---|
| 792 | #define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED__SHIFT 0xc |
|---|
| 793 | #define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED__SHIFT 0xd |
|---|
| 794 | #define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED__SHIFT 0xe |
|---|
| 795 | #define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED__SHIFT 0xf |
|---|
| 796 | #define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED__SHIFT 0x10 |
|---|
| 797 | #define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED__SHIFT 0x11 |
|---|
| 798 | #define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED__SHIFT 0x12 |
|---|
| 799 | #define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED__SHIFT 0x13 |
|---|
| 800 | #define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED__SHIFT 0x14 |
|---|
| 801 | #define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED__SHIFT 0x15 |
|---|
| 802 | #define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED__SHIFT 0x16 |
|---|
| 803 | #define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED__SHIFT 0x17 |
|---|
| 804 | #define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED__SHIFT 0x18 |
|---|
| 805 | #define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED__SHIFT 0x19 |
|---|
| 806 | #define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED__SHIFT 0x1a |
|---|
| 807 | #define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED__SHIFT 0x1b |
|---|
| 808 | #define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED__SHIFT 0x1c |
|---|
| 809 | #define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED__SHIFT 0x1d |
|---|
| 810 | #define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED__SHIFT 0x1e |
|---|
| 811 | #define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED__SHIFT 0x1f |
|---|
| 812 | #define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED_MASK 0x00000002L |
|---|
| 813 | #define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED_MASK 0x00000004L |
|---|
| 814 | #define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED_MASK 0x00000008L |
|---|
| 815 | #define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED_MASK 0x00000010L |
|---|
| 816 | #define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED_MASK 0x00000020L |
|---|
| 817 | #define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED_MASK 0x00000040L |
|---|
| 818 | #define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED_MASK 0x00000080L |
|---|
| 819 | #define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED_MASK 0x00000100L |
|---|
| 820 | #define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED_MASK 0x00000200L |
|---|
| 821 | #define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED_MASK 0x00000400L |
|---|
| 822 | #define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED_MASK 0x00000800L |
|---|
| 823 | #define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED_MASK 0x00001000L |
|---|
| 824 | #define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED_MASK 0x00002000L |
|---|
| 825 | #define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED_MASK 0x00004000L |
|---|
| 826 | #define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED_MASK 0x00008000L |
|---|
| 827 | #define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED_MASK 0x00010000L |
|---|
| 828 | #define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED_MASK 0x00020000L |
|---|
| 829 | #define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED_MASK 0x00040000L |
|---|
| 830 | #define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED_MASK 0x00080000L |
|---|
| 831 | #define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED_MASK 0x00100000L |
|---|
| 832 | #define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED_MASK 0x00200000L |
|---|
| 833 | #define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED_MASK 0x00400000L |
|---|
| 834 | #define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED_MASK 0x00800000L |
|---|
| 835 | #define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED_MASK 0x01000000L |
|---|
| 836 | #define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED_MASK 0x02000000L |
|---|
| 837 | #define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED_MASK 0x04000000L |
|---|
| 838 | #define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED_MASK 0x08000000L |
|---|
| 839 | #define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED_MASK 0x10000000L |
|---|
| 840 | #define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED_MASK 0x20000000L |
|---|
| 841 | #define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED_MASK 0x40000000L |
|---|
| 842 | #define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED_MASK 0x80000000L |
|---|
| 843 | //IH_MMHUB_ERROR |
|---|
| 844 | #define IH_MMHUB_ERROR__IH_BRESP_01__SHIFT 0x1 |
|---|
| 845 | #define IH_MMHUB_ERROR__IH_BRESP_10__SHIFT 0x2 |
|---|
| 846 | #define IH_MMHUB_ERROR__IH_BRESP_11__SHIFT 0x3 |
|---|
| 847 | #define IH_MMHUB_ERROR__IH_BUSER_NACK_01__SHIFT 0x5 |
|---|
| 848 | #define IH_MMHUB_ERROR__IH_BUSER_NACK_10__SHIFT 0x6 |
|---|
| 849 | #define IH_MMHUB_ERROR__IH_BUSER_NACK_11__SHIFT 0x7 |
|---|
| 850 | #define IH_MMHUB_ERROR__IH_BRESP_01_MASK 0x00000002L |
|---|
| 851 | #define IH_MMHUB_ERROR__IH_BRESP_10_MASK 0x00000004L |
|---|
| 852 | #define IH_MMHUB_ERROR__IH_BRESP_11_MASK 0x00000008L |
|---|
| 853 | #define IH_MMHUB_ERROR__IH_BUSER_NACK_01_MASK 0x00000020L |
|---|
| 854 | #define IH_MMHUB_ERROR__IH_BUSER_NACK_10_MASK 0x00000040L |
|---|
| 855 | #define IH_MMHUB_ERROR__IH_BUSER_NACK_11_MASK 0x00000080L |
|---|
| 856 | //IH_VF_RB_STATUS3 |
|---|
| 857 | #define IH_VF_RB_STATUS3__RB_OVERFLOW_VF__SHIFT 0x0 |
|---|
| 858 | #define IH_VF_RB_STATUS3__RB_OVERFLOW_VF_MASK 0x0000FFFFL |
|---|
| 859 | //IH_VF_RB_STATUS4 |
|---|
| 860 | #define IH_VF_RB_STATUS4__BIF_INTERRUPT_LINE_VF__SHIFT 0x0 |
|---|
| 861 | #define IH_VF_RB_STATUS4__BIF_INTERRUPT_LINE_VF_MASK 0x0000FFFFL |
|---|
| 862 | //IH_VF_RB1_STATUS3 |
|---|
| 863 | #define IH_VF_RB1_STATUS3__RB_OVERFLOW_VF__SHIFT 0x0 |
|---|
| 864 | #define IH_VF_RB1_STATUS3__RB_OVERFLOW_VF_MASK 0x0000FFFFL |
|---|
| 865 | //IH_MSI_STORM_CTRL |
|---|
| 866 | #define IH_MSI_STORM_CTRL__DELAY__SHIFT 0x0 |
|---|
| 867 | #define IH_MSI_STORM_CTRL__DELAY_MASK 0x00000FFFL |
|---|
| 868 | //IH_MSI_STORM_CLIENT_INDEX |
|---|
| 869 | #define IH_MSI_STORM_CLIENT_INDEX__INDEX__SHIFT 0x0 |
|---|
| 870 | #define IH_MSI_STORM_CLIENT_INDEX__INDEX_MASK 0x00000007L |
|---|
| 871 | //IH_MSI_STORM_CLIENT_DATA |
|---|
| 872 | #define IH_MSI_STORM_CLIENT_DATA__CLIENT_ID__SHIFT 0x0 |
|---|
| 873 | #define IH_MSI_STORM_CLIENT_DATA__SOURCE_ID__SHIFT 0x8 |
|---|
| 874 | #define IH_MSI_STORM_CLIENT_DATA__SOURCE_ID_MATCH_ENABLE__SHIFT 0x10 |
|---|
| 875 | #define IH_MSI_STORM_CLIENT_DATA__UTCL2_PAGE_FAULT_MATCH_ENABLE__SHIFT 0x11 |
|---|
| 876 | #define IH_MSI_STORM_CLIENT_DATA__ENTRY_VALID__SHIFT 0x1f |
|---|
| 877 | #define IH_MSI_STORM_CLIENT_DATA__CLIENT_ID_MASK 0x000000FFL |
|---|
| 878 | #define IH_MSI_STORM_CLIENT_DATA__SOURCE_ID_MASK 0x0000FF00L |
|---|
| 879 | #define IH_MSI_STORM_CLIENT_DATA__SOURCE_ID_MATCH_ENABLE_MASK 0x00010000L |
|---|
| 880 | #define IH_MSI_STORM_CLIENT_DATA__UTCL2_PAGE_FAULT_MATCH_ENABLE_MASK 0x00020000L |
|---|
| 881 | #define IH_MSI_STORM_CLIENT_DATA__ENTRY_VALID_MASK 0x80000000L |
|---|
| 882 | //IH_REGISTER_LAST_PART2 |
|---|
| 883 | #define IH_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0 |
|---|
| 884 | #define IH_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 885 | //SEM_MAILBOX |
|---|
| 886 | #define SEM_MAILBOX__HOSTPORT__SHIFT 0x0 |
|---|
| 887 | #define SEM_MAILBOX__RESERVED__SHIFT 0x10 |
|---|
| 888 | #define SEM_MAILBOX__HOSTPORT_MASK 0x0000FFFFL |
|---|
| 889 | #define SEM_MAILBOX__RESERVED_MASK 0xFFFF0000L |
|---|
| 890 | //SEM_MAILBOX_CLEAR |
|---|
| 891 | #define SEM_MAILBOX_CLEAR__CLEAR__SHIFT 0x0 |
|---|
| 892 | #define SEM_MAILBOX_CLEAR__RESERVED__SHIFT 0x10 |
|---|
| 893 | #define SEM_MAILBOX_CLEAR__CLEAR_MASK 0x0000FFFFL |
|---|
| 894 | #define SEM_MAILBOX_CLEAR__RESERVED_MASK 0xFFFF0000L |
|---|
| 895 | //SEM_REGISTER_LAST_PART2 |
|---|
| 896 | #define SEM_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0 |
|---|
| 897 | #define SEM_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 898 | //IH_ACTIVE_FCN_ID |
|---|
| 899 | #define IH_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 |
|---|
| 900 | #define IH_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 |
|---|
| 901 | #define IH_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f |
|---|
| 902 | #define IH_ACTIVE_FCN_ID__VF_ID_MASK 0x0000000FL |
|---|
| 903 | #define IH_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L |
|---|
| 904 | #define IH_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L |
|---|
| 905 | //IH_VIRT_RESET_REQ |
|---|
| 906 | #define IH_VIRT_RESET_REQ__VF__SHIFT 0x0 |
|---|
| 907 | #define IH_VIRT_RESET_REQ__PF__SHIFT 0x1f |
|---|
| 908 | #define IH_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL |
|---|
| 909 | #define IH_VIRT_RESET_REQ__PF_MASK 0x80000000L |
|---|
| 910 | //IH_CLIENT_CFG |
|---|
| 911 | #define IH_CLIENT_CFG__TOTAL_CLIENT_NUM__SHIFT 0x0 |
|---|
| 912 | #define IH_CLIENT_CFG__TOTAL_CLIENT_NUM_MASK 0x0000003FL |
|---|
| 913 | //IH_RING1_CLIENT_CFG_INDEX |
|---|
| 914 | #define IH_RING1_CLIENT_CFG_INDEX__INDEX__SHIFT 0x0 |
|---|
| 915 | #define IH_RING1_CLIENT_CFG_INDEX__INDEX_MASK 0x00000007L |
|---|
| 916 | //IH_RING1_CLIENT_CFG_DATA |
|---|
| 917 | #define IH_RING1_CLIENT_CFG_DATA__CLIENT_ID__SHIFT 0x0 |
|---|
| 918 | #define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID__SHIFT 0x8 |
|---|
| 919 | #define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MATCH_ENABLE__SHIFT 0x10 |
|---|
| 920 | #define IH_RING1_CLIENT_CFG_DATA__CLIENT_ID_MASK 0x000000FFL |
|---|
| 921 | #define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MASK 0x0000FF00L |
|---|
| 922 | #define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MATCH_ENABLE_MASK 0x00010000L |
|---|
| 923 | //IH_CLIENT_CFG_INDEX |
|---|
| 924 | #define IH_CLIENT_CFG_INDEX__INDEX__SHIFT 0x0 |
|---|
| 925 | #define IH_CLIENT_CFG_INDEX__INDEX_MASK 0x0000001FL |
|---|
| 926 | //IH_CLIENT_CFG_DATA |
|---|
| 927 | #define IH_CLIENT_CFG_DATA__CLIENT_TYPE__SHIFT 0x12 |
|---|
| 928 | #define IH_CLIENT_CFG_DATA__VF_RB_SELECT__SHIFT 0x16 |
|---|
| 929 | #define IH_CLIENT_CFG_DATA__OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID__SHIFT 0x18 |
|---|
| 930 | #define IH_CLIENT_CFG_DATA__INTERFACE_TYPE__SHIFT 0x19 |
|---|
| 931 | #define IH_CLIENT_CFG_DATA__CLIENT_TYPE_MASK 0x000C0000L |
|---|
| 932 | #define IH_CLIENT_CFG_DATA__VF_RB_SELECT_MASK 0x00C00000L |
|---|
| 933 | #define IH_CLIENT_CFG_DATA__OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID_MASK 0x01000000L |
|---|
| 934 | #define IH_CLIENT_CFG_DATA__INTERFACE_TYPE_MASK 0x02000000L |
|---|
| 935 | //IH_CLIENT_CFG_DATA2 |
|---|
| 936 | #define IH_CLIENT_CFG_DATA2__CREDIT_RETURN_ADDR__SHIFT 0x0 |
|---|
| 937 | #define IH_CLIENT_CFG_DATA2__CREDIT_RETURN_ADDR_MASK 0xFFFFFFFFL |
|---|
| 938 | //IH_CID_REMAP_INDEX |
|---|
| 939 | #define IH_CID_REMAP_INDEX__INDEX__SHIFT 0x0 |
|---|
| 940 | #define IH_CID_REMAP_INDEX__INDEX_MASK 0x00000003L |
|---|
| 941 | //IH_CID_REMAP_DATA |
|---|
| 942 | #define IH_CID_REMAP_DATA__CLIENT_ID__SHIFT 0x0 |
|---|
| 943 | #define IH_CID_REMAP_DATA__INITIATOR_ID__SHIFT 0x8 |
|---|
| 944 | #define IH_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT 0x18 |
|---|
| 945 | #define IH_CID_REMAP_DATA__CLIENT_ID_MASK 0x000000FFL |
|---|
| 946 | #define IH_CID_REMAP_DATA__INITIATOR_ID_MASK 0x0003FF00L |
|---|
| 947 | #define IH_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK 0xFF000000L |
|---|
| 948 | //IH_CHICKEN |
|---|
| 949 | #define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE__SHIFT 0x0 |
|---|
| 950 | #define IH_CHICKEN__DBGU_TRIGGER_ENABLE__SHIFT 0x1 |
|---|
| 951 | #define IH_CHICKEN__CROSS_TRIGGER_ENABLE__SHIFT 0x2 |
|---|
| 952 | #define IH_CHICKEN__MC_SPACE_FBPA_ENABLE__SHIFT 0x3 |
|---|
| 953 | #define IH_CHICKEN__MC_SPACE_GPA_ENABLE__SHIFT 0x4 |
|---|
| 954 | #define IH_CHICKEN__REG_FIREWALL_ENABLE__SHIFT 0x5 |
|---|
| 955 | #define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE_MASK 0x00000001L |
|---|
| 956 | #define IH_CHICKEN__DBGU_TRIGGER_ENABLE_MASK 0x00000002L |
|---|
| 957 | #define IH_CHICKEN__CROSS_TRIGGER_ENABLE_MASK 0x00000004L |
|---|
| 958 | #define IH_CHICKEN__MC_SPACE_FBPA_ENABLE_MASK 0x00000008L |
|---|
| 959 | #define IH_CHICKEN__MC_SPACE_GPA_ENABLE_MASK 0x00000010L |
|---|
| 960 | #define IH_CHICKEN__REG_FIREWALL_ENABLE_MASK 0x00000020L |
|---|
| 961 | //IH_MMHUB_CNTL |
|---|
| 962 | #define IH_MMHUB_CNTL__UNITID__SHIFT 0x0 |
|---|
| 963 | #define IH_MMHUB_CNTL__IV_TLVL__SHIFT 0x8 |
|---|
| 964 | #define IH_MMHUB_CNTL__WPTR_WB_TLVL__SHIFT 0xc |
|---|
| 965 | #define IH_MMHUB_CNTL__UNITID_MASK 0x0000003FL |
|---|
| 966 | #define IH_MMHUB_CNTL__IV_TLVL_MASK 0x00000F00L |
|---|
| 967 | #define IH_MMHUB_CNTL__WPTR_WB_TLVL_MASK 0x0000F000L |
|---|
| 968 | //IH_INT_DROP_CNTL |
|---|
| 969 | #define IH_INT_DROP_CNTL__INT_DROP_EN__SHIFT 0x0 |
|---|
| 970 | #define IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN__SHIFT 0x1 |
|---|
| 971 | #define IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN__SHIFT 0x2 |
|---|
| 972 | #define IH_INT_DROP_CNTL__VF_ID_MATCH_EN__SHIFT 0x3 |
|---|
| 973 | #define IH_INT_DROP_CNTL__VF_MATCH_EN__SHIFT 0x4 |
|---|
| 974 | #define IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN__SHIFT 0x5 |
|---|
| 975 | #define IH_INT_DROP_CNTL__INT_DROP_MODE__SHIFT 0x6 |
|---|
| 976 | #define IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN__SHIFT 0x8 |
|---|
| 977 | #define IH_INT_DROP_CNTL__INT_DROPPED__SHIFT 0x10 |
|---|
| 978 | #define IH_INT_DROP_CNTL__INT_DROP_EN_MASK 0x00000001L |
|---|
| 979 | #define IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN_MASK 0x00000002L |
|---|
| 980 | #define IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN_MASK 0x00000004L |
|---|
| 981 | #define IH_INT_DROP_CNTL__VF_ID_MATCH_EN_MASK 0x00000008L |
|---|
| 982 | #define IH_INT_DROP_CNTL__VF_MATCH_EN_MASK 0x00000010L |
|---|
| 983 | #define IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN_MASK 0x00000020L |
|---|
| 984 | #define IH_INT_DROP_CNTL__INT_DROP_MODE_MASK 0x000000C0L |
|---|
| 985 | #define IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN_MASK 0x00000100L |
|---|
| 986 | #define IH_INT_DROP_CNTL__INT_DROPPED_MASK 0x00010000L |
|---|
| 987 | //IH_INT_DROP_MATCH_VALUE0 |
|---|
| 988 | #define IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE__SHIFT 0x0 |
|---|
| 989 | #define IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE__SHIFT 0x8 |
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| 990 | #define IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE__SHIFT 0x10 |
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| 991 | #define IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE__SHIFT 0x17 |
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| 992 | #define IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE__SHIFT 0x18 |
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| 993 | #define IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE_MASK 0x000000FFL |
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| 994 | #define IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE_MASK 0x0000FF00L |
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| 995 | #define IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE_MASK 0x001F0000L |
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| 996 | #define IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE_MASK 0x00800000L |
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| 997 | #define IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE_MASK 0xFF000000L |
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| 998 | //IH_INT_DROP_MATCH_VALUE1 |
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| 999 | #define IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE__SHIFT 0x0 |
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| 1000 | #define IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE_MASK 0xFFFFFFFFL |
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| 1001 | //IH_INT_DROP_MATCH_MASK0 |
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| 1002 | #define IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK__SHIFT 0x0 |
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| 1003 | #define IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK__SHIFT 0x8 |
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| 1004 | #define IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK__SHIFT 0x10 |
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| 1005 | #define IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK__SHIFT 0x17 |
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| 1006 | #define IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK__SHIFT 0x18 |
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| 1007 | #define IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK_MASK 0x000000FFL |
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| 1008 | #define IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK_MASK 0x0000FF00L |
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| 1009 | #define IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK_MASK 0x001F0000L |
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| 1010 | #define IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK_MASK 0x00800000L |
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| 1011 | #define IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK_MASK 0xFF000000L |
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| 1012 | //IH_INT_DROP_MATCH_MASK1 |
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| 1013 | #define IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK__SHIFT 0x0 |
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| 1014 | #define IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK_MASK 0xFFFFFFFFL |
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| 1015 | //IH_REGISTER_LAST_PART1 |
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| 1016 | #define IH_REGISTER_LAST_PART1__RESERVED__SHIFT 0x0 |
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| 1017 | #define IH_REGISTER_LAST_PART1__RESERVED_MASK 0xFFFFFFFFL |
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| 1018 | |
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| 1019 | #endif |
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| 1020 | |
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