1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef _sdma_4_4_2_SH_MASK_HEADER
24#define _sdma_4_4_2_SH_MASK_HEADER
25
26
27// addressBlock: aid_sdma_insts_sdma0_sdmadec
28//SDMA_UCODE_ADDR
29#define SDMA_UCODE_ADDR__VALUE__SHIFT 0x0
30#define SDMA_UCODE_ADDR__VALUE_MASK 0x00003FFFL
31//SDMA_UCODE_DATA
32#define SDMA_UCODE_DATA__VALUE__SHIFT 0x0
33#define SDMA_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL
34//SDMA_F32_CNTL
35#define SDMA_F32_CNTL__HALT__SHIFT 0x0
36#define SDMA_F32_CNTL__STEP__SHIFT 0x1
37#define SDMA_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2
38#define SDMA_F32_CNTL__RESET__SHIFT 0x8
39#define SDMA_F32_CNTL__CHECKSUM_CLR__SHIFT 0x9
40#define SDMA_F32_CNTL__HALT_MASK 0x00000001L
41#define SDMA_F32_CNTL__STEP_MASK 0x00000002L
42#define SDMA_F32_CNTL__DBG_SELECT_BITS_MASK 0x000000FCL
43#define SDMA_F32_CNTL__RESET_MASK 0x00000100L
44#define SDMA_F32_CNTL__CHECKSUM_CLR_MASK 0x00000200L
45//SDMA_MMHUB_CNTL
46#define SDMA_MMHUB_CNTL__UNIT_ID__SHIFT 0x0
47#define SDMA_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL
48//SDMA_MMHUB_TRUSTLVL
49#define SDMA_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0
50#define SDMA_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x4
51#define SDMA_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x8
52#define SDMA_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0xc
53#define SDMA_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0x10
54#define SDMA_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0x14
55#define SDMA_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x18
56#define SDMA_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x1c
57#define SDMA_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x0000000FL
58#define SDMA_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x000000F0L
59#define SDMA_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x00000F00L
60#define SDMA_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x0000F000L
61#define SDMA_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x000F0000L
62#define SDMA_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00F00000L
63#define SDMA_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x0F000000L
64#define SDMA_MMHUB_TRUSTLVL__SECFLAG7_MASK 0xF0000000L
65//SDMA_VM_CNTL
66#define SDMA_VM_CNTL__CMD__SHIFT 0x0
67#define SDMA_VM_CNTL__CMD_MASK 0x0000000FL
68//SDMA_VM_CTX_LO
69#define SDMA_VM_CTX_LO__ADDR__SHIFT 0x2
70#define SDMA_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL
71//SDMA_VM_CTX_HI
72#define SDMA_VM_CTX_HI__ADDR__SHIFT 0x0
73#define SDMA_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL
74//SDMA_ACTIVE_FCN_ID
75#define SDMA_ACTIVE_FCN_ID__VFID__SHIFT 0x0
76#define SDMA_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
77#define SDMA_ACTIVE_FCN_ID__VF__SHIFT 0x1f
78#define SDMA_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
79#define SDMA_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L
80#define SDMA_ACTIVE_FCN_ID__VF_MASK 0x80000000L
81//SDMA_VM_CTX_CNTL
82#define SDMA_VM_CTX_CNTL__PRIV__SHIFT 0x0
83#define SDMA_VM_CTX_CNTL__VMID__SHIFT 0x4
84#define SDMA_VM_CTX_CNTL__PRIV_MASK 0x00000001L
85#define SDMA_VM_CTX_CNTL__VMID_MASK 0x000000F0L
86//SDMA_VIRT_RESET_REQ
87#define SDMA_VIRT_RESET_REQ__VF__SHIFT 0x0
88#define SDMA_VIRT_RESET_REQ__PF__SHIFT 0x1f
89#define SDMA_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
90#define SDMA_VIRT_RESET_REQ__PF_MASK 0x80000000L
91//SDMA_VF_ENABLE
92#define SDMA_VF_ENABLE__VF_ENABLE__SHIFT 0x0
93#define SDMA_VF_ENABLE__VF_ENABLE_MASK 0x00000001L
94//SDMA_CONTEXT_REG_TYPE0
95#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_CNTL__SHIFT 0x0
96#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_BASE__SHIFT 0x1
97#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_BASE_HI__SHIFT 0x2
98#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_RPTR__SHIFT 0x3
99#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_RPTR_HI__SHIFT 0x4
100#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_WPTR__SHIFT 0x5
101#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_WPTR_HI__SHIFT 0x6
102#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7
103#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8
104#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9
105#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_CNTL__SHIFT 0xa
106#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_RPTR__SHIFT 0xb
107#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_OFFSET__SHIFT 0xc
108#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_BASE_LO__SHIFT 0xd
109#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_BASE_HI__SHIFT 0xe
110#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_SIZE__SHIFT 0xf
111#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_SKIP_CNTL__SHIFT 0x10
112#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_CONTEXT_STATUS__SHIFT 0x11
113#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_DOORBELL__SHIFT 0x12
114#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_CONTEXT_CNTL__SHIFT 0x13
115#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_CNTL_MASK 0x00000001L
116#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_BASE_MASK 0x00000002L
117#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_BASE_HI_MASK 0x00000004L
118#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_RPTR_MASK 0x00000008L
119#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_RPTR_HI_MASK 0x00000010L
120#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_WPTR_MASK 0x00000020L
121#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_WPTR_HI_MASK 0x00000040L
122#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L
123#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L
124#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L
125#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_CNTL_MASK 0x00000400L
126#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_RPTR_MASK 0x00000800L
127#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_OFFSET_MASK 0x00001000L
128#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_BASE_LO_MASK 0x00002000L
129#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_BASE_HI_MASK 0x00004000L
130#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_SIZE_MASK 0x00008000L
131#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_SKIP_CNTL_MASK 0x00010000L
132#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_CONTEXT_STATUS_MASK 0x00020000L
133#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_DOORBELL_MASK 0x00040000L
134#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_CONTEXT_CNTL_MASK 0x00080000L
135//SDMA_CONTEXT_REG_TYPE1
136#define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_STATUS__SHIFT 0x8
137#define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_DOORBELL_LOG__SHIFT 0x9
138#define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_WATERMARK__SHIFT 0xa
139#define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_DOORBELL_OFFSET__SHIFT 0xb
140#define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_CSA_ADDR_LO__SHIFT 0xc
141#define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_CSA_ADDR_HI__SHIFT 0xd
142#define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_IB_SUB_REMAIN__SHIFT 0xf
143#define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_PREEMPT__SHIFT 0x10
144#define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_DUMMY_REG__SHIFT 0x11
145#define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12
146#define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13
147#define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_RB_AQL_CNTL__SHIFT 0x14
148#define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_MINOR_PTR_UPDATE__SHIFT 0x15
149#define SDMA_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16
150#define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_STATUS_MASK 0x00000100L
151#define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_DOORBELL_LOG_MASK 0x00000200L
152#define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_WATERMARK_MASK 0x00000400L
153#define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_DOORBELL_OFFSET_MASK 0x00000800L
154#define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_CSA_ADDR_LO_MASK 0x00001000L
155#define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_CSA_ADDR_HI_MASK 0x00002000L
156#define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_IB_SUB_REMAIN_MASK 0x00008000L
157#define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_PREEMPT_MASK 0x00010000L
158#define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_DUMMY_REG_MASK 0x00020000L
159#define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L
160#define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L
161#define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_RB_AQL_CNTL_MASK 0x00100000L
162#define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L
163#define SDMA_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L
164//SDMA_CONTEXT_REG_TYPE2
165#define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA0__SHIFT 0x0
166#define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA1__SHIFT 0x1
167#define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA2__SHIFT 0x2
168#define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA3__SHIFT 0x3
169#define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA4__SHIFT 0x4
170#define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA5__SHIFT 0x5
171#define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA6__SHIFT 0x6
172#define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA7__SHIFT 0x7
173#define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA8__SHIFT 0x8
174#define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA9__SHIFT 0x9
175#define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA10__SHIFT 0xa
176#define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_CNTL__SHIFT 0xb
177#define SDMA_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xe
178#define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA0_MASK 0x00000001L
179#define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA1_MASK 0x00000002L
180#define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA2_MASK 0x00000004L
181#define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA3_MASK 0x00000008L
182#define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA4_MASK 0x00000010L
183#define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA5_MASK 0x00000020L
184#define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA6_MASK 0x00000040L
185#define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA7_MASK 0x00000080L
186#define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA8_MASK 0x00000100L
187#define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA9_MASK 0x00000200L
188#define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA10_MASK 0x00000400L
189#define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_CNTL_MASK 0x00000800L
190#define SDMA_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFC000L
191//SDMA_CONTEXT_REG_TYPE3
192#define SDMA_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0
193#define SDMA_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL
194//SDMA_PUB_REG_TYPE0
195#define SDMA_PUB_REG_TYPE0__SDMA_UCODE_ADDR__SHIFT 0x0
196#define SDMA_PUB_REG_TYPE0__SDMA_UCODE_DATA__SHIFT 0x1
197#define SDMA_PUB_REG_TYPE0__SDMA_F32_CNTL__SHIFT 0x2
198#define SDMA_PUB_REG_TYPE0__SDMA_MMHUB_CNTL__SHIFT 0x5
199#define SDMA_PUB_REG_TYPE0__SDMA_MMHUB_TRUSTLVL__SHIFT 0x6
200#define SDMA_PUB_REG_TYPE0__RESERVED_14_10__SHIFT 0xa
201#define SDMA_PUB_REG_TYPE0__SDMA_VM_CNTL__SHIFT 0x10
202#define SDMA_PUB_REG_TYPE0__SDMA_VM_CTX_LO__SHIFT 0x11
203#define SDMA_PUB_REG_TYPE0__SDMA_VM_CTX_HI__SHIFT 0x12
204#define SDMA_PUB_REG_TYPE0__SDMA_ACTIVE_FCN_ID__SHIFT 0x13
205#define SDMA_PUB_REG_TYPE0__SDMA_VM_CTX_CNTL__SHIFT 0x14
206#define SDMA_PUB_REG_TYPE0__SDMA_VIRT_RESET_REQ__SHIFT 0x15
207#define SDMA_PUB_REG_TYPE0__SDMA_VF_ENABLE__SHIFT 0x16
208#define SDMA_PUB_REG_TYPE0__SDMA_CONTEXT_REG_TYPE0__SHIFT 0x17
209#define SDMA_PUB_REG_TYPE0__SDMA_CONTEXT_REG_TYPE1__SHIFT 0x18
210#define SDMA_PUB_REG_TYPE0__SDMA_CONTEXT_REG_TYPE2__SHIFT 0x19
211#define SDMA_PUB_REG_TYPE0__SDMA_CONTEXT_REG_TYPE3__SHIFT 0x1a
212#define SDMA_PUB_REG_TYPE0__SDMA_PUB_REG_TYPE0__SHIFT 0x1b
213#define SDMA_PUB_REG_TYPE0__SDMA_PUB_REG_TYPE1__SHIFT 0x1c
214#define SDMA_PUB_REG_TYPE0__SDMA_PUB_REG_TYPE2__SHIFT 0x1d
215#define SDMA_PUB_REG_TYPE0__SDMA_PUB_REG_TYPE3__SHIFT 0x1e
216#define SDMA_PUB_REG_TYPE0__SDMA_CONTEXT_GROUP_BOUNDARY__SHIFT 0x1f
217#define SDMA_PUB_REG_TYPE0__SDMA_UCODE_ADDR_MASK 0x00000001L
218#define SDMA_PUB_REG_TYPE0__SDMA_UCODE_DATA_MASK 0x00000002L
219#define SDMA_PUB_REG_TYPE0__SDMA_F32_CNTL_MASK 0x00000004L
220#define SDMA_PUB_REG_TYPE0__SDMA_MMHUB_CNTL_MASK 0x00000020L
221#define SDMA_PUB_REG_TYPE0__SDMA_MMHUB_TRUSTLVL_MASK 0x00000040L
222#define SDMA_PUB_REG_TYPE0__RESERVED_14_10_MASK 0x00007C00L
223#define SDMA_PUB_REG_TYPE0__SDMA_VM_CNTL_MASK 0x00010000L
224#define SDMA_PUB_REG_TYPE0__SDMA_VM_CTX_LO_MASK 0x00020000L
225#define SDMA_PUB_REG_TYPE0__SDMA_VM_CTX_HI_MASK 0x00040000L
226#define SDMA_PUB_REG_TYPE0__SDMA_ACTIVE_FCN_ID_MASK 0x00080000L
227#define SDMA_PUB_REG_TYPE0__SDMA_VM_CTX_CNTL_MASK 0x00100000L
228#define SDMA_PUB_REG_TYPE0__SDMA_VIRT_RESET_REQ_MASK 0x00200000L
229#define SDMA_PUB_REG_TYPE0__SDMA_VF_ENABLE_MASK 0x00400000L
230#define SDMA_PUB_REG_TYPE0__SDMA_CONTEXT_REG_TYPE0_MASK 0x00800000L
231#define SDMA_PUB_REG_TYPE0__SDMA_CONTEXT_REG_TYPE1_MASK 0x01000000L
232#define SDMA_PUB_REG_TYPE0__SDMA_CONTEXT_REG_TYPE2_MASK 0x02000000L
233#define SDMA_PUB_REG_TYPE0__SDMA_CONTEXT_REG_TYPE3_MASK 0x04000000L
234#define SDMA_PUB_REG_TYPE0__SDMA_PUB_REG_TYPE0_MASK 0x08000000L
235#define SDMA_PUB_REG_TYPE0__SDMA_PUB_REG_TYPE1_MASK 0x10000000L
236#define SDMA_PUB_REG_TYPE0__SDMA_PUB_REG_TYPE2_MASK 0x20000000L
237#define SDMA_PUB_REG_TYPE0__SDMA_PUB_REG_TYPE3_MASK 0x40000000L
238#define SDMA_PUB_REG_TYPE0__SDMA_CONTEXT_GROUP_BOUNDARY_MASK 0x80000000L
239//SDMA_PUB_REG_TYPE1
240#define SDMA_PUB_REG_TYPE1__SDMA_RB_RPTR_FETCH_HI__SHIFT 0x0
241#define SDMA_PUB_REG_TYPE1__SDMA_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1
242#define SDMA_PUB_REG_TYPE1__SDMA_RB_RPTR_FETCH__SHIFT 0x2
243#define SDMA_PUB_REG_TYPE1__SDMA_IB_OFFSET_FETCH__SHIFT 0x3
244#define SDMA_PUB_REG_TYPE1__SDMA_PROGRAM__SHIFT 0x4
245#define SDMA_PUB_REG_TYPE1__SDMA_STATUS_REG__SHIFT 0x5
246#define SDMA_PUB_REG_TYPE1__SDMA_STATUS1_REG__SHIFT 0x6
247#define SDMA_PUB_REG_TYPE1__SDMA_RD_BURST_CNTL__SHIFT 0x7
248#define SDMA_PUB_REG_TYPE1__SDMA_HBM_PAGE_CONFIG__SHIFT 0x8
249#define SDMA_PUB_REG_TYPE1__SDMA_UCODE_CHECKSUM__SHIFT 0x9
250#define SDMA_PUB_REG_TYPE1__RESERVED_10_10__SHIFT 0xa
251#define SDMA_PUB_REG_TYPE1__SDMA_FREEZE__SHIFT 0xb
252#define SDMA_PUB_REG_TYPE1__SDMA_PHASE0_QUANTUM__SHIFT 0xc
253#define SDMA_PUB_REG_TYPE1__SDMA_PHASE1_QUANTUM__SHIFT 0xd
254#define SDMA_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe
255#define SDMA_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf
256#define SDMA_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10
257#define SDMA_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11
258#define SDMA_PUB_REG_TYPE1__CC_SDMA_EDC_CONFIG__SHIFT 0x12
259#define SDMA_PUB_REG_TYPE1__SDMA_BA_THRESHOLD__SHIFT 0x13
260#define SDMA_PUB_REG_TYPE1__SDMA_ID__SHIFT 0x14
261#define SDMA_PUB_REG_TYPE1__SDMA_VERSION__SHIFT 0x15
262#define SDMA_PUB_REG_TYPE1__SDMA_EDC_COUNTER__SHIFT 0x16
263#define SDMA_PUB_REG_TYPE1__SDMA_EDC_COUNTER2__SHIFT 0x17
264#define SDMA_PUB_REG_TYPE1__SDMA_STATUS2_REG__SHIFT 0x18
265#define SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_CNTL__SHIFT 0x19
266#define SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PREOP_LO__SHIFT 0x1a
267#define SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PREOP_HI__SHIFT 0x1b
268#define SDMA_PUB_REG_TYPE1__SDMA_UTCL1_CNTL__SHIFT 0x1c
269#define SDMA_PUB_REG_TYPE1__SDMA_UTCL1_WATERMK__SHIFT 0x1d
270#define SDMA_PUB_REG_TYPE1__SDMA_UTCL1_RD_STATUS__SHIFT 0x1e
271#define SDMA_PUB_REG_TYPE1__SDMA_UTCL1_WR_STATUS__SHIFT 0x1f
272#define SDMA_PUB_REG_TYPE1__SDMA_RB_RPTR_FETCH_HI_MASK 0x00000001L
273#define SDMA_PUB_REG_TYPE1__SDMA_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L
274#define SDMA_PUB_REG_TYPE1__SDMA_RB_RPTR_FETCH_MASK 0x00000004L
275#define SDMA_PUB_REG_TYPE1__SDMA_IB_OFFSET_FETCH_MASK 0x00000008L
276#define SDMA_PUB_REG_TYPE1__SDMA_PROGRAM_MASK 0x00000010L
277#define SDMA_PUB_REG_TYPE1__SDMA_STATUS_REG_MASK 0x00000020L
278#define SDMA_PUB_REG_TYPE1__SDMA_STATUS1_REG_MASK 0x00000040L
279#define SDMA_PUB_REG_TYPE1__SDMA_RD_BURST_CNTL_MASK 0x00000080L
280#define SDMA_PUB_REG_TYPE1__SDMA_HBM_PAGE_CONFIG_MASK 0x00000100L
281#define SDMA_PUB_REG_TYPE1__SDMA_UCODE_CHECKSUM_MASK 0x00000200L
282#define SDMA_PUB_REG_TYPE1__RESERVED_10_10_MASK 0x00000400L
283#define SDMA_PUB_REG_TYPE1__SDMA_FREEZE_MASK 0x00000800L
284#define SDMA_PUB_REG_TYPE1__SDMA_PHASE0_QUANTUM_MASK 0x00001000L
285#define SDMA_PUB_REG_TYPE1__SDMA_PHASE1_QUANTUM_MASK 0x00002000L
286#define SDMA_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L
287#define SDMA_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L
288#define SDMA_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L
289#define SDMA_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L
290#define SDMA_PUB_REG_TYPE1__CC_SDMA_EDC_CONFIG_MASK 0x00040000L
291#define SDMA_PUB_REG_TYPE1__SDMA_BA_THRESHOLD_MASK 0x00080000L
292#define SDMA_PUB_REG_TYPE1__SDMA_ID_MASK 0x00100000L
293#define SDMA_PUB_REG_TYPE1__SDMA_VERSION_MASK 0x00200000L
294#define SDMA_PUB_REG_TYPE1__SDMA_EDC_COUNTER_MASK 0x00400000L
295#define SDMA_PUB_REG_TYPE1__SDMA_EDC_COUNTER2_MASK 0x00800000L
296#define SDMA_PUB_REG_TYPE1__SDMA_STATUS2_REG_MASK 0x01000000L
297#define SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_CNTL_MASK 0x02000000L
298#define SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PREOP_LO_MASK 0x04000000L
299#define SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PREOP_HI_MASK 0x08000000L
300#define SDMA_PUB_REG_TYPE1__SDMA_UTCL1_CNTL_MASK 0x10000000L
301#define SDMA_PUB_REG_TYPE1__SDMA_UTCL1_WATERMK_MASK 0x20000000L
302#define SDMA_PUB_REG_TYPE1__SDMA_UTCL1_RD_STATUS_MASK 0x40000000L
303#define SDMA_PUB_REG_TYPE1__SDMA_UTCL1_WR_STATUS_MASK 0x80000000L
304//SDMA_PUB_REG_TYPE2
305#define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV0__SHIFT 0x0
306#define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV1__SHIFT 0x1
307#define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV2__SHIFT 0x2
308#define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_XNACK0__SHIFT 0x3
309#define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_XNACK1__SHIFT 0x4
310#define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_XNACK0__SHIFT 0x5
311#define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_XNACK1__SHIFT 0x6
312#define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_TIMEOUT__SHIFT 0x7
313#define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_PAGE__SHIFT 0x8
314#define SDMA_PUB_REG_TYPE2__SDMA_POWER_CNTL_IDLE__SHIFT 0x9
315#define SDMA_PUB_REG_TYPE2__SDMA_RELAX_ORDERING_LUT__SHIFT 0xa
316#define SDMA_PUB_REG_TYPE2__SDMA_CHICKEN_BITS_2__SHIFT 0xb
317#define SDMA_PUB_REG_TYPE2__SDMA_STATUS3_REG__SHIFT 0xc
318#define SDMA_PUB_REG_TYPE2__SDMA_PHYSICAL_ADDR_LO__SHIFT 0xd
319#define SDMA_PUB_REG_TYPE2__SDMA_PHYSICAL_ADDR_HI__SHIFT 0xe
320#define SDMA_PUB_REG_TYPE2__SDMA_PHASE2_QUANTUM__SHIFT 0xf
321#define SDMA_PUB_REG_TYPE2__SDMA_ERROR_LOG__SHIFT 0x10
322#define SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG0__SHIFT 0x11
323#define SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG1__SHIFT 0x12
324#define SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG2__SHIFT 0x13
325#define SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG3__SHIFT 0x14
326#define SDMA_PUB_REG_TYPE2__SDMA_F32_COUNTER__SHIFT 0x15
327#define SDMA_PUB_REG_TYPE2__RESERVED_22_22__SHIFT 0x16
328#define SDMA_PUB_REG_TYPE2__SDMA_PERFCNT_PERFCOUNTER0_CFG__SHIFT 0x17
329#define SDMA_PUB_REG_TYPE2__SDMA_PERFCNT_PERFCOUNTER1_CFG__SHIFT 0x18
330#define SDMA_PUB_REG_TYPE2__SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__SHIFT 0x19
331#define SDMA_PUB_REG_TYPE2__SDMA_PERFCNT_MISC_CNTL__SHIFT 0x1a
332#define SDMA_PUB_REG_TYPE2__SDMA_PERFCNT_PERFCOUNTER_LO__SHIFT 0x1b
333#define SDMA_PUB_REG_TYPE2__SDMA_PERFCNT_PERFCOUNTER_HI__SHIFT 0x1c
334#define SDMA_PUB_REG_TYPE2__SDMA_CRD_CNTL__SHIFT 0x1d
335#define SDMA_PUB_REG_TYPE2__SDMA_GPU_IOV_VIOLATION_LOG__SHIFT 0x1e
336#define SDMA_PUB_REG_TYPE2__SDMA_ULV_CNTL__SHIFT 0x1f
337#define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV0_MASK 0x00000001L
338#define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV1_MASK 0x00000002L
339#define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV2_MASK 0x00000004L
340#define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_XNACK0_MASK 0x00000008L
341#define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_XNACK1_MASK 0x00000010L
342#define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_XNACK0_MASK 0x00000020L
343#define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_XNACK1_MASK 0x00000040L
344#define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_TIMEOUT_MASK 0x00000080L
345#define SDMA_PUB_REG_TYPE2__SDMA_UTCL1_PAGE_MASK 0x00000100L
346#define SDMA_PUB_REG_TYPE2__SDMA_POWER_CNTL_IDLE_MASK 0x00000200L
347#define SDMA_PUB_REG_TYPE2__SDMA_RELAX_ORDERING_LUT_MASK 0x00000400L
348#define SDMA_PUB_REG_TYPE2__SDMA_CHICKEN_BITS_2_MASK 0x00000800L
349#define SDMA_PUB_REG_TYPE2__SDMA_STATUS3_REG_MASK 0x00001000L
350#define SDMA_PUB_REG_TYPE2__SDMA_PHYSICAL_ADDR_LO_MASK 0x00002000L
351#define SDMA_PUB_REG_TYPE2__SDMA_PHYSICAL_ADDR_HI_MASK 0x00004000L
352#define SDMA_PUB_REG_TYPE2__SDMA_PHASE2_QUANTUM_MASK 0x00008000L
353#define SDMA_PUB_REG_TYPE2__SDMA_ERROR_LOG_MASK 0x00010000L
354#define SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG0_MASK 0x00020000L
355#define SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG1_MASK 0x00040000L
356#define SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG2_MASK 0x00080000L
357#define SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG3_MASK 0x00100000L
358#define SDMA_PUB_REG_TYPE2__SDMA_F32_COUNTER_MASK 0x00200000L
359#define SDMA_PUB_REG_TYPE2__RESERVED_22_22_MASK 0x00400000L
360#define SDMA_PUB_REG_TYPE2__SDMA_PERFCNT_PERFCOUNTER0_CFG_MASK 0x00800000L
361#define SDMA_PUB_REG_TYPE2__SDMA_PERFCNT_PERFCOUNTER1_CFG_MASK 0x01000000L
362#define SDMA_PUB_REG_TYPE2__SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL_MASK 0x02000000L
363#define SDMA_PUB_REG_TYPE2__SDMA_PERFCNT_MISC_CNTL_MASK 0x04000000L
364#define SDMA_PUB_REG_TYPE2__SDMA_PERFCNT_PERFCOUNTER_LO_MASK 0x08000000L
365#define SDMA_PUB_REG_TYPE2__SDMA_PERFCNT_PERFCOUNTER_HI_MASK 0x10000000L
366#define SDMA_PUB_REG_TYPE2__SDMA_CRD_CNTL_MASK 0x20000000L
367#define SDMA_PUB_REG_TYPE2__SDMA_GPU_IOV_VIOLATION_LOG_MASK 0x40000000L
368#define SDMA_PUB_REG_TYPE2__SDMA_ULV_CNTL_MASK 0x80000000L
369//SDMA_PUB_REG_TYPE3
370#define SDMA_PUB_REG_TYPE3__SDMA_EA_DBIT_ADDR_DATA__SHIFT 0x0
371#define SDMA_PUB_REG_TYPE3__SDMA_EA_DBIT_ADDR_INDEX__SHIFT 0x1
372#define SDMA_PUB_REG_TYPE3__SDMA_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2
373#define SDMA_PUB_REG_TYPE3__SDMA_STATUS4_REG__SHIFT 0x3
374#define SDMA_PUB_REG_TYPE3__SDMA_SCRATCH_RAM_DATA__SHIFT 0x4
375#define SDMA_PUB_REG_TYPE3__SDMA_SCRATCH_RAM_ADDR__SHIFT 0x5
376#define SDMA_PUB_REG_TYPE3__SDMA_CE_CTRL__SHIFT 0x6
377#define SDMA_PUB_REG_TYPE3__SDMA_RAS_STATUS__SHIFT 0x7
378#define SDMA_PUB_REG_TYPE3__SDMA_CLK_STATUS__SHIFT 0x8
379#define SDMA_PUB_REG_TYPE3__SDMA_POWER_CNTL__SHIFT 0xb
380#define SDMA_PUB_REG_TYPE3__SDMA_CLK_CTRL__SHIFT 0xc
381#define SDMA_PUB_REG_TYPE3__SDMA_CNTL__SHIFT 0xd
382#define SDMA_PUB_REG_TYPE3__SDMA_CHICKEN_BITS__SHIFT 0xe
383#define SDMA_PUB_REG_TYPE3__SDMA_GB_ADDR_CONFIG__SHIFT 0xf
384#define SDMA_PUB_REG_TYPE3__SDMA_GB_ADDR_CONFIG_READ__SHIFT 0x10
385#define SDMA_PUB_REG_TYPE3__RESERVED__SHIFT 0x13
386#define SDMA_PUB_REG_TYPE3__SDMA_EA_DBIT_ADDR_DATA_MASK 0x00000001L
387#define SDMA_PUB_REG_TYPE3__SDMA_EA_DBIT_ADDR_INDEX_MASK 0x00000002L
388#define SDMA_PUB_REG_TYPE3__SDMA_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L
389#define SDMA_PUB_REG_TYPE3__SDMA_STATUS4_REG_MASK 0x00000008L
390#define SDMA_PUB_REG_TYPE3__SDMA_SCRATCH_RAM_DATA_MASK 0x00000010L
391#define SDMA_PUB_REG_TYPE3__SDMA_SCRATCH_RAM_ADDR_MASK 0x00000020L
392#define SDMA_PUB_REG_TYPE3__SDMA_CE_CTRL_MASK 0x00000040L
393#define SDMA_PUB_REG_TYPE3__SDMA_RAS_STATUS_MASK 0x00000080L
394#define SDMA_PUB_REG_TYPE3__SDMA_CLK_STATUS_MASK 0x00000100L
395#define SDMA_PUB_REG_TYPE3__SDMA_POWER_CNTL_MASK 0x00000800L
396#define SDMA_PUB_REG_TYPE3__SDMA_CLK_CTRL_MASK 0x00001000L
397#define SDMA_PUB_REG_TYPE3__SDMA_CNTL_MASK 0x00002000L
398#define SDMA_PUB_REG_TYPE3__SDMA_CHICKEN_BITS_MASK 0x00004000L
399#define SDMA_PUB_REG_TYPE3__SDMA_GB_ADDR_CONFIG_MASK 0x00008000L
400#define SDMA_PUB_REG_TYPE3__SDMA_GB_ADDR_CONFIG_READ_MASK 0x00010000L
401#define SDMA_PUB_REG_TYPE3__RESERVED_MASK 0xFFF80000L
402//SDMA_CONTEXT_GROUP_BOUNDARY
403#define SDMA_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0
404#define SDMA_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL
405//SDMA_RB_RPTR_FETCH_HI
406#define SDMA_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0
407#define SDMA_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL
408//SDMA_SEM_WAIT_FAIL_TIMER_CNTL
409#define SDMA_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
410#define SDMA_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL
411//SDMA_RB_RPTR_FETCH
412#define SDMA_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
413#define SDMA_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL
414//SDMA_IB_OFFSET_FETCH
415#define SDMA_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
416#define SDMA_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL
417//SDMA_PROGRAM
418#define SDMA_PROGRAM__STREAM__SHIFT 0x0
419#define SDMA_PROGRAM__STREAM_MASK 0xFFFFFFFFL
420//SDMA_STATUS_REG
421#define SDMA_STATUS_REG__IDLE__SHIFT 0x0
422#define SDMA_STATUS_REG__REG_IDLE__SHIFT 0x1
423#define SDMA_STATUS_REG__RB_EMPTY__SHIFT 0x2
424#define SDMA_STATUS_REG__RB_FULL__SHIFT 0x3
425#define SDMA_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
426#define SDMA_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
427#define SDMA_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
428#define SDMA_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
429#define SDMA_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
430#define SDMA_STATUS_REG__INSIDE_IB__SHIFT 0x9
431#define SDMA_STATUS_REG__EX_IDLE__SHIFT 0xa
432#define SDMA_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
433#define SDMA_STATUS_REG__PACKET_READY__SHIFT 0xc
434#define SDMA_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
435#define SDMA_STATUS_REG__SRBM_IDLE__SHIFT 0xe
436#define SDMA_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
437#define SDMA_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
438#define SDMA_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
439#define SDMA_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
440#define SDMA_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
441#define SDMA_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
442#define SDMA_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
443#define SDMA_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
444#define SDMA_STATUS_REG__DRM_IDLE__SHIFT 0x17
445#define SDMA_STATUS_REG__DRM_MASK_FULL__SHIFT 0x18
446#define SDMA_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
447#define SDMA_STATUS_REG__SEM_IDLE__SHIFT 0x1a
448#define SDMA_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
449#define SDMA_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
450#define SDMA_STATUS_REG__INT_IDLE__SHIFT 0x1e
451#define SDMA_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
452#define SDMA_STATUS_REG__IDLE_MASK 0x00000001L
453#define SDMA_STATUS_REG__REG_IDLE_MASK 0x00000002L
454#define SDMA_STATUS_REG__RB_EMPTY_MASK 0x00000004L
455#define SDMA_STATUS_REG__RB_FULL_MASK 0x00000008L
456#define SDMA_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L
457#define SDMA_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L
458#define SDMA_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L
459#define SDMA_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L
460#define SDMA_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L
461#define SDMA_STATUS_REG__INSIDE_IB_MASK 0x00000200L
462#define SDMA_STATUS_REG__EX_IDLE_MASK 0x00000400L
463#define SDMA_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L
464#define SDMA_STATUS_REG__PACKET_READY_MASK 0x00001000L
465#define SDMA_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L
466#define SDMA_STATUS_REG__SRBM_IDLE_MASK 0x00004000L
467#define SDMA_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L
468#define SDMA_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L
469#define SDMA_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L
470#define SDMA_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L
471#define SDMA_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L
472#define SDMA_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L
473#define SDMA_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L
474#define SDMA_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L
475#define SDMA_STATUS_REG__DRM_IDLE_MASK 0x00800000L
476#define SDMA_STATUS_REG__DRM_MASK_FULL_MASK 0x01000000L
477#define SDMA_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L
478#define SDMA_STATUS_REG__SEM_IDLE_MASK 0x04000000L
479#define SDMA_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L
480#define SDMA_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L
481#define SDMA_STATUS_REG__INT_IDLE_MASK 0x40000000L
482#define SDMA_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L
483//SDMA_STATUS1_REG
484#define SDMA_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
485#define SDMA_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
486#define SDMA_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
487#define SDMA_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
488#define SDMA_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
489#define SDMA_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
490#define SDMA_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
491#define SDMA_STATUS1_REG__CE_DRM_IDLE__SHIFT 0x7
492#define SDMA_STATUS1_REG__CE_DRM1_IDLE__SHIFT 0x8
493#define SDMA_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
494#define SDMA_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
495#define SDMA_STATUS1_REG__CE_DRM_FULL__SHIFT 0xb
496#define SDMA_STATUS1_REG__CE_DRM1_FULL__SHIFT 0xc
497#define SDMA_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
498#define SDMA_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
499#define SDMA_STATUS1_REG__EX_START__SHIFT 0xf
500#define SDMA_STATUS1_REG__DRM_CTX_RESTORE__SHIFT 0x10
501#define SDMA_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
502#define SDMA_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
503#define SDMA_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L
504#define SDMA_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L
505#define SDMA_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L
506#define SDMA_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L
507#define SDMA_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L
508#define SDMA_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L
509#define SDMA_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L
510#define SDMA_STATUS1_REG__CE_DRM_IDLE_MASK 0x00000080L
511#define SDMA_STATUS1_REG__CE_DRM1_IDLE_MASK 0x00000100L
512#define SDMA_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L
513#define SDMA_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L
514#define SDMA_STATUS1_REG__CE_DRM_FULL_MASK 0x00000800L
515#define SDMA_STATUS1_REG__CE_DRM1_FULL_MASK 0x00001000L
516#define SDMA_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L
517#define SDMA_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L
518#define SDMA_STATUS1_REG__EX_START_MASK 0x00008000L
519#define SDMA_STATUS1_REG__DRM_CTX_RESTORE_MASK 0x00010000L
520#define SDMA_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L
521#define SDMA_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L
522//SDMA_RD_BURST_CNTL
523#define SDMA_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
524#define SDMA_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2
525#define SDMA_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L
526#define SDMA_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL
527//SDMA_HBM_PAGE_CONFIG
528#define SDMA_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0
529#define SDMA_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L
530//SDMA_UCODE_CHECKSUM
531#define SDMA_UCODE_CHECKSUM__DATA__SHIFT 0x0
532#define SDMA_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL
533//SDMA_FREEZE
534#define SDMA_FREEZE__PREEMPT__SHIFT 0x0
535#define SDMA_FREEZE__FREEZE__SHIFT 0x4
536#define SDMA_FREEZE__FROZEN__SHIFT 0x5
537#define SDMA_FREEZE__F32_FREEZE__SHIFT 0x6
538#define SDMA_FREEZE__PREEMPT_MASK 0x00000001L
539#define SDMA_FREEZE__FREEZE_MASK 0x00000010L
540#define SDMA_FREEZE__FROZEN_MASK 0x00000020L
541#define SDMA_FREEZE__F32_FREEZE_MASK 0x00000040L
542//SDMA_PHASE0_QUANTUM
543#define SDMA_PHASE0_QUANTUM__UNIT__SHIFT 0x0
544#define SDMA_PHASE0_QUANTUM__VALUE__SHIFT 0x8
545#define SDMA_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
546#define SDMA_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL
547#define SDMA_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L
548#define SDMA_PHASE0_QUANTUM__PREFER_MASK 0x40000000L
549//SDMA_PHASE1_QUANTUM
550#define SDMA_PHASE1_QUANTUM__UNIT__SHIFT 0x0
551#define SDMA_PHASE1_QUANTUM__VALUE__SHIFT 0x8
552#define SDMA_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
553#define SDMA_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL
554#define SDMA_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L
555#define SDMA_PHASE1_QUANTUM__PREFER_MASK 0x40000000L
556//SDMA_POWER_GATING
557#define SDMA_POWER_GATING__SDMA_POWER_OFF_CONDITION__SHIFT 0x0
558#define SDMA_POWER_GATING__SDMA_POWER_ON_CONDITION__SHIFT 0x1
559#define SDMA_POWER_GATING__SDMA_POWER_OFF_REQ__SHIFT 0x2
560#define SDMA_POWER_GATING__SDMA_POWER_ON_REQ__SHIFT 0x3
561#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4
562#define SDMA_POWER_GATING__SDMA_POWER_OFF_CONDITION_MASK 0x00000001L
563#define SDMA_POWER_GATING__SDMA_POWER_ON_CONDITION_MASK 0x00000002L
564#define SDMA_POWER_GATING__SDMA_POWER_OFF_REQ_MASK 0x00000004L
565#define SDMA_POWER_GATING__SDMA_POWER_ON_REQ_MASK 0x00000008L
566#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L
567//SDMA_PGFSM_CONFIG
568#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
569#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
570#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
571#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
572#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
573#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc
574#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd
575#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
576#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
577#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL
578#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L
579#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L
580#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L
581#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L
582#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L
583#define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L
584#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L
585#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L
586//SDMA_PGFSM_WRITE
587#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0
588#define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL
589//SDMA_PGFSM_READ
590#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0
591#define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL
592//CC_SDMA_EDC_CONFIG
593#define CC_SDMA_EDC_CONFIG__WRITE_DIS__SHIFT 0x0
594#define CC_SDMA_EDC_CONFIG__DIS_EDC__SHIFT 0x1
595#define CC_SDMA_EDC_CONFIG__WRITE_DIS_MASK 0x00000001L
596#define CC_SDMA_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
597//SDMA_BA_THRESHOLD
598#define SDMA_BA_THRESHOLD__READ_THRES__SHIFT 0x0
599#define SDMA_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
600#define SDMA_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL
601#define SDMA_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L
602//SDMA_ID
603#define SDMA_ID__DEVICE_ID__SHIFT 0x0
604#define SDMA_ID__DEVICE_ID_MASK 0x000000FFL
605//SDMA_VERSION
606#define SDMA_VERSION__MINVER__SHIFT 0x0
607#define SDMA_VERSION__MAJVER__SHIFT 0x8
608#define SDMA_VERSION__REV__SHIFT 0x10
609#define SDMA_VERSION__MINVER_MASK 0x0000007FL
610#define SDMA_VERSION__MAJVER_MASK 0x00007F00L
611#define SDMA_VERSION__REV_MASK 0x003F0000L
612//SDMA_EDC_COUNTER
613#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x0
614#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x2
615#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x4
616#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0x6
617#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0x8
618#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xa
619#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xc
620#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe
621#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0x10
622#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x12
623#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x14
624#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x16
625#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x18
626#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x1a
627#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x1c
628#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x1e
629#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000003L
630#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x0000000CL
631#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000030L
632#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x000000C0L
633#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000300L
634#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00000C00L
635#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00003000L
636#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x0000C000L
637#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00030000L
638#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x000C0000L
639#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00300000L
640#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00C00000L
641#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x03000000L
642#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x0C000000L
643#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x30000000L
644#define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0xC0000000L
645//SDMA_EDC_COUNTER2
646#define SDMA_EDC_COUNTER2__SDMA_UCODE_BUF_SED__SHIFT 0x0
647#define SDMA_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED__SHIFT 0x2
648#define SDMA_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED__SHIFT 0x4
649#define SDMA_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x6
650#define SDMA_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x8
651#define SDMA_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED__SHIFT 0xa
652#define SDMA_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED__SHIFT 0xc
653#define SDMA_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED__SHIFT 0xe
654#define SDMA_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10
655#define SDMA_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED__SHIFT 0x12
656#define SDMA_EDC_COUNTER2__SDMA_UCODE_BUF_SED_MASK 0x00000003L
657#define SDMA_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED_MASK 0x0000000CL
658#define SDMA_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED_MASK 0x00000030L
659#define SDMA_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED_MASK 0x000000C0L
660#define SDMA_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000300L
661#define SDMA_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED_MASK 0x00000C00L
662#define SDMA_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED_MASK 0x00003000L
663#define SDMA_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED_MASK 0x0000C000L
664#define SDMA_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00030000L
665#define SDMA_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED_MASK 0x000C0000L
666//SDMA_STATUS2_REG
667#define SDMA_STATUS2_REG__ID__SHIFT 0x0
668#define SDMA_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3
669#define SDMA_STATUS2_REG__CMD_OP__SHIFT 0x10
670#define SDMA_STATUS2_REG__ID_MASK 0x00000007L
671#define SDMA_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L
672#define SDMA_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L
673//SDMA_ATOMIC_CNTL
674#define SDMA_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
675#define SDMA_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f
676#define SDMA_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL
677#define SDMA_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L
678//SDMA_ATOMIC_PREOP_LO
679#define SDMA_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
680#define SDMA_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL
681//SDMA_ATOMIC_PREOP_HI
682#define SDMA_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
683#define SDMA_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL
684//SDMA_UTCL1_CNTL
685#define SDMA_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0
686#define SDMA_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1
687#define SDMA_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb
688#define SDMA_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe
689#define SDMA_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18
690#define SDMA_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
691#define SDMA_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L
692#define SDMA_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL
693#define SDMA_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L
694#define SDMA_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L
695#define SDMA_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L
696#define SDMA_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L
697//SDMA_UTCL1_WATERMK
698#define SDMA_UTCL1_WATERMK__REQ_WATERMK__SHIFT 0x0
699#define SDMA_UTCL1_WATERMK__REQ_DEPTH__SHIFT 0x3
700#define SDMA_UTCL1_WATERMK__PAGE_WATERMK__SHIFT 0x5
701#define SDMA_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x8
702#define SDMA_UTCL1_WATERMK__RESERVED__SHIFT 0x10
703#define SDMA_UTCL1_WATERMK__REQ_WATERMK_MASK 0x00000007L
704#define SDMA_UTCL1_WATERMK__REQ_DEPTH_MASK 0x00000018L
705#define SDMA_UTCL1_WATERMK__PAGE_WATERMK_MASK 0x000000E0L
706#define SDMA_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x0000FF00L
707#define SDMA_UTCL1_WATERMK__RESERVED_MASK 0xFFFF0000L
708//SDMA_UTCL1_RD_STATUS
709#define SDMA_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
710#define SDMA_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
711#define SDMA_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
712#define SDMA_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
713#define SDMA_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
714#define SDMA_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
715#define SDMA_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
716#define SDMA_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
717#define SDMA_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
718#define SDMA_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
719#define SDMA_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
720#define SDMA_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
721#define SDMA_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
722#define SDMA_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
723#define SDMA_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
724#define SDMA_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
725#define SDMA_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
726#define SDMA_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
727#define SDMA_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12
728#define SDMA_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13
729#define SDMA_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14
730#define SDMA_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15
731#define SDMA_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16
732#define SDMA_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a
733#define SDMA_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
734#define SDMA_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e
735#define SDMA_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f
736#define SDMA_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
737#define SDMA_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
738#define SDMA_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
739#define SDMA_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
740#define SDMA_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
741#define SDMA_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
742#define SDMA_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
743#define SDMA_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
744#define SDMA_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
745#define SDMA_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
746#define SDMA_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
747#define SDMA_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
748#define SDMA_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
749#define SDMA_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
750#define SDMA_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
751#define SDMA_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
752#define SDMA_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
753#define SDMA_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
754#define SDMA_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L
755#define SDMA_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L
756#define SDMA_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L
757#define SDMA_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L
758#define SDMA_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L
759#define SDMA_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L
760#define SDMA_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L
761#define SDMA_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L
762#define SDMA_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L
763//SDMA_UTCL1_WR_STATUS
764#define SDMA_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
765#define SDMA_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
766#define SDMA_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
767#define SDMA_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
768#define SDMA_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
769#define SDMA_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
770#define SDMA_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
771#define SDMA_UTCL1_WR_STATUS__REDO_ARR_EMPTY__SHIFT 0x7
772#define SDMA_UTCL1_WR_STATUS__RESERVED_8__SHIFT 0x8
773#define SDMA_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
774#define SDMA_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
775#define SDMA_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
776#define SDMA_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
777#define SDMA_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
778#define SDMA_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
779#define SDMA_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
780#define SDMA_UTCL1_WR_STATUS__REDO_ARR_FULL__SHIFT 0x10
781#define SDMA_UTCL1_WR_STATUS__RESERVED_17__SHIFT 0x11
782#define SDMA_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12
783#define SDMA_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13
784#define SDMA_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14
785#define SDMA_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15
786#define SDMA_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16
787#define SDMA_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19
788#define SDMA_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c
789#define SDMA_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
790#define SDMA_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e
791#define SDMA_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f
792#define SDMA_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
793#define SDMA_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
794#define SDMA_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
795#define SDMA_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
796#define SDMA_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
797#define SDMA_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
798#define SDMA_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
799#define SDMA_UTCL1_WR_STATUS__REDO_ARR_EMPTY_MASK 0x00000080L
800#define SDMA_UTCL1_WR_STATUS__RESERVED_8_MASK 0x00000100L
801#define SDMA_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
802#define SDMA_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
803#define SDMA_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
804#define SDMA_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
805#define SDMA_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
806#define SDMA_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
807#define SDMA_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
808#define SDMA_UTCL1_WR_STATUS__REDO_ARR_FULL_MASK 0x00010000L
809#define SDMA_UTCL1_WR_STATUS__RESERVED_17_MASK 0x00020000L
810#define SDMA_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L
811#define SDMA_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L
812#define SDMA_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L
813#define SDMA_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L
814#define SDMA_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L
815#define SDMA_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L
816#define SDMA_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L
817#define SDMA_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L
818#define SDMA_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L
819#define SDMA_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L
820//SDMA_UTCL1_INV0
821#define SDMA_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0
822#define SDMA_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1
823#define SDMA_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2
824#define SDMA_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3
825#define SDMA_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4
826#define SDMA_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5
827#define SDMA_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6
828#define SDMA_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7
829#define SDMA_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8
830#define SDMA_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9
831#define SDMA_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa
832#define SDMA_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb
833#define SDMA_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc
834#define SDMA_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c
835#define SDMA_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L
836#define SDMA_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L
837#define SDMA_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L
838#define SDMA_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L
839#define SDMA_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L
840#define SDMA_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L
841#define SDMA_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L
842#define SDMA_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L
843#define SDMA_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L
844#define SDMA_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L
845#define SDMA_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L
846#define SDMA_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L
847#define SDMA_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L
848#define SDMA_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L
849//SDMA_UTCL1_INV1
850#define SDMA_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0
851#define SDMA_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL
852//SDMA_UTCL1_INV2
853#define SDMA_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0
854#define SDMA_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL
855//SDMA_UTCL1_RD_XNACK0
856#define SDMA_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
857#define SDMA_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
858//SDMA_UTCL1_RD_XNACK1
859#define SDMA_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
860#define SDMA_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4
861#define SDMA_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8
862#define SDMA_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a
863#define SDMA_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
864#define SDMA_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L
865#define SDMA_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
866#define SDMA_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L
867//SDMA_UTCL1_WR_XNACK0
868#define SDMA_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
869#define SDMA_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
870//SDMA_UTCL1_WR_XNACK1
871#define SDMA_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
872#define SDMA_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4
873#define SDMA_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8
874#define SDMA_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a
875#define SDMA_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
876#define SDMA_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L
877#define SDMA_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
878#define SDMA_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L
879//SDMA_UTCL1_TIMEOUT
880#define SDMA_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0
881#define SDMA_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10
882#define SDMA_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL
883#define SDMA_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L
884//SDMA_UTCL1_PAGE
885#define SDMA_UTCL1_PAGE__VM_HOLE__SHIFT 0x0
886#define SDMA_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1
887#define SDMA_UTCL1_PAGE__TMZ_ENABLE__SHIFT 0x5
888#define SDMA_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6
889#define SDMA_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9
890#define SDMA_UTCL1_PAGE__LLC_NOALLOC__SHIFT 0xa
891#define SDMA_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L
892#define SDMA_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL
893#define SDMA_UTCL1_PAGE__TMZ_ENABLE_MASK 0x00000020L
894#define SDMA_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L
895#define SDMA_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L
896#define SDMA_UTCL1_PAGE__LLC_NOALLOC_MASK 0x00000400L
897//SDMA_POWER_CNTL_IDLE
898#define SDMA_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0
899#define SDMA_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10
900#define SDMA_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18
901#define SDMA_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL
902#define SDMA_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L
903#define SDMA_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L
904//SDMA_RELAX_ORDERING_LUT
905#define SDMA_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0
906#define SDMA_RELAX_ORDERING_LUT__COPY__SHIFT 0x1
907#define SDMA_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2
908#define SDMA_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3
909#define SDMA_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4
910#define SDMA_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5
911#define SDMA_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6
912#define SDMA_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8
913#define SDMA_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9
914#define SDMA_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
915#define SDMA_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb
916#define SDMA_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc
917#define SDMA_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd
918#define SDMA_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe
919#define SDMA_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b
920#define SDMA_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c
921#define SDMA_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
922#define SDMA_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e
923#define SDMA_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f
924#define SDMA_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L
925#define SDMA_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L
926#define SDMA_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L
927#define SDMA_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L
928#define SDMA_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L
929#define SDMA_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L
930#define SDMA_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L
931#define SDMA_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L
932#define SDMA_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L
933#define SDMA_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L
934#define SDMA_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L
935#define SDMA_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L
936#define SDMA_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L
937#define SDMA_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L
938#define SDMA_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L
939#define SDMA_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L
940#define SDMA_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L
941#define SDMA_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L
942#define SDMA_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L
943//SDMA_CHICKEN_BITS_2
944#define SDMA_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0
945#define SDMA_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x4
946#define SDMA_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL
947#define SDMA_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00000010L
948//SDMA_STATUS3_REG
949#define SDMA_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0
950#define SDMA_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10
951#define SDMA_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14
952#define SDMA_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15
953#define SDMA_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16
954#define SDMA_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL
955#define SDMA_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L
956#define SDMA_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L
957#define SDMA_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L
958#define SDMA_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L
959//SDMA_PHYSICAL_ADDR_LO
960#define SDMA_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0
961#define SDMA_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1
962#define SDMA_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2
963#define SDMA_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc
964#define SDMA_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L
965#define SDMA_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L
966#define SDMA_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L
967#define SDMA_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L
968//SDMA_PHYSICAL_ADDR_HI
969#define SDMA_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0
970#define SDMA_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL
971//SDMA_PHASE2_QUANTUM
972#define SDMA_PHASE2_QUANTUM__UNIT__SHIFT 0x0
973#define SDMA_PHASE2_QUANTUM__VALUE__SHIFT 0x8
974#define SDMA_PHASE2_QUANTUM__PREFER__SHIFT 0x1e
975#define SDMA_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL
976#define SDMA_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L
977#define SDMA_PHASE2_QUANTUM__PREFER_MASK 0x40000000L
978//SDMA_ERROR_LOG
979#define SDMA_ERROR_LOG__OVERRIDE__SHIFT 0x0
980#define SDMA_ERROR_LOG__STATUS__SHIFT 0x10
981#define SDMA_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL
982#define SDMA_ERROR_LOG__STATUS_MASK 0xFFFF0000L
983//SDMA_PUB_DUMMY_REG0
984#define SDMA_PUB_DUMMY_REG0__VALUE__SHIFT 0x0
985#define SDMA_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL
986//SDMA_PUB_DUMMY_REG1
987#define SDMA_PUB_DUMMY_REG1__VALUE__SHIFT 0x0
988#define SDMA_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL
989//SDMA_PUB_DUMMY_REG2
990#define SDMA_PUB_DUMMY_REG2__VALUE__SHIFT 0x0
991#define SDMA_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL
992//SDMA_PUB_DUMMY_REG3
993#define SDMA_PUB_DUMMY_REG3__VALUE__SHIFT 0x0
994#define SDMA_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL
995//SDMA_F32_COUNTER
996#define SDMA_F32_COUNTER__VALUE__SHIFT 0x0
997#define SDMA_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL
998//SDMA_PERFCNT_PERFCOUNTER0_CFG
999#define SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
1000#define SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
1001#define SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
1002#define SDMA_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
1003#define SDMA_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
1004#define SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
1005#define SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
1006#define SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
1007#define SDMA_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
1008#define SDMA_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
1009//SDMA_PERFCNT_PERFCOUNTER1_CFG
1010#define SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
1011#define SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
1012#define SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
1013#define SDMA_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
1014#define SDMA_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
1015#define SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
1016#define SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
1017#define SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
1018#define SDMA_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
1019#define SDMA_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
1020//SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL
1021#define SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
1022#define SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
1023#define SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
1024#define SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
1025#define SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
1026#define SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
1027#define SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
1028#define SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
1029#define SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
1030#define SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
1031#define SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
1032#define SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
1033//SDMA_PERFCNT_MISC_CNTL
1034#define SDMA_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0
1035#define SDMA_PERFCNT_MISC_CNTL__MMHUB_REQ_EVENT_SELECT__SHIFT 0x10
1036#define SDMA_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL
1037#define SDMA_PERFCNT_MISC_CNTL__MMHUB_REQ_EVENT_SELECT_MASK 0x00010000L
1038//SDMA_PERFCNT_PERFCOUNTER_LO
1039#define SDMA_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
1040#define SDMA_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
1041//SDMA_PERFCNT_PERFCOUNTER_HI
1042#define SDMA_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
1043#define SDMA_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
1044#define SDMA_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
1045#define SDMA_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
1046//SDMA_CRD_CNTL
1047#define SDMA_CRD_CNTL__DRM_CREDIT__SHIFT 0x0
1048#define SDMA_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7
1049#define SDMA_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
1050#define SDMA_CRD_CNTL__DRM_CREDIT_MASK 0x0000007FL
1051#define SDMA_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L
1052#define SDMA_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L
1053//SDMA_GPU_IOV_VIOLATION_LOG
1054#define SDMA_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0
1055#define SDMA_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1
1056#define SDMA_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2
1057#define SDMA_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14
1058#define SDMA_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15
1059#define SDMA_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16
1060#define SDMA_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L
1061#define SDMA_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L
1062#define SDMA_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL
1063#define SDMA_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L
1064#define SDMA_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L
1065#define SDMA_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x03C00000L
1066//SDMA_ULV_CNTL
1067#define SDMA_ULV_CNTL__HYSTERESIS__SHIFT 0x0
1068#define SDMA_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b
1069#define SDMA_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c
1070#define SDMA_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
1071#define SDMA_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e
1072#define SDMA_ULV_CNTL__ULV_STATUS__SHIFT 0x1f
1073#define SDMA_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL
1074#define SDMA_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L
1075#define SDMA_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L
1076#define SDMA_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L
1077#define SDMA_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L
1078#define SDMA_ULV_CNTL__ULV_STATUS_MASK 0x80000000L
1079//SDMA_EA_DBIT_ADDR_DATA
1080#define SDMA_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0
1081#define SDMA_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL
1082//SDMA_EA_DBIT_ADDR_INDEX
1083#define SDMA_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0
1084#define SDMA_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L
1085//SDMA_GPU_IOV_VIOLATION_LOG2
1086#define SDMA_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0
1087#define SDMA_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL
1088//SDMA_STATUS4_REG
1089#define SDMA_STATUS4_REG__IDLE__SHIFT 0x0
1090#define SDMA_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2
1091#define SDMA_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3
1092#define SDMA_STATUS4_REG__MMHUB_RD_OUTSTANDING__SHIFT 0x4
1093#define SDMA_STATUS4_REG__MMHUB_WR_OUTSTANDING__SHIFT 0x5
1094#define SDMA_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x6
1095#define SDMA_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x7
1096#define SDMA_STATUS4_REG__REG_POLLING__SHIFT 0x8
1097#define SDMA_STATUS4_REG__MEM_POLLING__SHIFT 0x9
1098#define SDMA_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xa
1099#define SDMA_STATUS4_REG__UTCL2_WR_XNACK__SHIFT 0xc
1100#define SDMA_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0xe
1101#define SDMA_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x12
1102#define SDMA_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x13
1103#define SDMA_STATUS4_REG__VM_HOLE_STATUS__SHIFT 0x14
1104#define SDMA_STATUS4_REG__IDLE_MASK 0x00000001L
1105#define SDMA_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L
1106#define SDMA_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L
1107#define SDMA_STATUS4_REG__MMHUB_RD_OUTSTANDING_MASK 0x00000010L
1108#define SDMA_STATUS4_REG__MMHUB_WR_OUTSTANDING_MASK 0x00000020L
1109#define SDMA_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000040L
1110#define SDMA_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000080L
1111#define SDMA_STATUS4_REG__REG_POLLING_MASK 0x00000100L
1112#define SDMA_STATUS4_REG__MEM_POLLING_MASK 0x00000200L
1113#define SDMA_STATUS4_REG__UTCL2_RD_XNACK_MASK 0x00000C00L
1114#define SDMA_STATUS4_REG__UTCL2_WR_XNACK_MASK 0x00003000L
1115#define SDMA_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x0003C000L
1116#define SDMA_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00040000L
1117#define SDMA_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00080000L
1118#define SDMA_STATUS4_REG__VM_HOLE_STATUS_MASK 0x00100000L
1119//SDMA_SCRATCH_RAM_DATA
1120#define SDMA_SCRATCH_RAM_DATA__DATA__SHIFT 0x0
1121#define SDMA_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL
1122//SDMA_SCRATCH_RAM_ADDR
1123#define SDMA_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0
1124#define SDMA_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL
1125//SDMA_CE_CTRL
1126#define SDMA_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0
1127#define SDMA_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3
1128#define SDMA_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5
1129#define SDMA_CE_CTRL__RESERVED__SHIFT 0x8
1130#define SDMA_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L
1131#define SDMA_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L
1132#define SDMA_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L
1133#define SDMA_CE_CTRL__RESERVED_MASK 0xFFFFFF00L
1134//SDMA_RAS_STATUS
1135#define SDMA_RAS_STATUS__RB_FETCH_ECC__SHIFT 0x0
1136#define SDMA_RAS_STATUS__IB_FETCH_ECC__SHIFT 0x1
1137#define SDMA_RAS_STATUS__F32_DATA_ECC__SHIFT 0x2
1138#define SDMA_RAS_STATUS__WPTR_ATOMIC_ECC__SHIFT 0x3
1139#define SDMA_RAS_STATUS__COPY_DATA_ECC__SHIFT 0x4
1140#define SDMA_RAS_STATUS__SRAM_ECC__SHIFT 0x5
1141#define SDMA_RAS_STATUS__RB_FETCH_NACK_GEN_ERR__SHIFT 0x8
1142#define SDMA_RAS_STATUS__IB_FETCH_NACK_GEN_ERR__SHIFT 0x9
1143#define SDMA_RAS_STATUS__F32_DATA_NACK_GEN_ERR__SHIFT 0xa
1144#define SDMA_RAS_STATUS__COPY_DATA_NACK_GEN_ERR__SHIFT 0xb
1145#define SDMA_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR__SHIFT 0xc
1146#define SDMA_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR__SHIFT 0xd
1147#define SDMA_RAS_STATUS__ECC_PWRMGT_INT_BUSY__SHIFT 0xe
1148#define SDMA_RAS_STATUS__RB_FETCH_ECC_MASK 0x00000001L
1149#define SDMA_RAS_STATUS__IB_FETCH_ECC_MASK 0x00000002L
1150#define SDMA_RAS_STATUS__F32_DATA_ECC_MASK 0x00000004L
1151#define SDMA_RAS_STATUS__WPTR_ATOMIC_ECC_MASK 0x00000008L
1152#define SDMA_RAS_STATUS__COPY_DATA_ECC_MASK 0x00000010L
1153#define SDMA_RAS_STATUS__SRAM_ECC_MASK 0x00000020L
1154#define SDMA_RAS_STATUS__RB_FETCH_NACK_GEN_ERR_MASK 0x00000100L
1155#define SDMA_RAS_STATUS__IB_FETCH_NACK_GEN_ERR_MASK 0x00000200L
1156#define SDMA_RAS_STATUS__F32_DATA_NACK_GEN_ERR_MASK 0x00000400L
1157#define SDMA_RAS_STATUS__COPY_DATA_NACK_GEN_ERR_MASK 0x00000800L
1158#define SDMA_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR_MASK 0x00001000L
1159#define SDMA_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR_MASK 0x00002000L
1160#define SDMA_RAS_STATUS__ECC_PWRMGT_INT_BUSY_MASK 0x00004000L
1161//SDMA_CLK_STATUS
1162#define SDMA_CLK_STATUS__DYN_CLK__SHIFT 0x0
1163#define SDMA_CLK_STATUS__PTR_CLK__SHIFT 0x1
1164#define SDMA_CLK_STATUS__REG_CLK__SHIFT 0x2
1165#define SDMA_CLK_STATUS__F32_CLK__SHIFT 0x3
1166#define SDMA_CLK_STATUS__CE_CLK__SHIFT 0x4
1167#define SDMA_CLK_STATUS__PERF_CLK__SHIFT 0x5
1168#define SDMA_CLK_STATUS__DYN_CLK_MASK 0x00000001L
1169#define SDMA_CLK_STATUS__PTR_CLK_MASK 0x00000002L
1170#define SDMA_CLK_STATUS__REG_CLK_MASK 0x00000004L
1171#define SDMA_CLK_STATUS__F32_CLK_MASK 0x00000008L
1172#define SDMA_CLK_STATUS__CE_CLK_MASK 0x00000010L
1173#define SDMA_CLK_STATUS__PERF_CLK_MASK 0x00000020L
1174//SDMA_UE_ERR_STATUS_LO
1175#define SDMA_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
1176#define SDMA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1
1177#define SDMA_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2
1178#define SDMA_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
1179#define SDMA_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
1180#define SDMA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L
1181#define SDMA_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL
1182#define SDMA_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
1183//SDMA_UE_ERR_STATUS_HI
1184#define SDMA_UE_ERR_STATUS_HI__ECC__SHIFT 0x0
1185#define SDMA_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1
1186#define SDMA_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
1187#define SDMA_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3
1188#define SDMA_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17
1189#define SDMA_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a
1190#define SDMA_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d
1191#define SDMA_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L
1192#define SDMA_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L
1193#define SDMA_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
1194#define SDMA_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L
1195#define SDMA_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L
1196#define SDMA_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L
1197#define SDMA_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L
1198//SDMA_POWER_CNTL
1199#define SDMA_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0
1200#define SDMA_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1
1201#define SDMA_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2
1202#define SDMA_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3
1203#define SDMA_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
1204#define SDMA_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
1205#define SDMA_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
1206#define SDMA_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
1207#define SDMA_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
1208#define SDMA_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a
1209#define SDMA_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L
1210#define SDMA_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L
1211#define SDMA_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L
1212#define SDMA_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
1213#define SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L
1214#define SDMA_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L
1215#define SDMA_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L
1216#define SDMA_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L
1217#define SDMA_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L
1218#define SDMA_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
1219//SDMA_CLK_CTRL
1220#define SDMA_CLK_CTRL__ON_DELAY__SHIFT 0x0
1221#define SDMA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
1222#define SDMA_CLK_CTRL__RESERVED__SHIFT 0xc
1223#define SDMA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
1224#define SDMA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
1225#define SDMA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
1226#define SDMA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
1227#define SDMA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
1228#define SDMA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
1229#define SDMA_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
1230#define SDMA_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
1231#define SDMA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
1232#define SDMA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
1233#define SDMA_CLK_CTRL__RESERVED_MASK 0x00FFF000L
1234#define SDMA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
1235#define SDMA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
1236#define SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
1237#define SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
1238#define SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
1239#define SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
1240#define SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
1241#define SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
1242//SDMA_CNTL
1243#define SDMA_CNTL__TRAP_ENABLE__SHIFT 0x0
1244#define SDMA_CNTL__UTC_L1_ENABLE__SHIFT 0x1
1245#define SDMA_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
1246#define SDMA_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
1247#define SDMA_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
1248#define SDMA_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
1249#define SDMA_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x6
1250#define SDMA_CNTL__REG_WRITE_PROTECT_INT_ENABLE__SHIFT 0x7
1251#define SDMA_CNTL__INVALID_DOORBELL_INT_ENABLE__SHIFT 0x8
1252#define SDMA_CNTL__VM_HOLE_INT_ENABLE__SHIFT 0x9
1253#define SDMA_CNTL__DRAM_ECC_INT_ENABLE__SHIFT 0xa
1254#define SDMA_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE__SHIFT 0xb
1255#define SDMA_CNTL__PAGE_NULL_INT_ENABLE__SHIFT 0xc
1256#define SDMA_CNTL__PAGE_FAULT_INT_ENABLE__SHIFT 0xd
1257#define SDMA_CNTL__NACK_GEN_ERR_INT_ENABLE__SHIFT 0xe
1258#define SDMA_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
1259#define SDMA_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
1260#define SDMA_CNTL__DRM_RESTORE_ENABLE__SHIFT 0x13
1261#define SDMA_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
1262#define SDMA_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
1263#define SDMA_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
1264#define SDMA_CNTL__RB_PREEMPT_INT_ENABLE__SHIFT 0x1f
1265#define SDMA_CNTL__TRAP_ENABLE_MASK 0x00000001L
1266#define SDMA_CNTL__UTC_L1_ENABLE_MASK 0x00000002L
1267#define SDMA_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L
1268#define SDMA_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L
1269#define SDMA_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L
1270#define SDMA_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L
1271#define SDMA_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000040L
1272#define SDMA_CNTL__REG_WRITE_PROTECT_INT_ENABLE_MASK 0x00000080L
1273#define SDMA_CNTL__INVALID_DOORBELL_INT_ENABLE_MASK 0x00000100L
1274#define SDMA_CNTL__VM_HOLE_INT_ENABLE_MASK 0x00000200L
1275#define SDMA_CNTL__DRAM_ECC_INT_ENABLE_MASK 0x00000400L
1276#define SDMA_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE_MASK 0x00000800L
1277#define SDMA_CNTL__PAGE_NULL_INT_ENABLE_MASK 0x00001000L
1278#define SDMA_CNTL__PAGE_FAULT_INT_ENABLE_MASK 0x00002000L
1279#define SDMA_CNTL__NACK_GEN_ERR_INT_ENABLE_MASK 0x00004000L
1280#define SDMA_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L
1281#define SDMA_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L
1282#define SDMA_CNTL__DRM_RESTORE_ENABLE_MASK 0x00080000L
1283#define SDMA_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L
1284#define SDMA_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L
1285#define SDMA_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L
1286#define SDMA_CNTL__RB_PREEMPT_INT_ENABLE_MASK 0x80000000L
1287//SDMA_CHICKEN_BITS
1288#define SDMA_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
1289#define SDMA_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
1290#define SDMA_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
1291#define SDMA_CHICKEN_BITS__F32_MGCG_ENABLE__SHIFT 0x3
1292#define SDMA_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8
1293#define SDMA_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
1294#define SDMA_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
1295#define SDMA_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11
1296#define SDMA_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
1297#define SDMA_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
1298#define SDMA_CHICKEN_BITS__SRAM_FGCG_ENABLE__SHIFT 0x1a
1299#define SDMA_CHICKEN_BITS__RESERVED__SHIFT 0x1b
1300#define SDMA_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L
1301#define SDMA_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L
1302#define SDMA_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L
1303#define SDMA_CHICKEN_BITS__F32_MGCG_ENABLE_MASK 0x00000008L
1304#define SDMA_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L
1305#define SDMA_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L
1306#define SDMA_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L
1307#define SDMA_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L
1308#define SDMA_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L
1309#define SDMA_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L
1310#define SDMA_CHICKEN_BITS__SRAM_FGCG_ENABLE_MASK 0x04000000L
1311#define SDMA_CHICKEN_BITS__RESERVED_MASK 0xF8000000L
1312//SDMA_GB_ADDR_CONFIG
1313#define SDMA_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
1314#define SDMA_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
1315#define SDMA_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
1316#define SDMA_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
1317#define SDMA_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
1318#define SDMA_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
1319#define SDMA_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
1320#define SDMA_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
1321#define SDMA_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
1322#define SDMA_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
1323//SDMA_GB_ADDR_CONFIG_READ
1324#define SDMA_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
1325#define SDMA_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
1326#define SDMA_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8
1327#define SDMA_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc
1328#define SDMA_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
1329#define SDMA_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
1330#define SDMA_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
1331#define SDMA_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
1332#define SDMA_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L
1333#define SDMA_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
1334//SDMA_GFX_RB_CNTL
1335#define SDMA_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
1336#define SDMA_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
1337#define SDMA_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
1338#define SDMA_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
1339#define SDMA_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
1340#define SDMA_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
1341#define SDMA_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
1342#define SDMA_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
1343#define SDMA_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L
1344#define SDMA_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL
1345#define SDMA_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
1346#define SDMA_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
1347#define SDMA_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
1348#define SDMA_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
1349#define SDMA_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L
1350#define SDMA_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L
1351//SDMA_GFX_RB_BASE
1352#define SDMA_GFX_RB_BASE__ADDR__SHIFT 0x0
1353#define SDMA_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL
1354//SDMA_GFX_RB_BASE_HI
1355#define SDMA_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
1356#define SDMA_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
1357//SDMA_GFX_RB_RPTR
1358#define SDMA_GFX_RB_RPTR__OFFSET__SHIFT 0x0
1359#define SDMA_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
1360//SDMA_GFX_RB_RPTR_HI
1361#define SDMA_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0
1362#define SDMA_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
1363//SDMA_GFX_RB_WPTR
1364#define SDMA_GFX_RB_WPTR__OFFSET__SHIFT 0x0
1365#define SDMA_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
1366//SDMA_GFX_RB_WPTR_HI
1367#define SDMA_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0
1368#define SDMA_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
1369//SDMA_GFX_RB_WPTR_POLL_CNTL
1370#define SDMA_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
1371#define SDMA_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
1372#define SDMA_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
1373#define SDMA_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
1374#define SDMA_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
1375#define SDMA_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
1376#define SDMA_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
1377#define SDMA_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
1378#define SDMA_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
1379#define SDMA_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
1380//SDMA_GFX_RB_RPTR_ADDR_HI
1381#define SDMA_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
1382#define SDMA_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
1383//SDMA_GFX_RB_RPTR_ADDR_LO
1384#define SDMA_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
1385#define SDMA_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1386#define SDMA_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
1387#define SDMA_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
1388//SDMA_GFX_IB_CNTL
1389#define SDMA_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
1390#define SDMA_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
1391#define SDMA_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
1392#define SDMA_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
1393#define SDMA_GFX_IB_CNTL__IB_PRIV__SHIFT 0x1f
1394#define SDMA_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L
1395#define SDMA_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
1396#define SDMA_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
1397#define SDMA_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L
1398#define SDMA_GFX_IB_CNTL__IB_PRIV_MASK 0x80000000L
1399//SDMA_GFX_IB_RPTR
1400#define SDMA_GFX_IB_RPTR__OFFSET__SHIFT 0x2
1401#define SDMA_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL
1402//SDMA_GFX_IB_OFFSET
1403#define SDMA_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
1404#define SDMA_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
1405//SDMA_GFX_IB_BASE_LO
1406#define SDMA_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
1407#define SDMA_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
1408//SDMA_GFX_IB_BASE_HI
1409#define SDMA_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
1410#define SDMA_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
1411//SDMA_GFX_IB_SIZE
1412#define SDMA_GFX_IB_SIZE__SIZE__SHIFT 0x0
1413#define SDMA_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL
1414//SDMA_GFX_SKIP_CNTL
1415#define SDMA_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
1416#define SDMA_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
1417//SDMA_GFX_CONTEXT_STATUS
1418#define SDMA_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
1419#define SDMA_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
1420#define SDMA_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
1421#define SDMA_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
1422#define SDMA_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
1423#define SDMA_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
1424#define SDMA_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
1425#define SDMA_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1426#define SDMA_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
1427#define SDMA_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L
1428#define SDMA_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
1429#define SDMA_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
1430#define SDMA_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
1431#define SDMA_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
1432#define SDMA_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
1433#define SDMA_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
1434//SDMA_GFX_DOORBELL
1435#define SDMA_GFX_DOORBELL__ENABLE__SHIFT 0x1c
1436#define SDMA_GFX_DOORBELL__CAPTURED__SHIFT 0x1e
1437#define SDMA_GFX_DOORBELL__ENABLE_MASK 0x10000000L
1438#define SDMA_GFX_DOORBELL__CAPTURED_MASK 0x40000000L
1439//SDMA_GFX_CONTEXT_CNTL
1440#define SDMA_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
1441#define SDMA_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18
1442#define SDMA_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L
1443#define SDMA_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0x0F000000L
1444//SDMA_GFX_STATUS
1445#define SDMA_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
1446#define SDMA_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
1447#define SDMA_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
1448#define SDMA_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
1449//SDMA_GFX_DOORBELL_LOG
1450#define SDMA_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
1451#define SDMA_GFX_DOORBELL_LOG__DATA__SHIFT 0x2
1452#define SDMA_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
1453#define SDMA_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
1454//SDMA_GFX_WATERMARK
1455#define SDMA_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
1456#define SDMA_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
1457#define SDMA_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
1458#define SDMA_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
1459//SDMA_GFX_DOORBELL_OFFSET
1460#define SDMA_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
1461#define SDMA_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
1462//SDMA_GFX_CSA_ADDR_LO
1463#define SDMA_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
1464#define SDMA_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
1465//SDMA_GFX_CSA_ADDR_HI
1466#define SDMA_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
1467#define SDMA_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
1468//SDMA_GFX_IB_SUB_REMAIN
1469#define SDMA_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
1470#define SDMA_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
1471//SDMA_GFX_PREEMPT
1472#define SDMA_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
1473#define SDMA_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L
1474//SDMA_GFX_DUMMY_REG
1475#define SDMA_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
1476#define SDMA_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
1477//SDMA_GFX_RB_WPTR_POLL_ADDR_HI
1478#define SDMA_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
1479#define SDMA_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
1480//SDMA_GFX_RB_WPTR_POLL_ADDR_LO
1481#define SDMA_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1482#define SDMA_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
1483//SDMA_GFX_RB_AQL_CNTL
1484#define SDMA_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
1485#define SDMA_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
1486#define SDMA_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
1487#define SDMA_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
1488#define SDMA_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
1489#define SDMA_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
1490//SDMA_GFX_MINOR_PTR_UPDATE
1491#define SDMA_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
1492#define SDMA_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
1493//SDMA_GFX_MIDCMD_DATA0
1494#define SDMA_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0
1495#define SDMA_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
1496//SDMA_GFX_MIDCMD_DATA1
1497#define SDMA_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0
1498#define SDMA_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
1499//SDMA_GFX_MIDCMD_DATA2
1500#define SDMA_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0
1501#define SDMA_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
1502//SDMA_GFX_MIDCMD_DATA3
1503#define SDMA_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0
1504#define SDMA_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
1505//SDMA_GFX_MIDCMD_DATA4
1506#define SDMA_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0
1507#define SDMA_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
1508//SDMA_GFX_MIDCMD_DATA5
1509#define SDMA_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0
1510#define SDMA_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
1511//SDMA_GFX_MIDCMD_DATA6
1512#define SDMA_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0
1513#define SDMA_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
1514//SDMA_GFX_MIDCMD_DATA7
1515#define SDMA_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0
1516#define SDMA_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
1517//SDMA_GFX_MIDCMD_DATA8
1518#define SDMA_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0
1519#define SDMA_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
1520//SDMA_GFX_MIDCMD_DATA9
1521#define SDMA_GFX_MIDCMD_DATA9__DATA9__SHIFT 0x0
1522#define SDMA_GFX_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
1523//SDMA_GFX_MIDCMD_DATA10
1524#define SDMA_GFX_MIDCMD_DATA10__DATA10__SHIFT 0x0
1525#define SDMA_GFX_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
1526//SDMA_GFX_MIDCMD_CNTL
1527#define SDMA_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
1528#define SDMA_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
1529#define SDMA_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
1530#define SDMA_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
1531#define SDMA_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
1532#define SDMA_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
1533#define SDMA_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
1534#define SDMA_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
1535//SDMA_PAGE_RB_CNTL
1536#define SDMA_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0
1537#define SDMA_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1
1538#define SDMA_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
1539#define SDMA_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
1540#define SDMA_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
1541#define SDMA_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
1542#define SDMA_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17
1543#define SDMA_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18
1544#define SDMA_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L
1545#define SDMA_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL
1546#define SDMA_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
1547#define SDMA_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
1548#define SDMA_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
1549#define SDMA_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
1550#define SDMA_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L
1551#define SDMA_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L
1552//SDMA_PAGE_RB_BASE
1553#define SDMA_PAGE_RB_BASE__ADDR__SHIFT 0x0
1554#define SDMA_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL
1555//SDMA_PAGE_RB_BASE_HI
1556#define SDMA_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0
1557#define SDMA_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
1558//SDMA_PAGE_RB_RPTR
1559#define SDMA_PAGE_RB_RPTR__OFFSET__SHIFT 0x0
1560#define SDMA_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
1561//SDMA_PAGE_RB_RPTR_HI
1562#define SDMA_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0
1563#define SDMA_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
1564//SDMA_PAGE_RB_WPTR
1565#define SDMA_PAGE_RB_WPTR__OFFSET__SHIFT 0x0
1566#define SDMA_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
1567//SDMA_PAGE_RB_WPTR_HI
1568#define SDMA_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0
1569#define SDMA_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
1570//SDMA_PAGE_RB_WPTR_POLL_CNTL
1571#define SDMA_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
1572#define SDMA_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
1573#define SDMA_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
1574#define SDMA_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
1575#define SDMA_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
1576#define SDMA_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
1577#define SDMA_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
1578#define SDMA_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
1579#define SDMA_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
1580#define SDMA_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
1581//SDMA_PAGE_RB_RPTR_ADDR_HI
1582#define SDMA_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
1583#define SDMA_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
1584//SDMA_PAGE_RB_RPTR_ADDR_LO
1585#define SDMA_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
1586#define SDMA_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1587#define SDMA_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
1588#define SDMA_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
1589//SDMA_PAGE_IB_CNTL
1590#define SDMA_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0
1591#define SDMA_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
1592#define SDMA_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
1593#define SDMA_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10
1594#define SDMA_PAGE_IB_CNTL__IB_PRIV__SHIFT 0x1f
1595#define SDMA_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L
1596#define SDMA_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
1597#define SDMA_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
1598#define SDMA_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L
1599#define SDMA_PAGE_IB_CNTL__IB_PRIV_MASK 0x80000000L
1600//SDMA_PAGE_IB_RPTR
1601#define SDMA_PAGE_IB_RPTR__OFFSET__SHIFT 0x2
1602#define SDMA_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL
1603//SDMA_PAGE_IB_OFFSET
1604#define SDMA_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2
1605#define SDMA_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
1606//SDMA_PAGE_IB_BASE_LO
1607#define SDMA_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5
1608#define SDMA_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
1609//SDMA_PAGE_IB_BASE_HI
1610#define SDMA_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0
1611#define SDMA_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
1612//SDMA_PAGE_IB_SIZE
1613#define SDMA_PAGE_IB_SIZE__SIZE__SHIFT 0x0
1614#define SDMA_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL
1615//SDMA_PAGE_SKIP_CNTL
1616#define SDMA_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
1617#define SDMA_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
1618//SDMA_PAGE_CONTEXT_STATUS
1619#define SDMA_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0
1620#define SDMA_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2
1621#define SDMA_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
1622#define SDMA_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
1623#define SDMA_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
1624#define SDMA_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
1625#define SDMA_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
1626#define SDMA_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1627#define SDMA_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
1628#define SDMA_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L
1629#define SDMA_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
1630#define SDMA_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
1631#define SDMA_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
1632#define SDMA_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
1633#define SDMA_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
1634#define SDMA_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
1635//SDMA_PAGE_DOORBELL
1636#define SDMA_PAGE_DOORBELL__ENABLE__SHIFT 0x1c
1637#define SDMA_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e
1638#define SDMA_PAGE_DOORBELL__ENABLE_MASK 0x10000000L
1639#define SDMA_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L
1640//SDMA_PAGE_STATUS
1641#define SDMA_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
1642#define SDMA_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
1643#define SDMA_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
1644#define SDMA_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
1645//SDMA_PAGE_DOORBELL_LOG
1646#define SDMA_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
1647#define SDMA_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2
1648#define SDMA_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
1649#define SDMA_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
1650//SDMA_PAGE_WATERMARK
1651#define SDMA_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
1652#define SDMA_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
1653#define SDMA_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
1654#define SDMA_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
1655//SDMA_PAGE_DOORBELL_OFFSET
1656#define SDMA_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
1657#define SDMA_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
1658//SDMA_PAGE_CSA_ADDR_LO
1659#define SDMA_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2
1660#define SDMA_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
1661//SDMA_PAGE_CSA_ADDR_HI
1662#define SDMA_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0
1663#define SDMA_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
1664//SDMA_PAGE_IB_SUB_REMAIN
1665#define SDMA_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0
1666#define SDMA_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
1667//SDMA_PAGE_PREEMPT
1668#define SDMA_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0
1669#define SDMA_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L
1670//SDMA_PAGE_DUMMY_REG
1671#define SDMA_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0
1672#define SDMA_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
1673//SDMA_PAGE_RB_WPTR_POLL_ADDR_HI
1674#define SDMA_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
1675#define SDMA_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
1676//SDMA_PAGE_RB_WPTR_POLL_ADDR_LO
1677#define SDMA_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1678#define SDMA_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
1679//SDMA_PAGE_RB_AQL_CNTL
1680#define SDMA_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
1681#define SDMA_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
1682#define SDMA_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
1683#define SDMA_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
1684#define SDMA_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
1685#define SDMA_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
1686//SDMA_PAGE_MINOR_PTR_UPDATE
1687#define SDMA_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
1688#define SDMA_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
1689//SDMA_PAGE_MIDCMD_DATA0
1690#define SDMA_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0
1691#define SDMA_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
1692//SDMA_PAGE_MIDCMD_DATA1
1693#define SDMA_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0
1694#define SDMA_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
1695//SDMA_PAGE_MIDCMD_DATA2
1696#define SDMA_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0
1697#define SDMA_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
1698//SDMA_PAGE_MIDCMD_DATA3
1699#define SDMA_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0
1700#define SDMA_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
1701//SDMA_PAGE_MIDCMD_DATA4
1702#define SDMA_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0
1703#define SDMA_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
1704//SDMA_PAGE_MIDCMD_DATA5
1705#define SDMA_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0
1706#define SDMA_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
1707//SDMA_PAGE_MIDCMD_DATA6
1708#define SDMA_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0
1709#define SDMA_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
1710//SDMA_PAGE_MIDCMD_DATA7
1711#define SDMA_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0
1712#define SDMA_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
1713//SDMA_PAGE_MIDCMD_DATA8
1714#define SDMA_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0
1715#define SDMA_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
1716//SDMA_PAGE_MIDCMD_DATA9
1717#define SDMA_PAGE_MIDCMD_DATA9__DATA9__SHIFT 0x0
1718#define SDMA_PAGE_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
1719//SDMA_PAGE_MIDCMD_DATA10
1720#define SDMA_PAGE_MIDCMD_DATA10__DATA10__SHIFT 0x0
1721#define SDMA_PAGE_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
1722//SDMA_PAGE_MIDCMD_CNTL
1723#define SDMA_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
1724#define SDMA_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
1725#define SDMA_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
1726#define SDMA_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
1727#define SDMA_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
1728#define SDMA_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
1729#define SDMA_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
1730#define SDMA_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
1731//SDMA_RLC0_RB_CNTL
1732#define SDMA_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
1733#define SDMA_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
1734#define SDMA_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
1735#define SDMA_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
1736#define SDMA_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
1737#define SDMA_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
1738#define SDMA_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
1739#define SDMA_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
1740#define SDMA_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L
1741#define SDMA_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL
1742#define SDMA_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
1743#define SDMA_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
1744#define SDMA_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
1745#define SDMA_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
1746#define SDMA_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L
1747#define SDMA_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L
1748//SDMA_RLC0_RB_BASE
1749#define SDMA_RLC0_RB_BASE__ADDR__SHIFT 0x0
1750#define SDMA_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL
1751//SDMA_RLC0_RB_BASE_HI
1752#define SDMA_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
1753#define SDMA_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
1754//SDMA_RLC0_RB_RPTR
1755#define SDMA_RLC0_RB_RPTR__OFFSET__SHIFT 0x0
1756#define SDMA_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
1757//SDMA_RLC0_RB_RPTR_HI
1758#define SDMA_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0
1759#define SDMA_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
1760//SDMA_RLC0_RB_WPTR
1761#define SDMA_RLC0_RB_WPTR__OFFSET__SHIFT 0x0
1762#define SDMA_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
1763//SDMA_RLC0_RB_WPTR_HI
1764#define SDMA_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0
1765#define SDMA_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
1766//SDMA_RLC0_RB_WPTR_POLL_CNTL
1767#define SDMA_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
1768#define SDMA_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
1769#define SDMA_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
1770#define SDMA_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
1771#define SDMA_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
1772#define SDMA_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
1773#define SDMA_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
1774#define SDMA_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
1775#define SDMA_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
1776#define SDMA_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
1777//SDMA_RLC0_RB_RPTR_ADDR_HI
1778#define SDMA_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
1779#define SDMA_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
1780//SDMA_RLC0_RB_RPTR_ADDR_LO
1781#define SDMA_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
1782#define SDMA_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1783#define SDMA_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
1784#define SDMA_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
1785//SDMA_RLC0_IB_CNTL
1786#define SDMA_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
1787#define SDMA_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
1788#define SDMA_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
1789#define SDMA_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
1790#define SDMA_RLC0_IB_CNTL__IB_PRIV__SHIFT 0x1f
1791#define SDMA_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L
1792#define SDMA_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
1793#define SDMA_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
1794#define SDMA_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L
1795#define SDMA_RLC0_IB_CNTL__IB_PRIV_MASK 0x80000000L
1796//SDMA_RLC0_IB_RPTR
1797#define SDMA_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
1798#define SDMA_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL
1799//SDMA_RLC0_IB_OFFSET
1800#define SDMA_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
1801#define SDMA_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
1802//SDMA_RLC0_IB_BASE_LO
1803#define SDMA_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
1804#define SDMA_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
1805//SDMA_RLC0_IB_BASE_HI
1806#define SDMA_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
1807#define SDMA_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
1808//SDMA_RLC0_IB_SIZE
1809#define SDMA_RLC0_IB_SIZE__SIZE__SHIFT 0x0
1810#define SDMA_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL
1811//SDMA_RLC0_SKIP_CNTL
1812#define SDMA_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
1813#define SDMA_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
1814//SDMA_RLC0_CONTEXT_STATUS
1815#define SDMA_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
1816#define SDMA_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
1817#define SDMA_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
1818#define SDMA_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
1819#define SDMA_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
1820#define SDMA_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
1821#define SDMA_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
1822#define SDMA_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1823#define SDMA_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
1824#define SDMA_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L
1825#define SDMA_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
1826#define SDMA_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
1827#define SDMA_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
1828#define SDMA_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
1829#define SDMA_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
1830#define SDMA_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
1831//SDMA_RLC0_DOORBELL
1832#define SDMA_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
1833#define SDMA_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
1834#define SDMA_RLC0_DOORBELL__ENABLE_MASK 0x10000000L
1835#define SDMA_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L
1836//SDMA_RLC0_STATUS
1837#define SDMA_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
1838#define SDMA_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
1839#define SDMA_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
1840#define SDMA_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
1841//SDMA_RLC0_DOORBELL_LOG
1842#define SDMA_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
1843#define SDMA_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
1844#define SDMA_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
1845#define SDMA_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
1846//SDMA_RLC0_WATERMARK
1847#define SDMA_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
1848#define SDMA_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
1849#define SDMA_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
1850#define SDMA_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
1851//SDMA_RLC0_DOORBELL_OFFSET
1852#define SDMA_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
1853#define SDMA_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
1854//SDMA_RLC0_CSA_ADDR_LO
1855#define SDMA_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
1856#define SDMA_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
1857//SDMA_RLC0_CSA_ADDR_HI
1858#define SDMA_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
1859#define SDMA_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
1860//SDMA_RLC0_IB_SUB_REMAIN
1861#define SDMA_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
1862#define SDMA_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
1863//SDMA_RLC0_PREEMPT
1864#define SDMA_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
1865#define SDMA_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L
1866//SDMA_RLC0_DUMMY_REG
1867#define SDMA_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
1868#define SDMA_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
1869//SDMA_RLC0_RB_WPTR_POLL_ADDR_HI
1870#define SDMA_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
1871#define SDMA_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
1872//SDMA_RLC0_RB_WPTR_POLL_ADDR_LO
1873#define SDMA_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1874#define SDMA_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
1875//SDMA_RLC0_RB_AQL_CNTL
1876#define SDMA_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
1877#define SDMA_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
1878#define SDMA_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
1879#define SDMA_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
1880#define SDMA_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
1881#define SDMA_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
1882//SDMA_RLC0_MINOR_PTR_UPDATE
1883#define SDMA_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
1884#define SDMA_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
1885//SDMA_RLC0_MIDCMD_DATA0
1886#define SDMA_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0
1887#define SDMA_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
1888//SDMA_RLC0_MIDCMD_DATA1
1889#define SDMA_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
1890#define SDMA_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
1891//SDMA_RLC0_MIDCMD_DATA2
1892#define SDMA_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0
1893#define SDMA_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
1894//SDMA_RLC0_MIDCMD_DATA3
1895#define SDMA_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0
1896#define SDMA_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
1897//SDMA_RLC0_MIDCMD_DATA4
1898#define SDMA_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0
1899#define SDMA_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
1900//SDMA_RLC0_MIDCMD_DATA5
1901#define SDMA_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0
1902#define SDMA_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
1903//SDMA_RLC0_MIDCMD_DATA6
1904#define SDMA_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0
1905#define SDMA_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
1906//SDMA_RLC0_MIDCMD_DATA7
1907#define SDMA_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0
1908#define SDMA_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
1909//SDMA_RLC0_MIDCMD_DATA8
1910#define SDMA_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0
1911#define SDMA_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
1912//SDMA_RLC0_MIDCMD_DATA9
1913#define SDMA_RLC0_MIDCMD_DATA9__DATA9__SHIFT 0x0
1914#define SDMA_RLC0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
1915//SDMA_RLC0_MIDCMD_DATA10
1916#define SDMA_RLC0_MIDCMD_DATA10__DATA10__SHIFT 0x0
1917#define SDMA_RLC0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
1918//SDMA_RLC0_MIDCMD_CNTL
1919#define SDMA_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
1920#define SDMA_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
1921#define SDMA_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
1922#define SDMA_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
1923#define SDMA_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
1924#define SDMA_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
1925#define SDMA_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
1926#define SDMA_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
1927//SDMA_RLC1_RB_CNTL
1928#define SDMA_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
1929#define SDMA_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
1930#define SDMA_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
1931#define SDMA_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
1932#define SDMA_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
1933#define SDMA_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
1934#define SDMA_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
1935#define SDMA_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
1936#define SDMA_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L
1937#define SDMA_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL
1938#define SDMA_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
1939#define SDMA_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
1940#define SDMA_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
1941#define SDMA_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
1942#define SDMA_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L
1943#define SDMA_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L
1944//SDMA_RLC1_RB_BASE
1945#define SDMA_RLC1_RB_BASE__ADDR__SHIFT 0x0
1946#define SDMA_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL
1947//SDMA_RLC1_RB_BASE_HI
1948#define SDMA_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
1949#define SDMA_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
1950//SDMA_RLC1_RB_RPTR
1951#define SDMA_RLC1_RB_RPTR__OFFSET__SHIFT 0x0
1952#define SDMA_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
1953//SDMA_RLC1_RB_RPTR_HI
1954#define SDMA_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0
1955#define SDMA_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
1956//SDMA_RLC1_RB_WPTR
1957#define SDMA_RLC1_RB_WPTR__OFFSET__SHIFT 0x0
1958#define SDMA_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
1959//SDMA_RLC1_RB_WPTR_HI
1960#define SDMA_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0
1961#define SDMA_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
1962//SDMA_RLC1_RB_WPTR_POLL_CNTL
1963#define SDMA_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
1964#define SDMA_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
1965#define SDMA_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
1966#define SDMA_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
1967#define SDMA_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
1968#define SDMA_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
1969#define SDMA_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
1970#define SDMA_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
1971#define SDMA_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
1972#define SDMA_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
1973//SDMA_RLC1_RB_RPTR_ADDR_HI
1974#define SDMA_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
1975#define SDMA_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
1976//SDMA_RLC1_RB_RPTR_ADDR_LO
1977#define SDMA_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
1978#define SDMA_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1979#define SDMA_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
1980#define SDMA_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
1981//SDMA_RLC1_IB_CNTL
1982#define SDMA_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
1983#define SDMA_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
1984#define SDMA_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
1985#define SDMA_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
1986#define SDMA_RLC1_IB_CNTL__IB_PRIV__SHIFT 0x1f
1987#define SDMA_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L
1988#define SDMA_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
1989#define SDMA_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
1990#define SDMA_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L
1991#define SDMA_RLC1_IB_CNTL__IB_PRIV_MASK 0x80000000L
1992//SDMA_RLC1_IB_RPTR
1993#define SDMA_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
1994#define SDMA_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL
1995//SDMA_RLC1_IB_OFFSET
1996#define SDMA_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
1997#define SDMA_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
1998//SDMA_RLC1_IB_BASE_LO
1999#define SDMA_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
2000#define SDMA_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
2001//SDMA_RLC1_IB_BASE_HI
2002#define SDMA_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
2003#define SDMA_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
2004//SDMA_RLC1_IB_SIZE
2005#define SDMA_RLC1_IB_SIZE__SIZE__SHIFT 0x0
2006#define SDMA_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL
2007//SDMA_RLC1_SKIP_CNTL
2008#define SDMA_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
2009#define SDMA_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
2010//SDMA_RLC1_CONTEXT_STATUS
2011#define SDMA_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
2012#define SDMA_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
2013#define SDMA_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
2014#define SDMA_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
2015#define SDMA_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
2016#define SDMA_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
2017#define SDMA_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
2018#define SDMA_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
2019#define SDMA_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
2020#define SDMA_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L
2021#define SDMA_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
2022#define SDMA_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
2023#define SDMA_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
2024#define SDMA_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
2025#define SDMA_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
2026#define SDMA_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
2027//SDMA_RLC1_DOORBELL
2028#define SDMA_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
2029#define SDMA_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
2030#define SDMA_RLC1_DOORBELL__ENABLE_MASK 0x10000000L
2031#define SDMA_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L
2032//SDMA_RLC1_STATUS
2033#define SDMA_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
2034#define SDMA_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
2035#define SDMA_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
2036#define SDMA_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
2037//SDMA_RLC1_DOORBELL_LOG
2038#define SDMA_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
2039#define SDMA_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
2040#define SDMA_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
2041#define SDMA_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
2042//SDMA_RLC1_WATERMARK
2043#define SDMA_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
2044#define SDMA_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
2045#define SDMA_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
2046#define SDMA_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
2047//SDMA_RLC1_DOORBELL_OFFSET
2048#define SDMA_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
2049#define SDMA_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
2050//SDMA_RLC1_CSA_ADDR_LO
2051#define SDMA_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
2052#define SDMA_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
2053//SDMA_RLC1_CSA_ADDR_HI
2054#define SDMA_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
2055#define SDMA_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
2056//SDMA_RLC1_IB_SUB_REMAIN
2057#define SDMA_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
2058#define SDMA_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
2059//SDMA_RLC1_PREEMPT
2060#define SDMA_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
2061#define SDMA_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L
2062//SDMA_RLC1_DUMMY_REG
2063#define SDMA_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
2064#define SDMA_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
2065//SDMA_RLC1_RB_WPTR_POLL_ADDR_HI
2066#define SDMA_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
2067#define SDMA_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
2068//SDMA_RLC1_RB_WPTR_POLL_ADDR_LO
2069#define SDMA_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
2070#define SDMA_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
2071//SDMA_RLC1_RB_AQL_CNTL
2072#define SDMA_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
2073#define SDMA_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
2074#define SDMA_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
2075#define SDMA_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
2076#define SDMA_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
2077#define SDMA_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
2078//SDMA_RLC1_MINOR_PTR_UPDATE
2079#define SDMA_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
2080#define SDMA_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
2081//SDMA_RLC1_MIDCMD_DATA0
2082#define SDMA_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0
2083#define SDMA_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
2084//SDMA_RLC1_MIDCMD_DATA1
2085#define SDMA_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0
2086#define SDMA_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
2087//SDMA_RLC1_MIDCMD_DATA2
2088#define SDMA_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0
2089#define SDMA_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
2090//SDMA_RLC1_MIDCMD_DATA3
2091#define SDMA_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0
2092#define SDMA_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
2093//SDMA_RLC1_MIDCMD_DATA4
2094#define SDMA_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0
2095#define SDMA_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
2096//SDMA_RLC1_MIDCMD_DATA5
2097#define SDMA_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0
2098#define SDMA_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
2099//SDMA_RLC1_MIDCMD_DATA6
2100#define SDMA_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0
2101#define SDMA_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
2102//SDMA_RLC1_MIDCMD_DATA7
2103#define SDMA_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0
2104#define SDMA_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
2105//SDMA_RLC1_MIDCMD_DATA8
2106#define SDMA_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0
2107#define SDMA_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
2108//SDMA_RLC1_MIDCMD_DATA9
2109#define SDMA_RLC1_MIDCMD_DATA9__DATA9__SHIFT 0x0
2110#define SDMA_RLC1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
2111//SDMA_RLC1_MIDCMD_DATA10
2112#define SDMA_RLC1_MIDCMD_DATA10__DATA10__SHIFT 0x0
2113#define SDMA_RLC1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
2114//SDMA_RLC1_MIDCMD_CNTL
2115#define SDMA_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
2116#define SDMA_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
2117#define SDMA_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
2118#define SDMA_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
2119#define SDMA_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
2120#define SDMA_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
2121#define SDMA_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
2122#define SDMA_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
2123//SDMA_RLC2_RB_CNTL
2124#define SDMA_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0
2125#define SDMA_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1
2126#define SDMA_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
2127#define SDMA_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
2128#define SDMA_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
2129#define SDMA_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
2130#define SDMA_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17
2131#define SDMA_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18
2132#define SDMA_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L
2133#define SDMA_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL
2134#define SDMA_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
2135#define SDMA_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
2136#define SDMA_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
2137#define SDMA_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
2138#define SDMA_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L
2139#define SDMA_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L
2140//SDMA_RLC2_RB_BASE
2141#define SDMA_RLC2_RB_BASE__ADDR__SHIFT 0x0
2142#define SDMA_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL
2143//SDMA_RLC2_RB_BASE_HI
2144#define SDMA_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0
2145#define SDMA_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
2146//SDMA_RLC2_RB_RPTR
2147#define SDMA_RLC2_RB_RPTR__OFFSET__SHIFT 0x0
2148#define SDMA_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
2149//SDMA_RLC2_RB_RPTR_HI
2150#define SDMA_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0
2151#define SDMA_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
2152//SDMA_RLC2_RB_WPTR
2153#define SDMA_RLC2_RB_WPTR__OFFSET__SHIFT 0x0
2154#define SDMA_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
2155//SDMA_RLC2_RB_WPTR_HI
2156#define SDMA_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0
2157#define SDMA_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
2158//SDMA_RLC2_RB_WPTR_POLL_CNTL
2159#define SDMA_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
2160#define SDMA_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
2161#define SDMA_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
2162#define SDMA_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
2163#define SDMA_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
2164#define SDMA_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
2165#define SDMA_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
2166#define SDMA_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
2167#define SDMA_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
2168#define SDMA_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
2169//SDMA_RLC2_RB_RPTR_ADDR_HI
2170#define SDMA_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
2171#define SDMA_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
2172//SDMA_RLC2_RB_RPTR_ADDR_LO
2173#define SDMA_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
2174#define SDMA_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
2175#define SDMA_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
2176#define SDMA_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
2177//SDMA_RLC2_IB_CNTL
2178#define SDMA_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0
2179#define SDMA_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
2180#define SDMA_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
2181#define SDMA_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10
2182#define SDMA_RLC2_IB_CNTL__IB_PRIV__SHIFT 0x1f
2183#define SDMA_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L
2184#define SDMA_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
2185#define SDMA_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
2186#define SDMA_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L
2187#define SDMA_RLC2_IB_CNTL__IB_PRIV_MASK 0x80000000L
2188//SDMA_RLC2_IB_RPTR
2189#define SDMA_RLC2_IB_RPTR__OFFSET__SHIFT 0x2
2190#define SDMA_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL
2191//SDMA_RLC2_IB_OFFSET
2192#define SDMA_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2
2193#define SDMA_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
2194//SDMA_RLC2_IB_BASE_LO
2195#define SDMA_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5
2196#define SDMA_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
2197//SDMA_RLC2_IB_BASE_HI
2198#define SDMA_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0
2199#define SDMA_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
2200//SDMA_RLC2_IB_SIZE
2201#define SDMA_RLC2_IB_SIZE__SIZE__SHIFT 0x0
2202#define SDMA_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL
2203//SDMA_RLC2_SKIP_CNTL
2204#define SDMA_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
2205#define SDMA_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
2206//SDMA_RLC2_CONTEXT_STATUS
2207#define SDMA_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0
2208#define SDMA_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2
2209#define SDMA_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
2210#define SDMA_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
2211#define SDMA_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
2212#define SDMA_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
2213#define SDMA_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
2214#define SDMA_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
2215#define SDMA_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
2216#define SDMA_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L
2217#define SDMA_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
2218#define SDMA_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
2219#define SDMA_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
2220#define SDMA_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
2221#define SDMA_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
2222#define SDMA_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
2223//SDMA_RLC2_DOORBELL
2224#define SDMA_RLC2_DOORBELL__ENABLE__SHIFT 0x1c
2225#define SDMA_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e
2226#define SDMA_RLC2_DOORBELL__ENABLE_MASK 0x10000000L
2227#define SDMA_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L
2228//SDMA_RLC2_STATUS
2229#define SDMA_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
2230#define SDMA_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
2231#define SDMA_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
2232#define SDMA_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
2233//SDMA_RLC2_DOORBELL_LOG
2234#define SDMA_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
2235#define SDMA_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2
2236#define SDMA_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
2237#define SDMA_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
2238//SDMA_RLC2_WATERMARK
2239#define SDMA_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
2240#define SDMA_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
2241#define SDMA_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
2242#define SDMA_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
2243//SDMA_RLC2_DOORBELL_OFFSET
2244#define SDMA_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
2245#define SDMA_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
2246//SDMA_RLC2_CSA_ADDR_LO
2247#define SDMA_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2
2248#define SDMA_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
2249//SDMA_RLC2_CSA_ADDR_HI
2250#define SDMA_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0
2251#define SDMA_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
2252//SDMA_RLC2_IB_SUB_REMAIN
2253#define SDMA_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0
2254#define SDMA_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
2255//SDMA_RLC2_PREEMPT
2256#define SDMA_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0
2257#define SDMA_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L
2258//SDMA_RLC2_DUMMY_REG
2259#define SDMA_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0
2260#define SDMA_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
2261//SDMA_RLC2_RB_WPTR_POLL_ADDR_HI
2262#define SDMA_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
2263#define SDMA_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
2264//SDMA_RLC2_RB_WPTR_POLL_ADDR_LO
2265#define SDMA_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
2266#define SDMA_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
2267//SDMA_RLC2_RB_AQL_CNTL
2268#define SDMA_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
2269#define SDMA_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
2270#define SDMA_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
2271#define SDMA_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
2272#define SDMA_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
2273#define SDMA_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
2274//SDMA_RLC2_MINOR_PTR_UPDATE
2275#define SDMA_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
2276#define SDMA_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
2277//SDMA_RLC2_MIDCMD_DATA0
2278#define SDMA_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0
2279#define SDMA_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
2280//SDMA_RLC2_MIDCMD_DATA1
2281#define SDMA_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0
2282#define SDMA_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
2283//SDMA_RLC2_MIDCMD_DATA2
2284#define SDMA_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0
2285#define SDMA_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
2286//SDMA_RLC2_MIDCMD_DATA3
2287#define SDMA_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0
2288#define SDMA_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
2289//SDMA_RLC2_MIDCMD_DATA4
2290#define SDMA_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0
2291#define SDMA_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
2292//SDMA_RLC2_MIDCMD_DATA5
2293#define SDMA_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0
2294#define SDMA_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
2295//SDMA_RLC2_MIDCMD_DATA6
2296#define SDMA_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0
2297#define SDMA_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
2298//SDMA_RLC2_MIDCMD_DATA7
2299#define SDMA_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0
2300#define SDMA_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
2301//SDMA_RLC2_MIDCMD_DATA8
2302#define SDMA_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0
2303#define SDMA_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
2304//SDMA_RLC2_MIDCMD_DATA9
2305#define SDMA_RLC2_MIDCMD_DATA9__DATA9__SHIFT 0x0
2306#define SDMA_RLC2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
2307//SDMA_RLC2_MIDCMD_DATA10
2308#define SDMA_RLC2_MIDCMD_DATA10__DATA10__SHIFT 0x0
2309#define SDMA_RLC2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
2310//SDMA_RLC2_MIDCMD_CNTL
2311#define SDMA_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
2312#define SDMA_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
2313#define SDMA_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
2314#define SDMA_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
2315#define SDMA_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
2316#define SDMA_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
2317#define SDMA_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
2318#define SDMA_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
2319//SDMA_RLC3_RB_CNTL
2320#define SDMA_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0
2321#define SDMA_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1
2322#define SDMA_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
2323#define SDMA_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
2324#define SDMA_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
2325#define SDMA_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
2326#define SDMA_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17
2327#define SDMA_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18
2328#define SDMA_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L
2329#define SDMA_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL
2330#define SDMA_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
2331#define SDMA_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
2332#define SDMA_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
2333#define SDMA_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
2334#define SDMA_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L
2335#define SDMA_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L
2336//SDMA_RLC3_RB_BASE
2337#define SDMA_RLC3_RB_BASE__ADDR__SHIFT 0x0
2338#define SDMA_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL
2339//SDMA_RLC3_RB_BASE_HI
2340#define SDMA_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0
2341#define SDMA_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
2342//SDMA_RLC3_RB_RPTR
2343#define SDMA_RLC3_RB_RPTR__OFFSET__SHIFT 0x0
2344#define SDMA_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
2345//SDMA_RLC3_RB_RPTR_HI
2346#define SDMA_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0
2347#define SDMA_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
2348//SDMA_RLC3_RB_WPTR
2349#define SDMA_RLC3_RB_WPTR__OFFSET__SHIFT 0x0
2350#define SDMA_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
2351//SDMA_RLC3_RB_WPTR_HI
2352#define SDMA_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0
2353#define SDMA_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
2354//SDMA_RLC3_RB_WPTR_POLL_CNTL
2355#define SDMA_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
2356#define SDMA_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
2357#define SDMA_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
2358#define SDMA_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
2359#define SDMA_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
2360#define SDMA_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
2361#define SDMA_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
2362#define SDMA_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
2363#define SDMA_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
2364#define SDMA_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
2365//SDMA_RLC3_RB_RPTR_ADDR_HI
2366#define SDMA_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
2367#define SDMA_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
2368//SDMA_RLC3_RB_RPTR_ADDR_LO
2369#define SDMA_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
2370#define SDMA_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
2371#define SDMA_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
2372#define SDMA_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
2373//SDMA_RLC3_IB_CNTL
2374#define SDMA_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0
2375#define SDMA_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
2376#define SDMA_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
2377#define SDMA_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10
2378#define SDMA_RLC3_IB_CNTL__IB_PRIV__SHIFT 0x1f
2379#define SDMA_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L
2380#define SDMA_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
2381#define SDMA_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
2382#define SDMA_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L
2383#define SDMA_RLC3_IB_CNTL__IB_PRIV_MASK 0x80000000L
2384//SDMA_RLC3_IB_RPTR
2385#define SDMA_RLC3_IB_RPTR__OFFSET__SHIFT 0x2
2386#define SDMA_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL
2387//SDMA_RLC3_IB_OFFSET
2388#define SDMA_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2
2389#define SDMA_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
2390//SDMA_RLC3_IB_BASE_LO
2391#define SDMA_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5
2392#define SDMA_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
2393//SDMA_RLC3_IB_BASE_HI
2394#define SDMA_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0
2395#define SDMA_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
2396//SDMA_RLC3_IB_SIZE
2397#define SDMA_RLC3_IB_SIZE__SIZE__SHIFT 0x0
2398#define SDMA_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL
2399//SDMA_RLC3_SKIP_CNTL
2400#define SDMA_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
2401#define SDMA_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
2402//SDMA_RLC3_CONTEXT_STATUS
2403#define SDMA_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0
2404#define SDMA_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2
2405#define SDMA_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
2406#define SDMA_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
2407#define SDMA_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
2408#define SDMA_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
2409#define SDMA_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
2410#define SDMA_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
2411#define SDMA_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
2412#define SDMA_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L
2413#define SDMA_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
2414#define SDMA_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
2415#define SDMA_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
2416#define SDMA_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
2417#define SDMA_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
2418#define SDMA_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
2419//SDMA_RLC3_DOORBELL
2420#define SDMA_RLC3_DOORBELL__ENABLE__SHIFT 0x1c
2421#define SDMA_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e
2422#define SDMA_RLC3_DOORBELL__ENABLE_MASK 0x10000000L
2423#define SDMA_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L
2424//SDMA_RLC3_STATUS
2425#define SDMA_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
2426#define SDMA_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
2427#define SDMA_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
2428#define SDMA_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
2429//SDMA_RLC3_DOORBELL_LOG
2430#define SDMA_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
2431#define SDMA_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2
2432#define SDMA_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
2433#define SDMA_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
2434//SDMA_RLC3_WATERMARK
2435#define SDMA_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
2436#define SDMA_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
2437#define SDMA_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
2438#define SDMA_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
2439//SDMA_RLC3_DOORBELL_OFFSET
2440#define SDMA_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
2441#define SDMA_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
2442//SDMA_RLC3_CSA_ADDR_LO
2443#define SDMA_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2
2444#define SDMA_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
2445//SDMA_RLC3_CSA_ADDR_HI
2446#define SDMA_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0
2447#define SDMA_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
2448//SDMA_RLC3_IB_SUB_REMAIN
2449#define SDMA_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0
2450#define SDMA_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
2451//SDMA_RLC3_PREEMPT
2452#define SDMA_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0
2453#define SDMA_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L
2454//SDMA_RLC3_DUMMY_REG
2455#define SDMA_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0
2456#define SDMA_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
2457//SDMA_RLC3_RB_WPTR_POLL_ADDR_HI
2458#define SDMA_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
2459#define SDMA_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
2460//SDMA_RLC3_RB_WPTR_POLL_ADDR_LO
2461#define SDMA_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
2462#define SDMA_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
2463//SDMA_RLC3_RB_AQL_CNTL
2464#define SDMA_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
2465#define SDMA_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
2466#define SDMA_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
2467#define SDMA_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
2468#define SDMA_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
2469#define SDMA_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
2470//SDMA_RLC3_MINOR_PTR_UPDATE
2471#define SDMA_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
2472#define SDMA_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
2473//SDMA_RLC3_MIDCMD_DATA0
2474#define SDMA_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0
2475#define SDMA_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
2476//SDMA_RLC3_MIDCMD_DATA1
2477#define SDMA_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0
2478#define SDMA_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
2479//SDMA_RLC3_MIDCMD_DATA2
2480#define SDMA_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0
2481#define SDMA_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
2482//SDMA_RLC3_MIDCMD_DATA3
2483#define SDMA_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0
2484#define SDMA_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
2485//SDMA_RLC3_MIDCMD_DATA4
2486#define SDMA_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0
2487#define SDMA_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
2488//SDMA_RLC3_MIDCMD_DATA5
2489#define SDMA_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0
2490#define SDMA_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
2491//SDMA_RLC3_MIDCMD_DATA6
2492#define SDMA_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0
2493#define SDMA_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
2494//SDMA_RLC3_MIDCMD_DATA7
2495#define SDMA_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0
2496#define SDMA_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
2497//SDMA_RLC3_MIDCMD_DATA8
2498#define SDMA_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0
2499#define SDMA_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
2500//SDMA_RLC3_MIDCMD_DATA9
2501#define SDMA_RLC3_MIDCMD_DATA9__DATA9__SHIFT 0x0
2502#define SDMA_RLC3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
2503//SDMA_RLC3_MIDCMD_DATA10
2504#define SDMA_RLC3_MIDCMD_DATA10__DATA10__SHIFT 0x0
2505#define SDMA_RLC3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
2506//SDMA_RLC3_MIDCMD_CNTL
2507#define SDMA_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
2508#define SDMA_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
2509#define SDMA_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
2510#define SDMA_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
2511#define SDMA_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
2512#define SDMA_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
2513#define SDMA_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
2514#define SDMA_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
2515//SDMA_RLC4_RB_CNTL
2516#define SDMA_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0
2517#define SDMA_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1
2518#define SDMA_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
2519#define SDMA_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
2520#define SDMA_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
2521#define SDMA_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
2522#define SDMA_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17
2523#define SDMA_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18
2524#define SDMA_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L
2525#define SDMA_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL
2526#define SDMA_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
2527#define SDMA_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
2528#define SDMA_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
2529#define SDMA_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
2530#define SDMA_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L
2531#define SDMA_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L
2532//SDMA_RLC4_RB_BASE
2533#define SDMA_RLC4_RB_BASE__ADDR__SHIFT 0x0
2534#define SDMA_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL
2535//SDMA_RLC4_RB_BASE_HI
2536#define SDMA_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0
2537#define SDMA_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
2538//SDMA_RLC4_RB_RPTR
2539#define SDMA_RLC4_RB_RPTR__OFFSET__SHIFT 0x0
2540#define SDMA_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
2541//SDMA_RLC4_RB_RPTR_HI
2542#define SDMA_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0
2543#define SDMA_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
2544//SDMA_RLC4_RB_WPTR
2545#define SDMA_RLC4_RB_WPTR__OFFSET__SHIFT 0x0
2546#define SDMA_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
2547//SDMA_RLC4_RB_WPTR_HI
2548#define SDMA_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0
2549#define SDMA_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
2550//SDMA_RLC4_RB_WPTR_POLL_CNTL
2551#define SDMA_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
2552#define SDMA_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
2553#define SDMA_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
2554#define SDMA_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
2555#define SDMA_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
2556#define SDMA_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
2557#define SDMA_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
2558#define SDMA_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
2559#define SDMA_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
2560#define SDMA_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
2561//SDMA_RLC4_RB_RPTR_ADDR_HI
2562#define SDMA_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
2563#define SDMA_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
2564//SDMA_RLC4_RB_RPTR_ADDR_LO
2565#define SDMA_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
2566#define SDMA_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
2567#define SDMA_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
2568#define SDMA_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
2569//SDMA_RLC4_IB_CNTL
2570#define SDMA_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0
2571#define SDMA_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
2572#define SDMA_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
2573#define SDMA_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10
2574#define SDMA_RLC4_IB_CNTL__IB_PRIV__SHIFT 0x1f
2575#define SDMA_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L
2576#define SDMA_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
2577#define SDMA_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
2578#define SDMA_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L
2579#define SDMA_RLC4_IB_CNTL__IB_PRIV_MASK 0x80000000L
2580//SDMA_RLC4_IB_RPTR
2581#define SDMA_RLC4_IB_RPTR__OFFSET__SHIFT 0x2
2582#define SDMA_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL
2583//SDMA_RLC4_IB_OFFSET
2584#define SDMA_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2
2585#define SDMA_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
2586//SDMA_RLC4_IB_BASE_LO
2587#define SDMA_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5
2588#define SDMA_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
2589//SDMA_RLC4_IB_BASE_HI
2590#define SDMA_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0
2591#define SDMA_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
2592//SDMA_RLC4_IB_SIZE
2593#define SDMA_RLC4_IB_SIZE__SIZE__SHIFT 0x0
2594#define SDMA_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL
2595//SDMA_RLC4_SKIP_CNTL
2596#define SDMA_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
2597#define SDMA_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
2598//SDMA_RLC4_CONTEXT_STATUS
2599#define SDMA_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0
2600#define SDMA_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2
2601#define SDMA_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
2602#define SDMA_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
2603#define SDMA_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
2604#define SDMA_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
2605#define SDMA_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
2606#define SDMA_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
2607#define SDMA_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
2608#define SDMA_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L
2609#define SDMA_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
2610#define SDMA_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
2611#define SDMA_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
2612#define SDMA_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
2613#define SDMA_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
2614#define SDMA_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
2615//SDMA_RLC4_DOORBELL
2616#define SDMA_RLC4_DOORBELL__ENABLE__SHIFT 0x1c
2617#define SDMA_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e
2618#define SDMA_RLC4_DOORBELL__ENABLE_MASK 0x10000000L
2619#define SDMA_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L
2620//SDMA_RLC4_STATUS
2621#define SDMA_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
2622#define SDMA_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
2623#define SDMA_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
2624#define SDMA_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
2625//SDMA_RLC4_DOORBELL_LOG
2626#define SDMA_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
2627#define SDMA_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2
2628#define SDMA_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
2629#define SDMA_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
2630//SDMA_RLC4_WATERMARK
2631#define SDMA_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
2632#define SDMA_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
2633#define SDMA_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
2634#define SDMA_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
2635//SDMA_RLC4_DOORBELL_OFFSET
2636#define SDMA_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
2637#define SDMA_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
2638//SDMA_RLC4_CSA_ADDR_LO
2639#define SDMA_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2
2640#define SDMA_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
2641//SDMA_RLC4_CSA_ADDR_HI
2642#define SDMA_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0
2643#define SDMA_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
2644//SDMA_RLC4_IB_SUB_REMAIN
2645#define SDMA_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0
2646#define SDMA_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
2647//SDMA_RLC4_PREEMPT
2648#define SDMA_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0
2649#define SDMA_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L
2650//SDMA_RLC4_DUMMY_REG
2651#define SDMA_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0
2652#define SDMA_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
2653//SDMA_RLC4_RB_WPTR_POLL_ADDR_HI
2654#define SDMA_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
2655#define SDMA_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
2656//SDMA_RLC4_RB_WPTR_POLL_ADDR_LO
2657#define SDMA_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
2658#define SDMA_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
2659//SDMA_RLC4_RB_AQL_CNTL
2660#define SDMA_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
2661#define SDMA_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
2662#define SDMA_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
2663#define SDMA_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
2664#define SDMA_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
2665#define SDMA_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
2666//SDMA_RLC4_MINOR_PTR_UPDATE
2667#define SDMA_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
2668#define SDMA_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
2669//SDMA_RLC4_MIDCMD_DATA0
2670#define SDMA_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0
2671#define SDMA_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
2672//SDMA_RLC4_MIDCMD_DATA1
2673#define SDMA_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0
2674#define SDMA_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
2675//SDMA_RLC4_MIDCMD_DATA2
2676#define SDMA_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0
2677#define SDMA_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
2678//SDMA_RLC4_MIDCMD_DATA3
2679#define SDMA_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0
2680#define SDMA_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
2681//SDMA_RLC4_MIDCMD_DATA4
2682#define SDMA_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0
2683#define SDMA_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
2684//SDMA_RLC4_MIDCMD_DATA5
2685#define SDMA_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0
2686#define SDMA_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
2687//SDMA_RLC4_MIDCMD_DATA6
2688#define SDMA_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0
2689#define SDMA_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
2690//SDMA_RLC4_MIDCMD_DATA7
2691#define SDMA_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0
2692#define SDMA_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
2693//SDMA_RLC4_MIDCMD_DATA8
2694#define SDMA_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0
2695#define SDMA_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
2696//SDMA_RLC4_MIDCMD_DATA9
2697#define SDMA_RLC4_MIDCMD_DATA9__DATA9__SHIFT 0x0
2698#define SDMA_RLC4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
2699//SDMA_RLC4_MIDCMD_DATA10
2700#define SDMA_RLC4_MIDCMD_DATA10__DATA10__SHIFT 0x0
2701#define SDMA_RLC4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
2702//SDMA_RLC4_MIDCMD_CNTL
2703#define SDMA_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
2704#define SDMA_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
2705#define SDMA_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
2706#define SDMA_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
2707#define SDMA_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
2708#define SDMA_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
2709#define SDMA_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
2710#define SDMA_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
2711//SDMA_RLC5_RB_CNTL
2712#define SDMA_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0
2713#define SDMA_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1
2714#define SDMA_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
2715#define SDMA_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
2716#define SDMA_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
2717#define SDMA_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
2718#define SDMA_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17
2719#define SDMA_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18
2720#define SDMA_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L
2721#define SDMA_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL
2722#define SDMA_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
2723#define SDMA_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
2724#define SDMA_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
2725#define SDMA_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
2726#define SDMA_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L
2727#define SDMA_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L
2728//SDMA_RLC5_RB_BASE
2729#define SDMA_RLC5_RB_BASE__ADDR__SHIFT 0x0
2730#define SDMA_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL
2731//SDMA_RLC5_RB_BASE_HI
2732#define SDMA_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0
2733#define SDMA_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
2734//SDMA_RLC5_RB_RPTR
2735#define SDMA_RLC5_RB_RPTR__OFFSET__SHIFT 0x0
2736#define SDMA_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
2737//SDMA_RLC5_RB_RPTR_HI
2738#define SDMA_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0
2739#define SDMA_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
2740//SDMA_RLC5_RB_WPTR
2741#define SDMA_RLC5_RB_WPTR__OFFSET__SHIFT 0x0
2742#define SDMA_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
2743//SDMA_RLC5_RB_WPTR_HI
2744#define SDMA_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0
2745#define SDMA_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
2746//SDMA_RLC5_RB_WPTR_POLL_CNTL
2747#define SDMA_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
2748#define SDMA_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
2749#define SDMA_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
2750#define SDMA_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
2751#define SDMA_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
2752#define SDMA_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
2753#define SDMA_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
2754#define SDMA_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
2755#define SDMA_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
2756#define SDMA_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
2757//SDMA_RLC5_RB_RPTR_ADDR_HI
2758#define SDMA_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
2759#define SDMA_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
2760//SDMA_RLC5_RB_RPTR_ADDR_LO
2761#define SDMA_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
2762#define SDMA_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
2763#define SDMA_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
2764#define SDMA_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
2765//SDMA_RLC5_IB_CNTL
2766#define SDMA_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0
2767#define SDMA_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
2768#define SDMA_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
2769#define SDMA_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10
2770#define SDMA_RLC5_IB_CNTL__IB_PRIV__SHIFT 0x1f
2771#define SDMA_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L
2772#define SDMA_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
2773#define SDMA_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
2774#define SDMA_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L
2775#define SDMA_RLC5_IB_CNTL__IB_PRIV_MASK 0x80000000L
2776//SDMA_RLC5_IB_RPTR
2777#define SDMA_RLC5_IB_RPTR__OFFSET__SHIFT 0x2
2778#define SDMA_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL
2779//SDMA_RLC5_IB_OFFSET
2780#define SDMA_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2
2781#define SDMA_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
2782//SDMA_RLC5_IB_BASE_LO
2783#define SDMA_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5
2784#define SDMA_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
2785//SDMA_RLC5_IB_BASE_HI
2786#define SDMA_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0
2787#define SDMA_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
2788//SDMA_RLC5_IB_SIZE
2789#define SDMA_RLC5_IB_SIZE__SIZE__SHIFT 0x0
2790#define SDMA_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL
2791//SDMA_RLC5_SKIP_CNTL
2792#define SDMA_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
2793#define SDMA_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
2794//SDMA_RLC5_CONTEXT_STATUS
2795#define SDMA_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0
2796#define SDMA_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2
2797#define SDMA_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
2798#define SDMA_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
2799#define SDMA_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
2800#define SDMA_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
2801#define SDMA_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
2802#define SDMA_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
2803#define SDMA_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
2804#define SDMA_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L
2805#define SDMA_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
2806#define SDMA_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
2807#define SDMA_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
2808#define SDMA_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
2809#define SDMA_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
2810#define SDMA_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
2811//SDMA_RLC5_DOORBELL
2812#define SDMA_RLC5_DOORBELL__ENABLE__SHIFT 0x1c
2813#define SDMA_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e
2814#define SDMA_RLC5_DOORBELL__ENABLE_MASK 0x10000000L
2815#define SDMA_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L
2816//SDMA_RLC5_STATUS
2817#define SDMA_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
2818#define SDMA_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
2819#define SDMA_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
2820#define SDMA_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
2821//SDMA_RLC5_DOORBELL_LOG
2822#define SDMA_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
2823#define SDMA_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2
2824#define SDMA_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
2825#define SDMA_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
2826//SDMA_RLC5_WATERMARK
2827#define SDMA_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
2828#define SDMA_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
2829#define SDMA_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
2830#define SDMA_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
2831//SDMA_RLC5_DOORBELL_OFFSET
2832#define SDMA_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
2833#define SDMA_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
2834//SDMA_RLC5_CSA_ADDR_LO
2835#define SDMA_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2
2836#define SDMA_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
2837//SDMA_RLC5_CSA_ADDR_HI
2838#define SDMA_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0
2839#define SDMA_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
2840//SDMA_RLC5_IB_SUB_REMAIN
2841#define SDMA_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0
2842#define SDMA_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
2843//SDMA_RLC5_PREEMPT
2844#define SDMA_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0
2845#define SDMA_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L
2846//SDMA_RLC5_DUMMY_REG
2847#define SDMA_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0
2848#define SDMA_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
2849//SDMA_RLC5_RB_WPTR_POLL_ADDR_HI
2850#define SDMA_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
2851#define SDMA_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
2852//SDMA_RLC5_RB_WPTR_POLL_ADDR_LO
2853#define SDMA_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
2854#define SDMA_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
2855//SDMA_RLC5_RB_AQL_CNTL
2856#define SDMA_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
2857#define SDMA_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
2858#define SDMA_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
2859#define SDMA_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
2860#define SDMA_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
2861#define SDMA_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
2862//SDMA_RLC5_MINOR_PTR_UPDATE
2863#define SDMA_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
2864#define SDMA_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
2865//SDMA_RLC5_MIDCMD_DATA0
2866#define SDMA_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0
2867#define SDMA_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
2868//SDMA_RLC5_MIDCMD_DATA1
2869#define SDMA_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0
2870#define SDMA_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
2871//SDMA_RLC5_MIDCMD_DATA2
2872#define SDMA_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0
2873#define SDMA_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
2874//SDMA_RLC5_MIDCMD_DATA3
2875#define SDMA_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0
2876#define SDMA_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
2877//SDMA_RLC5_MIDCMD_DATA4
2878#define SDMA_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0
2879#define SDMA_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
2880//SDMA_RLC5_MIDCMD_DATA5
2881#define SDMA_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0
2882#define SDMA_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
2883//SDMA_RLC5_MIDCMD_DATA6
2884#define SDMA_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0
2885#define SDMA_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
2886//SDMA_RLC5_MIDCMD_DATA7
2887#define SDMA_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0
2888#define SDMA_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
2889//SDMA_RLC5_MIDCMD_DATA8
2890#define SDMA_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0
2891#define SDMA_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
2892//SDMA_RLC5_MIDCMD_DATA9
2893#define SDMA_RLC5_MIDCMD_DATA9__DATA9__SHIFT 0x0
2894#define SDMA_RLC5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
2895//SDMA_RLC5_MIDCMD_DATA10
2896#define SDMA_RLC5_MIDCMD_DATA10__DATA10__SHIFT 0x0
2897#define SDMA_RLC5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
2898//SDMA_RLC5_MIDCMD_CNTL
2899#define SDMA_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
2900#define SDMA_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
2901#define SDMA_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
2902#define SDMA_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
2903#define SDMA_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
2904#define SDMA_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
2905#define SDMA_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
2906#define SDMA_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
2907//SDMA_RLC6_RB_CNTL
2908#define SDMA_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0
2909#define SDMA_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1
2910#define SDMA_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
2911#define SDMA_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
2912#define SDMA_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
2913#define SDMA_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
2914#define SDMA_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17
2915#define SDMA_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18
2916#define SDMA_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L
2917#define SDMA_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL
2918#define SDMA_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
2919#define SDMA_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
2920#define SDMA_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
2921#define SDMA_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
2922#define SDMA_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L
2923#define SDMA_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L
2924//SDMA_RLC6_RB_BASE
2925#define SDMA_RLC6_RB_BASE__ADDR__SHIFT 0x0
2926#define SDMA_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL
2927//SDMA_RLC6_RB_BASE_HI
2928#define SDMA_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0
2929#define SDMA_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
2930//SDMA_RLC6_RB_RPTR
2931#define SDMA_RLC6_RB_RPTR__OFFSET__SHIFT 0x0
2932#define SDMA_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
2933//SDMA_RLC6_RB_RPTR_HI
2934#define SDMA_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0
2935#define SDMA_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
2936//SDMA_RLC6_RB_WPTR
2937#define SDMA_RLC6_RB_WPTR__OFFSET__SHIFT 0x0
2938#define SDMA_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
2939//SDMA_RLC6_RB_WPTR_HI
2940#define SDMA_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0
2941#define SDMA_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
2942//SDMA_RLC6_RB_WPTR_POLL_CNTL
2943#define SDMA_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
2944#define SDMA_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
2945#define SDMA_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
2946#define SDMA_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
2947#define SDMA_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
2948#define SDMA_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
2949#define SDMA_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
2950#define SDMA_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
2951#define SDMA_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
2952#define SDMA_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
2953//SDMA_RLC6_RB_RPTR_ADDR_HI
2954#define SDMA_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
2955#define SDMA_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
2956//SDMA_RLC6_RB_RPTR_ADDR_LO
2957#define SDMA_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
2958#define SDMA_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
2959#define SDMA_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
2960#define SDMA_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
2961//SDMA_RLC6_IB_CNTL
2962#define SDMA_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0
2963#define SDMA_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
2964#define SDMA_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
2965#define SDMA_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10
2966#define SDMA_RLC6_IB_CNTL__IB_PRIV__SHIFT 0x1f
2967#define SDMA_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L
2968#define SDMA_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
2969#define SDMA_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
2970#define SDMA_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L
2971#define SDMA_RLC6_IB_CNTL__IB_PRIV_MASK 0x80000000L
2972//SDMA_RLC6_IB_RPTR
2973#define SDMA_RLC6_IB_RPTR__OFFSET__SHIFT 0x2
2974#define SDMA_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL
2975//SDMA_RLC6_IB_OFFSET
2976#define SDMA_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2
2977#define SDMA_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
2978//SDMA_RLC6_IB_BASE_LO
2979#define SDMA_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5
2980#define SDMA_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
2981//SDMA_RLC6_IB_BASE_HI
2982#define SDMA_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0
2983#define SDMA_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
2984//SDMA_RLC6_IB_SIZE
2985#define SDMA_RLC6_IB_SIZE__SIZE__SHIFT 0x0
2986#define SDMA_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL
2987//SDMA_RLC6_SKIP_CNTL
2988#define SDMA_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
2989#define SDMA_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
2990//SDMA_RLC6_CONTEXT_STATUS
2991#define SDMA_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0
2992#define SDMA_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2
2993#define SDMA_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
2994#define SDMA_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
2995#define SDMA_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
2996#define SDMA_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
2997#define SDMA_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
2998#define SDMA_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
2999#define SDMA_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
3000#define SDMA_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L
3001#define SDMA_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
3002#define SDMA_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
3003#define SDMA_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
3004#define SDMA_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
3005#define SDMA_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
3006#define SDMA_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
3007//SDMA_RLC6_DOORBELL
3008#define SDMA_RLC6_DOORBELL__ENABLE__SHIFT 0x1c
3009#define SDMA_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e
3010#define SDMA_RLC6_DOORBELL__ENABLE_MASK 0x10000000L
3011#define SDMA_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L
3012//SDMA_RLC6_STATUS
3013#define SDMA_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
3014#define SDMA_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
3015#define SDMA_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
3016#define SDMA_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
3017//SDMA_RLC6_DOORBELL_LOG
3018#define SDMA_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
3019#define SDMA_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2
3020#define SDMA_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
3021#define SDMA_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
3022//SDMA_RLC6_WATERMARK
3023#define SDMA_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
3024#define SDMA_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
3025#define SDMA_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
3026#define SDMA_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
3027//SDMA_RLC6_DOORBELL_OFFSET
3028#define SDMA_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
3029#define SDMA_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
3030//SDMA_RLC6_CSA_ADDR_LO
3031#define SDMA_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2
3032#define SDMA_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
3033//SDMA_RLC6_CSA_ADDR_HI
3034#define SDMA_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0
3035#define SDMA_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
3036//SDMA_RLC6_IB_SUB_REMAIN
3037#define SDMA_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0
3038#define SDMA_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
3039//SDMA_RLC6_PREEMPT
3040#define SDMA_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0
3041#define SDMA_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L
3042//SDMA_RLC6_DUMMY_REG
3043#define SDMA_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0
3044#define SDMA_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
3045//SDMA_RLC6_RB_WPTR_POLL_ADDR_HI
3046#define SDMA_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
3047#define SDMA_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
3048//SDMA_RLC6_RB_WPTR_POLL_ADDR_LO
3049#define SDMA_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
3050#define SDMA_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
3051//SDMA_RLC6_RB_AQL_CNTL
3052#define SDMA_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
3053#define SDMA_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
3054#define SDMA_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
3055#define SDMA_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
3056#define SDMA_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
3057#define SDMA_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
3058//SDMA_RLC6_MINOR_PTR_UPDATE
3059#define SDMA_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
3060#define SDMA_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
3061//SDMA_RLC6_MIDCMD_DATA0
3062#define SDMA_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0
3063#define SDMA_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
3064//SDMA_RLC6_MIDCMD_DATA1
3065#define SDMA_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0
3066#define SDMA_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
3067//SDMA_RLC6_MIDCMD_DATA2
3068#define SDMA_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0
3069#define SDMA_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
3070//SDMA_RLC6_MIDCMD_DATA3
3071#define SDMA_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0
3072#define SDMA_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
3073//SDMA_RLC6_MIDCMD_DATA4
3074#define SDMA_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0
3075#define SDMA_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
3076//SDMA_RLC6_MIDCMD_DATA5
3077#define SDMA_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0
3078#define SDMA_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
3079//SDMA_RLC6_MIDCMD_DATA6
3080#define SDMA_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0
3081#define SDMA_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
3082//SDMA_RLC6_MIDCMD_DATA7
3083#define SDMA_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0
3084#define SDMA_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
3085//SDMA_RLC6_MIDCMD_DATA8
3086#define SDMA_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0
3087#define SDMA_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
3088//SDMA_RLC6_MIDCMD_DATA9
3089#define SDMA_RLC6_MIDCMD_DATA9__DATA9__SHIFT 0x0
3090#define SDMA_RLC6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
3091//SDMA_RLC6_MIDCMD_DATA10
3092#define SDMA_RLC6_MIDCMD_DATA10__DATA10__SHIFT 0x0
3093#define SDMA_RLC6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
3094//SDMA_RLC6_MIDCMD_CNTL
3095#define SDMA_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
3096#define SDMA_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
3097#define SDMA_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
3098#define SDMA_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
3099#define SDMA_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
3100#define SDMA_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
3101#define SDMA_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
3102#define SDMA_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
3103//SDMA_RLC7_RB_CNTL
3104#define SDMA_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0
3105#define SDMA_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1
3106#define SDMA_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
3107#define SDMA_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
3108#define SDMA_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
3109#define SDMA_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
3110#define SDMA_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17
3111#define SDMA_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18
3112#define SDMA_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L
3113#define SDMA_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL
3114#define SDMA_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
3115#define SDMA_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
3116#define SDMA_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
3117#define SDMA_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
3118#define SDMA_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L
3119#define SDMA_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L
3120//SDMA_RLC7_RB_BASE
3121#define SDMA_RLC7_RB_BASE__ADDR__SHIFT 0x0
3122#define SDMA_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL
3123//SDMA_RLC7_RB_BASE_HI
3124#define SDMA_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0
3125#define SDMA_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
3126//SDMA_RLC7_RB_RPTR
3127#define SDMA_RLC7_RB_RPTR__OFFSET__SHIFT 0x0
3128#define SDMA_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
3129//SDMA_RLC7_RB_RPTR_HI
3130#define SDMA_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0
3131#define SDMA_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
3132//SDMA_RLC7_RB_WPTR
3133#define SDMA_RLC7_RB_WPTR__OFFSET__SHIFT 0x0
3134#define SDMA_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
3135//SDMA_RLC7_RB_WPTR_HI
3136#define SDMA_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0
3137#define SDMA_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
3138//SDMA_RLC7_RB_WPTR_POLL_CNTL
3139#define SDMA_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
3140#define SDMA_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
3141#define SDMA_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
3142#define SDMA_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
3143#define SDMA_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
3144#define SDMA_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
3145#define SDMA_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
3146#define SDMA_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
3147#define SDMA_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
3148#define SDMA_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
3149//SDMA_RLC7_RB_RPTR_ADDR_HI
3150#define SDMA_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
3151#define SDMA_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
3152//SDMA_RLC7_RB_RPTR_ADDR_LO
3153#define SDMA_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
3154#define SDMA_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
3155#define SDMA_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
3156#define SDMA_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
3157//SDMA_RLC7_IB_CNTL
3158#define SDMA_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0
3159#define SDMA_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
3160#define SDMA_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
3161#define SDMA_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10
3162#define SDMA_RLC7_IB_CNTL__IB_PRIV__SHIFT 0x1f
3163#define SDMA_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L
3164#define SDMA_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
3165#define SDMA_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
3166#define SDMA_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L
3167#define SDMA_RLC7_IB_CNTL__IB_PRIV_MASK 0x80000000L
3168//SDMA_RLC7_IB_RPTR
3169#define SDMA_RLC7_IB_RPTR__OFFSET__SHIFT 0x2
3170#define SDMA_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL
3171//SDMA_RLC7_IB_OFFSET
3172#define SDMA_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2
3173#define SDMA_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
3174//SDMA_RLC7_IB_BASE_LO
3175#define SDMA_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5
3176#define SDMA_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
3177//SDMA_RLC7_IB_BASE_HI
3178#define SDMA_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0
3179#define SDMA_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
3180//SDMA_RLC7_IB_SIZE
3181#define SDMA_RLC7_IB_SIZE__SIZE__SHIFT 0x0
3182#define SDMA_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL
3183//SDMA_RLC7_SKIP_CNTL
3184#define SDMA_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
3185#define SDMA_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
3186//SDMA_RLC7_CONTEXT_STATUS
3187#define SDMA_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0
3188#define SDMA_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2
3189#define SDMA_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
3190#define SDMA_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
3191#define SDMA_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
3192#define SDMA_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
3193#define SDMA_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
3194#define SDMA_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
3195#define SDMA_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
3196#define SDMA_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L
3197#define SDMA_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
3198#define SDMA_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
3199#define SDMA_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
3200#define SDMA_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
3201#define SDMA_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
3202#define SDMA_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
3203//SDMA_RLC7_DOORBELL
3204#define SDMA_RLC7_DOORBELL__ENABLE__SHIFT 0x1c
3205#define SDMA_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e
3206#define SDMA_RLC7_DOORBELL__ENABLE_MASK 0x10000000L
3207#define SDMA_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L
3208//SDMA_RLC7_STATUS
3209#define SDMA_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
3210#define SDMA_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
3211#define SDMA_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
3212#define SDMA_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
3213//SDMA_RLC7_DOORBELL_LOG
3214#define SDMA_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
3215#define SDMA_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2
3216#define SDMA_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
3217#define SDMA_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
3218//SDMA_RLC7_WATERMARK
3219#define SDMA_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
3220#define SDMA_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
3221#define SDMA_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
3222#define SDMA_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
3223//SDMA_RLC7_DOORBELL_OFFSET
3224#define SDMA_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
3225#define SDMA_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
3226//SDMA_RLC7_CSA_ADDR_LO
3227#define SDMA_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2
3228#define SDMA_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
3229//SDMA_RLC7_CSA_ADDR_HI
3230#define SDMA_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0
3231#define SDMA_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
3232//SDMA_RLC7_IB_SUB_REMAIN
3233#define SDMA_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0
3234#define SDMA_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
3235//SDMA_RLC7_PREEMPT
3236#define SDMA_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0
3237#define SDMA_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L
3238//SDMA_RLC7_DUMMY_REG
3239#define SDMA_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0
3240#define SDMA_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
3241//SDMA_RLC7_RB_WPTR_POLL_ADDR_HI
3242#define SDMA_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
3243#define SDMA_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
3244//SDMA_RLC7_RB_WPTR_POLL_ADDR_LO
3245#define SDMA_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
3246#define SDMA_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
3247//SDMA_RLC7_RB_AQL_CNTL
3248#define SDMA_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
3249#define SDMA_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
3250#define SDMA_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
3251#define SDMA_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
3252#define SDMA_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
3253#define SDMA_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
3254//SDMA_RLC7_MINOR_PTR_UPDATE
3255#define SDMA_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
3256#define SDMA_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
3257//SDMA_RLC7_MIDCMD_DATA0
3258#define SDMA_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0
3259#define SDMA_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
3260//SDMA_RLC7_MIDCMD_DATA1
3261#define SDMA_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0
3262#define SDMA_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
3263//SDMA_RLC7_MIDCMD_DATA2
3264#define SDMA_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0
3265#define SDMA_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
3266//SDMA_RLC7_MIDCMD_DATA3
3267#define SDMA_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0
3268#define SDMA_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
3269//SDMA_RLC7_MIDCMD_DATA4
3270#define SDMA_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0
3271#define SDMA_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
3272//SDMA_RLC7_MIDCMD_DATA5
3273#define SDMA_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0
3274#define SDMA_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
3275//SDMA_RLC7_MIDCMD_DATA6
3276#define SDMA_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0
3277#define SDMA_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
3278//SDMA_RLC7_MIDCMD_DATA7
3279#define SDMA_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0
3280#define SDMA_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
3281//SDMA_RLC7_MIDCMD_DATA8
3282#define SDMA_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0
3283#define SDMA_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
3284//SDMA_RLC7_MIDCMD_DATA9
3285#define SDMA_RLC7_MIDCMD_DATA9__DATA9__SHIFT 0x0
3286#define SDMA_RLC7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
3287//SDMA_RLC7_MIDCMD_DATA10
3288#define SDMA_RLC7_MIDCMD_DATA10__DATA10__SHIFT 0x0
3289#define SDMA_RLC7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
3290//SDMA_RLC7_MIDCMD_CNTL
3291#define SDMA_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
3292#define SDMA_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
3293#define SDMA_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
3294#define SDMA_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
3295#define SDMA_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
3296#define SDMA_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
3297#define SDMA_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
3298#define SDMA_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
3299
3300#endif
3301

source code of linux/drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_2_sh_mask.h