1 | /* |
2 | * Copyright (C) 2018 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included |
12 | * in all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
20 | */ |
21 | #ifndef _sdma0_4_2_2_OFFSET_HEADER |
22 | #define |
23 | |
24 | |
25 | |
26 | // addressBlock: sdma0_sdma0dec |
27 | // base address: 0x4980 |
28 | #define mmSDMA0_UCODE_ADDR 0x0000 |
29 | #define mmSDMA0_UCODE_ADDR_BASE_IDX 0 |
30 | #define mmSDMA0_UCODE_DATA 0x0001 |
31 | #define mmSDMA0_UCODE_DATA_BASE_IDX 0 |
32 | #define mmSDMA0_VM_CNTL 0x0004 |
33 | #define mmSDMA0_VM_CNTL_BASE_IDX 0 |
34 | #define mmSDMA0_VM_CTX_LO 0x0005 |
35 | #define mmSDMA0_VM_CTX_LO_BASE_IDX 0 |
36 | #define mmSDMA0_VM_CTX_HI 0x0006 |
37 | #define mmSDMA0_VM_CTX_HI_BASE_IDX 0 |
38 | #define mmSDMA0_ACTIVE_FCN_ID 0x0007 |
39 | #define mmSDMA0_ACTIVE_FCN_ID_BASE_IDX 0 |
40 | #define mmSDMA0_VM_CTX_CNTL 0x0008 |
41 | #define mmSDMA0_VM_CTX_CNTL_BASE_IDX 0 |
42 | #define mmSDMA0_VIRT_RESET_REQ 0x0009 |
43 | #define mmSDMA0_VIRT_RESET_REQ_BASE_IDX 0 |
44 | #define mmSDMA0_VF_ENABLE 0x000a |
45 | #define mmSDMA0_VF_ENABLE_BASE_IDX 0 |
46 | #define mmSDMA0_CONTEXT_REG_TYPE0 0x000b |
47 | #define mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX 0 |
48 | #define mmSDMA0_CONTEXT_REG_TYPE1 0x000c |
49 | #define mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX 0 |
50 | #define mmSDMA0_CONTEXT_REG_TYPE2 0x000d |
51 | #define mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX 0 |
52 | #define mmSDMA0_CONTEXT_REG_TYPE3 0x000e |
53 | #define mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX 0 |
54 | #define mmSDMA0_PUB_REG_TYPE0 0x000f |
55 | #define mmSDMA0_PUB_REG_TYPE0_BASE_IDX 0 |
56 | #define mmSDMA0_PUB_REG_TYPE1 0x0010 |
57 | #define mmSDMA0_PUB_REG_TYPE1_BASE_IDX 0 |
58 | #define mmSDMA0_PUB_REG_TYPE2 0x0011 |
59 | #define mmSDMA0_PUB_REG_TYPE2_BASE_IDX 0 |
60 | #define mmSDMA0_PUB_REG_TYPE3 0x0012 |
61 | #define mmSDMA0_PUB_REG_TYPE3_BASE_IDX 0 |
62 | #define mmSDMA0_MMHUB_CNTL 0x0013 |
63 | #define mmSDMA0_MMHUB_CNTL_BASE_IDX 0 |
64 | #define mmSDMA0_CONTEXT_GROUP_BOUNDARY 0x0019 |
65 | #define mmSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 |
66 | #define mmSDMA0_POWER_CNTL 0x001a |
67 | #define mmSDMA0_POWER_CNTL_BASE_IDX 0 |
68 | #define mmSDMA0_CLK_CTRL 0x001b |
69 | #define mmSDMA0_CLK_CTRL_BASE_IDX 0 |
70 | #define mmSDMA0_CNTL 0x001c |
71 | #define mmSDMA0_CNTL_BASE_IDX 0 |
72 | #define mmSDMA0_CHICKEN_BITS 0x001d |
73 | #define mmSDMA0_CHICKEN_BITS_BASE_IDX 0 |
74 | #define mmSDMA0_GB_ADDR_CONFIG 0x001e |
75 | #define mmSDMA0_GB_ADDR_CONFIG_BASE_IDX 0 |
76 | #define mmSDMA0_GB_ADDR_CONFIG_READ 0x001f |
77 | #define mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0 |
78 | #define mmSDMA0_RB_RPTR_FETCH_HI 0x0020 |
79 | #define mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0 |
80 | #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 |
81 | #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 |
82 | #define mmSDMA0_RB_RPTR_FETCH 0x0022 |
83 | #define mmSDMA0_RB_RPTR_FETCH_BASE_IDX 0 |
84 | #define mmSDMA0_IB_OFFSET_FETCH 0x0023 |
85 | #define mmSDMA0_IB_OFFSET_FETCH_BASE_IDX 0 |
86 | #define mmSDMA0_PROGRAM 0x0024 |
87 | #define mmSDMA0_PROGRAM_BASE_IDX 0 |
88 | #define mmSDMA0_STATUS_REG 0x0025 |
89 | #define mmSDMA0_STATUS_REG_BASE_IDX 0 |
90 | #define mmSDMA0_STATUS1_REG 0x0026 |
91 | #define mmSDMA0_STATUS1_REG_BASE_IDX 0 |
92 | #define mmSDMA0_RD_BURST_CNTL 0x0027 |
93 | #define mmSDMA0_RD_BURST_CNTL_BASE_IDX 0 |
94 | #define mmSDMA0_HBM_PAGE_CONFIG 0x0028 |
95 | #define mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0 |
96 | #define mmSDMA0_UCODE_CHECKSUM 0x0029 |
97 | #define mmSDMA0_UCODE_CHECKSUM_BASE_IDX 0 |
98 | #define mmSDMA0_F32_CNTL 0x002a |
99 | #define mmSDMA0_F32_CNTL_BASE_IDX 0 |
100 | #define mmSDMA0_FREEZE 0x002b |
101 | #define mmSDMA0_FREEZE_BASE_IDX 0 |
102 | #define mmSDMA0_PHASE0_QUANTUM 0x002c |
103 | #define mmSDMA0_PHASE0_QUANTUM_BASE_IDX 0 |
104 | #define mmSDMA0_PHASE1_QUANTUM 0x002d |
105 | #define mmSDMA0_PHASE1_QUANTUM_BASE_IDX 0 |
106 | #define mmSDMA_POWER_GATING 0x002e |
107 | #define mmSDMA_POWER_GATING_BASE_IDX 0 |
108 | #define mmSDMA_PGFSM_CONFIG 0x002f |
109 | #define mmSDMA_PGFSM_CONFIG_BASE_IDX 0 |
110 | #define mmSDMA_PGFSM_WRITE 0x0030 |
111 | #define mmSDMA_PGFSM_WRITE_BASE_IDX 0 |
112 | #define mmSDMA_PGFSM_READ 0x0031 |
113 | #define mmSDMA_PGFSM_READ_BASE_IDX 0 |
114 | #define mmSDMA0_EDC_CONFIG 0x0032 |
115 | #define mmSDMA0_EDC_CONFIG_BASE_IDX 0 |
116 | #define mmSDMA0_BA_THRESHOLD 0x0033 |
117 | #define mmSDMA0_BA_THRESHOLD_BASE_IDX 0 |
118 | #define mmSDMA0_ID 0x0034 |
119 | #define mmSDMA0_ID_BASE_IDX 0 |
120 | #define mmSDMA0_VERSION 0x0035 |
121 | #define mmSDMA0_VERSION_BASE_IDX 0 |
122 | #define mmSDMA0_EDC_COUNTER 0x0036 |
123 | #define mmSDMA0_EDC_COUNTER_BASE_IDX 0 |
124 | #define mmSDMA0_EDC_COUNTER_CLEAR 0x0037 |
125 | #define mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX 0 |
126 | #define mmSDMA0_STATUS2_REG 0x0038 |
127 | #define mmSDMA0_STATUS2_REG_BASE_IDX 0 |
128 | #define mmSDMA0_ATOMIC_CNTL 0x0039 |
129 | #define mmSDMA0_ATOMIC_CNTL_BASE_IDX 0 |
130 | #define mmSDMA0_ATOMIC_PREOP_LO 0x003a |
131 | #define mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0 |
132 | #define mmSDMA0_ATOMIC_PREOP_HI 0x003b |
133 | #define mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0 |
134 | #define mmSDMA0_UTCL1_CNTL 0x003c |
135 | #define mmSDMA0_UTCL1_CNTL_BASE_IDX 0 |
136 | #define mmSDMA0_UTCL1_WATERMK 0x003d |
137 | #define mmSDMA0_UTCL1_WATERMK_BASE_IDX 0 |
138 | #define mmSDMA0_UTCL1_RD_STATUS 0x003e |
139 | #define mmSDMA0_UTCL1_RD_STATUS_BASE_IDX 0 |
140 | #define mmSDMA0_UTCL1_WR_STATUS 0x003f |
141 | #define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX 0 |
142 | #define mmSDMA0_UTCL1_INV0 0x0040 |
143 | #define mmSDMA0_UTCL1_INV0_BASE_IDX 0 |
144 | #define mmSDMA0_UTCL1_INV1 0x0041 |
145 | #define mmSDMA0_UTCL1_INV1_BASE_IDX 0 |
146 | #define mmSDMA0_UTCL1_INV2 0x0042 |
147 | #define mmSDMA0_UTCL1_INV2_BASE_IDX 0 |
148 | #define mmSDMA0_UTCL1_RD_XNACK0 0x0043 |
149 | #define mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX 0 |
150 | #define mmSDMA0_UTCL1_RD_XNACK1 0x0044 |
151 | #define mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX 0 |
152 | #define mmSDMA0_UTCL1_WR_XNACK0 0x0045 |
153 | #define mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX 0 |
154 | #define mmSDMA0_UTCL1_WR_XNACK1 0x0046 |
155 | #define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX 0 |
156 | #define mmSDMA0_UTCL1_TIMEOUT 0x0047 |
157 | #define mmSDMA0_UTCL1_TIMEOUT_BASE_IDX 0 |
158 | #define mmSDMA0_UTCL1_PAGE 0x0048 |
159 | #define mmSDMA0_UTCL1_PAGE_BASE_IDX 0 |
160 | #define mmSDMA0_POWER_CNTL_IDLE 0x0049 |
161 | #define mmSDMA0_POWER_CNTL_IDLE_BASE_IDX 0 |
162 | #define mmSDMA0_RELAX_ORDERING_LUT 0x004a |
163 | #define mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX 0 |
164 | #define mmSDMA0_CHICKEN_BITS_2 0x004b |
165 | #define mmSDMA0_CHICKEN_BITS_2_BASE_IDX 0 |
166 | #define mmSDMA0_STATUS3_REG 0x004c |
167 | #define mmSDMA0_STATUS3_REG_BASE_IDX 0 |
168 | #define mmSDMA0_PHYSICAL_ADDR_LO 0x004d |
169 | #define mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX 0 |
170 | #define mmSDMA0_PHYSICAL_ADDR_HI 0x004e |
171 | #define mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX 0 |
172 | #define mmSDMA0_PHASE2_QUANTUM 0x004f |
173 | #define mmSDMA0_PHASE2_QUANTUM_BASE_IDX 0 |
174 | #define mmSDMA0_ERROR_LOG 0x0050 |
175 | #define mmSDMA0_ERROR_LOG_BASE_IDX 0 |
176 | #define mmSDMA0_PUB_DUMMY_REG0 0x0051 |
177 | #define mmSDMA0_PUB_DUMMY_REG0_BASE_IDX 0 |
178 | #define mmSDMA0_PUB_DUMMY_REG1 0x0052 |
179 | #define mmSDMA0_PUB_DUMMY_REG1_BASE_IDX 0 |
180 | #define mmSDMA0_PUB_DUMMY_REG2 0x0053 |
181 | #define mmSDMA0_PUB_DUMMY_REG2_BASE_IDX 0 |
182 | #define mmSDMA0_PUB_DUMMY_REG3 0x0054 |
183 | #define mmSDMA0_PUB_DUMMY_REG3_BASE_IDX 0 |
184 | #define mmSDMA0_F32_COUNTER 0x0055 |
185 | #define mmSDMA0_F32_COUNTER_BASE_IDX 0 |
186 | #define mmSDMA0_UNBREAKABLE 0x0056 |
187 | #define mmSDMA0_UNBREAKABLE_BASE_IDX 0 |
188 | #define mmSDMA0_PERFMON_CNTL 0x0057 |
189 | #define mmSDMA0_PERFMON_CNTL_BASE_IDX 0 |
190 | #define mmSDMA0_PERFCOUNTER0_RESULT 0x0058 |
191 | #define mmSDMA0_PERFCOUNTER0_RESULT_BASE_IDX 0 |
192 | #define mmSDMA0_PERFCOUNTER1_RESULT 0x0059 |
193 | #define mmSDMA0_PERFCOUNTER1_RESULT_BASE_IDX 0 |
194 | #define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE 0x005a |
195 | #define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0 |
196 | #define mmSDMA0_CRD_CNTL 0x005b |
197 | #define mmSDMA0_CRD_CNTL_BASE_IDX 0 |
198 | #define mmSDMA0_GPU_IOV_VIOLATION_LOG 0x005d |
199 | #define mmSDMA0_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 |
200 | #define mmSDMA0_ULV_CNTL 0x005e |
201 | #define mmSDMA0_ULV_CNTL_BASE_IDX 0 |
202 | #define mmSDMA0_EA_DBIT_ADDR_DATA 0x0060 |
203 | #define mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX 0 |
204 | #define mmSDMA0_EA_DBIT_ADDR_INDEX 0x0061 |
205 | #define mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX 0 |
206 | #define mmSDMA0_GPU_IOV_VIOLATION_LOG2 0x0062 |
207 | #define mmSDMA0_GPU_IOV_VIOLATION_LOG2_BASE_IDX 0 |
208 | #define mmSDMA0_GFX_RB_CNTL 0x0080 |
209 | #define mmSDMA0_GFX_RB_CNTL_BASE_IDX 0 |
210 | #define mmSDMA0_GFX_RB_BASE 0x0081 |
211 | #define mmSDMA0_GFX_RB_BASE_BASE_IDX 0 |
212 | #define mmSDMA0_GFX_RB_BASE_HI 0x0082 |
213 | #define mmSDMA0_GFX_RB_BASE_HI_BASE_IDX 0 |
214 | #define mmSDMA0_GFX_RB_RPTR 0x0083 |
215 | #define mmSDMA0_GFX_RB_RPTR_BASE_IDX 0 |
216 | #define mmSDMA0_GFX_RB_RPTR_HI 0x0084 |
217 | #define mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX 0 |
218 | #define mmSDMA0_GFX_RB_WPTR 0x0085 |
219 | #define mmSDMA0_GFX_RB_WPTR_BASE_IDX 0 |
220 | #define mmSDMA0_GFX_RB_WPTR_HI 0x0086 |
221 | #define mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX 0 |
222 | #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087 |
223 | #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
224 | #define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x0088 |
225 | #define mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 |
226 | #define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089 |
227 | #define mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 |
228 | #define mmSDMA0_GFX_IB_CNTL 0x008a |
229 | #define mmSDMA0_GFX_IB_CNTL_BASE_IDX 0 |
230 | #define mmSDMA0_GFX_IB_RPTR 0x008b |
231 | #define mmSDMA0_GFX_IB_RPTR_BASE_IDX 0 |
232 | #define mmSDMA0_GFX_IB_OFFSET 0x008c |
233 | #define mmSDMA0_GFX_IB_OFFSET_BASE_IDX 0 |
234 | #define mmSDMA0_GFX_IB_BASE_LO 0x008d |
235 | #define mmSDMA0_GFX_IB_BASE_LO_BASE_IDX 0 |
236 | #define mmSDMA0_GFX_IB_BASE_HI 0x008e |
237 | #define mmSDMA0_GFX_IB_BASE_HI_BASE_IDX 0 |
238 | #define mmSDMA0_GFX_IB_SIZE 0x008f |
239 | #define mmSDMA0_GFX_IB_SIZE_BASE_IDX 0 |
240 | #define mmSDMA0_GFX_SKIP_CNTL 0x0090 |
241 | #define mmSDMA0_GFX_SKIP_CNTL_BASE_IDX 0 |
242 | #define mmSDMA0_GFX_CONTEXT_STATUS 0x0091 |
243 | #define mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX 0 |
244 | #define mmSDMA0_GFX_DOORBELL 0x0092 |
245 | #define mmSDMA0_GFX_DOORBELL_BASE_IDX 0 |
246 | #define mmSDMA0_GFX_CONTEXT_CNTL 0x0093 |
247 | #define mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX 0 |
248 | #define mmSDMA0_GFX_STATUS 0x00a8 |
249 | #define mmSDMA0_GFX_STATUS_BASE_IDX 0 |
250 | #define mmSDMA0_GFX_DOORBELL_LOG 0x00a9 |
251 | #define mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX 0 |
252 | #define mmSDMA0_GFX_WATERMARK 0x00aa |
253 | #define mmSDMA0_GFX_WATERMARK_BASE_IDX 0 |
254 | #define mmSDMA0_GFX_DOORBELL_OFFSET 0x00ab |
255 | #define mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX 0 |
256 | #define mmSDMA0_GFX_CSA_ADDR_LO 0x00ac |
257 | #define mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX 0 |
258 | #define mmSDMA0_GFX_CSA_ADDR_HI 0x00ad |
259 | #define mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX 0 |
260 | #define mmSDMA0_GFX_IB_SUB_REMAIN 0x00af |
261 | #define mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX 0 |
262 | #define mmSDMA0_GFX_PREEMPT 0x00b0 |
263 | #define mmSDMA0_GFX_PREEMPT_BASE_IDX 0 |
264 | #define mmSDMA0_GFX_DUMMY_REG 0x00b1 |
265 | #define mmSDMA0_GFX_DUMMY_REG_BASE_IDX 0 |
266 | #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 |
267 | #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
268 | #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 |
269 | #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
270 | #define mmSDMA0_GFX_RB_AQL_CNTL 0x00b4 |
271 | #define mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX 0 |
272 | #define mmSDMA0_GFX_MINOR_PTR_UPDATE 0x00b5 |
273 | #define mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 |
274 | #define mmSDMA0_GFX_MIDCMD_DATA0 0x00c0 |
275 | #define mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX 0 |
276 | #define mmSDMA0_GFX_MIDCMD_DATA1 0x00c1 |
277 | #define mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX 0 |
278 | #define mmSDMA0_GFX_MIDCMD_DATA2 0x00c2 |
279 | #define mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX 0 |
280 | #define mmSDMA0_GFX_MIDCMD_DATA3 0x00c3 |
281 | #define mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX 0 |
282 | #define mmSDMA0_GFX_MIDCMD_DATA4 0x00c4 |
283 | #define mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX 0 |
284 | #define mmSDMA0_GFX_MIDCMD_DATA5 0x00c5 |
285 | #define mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX 0 |
286 | #define mmSDMA0_GFX_MIDCMD_DATA6 0x00c6 |
287 | #define mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX 0 |
288 | #define mmSDMA0_GFX_MIDCMD_DATA7 0x00c7 |
289 | #define mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX 0 |
290 | #define mmSDMA0_GFX_MIDCMD_DATA8 0x00c8 |
291 | #define mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX 0 |
292 | #define mmSDMA0_GFX_MIDCMD_CNTL 0x00c9 |
293 | #define mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX 0 |
294 | #define mmSDMA0_PAGE_RB_CNTL 0x00d8 |
295 | #define mmSDMA0_PAGE_RB_CNTL_BASE_IDX 0 |
296 | #define mmSDMA0_PAGE_RB_BASE 0x00d9 |
297 | #define mmSDMA0_PAGE_RB_BASE_BASE_IDX 0 |
298 | #define mmSDMA0_PAGE_RB_BASE_HI 0x00da |
299 | #define mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX 0 |
300 | #define mmSDMA0_PAGE_RB_RPTR 0x00db |
301 | #define mmSDMA0_PAGE_RB_RPTR_BASE_IDX 0 |
302 | #define mmSDMA0_PAGE_RB_RPTR_HI 0x00dc |
303 | #define mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX 0 |
304 | #define mmSDMA0_PAGE_RB_WPTR 0x00dd |
305 | #define mmSDMA0_PAGE_RB_WPTR_BASE_IDX 0 |
306 | #define mmSDMA0_PAGE_RB_WPTR_HI 0x00de |
307 | #define mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX 0 |
308 | #define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL 0x00df |
309 | #define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
310 | #define mmSDMA0_PAGE_RB_RPTR_ADDR_HI 0x00e0 |
311 | #define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 |
312 | #define mmSDMA0_PAGE_RB_RPTR_ADDR_LO 0x00e1 |
313 | #define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 |
314 | #define mmSDMA0_PAGE_IB_CNTL 0x00e2 |
315 | #define mmSDMA0_PAGE_IB_CNTL_BASE_IDX 0 |
316 | #define mmSDMA0_PAGE_IB_RPTR 0x00e3 |
317 | #define mmSDMA0_PAGE_IB_RPTR_BASE_IDX 0 |
318 | #define mmSDMA0_PAGE_IB_OFFSET 0x00e4 |
319 | #define mmSDMA0_PAGE_IB_OFFSET_BASE_IDX 0 |
320 | #define mmSDMA0_PAGE_IB_BASE_LO 0x00e5 |
321 | #define mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX 0 |
322 | #define mmSDMA0_PAGE_IB_BASE_HI 0x00e6 |
323 | #define mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX 0 |
324 | #define mmSDMA0_PAGE_IB_SIZE 0x00e7 |
325 | #define mmSDMA0_PAGE_IB_SIZE_BASE_IDX 0 |
326 | #define mmSDMA0_PAGE_SKIP_CNTL 0x00e8 |
327 | #define mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX 0 |
328 | #define mmSDMA0_PAGE_CONTEXT_STATUS 0x00e9 |
329 | #define mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX 0 |
330 | #define mmSDMA0_PAGE_DOORBELL 0x00ea |
331 | #define mmSDMA0_PAGE_DOORBELL_BASE_IDX 0 |
332 | #define mmSDMA0_PAGE_STATUS 0x0100 |
333 | #define mmSDMA0_PAGE_STATUS_BASE_IDX 0 |
334 | #define mmSDMA0_PAGE_DOORBELL_LOG 0x0101 |
335 | #define mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX 0 |
336 | #define mmSDMA0_PAGE_WATERMARK 0x0102 |
337 | #define mmSDMA0_PAGE_WATERMARK_BASE_IDX 0 |
338 | #define mmSDMA0_PAGE_DOORBELL_OFFSET 0x0103 |
339 | #define mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX 0 |
340 | #define mmSDMA0_PAGE_CSA_ADDR_LO 0x0104 |
341 | #define mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX 0 |
342 | #define mmSDMA0_PAGE_CSA_ADDR_HI 0x0105 |
343 | #define mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX 0 |
344 | #define mmSDMA0_PAGE_IB_SUB_REMAIN 0x0107 |
345 | #define mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX 0 |
346 | #define mmSDMA0_PAGE_PREEMPT 0x0108 |
347 | #define mmSDMA0_PAGE_PREEMPT_BASE_IDX 0 |
348 | #define mmSDMA0_PAGE_DUMMY_REG 0x0109 |
349 | #define mmSDMA0_PAGE_DUMMY_REG_BASE_IDX 0 |
350 | #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 0x010a |
351 | #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
352 | #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 0x010b |
353 | #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
354 | #define mmSDMA0_PAGE_RB_AQL_CNTL 0x010c |
355 | #define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX 0 |
356 | #define mmSDMA0_PAGE_MINOR_PTR_UPDATE 0x010d |
357 | #define mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 |
358 | #define mmSDMA0_PAGE_MIDCMD_DATA0 0x0118 |
359 | #define mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX 0 |
360 | #define mmSDMA0_PAGE_MIDCMD_DATA1 0x0119 |
361 | #define mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX 0 |
362 | #define mmSDMA0_PAGE_MIDCMD_DATA2 0x011a |
363 | #define mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX 0 |
364 | #define mmSDMA0_PAGE_MIDCMD_DATA3 0x011b |
365 | #define mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX 0 |
366 | #define mmSDMA0_PAGE_MIDCMD_DATA4 0x011c |
367 | #define mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX 0 |
368 | #define mmSDMA0_PAGE_MIDCMD_DATA5 0x011d |
369 | #define mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX 0 |
370 | #define mmSDMA0_PAGE_MIDCMD_DATA6 0x011e |
371 | #define mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX 0 |
372 | #define mmSDMA0_PAGE_MIDCMD_DATA7 0x011f |
373 | #define mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX 0 |
374 | #define mmSDMA0_PAGE_MIDCMD_DATA8 0x0120 |
375 | #define mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX 0 |
376 | #define mmSDMA0_PAGE_MIDCMD_CNTL 0x0121 |
377 | #define mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX 0 |
378 | #define mmSDMA0_RLC0_RB_CNTL 0x0130 |
379 | #define mmSDMA0_RLC0_RB_CNTL_BASE_IDX 0 |
380 | #define mmSDMA0_RLC0_RB_BASE 0x0131 |
381 | #define mmSDMA0_RLC0_RB_BASE_BASE_IDX 0 |
382 | #define mmSDMA0_RLC0_RB_BASE_HI 0x0132 |
383 | #define mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX 0 |
384 | #define mmSDMA0_RLC0_RB_RPTR 0x0133 |
385 | #define mmSDMA0_RLC0_RB_RPTR_BASE_IDX 0 |
386 | #define mmSDMA0_RLC0_RB_RPTR_HI 0x0134 |
387 | #define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX 0 |
388 | #define mmSDMA0_RLC0_RB_WPTR 0x0135 |
389 | #define mmSDMA0_RLC0_RB_WPTR_BASE_IDX 0 |
390 | #define mmSDMA0_RLC0_RB_WPTR_HI 0x0136 |
391 | #define mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX 0 |
392 | #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0137 |
393 | #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
394 | #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x0138 |
395 | #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 |
396 | #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x0139 |
397 | #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 |
398 | #define mmSDMA0_RLC0_IB_CNTL 0x013a |
399 | #define mmSDMA0_RLC0_IB_CNTL_BASE_IDX 0 |
400 | #define mmSDMA0_RLC0_IB_RPTR 0x013b |
401 | #define mmSDMA0_RLC0_IB_RPTR_BASE_IDX 0 |
402 | #define mmSDMA0_RLC0_IB_OFFSET 0x013c |
403 | #define mmSDMA0_RLC0_IB_OFFSET_BASE_IDX 0 |
404 | #define mmSDMA0_RLC0_IB_BASE_LO 0x013d |
405 | #define mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX 0 |
406 | #define mmSDMA0_RLC0_IB_BASE_HI 0x013e |
407 | #define mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX 0 |
408 | #define mmSDMA0_RLC0_IB_SIZE 0x013f |
409 | #define mmSDMA0_RLC0_IB_SIZE_BASE_IDX 0 |
410 | #define mmSDMA0_RLC0_SKIP_CNTL 0x0140 |
411 | #define mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX 0 |
412 | #define mmSDMA0_RLC0_CONTEXT_STATUS 0x0141 |
413 | #define mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX 0 |
414 | #define mmSDMA0_RLC0_DOORBELL 0x0142 |
415 | #define mmSDMA0_RLC0_DOORBELL_BASE_IDX 0 |
416 | #define mmSDMA0_RLC0_STATUS 0x0158 |
417 | #define mmSDMA0_RLC0_STATUS_BASE_IDX 0 |
418 | #define mmSDMA0_RLC0_DOORBELL_LOG 0x0159 |
419 | #define mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX 0 |
420 | #define mmSDMA0_RLC0_WATERMARK 0x015a |
421 | #define mmSDMA0_RLC0_WATERMARK_BASE_IDX 0 |
422 | #define mmSDMA0_RLC0_DOORBELL_OFFSET 0x015b |
423 | #define mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX 0 |
424 | #define mmSDMA0_RLC0_CSA_ADDR_LO 0x015c |
425 | #define mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX 0 |
426 | #define mmSDMA0_RLC0_CSA_ADDR_HI 0x015d |
427 | #define mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX 0 |
428 | #define mmSDMA0_RLC0_IB_SUB_REMAIN 0x015f |
429 | #define mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX 0 |
430 | #define mmSDMA0_RLC0_PREEMPT 0x0160 |
431 | #define mmSDMA0_RLC0_PREEMPT_BASE_IDX 0 |
432 | #define mmSDMA0_RLC0_DUMMY_REG 0x0161 |
433 | #define mmSDMA0_RLC0_DUMMY_REG_BASE_IDX 0 |
434 | #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x0162 |
435 | #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
436 | #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x0163 |
437 | #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
438 | #define mmSDMA0_RLC0_RB_AQL_CNTL 0x0164 |
439 | #define mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX 0 |
440 | #define mmSDMA0_RLC0_MINOR_PTR_UPDATE 0x0165 |
441 | #define mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 |
442 | #define mmSDMA0_RLC0_MIDCMD_DATA0 0x0170 |
443 | #define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX 0 |
444 | #define mmSDMA0_RLC0_MIDCMD_DATA1 0x0171 |
445 | #define mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX 0 |
446 | #define mmSDMA0_RLC0_MIDCMD_DATA2 0x0172 |
447 | #define mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX 0 |
448 | #define mmSDMA0_RLC0_MIDCMD_DATA3 0x0173 |
449 | #define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX 0 |
450 | #define mmSDMA0_RLC0_MIDCMD_DATA4 0x0174 |
451 | #define mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX 0 |
452 | #define mmSDMA0_RLC0_MIDCMD_DATA5 0x0175 |
453 | #define mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX 0 |
454 | #define mmSDMA0_RLC0_MIDCMD_DATA6 0x0176 |
455 | #define mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX 0 |
456 | #define mmSDMA0_RLC0_MIDCMD_DATA7 0x0177 |
457 | #define mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX 0 |
458 | #define mmSDMA0_RLC0_MIDCMD_DATA8 0x0178 |
459 | #define mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX 0 |
460 | #define mmSDMA0_RLC0_MIDCMD_CNTL 0x0179 |
461 | #define mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX 0 |
462 | #define mmSDMA0_RLC1_RB_CNTL 0x0188 |
463 | #define mmSDMA0_RLC1_RB_CNTL_BASE_IDX 0 |
464 | #define mmSDMA0_RLC1_RB_BASE 0x0189 |
465 | #define mmSDMA0_RLC1_RB_BASE_BASE_IDX 0 |
466 | #define mmSDMA0_RLC1_RB_BASE_HI 0x018a |
467 | #define mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX 0 |
468 | #define mmSDMA0_RLC1_RB_RPTR 0x018b |
469 | #define mmSDMA0_RLC1_RB_RPTR_BASE_IDX 0 |
470 | #define mmSDMA0_RLC1_RB_RPTR_HI 0x018c |
471 | #define mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX 0 |
472 | #define mmSDMA0_RLC1_RB_WPTR 0x018d |
473 | #define mmSDMA0_RLC1_RB_WPTR_BASE_IDX 0 |
474 | #define mmSDMA0_RLC1_RB_WPTR_HI 0x018e |
475 | #define mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX 0 |
476 | #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x018f |
477 | #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
478 | #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x0190 |
479 | #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 |
480 | #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x0191 |
481 | #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 |
482 | #define mmSDMA0_RLC1_IB_CNTL 0x0192 |
483 | #define mmSDMA0_RLC1_IB_CNTL_BASE_IDX 0 |
484 | #define mmSDMA0_RLC1_IB_RPTR 0x0193 |
485 | #define mmSDMA0_RLC1_IB_RPTR_BASE_IDX 0 |
486 | #define mmSDMA0_RLC1_IB_OFFSET 0x0194 |
487 | #define mmSDMA0_RLC1_IB_OFFSET_BASE_IDX 0 |
488 | #define mmSDMA0_RLC1_IB_BASE_LO 0x0195 |
489 | #define mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX 0 |
490 | #define mmSDMA0_RLC1_IB_BASE_HI 0x0196 |
491 | #define mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX 0 |
492 | #define mmSDMA0_RLC1_IB_SIZE 0x0197 |
493 | #define mmSDMA0_RLC1_IB_SIZE_BASE_IDX 0 |
494 | #define mmSDMA0_RLC1_SKIP_CNTL 0x0198 |
495 | #define mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX 0 |
496 | #define mmSDMA0_RLC1_CONTEXT_STATUS 0x0199 |
497 | #define mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX 0 |
498 | #define mmSDMA0_RLC1_DOORBELL 0x019a |
499 | #define mmSDMA0_RLC1_DOORBELL_BASE_IDX 0 |
500 | #define mmSDMA0_RLC1_STATUS 0x01b0 |
501 | #define mmSDMA0_RLC1_STATUS_BASE_IDX 0 |
502 | #define mmSDMA0_RLC1_DOORBELL_LOG 0x01b1 |
503 | #define mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX 0 |
504 | #define mmSDMA0_RLC1_WATERMARK 0x01b2 |
505 | #define mmSDMA0_RLC1_WATERMARK_BASE_IDX 0 |
506 | #define mmSDMA0_RLC1_DOORBELL_OFFSET 0x01b3 |
507 | #define mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX 0 |
508 | #define mmSDMA0_RLC1_CSA_ADDR_LO 0x01b4 |
509 | #define mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX 0 |
510 | #define mmSDMA0_RLC1_CSA_ADDR_HI 0x01b5 |
511 | #define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX 0 |
512 | #define mmSDMA0_RLC1_IB_SUB_REMAIN 0x01b7 |
513 | #define mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX 0 |
514 | #define mmSDMA0_RLC1_PREEMPT 0x01b8 |
515 | #define mmSDMA0_RLC1_PREEMPT_BASE_IDX 0 |
516 | #define mmSDMA0_RLC1_DUMMY_REG 0x01b9 |
517 | #define mmSDMA0_RLC1_DUMMY_REG_BASE_IDX 0 |
518 | #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x01ba |
519 | #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
520 | #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x01bb |
521 | #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
522 | #define mmSDMA0_RLC1_RB_AQL_CNTL 0x01bc |
523 | #define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX 0 |
524 | #define mmSDMA0_RLC1_MINOR_PTR_UPDATE 0x01bd |
525 | #define mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 |
526 | #define mmSDMA0_RLC1_MIDCMD_DATA0 0x01c8 |
527 | #define mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX 0 |
528 | #define mmSDMA0_RLC1_MIDCMD_DATA1 0x01c9 |
529 | #define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX 0 |
530 | #define mmSDMA0_RLC1_MIDCMD_DATA2 0x01ca |
531 | #define mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX 0 |
532 | #define mmSDMA0_RLC1_MIDCMD_DATA3 0x01cb |
533 | #define mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX 0 |
534 | #define mmSDMA0_RLC1_MIDCMD_DATA4 0x01cc |
535 | #define mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX 0 |
536 | #define mmSDMA0_RLC1_MIDCMD_DATA5 0x01cd |
537 | #define mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX 0 |
538 | #define mmSDMA0_RLC1_MIDCMD_DATA6 0x01ce |
539 | #define mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX 0 |
540 | #define mmSDMA0_RLC1_MIDCMD_DATA7 0x01cf |
541 | #define mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX 0 |
542 | #define mmSDMA0_RLC1_MIDCMD_DATA8 0x01d0 |
543 | #define mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX 0 |
544 | #define mmSDMA0_RLC1_MIDCMD_CNTL 0x01d1 |
545 | #define mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX 0 |
546 | #define mmSDMA0_RLC2_RB_CNTL 0x01e0 |
547 | #define mmSDMA0_RLC2_RB_CNTL_BASE_IDX 0 |
548 | #define mmSDMA0_RLC2_RB_BASE 0x01e1 |
549 | #define mmSDMA0_RLC2_RB_BASE_BASE_IDX 0 |
550 | #define mmSDMA0_RLC2_RB_BASE_HI 0x01e2 |
551 | #define mmSDMA0_RLC2_RB_BASE_HI_BASE_IDX 0 |
552 | #define mmSDMA0_RLC2_RB_RPTR 0x01e3 |
553 | #define mmSDMA0_RLC2_RB_RPTR_BASE_IDX 0 |
554 | #define mmSDMA0_RLC2_RB_RPTR_HI 0x01e4 |
555 | #define mmSDMA0_RLC2_RB_RPTR_HI_BASE_IDX 0 |
556 | #define mmSDMA0_RLC2_RB_WPTR 0x01e5 |
557 | #define mmSDMA0_RLC2_RB_WPTR_BASE_IDX 0 |
558 | #define mmSDMA0_RLC2_RB_WPTR_HI 0x01e6 |
559 | #define mmSDMA0_RLC2_RB_WPTR_HI_BASE_IDX 0 |
560 | #define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL 0x01e7 |
561 | #define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
562 | #define mmSDMA0_RLC2_RB_RPTR_ADDR_HI 0x01e8 |
563 | #define mmSDMA0_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0 |
564 | #define mmSDMA0_RLC2_RB_RPTR_ADDR_LO 0x01e9 |
565 | #define mmSDMA0_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0 |
566 | #define mmSDMA0_RLC2_IB_CNTL 0x01ea |
567 | #define mmSDMA0_RLC2_IB_CNTL_BASE_IDX 0 |
568 | #define mmSDMA0_RLC2_IB_RPTR 0x01eb |
569 | #define mmSDMA0_RLC2_IB_RPTR_BASE_IDX 0 |
570 | #define mmSDMA0_RLC2_IB_OFFSET 0x01ec |
571 | #define mmSDMA0_RLC2_IB_OFFSET_BASE_IDX 0 |
572 | #define mmSDMA0_RLC2_IB_BASE_LO 0x01ed |
573 | #define mmSDMA0_RLC2_IB_BASE_LO_BASE_IDX 0 |
574 | #define mmSDMA0_RLC2_IB_BASE_HI 0x01ee |
575 | #define mmSDMA0_RLC2_IB_BASE_HI_BASE_IDX 0 |
576 | #define mmSDMA0_RLC2_IB_SIZE 0x01ef |
577 | #define mmSDMA0_RLC2_IB_SIZE_BASE_IDX 0 |
578 | #define mmSDMA0_RLC2_SKIP_CNTL 0x01f0 |
579 | #define mmSDMA0_RLC2_SKIP_CNTL_BASE_IDX 0 |
580 | #define mmSDMA0_RLC2_CONTEXT_STATUS 0x01f1 |
581 | #define mmSDMA0_RLC2_CONTEXT_STATUS_BASE_IDX 0 |
582 | #define mmSDMA0_RLC2_DOORBELL 0x01f2 |
583 | #define mmSDMA0_RLC2_DOORBELL_BASE_IDX 0 |
584 | #define mmSDMA0_RLC2_STATUS 0x0208 |
585 | #define mmSDMA0_RLC2_STATUS_BASE_IDX 0 |
586 | #define mmSDMA0_RLC2_DOORBELL_LOG 0x0209 |
587 | #define mmSDMA0_RLC2_DOORBELL_LOG_BASE_IDX 0 |
588 | #define mmSDMA0_RLC2_WATERMARK 0x020a |
589 | #define mmSDMA0_RLC2_WATERMARK_BASE_IDX 0 |
590 | #define mmSDMA0_RLC2_DOORBELL_OFFSET 0x020b |
591 | #define mmSDMA0_RLC2_DOORBELL_OFFSET_BASE_IDX 0 |
592 | #define mmSDMA0_RLC2_CSA_ADDR_LO 0x020c |
593 | #define mmSDMA0_RLC2_CSA_ADDR_LO_BASE_IDX 0 |
594 | #define mmSDMA0_RLC2_CSA_ADDR_HI 0x020d |
595 | #define mmSDMA0_RLC2_CSA_ADDR_HI_BASE_IDX 0 |
596 | #define mmSDMA0_RLC2_IB_SUB_REMAIN 0x020f |
597 | #define mmSDMA0_RLC2_IB_SUB_REMAIN_BASE_IDX 0 |
598 | #define mmSDMA0_RLC2_PREEMPT 0x0210 |
599 | #define mmSDMA0_RLC2_PREEMPT_BASE_IDX 0 |
600 | #define mmSDMA0_RLC2_DUMMY_REG 0x0211 |
601 | #define mmSDMA0_RLC2_DUMMY_REG_BASE_IDX 0 |
602 | #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI 0x0212 |
603 | #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
604 | #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO 0x0213 |
605 | #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
606 | #define mmSDMA0_RLC2_RB_AQL_CNTL 0x0214 |
607 | #define mmSDMA0_RLC2_RB_AQL_CNTL_BASE_IDX 0 |
608 | #define mmSDMA0_RLC2_MINOR_PTR_UPDATE 0x0215 |
609 | #define mmSDMA0_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0 |
610 | #define mmSDMA0_RLC2_MIDCMD_DATA0 0x0220 |
611 | #define mmSDMA0_RLC2_MIDCMD_DATA0_BASE_IDX 0 |
612 | #define mmSDMA0_RLC2_MIDCMD_DATA1 0x0221 |
613 | #define mmSDMA0_RLC2_MIDCMD_DATA1_BASE_IDX 0 |
614 | #define mmSDMA0_RLC2_MIDCMD_DATA2 0x0222 |
615 | #define mmSDMA0_RLC2_MIDCMD_DATA2_BASE_IDX 0 |
616 | #define mmSDMA0_RLC2_MIDCMD_DATA3 0x0223 |
617 | #define mmSDMA0_RLC2_MIDCMD_DATA3_BASE_IDX 0 |
618 | #define mmSDMA0_RLC2_MIDCMD_DATA4 0x0224 |
619 | #define mmSDMA0_RLC2_MIDCMD_DATA4_BASE_IDX 0 |
620 | #define mmSDMA0_RLC2_MIDCMD_DATA5 0x0225 |
621 | #define mmSDMA0_RLC2_MIDCMD_DATA5_BASE_IDX 0 |
622 | #define mmSDMA0_RLC2_MIDCMD_DATA6 0x0226 |
623 | #define mmSDMA0_RLC2_MIDCMD_DATA6_BASE_IDX 0 |
624 | #define mmSDMA0_RLC2_MIDCMD_DATA7 0x0227 |
625 | #define mmSDMA0_RLC2_MIDCMD_DATA7_BASE_IDX 0 |
626 | #define mmSDMA0_RLC2_MIDCMD_DATA8 0x0228 |
627 | #define mmSDMA0_RLC2_MIDCMD_DATA8_BASE_IDX 0 |
628 | #define mmSDMA0_RLC2_MIDCMD_CNTL 0x0229 |
629 | #define mmSDMA0_RLC2_MIDCMD_CNTL_BASE_IDX 0 |
630 | #define mmSDMA0_RLC3_RB_CNTL 0x0238 |
631 | #define mmSDMA0_RLC3_RB_CNTL_BASE_IDX 0 |
632 | #define mmSDMA0_RLC3_RB_BASE 0x0239 |
633 | #define mmSDMA0_RLC3_RB_BASE_BASE_IDX 0 |
634 | #define mmSDMA0_RLC3_RB_BASE_HI 0x023a |
635 | #define mmSDMA0_RLC3_RB_BASE_HI_BASE_IDX 0 |
636 | #define mmSDMA0_RLC3_RB_RPTR 0x023b |
637 | #define mmSDMA0_RLC3_RB_RPTR_BASE_IDX 0 |
638 | #define mmSDMA0_RLC3_RB_RPTR_HI 0x023c |
639 | #define mmSDMA0_RLC3_RB_RPTR_HI_BASE_IDX 0 |
640 | #define mmSDMA0_RLC3_RB_WPTR 0x023d |
641 | #define mmSDMA0_RLC3_RB_WPTR_BASE_IDX 0 |
642 | #define mmSDMA0_RLC3_RB_WPTR_HI 0x023e |
643 | #define mmSDMA0_RLC3_RB_WPTR_HI_BASE_IDX 0 |
644 | #define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL 0x023f |
645 | #define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
646 | #define mmSDMA0_RLC3_RB_RPTR_ADDR_HI 0x0240 |
647 | #define mmSDMA0_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0 |
648 | #define mmSDMA0_RLC3_RB_RPTR_ADDR_LO 0x0241 |
649 | #define mmSDMA0_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0 |
650 | #define mmSDMA0_RLC3_IB_CNTL 0x0242 |
651 | #define mmSDMA0_RLC3_IB_CNTL_BASE_IDX 0 |
652 | #define mmSDMA0_RLC3_IB_RPTR 0x0243 |
653 | #define mmSDMA0_RLC3_IB_RPTR_BASE_IDX 0 |
654 | #define mmSDMA0_RLC3_IB_OFFSET 0x0244 |
655 | #define mmSDMA0_RLC3_IB_OFFSET_BASE_IDX 0 |
656 | #define mmSDMA0_RLC3_IB_BASE_LO 0x0245 |
657 | #define mmSDMA0_RLC3_IB_BASE_LO_BASE_IDX 0 |
658 | #define mmSDMA0_RLC3_IB_BASE_HI 0x0246 |
659 | #define mmSDMA0_RLC3_IB_BASE_HI_BASE_IDX 0 |
660 | #define mmSDMA0_RLC3_IB_SIZE 0x0247 |
661 | #define mmSDMA0_RLC3_IB_SIZE_BASE_IDX 0 |
662 | #define mmSDMA0_RLC3_SKIP_CNTL 0x0248 |
663 | #define mmSDMA0_RLC3_SKIP_CNTL_BASE_IDX 0 |
664 | #define mmSDMA0_RLC3_CONTEXT_STATUS 0x0249 |
665 | #define mmSDMA0_RLC3_CONTEXT_STATUS_BASE_IDX 0 |
666 | #define mmSDMA0_RLC3_DOORBELL 0x024a |
667 | #define mmSDMA0_RLC3_DOORBELL_BASE_IDX 0 |
668 | #define mmSDMA0_RLC3_STATUS 0x0260 |
669 | #define mmSDMA0_RLC3_STATUS_BASE_IDX 0 |
670 | #define mmSDMA0_RLC3_DOORBELL_LOG 0x0261 |
671 | #define mmSDMA0_RLC3_DOORBELL_LOG_BASE_IDX 0 |
672 | #define mmSDMA0_RLC3_WATERMARK 0x0262 |
673 | #define mmSDMA0_RLC3_WATERMARK_BASE_IDX 0 |
674 | #define mmSDMA0_RLC3_DOORBELL_OFFSET 0x0263 |
675 | #define mmSDMA0_RLC3_DOORBELL_OFFSET_BASE_IDX 0 |
676 | #define mmSDMA0_RLC3_CSA_ADDR_LO 0x0264 |
677 | #define mmSDMA0_RLC3_CSA_ADDR_LO_BASE_IDX 0 |
678 | #define mmSDMA0_RLC3_CSA_ADDR_HI 0x0265 |
679 | #define mmSDMA0_RLC3_CSA_ADDR_HI_BASE_IDX 0 |
680 | #define mmSDMA0_RLC3_IB_SUB_REMAIN 0x0267 |
681 | #define mmSDMA0_RLC3_IB_SUB_REMAIN_BASE_IDX 0 |
682 | #define mmSDMA0_RLC3_PREEMPT 0x0268 |
683 | #define mmSDMA0_RLC3_PREEMPT_BASE_IDX 0 |
684 | #define mmSDMA0_RLC3_DUMMY_REG 0x0269 |
685 | #define mmSDMA0_RLC3_DUMMY_REG_BASE_IDX 0 |
686 | #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI 0x026a |
687 | #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
688 | #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO 0x026b |
689 | #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
690 | #define mmSDMA0_RLC3_RB_AQL_CNTL 0x026c |
691 | #define mmSDMA0_RLC3_RB_AQL_CNTL_BASE_IDX 0 |
692 | #define mmSDMA0_RLC3_MINOR_PTR_UPDATE 0x026d |
693 | #define mmSDMA0_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0 |
694 | #define mmSDMA0_RLC3_MIDCMD_DATA0 0x0278 |
695 | #define mmSDMA0_RLC3_MIDCMD_DATA0_BASE_IDX 0 |
696 | #define mmSDMA0_RLC3_MIDCMD_DATA1 0x0279 |
697 | #define mmSDMA0_RLC3_MIDCMD_DATA1_BASE_IDX 0 |
698 | #define mmSDMA0_RLC3_MIDCMD_DATA2 0x027a |
699 | #define mmSDMA0_RLC3_MIDCMD_DATA2_BASE_IDX 0 |
700 | #define mmSDMA0_RLC3_MIDCMD_DATA3 0x027b |
701 | #define mmSDMA0_RLC3_MIDCMD_DATA3_BASE_IDX 0 |
702 | #define mmSDMA0_RLC3_MIDCMD_DATA4 0x027c |
703 | #define mmSDMA0_RLC3_MIDCMD_DATA4_BASE_IDX 0 |
704 | #define mmSDMA0_RLC3_MIDCMD_DATA5 0x027d |
705 | #define mmSDMA0_RLC3_MIDCMD_DATA5_BASE_IDX 0 |
706 | #define mmSDMA0_RLC3_MIDCMD_DATA6 0x027e |
707 | #define mmSDMA0_RLC3_MIDCMD_DATA6_BASE_IDX 0 |
708 | #define mmSDMA0_RLC3_MIDCMD_DATA7 0x027f |
709 | #define mmSDMA0_RLC3_MIDCMD_DATA7_BASE_IDX 0 |
710 | #define mmSDMA0_RLC3_MIDCMD_DATA8 0x0280 |
711 | #define mmSDMA0_RLC3_MIDCMD_DATA8_BASE_IDX 0 |
712 | #define mmSDMA0_RLC3_MIDCMD_CNTL 0x0281 |
713 | #define mmSDMA0_RLC3_MIDCMD_CNTL_BASE_IDX 0 |
714 | #define mmSDMA0_RLC4_RB_CNTL 0x0290 |
715 | #define mmSDMA0_RLC4_RB_CNTL_BASE_IDX 0 |
716 | #define mmSDMA0_RLC4_RB_BASE 0x0291 |
717 | #define mmSDMA0_RLC4_RB_BASE_BASE_IDX 0 |
718 | #define mmSDMA0_RLC4_RB_BASE_HI 0x0292 |
719 | #define mmSDMA0_RLC4_RB_BASE_HI_BASE_IDX 0 |
720 | #define mmSDMA0_RLC4_RB_RPTR 0x0293 |
721 | #define mmSDMA0_RLC4_RB_RPTR_BASE_IDX 0 |
722 | #define mmSDMA0_RLC4_RB_RPTR_HI 0x0294 |
723 | #define mmSDMA0_RLC4_RB_RPTR_HI_BASE_IDX 0 |
724 | #define mmSDMA0_RLC4_RB_WPTR 0x0295 |
725 | #define mmSDMA0_RLC4_RB_WPTR_BASE_IDX 0 |
726 | #define mmSDMA0_RLC4_RB_WPTR_HI 0x0296 |
727 | #define mmSDMA0_RLC4_RB_WPTR_HI_BASE_IDX 0 |
728 | #define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL 0x0297 |
729 | #define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
730 | #define mmSDMA0_RLC4_RB_RPTR_ADDR_HI 0x0298 |
731 | #define mmSDMA0_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0 |
732 | #define mmSDMA0_RLC4_RB_RPTR_ADDR_LO 0x0299 |
733 | #define mmSDMA0_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0 |
734 | #define mmSDMA0_RLC4_IB_CNTL 0x029a |
735 | #define mmSDMA0_RLC4_IB_CNTL_BASE_IDX 0 |
736 | #define mmSDMA0_RLC4_IB_RPTR 0x029b |
737 | #define mmSDMA0_RLC4_IB_RPTR_BASE_IDX 0 |
738 | #define mmSDMA0_RLC4_IB_OFFSET 0x029c |
739 | #define mmSDMA0_RLC4_IB_OFFSET_BASE_IDX 0 |
740 | #define mmSDMA0_RLC4_IB_BASE_LO 0x029d |
741 | #define mmSDMA0_RLC4_IB_BASE_LO_BASE_IDX 0 |
742 | #define mmSDMA0_RLC4_IB_BASE_HI 0x029e |
743 | #define mmSDMA0_RLC4_IB_BASE_HI_BASE_IDX 0 |
744 | #define mmSDMA0_RLC4_IB_SIZE 0x029f |
745 | #define mmSDMA0_RLC4_IB_SIZE_BASE_IDX 0 |
746 | #define mmSDMA0_RLC4_SKIP_CNTL 0x02a0 |
747 | #define mmSDMA0_RLC4_SKIP_CNTL_BASE_IDX 0 |
748 | #define mmSDMA0_RLC4_CONTEXT_STATUS 0x02a1 |
749 | #define mmSDMA0_RLC4_CONTEXT_STATUS_BASE_IDX 0 |
750 | #define mmSDMA0_RLC4_DOORBELL 0x02a2 |
751 | #define mmSDMA0_RLC4_DOORBELL_BASE_IDX 0 |
752 | #define mmSDMA0_RLC4_STATUS 0x02b8 |
753 | #define mmSDMA0_RLC4_STATUS_BASE_IDX 0 |
754 | #define mmSDMA0_RLC4_DOORBELL_LOG 0x02b9 |
755 | #define mmSDMA0_RLC4_DOORBELL_LOG_BASE_IDX 0 |
756 | #define mmSDMA0_RLC4_WATERMARK 0x02ba |
757 | #define mmSDMA0_RLC4_WATERMARK_BASE_IDX 0 |
758 | #define mmSDMA0_RLC4_DOORBELL_OFFSET 0x02bb |
759 | #define mmSDMA0_RLC4_DOORBELL_OFFSET_BASE_IDX 0 |
760 | #define mmSDMA0_RLC4_CSA_ADDR_LO 0x02bc |
761 | #define mmSDMA0_RLC4_CSA_ADDR_LO_BASE_IDX 0 |
762 | #define mmSDMA0_RLC4_CSA_ADDR_HI 0x02bd |
763 | #define mmSDMA0_RLC4_CSA_ADDR_HI_BASE_IDX 0 |
764 | #define mmSDMA0_RLC4_IB_SUB_REMAIN 0x02bf |
765 | #define mmSDMA0_RLC4_IB_SUB_REMAIN_BASE_IDX 0 |
766 | #define mmSDMA0_RLC4_PREEMPT 0x02c0 |
767 | #define mmSDMA0_RLC4_PREEMPT_BASE_IDX 0 |
768 | #define mmSDMA0_RLC4_DUMMY_REG 0x02c1 |
769 | #define mmSDMA0_RLC4_DUMMY_REG_BASE_IDX 0 |
770 | #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI 0x02c2 |
771 | #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
772 | #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO 0x02c3 |
773 | #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
774 | #define mmSDMA0_RLC4_RB_AQL_CNTL 0x02c4 |
775 | #define mmSDMA0_RLC4_RB_AQL_CNTL_BASE_IDX 0 |
776 | #define mmSDMA0_RLC4_MINOR_PTR_UPDATE 0x02c5 |
777 | #define mmSDMA0_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0 |
778 | #define mmSDMA0_RLC4_MIDCMD_DATA0 0x02d0 |
779 | #define mmSDMA0_RLC4_MIDCMD_DATA0_BASE_IDX 0 |
780 | #define mmSDMA0_RLC4_MIDCMD_DATA1 0x02d1 |
781 | #define mmSDMA0_RLC4_MIDCMD_DATA1_BASE_IDX 0 |
782 | #define mmSDMA0_RLC4_MIDCMD_DATA2 0x02d2 |
783 | #define mmSDMA0_RLC4_MIDCMD_DATA2_BASE_IDX 0 |
784 | #define mmSDMA0_RLC4_MIDCMD_DATA3 0x02d3 |
785 | #define mmSDMA0_RLC4_MIDCMD_DATA3_BASE_IDX 0 |
786 | #define mmSDMA0_RLC4_MIDCMD_DATA4 0x02d4 |
787 | #define mmSDMA0_RLC4_MIDCMD_DATA4_BASE_IDX 0 |
788 | #define mmSDMA0_RLC4_MIDCMD_DATA5 0x02d5 |
789 | #define mmSDMA0_RLC4_MIDCMD_DATA5_BASE_IDX 0 |
790 | #define mmSDMA0_RLC4_MIDCMD_DATA6 0x02d6 |
791 | #define mmSDMA0_RLC4_MIDCMD_DATA6_BASE_IDX 0 |
792 | #define mmSDMA0_RLC4_MIDCMD_DATA7 0x02d7 |
793 | #define mmSDMA0_RLC4_MIDCMD_DATA7_BASE_IDX 0 |
794 | #define mmSDMA0_RLC4_MIDCMD_DATA8 0x02d8 |
795 | #define mmSDMA0_RLC4_MIDCMD_DATA8_BASE_IDX 0 |
796 | #define mmSDMA0_RLC4_MIDCMD_CNTL 0x02d9 |
797 | #define mmSDMA0_RLC4_MIDCMD_CNTL_BASE_IDX 0 |
798 | #define mmSDMA0_RLC5_RB_CNTL 0x02e8 |
799 | #define mmSDMA0_RLC5_RB_CNTL_BASE_IDX 0 |
800 | #define mmSDMA0_RLC5_RB_BASE 0x02e9 |
801 | #define mmSDMA0_RLC5_RB_BASE_BASE_IDX 0 |
802 | #define mmSDMA0_RLC5_RB_BASE_HI 0x02ea |
803 | #define mmSDMA0_RLC5_RB_BASE_HI_BASE_IDX 0 |
804 | #define mmSDMA0_RLC5_RB_RPTR 0x02eb |
805 | #define mmSDMA0_RLC5_RB_RPTR_BASE_IDX 0 |
806 | #define mmSDMA0_RLC5_RB_RPTR_HI 0x02ec |
807 | #define mmSDMA0_RLC5_RB_RPTR_HI_BASE_IDX 0 |
808 | #define mmSDMA0_RLC5_RB_WPTR 0x02ed |
809 | #define mmSDMA0_RLC5_RB_WPTR_BASE_IDX 0 |
810 | #define mmSDMA0_RLC5_RB_WPTR_HI 0x02ee |
811 | #define mmSDMA0_RLC5_RB_WPTR_HI_BASE_IDX 0 |
812 | #define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL 0x02ef |
813 | #define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
814 | #define mmSDMA0_RLC5_RB_RPTR_ADDR_HI 0x02f0 |
815 | #define mmSDMA0_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0 |
816 | #define mmSDMA0_RLC5_RB_RPTR_ADDR_LO 0x02f1 |
817 | #define mmSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0 |
818 | #define mmSDMA0_RLC5_IB_CNTL 0x02f2 |
819 | #define mmSDMA0_RLC5_IB_CNTL_BASE_IDX 0 |
820 | #define mmSDMA0_RLC5_IB_RPTR 0x02f3 |
821 | #define mmSDMA0_RLC5_IB_RPTR_BASE_IDX 0 |
822 | #define mmSDMA0_RLC5_IB_OFFSET 0x02f4 |
823 | #define mmSDMA0_RLC5_IB_OFFSET_BASE_IDX 0 |
824 | #define mmSDMA0_RLC5_IB_BASE_LO 0x02f5 |
825 | #define mmSDMA0_RLC5_IB_BASE_LO_BASE_IDX 0 |
826 | #define mmSDMA0_RLC5_IB_BASE_HI 0x02f6 |
827 | #define mmSDMA0_RLC5_IB_BASE_HI_BASE_IDX 0 |
828 | #define mmSDMA0_RLC5_IB_SIZE 0x02f7 |
829 | #define mmSDMA0_RLC5_IB_SIZE_BASE_IDX 0 |
830 | #define mmSDMA0_RLC5_SKIP_CNTL 0x02f8 |
831 | #define mmSDMA0_RLC5_SKIP_CNTL_BASE_IDX 0 |
832 | #define mmSDMA0_RLC5_CONTEXT_STATUS 0x02f9 |
833 | #define mmSDMA0_RLC5_CONTEXT_STATUS_BASE_IDX 0 |
834 | #define mmSDMA0_RLC5_DOORBELL 0x02fa |
835 | #define mmSDMA0_RLC5_DOORBELL_BASE_IDX 0 |
836 | #define mmSDMA0_RLC5_STATUS 0x0310 |
837 | #define mmSDMA0_RLC5_STATUS_BASE_IDX 0 |
838 | #define mmSDMA0_RLC5_DOORBELL_LOG 0x0311 |
839 | #define mmSDMA0_RLC5_DOORBELL_LOG_BASE_IDX 0 |
840 | #define mmSDMA0_RLC5_WATERMARK 0x0312 |
841 | #define mmSDMA0_RLC5_WATERMARK_BASE_IDX 0 |
842 | #define mmSDMA0_RLC5_DOORBELL_OFFSET 0x0313 |
843 | #define mmSDMA0_RLC5_DOORBELL_OFFSET_BASE_IDX 0 |
844 | #define mmSDMA0_RLC5_CSA_ADDR_LO 0x0314 |
845 | #define mmSDMA0_RLC5_CSA_ADDR_LO_BASE_IDX 0 |
846 | #define mmSDMA0_RLC5_CSA_ADDR_HI 0x0315 |
847 | #define mmSDMA0_RLC5_CSA_ADDR_HI_BASE_IDX 0 |
848 | #define mmSDMA0_RLC5_IB_SUB_REMAIN 0x0317 |
849 | #define mmSDMA0_RLC5_IB_SUB_REMAIN_BASE_IDX 0 |
850 | #define mmSDMA0_RLC5_PREEMPT 0x0318 |
851 | #define mmSDMA0_RLC5_PREEMPT_BASE_IDX 0 |
852 | #define mmSDMA0_RLC5_DUMMY_REG 0x0319 |
853 | #define mmSDMA0_RLC5_DUMMY_REG_BASE_IDX 0 |
854 | #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI 0x031a |
855 | #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
856 | #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO 0x031b |
857 | #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
858 | #define mmSDMA0_RLC5_RB_AQL_CNTL 0x031c |
859 | #define mmSDMA0_RLC5_RB_AQL_CNTL_BASE_IDX 0 |
860 | #define mmSDMA0_RLC5_MINOR_PTR_UPDATE 0x031d |
861 | #define mmSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0 |
862 | #define mmSDMA0_RLC5_MIDCMD_DATA0 0x0328 |
863 | #define mmSDMA0_RLC5_MIDCMD_DATA0_BASE_IDX 0 |
864 | #define mmSDMA0_RLC5_MIDCMD_DATA1 0x0329 |
865 | #define mmSDMA0_RLC5_MIDCMD_DATA1_BASE_IDX 0 |
866 | #define mmSDMA0_RLC5_MIDCMD_DATA2 0x032a |
867 | #define mmSDMA0_RLC5_MIDCMD_DATA2_BASE_IDX 0 |
868 | #define mmSDMA0_RLC5_MIDCMD_DATA3 0x032b |
869 | #define mmSDMA0_RLC5_MIDCMD_DATA3_BASE_IDX 0 |
870 | #define mmSDMA0_RLC5_MIDCMD_DATA4 0x032c |
871 | #define mmSDMA0_RLC5_MIDCMD_DATA4_BASE_IDX 0 |
872 | #define mmSDMA0_RLC5_MIDCMD_DATA5 0x032d |
873 | #define mmSDMA0_RLC5_MIDCMD_DATA5_BASE_IDX 0 |
874 | #define mmSDMA0_RLC5_MIDCMD_DATA6 0x032e |
875 | #define mmSDMA0_RLC5_MIDCMD_DATA6_BASE_IDX 0 |
876 | #define mmSDMA0_RLC5_MIDCMD_DATA7 0x032f |
877 | #define mmSDMA0_RLC5_MIDCMD_DATA7_BASE_IDX 0 |
878 | #define mmSDMA0_RLC5_MIDCMD_DATA8 0x0330 |
879 | #define mmSDMA0_RLC5_MIDCMD_DATA8_BASE_IDX 0 |
880 | #define mmSDMA0_RLC5_MIDCMD_CNTL 0x0331 |
881 | #define mmSDMA0_RLC5_MIDCMD_CNTL_BASE_IDX 0 |
882 | #define mmSDMA0_RLC6_RB_CNTL 0x0340 |
883 | #define mmSDMA0_RLC6_RB_CNTL_BASE_IDX 0 |
884 | #define mmSDMA0_RLC6_RB_BASE 0x0341 |
885 | #define mmSDMA0_RLC6_RB_BASE_BASE_IDX 0 |
886 | #define mmSDMA0_RLC6_RB_BASE_HI 0x0342 |
887 | #define mmSDMA0_RLC6_RB_BASE_HI_BASE_IDX 0 |
888 | #define mmSDMA0_RLC6_RB_RPTR 0x0343 |
889 | #define mmSDMA0_RLC6_RB_RPTR_BASE_IDX 0 |
890 | #define mmSDMA0_RLC6_RB_RPTR_HI 0x0344 |
891 | #define mmSDMA0_RLC6_RB_RPTR_HI_BASE_IDX 0 |
892 | #define mmSDMA0_RLC6_RB_WPTR 0x0345 |
893 | #define mmSDMA0_RLC6_RB_WPTR_BASE_IDX 0 |
894 | #define mmSDMA0_RLC6_RB_WPTR_HI 0x0346 |
895 | #define mmSDMA0_RLC6_RB_WPTR_HI_BASE_IDX 0 |
896 | #define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL 0x0347 |
897 | #define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
898 | #define mmSDMA0_RLC6_RB_RPTR_ADDR_HI 0x0348 |
899 | #define mmSDMA0_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0 |
900 | #define mmSDMA0_RLC6_RB_RPTR_ADDR_LO 0x0349 |
901 | #define mmSDMA0_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0 |
902 | #define mmSDMA0_RLC6_IB_CNTL 0x034a |
903 | #define mmSDMA0_RLC6_IB_CNTL_BASE_IDX 0 |
904 | #define mmSDMA0_RLC6_IB_RPTR 0x034b |
905 | #define mmSDMA0_RLC6_IB_RPTR_BASE_IDX 0 |
906 | #define mmSDMA0_RLC6_IB_OFFSET 0x034c |
907 | #define mmSDMA0_RLC6_IB_OFFSET_BASE_IDX 0 |
908 | #define mmSDMA0_RLC6_IB_BASE_LO 0x034d |
909 | #define mmSDMA0_RLC6_IB_BASE_LO_BASE_IDX 0 |
910 | #define mmSDMA0_RLC6_IB_BASE_HI 0x034e |
911 | #define mmSDMA0_RLC6_IB_BASE_HI_BASE_IDX 0 |
912 | #define mmSDMA0_RLC6_IB_SIZE 0x034f |
913 | #define mmSDMA0_RLC6_IB_SIZE_BASE_IDX 0 |
914 | #define mmSDMA0_RLC6_SKIP_CNTL 0x0350 |
915 | #define mmSDMA0_RLC6_SKIP_CNTL_BASE_IDX 0 |
916 | #define mmSDMA0_RLC6_CONTEXT_STATUS 0x0351 |
917 | #define mmSDMA0_RLC6_CONTEXT_STATUS_BASE_IDX 0 |
918 | #define mmSDMA0_RLC6_DOORBELL 0x0352 |
919 | #define mmSDMA0_RLC6_DOORBELL_BASE_IDX 0 |
920 | #define mmSDMA0_RLC6_STATUS 0x0368 |
921 | #define mmSDMA0_RLC6_STATUS_BASE_IDX 0 |
922 | #define mmSDMA0_RLC6_DOORBELL_LOG 0x0369 |
923 | #define mmSDMA0_RLC6_DOORBELL_LOG_BASE_IDX 0 |
924 | #define mmSDMA0_RLC6_WATERMARK 0x036a |
925 | #define mmSDMA0_RLC6_WATERMARK_BASE_IDX 0 |
926 | #define mmSDMA0_RLC6_DOORBELL_OFFSET 0x036b |
927 | #define mmSDMA0_RLC6_DOORBELL_OFFSET_BASE_IDX 0 |
928 | #define mmSDMA0_RLC6_CSA_ADDR_LO 0x036c |
929 | #define mmSDMA0_RLC6_CSA_ADDR_LO_BASE_IDX 0 |
930 | #define mmSDMA0_RLC6_CSA_ADDR_HI 0x036d |
931 | #define mmSDMA0_RLC6_CSA_ADDR_HI_BASE_IDX 0 |
932 | #define mmSDMA0_RLC6_IB_SUB_REMAIN 0x036f |
933 | #define mmSDMA0_RLC6_IB_SUB_REMAIN_BASE_IDX 0 |
934 | #define mmSDMA0_RLC6_PREEMPT 0x0370 |
935 | #define mmSDMA0_RLC6_PREEMPT_BASE_IDX 0 |
936 | #define mmSDMA0_RLC6_DUMMY_REG 0x0371 |
937 | #define mmSDMA0_RLC6_DUMMY_REG_BASE_IDX 0 |
938 | #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI 0x0372 |
939 | #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
940 | #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO 0x0373 |
941 | #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
942 | #define mmSDMA0_RLC6_RB_AQL_CNTL 0x0374 |
943 | #define mmSDMA0_RLC6_RB_AQL_CNTL_BASE_IDX 0 |
944 | #define mmSDMA0_RLC6_MINOR_PTR_UPDATE 0x0375 |
945 | #define mmSDMA0_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0 |
946 | #define mmSDMA0_RLC6_MIDCMD_DATA0 0x0380 |
947 | #define mmSDMA0_RLC6_MIDCMD_DATA0_BASE_IDX 0 |
948 | #define mmSDMA0_RLC6_MIDCMD_DATA1 0x0381 |
949 | #define mmSDMA0_RLC6_MIDCMD_DATA1_BASE_IDX 0 |
950 | #define mmSDMA0_RLC6_MIDCMD_DATA2 0x0382 |
951 | #define mmSDMA0_RLC6_MIDCMD_DATA2_BASE_IDX 0 |
952 | #define mmSDMA0_RLC6_MIDCMD_DATA3 0x0383 |
953 | #define mmSDMA0_RLC6_MIDCMD_DATA3_BASE_IDX 0 |
954 | #define mmSDMA0_RLC6_MIDCMD_DATA4 0x0384 |
955 | #define mmSDMA0_RLC6_MIDCMD_DATA4_BASE_IDX 0 |
956 | #define mmSDMA0_RLC6_MIDCMD_DATA5 0x0385 |
957 | #define mmSDMA0_RLC6_MIDCMD_DATA5_BASE_IDX 0 |
958 | #define mmSDMA0_RLC6_MIDCMD_DATA6 0x0386 |
959 | #define mmSDMA0_RLC6_MIDCMD_DATA6_BASE_IDX 0 |
960 | #define mmSDMA0_RLC6_MIDCMD_DATA7 0x0387 |
961 | #define mmSDMA0_RLC6_MIDCMD_DATA7_BASE_IDX 0 |
962 | #define mmSDMA0_RLC6_MIDCMD_DATA8 0x0388 |
963 | #define mmSDMA0_RLC6_MIDCMD_DATA8_BASE_IDX 0 |
964 | #define mmSDMA0_RLC6_MIDCMD_CNTL 0x0389 |
965 | #define mmSDMA0_RLC6_MIDCMD_CNTL_BASE_IDX 0 |
966 | #define mmSDMA0_RLC7_RB_CNTL 0x0398 |
967 | #define mmSDMA0_RLC7_RB_CNTL_BASE_IDX 0 |
968 | #define mmSDMA0_RLC7_RB_BASE 0x0399 |
969 | #define mmSDMA0_RLC7_RB_BASE_BASE_IDX 0 |
970 | #define mmSDMA0_RLC7_RB_BASE_HI 0x039a |
971 | #define mmSDMA0_RLC7_RB_BASE_HI_BASE_IDX 0 |
972 | #define mmSDMA0_RLC7_RB_RPTR 0x039b |
973 | #define mmSDMA0_RLC7_RB_RPTR_BASE_IDX 0 |
974 | #define mmSDMA0_RLC7_RB_RPTR_HI 0x039c |
975 | #define mmSDMA0_RLC7_RB_RPTR_HI_BASE_IDX 0 |
976 | #define mmSDMA0_RLC7_RB_WPTR 0x039d |
977 | #define mmSDMA0_RLC7_RB_WPTR_BASE_IDX 0 |
978 | #define mmSDMA0_RLC7_RB_WPTR_HI 0x039e |
979 | #define mmSDMA0_RLC7_RB_WPTR_HI_BASE_IDX 0 |
980 | #define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL 0x039f |
981 | #define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
982 | #define mmSDMA0_RLC7_RB_RPTR_ADDR_HI 0x03a0 |
983 | #define mmSDMA0_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0 |
984 | #define mmSDMA0_RLC7_RB_RPTR_ADDR_LO 0x03a1 |
985 | #define mmSDMA0_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0 |
986 | #define mmSDMA0_RLC7_IB_CNTL 0x03a2 |
987 | #define mmSDMA0_RLC7_IB_CNTL_BASE_IDX 0 |
988 | #define mmSDMA0_RLC7_IB_RPTR 0x03a3 |
989 | #define mmSDMA0_RLC7_IB_RPTR_BASE_IDX 0 |
990 | #define mmSDMA0_RLC7_IB_OFFSET 0x03a4 |
991 | #define mmSDMA0_RLC7_IB_OFFSET_BASE_IDX 0 |
992 | #define mmSDMA0_RLC7_IB_BASE_LO 0x03a5 |
993 | #define mmSDMA0_RLC7_IB_BASE_LO_BASE_IDX 0 |
994 | #define mmSDMA0_RLC7_IB_BASE_HI 0x03a6 |
995 | #define mmSDMA0_RLC7_IB_BASE_HI_BASE_IDX 0 |
996 | #define mmSDMA0_RLC7_IB_SIZE 0x03a7 |
997 | #define mmSDMA0_RLC7_IB_SIZE_BASE_IDX 0 |
998 | #define mmSDMA0_RLC7_SKIP_CNTL 0x03a8 |
999 | #define mmSDMA0_RLC7_SKIP_CNTL_BASE_IDX 0 |
1000 | #define mmSDMA0_RLC7_CONTEXT_STATUS 0x03a9 |
1001 | #define mmSDMA0_RLC7_CONTEXT_STATUS_BASE_IDX 0 |
1002 | #define mmSDMA0_RLC7_DOORBELL 0x03aa |
1003 | #define mmSDMA0_RLC7_DOORBELL_BASE_IDX 0 |
1004 | #define mmSDMA0_RLC7_STATUS 0x03c0 |
1005 | #define mmSDMA0_RLC7_STATUS_BASE_IDX 0 |
1006 | #define mmSDMA0_RLC7_DOORBELL_LOG 0x03c1 |
1007 | #define mmSDMA0_RLC7_DOORBELL_LOG_BASE_IDX 0 |
1008 | #define mmSDMA0_RLC7_WATERMARK 0x03c2 |
1009 | #define mmSDMA0_RLC7_WATERMARK_BASE_IDX 0 |
1010 | #define mmSDMA0_RLC7_DOORBELL_OFFSET 0x03c3 |
1011 | #define mmSDMA0_RLC7_DOORBELL_OFFSET_BASE_IDX 0 |
1012 | #define mmSDMA0_RLC7_CSA_ADDR_LO 0x03c4 |
1013 | #define mmSDMA0_RLC7_CSA_ADDR_LO_BASE_IDX 0 |
1014 | #define mmSDMA0_RLC7_CSA_ADDR_HI 0x03c5 |
1015 | #define mmSDMA0_RLC7_CSA_ADDR_HI_BASE_IDX 0 |
1016 | #define mmSDMA0_RLC7_IB_SUB_REMAIN 0x03c7 |
1017 | #define mmSDMA0_RLC7_IB_SUB_REMAIN_BASE_IDX 0 |
1018 | #define mmSDMA0_RLC7_PREEMPT 0x03c8 |
1019 | #define mmSDMA0_RLC7_PREEMPT_BASE_IDX 0 |
1020 | #define mmSDMA0_RLC7_DUMMY_REG 0x03c9 |
1021 | #define mmSDMA0_RLC7_DUMMY_REG_BASE_IDX 0 |
1022 | #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI 0x03ca |
1023 | #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
1024 | #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO 0x03cb |
1025 | #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
1026 | #define mmSDMA0_RLC7_RB_AQL_CNTL 0x03cc |
1027 | #define mmSDMA0_RLC7_RB_AQL_CNTL_BASE_IDX 0 |
1028 | #define mmSDMA0_RLC7_MINOR_PTR_UPDATE 0x03cd |
1029 | #define mmSDMA0_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0 |
1030 | #define mmSDMA0_RLC7_MIDCMD_DATA0 0x03d8 |
1031 | #define mmSDMA0_RLC7_MIDCMD_DATA0_BASE_IDX 0 |
1032 | #define mmSDMA0_RLC7_MIDCMD_DATA1 0x03d9 |
1033 | #define mmSDMA0_RLC7_MIDCMD_DATA1_BASE_IDX 0 |
1034 | #define mmSDMA0_RLC7_MIDCMD_DATA2 0x03da |
1035 | #define mmSDMA0_RLC7_MIDCMD_DATA2_BASE_IDX 0 |
1036 | #define mmSDMA0_RLC7_MIDCMD_DATA3 0x03db |
1037 | #define mmSDMA0_RLC7_MIDCMD_DATA3_BASE_IDX 0 |
1038 | #define mmSDMA0_RLC7_MIDCMD_DATA4 0x03dc |
1039 | #define mmSDMA0_RLC7_MIDCMD_DATA4_BASE_IDX 0 |
1040 | #define mmSDMA0_RLC7_MIDCMD_DATA5 0x03dd |
1041 | #define mmSDMA0_RLC7_MIDCMD_DATA5_BASE_IDX 0 |
1042 | #define mmSDMA0_RLC7_MIDCMD_DATA6 0x03de |
1043 | #define mmSDMA0_RLC7_MIDCMD_DATA6_BASE_IDX 0 |
1044 | #define mmSDMA0_RLC7_MIDCMD_DATA7 0x03df |
1045 | #define mmSDMA0_RLC7_MIDCMD_DATA7_BASE_IDX 0 |
1046 | #define mmSDMA0_RLC7_MIDCMD_DATA8 0x03e0 |
1047 | #define mmSDMA0_RLC7_MIDCMD_DATA8_BASE_IDX 0 |
1048 | #define mmSDMA0_RLC7_MIDCMD_CNTL 0x03e1 |
1049 | #define mmSDMA0_RLC7_MIDCMD_CNTL_BASE_IDX 0 |
1050 | |
1051 | #endif |
1052 | |