| 1 | /* |
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| 2 | * |
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| 3 | * Copyright (C) 2016 Advanced Micro Devices, Inc. |
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| 4 | * |
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| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 6 | * copy of this software and associated documentation files (the "Software"), |
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| 7 | * to deal in the Software without restriction, including without limitation |
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| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 10 | * Software is furnished to do so, subject to the following conditions: |
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| 11 | * |
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| 12 | * The above copyright notice and this permission notice shall be included |
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| 13 | * in all copies or substantial portions of the Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 16 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
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| 19 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 20 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | */ |
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| 22 | |
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| 23 | #ifndef SMU_6_0_D_H |
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| 24 | #define SMU_6_0_D_H |
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| 25 | |
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| 26 | #define ixLCAC_MC0_CNTL 0x011C |
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| 27 | #define ixLCAC_MC0_OVR_SEL 0x011D |
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| 28 | #define ixLCAC_MC0_OVR_VAL 0x011E |
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| 29 | #define ixLCAC_MC1_CNTL 0x011F |
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| 30 | #define ixLCAC_MC1_OVR_SEL 0x0120 |
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| 31 | #define ixLCAC_MC1_OVR_VAL 0x0121 |
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| 32 | #define ixLCAC_MC2_CNTL 0x0122 |
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| 33 | #define ixLCAC_MC2_OVR_SEL 0x0123 |
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| 34 | #define ixLCAC_MC2_OVR_VAL 0x0124 |
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| 35 | #define ixLCAC_MC3_CNTL 0x0125 |
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| 36 | #define ixLCAC_MC3_OVR_SEL 0x0126 |
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| 37 | #define ixLCAC_MC3_OVR_VAL 0x0127 |
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| 38 | #define ixLCAC_MC4_CNTL 0x0128 |
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| 39 | #define ixLCAC_MC4_OVR_SEL 0x0129 |
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| 40 | #define ixLCAC_MC4_OVR_VAL 0x012A |
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| 41 | #define ixLCAC_MC5_CNTL 0x012B |
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| 42 | #define ixLCAC_MC5_OVR_SEL 0x012C |
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| 43 | #define ixLCAC_MC5_OVR_VAL 0x012D |
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| 44 | #define ixSMC_PC_C 0x80000370 |
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| 45 | #define ixTHM_TMON0_DEBUG 0x03F0 |
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| 46 | #define ixTHM_TMON0_INT_DATA 0x0380 |
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| 47 | #define ixTHM_TMON0_RDIL0_DATA 0x0300 |
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| 48 | #define ixTHM_TMON0_RDIL10_DATA 0x030A |
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| 49 | #define ixTHM_TMON0_RDIL11_DATA 0x030B |
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| 50 | #define ixTHM_TMON0_RDIL12_DATA 0x030C |
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| 51 | #define ixTHM_TMON0_RDIL13_DATA 0x030D |
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| 52 | #define ixTHM_TMON0_RDIL14_DATA 0x030E |
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| 53 | #define ixTHM_TMON0_RDIL15_DATA 0x030F |
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| 54 | #define ixTHM_TMON0_RDIL1_DATA 0x0301 |
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| 55 | #define ixTHM_TMON0_RDIL2_DATA 0x0302 |
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| 56 | #define ixTHM_TMON0_RDIL3_DATA 0x0303 |
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| 57 | #define ixTHM_TMON0_RDIL4_DATA 0x0304 |
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| 58 | #define ixTHM_TMON0_RDIL5_DATA 0x0305 |
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| 59 | #define ixTHM_TMON0_RDIL6_DATA 0x0306 |
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| 60 | #define ixTHM_TMON0_RDIL7_DATA 0x0307 |
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| 61 | #define ixTHM_TMON0_RDIL8_DATA 0x0308 |
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| 62 | #define ixTHM_TMON0_RDIL9_DATA 0x0309 |
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| 63 | #define ixTHM_TMON0_RDIR0_DATA 0x0310 |
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| 64 | #define ixTHM_TMON0_RDIR10_DATA 0x031A |
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| 65 | #define ixTHM_TMON0_RDIR11_DATA 0x031B |
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| 66 | #define ixTHM_TMON0_RDIR12_DATA 0x031C |
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| 67 | #define ixTHM_TMON0_RDIR13_DATA 0x031D |
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| 68 | #define ixTHM_TMON0_RDIR14_DATA 0x031E |
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| 69 | #define ixTHM_TMON0_RDIR15_DATA 0x031F |
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| 70 | #define ixTHM_TMON0_RDIR1_DATA 0x0311 |
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| 71 | #define ixTHM_TMON0_RDIR2_DATA 0x0312 |
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| 72 | #define ixTHM_TMON0_RDIR3_DATA 0x0313 |
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| 73 | #define ixTHM_TMON0_RDIR4_DATA 0x0314 |
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| 74 | #define ixTHM_TMON0_RDIR5_DATA 0x0315 |
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| 75 | #define ixTHM_TMON0_RDIR6_DATA 0x0316 |
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| 76 | #define ixTHM_TMON0_RDIR7_DATA 0x0317 |
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| 77 | #define ixTHM_TMON0_RDIR8_DATA 0x0318 |
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| 78 | #define ixTHM_TMON0_RDIR9_DATA 0x0319 |
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| 79 | #define ixTHM_TMON1_DEBUG 0x03F1 |
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| 80 | #define ixTHM_TMON1_INT_DATA 0x0381 |
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| 81 | #define ixTHM_TMON1_RDIL0_DATA 0x0320 |
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| 82 | #define ixTHM_TMON1_RDIL10_DATA 0x032A |
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| 83 | #define ixTHM_TMON1_RDIL11_DATA 0x032B |
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| 84 | #define ixTHM_TMON1_RDIL12_DATA 0x032C |
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| 85 | #define ixTHM_TMON1_RDIL13_DATA 0x032D |
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| 86 | #define ixTHM_TMON1_RDIL14_DATA 0x032E |
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| 87 | #define ixTHM_TMON1_RDIL15_DATA 0x032F |
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| 88 | #define ixTHM_TMON1_RDIL1_DATA 0x0321 |
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| 89 | #define ixTHM_TMON1_RDIL2_DATA 0x0322 |
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| 90 | #define ixTHM_TMON1_RDIL3_DATA 0x0323 |
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| 91 | #define ixTHM_TMON1_RDIL4_DATA 0x0324 |
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| 92 | #define ixTHM_TMON1_RDIL5_DATA 0x0325 |
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| 93 | #define ixTHM_TMON1_RDIL6_DATA 0x0326 |
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| 94 | #define ixTHM_TMON1_RDIL7_DATA 0x0327 |
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| 95 | #define ixTHM_TMON1_RDIL8_DATA 0x0328 |
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| 96 | #define ixTHM_TMON1_RDIL9_DATA 0x0329 |
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| 97 | #define ixTHM_TMON1_RDIR0_DATA 0x0330 |
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| 98 | #define ixTHM_TMON1_RDIR10_DATA 0x033A |
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| 99 | #define ixTHM_TMON1_RDIR11_DATA 0x033B |
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| 100 | #define ixTHM_TMON1_RDIR12_DATA 0x033C |
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| 101 | #define ixTHM_TMON1_RDIR13_DATA 0x033D |
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| 102 | #define ixTHM_TMON1_RDIR14_DATA 0x033E |
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| 103 | #define ixTHM_TMON1_RDIR15_DATA 0x033F |
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| 104 | #define ixTHM_TMON1_RDIR1_DATA 0x0331 |
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| 105 | #define ixTHM_TMON1_RDIR2_DATA 0x0332 |
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| 106 | #define ixTHM_TMON1_RDIR3_DATA 0x0333 |
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| 107 | #define ixTHM_TMON1_RDIR4_DATA 0x0334 |
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| 108 | #define ixTHM_TMON1_RDIR5_DATA 0x0335 |
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| 109 | #define ixTHM_TMON1_RDIR6_DATA 0x0336 |
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| 110 | #define ixTHM_TMON1_RDIR7_DATA 0x0337 |
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| 111 | #define ixTHM_TMON1_RDIR8_DATA 0x0338 |
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| 112 | #define ixTHM_TMON1_RDIR9_DATA 0x0339 |
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| 113 | #define mmGPIOPAD_A 0x05E7 |
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| 114 | #define mmGPIOPAD_EN 0x05E8 |
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| 115 | #define mmGPIOPAD_EXTERN_TRIG_CNTL 0x05F1 |
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| 116 | #define mmGPIOPAD_INT_EN 0x05EE |
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| 117 | #define mmGPIOPAD_INT_POLARITY 0x05F0 |
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| 118 | #define mmGPIOPAD_INT_STAT 0x05EC |
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| 119 | #define mmGPIOPAD_INT_STAT_AK 0x05ED |
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| 120 | #define mmGPIOPAD_INT_STAT_EN 0x05EB |
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| 121 | #define mmGPIOPAD_INT_TYPE 0x05EF |
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| 122 | #define mmGPIOPAD_MASK 0x05E6 |
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| 123 | #define mmGPIOPAD_PD_EN 0x05F4 |
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| 124 | #define mmGPIOPAD_PINSTRAPS 0x05EA |
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| 125 | #define mmGPIOPAD_PU_EN 0x05F3 |
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| 126 | #define mmGPIOPAD_RCVR_SEL 0x05F2 |
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| 127 | #define mmGPIOPAD_STRENGTH 0x05E5 |
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| 128 | #define mmGPIOPAD_SW_INT_STAT 0x05E4 |
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| 129 | #define mmGPIOPAD_Y 0x05E9 |
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| 130 | #define mmSMC_IND_ACCESS_CNTL 0x008A |
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| 131 | #define mmSMC_IND_DATA_0 0x0081 |
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| 132 | #define mmSMC_IND_DATA 0x0081 |
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| 133 | #define mmSMC_IND_DATA_1 0x0083 |
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| 134 | #define mmSMC_IND_DATA_2 0x0085 |
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| 135 | #define mmSMC_IND_DATA_3 0x0087 |
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| 136 | #define mmSMC_IND_INDEX_0 0x0080 |
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| 137 | #define mmSMC_IND_INDEX 0x0080 |
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| 138 | #define mmSMC_IND_INDEX_1 0x0082 |
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| 139 | #define mmSMC_IND_INDEX_2 0x0084 |
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| 140 | #define mmSMC_IND_INDEX_3 0x0086 |
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| 141 | #define mmSMC_MESSAGE_0 0x008B |
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| 142 | #define mmSMC_MESSAGE_1 0x008D |
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| 143 | #define mmSMC_MESSAGE_2 0x008F |
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| 144 | #define mmSMC_RESP_0 0x008C |
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| 145 | #define mmSMC_RESP_1 0x008E |
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| 146 | #define mmSMC_RESP_2 0x0090 |
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| 147 | |
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| 148 | #endif |
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| 149 | |
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