| 1 | /* |
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| 2 | * SMU_7_0_0 Register documentation |
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| 3 | * |
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| 4 | * Copyright (C) 2014 Advanced Micro Devices, Inc. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included |
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| 14 | * in all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
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| 20 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 22 | */ |
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| 23 | |
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| 24 | #ifndef SMU_7_0_0_D_H |
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| 25 | #define SMU_7_0_0_D_H |
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| 26 | |
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| 27 | #define mmGCK_SMC_IND_INDEX 0x80 |
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| 28 | #define mmGCK0_GCK_SMC_IND_INDEX 0x80 |
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| 29 | #define mmGCK1_GCK_SMC_IND_INDEX 0x82 |
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| 30 | #define mmGCK2_GCK_SMC_IND_INDEX 0x84 |
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| 31 | #define mmGCK3_GCK_SMC_IND_INDEX 0x86 |
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| 32 | #define mmGCK_SMC_IND_DATA 0x81 |
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| 33 | #define mmGCK0_GCK_SMC_IND_DATA 0x81 |
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| 34 | #define mmGCK1_GCK_SMC_IND_DATA 0x83 |
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| 35 | #define mmGCK2_GCK_SMC_IND_DATA 0x85 |
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| 36 | #define mmGCK3_GCK_SMC_IND_DATA 0x87 |
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| 37 | #define ixCG_DCLK_CNTL 0xc050009c |
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| 38 | #define ixCG_DCLK_STATUS 0xc05000a0 |
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| 39 | #define ixCG_VCLK_CNTL 0xc05000a4 |
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| 40 | #define ixCG_VCLK_STATUS 0xc05000a8 |
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| 41 | #define ixCG_ECLK_CNTL 0xc05000ac |
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| 42 | #define ixCG_ECLK_STATUS 0xc05000b0 |
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| 43 | #define ixCG_ACLK_CNTL 0xc05000dc |
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| 44 | #define ixGCK_DFS_BYPASS_CNTL 0xc0500118 |
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| 45 | #define ixCG_SPLL_FUNC_CNTL 0xc0500140 |
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| 46 | #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 |
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| 47 | #define ixCG_SPLL_FUNC_CNTL_3 0xc0500148 |
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| 48 | #define ixCG_SPLL_FUNC_CNTL_4 0xc050014c |
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| 49 | #define ixCG_SPLL_FUNC_CNTL_5 0xc0500150 |
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| 50 | #define ixCG_SPLL_FUNC_CNTL_6 0xc0500154 |
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| 51 | #define ixCG_SPLL_FUNC_CNTL_7 0xc0500158 |
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| 52 | #define ixSPLL_CNTL_MODE 0xc0500160 |
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| 53 | #define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164 |
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| 54 | #define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168 |
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| 55 | #define ixMPLL_BYPASSCLK_SEL 0xc050019c |
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| 56 | #define ixCG_CLKPIN_CNTL 0xc05001a0 |
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| 57 | #define ixCG_CLKPIN_CNTL_2 0xc05001a4 |
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| 58 | #define ixTHM_CLK_CNTL 0xc05001a8 |
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| 59 | #define ixMISC_CLK_CTRL 0xc05001ac |
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| 60 | #define ixGCK_PLL_TEST_CNTL 0xc05001c0 |
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| 61 | #define ixGCK_PLL_TEST_CNTL_2 0xc05001c4 |
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| 62 | #define ixGCK_ADFS_CLK_BYPASS_CNTL1 0xc05001c8 |
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| 63 | #define mmSMC_IND_INDEX 0x80 |
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| 64 | #define mmSMC0_SMC_IND_INDEX 0x80 |
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| 65 | #define mmSMC1_SMC_IND_INDEX 0x82 |
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| 66 | #define mmSMC2_SMC_IND_INDEX 0x84 |
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| 67 | #define mmSMC3_SMC_IND_INDEX 0x86 |
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| 68 | #define mmSMC_IND_DATA 0x81 |
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| 69 | #define mmSMC0_SMC_IND_DATA 0x81 |
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| 70 | #define mmSMC1_SMC_IND_DATA 0x83 |
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| 71 | #define mmSMC2_SMC_IND_DATA 0x85 |
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| 72 | #define mmSMC3_SMC_IND_DATA 0x87 |
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| 73 | #define mmSMC_IND_INDEX_0 0x80 |
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| 74 | #define mmSMC_IND_DATA_0 0x81 |
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| 75 | #define mmSMC_IND_INDEX_1 0x82 |
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| 76 | #define mmSMC_IND_DATA_1 0x83 |
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| 77 | #define mmSMC_IND_INDEX_2 0x84 |
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| 78 | #define mmSMC_IND_DATA_2 0x85 |
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| 79 | #define mmSMC_IND_INDEX_3 0x86 |
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| 80 | #define mmSMC_IND_DATA_3 0x87 |
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| 81 | #define mmSMC_IND_INDEX_4 0x88 |
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| 82 | #define mmSMC_IND_DATA_4 0x89 |
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| 83 | #define mmSMC_IND_INDEX_5 0x8a |
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| 84 | #define mmSMC_IND_DATA_5 0x8b |
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| 85 | #define mmSMC_IND_INDEX_6 0x8c |
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| 86 | #define mmSMC_IND_DATA_6 0x8d |
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| 87 | #define mmSMC_IND_INDEX_7 0x8e |
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| 88 | #define mmSMC_IND_DATA_7 0x8f |
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| 89 | #define mmSMC_IND_ACCESS_CNTL 0x90 |
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| 90 | #define mmSMC_MESSAGE_0 0x94 |
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| 91 | #define mmSMC_RESP_0 0x95 |
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| 92 | #define mmSMC_MESSAGE_1 0x96 |
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| 93 | #define mmSMC_RESP_1 0x97 |
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| 94 | #define mmSMC_MESSAGE_2 0x98 |
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| 95 | #define mmSMC_RESP_2 0x99 |
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| 96 | #define mmSMC_MESSAGE_3 0x9a |
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| 97 | #define mmSMC_RESP_3 0x9b |
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| 98 | #define mmSMC_MESSAGE_4 0x9c |
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| 99 | #define mmSMC_RESP_4 0x9d |
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| 100 | #define mmSMC_MESSAGE_5 0x9e |
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| 101 | #define mmSMC_RESP_5 0x9f |
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| 102 | #define mmSMC_MESSAGE_6 0xa0 |
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| 103 | #define mmSMC_RESP_6 0xa1 |
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| 104 | #define mmSMC_MESSAGE_7 0xa2 |
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| 105 | #define mmSMC_RESP_7 0xa3 |
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| 106 | #define mmSMC_MSG_ARG_0 0xa4 |
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| 107 | #define mmSMC_MSG_ARG_1 0xa5 |
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| 108 | #define mmSMC_MSG_ARG_2 0xa6 |
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| 109 | #define mmSMC_MSG_ARG_3 0xa7 |
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| 110 | #define mmSMC_MSG_ARG_4 0xa8 |
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| 111 | #define mmSMC_MSG_ARG_5 0xa9 |
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| 112 | #define mmSMC_MSG_ARG_6 0xaa |
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| 113 | #define mmSMC_MSG_ARG_7 0xab |
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| 114 | #define mmSMC_MESSAGE_8 0xb5 |
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| 115 | #define mmSMC_RESP_8 0xb6 |
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| 116 | #define mmSMC_MESSAGE_9 0xb7 |
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| 117 | #define mmSMC_RESP_9 0xb8 |
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| 118 | #define mmSMC_MESSAGE_10 0xb9 |
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| 119 | #define mmSMC_RESP_10 0xba |
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| 120 | #define mmSMC_MESSAGE_11 0xbb |
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| 121 | #define mmSMC_RESP_11 0xbc |
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| 122 | #define mmSMC_MSG_ARG_8 0xbd |
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| 123 | #define mmSMC_MSG_ARG_9 0xbe |
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| 124 | #define mmSMC_MSG_ARG_10 0xbf |
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| 125 | #define mmSMC_MSG_ARG_11 0x91 |
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| 126 | #define ixSMC_SYSCON_RESET_CNTL 0x80000000 |
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| 127 | #define ixSMC_SYSCON_CLOCK_CNTL_0 0x80000004 |
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| 128 | #define ixSMC_SYSCON_CLOCK_CNTL_1 0x80000008 |
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| 129 | #define ixSMC_SYSCON_CLOCK_CNTL_2 0x8000000c |
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| 130 | #define ixSMC_SYSCON_MISC_CNTL 0x80000010 |
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| 131 | #define ixSMC_SYSCON_MSG_ARG_0 0x80000068 |
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| 132 | #define ixSMC_PC_C 0x80000370 |
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| 133 | #define ixSMC_SCRATCH9 0x80000424 |
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| 134 | #define mmCG_FPS_CNT 0x1a4 |
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| 135 | #define mmSMU_SMC_IND_INDEX 0x80 |
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| 136 | #define mmSMU0_SMU_SMC_IND_INDEX 0x80 |
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| 137 | #define mmSMU1_SMU_SMC_IND_INDEX 0x82 |
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| 138 | #define mmSMU2_SMU_SMC_IND_INDEX 0x84 |
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| 139 | #define mmSMU3_SMU_SMC_IND_INDEX 0x86 |
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| 140 | #define mmSMU_SMC_IND_DATA 0x81 |
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| 141 | #define mmSMU0_SMU_SMC_IND_DATA 0x81 |
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| 142 | #define mmSMU1_SMU_SMC_IND_DATA 0x83 |
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| 143 | #define mmSMU2_SMU_SMC_IND_DATA 0x85 |
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| 144 | #define mmSMU3_SMU_SMC_IND_DATA 0x87 |
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| 145 | #define ixRCU_UC_EVENTS 0xc0000004 |
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| 146 | #define ixRCU_MISC_CTRL 0xc0000010 |
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| 147 | #define ixCC_RCU_FUSES 0xc00c0000 |
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| 148 | #define ixCC_SMU_MISC_FUSES 0xc00c0004 |
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| 149 | #define ixCC_SCLK_VID_FUSES 0xc00c0008 |
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| 150 | #define ixCC_GIO_IOCCFG_FUSES 0xc00c000c |
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| 151 | #define ixCC_GIO_IOC_FUSES 0xc00c0010 |
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| 152 | #define ixCC_SMU_TST_EFUSE1_MISC 0xc00c001c |
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| 153 | #define ixCC_TST_ID_STRAPS 0xc00c0020 |
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| 154 | #define ixCC_FCTRL_FUSES 0xc00c0024 |
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| 155 | #define ixSMU_MAIN_PLL_OP_FREQ 0xe0003020 |
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| 156 | #define ixSMU_STATUS 0xe0003088 |
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| 157 | #define ixSMU_FIRMWARE 0xe00030a4 |
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| 158 | #define ixSMU_INPUT_DATA 0xe00030b8 |
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| 159 | #define ixSMU_EFUSE_0 0xc0100000 |
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| 160 | #define ixDPM_TABLE_1 0x3f000 |
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| 161 | #define ixDPM_TABLE_2 0x3f004 |
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| 162 | #define ixDPM_TABLE_3 0x3f008 |
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| 163 | #define ixDPM_TABLE_4 0x3f00c |
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| 164 | #define ixDPM_TABLE_5 0x3f010 |
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| 165 | #define ixDPM_TABLE_6 0x3f014 |
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| 166 | #define ixDPM_TABLE_7 0x3f018 |
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| 167 | #define ixDPM_TABLE_8 0x3f01c |
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| 168 | #define ixDPM_TABLE_9 0x3f020 |
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| 169 | #define ixDPM_TABLE_10 0x3f024 |
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| 170 | #define ixDPM_TABLE_11 0x3f028 |
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| 171 | #define ixDPM_TABLE_12 0x3f02c |
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| 172 | #define ixDPM_TABLE_13 0x3f030 |
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| 173 | #define ixDPM_TABLE_14 0x3f034 |
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| 174 | #define ixDPM_TABLE_15 0x3f038 |
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| 175 | #define ixDPM_TABLE_16 0x3f03c |
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| 176 | #define ixDPM_TABLE_17 0x3f040 |
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| 177 | #define ixDPM_TABLE_18 0x3f044 |
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| 178 | #define ixDPM_TABLE_19 0x3f048 |
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| 179 | #define ixDPM_TABLE_20 0x3f04c |
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| 180 | #define ixDPM_TABLE_21 0x3f050 |
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| 181 | #define ixDPM_TABLE_22 0x3f054 |
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| 182 | #define ixDPM_TABLE_23 0x3f058 |
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| 183 | #define ixDPM_TABLE_24 0x3f05c |
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| 184 | #define ixDPM_TABLE_25 0x3f060 |
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| 185 | #define ixDPM_TABLE_26 0x3f064 |
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| 186 | #define ixDPM_TABLE_27 0x3f068 |
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| 187 | #define ixDPM_TABLE_28 0x3f06c |
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| 188 | #define ixDPM_TABLE_29 0x3f070 |
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| 189 | #define ixDPM_TABLE_30 0x3f074 |
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| 190 | #define ixDPM_TABLE_31 0x3f078 |
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| 191 | #define ixDPM_TABLE_32 0x3f07c |
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| 192 | #define ixDPM_TABLE_33 0x3f080 |
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| 193 | #define ixDPM_TABLE_34 0x3f084 |
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| 194 | #define ixDPM_TABLE_35 0x3f088 |
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| 195 | #define ixDPM_TABLE_36 0x3f08c |
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| 196 | #define ixDPM_TABLE_37 0x3f090 |
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| 197 | #define ixDPM_TABLE_38 0x3f094 |
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| 198 | #define ixDPM_TABLE_39 0x3f098 |
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| 199 | #define ixDPM_TABLE_40 0x3f09c |
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| 200 | #define ixDPM_TABLE_41 0x3f0a0 |
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| 201 | #define ixDPM_TABLE_42 0x3f0a4 |
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| 202 | #define ixDPM_TABLE_43 0x3f0a8 |
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| 203 | #define ixDPM_TABLE_44 0x3f0ac |
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| 204 | #define ixDPM_TABLE_45 0x3f0b0 |
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| 205 | #define ixDPM_TABLE_46 0x3f0b4 |
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| 206 | #define ixDPM_TABLE_47 0x3f0b8 |
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| 207 | #define ixDPM_TABLE_48 0x3f0bc |
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| 208 | #define ixDPM_TABLE_49 0x3f0c0 |
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| 209 | #define ixDPM_TABLE_50 0x3f0c4 |
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| 210 | #define ixDPM_TABLE_51 0x3f0c8 |
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| 211 | #define ixDPM_TABLE_52 0x3f0cc |
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| 212 | #define ixDPM_TABLE_53 0x3f0d0 |
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| 213 | #define ixDPM_TABLE_54 0x3f0d4 |
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| 214 | #define ixDPM_TABLE_55 0x3f0d8 |
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| 215 | #define ixDPM_TABLE_56 0x3f0dc |
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| 216 | #define ixDPM_TABLE_57 0x3f0e0 |
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| 217 | #define ixDPM_TABLE_58 0x3f0e4 |
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| 218 | #define ixDPM_TABLE_59 0x3f0e8 |
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| 219 | #define ixDPM_TABLE_60 0x3f0ec |
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| 220 | #define ixDPM_TABLE_61 0x3f0f0 |
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| 221 | #define ixDPM_TABLE_62 0x3f0f4 |
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| 222 | #define ixDPM_TABLE_63 0x3f0f8 |
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| 223 | #define ixDPM_TABLE_64 0x3f0fc |
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| 224 | #define ixDPM_TABLE_65 0x3f100 |
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| 225 | #define ixDPM_TABLE_66 0x3f104 |
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| 226 | #define ixDPM_TABLE_67 0x3f108 |
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| 227 | #define ixDPM_TABLE_68 0x3f10c |
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| 228 | #define ixDPM_TABLE_69 0x3f110 |
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| 229 | #define ixDPM_TABLE_70 0x3f114 |
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| 230 | #define ixDPM_TABLE_71 0x3f118 |
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| 231 | #define ixDPM_TABLE_72 0x3f11c |
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| 232 | #define ixDPM_TABLE_73 0x3f120 |
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| 233 | #define ixDPM_TABLE_74 0x3f124 |
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| 234 | #define ixDPM_TABLE_75 0x3f128 |
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| 235 | #define ixDPM_TABLE_76 0x3f12c |
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| 236 | #define ixDPM_TABLE_77 0x3f130 |
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| 237 | #define ixDPM_TABLE_78 0x3f134 |
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| 238 | #define ixDPM_TABLE_79 0x3f138 |
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| 239 | #define ixDPM_TABLE_80 0x3f13c |
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| 240 | #define ixDPM_TABLE_81 0x3f140 |
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| 241 | #define ixDPM_TABLE_82 0x3f144 |
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| 242 | #define ixDPM_TABLE_83 0x3f148 |
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| 243 | #define ixDPM_TABLE_84 0x3f14c |
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| 244 | #define ixDPM_TABLE_85 0x3f150 |
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| 245 | #define ixDPM_TABLE_86 0x3f154 |
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| 246 | #define ixDPM_TABLE_87 0x3f158 |
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| 247 | #define ixDPM_TABLE_88 0x3f15c |
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| 248 | #define ixDPM_TABLE_89 0x3f160 |
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| 249 | #define ixDPM_TABLE_90 0x3f164 |
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| 250 | #define ixDPM_TABLE_91 0x3f168 |
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| 251 | #define ixDPM_TABLE_92 0x3f16c |
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| 252 | #define ixDPM_TABLE_93 0x3f170 |
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| 253 | #define ixDPM_TABLE_94 0x3f174 |
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| 254 | #define ixDPM_TABLE_95 0x3f178 |
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| 255 | #define ixDPM_TABLE_96 0x3f17c |
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| 256 | #define ixDPM_TABLE_97 0x3f180 |
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| 257 | #define ixDPM_TABLE_98 0x3f184 |
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| 258 | #define ixDPM_TABLE_99 0x3f188 |
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| 259 | #define ixDPM_TABLE_100 0x3f18c |
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| 260 | #define ixDPM_TABLE_101 0x3f190 |
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| 261 | #define ixDPM_TABLE_102 0x3f194 |
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| 262 | #define ixDPM_TABLE_103 0x3f198 |
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| 263 | #define ixDPM_TABLE_104 0x3f19c |
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| 264 | #define ixDPM_TABLE_105 0x3f1a0 |
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| 265 | #define ixDPM_TABLE_106 0x3f1a4 |
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| 266 | #define ixDPM_TABLE_107 0x3f1a8 |
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| 267 | #define ixDPM_TABLE_108 0x3f1ac |
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| 268 | #define ixDPM_TABLE_109 0x3f1b0 |
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| 269 | #define ixDPM_TABLE_110 0x3f1b4 |
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| 270 | #define ixDPM_TABLE_111 0x3f1b8 |
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| 271 | #define ixDPM_TABLE_112 0x3f1bc |
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| 272 | #define ixDPM_TABLE_113 0x3f1c0 |
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| 273 | #define ixDPM_TABLE_114 0x3f1c4 |
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| 274 | #define ixDPM_TABLE_115 0x3f1c8 |
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| 275 | #define ixDPM_TABLE_116 0x3f1cc |
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| 276 | #define ixDPM_TABLE_117 0x3f1d0 |
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| 277 | #define ixDPM_TABLE_118 0x3f1d4 |
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| 278 | #define ixDPM_TABLE_119 0x3f1d8 |
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| 279 | #define ixDPM_TABLE_120 0x3f1dc |
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| 280 | #define ixDPM_TABLE_121 0x3f1e0 |
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| 281 | #define ixDPM_TABLE_122 0x3f1e4 |
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| 282 | #define ixDPM_TABLE_123 0x3f1e8 |
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| 283 | #define ixDPM_TABLE_124 0x3f1ec |
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| 284 | #define ixDPM_TABLE_125 0x3f1f0 |
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| 285 | #define ixDPM_TABLE_126 0x3f1f4 |
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| 286 | #define ixDPM_TABLE_127 0x3f1f8 |
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| 287 | #define ixDPM_TABLE_128 0x3f1fc |
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| 288 | #define ixDPM_TABLE_129 0x3f200 |
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| 289 | #define ixDPM_TABLE_130 0x3f204 |
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| 290 | #define ixDPM_TABLE_131 0x3f208 |
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| 291 | #define ixDPM_TABLE_132 0x3f20c |
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| 292 | #define ixDPM_TABLE_133 0x3f210 |
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| 293 | #define ixDPM_TABLE_134 0x3f214 |
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| 294 | #define ixDPM_TABLE_135 0x3f218 |
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| 295 | #define ixDPM_TABLE_136 0x3f21c |
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| 296 | #define ixDPM_TABLE_137 0x3f220 |
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| 297 | #define ixDPM_TABLE_138 0x3f224 |
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| 298 | #define ixDPM_TABLE_139 0x3f228 |
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| 299 | #define ixDPM_TABLE_140 0x3f22c |
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| 300 | #define ixDPM_TABLE_141 0x3f230 |
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| 301 | #define ixDPM_TABLE_142 0x3f234 |
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| 302 | #define ixDPM_TABLE_143 0x3f238 |
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| 303 | #define ixDPM_TABLE_144 0x3f23c |
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| 304 | #define ixDPM_TABLE_145 0x3f240 |
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| 305 | #define ixDPM_TABLE_146 0x3f244 |
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| 306 | #define ixDPM_TABLE_147 0x3f248 |
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| 307 | #define ixDPM_TABLE_148 0x3f24c |
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| 308 | #define ixDPM_TABLE_149 0x3f250 |
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| 309 | #define ixDPM_TABLE_150 0x3f254 |
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| 310 | #define ixDPM_TABLE_151 0x3f258 |
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| 311 | #define ixDPM_TABLE_152 0x3f25c |
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| 312 | #define ixDPM_TABLE_153 0x3f260 |
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| 313 | #define ixDPM_TABLE_154 0x3f264 |
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| 314 | #define ixDPM_TABLE_155 0x3f268 |
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| 315 | #define ixDPM_TABLE_156 0x3f26c |
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| 316 | #define ixDPM_TABLE_157 0x3f270 |
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| 317 | #define ixDPM_TABLE_158 0x3f274 |
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| 318 | #define ixDPM_TABLE_159 0x3f278 |
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| 319 | #define ixDPM_TABLE_160 0x3f27c |
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| 320 | #define ixDPM_TABLE_161 0x3f280 |
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| 321 | #define ixDPM_TABLE_162 0x3f284 |
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| 322 | #define ixDPM_TABLE_163 0x3f288 |
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| 323 | #define ixDPM_TABLE_164 0x3f28c |
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| 324 | #define ixDPM_TABLE_165 0x3f290 |
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| 325 | #define ixDPM_TABLE_166 0x3f294 |
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| 326 | #define ixDPM_TABLE_167 0x3f298 |
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| 327 | #define ixDPM_TABLE_168 0x3f29c |
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| 328 | #define ixDPM_TABLE_169 0x3f2a0 |
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| 329 | #define ixDPM_TABLE_170 0x3f2a4 |
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| 330 | #define ixDPM_TABLE_171 0x3f2a8 |
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| 331 | #define ixDPM_TABLE_172 0x3f2ac |
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| 332 | #define ixDPM_TABLE_173 0x3f2b0 |
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| 333 | #define ixDPM_TABLE_174 0x3f2b4 |
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| 334 | #define ixDPM_TABLE_175 0x3f2b8 |
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| 335 | #define ixDPM_TABLE_176 0x3f2bc |
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| 336 | #define ixDPM_TABLE_177 0x3f2c0 |
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| 337 | #define ixDPM_TABLE_178 0x3f2c4 |
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| 338 | #define ixDPM_TABLE_179 0x3f2c8 |
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| 339 | #define ixDPM_TABLE_180 0x3f2cc |
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| 340 | #define ixDPM_TABLE_181 0x3f2d0 |
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| 341 | #define ixDPM_TABLE_182 0x3f2d4 |
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| 342 | #define ixDPM_TABLE_183 0x3f2d8 |
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| 343 | #define ixDPM_TABLE_184 0x3f2dc |
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| 344 | #define ixDPM_TABLE_185 0x3f2e0 |
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| 345 | #define ixDPM_TABLE_186 0x3f2e4 |
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| 346 | #define ixDPM_TABLE_187 0x3f2e8 |
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| 347 | #define ixDPM_TABLE_188 0x3f2ec |
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| 348 | #define ixDPM_TABLE_189 0x3f2f0 |
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| 349 | #define ixDPM_TABLE_190 0x3f2f4 |
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| 350 | #define ixDPM_TABLE_191 0x3f2f8 |
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| 351 | #define ixSOFT_REGISTERS_TABLE_1 0x3f900 |
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| 352 | #define ixSOFT_REGISTERS_TABLE_2 0x3f904 |
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| 353 | #define ixSOFT_REGISTERS_TABLE_3 0x3f908 |
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| 354 | #define ixSOFT_REGISTERS_TABLE_4 0x3f90c |
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| 355 | #define ixSOFT_REGISTERS_TABLE_5 0x3f910 |
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| 356 | #define ixSOFT_REGISTERS_TABLE_6 0x3f914 |
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| 357 | #define ixSOFT_REGISTERS_TABLE_7 0x3f918 |
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| 358 | #define ixSOFT_REGISTERS_TABLE_8 0x3f91c |
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| 359 | #define ixSOFT_REGISTERS_TABLE_9 0x3f920 |
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| 360 | #define ixSOFT_REGISTERS_TABLE_10 0x3f924 |
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| 361 | #define ixSOFT_REGISTERS_TABLE_11 0x3f928 |
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| 362 | #define ixSOFT_REGISTERS_TABLE_12 0x3f92c |
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| 363 | #define ixSOFT_REGISTERS_TABLE_13 0x3f930 |
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| 364 | #define ixSOFT_REGISTERS_TABLE_14 0x3f934 |
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| 365 | #define ixSOFT_REGISTERS_TABLE_15 0x3f938 |
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| 366 | #define ixSOFT_REGISTERS_TABLE_16 0x3f93c |
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| 367 | #define ixSOFT_REGISTERS_TABLE_17 0x3f940 |
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| 368 | #define ixSOFT_REGISTERS_TABLE_18 0x3f944 |
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| 369 | #define ixSOFT_REGISTERS_TABLE_19 0x3f948 |
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| 370 | #define ixSOFT_REGISTERS_TABLE_20 0x3f94c |
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| 371 | #define ixSOFT_REGISTERS_TABLE_21 0x3f950 |
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| 372 | #define ixSMU_LCLK_DPM_STATE_0_CNTL_0 0x3fd00 |
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| 373 | #define ixSMU_LCLK_DPM_STATE_1_CNTL_0 0x3fd14 |
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| 374 | #define ixSMU_LCLK_DPM_STATE_2_CNTL_0 0x3fd28 |
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| 375 | #define ixSMU_LCLK_DPM_STATE_3_CNTL_0 0x3fd3c |
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| 376 | #define ixSMU_LCLK_DPM_STATE_4_CNTL_0 0x3fd50 |
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| 377 | #define ixSMU_LCLK_DPM_STATE_5_CNTL_0 0x3fd64 |
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| 378 | #define ixSMU_LCLK_DPM_STATE_6_CNTL_0 0x3fd78 |
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| 379 | #define ixSMU_LCLK_DPM_STATE_7_CNTL_0 0x3fd8c |
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| 380 | #define ixSMU_LCLK_DPM_STATE_0_CNTL_1 0x3fd04 |
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| 381 | #define ixSMU_LCLK_DPM_STATE_1_CNTL_1 0x3fd18 |
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| 382 | #define ixSMU_LCLK_DPM_STATE_2_CNTL_1 0x3fd2c |
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| 383 | #define ixSMU_LCLK_DPM_STATE_3_CNTL_1 0x3fd40 |
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| 384 | #define ixSMU_LCLK_DPM_STATE_4_CNTL_1 0x3fd54 |
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| 385 | #define ixSMU_LCLK_DPM_STATE_5_CNTL_1 0x3fd68 |
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| 386 | #define ixSMU_LCLK_DPM_STATE_6_CNTL_1 0x3fd7c |
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| 387 | #define ixSMU_LCLK_DPM_STATE_7_CNTL_1 0x3fd90 |
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| 388 | #define ixSMU_LCLK_DPM_STATE_0_CNTL_2 0x3fd08 |
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| 389 | #define ixSMU_LCLK_DPM_STATE_1_CNTL_2 0x3fd1c |
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| 390 | #define ixSMU_LCLK_DPM_STATE_2_CNTL_2 0x3fd30 |
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| 391 | #define ixSMU_LCLK_DPM_STATE_3_CNTL_2 0x3fd44 |
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| 392 | #define ixSMU_LCLK_DPM_STATE_4_CNTL_2 0x3fd58 |
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| 393 | #define ixSMU_LCLK_DPM_STATE_5_CNTL_2 0x3fd6c |
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| 394 | #define ixSMU_LCLK_DPM_STATE_6_CNTL_2 0x3fd80 |
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| 395 | #define ixSMU_LCLK_DPM_STATE_7_CNTL_2 0x3fd94 |
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| 396 | #define ixSMU_LCLK_DPM_STATE_0_CNTL_3 0x3fd0c |
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| 397 | #define ixSMU_LCLK_DPM_STATE_1_CNTL_3 0x3fd20 |
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| 398 | #define ixSMU_LCLK_DPM_STATE_2_CNTL_3 0x3fd34 |
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| 399 | #define ixSMU_LCLK_DPM_STATE_3_CNTL_3 0x3fd48 |
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| 400 | #define ixSMU_LCLK_DPM_STATE_4_CNTL_3 0x3fd5c |
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| 401 | #define ixSMU_LCLK_DPM_STATE_5_CNTL_3 0x3fd70 |
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| 402 | #define ixSMU_LCLK_DPM_STATE_6_CNTL_3 0x3fd84 |
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| 403 | #define ixSMU_LCLK_DPM_STATE_7_CNTL_3 0x3fd98 |
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| 404 | #define ixSMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD 0x3fd10 |
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| 405 | #define ixSMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD 0x3fd24 |
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| 406 | #define ixSMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD 0x3fd38 |
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| 407 | #define ixSMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD 0x3fd4c |
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| 408 | #define ixSMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD 0x3fd60 |
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| 409 | #define ixSMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD 0x3fd74 |
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| 410 | #define ixSMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD 0x3fd88 |
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| 411 | #define ixSMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD 0x3fd9c |
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| 412 | #define ixGIO_PID_CONTROLLER_CNTL_0 0x3fda0 |
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| 413 | #define ixGIO_PID_CONTROLLER_CNTL_1 0x3fda4 |
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| 414 | #define ixGIO_PID_CONTROLLER_CNTL_2 0x3fda8 |
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| 415 | #define ixGIO_PID_CONTROLLER_CNTL_3 0x3fdac |
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| 416 | #define ixGIO_PID_CONTROLLER_CNTL_4 0x3fdb0 |
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| 417 | #define ixGIO_PID_CONTROLLER_CNTL_5 0x3fdb4 |
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| 418 | #define ixGIO_PID_CONTROLLER_CNTL_6 0x3fdb8 |
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| 419 | #define ixGIO_PID_CONTROLLER_CNTL_7 0x3fdbc |
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| 420 | #define ixGIO_PID_CONTROLLER_CNTL_8 0x3fdc0 |
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| 421 | #define ixSMU_LCLK_DPM_LEVEL_COUNT 0x3fdc4 |
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| 422 | #define ixSMU_LCLK_DPM_CNTL 0x3fdc8 |
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| 423 | #define ixSMU_LCLK_DPM_CURRENT_AND_TARGET_STATE 0x3fdcc |
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| 424 | #define ixSMU_LCLK_DPM_THERMAL_THROTTLING_CNTL 0x3fdd0 |
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| 425 | #define ixSMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS 0x3fdd4 |
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| 426 | #define ixPM_FUSES_1 0x3fa80 |
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| 427 | #define ixPM_FUSES_2 0x3fa84 |
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| 428 | #define ixPM_FUSES_3 0x3fa88 |
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| 429 | #define ixPM_FUSES_4 0x3fa8c |
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| 430 | #define ixPM_FUSES_5 0x3fa90 |
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| 431 | #define ixPM_FUSES_6 0x3fa94 |
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| 432 | #define ixPM_FUSES_7 0x3fa98 |
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| 433 | #define ixPM_FUSES_8 0x3fa9c |
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| 434 | #define ixPM_FUSES_9 0x3faa0 |
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| 435 | #define ixPM_FUSES_10 0x3faa4 |
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| 436 | #define ixPM_FUSES_11 0x3faa8 |
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| 437 | #define ixPM_FUSES_12 0x3faac |
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| 438 | #define ixPM_FUSES_13 0x3fab0 |
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| 439 | #define ixPM_FUSES_14 0x3fab4 |
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| 440 | #define ixPM_FUSES_15 0x3fab8 |
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| 441 | #define ixPM_FUSES_16 0x3fabc |
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| 442 | #define ixPM_FUSES_17 0x3fac0 |
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| 443 | #define ixPM_FUSES_18 0x3fac4 |
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| 444 | #define ixPM_FUSES_19 0x3fac8 |
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| 445 | #define ixPM_FUSES_20 0x3facc |
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| 446 | #define ixPM_FUSES_21 0x3fad0 |
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| 447 | #define ixPM_FUSES_22 0x3fad4 |
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| 448 | #define ixPM_FUSES_23 0x3fad8 |
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| 449 | #define ixPM_FUSES_24 0x3fadc |
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| 450 | #define ixPM_FUSES_25 0x3fae0 |
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| 451 | #define ixPM_FUSES_26 0x3fae4 |
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| 452 | #define ixPM_FUSES_27 0x3fae8 |
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| 453 | #define ixPM_FUSES_28 0x3faec |
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| 454 | #define ixPM_FUSES_29 0x3faf0 |
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| 455 | #define ixPM_FUSES_30 0x3faf4 |
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| 456 | #define ixPM_FUSES_31 0x3faf8 |
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| 457 | #define ixPM_FUSES_32 0x3fafc |
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| 458 | #define ixPM_FUSES_33 0x3fb00 |
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| 459 | #define ixPM_FUSES_34 0x3fb04 |
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| 460 | #define ixPM_FUSES_35 0x3fb08 |
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| 461 | #define ixPM_FUSES_36 0x3fb0c |
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| 462 | #define ixPM_FUSES_37 0x3fb10 |
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| 463 | #define ixPM_FUSES_38 0x3fb14 |
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| 464 | #define ixPM_FUSES_39 0x3fb18 |
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| 465 | #define ixPM_FUSES_40 0x3fb1c |
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| 466 | #define ixPM_FUSES_41 0x3fb20 |
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| 467 | #define ixPM_FUSES_42 0x3fb24 |
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| 468 | #define ixPM_FUSES_43 0x3fb28 |
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| 469 | #define ixPM_FUSES_44 0x3fb2c |
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| 470 | #define ixPM_FUSES_45 0x3fb30 |
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| 471 | #define ixPM_FUSES_46 0x3fb34 |
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| 472 | #define ixPM_FUSES_47 0x3fb38 |
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| 473 | #define ixPM_FUSES_48 0x3fb3c |
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| 474 | #define ixPM_FUSES_49 0x3fb40 |
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| 475 | #define ixPM_FUSES_50 0x3fb44 |
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| 476 | #define ixPM_FUSES_51 0x3fb48 |
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| 477 | #define ixPM_FUSES_52 0x3fb4c |
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| 478 | #define ixPM_FUSES_53 0x3fb50 |
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| 479 | #define ixPM_FUSES_54 0x3fb54 |
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| 480 | #define ixPM_FUSES_55 0x3fb58 |
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| 481 | #define ixPM_FUSES_56 0x3fb5c |
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| 482 | #define ixPM_FUSES_57 0x3fb60 |
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| 483 | #define ixPM_FUSES_58 0x3fb64 |
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| 484 | #define ixPM_FUSES_59 0x3fb68 |
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| 485 | #define ixPM_FUSES_60 0x3fb6c |
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| 486 | #define ixPM_FUSES_61 0x3fb70 |
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| 487 | #define ixPM_FUSES_62 0x3fb74 |
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| 488 | #define ixPM_FUSES_63 0x3fb78 |
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| 489 | #define ixPM_FUSES_64 0x3fb7c |
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| 490 | #define ixPM_FUSES_65 0x3fb80 |
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| 491 | #define ixFIRMWARE_FLAGS 0x3f800 |
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| 492 | #define ixTEMPERATURE_READ_ADDR 0x3f808 |
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| 493 | #define ixCURRENT_GNB_TEMP 0x3f810 |
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| 494 | #define ixCURRENT_GLOBAL_TEMP 0x3f814 |
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| 495 | #define ixFEATURE_STATUS 0x3f818 |
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| 496 | #define ixPCIE_PLL_RECONF 0x3f81c |
|---|
| 497 | #define ixPM_INTERVAL_CNTL_0 0x3f820 |
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| 498 | #define ixPM_INTERVAL_CNTL_1 0x3f824 |
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| 499 | #define ixPM_INTERVAL_CNTL_2 0x3f82c |
|---|
| 500 | #define ixVPC_INTERVAL_CNTL 0x3f830 |
|---|
| 501 | #define ixDISP_PHY_TDP_LIMIT 0x3f834 |
|---|
| 502 | #define ixFCH_PWR_CREDIT 0x3f838 |
|---|
| 503 | #define ixPKGPWR_MV_AVG 0x3f83c |
|---|
| 504 | #define ixPACKAGE_POWER 0x3f840 |
|---|
| 505 | #define ixPKG_PWR_CNTL 0x3f844 |
|---|
| 506 | #define ixPKG_PWR_STATUS 0x3f848 |
|---|
| 507 | #define ixDISP_PHY_CONFIG 0x3f84c |
|---|
| 508 | #define ixGPU_TDP_LIMIT 0x3f850 |
|---|
| 509 | #define ixEXT_API_IN_DATA_0_0 0x3f858 |
|---|
| 510 | #define ixEXT_API_IN_DATA_0_1 0x3f85c |
|---|
| 511 | #define ixEXT_API_IN_DATA_0_2 0x3f860 |
|---|
| 512 | #define ixEXT_API_IN_DATA_0_3 0x3f864 |
|---|
| 513 | #define ixEXT_API_OUT_DATA_0_0 0x3f868 |
|---|
| 514 | #define ixEXT_API_OUT_DATA_0_1 0x3f86c |
|---|
| 515 | #define ixEXT_API_OUT_DATA_0_2 0x3f870 |
|---|
| 516 | #define ixEXT_API_OUT_DATA_0_3 0x3f874 |
|---|
| 517 | #define ixBAPM_PARAMETERS 0x3f984 |
|---|
| 518 | #define ixBAPM_PARAMETERS_2 0x3f988 |
|---|
| 519 | #define ixBAPM_PARAMETERS_3 0x3f98c |
|---|
| 520 | #define ixBAPM_PARAMETERS_4 0x3f990 |
|---|
| 521 | #define ixSMU_SVI_TELEMETRY 0x3f994 |
|---|
| 522 | #define ixBAPM_STATUS 0x3f998 |
|---|
| 523 | #define ixSMU_HTC_STATUS 0x3f99c |
|---|
| 524 | #define ixSMU_VPC_STATUS 0x3f9a0 |
|---|
| 525 | #define ixENTITY_TEMPERATURES_1 0x3f9a4 |
|---|
| 526 | #define ixENTITY_TEMPERATURES_2 0x3f9a8 |
|---|
| 527 | #define ixENTITY_TEMPERATURES_3 0x3f9ac |
|---|
| 528 | #define ixCU_POWER 0x3f9b0 |
|---|
| 529 | #define ixGPU_POWER 0x3f9b4 |
|---|
| 530 | #define ixNTE_POWER 0x3f9b8 |
|---|
| 531 | #define ixTDC_STATUS 0x3f9d0 |
|---|
| 532 | #define ixTDC_MV_AVERAGE 0x3f9d4 |
|---|
| 533 | #define ixPM_CONFIG 0x3f9d8 |
|---|
| 534 | #define ixTE0_TEMPERATURE_READ_ADDR 0x3f9dc |
|---|
| 535 | #define ixTE1_TEMPERATURE_READ_ADDR 0x3f9e0 |
|---|
| 536 | #define ixTE2_TEMPERATURE_READ_ADDR 0x3f9e4 |
|---|
| 537 | #define ixNB_DPM_CONFIG_1 0x3f9e8 |
|---|
| 538 | #define ixNB_DPM_CONFIG_2 0x3f9ec |
|---|
| 539 | #define ixNB_DPM_CONFIG_3 0x3f9f0 |
|---|
| 540 | #define ixSMU_IDD_OVERRIDE 0x3f9fc |
|---|
| 541 | #define ixAVS_CONFIG 0x3fa00 |
|---|
| 542 | #define ixTDC_VRM_LIMIT 0x3fa04 |
|---|
| 543 | #define ixCU0_PSM_CONFIG 0x3fa08 |
|---|
| 544 | #define ixCU1_PSM_CONFIG 0x3fa0c |
|---|
| 545 | #define ixSPMI_CONFIG 0x3fa10 |
|---|
| 546 | #define ixSPMI_SMC_CHAIN_ADDR 0x3fa14 |
|---|
| 547 | #define ixSPMI_STATUS 0x3fa30 |
|---|
| 548 | #define ixAVSNB_CONFIG 0x3fa34 |
|---|
| 549 | #define ixHTC_CONFIG 0x3fa38 |
|---|
| 550 | #define ixAVS_CU0_TEMPERATURE_SENSOR 0x3fa3c |
|---|
| 551 | #define ixAVS_CU1_TEMPERATURE_SENSOR 0x3fa40 |
|---|
| 552 | #define ixAVS_GNB_TEMPERATURE_SENSOR 0x3fa44 |
|---|
| 553 | #define ixAVS_UNB_TEMPERATURE_SENSOR 0x3fa48 |
|---|
| 554 | #define ixSMU_MONITOR_PORT80_MMIO_ADDR 0x3fa4c |
|---|
| 555 | #define ixSMU_MONITOR_PORT80_MEMBASE_HI 0x3fa50 |
|---|
| 556 | #define ixSMU_MONITOR_PORT80_MEMBASE_LO 0x3fa54 |
|---|
| 557 | #define ixSMU_MONITOR_PORT80_MEMSETUP 0x3fa58 |
|---|
| 558 | #define ixSMU_MONITOR_PORT80_CTRL 0x3fa5c |
|---|
| 559 | #define ixSMU_TCEN_ALIVE 0x3fa60 |
|---|
| 560 | #define ixPDM_STATUS 0x3fa64 |
|---|
| 561 | #define ixPDM_CNTL_1 0x3fa68 |
|---|
| 562 | #define ixPDM_CNTL_2 0x3fa6c |
|---|
| 563 | #define ixPDM_CNTL_3 0x3fa70 |
|---|
| 564 | #define ixSMU_PM_STATUS_0 0x3fe00 |
|---|
| 565 | #define ixSMU_PM_STATUS_1 0x3fe04 |
|---|
| 566 | #define ixSMU_PM_STATUS_2 0x3fe08 |
|---|
| 567 | #define ixSMU_PM_STATUS_3 0x3fe0c |
|---|
| 568 | #define ixSMU_PM_STATUS_4 0x3fe10 |
|---|
| 569 | #define ixSMU_PM_STATUS_5 0x3fe14 |
|---|
| 570 | #define ixSMU_PM_STATUS_6 0x3fe18 |
|---|
| 571 | #define ixSMU_PM_STATUS_7 0x3fe1c |
|---|
| 572 | #define ixSMU_PM_STATUS_8 0x3fe20 |
|---|
| 573 | #define ixSMU_PM_STATUS_9 0x3fe24 |
|---|
| 574 | #define ixSMU_PM_STATUS_10 0x3fe28 |
|---|
| 575 | #define ixSMU_PM_STATUS_11 0x3fe2c |
|---|
| 576 | #define ixSMU_PM_STATUS_12 0x3fe30 |
|---|
| 577 | #define ixSMU_PM_STATUS_13 0x3fe34 |
|---|
| 578 | #define ixSMU_PM_STATUS_14 0x3fe38 |
|---|
| 579 | #define ixSMU_PM_STATUS_15 0x3fe3c |
|---|
| 580 | #define ixSMU_PM_STATUS_16 0x3fe40 |
|---|
| 581 | #define ixSMU_PM_STATUS_17 0x3fe44 |
|---|
| 582 | #define ixSMU_PM_STATUS_18 0x3fe48 |
|---|
| 583 | #define ixSMU_PM_STATUS_19 0x3fe4c |
|---|
| 584 | #define ixSMU_PM_STATUS_20 0x3fe50 |
|---|
| 585 | #define ixSMU_PM_STATUS_21 0x3fe54 |
|---|
| 586 | #define ixSMU_PM_STATUS_22 0x3fe58 |
|---|
| 587 | #define ixSMU_PM_STATUS_23 0x3fe5c |
|---|
| 588 | #define ixSMU_PM_STATUS_24 0x3fe60 |
|---|
| 589 | #define ixSMU_PM_STATUS_25 0x3fe64 |
|---|
| 590 | #define ixSMU_PM_STATUS_26 0x3fe68 |
|---|
| 591 | #define ixSMU_PM_STATUS_27 0x3fe6c |
|---|
| 592 | #define ixSMU_PM_STATUS_28 0x3fe70 |
|---|
| 593 | #define ixSMU_PM_STATUS_29 0x3fe74 |
|---|
| 594 | #define ixSMU_PM_STATUS_30 0x3fe78 |
|---|
| 595 | #define ixSMU_PM_STATUS_31 0x3fe7c |
|---|
| 596 | #define ixSMU_PM_STATUS_32 0x3fe80 |
|---|
| 597 | #define ixSMU_PM_STATUS_33 0x3fe84 |
|---|
| 598 | #define ixSMU_PM_STATUS_34 0x3fe88 |
|---|
| 599 | #define ixSMU_PM_STATUS_35 0x3fe8c |
|---|
| 600 | #define ixSMU_PM_STATUS_36 0x3fe90 |
|---|
| 601 | #define ixSMU_PM_STATUS_37 0x3fe94 |
|---|
| 602 | #define ixSMU_PM_STATUS_38 0x3fe98 |
|---|
| 603 | #define ixSMU_PM_STATUS_39 0x3fe9c |
|---|
| 604 | #define ixSMU_PM_STATUS_40 0x3fea0 |
|---|
| 605 | #define ixSMU_PM_STATUS_41 0x3fea4 |
|---|
| 606 | #define ixSMU_PM_STATUS_42 0x3fea8 |
|---|
| 607 | #define ixSMU_PM_STATUS_43 0x3feac |
|---|
| 608 | #define ixSMU_PM_STATUS_44 0x3feb0 |
|---|
| 609 | #define ixSMU_PM_STATUS_45 0x3feb4 |
|---|
| 610 | #define ixSMU_PM_STATUS_46 0x3feb8 |
|---|
| 611 | #define ixSMU_PM_STATUS_47 0x3febc |
|---|
| 612 | #define ixSMU_PM_STATUS_48 0x3fec0 |
|---|
| 613 | #define ixSMU_PM_STATUS_49 0x3fec4 |
|---|
| 614 | #define ixSMU_PM_STATUS_50 0x3fec8 |
|---|
| 615 | #define ixSMU_PM_STATUS_51 0x3fecc |
|---|
| 616 | #define ixSMU_PM_STATUS_52 0x3fed0 |
|---|
| 617 | #define ixSMU_PM_STATUS_53 0x3fed4 |
|---|
| 618 | #define ixSMU_PM_STATUS_54 0x3fed8 |
|---|
| 619 | #define ixSMU_PM_STATUS_55 0x3fedc |
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| 620 | #define ixSMU_PM_STATUS_56 0x3fee0 |
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| 621 | #define ixSMU_PM_STATUS_57 0x3fee4 |
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| 622 | #define ixSMU_PM_STATUS_58 0x3fee8 |
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| 623 | #define ixSMU_PM_STATUS_59 0x3feec |
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| 624 | #define ixSMU_PM_STATUS_60 0x3fef0 |
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| 625 | #define ixSMU_PM_STATUS_61 0x3fef4 |
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| 626 | #define ixSMU_PM_STATUS_62 0x3fef8 |
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| 627 | #define ixSMU_PM_STATUS_63 0x3fefc |
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| 628 | #define ixSMU_PM_STATUS_64 0x3ff00 |
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| 629 | #define ixSMU_PM_STATUS_65 0x3ff04 |
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| 630 | #define ixSMU_PM_STATUS_66 0x3ff08 |
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| 631 | #define ixSMU_PM_STATUS_67 0x3ff0c |
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| 632 | #define ixSMU_PM_STATUS_68 0x3ff10 |
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| 633 | #define ixSMU_PM_STATUS_69 0x3ff14 |
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| 634 | #define ixSMU_PM_STATUS_70 0x3ff18 |
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| 635 | #define ixSMU_PM_STATUS_71 0x3ff1c |
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| 636 | #define ixSMU_PM_STATUS_72 0x3ff20 |
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| 637 | #define ixSMU_PM_STATUS_73 0x3ff24 |
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| 638 | #define ixSMU_PM_STATUS_74 0x3ff28 |
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| 639 | #define ixSMU_PM_STATUS_75 0x3ff2c |
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| 640 | #define ixSMU_PM_STATUS_76 0x3ff30 |
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| 641 | #define ixSMU_PM_STATUS_77 0x3ff34 |
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| 642 | #define ixSMU_PM_STATUS_78 0x3ff38 |
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| 643 | #define ixSMU_PM_STATUS_79 0x3ff3c |
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| 644 | #define ixSMU_PM_STATUS_80 0x3ff40 |
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| 645 | #define ixSMU_PM_STATUS_81 0x3ff44 |
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| 646 | #define ixSMU_PM_STATUS_82 0x3ff48 |
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| 647 | #define ixSMU_PM_STATUS_83 0x3ff4c |
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| 648 | #define ixSMU_PM_STATUS_84 0x3ff50 |
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| 649 | #define ixSMU_PM_STATUS_85 0x3ff54 |
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| 650 | #define ixSMU_PM_STATUS_86 0x3ff58 |
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| 651 | #define ixSMU_PM_STATUS_87 0x3ff5c |
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| 652 | #define ixSMU_PM_STATUS_88 0x3ff60 |
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| 653 | #define ixSMU_PM_STATUS_89 0x3ff64 |
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| 654 | #define ixSMU_PM_STATUS_90 0x3ff68 |
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| 655 | #define ixSMU_PM_STATUS_91 0x3ff6c |
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| 656 | #define ixSMU_PM_STATUS_92 0x3ff70 |
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| 657 | #define ixSMU_PM_STATUS_93 0x3ff74 |
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| 658 | #define ixSMU_PM_STATUS_94 0x3ff78 |
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| 659 | #define ixSMU_PM_STATUS_95 0x3ff7c |
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| 660 | #define ixSMU_PM_STATUS_96 0x3ff80 |
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| 661 | #define ixSMU_PM_STATUS_97 0x3ff84 |
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| 662 | #define ixSMU_PM_STATUS_98 0x3ff88 |
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| 663 | #define ixSMU_PM_STATUS_99 0x3ff8c |
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| 664 | #define ixSMU_PM_STATUS_100 0x3ff90 |
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| 665 | #define ixSMU_PM_STATUS_101 0x3ff94 |
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| 666 | #define ixSMU_PM_STATUS_102 0x3ff98 |
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| 667 | #define ixSMU_PM_STATUS_103 0x3ff9c |
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| 668 | #define ixSMU_PM_STATUS_104 0x3ffa0 |
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| 669 | #define ixSMU_PM_STATUS_105 0x3ffa4 |
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| 670 | #define ixSMU_PM_STATUS_106 0x3ffa8 |
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| 671 | #define ixSMU_PM_STATUS_107 0x3ffac |
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| 672 | #define ixSMU_PM_STATUS_108 0x3ffb0 |
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| 673 | #define ixSMU_PM_STATUS_109 0x3ffb4 |
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| 674 | #define ixSMU_PM_STATUS_110 0x3ffb8 |
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| 675 | #define ixSMU_PM_STATUS_111 0x3ffbc |
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| 676 | #define ixSMU_PM_STATUS_112 0x3ffc0 |
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| 677 | #define ixSMU_PM_STATUS_113 0x3ffc4 |
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| 678 | #define ixSMU_PM_STATUS_114 0x3ffc8 |
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| 679 | #define ixSMU_PM_STATUS_115 0x3ffcc |
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| 680 | #define ixSMU_PM_STATUS_116 0x3ffd0 |
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| 681 | #define ixSMU_PM_STATUS_117 0x3ffd4 |
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| 682 | #define ixSMU_PM_STATUS_118 0x3ffd8 |
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| 683 | #define ixSMU_PM_STATUS_119 0x3ffdc |
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| 684 | #define ixSMU_PM_STATUS_120 0x3ffe0 |
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| 685 | #define ixSMU_PM_STATUS_121 0x3ffe4 |
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| 686 | #define ixSMU_PM_STATUS_122 0x3ffe8 |
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| 687 | #define ixSMU_PM_STATUS_123 0x3ffec |
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| 688 | #define ixSMU_PM_STATUS_124 0x3fff0 |
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| 689 | #define ixSMU_PM_STATUS_125 0x3fff4 |
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| 690 | #define ixSMU_PM_STATUS_126 0x3fff8 |
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| 691 | #define ixSMU_PM_STATUS_127 0x3fffc |
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| 692 | #define ixCG_THERMAL_INT_ENA 0xc2100024 |
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| 693 | #define ixCG_THERMAL_INT_CTRL 0xc2100028 |
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| 694 | #define ixCG_THERMAL_INT_STATUS 0xc210002c |
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| 695 | #define ixGENERAL_PWRMGT 0xc0200000 |
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| 696 | #define ixCNB_PWRMGT_CNTL 0xc0200004 |
|---|
| 697 | #define ixSCLK_PWRMGT_CNTL 0xc0200008 |
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| 698 | #define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xc0200014 |
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| 699 | #define ixCG_FREQ_TRAN_VOTING_0 0xc02001a8 |
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| 700 | #define ixCG_FREQ_TRAN_VOTING_1 0xc02001ac |
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| 701 | #define ixCG_FREQ_TRAN_VOTING_2 0xc02001b0 |
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| 702 | #define ixCG_FREQ_TRAN_VOTING_3 0xc02001b4 |
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| 703 | #define ixCG_FREQ_TRAN_VOTING_4 0xc02001b8 |
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| 704 | #define ixCG_FREQ_TRAN_VOTING_5 0xc02001bc |
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| 705 | #define ixCG_FREQ_TRAN_VOTING_6 0xc02001c0 |
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| 706 | #define ixCG_FREQ_TRAN_VOTING_7 0xc02001c4 |
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| 707 | #define ixPLL_TEST_CNTL 0xc020003c |
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| 708 | #define ixCG_STATIC_SCREEN_PARAMETER 0xc0200044 |
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| 709 | #define ixCG_DISPLAY_GAP_CNTL 0xc0200060 |
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| 710 | #define ixCG_DISPLAY_GAP_CNTL2 0xc0200230 |
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| 711 | #define ixCG_ACPI_CNTL 0xc0200064 |
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| 712 | #define ixSCLK_DEEP_SLEEP_CNTL 0xc0200080 |
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| 713 | #define ixSCLK_DEEP_SLEEP_CNTL2 0xc0200084 |
|---|
| 714 | #define ixSCLK_DEEP_SLEEP_CNTL3 0xc020009c |
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| 715 | #define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xc0200088 |
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| 716 | #define ixLCLK_DEEP_SLEEP_CNTL 0xc020008c |
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| 717 | #define ixLCLK_DEEP_SLEEP_CNTL2 0xc0200310 |
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| 718 | #define ixSMU_VOLTAGE_STATUS 0xc0200094 |
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| 719 | #define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xc02000f0 |
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| 720 | #define ixCG_ULV_PARAMETER 0xc020015c |
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| 721 | #define ixSCLK_MIN_DIV 0xc0200308 |
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| 722 | #define ixLCAC_SX0_CNTL 0xc0400d00 |
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| 723 | #define ixLCAC_SX0_OVR_SEL 0xc0400d04 |
|---|
| 724 | #define ixLCAC_SX0_OVR_VAL 0xc0400d08 |
|---|
| 725 | #define ixLCAC_MC0_CNTL 0xc0400d30 |
|---|
| 726 | #define ixLCAC_MC0_OVR_SEL 0xc0400d34 |
|---|
| 727 | #define ixLCAC_MC0_OVR_VAL 0xc0400d38 |
|---|
| 728 | #define ixLCAC_MC1_CNTL 0xc0400d3c |
|---|
| 729 | #define ixLCAC_MC1_OVR_SEL 0xc0400d40 |
|---|
| 730 | #define ixLCAC_MC1_OVR_VAL 0xc0400d44 |
|---|
| 731 | #define ixLCAC_MC2_CNTL 0xc0400d48 |
|---|
| 732 | #define ixLCAC_MC2_OVR_SEL 0xc0400d4c |
|---|
| 733 | #define ixLCAC_MC2_OVR_VAL 0xc0400d50 |
|---|
| 734 | #define ixLCAC_MC3_CNTL 0xc0400d54 |
|---|
| 735 | #define ixLCAC_MC3_OVR_SEL 0xc0400d58 |
|---|
| 736 | #define ixLCAC_MC3_OVR_VAL 0xc0400d5c |
|---|
| 737 | #define ixLCAC_CPL_CNTL 0xc0400d80 |
|---|
| 738 | #define ixLCAC_CPL_OVR_SEL 0xc0400d84 |
|---|
| 739 | #define ixLCAC_CPL_OVR_VAL 0xc0400d88 |
|---|
| 740 | |
|---|
| 741 | #endif /* SMU_7_0_0_D_H */ |
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| 742 | |
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