| 1 | /* |
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| 2 | * Copyright 2022 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | */ |
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| 23 | #ifndef _smuio_13_0_3_SH_MASK_HEADER |
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| 24 | #define |
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| 25 | |
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| 26 | |
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| 27 | // addressBlock: aid_smuio_smuio_reset_SmuSmuioDec |
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| 28 | //SMUIO_MP_RESET_INTR |
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| 29 | #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR__SHIFT 0x0 |
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| 30 | #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR_MASK 0x00000001L |
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| 31 | //SMUIO_SOC_HALT |
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| 32 | #define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN__SHIFT 0x2 |
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| 33 | #define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN__SHIFT 0x3 |
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| 34 | #define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN_MASK 0x00000004L |
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| 35 | #define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN_MASK 0x00000008L |
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| 36 | |
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| 37 | |
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| 38 | // addressBlock: aid_smuio_smuio_tsc_SmuSmuioDec |
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| 39 | //PWROK_REFCLK_GAP_CYCLES |
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| 40 | #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles__SHIFT 0x0 |
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| 41 | #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles__SHIFT 0x8 |
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| 42 | #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles_MASK 0x000000FFL |
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| 43 | #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles_MASK 0x0000FF00L |
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| 44 | //GOLDEN_TSC_INCREMENT_UPPER |
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| 45 | #define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper__SHIFT 0x0 |
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| 46 | #define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper_MASK 0x00FFFFFFL |
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| 47 | //GOLDEN_TSC_INCREMENT_LOWER |
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| 48 | #define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower__SHIFT 0x0 |
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| 49 | #define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower_MASK 0xFFFFFFFFL |
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| 50 | //GOLDEN_TSC_COUNT_UPPER |
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| 51 | #define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper__SHIFT 0x0 |
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| 52 | #define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper_MASK 0x00FFFFFFL |
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| 53 | //GOLDEN_TSC_COUNT_LOWER |
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| 54 | #define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower__SHIFT 0x0 |
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| 55 | #define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower_MASK 0xFFFFFFFFL |
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| 56 | //SOC_GOLDEN_TSC_SHADOW_UPPER |
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| 57 | #define SOC_GOLDEN_TSC_SHADOW_UPPER__SocGoldenTscShadowUpper__SHIFT 0x0 |
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| 58 | #define SOC_GOLDEN_TSC_SHADOW_UPPER__SocGoldenTscShadowUpper_MASK 0x00FFFFFFL |
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| 59 | //SOC_GOLDEN_TSC_SHADOW_LOWER |
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| 60 | #define SOC_GOLDEN_TSC_SHADOW_LOWER__SocGoldenTscShadowLower__SHIFT 0x0 |
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| 61 | #define SOC_GOLDEN_TSC_SHADOW_LOWER__SocGoldenTscShadowLower_MASK 0xFFFFFFFFL |
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| 62 | //SOC_GAP_PWROK |
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| 63 | #define SOC_GAP_PWROK__soc_gap_pwrok__SHIFT 0x0 |
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| 64 | #define SOC_GAP_PWROK__soc_gap_pwrok_MASK 0x00000001L |
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| 65 | |
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| 66 | |
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| 67 | // addressBlock: aid_smuio_smuio_swtimer_SmuSmuioDec |
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| 68 | //PWR_VIRT_RESET_REQ |
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| 69 | #define PWR_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0 |
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| 70 | #define PWR_VIRT_RESET_REQ__PF_FLR__SHIFT 0x1f |
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| 71 | #define PWR_VIRT_RESET_REQ__VF_FLR_MASK 0x7FFFFFFFL |
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| 72 | #define PWR_VIRT_RESET_REQ__PF_FLR_MASK 0x80000000L |
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| 73 | //PWR_DISP_TIMER_CONTROL |
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| 74 | #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 |
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| 75 | #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 |
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| 76 | #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a |
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| 77 | #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b |
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| 78 | #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c |
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| 79 | #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d |
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| 80 | #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e |
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| 81 | #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL |
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| 82 | #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L |
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| 83 | #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L |
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| 84 | #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L |
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| 85 | #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L |
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| 86 | #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L |
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| 87 | #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L |
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| 88 | //PWR_DISP_TIMER_DEBUG |
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| 89 | #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0 |
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| 90 | #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1 |
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| 91 | #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT__SHIFT 0x2 |
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| 92 | #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7 |
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| 93 | #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x00000001L |
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| 94 | #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT_MASK 0x00000002L |
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| 95 | #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_MASK 0x00000004L |
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| 96 | #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xFFFFFF80L |
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| 97 | //PWR_DISP_TIMER2_CONTROL |
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| 98 | #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 |
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| 99 | #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 |
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| 100 | #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a |
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| 101 | #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b |
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| 102 | #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c |
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| 103 | #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d |
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| 104 | #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e |
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| 105 | #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL |
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| 106 | #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L |
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| 107 | #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L |
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| 108 | #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L |
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| 109 | #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L |
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| 110 | #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L |
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| 111 | #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L |
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| 112 | //PWR_DISP_TIMER2_DEBUG |
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| 113 | #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0 |
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| 114 | #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1 |
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| 115 | #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT__SHIFT 0x2 |
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| 116 | #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7 |
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| 117 | #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x00000001L |
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| 118 | #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT_MASK 0x00000002L |
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| 119 | #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_MASK 0x00000004L |
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| 120 | #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xFFFFFF80L |
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| 121 | //PWR_DISP_TIMER_GLOBAL_CONTROL |
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| 122 | #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0 |
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| 123 | #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN__SHIFT 0xa |
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| 124 | #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH_MASK 0x000003FFL |
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| 125 | #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN_MASK 0x00000400L |
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| 126 | //PWR_IH_CONTROL |
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| 127 | #define PWR_IH_CONTROL__MAX_CREDIT__SHIFT 0x0 |
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| 128 | #define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK__SHIFT 0x5 |
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| 129 | #define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK__SHIFT 0x6 |
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| 130 | #define PWR_IH_CONTROL__PWR_IH_CLK_GATE_EN__SHIFT 0x1f |
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| 131 | #define PWR_IH_CONTROL__MAX_CREDIT_MASK 0x0000001FL |
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| 132 | #define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK_MASK 0x00000020L |
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| 133 | #define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK_MASK 0x00000040L |
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| 134 | #define PWR_IH_CONTROL__PWR_IH_CLK_GATE_EN_MASK 0x80000000L |
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| 135 | |
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| 136 | |
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| 137 | // addressBlock: aid_smuio_smuio_misc_SmuSmuioDec |
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| 138 | //SMUIO_MCM_CONFIG |
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| 139 | #define SMUIO_MCM_CONFIG__DIE_ID__SHIFT 0x0 |
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| 140 | #define SMUIO_MCM_CONFIG__PKG_TYPE__SHIFT 0x2 |
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| 141 | #define SMUIO_MCM_CONFIG__SOCKET_ID__SHIFT 0x8 |
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| 142 | #define SMUIO_MCM_CONFIG__PKG_SUBTYPE__SHIFT 0xc |
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| 143 | #define SMUIO_MCM_CONFIG__CONSOLE_K__SHIFT 0x10 |
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| 144 | #define SMUIO_MCM_CONFIG__CONSOLE_A__SHIFT 0x11 |
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| 145 | #define SMUIO_MCM_CONFIG__TOPOLOGY_ID__SHIFT 0x12 |
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| 146 | #define SMUIO_MCM_CONFIG__DIE_ID_MASK 0x00000003L |
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| 147 | #define SMUIO_MCM_CONFIG__PKG_TYPE_MASK 0x0000003CL |
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| 148 | #define SMUIO_MCM_CONFIG__SOCKET_ID_MASK 0x00000F00L |
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| 149 | #define SMUIO_MCM_CONFIG__PKG_SUBTYPE_MASK 0x00001000L |
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| 150 | #define SMUIO_MCM_CONFIG__CONSOLE_K_MASK 0x00010000L |
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| 151 | #define SMUIO_MCM_CONFIG__CONSOLE_A_MASK 0x00020000L |
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| 152 | #define SMUIO_MCM_CONFIG__TOPOLOGY_ID_MASK 0x007C0000L |
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| 153 | //IP_DISCOVERY_VERSION |
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| 154 | #define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION__SHIFT 0x0 |
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| 155 | #define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION_MASK 0xFFFFFFFFL |
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| 156 | //SCRATCH_REGISTER0 |
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| 157 | #define SCRATCH_REGISTER0__ScratchPad0__SHIFT 0x0 |
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| 158 | #define SCRATCH_REGISTER0__ScratchPad0_MASK 0xFFFFFFFFL |
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| 159 | //SCRATCH_REGISTER1 |
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| 160 | #define SCRATCH_REGISTER1__ScratchPad1__SHIFT 0x0 |
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| 161 | #define SCRATCH_REGISTER1__ScratchPad1_MASK 0xFFFFFFFFL |
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| 162 | //SCRATCH_REGISTER2 |
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| 163 | #define SCRATCH_REGISTER2__ScratchPad2__SHIFT 0x0 |
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| 164 | #define SCRATCH_REGISTER2__ScratchPad2_MASK 0xFFFFFFFFL |
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| 165 | //SCRATCH_REGISTER3 |
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| 166 | #define SCRATCH_REGISTER3__ScratchPad3__SHIFT 0x0 |
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| 167 | #define SCRATCH_REGISTER3__ScratchPad3_MASK 0xFFFFFFFFL |
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| 168 | //SCRATCH_REGISTER4 |
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| 169 | #define SCRATCH_REGISTER4__ScratchPad4__SHIFT 0x0 |
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| 170 | #define SCRATCH_REGISTER4__ScratchPad4_MASK 0xFFFFFFFFL |
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| 171 | //SCRATCH_REGISTER5 |
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| 172 | #define SCRATCH_REGISTER5__ScratchPad5__SHIFT 0x0 |
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| 173 | #define SCRATCH_REGISTER5__ScratchPad5_MASK 0xFFFFFFFFL |
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| 174 | //SCRATCH_REGISTER6 |
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| 175 | #define SCRATCH_REGISTER6__ScratchPad6__SHIFT 0x0 |
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| 176 | #define SCRATCH_REGISTER6__ScratchPad6_MASK 0xFFFFFFFFL |
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| 177 | //SCRATCH_REGISTER7 |
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| 178 | #define SCRATCH_REGISTER7__ScratchPad7__SHIFT 0x0 |
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| 179 | #define SCRATCH_REGISTER7__ScratchPad7_MASK 0xFFFFFFFFL |
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| 180 | |
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| 181 | |
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| 182 | // addressBlock: aid_smuio_smuio_gpio_SmuSmuioDec |
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| 183 | //SMU_GPIOPAD_SW_INT_STAT |
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| 184 | #define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0 |
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| 185 | #define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x00000001L |
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| 186 | //SMU_GPIOPAD_MASK |
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| 187 | #define SMU_GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0 |
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| 188 | #define SMU_GPIOPAD_MASK__GPIO_MASK_MASK 0x7FFFFFFFL |
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| 189 | //SMU_GPIOPAD_A |
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| 190 | #define SMU_GPIOPAD_A__GPIO_A__SHIFT 0x0 |
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| 191 | #define SMU_GPIOPAD_A__GPIO_A_MASK 0x7FFFFFFFL |
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| 192 | //SMU_GPIOPAD_TXIMPSEL |
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| 193 | #define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL__SHIFT 0x0 |
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| 194 | #define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL_MASK 0x7FFFFFFFL |
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| 195 | //SMU_GPIOPAD_EN |
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| 196 | #define SMU_GPIOPAD_EN__GPIO_EN__SHIFT 0x0 |
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| 197 | #define SMU_GPIOPAD_EN__GPIO_EN_MASK 0x7FFFFFFFL |
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| 198 | //SMU_GPIOPAD_Y |
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| 199 | #define SMU_GPIOPAD_Y__GPIO_Y__SHIFT 0x0 |
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| 200 | #define SMU_GPIOPAD_Y__GPIO_Y_MASK 0x7FFFFFFFL |
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| 201 | //SMU_GPIOPAD_RXEN |
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| 202 | #define SMU_GPIOPAD_RXEN__GPIO_RXEN__SHIFT 0x0 |
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| 203 | #define SMU_GPIOPAD_RXEN__GPIO_RXEN_MASK 0x7FFFFFFFL |
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| 204 | //SMU_GPIOPAD_RCVR_SEL0 |
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| 205 | #define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0__SHIFT 0x0 |
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| 206 | #define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0_MASK 0x7FFFFFFFL |
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| 207 | //SMU_GPIOPAD_RCVR_SEL1 |
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| 208 | #define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1__SHIFT 0x0 |
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| 209 | #define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1_MASK 0x7FFFFFFFL |
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| 210 | //SMU_GPIOPAD_PU_EN |
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| 211 | #define SMU_GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0 |
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| 212 | #define SMU_GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7FFFFFFFL |
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| 213 | //SMU_GPIOPAD_PD_EN |
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| 214 | #define SMU_GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0 |
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| 215 | #define SMU_GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7FFFFFFFL |
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| 216 | //SMU_GPIOPAD_PINSTRAPS |
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| 217 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0 |
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| 218 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1 |
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| 219 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2 |
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| 220 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3 |
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| 221 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4 |
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| 222 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5 |
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| 223 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6 |
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| 224 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7 |
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| 225 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8 |
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| 226 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9 |
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| 227 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa |
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| 228 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb |
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| 229 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc |
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| 230 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd |
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| 231 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe |
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| 232 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf |
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| 233 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10 |
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| 234 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11 |
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| 235 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12 |
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| 236 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13 |
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| 237 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14 |
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| 238 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15 |
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| 239 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16 |
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| 240 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17 |
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| 241 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18 |
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| 242 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19 |
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| 243 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a |
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| 244 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b |
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| 245 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c |
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| 246 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d |
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| 247 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e |
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| 248 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x00000001L |
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| 249 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x00000002L |
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| 250 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x00000004L |
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| 251 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x00000008L |
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| 252 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x00000010L |
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| 253 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x00000020L |
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| 254 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x00000040L |
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| 255 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x00000080L |
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| 256 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x00000100L |
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| 257 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x00000200L |
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| 258 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x00000400L |
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| 259 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x00000800L |
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| 260 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x00001000L |
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| 261 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x00002000L |
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| 262 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x00004000L |
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| 263 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x00008000L |
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| 264 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x00010000L |
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| 265 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x00020000L |
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| 266 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x00040000L |
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| 267 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x00080000L |
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| 268 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x00100000L |
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| 269 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x00200000L |
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| 270 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x00400000L |
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| 271 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x00800000L |
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| 272 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x01000000L |
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| 273 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x02000000L |
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| 274 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x04000000L |
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| 275 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x08000000L |
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| 276 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000L |
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| 277 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000L |
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| 278 | #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000L |
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| 279 | //DFT_PINSTRAPS |
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| 280 | #define DFT_PINSTRAPS__DFT_PINSTRAPS__SHIFT 0x0 |
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| 281 | #define DFT_PINSTRAPS__DFT_PINSTRAPS_MASK 0x000003FFL |
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| 282 | //SMU_GPIOPAD_INT_STAT_EN |
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| 283 | #define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0 |
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| 284 | #define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f |
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| 285 | #define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1FFFFFFFL |
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| 286 | #define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000L |
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| 287 | //SMU_GPIOPAD_INT_STAT |
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| 288 | #define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0 |
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| 289 | #define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f |
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| 290 | #define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1FFFFFFFL |
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| 291 | #define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000L |
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| 292 | //SMU_GPIOPAD_INT_STAT_AK |
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| 293 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0 |
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| 294 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1 |
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| 295 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2 |
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| 296 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3 |
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| 297 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4 |
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| 298 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5 |
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| 299 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6 |
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| 300 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7 |
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| 301 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8 |
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| 302 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9 |
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| 303 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa |
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| 304 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb |
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| 305 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc |
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| 306 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd |
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| 307 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe |
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| 308 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf |
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| 309 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10 |
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| 310 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11 |
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| 311 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12 |
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| 312 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13 |
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| 313 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14 |
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| 314 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15 |
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| 315 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16 |
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| 316 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17 |
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| 317 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18 |
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| 318 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19 |
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| 319 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a |
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| 320 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b |
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| 321 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c |
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| 322 | #define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f |
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| 323 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x00000001L |
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| 324 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x00000002L |
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| 325 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x00000004L |
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| 326 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x00000008L |
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| 327 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x00000010L |
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| 328 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x00000020L |
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| 329 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x00000040L |
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| 330 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x00000080L |
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| 331 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x00000100L |
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| 332 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x00000200L |
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| 333 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x00000400L |
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| 334 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x00000800L |
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| 335 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x00001000L |
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| 336 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x00002000L |
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| 337 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x00004000L |
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| 338 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x00008000L |
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| 339 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x00010000L |
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| 340 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x00020000L |
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| 341 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x00040000L |
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| 342 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x00080000L |
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| 343 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x00100000L |
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| 344 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x00200000L |
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| 345 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x00400000L |
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| 346 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x00800000L |
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| 347 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x01000000L |
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| 348 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x02000000L |
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| 349 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x04000000L |
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| 350 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x08000000L |
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| 351 | #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000L |
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| 352 | #define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000L |
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| 353 | //SMU_GPIOPAD_INT_EN |
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| 354 | #define SMU_GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0 |
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| 355 | #define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f |
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| 356 | #define SMU_GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1FFFFFFFL |
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| 357 | #define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000L |
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| 358 | //SMU_GPIOPAD_INT_TYPE |
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| 359 | #define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0 |
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| 360 | #define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f |
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| 361 | #define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1FFFFFFFL |
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| 362 | #define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000L |
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| 363 | //SMU_GPIOPAD_INT_POLARITY |
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| 364 | #define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0 |
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| 365 | #define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f |
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| 366 | #define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1FFFFFFFL |
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| 367 | #define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000L |
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| 368 | //SMUIO_PCC_GPIO_SELECT |
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| 369 | #define SMUIO_PCC_GPIO_SELECT__GPIO__SHIFT 0x0 |
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| 370 | #define SMUIO_PCC_GPIO_SELECT__GPIO_MASK 0xFFFFFFFFL |
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| 371 | //SMU_GPIOPAD_S0 |
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| 372 | #define SMU_GPIOPAD_S0__GPIO_S0__SHIFT 0x0 |
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| 373 | #define SMU_GPIOPAD_S0__GPIO_S0_MASK 0x7FFFFFFFL |
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| 374 | //SMU_GPIOPAD_S1 |
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| 375 | #define SMU_GPIOPAD_S1__GPIO_S1__SHIFT 0x0 |
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| 376 | #define SMU_GPIOPAD_S1__GPIO_S1_MASK 0x7FFFFFFFL |
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| 377 | //SMU_GPIOPAD_SCHMEN |
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| 378 | #define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN__SHIFT 0x0 |
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| 379 | #define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN_MASK 0x7FFFFFFFL |
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| 380 | //SMU_GPIOPAD_SCL_EN |
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| 381 | #define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN__SHIFT 0x0 |
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| 382 | #define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN_MASK 0x7FFFFFFFL |
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| 383 | //SMU_GPIOPAD_SDA_EN |
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| 384 | #define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN__SHIFT 0x0 |
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| 385 | #define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN_MASK 0x7FFFFFFFL |
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| 386 | //SMUIO_GPIO_INT0_SELECT |
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| 387 | #define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT__SHIFT 0x0 |
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| 388 | #define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT_MASK 0xFFFFFFFFL |
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| 389 | //SMUIO_GPIO_INT1_SELECT |
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| 390 | #define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT__SHIFT 0x0 |
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| 391 | #define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT_MASK 0xFFFFFFFFL |
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| 392 | //SMUIO_GPIO_INT2_SELECT |
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| 393 | #define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT__SHIFT 0x0 |
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| 394 | #define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT_MASK 0xFFFFFFFFL |
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| 395 | //SMUIO_GPIO_INT3_SELECT |
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| 396 | #define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT__SHIFT 0x0 |
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| 397 | #define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT_MASK 0xFFFFFFFFL |
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| 398 | //SMU_GPIOPAD_MP_INT0_STAT |
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| 399 | #define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT__SHIFT 0x0 |
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| 400 | #define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT_MASK 0x1FFFFFFFL |
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| 401 | //SMU_GPIOPAD_MP_INT1_STAT |
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| 402 | #define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT__SHIFT 0x0 |
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| 403 | #define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT_MASK 0x1FFFFFFFL |
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| 404 | //SMU_GPIOPAD_MP_INT2_STAT |
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| 405 | #define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT__SHIFT 0x0 |
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| 406 | #define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT_MASK 0x1FFFFFFFL |
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| 407 | //SMU_GPIOPAD_MP_INT3_STAT |
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| 408 | #define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT__SHIFT 0x0 |
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| 409 | #define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT_MASK 0x1FFFFFFFL |
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| 410 | //SMIO_INDEX |
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| 411 | #define SMIO_INDEX__SW_SMIO_INDEX__SHIFT 0x0 |
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| 412 | #define SMIO_INDEX__SW_SMIO_INDEX_MASK 0x00000001L |
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| 413 | //S0_VID_SMIO_CNTL |
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| 414 | #define S0_VID_SMIO_CNTL__S0_SMIO_VALUES__SHIFT 0x0 |
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| 415 | #define S0_VID_SMIO_CNTL__S0_SMIO_VALUES_MASK 0xFFFFFFFFL |
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| 416 | //S1_VID_SMIO_CNTL |
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| 417 | #define S1_VID_SMIO_CNTL__S1_SMIO_VALUES__SHIFT 0x0 |
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| 418 | #define S1_VID_SMIO_CNTL__S1_SMIO_VALUES_MASK 0xFFFFFFFFL |
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| 419 | //OPEN_DRAIN_SELECT |
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| 420 | #define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT__SHIFT 0x0 |
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| 421 | #define OPEN_DRAIN_SELECT__RESERVED__SHIFT 0x1f |
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| 422 | #define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT_MASK 0x7FFFFFFFL |
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| 423 | #define OPEN_DRAIN_SELECT__RESERVED_MASK 0x80000000L |
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| 424 | //SMIO_ENABLE |
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| 425 | #define SMIO_ENABLE__SMIO_ENABLE__SHIFT 0x0 |
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| 426 | #define SMIO_ENABLE__SMIO_ENABLE_MASK 0xFFFFFFFFL |
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| 427 | |
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| 428 | #endif |
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| 429 | |
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