1 | /* |
2 | * VCE_2_0 Register documentation |
3 | * |
4 | * Copyright (C) 2014 Advanced Micro Devices, Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included |
14 | * in all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
20 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
22 | */ |
23 | |
24 | #ifndef VCE_2_0_SH_MASK_H |
25 | #define VCE_2_0_SH_MASK_H |
26 | |
27 | #define VCE_STATUS__JOB_BUSY_MASK 0x1 |
28 | #define VCE_STATUS__JOB_BUSY__SHIFT 0x0 |
29 | #define VCE_STATUS__VCPU_REPORT_MASK 0xfe |
30 | #define VCE_STATUS__VCPU_REPORT__SHIFT 0x1 |
31 | #define VCE_STATUS__UENC_BUSY_MASK 0x100 |
32 | #define VCE_STATUS__UENC_BUSY__SHIFT 0x8 |
33 | #define VCE_VCPU_CNTL__CLK_EN_MASK 0x1 |
34 | #define VCE_VCPU_CNTL__CLK_EN__SHIFT 0x0 |
35 | #define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x40000 |
36 | #define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x12 |
37 | #define VCE_VCPU_CACHE_OFFSET0__OFFSET_MASK 0xfffffff |
38 | #define VCE_VCPU_CACHE_OFFSET0__OFFSET__SHIFT 0x0 |
39 | #define VCE_VCPU_CACHE_SIZE0__SIZE_MASK 0xffffff |
40 | #define VCE_VCPU_CACHE_SIZE0__SIZE__SHIFT 0x0 |
41 | #define VCE_VCPU_CACHE_OFFSET1__OFFSET_MASK 0xfffffff |
42 | #define VCE_VCPU_CACHE_OFFSET1__OFFSET__SHIFT 0x0 |
43 | #define VCE_VCPU_CACHE_SIZE1__SIZE_MASK 0xffffff |
44 | #define VCE_VCPU_CACHE_SIZE1__SIZE__SHIFT 0x0 |
45 | #define VCE_VCPU_CACHE_OFFSET2__OFFSET_MASK 0xfffffff |
46 | #define VCE_VCPU_CACHE_OFFSET2__OFFSET__SHIFT 0x0 |
47 | #define VCE_VCPU_CACHE_SIZE2__SIZE_MASK 0xffffff |
48 | #define VCE_VCPU_CACHE_SIZE2__SIZE__SHIFT 0x0 |
49 | #define VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK 0x1 |
50 | #define VCE_SOFT_RESET__ECPU_SOFT_RESET__SHIFT 0x0 |
51 | #define VCE_RB_BASE_LO2__RB_BASE_LO_MASK 0xffffffc0 |
52 | #define VCE_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6 |
53 | #define VCE_RB_BASE_HI2__RB_BASE_HI_MASK 0xffffffff |
54 | #define VCE_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0 |
55 | #define VCE_RB_SIZE2__RB_SIZE_MASK 0x7ffff0 |
56 | #define VCE_RB_SIZE2__RB_SIZE__SHIFT 0x4 |
57 | #define VCE_RB_RPTR2__RB_RPTR_MASK 0x7ffff0 |
58 | #define VCE_RB_RPTR2__RB_RPTR__SHIFT 0x4 |
59 | #define VCE_RB_WPTR2__RB_WPTR_MASK 0x7ffff0 |
60 | #define VCE_RB_WPTR2__RB_WPTR__SHIFT 0x4 |
61 | #define VCE_RB_BASE_LO__RB_BASE_LO_MASK 0xffffffc0 |
62 | #define VCE_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 |
63 | #define VCE_RB_BASE_HI__RB_BASE_HI_MASK 0xffffffff |
64 | #define VCE_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 |
65 | #define VCE_RB_SIZE__RB_SIZE_MASK 0x7ffff0 |
66 | #define VCE_RB_SIZE__RB_SIZE__SHIFT 0x4 |
67 | #define VCE_RB_RPTR__RB_RPTR_MASK 0x7ffff0 |
68 | #define VCE_RB_RPTR__RB_RPTR__SHIFT 0x4 |
69 | #define VCE_RB_WPTR__RB_WPTR_MASK 0x7ffff0 |
70 | #define VCE_RB_WPTR__RB_WPTR__SHIFT 0x4 |
71 | #define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK 0x1 |
72 | #define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON__SHIFT 0x0 |
73 | #define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK 0x2 |
74 | #define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON__SHIFT 0x1 |
75 | #define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK 0x4 |
76 | #define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON__SHIFT 0x2 |
77 | #define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK 0x8 |
78 | #define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN__SHIFT 0x3 |
79 | #define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK 0x8 |
80 | #define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT__SHIFT 0x3 |
81 | #define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK_MASK 0x8 |
82 | #define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK__SHIFT 0x3 |
83 | #define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR_MASK 0xffffffff |
84 | #define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR__SHIFT 0x0 |
85 | #define VCE_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 |
86 | #define VCE_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 |
87 | #define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP_MASK 0x3 |
88 | #define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP__SHIFT 0x0 |
89 | #define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000 |
90 | #define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 |
91 | #define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x3 |
92 | #define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x0 |
93 | #define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP_MASK 0x3ffc |
94 | #define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP__SHIFT 0x2 |
95 | #define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP_MASK 0x3 |
96 | #define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP__SHIFT 0x0 |
97 | #define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP_MASK 0x3ffc |
98 | #define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP__SHIFT 0x2 |
99 | #define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP_MASK 0xff |
100 | #define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP__SHIFT 0x0 |
101 | #define VCE_LMI_CACHE_CTRL__VCPU_EN_MASK 0x1 |
102 | #define VCE_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x0 |
103 | |
104 | #endif /* VCE_2_0_SH_MASK_H */ |
105 | |