| 1 | /* |
|---|
| 2 | * VCE_3_0 Register documentation |
|---|
| 3 | * |
|---|
| 4 | * Copyright (C) 2014 Advanced Micro Devices, Inc. |
|---|
| 5 | * |
|---|
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
|---|
| 7 | * copy of this software and associated documentation files (the "Software"), |
|---|
| 8 | * to deal in the Software without restriction, including without limitation |
|---|
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
|---|
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
|---|
| 11 | * Software is furnished to do so, subject to the following conditions: |
|---|
| 12 | * |
|---|
| 13 | * The above copyright notice and this permission notice shall be included |
|---|
| 14 | * in all copies or substantial portions of the Software. |
|---|
| 15 | * |
|---|
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
|---|
| 17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
|---|
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
|---|
| 19 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
|---|
| 20 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
|---|
| 21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
|---|
| 22 | */ |
|---|
| 23 | |
|---|
| 24 | #ifndef VCE_3_0_D_H |
|---|
| 25 | #define VCE_3_0_D_H |
|---|
| 26 | |
|---|
| 27 | #define mmVCE_STATUS 0x8001 |
|---|
| 28 | #define mmVCE_VCPU_CNTL 0x8005 |
|---|
| 29 | #define mmVCE_VCPU_CACHE_OFFSET0 0x8009 |
|---|
| 30 | #define mmVCE_VCPU_CACHE_SIZE0 0x800a |
|---|
| 31 | #define mmVCE_VCPU_CACHE_OFFSET1 0x800b |
|---|
| 32 | #define mmVCE_VCPU_CACHE_SIZE1 0x800c |
|---|
| 33 | #define mmVCE_VCPU_CACHE_OFFSET2 0x800d |
|---|
| 34 | #define mmVCE_VCPU_CACHE_SIZE2 0x800e |
|---|
| 35 | #define mmVCE_SOFT_RESET 0x8048 |
|---|
| 36 | #define mmVCE_RB_BASE_LO2 0x805b |
|---|
| 37 | #define mmVCE_RB_BASE_HI2 0x805c |
|---|
| 38 | #define mmVCE_RB_SIZE2 0x805d |
|---|
| 39 | #define mmVCE_RB_RPTR2 0x805e |
|---|
| 40 | #define mmVCE_RB_WPTR2 0x805f |
|---|
| 41 | #define mmVCE_RB_BASE_LO 0x8060 |
|---|
| 42 | #define mmVCE_RB_BASE_HI 0x8061 |
|---|
| 43 | #define mmVCE_RB_SIZE 0x8062 |
|---|
| 44 | #define mmVCE_RB_RPTR 0x8063 |
|---|
| 45 | #define mmVCE_RB_WPTR 0x8064 |
|---|
| 46 | #define mmVCE_RB_ARB_CTRL 0x809f |
|---|
| 47 | #define mmVCE_CLOCK_GATING_A 0x80be |
|---|
| 48 | #define mmVCE_CLOCK_GATING_B 0x80bf |
|---|
| 49 | #define mmVCE_RB_BASE_LO3 0x80d4 |
|---|
| 50 | #define mmVCE_RB_BASE_HI3 0x80d5 |
|---|
| 51 | #define mmVCE_RB_SIZE3 0x80d6 |
|---|
| 52 | #define mmVCE_RB_RPTR3 0x80d7 |
|---|
| 53 | #define mmVCE_RB_WPTR3 0x80d8 |
|---|
| 54 | #define mmVCE_UENC_DMA_DCLK_CTRL 0x8390 |
|---|
| 55 | #define mmVCE_UENC_CLOCK_GATING 0x81ef |
|---|
| 56 | #define mmVCE_UENC_REG_CLOCK_GATING 0x81f0 |
|---|
| 57 | #define mmVCE_UENC_CLOCK_GATING_2 0x8210 |
|---|
| 58 | #define mmVCE_SYS_INT_EN 0x8540 |
|---|
| 59 | #define mmVCE_SYS_INT_STATUS 0x8541 |
|---|
| 60 | #define mmVCE_SYS_INT_ACK 0x8541 |
|---|
| 61 | #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR 0x8597 |
|---|
| 62 | #define mmVCE_LMI_CTRL2 0x859d |
|---|
| 63 | #define mmVCE_LMI_SWAP_CNTL3 0x859e |
|---|
| 64 | #define mmVCE_LMI_CTRL 0x85a6 |
|---|
| 65 | #define mmVCE_LMI_STATUS 0x85a7 |
|---|
| 66 | #define mmVCE_LMI_VM_CTRL 0x85a8 |
|---|
| 67 | #define mmVCE_LMI_SWAP_CNTL 0x85ad |
|---|
| 68 | #define mmVCE_LMI_SWAP_CNTL1 0x85ae |
|---|
| 69 | #define mmVCE_LMI_SWAP_CNTL2 0x85b3 |
|---|
| 70 | #define mmVCE_LMI_MISC_CTRL 0x85b5 |
|---|
| 71 | #define mmVCE_LMI_CACHE_CTRL 0x85bd |
|---|
| 72 | |
|---|
| 73 | #endif /* VCE_3_0_D_H */ |
|---|
| 74 | |
|---|
