1 | /* |
2 | * Copyright 2021 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | #ifndef _vcn_4_0_0_SH_MASK_HEADER |
24 | #define |
25 | |
26 | |
27 | // addressBlock: uvd0_uvddec |
28 | //UVD_TOP_CTRL |
29 | #define UVD_TOP_CTRL__STANDARD__SHIFT 0x0 |
30 | #define UVD_TOP_CTRL__STD_VERSION__SHIFT 0x4 |
31 | #define UVD_TOP_CTRL__STANDARD_MASK 0x0000000FL |
32 | #define UVD_TOP_CTRL__STD_VERSION_MASK 0x00000010L |
33 | //UVD_CGC_GATE |
34 | #define UVD_CGC_GATE__SYS__SHIFT 0x0 |
35 | #define UVD_CGC_GATE__UDEC__SHIFT 0x1 |
36 | #define UVD_CGC_GATE__MPEG2__SHIFT 0x2 |
37 | #define UVD_CGC_GATE__REGS__SHIFT 0x3 |
38 | #define UVD_CGC_GATE__RBC__SHIFT 0x4 |
39 | #define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 |
40 | #define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 |
41 | #define UVD_CGC_GATE__IDCT__SHIFT 0x7 |
42 | #define UVD_CGC_GATE__MPRD__SHIFT 0x8 |
43 | #define UVD_CGC_GATE__MPC__SHIFT 0x9 |
44 | #define UVD_CGC_GATE__LBSI__SHIFT 0xa |
45 | #define UVD_CGC_GATE__LRBBM__SHIFT 0xb |
46 | #define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc |
47 | #define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd |
48 | #define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe |
49 | #define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf |
50 | #define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 |
51 | #define UVD_CGC_GATE__WCB__SHIFT 0x11 |
52 | #define UVD_CGC_GATE__VCPU__SHIFT 0x12 |
53 | #define UVD_CGC_GATE__MMSCH__SHIFT 0x14 |
54 | #define UVD_CGC_GATE__LCM0__SHIFT 0x15 |
55 | #define UVD_CGC_GATE__LCM1__SHIFT 0x16 |
56 | #define UVD_CGC_GATE__MIF__SHIFT 0x17 |
57 | #define UVD_CGC_GATE__VREG__SHIFT 0x18 |
58 | #define UVD_CGC_GATE__PE__SHIFT 0x19 |
59 | #define UVD_CGC_GATE__PPU__SHIFT 0x1a |
60 | #define UVD_CGC_GATE__SYS_MASK 0x00000001L |
61 | #define UVD_CGC_GATE__UDEC_MASK 0x00000002L |
62 | #define UVD_CGC_GATE__MPEG2_MASK 0x00000004L |
63 | #define UVD_CGC_GATE__REGS_MASK 0x00000008L |
64 | #define UVD_CGC_GATE__RBC_MASK 0x00000010L |
65 | #define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L |
66 | #define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L |
67 | #define UVD_CGC_GATE__IDCT_MASK 0x00000080L |
68 | #define UVD_CGC_GATE__MPRD_MASK 0x00000100L |
69 | #define UVD_CGC_GATE__MPC_MASK 0x00000200L |
70 | #define UVD_CGC_GATE__LBSI_MASK 0x00000400L |
71 | #define UVD_CGC_GATE__LRBBM_MASK 0x00000800L |
72 | #define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L |
73 | #define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L |
74 | #define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L |
75 | #define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L |
76 | #define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L |
77 | #define UVD_CGC_GATE__WCB_MASK 0x00020000L |
78 | #define UVD_CGC_GATE__VCPU_MASK 0x00040000L |
79 | #define UVD_CGC_GATE__MMSCH_MASK 0x00100000L |
80 | #define UVD_CGC_GATE__LCM0_MASK 0x00200000L |
81 | #define UVD_CGC_GATE__LCM1_MASK 0x00400000L |
82 | #define UVD_CGC_GATE__MIF_MASK 0x00800000L |
83 | #define UVD_CGC_GATE__VREG_MASK 0x01000000L |
84 | #define UVD_CGC_GATE__PE_MASK 0x02000000L |
85 | #define UVD_CGC_GATE__PPU_MASK 0x04000000L |
86 | //UVD_CGC_CTRL |
87 | #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 |
88 | #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 |
89 | #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 |
90 | #define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb |
91 | #define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc |
92 | #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd |
93 | #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe |
94 | #define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf |
95 | #define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 |
96 | #define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 |
97 | #define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 |
98 | #define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 |
99 | #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 |
100 | #define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 |
101 | #define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 |
102 | #define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 |
103 | #define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 |
104 | #define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 |
105 | #define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a |
106 | #define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b |
107 | #define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c |
108 | #define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d |
109 | #define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f |
110 | #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L |
111 | #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL |
112 | #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L |
113 | #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L |
114 | #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L |
115 | #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L |
116 | #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L |
117 | #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L |
118 | #define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L |
119 | #define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L |
120 | #define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L |
121 | #define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L |
122 | #define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L |
123 | #define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L |
124 | #define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L |
125 | #define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L |
126 | #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L |
127 | #define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L |
128 | #define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L |
129 | #define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L |
130 | #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L |
131 | #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L |
132 | #define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L |
133 | //AVM_SUVD_CGC_GATE |
134 | #define AVM_SUVD_CGC_GATE__SRE__SHIFT 0x0 |
135 | #define AVM_SUVD_CGC_GATE__SIT__SHIFT 0x1 |
136 | #define AVM_SUVD_CGC_GATE__SMP__SHIFT 0x2 |
137 | #define AVM_SUVD_CGC_GATE__SCM__SHIFT 0x3 |
138 | #define AVM_SUVD_CGC_GATE__SDB__SHIFT 0x4 |
139 | #define AVM_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 |
140 | #define AVM_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 |
141 | #define AVM_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 |
142 | #define AVM_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 |
143 | #define AVM_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 |
144 | #define AVM_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa |
145 | #define AVM_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb |
146 | #define AVM_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc |
147 | #define AVM_SUVD_CGC_GATE__SCLR__SHIFT 0xd |
148 | #define AVM_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe |
149 | #define AVM_SUVD_CGC_GATE__ENT__SHIFT 0xf |
150 | #define AVM_SUVD_CGC_GATE__IME__SHIFT 0x10 |
151 | #define AVM_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 |
152 | #define AVM_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 |
153 | #define AVM_SUVD_CGC_GATE__SITE__SHIFT 0x13 |
154 | #define AVM_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 |
155 | #define AVM_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 |
156 | #define AVM_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 |
157 | #define AVM_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 |
158 | #define AVM_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 |
159 | #define AVM_SUVD_CGC_GATE__EFC__SHIFT 0x19 |
160 | #define AVM_SUVD_CGC_GATE__SAOE__SHIFT 0x1a |
161 | #define AVM_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b |
162 | #define AVM_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c |
163 | #define AVM_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d |
164 | #define AVM_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e |
165 | #define AVM_SUVD_CGC_GATE__SMPA__SHIFT 0x1f |
166 | #define AVM_SUVD_CGC_GATE__SRE_MASK 0x00000001L |
167 | #define AVM_SUVD_CGC_GATE__SIT_MASK 0x00000002L |
168 | #define AVM_SUVD_CGC_GATE__SMP_MASK 0x00000004L |
169 | #define AVM_SUVD_CGC_GATE__SCM_MASK 0x00000008L |
170 | #define AVM_SUVD_CGC_GATE__SDB_MASK 0x00000010L |
171 | #define AVM_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L |
172 | #define AVM_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L |
173 | #define AVM_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L |
174 | #define AVM_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L |
175 | #define AVM_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L |
176 | #define AVM_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L |
177 | #define AVM_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L |
178 | #define AVM_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L |
179 | #define AVM_SUVD_CGC_GATE__SCLR_MASK 0x00002000L |
180 | #define AVM_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L |
181 | #define AVM_SUVD_CGC_GATE__ENT_MASK 0x00008000L |
182 | #define AVM_SUVD_CGC_GATE__IME_MASK 0x00010000L |
183 | #define AVM_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L |
184 | #define AVM_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L |
185 | #define AVM_SUVD_CGC_GATE__SITE_MASK 0x00080000L |
186 | #define AVM_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L |
187 | #define AVM_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L |
188 | #define AVM_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L |
189 | #define AVM_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L |
190 | #define AVM_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L |
191 | #define AVM_SUVD_CGC_GATE__EFC_MASK 0x02000000L |
192 | #define AVM_SUVD_CGC_GATE__SAOE_MASK 0x04000000L |
193 | #define AVM_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L |
194 | #define AVM_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L |
195 | #define AVM_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L |
196 | #define AVM_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L |
197 | #define AVM_SUVD_CGC_GATE__SMPA_MASK 0x80000000L |
198 | //CDEFE_SUVD_CGC_GATE |
199 | #define CDEFE_SUVD_CGC_GATE__SRE__SHIFT 0x0 |
200 | #define CDEFE_SUVD_CGC_GATE__SIT__SHIFT 0x1 |
201 | #define CDEFE_SUVD_CGC_GATE__SMP__SHIFT 0x2 |
202 | #define CDEFE_SUVD_CGC_GATE__SCM__SHIFT 0x3 |
203 | #define CDEFE_SUVD_CGC_GATE__SDB__SHIFT 0x4 |
204 | #define CDEFE_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 |
205 | #define CDEFE_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 |
206 | #define CDEFE_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 |
207 | #define CDEFE_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 |
208 | #define CDEFE_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 |
209 | #define CDEFE_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa |
210 | #define CDEFE_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb |
211 | #define CDEFE_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc |
212 | #define CDEFE_SUVD_CGC_GATE__SCLR__SHIFT 0xd |
213 | #define CDEFE_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe |
214 | #define CDEFE_SUVD_CGC_GATE__ENT__SHIFT 0xf |
215 | #define CDEFE_SUVD_CGC_GATE__IME__SHIFT 0x10 |
216 | #define CDEFE_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 |
217 | #define CDEFE_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 |
218 | #define CDEFE_SUVD_CGC_GATE__SITE__SHIFT 0x13 |
219 | #define CDEFE_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 |
220 | #define CDEFE_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 |
221 | #define CDEFE_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 |
222 | #define CDEFE_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 |
223 | #define CDEFE_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 |
224 | #define CDEFE_SUVD_CGC_GATE__EFC__SHIFT 0x19 |
225 | #define CDEFE_SUVD_CGC_GATE__SAOE__SHIFT 0x1a |
226 | #define CDEFE_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b |
227 | #define CDEFE_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c |
228 | #define CDEFE_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d |
229 | #define CDEFE_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e |
230 | #define CDEFE_SUVD_CGC_GATE__SMPA__SHIFT 0x1f |
231 | #define CDEFE_SUVD_CGC_GATE__SRE_MASK 0x00000001L |
232 | #define CDEFE_SUVD_CGC_GATE__SIT_MASK 0x00000002L |
233 | #define CDEFE_SUVD_CGC_GATE__SMP_MASK 0x00000004L |
234 | #define CDEFE_SUVD_CGC_GATE__SCM_MASK 0x00000008L |
235 | #define CDEFE_SUVD_CGC_GATE__SDB_MASK 0x00000010L |
236 | #define CDEFE_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L |
237 | #define CDEFE_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L |
238 | #define CDEFE_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L |
239 | #define CDEFE_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L |
240 | #define CDEFE_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L |
241 | #define CDEFE_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L |
242 | #define CDEFE_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L |
243 | #define CDEFE_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L |
244 | #define CDEFE_SUVD_CGC_GATE__SCLR_MASK 0x00002000L |
245 | #define CDEFE_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L |
246 | #define CDEFE_SUVD_CGC_GATE__ENT_MASK 0x00008000L |
247 | #define CDEFE_SUVD_CGC_GATE__IME_MASK 0x00010000L |
248 | #define CDEFE_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L |
249 | #define CDEFE_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L |
250 | #define CDEFE_SUVD_CGC_GATE__SITE_MASK 0x00080000L |
251 | #define CDEFE_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L |
252 | #define CDEFE_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L |
253 | #define CDEFE_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L |
254 | #define CDEFE_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L |
255 | #define CDEFE_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L |
256 | #define CDEFE_SUVD_CGC_GATE__EFC_MASK 0x02000000L |
257 | #define CDEFE_SUVD_CGC_GATE__SAOE_MASK 0x04000000L |
258 | #define CDEFE_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L |
259 | #define CDEFE_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L |
260 | #define CDEFE_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L |
261 | #define CDEFE_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L |
262 | #define CDEFE_SUVD_CGC_GATE__SMPA_MASK 0x80000000L |
263 | //EFC_SUVD_CGC_GATE |
264 | #define EFC_SUVD_CGC_GATE__SRE__SHIFT 0x0 |
265 | #define EFC_SUVD_CGC_GATE__SIT__SHIFT 0x1 |
266 | #define EFC_SUVD_CGC_GATE__SMP__SHIFT 0x2 |
267 | #define EFC_SUVD_CGC_GATE__SCM__SHIFT 0x3 |
268 | #define EFC_SUVD_CGC_GATE__SDB__SHIFT 0x4 |
269 | #define EFC_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 |
270 | #define EFC_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 |
271 | #define EFC_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 |
272 | #define EFC_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 |
273 | #define EFC_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 |
274 | #define EFC_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa |
275 | #define EFC_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb |
276 | #define EFC_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc |
277 | #define EFC_SUVD_CGC_GATE__SCLR__SHIFT 0xd |
278 | #define EFC_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe |
279 | #define EFC_SUVD_CGC_GATE__ENT__SHIFT 0xf |
280 | #define EFC_SUVD_CGC_GATE__IME__SHIFT 0x10 |
281 | #define EFC_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 |
282 | #define EFC_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 |
283 | #define EFC_SUVD_CGC_GATE__SITE__SHIFT 0x13 |
284 | #define EFC_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 |
285 | #define EFC_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 |
286 | #define EFC_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 |
287 | #define EFC_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 |
288 | #define EFC_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 |
289 | #define EFC_SUVD_CGC_GATE__EFC__SHIFT 0x19 |
290 | #define EFC_SUVD_CGC_GATE__SAOE__SHIFT 0x1a |
291 | #define EFC_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b |
292 | #define EFC_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c |
293 | #define EFC_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d |
294 | #define EFC_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e |
295 | #define EFC_SUVD_CGC_GATE__SMPA__SHIFT 0x1f |
296 | #define EFC_SUVD_CGC_GATE__SRE_MASK 0x00000001L |
297 | #define EFC_SUVD_CGC_GATE__SIT_MASK 0x00000002L |
298 | #define EFC_SUVD_CGC_GATE__SMP_MASK 0x00000004L |
299 | #define EFC_SUVD_CGC_GATE__SCM_MASK 0x00000008L |
300 | #define EFC_SUVD_CGC_GATE__SDB_MASK 0x00000010L |
301 | #define EFC_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L |
302 | #define EFC_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L |
303 | #define EFC_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L |
304 | #define EFC_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L |
305 | #define EFC_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L |
306 | #define EFC_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L |
307 | #define EFC_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L |
308 | #define EFC_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L |
309 | #define EFC_SUVD_CGC_GATE__SCLR_MASK 0x00002000L |
310 | #define EFC_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L |
311 | #define EFC_SUVD_CGC_GATE__ENT_MASK 0x00008000L |
312 | #define EFC_SUVD_CGC_GATE__IME_MASK 0x00010000L |
313 | #define EFC_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L |
314 | #define EFC_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L |
315 | #define EFC_SUVD_CGC_GATE__SITE_MASK 0x00080000L |
316 | #define EFC_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L |
317 | #define EFC_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L |
318 | #define EFC_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L |
319 | #define EFC_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L |
320 | #define EFC_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L |
321 | #define EFC_SUVD_CGC_GATE__EFC_MASK 0x02000000L |
322 | #define EFC_SUVD_CGC_GATE__SAOE_MASK 0x04000000L |
323 | #define EFC_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L |
324 | #define EFC_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L |
325 | #define EFC_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L |
326 | #define EFC_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L |
327 | #define EFC_SUVD_CGC_GATE__SMPA_MASK 0x80000000L |
328 | //ENT_SUVD_CGC_GATE |
329 | #define ENT_SUVD_CGC_GATE__SRE__SHIFT 0x0 |
330 | #define ENT_SUVD_CGC_GATE__SIT__SHIFT 0x1 |
331 | #define ENT_SUVD_CGC_GATE__SMP__SHIFT 0x2 |
332 | #define ENT_SUVD_CGC_GATE__SCM__SHIFT 0x3 |
333 | #define ENT_SUVD_CGC_GATE__SDB__SHIFT 0x4 |
334 | #define ENT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 |
335 | #define ENT_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 |
336 | #define ENT_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 |
337 | #define ENT_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 |
338 | #define ENT_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 |
339 | #define ENT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa |
340 | #define ENT_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb |
341 | #define ENT_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc |
342 | #define ENT_SUVD_CGC_GATE__SCLR__SHIFT 0xd |
343 | #define ENT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe |
344 | #define ENT_SUVD_CGC_GATE__ENT__SHIFT 0xf |
345 | #define ENT_SUVD_CGC_GATE__IME__SHIFT 0x10 |
346 | #define ENT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 |
347 | #define ENT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 |
348 | #define ENT_SUVD_CGC_GATE__SITE__SHIFT 0x13 |
349 | #define ENT_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 |
350 | #define ENT_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 |
351 | #define ENT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 |
352 | #define ENT_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 |
353 | #define ENT_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 |
354 | #define ENT_SUVD_CGC_GATE__EFC__SHIFT 0x19 |
355 | #define ENT_SUVD_CGC_GATE__SAOE__SHIFT 0x1a |
356 | #define ENT_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b |
357 | #define ENT_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c |
358 | #define ENT_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d |
359 | #define ENT_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e |
360 | #define ENT_SUVD_CGC_GATE__SMPA__SHIFT 0x1f |
361 | #define ENT_SUVD_CGC_GATE__SRE_MASK 0x00000001L |
362 | #define ENT_SUVD_CGC_GATE__SIT_MASK 0x00000002L |
363 | #define ENT_SUVD_CGC_GATE__SMP_MASK 0x00000004L |
364 | #define ENT_SUVD_CGC_GATE__SCM_MASK 0x00000008L |
365 | #define ENT_SUVD_CGC_GATE__SDB_MASK 0x00000010L |
366 | #define ENT_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L |
367 | #define ENT_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L |
368 | #define ENT_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L |
369 | #define ENT_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L |
370 | #define ENT_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L |
371 | #define ENT_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L |
372 | #define ENT_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L |
373 | #define ENT_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L |
374 | #define ENT_SUVD_CGC_GATE__SCLR_MASK 0x00002000L |
375 | #define ENT_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L |
376 | #define ENT_SUVD_CGC_GATE__ENT_MASK 0x00008000L |
377 | #define ENT_SUVD_CGC_GATE__IME_MASK 0x00010000L |
378 | #define ENT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L |
379 | #define ENT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L |
380 | #define ENT_SUVD_CGC_GATE__SITE_MASK 0x00080000L |
381 | #define ENT_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L |
382 | #define ENT_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L |
383 | #define ENT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L |
384 | #define ENT_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L |
385 | #define ENT_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L |
386 | #define ENT_SUVD_CGC_GATE__EFC_MASK 0x02000000L |
387 | #define ENT_SUVD_CGC_GATE__SAOE_MASK 0x04000000L |
388 | #define ENT_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L |
389 | #define ENT_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L |
390 | #define ENT_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L |
391 | #define ENT_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L |
392 | #define ENT_SUVD_CGC_GATE__SMPA_MASK 0x80000000L |
393 | //IME_SUVD_CGC_GATE |
394 | #define IME_SUVD_CGC_GATE__SRE__SHIFT 0x0 |
395 | #define IME_SUVD_CGC_GATE__SIT__SHIFT 0x1 |
396 | #define IME_SUVD_CGC_GATE__SMP__SHIFT 0x2 |
397 | #define IME_SUVD_CGC_GATE__SCM__SHIFT 0x3 |
398 | #define IME_SUVD_CGC_GATE__SDB__SHIFT 0x4 |
399 | #define IME_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 |
400 | #define IME_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 |
401 | #define IME_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 |
402 | #define IME_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 |
403 | #define IME_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 |
404 | #define IME_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa |
405 | #define IME_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb |
406 | #define IME_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc |
407 | #define IME_SUVD_CGC_GATE__SCLR__SHIFT 0xd |
408 | #define IME_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe |
409 | #define IME_SUVD_CGC_GATE__ENT__SHIFT 0xf |
410 | #define IME_SUVD_CGC_GATE__IME__SHIFT 0x10 |
411 | #define IME_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 |
412 | #define IME_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 |
413 | #define IME_SUVD_CGC_GATE__SITE__SHIFT 0x13 |
414 | #define IME_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 |
415 | #define IME_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 |
416 | #define IME_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 |
417 | #define IME_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 |
418 | #define IME_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 |
419 | #define IME_SUVD_CGC_GATE__EFC__SHIFT 0x19 |
420 | #define IME_SUVD_CGC_GATE__SAOE__SHIFT 0x1a |
421 | #define IME_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b |
422 | #define IME_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c |
423 | #define IME_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d |
424 | #define IME_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e |
425 | #define IME_SUVD_CGC_GATE__SMPA__SHIFT 0x1f |
426 | #define IME_SUVD_CGC_GATE__SRE_MASK 0x00000001L |
427 | #define IME_SUVD_CGC_GATE__SIT_MASK 0x00000002L |
428 | #define IME_SUVD_CGC_GATE__SMP_MASK 0x00000004L |
429 | #define IME_SUVD_CGC_GATE__SCM_MASK 0x00000008L |
430 | #define IME_SUVD_CGC_GATE__SDB_MASK 0x00000010L |
431 | #define IME_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L |
432 | #define IME_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L |
433 | #define IME_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L |
434 | #define IME_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L |
435 | #define IME_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L |
436 | #define IME_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L |
437 | #define IME_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L |
438 | #define IME_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L |
439 | #define IME_SUVD_CGC_GATE__SCLR_MASK 0x00002000L |
440 | #define IME_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L |
441 | #define IME_SUVD_CGC_GATE__ENT_MASK 0x00008000L |
442 | #define IME_SUVD_CGC_GATE__IME_MASK 0x00010000L |
443 | #define IME_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L |
444 | #define IME_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L |
445 | #define IME_SUVD_CGC_GATE__SITE_MASK 0x00080000L |
446 | #define IME_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L |
447 | #define IME_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L |
448 | #define IME_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L |
449 | #define IME_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L |
450 | #define IME_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L |
451 | #define IME_SUVD_CGC_GATE__EFC_MASK 0x02000000L |
452 | #define IME_SUVD_CGC_GATE__SAOE_MASK 0x04000000L |
453 | #define IME_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L |
454 | #define IME_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L |
455 | #define IME_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L |
456 | #define IME_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L |
457 | #define IME_SUVD_CGC_GATE__SMPA_MASK 0x80000000L |
458 | //PPU_SUVD_CGC_GATE |
459 | #define PPU_SUVD_CGC_GATE__SRE__SHIFT 0x0 |
460 | #define PPU_SUVD_CGC_GATE__SIT__SHIFT 0x1 |
461 | #define PPU_SUVD_CGC_GATE__SMP__SHIFT 0x2 |
462 | #define PPU_SUVD_CGC_GATE__SCM__SHIFT 0x3 |
463 | #define PPU_SUVD_CGC_GATE__SDB__SHIFT 0x4 |
464 | #define PPU_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 |
465 | #define PPU_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 |
466 | #define PPU_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 |
467 | #define PPU_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 |
468 | #define PPU_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 |
469 | #define PPU_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa |
470 | #define PPU_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb |
471 | #define PPU_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc |
472 | #define PPU_SUVD_CGC_GATE__SCLR__SHIFT 0xd |
473 | #define PPU_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe |
474 | #define PPU_SUVD_CGC_GATE__ENT__SHIFT 0xf |
475 | #define PPU_SUVD_CGC_GATE__IME__SHIFT 0x10 |
476 | #define PPU_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 |
477 | #define PPU_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 |
478 | #define PPU_SUVD_CGC_GATE__SITE__SHIFT 0x13 |
479 | #define PPU_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 |
480 | #define PPU_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 |
481 | #define PPU_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 |
482 | #define PPU_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 |
483 | #define PPU_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 |
484 | #define PPU_SUVD_CGC_GATE__EFC__SHIFT 0x19 |
485 | #define PPU_SUVD_CGC_GATE__SAOE__SHIFT 0x1a |
486 | #define PPU_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b |
487 | #define PPU_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c |
488 | #define PPU_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d |
489 | #define PPU_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e |
490 | #define PPU_SUVD_CGC_GATE__SMPA__SHIFT 0x1f |
491 | #define PPU_SUVD_CGC_GATE__SRE_MASK 0x00000001L |
492 | #define PPU_SUVD_CGC_GATE__SIT_MASK 0x00000002L |
493 | #define PPU_SUVD_CGC_GATE__SMP_MASK 0x00000004L |
494 | #define PPU_SUVD_CGC_GATE__SCM_MASK 0x00000008L |
495 | #define PPU_SUVD_CGC_GATE__SDB_MASK 0x00000010L |
496 | #define PPU_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L |
497 | #define PPU_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L |
498 | #define PPU_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L |
499 | #define PPU_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L |
500 | #define PPU_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L |
501 | #define PPU_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L |
502 | #define PPU_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L |
503 | #define PPU_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L |
504 | #define PPU_SUVD_CGC_GATE__SCLR_MASK 0x00002000L |
505 | #define PPU_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L |
506 | #define PPU_SUVD_CGC_GATE__ENT_MASK 0x00008000L |
507 | #define PPU_SUVD_CGC_GATE__IME_MASK 0x00010000L |
508 | #define PPU_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L |
509 | #define PPU_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L |
510 | #define PPU_SUVD_CGC_GATE__SITE_MASK 0x00080000L |
511 | #define PPU_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L |
512 | #define PPU_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L |
513 | #define PPU_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L |
514 | #define PPU_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L |
515 | #define PPU_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L |
516 | #define PPU_SUVD_CGC_GATE__EFC_MASK 0x02000000L |
517 | #define PPU_SUVD_CGC_GATE__SAOE_MASK 0x04000000L |
518 | #define PPU_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L |
519 | #define PPU_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L |
520 | #define PPU_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L |
521 | #define PPU_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L |
522 | #define PPU_SUVD_CGC_GATE__SMPA_MASK 0x80000000L |
523 | //SAOE_SUVD_CGC_GATE |
524 | #define SAOE_SUVD_CGC_GATE__SRE__SHIFT 0x0 |
525 | #define SAOE_SUVD_CGC_GATE__SIT__SHIFT 0x1 |
526 | #define SAOE_SUVD_CGC_GATE__SMP__SHIFT 0x2 |
527 | #define SAOE_SUVD_CGC_GATE__SCM__SHIFT 0x3 |
528 | #define SAOE_SUVD_CGC_GATE__SDB__SHIFT 0x4 |
529 | #define SAOE_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 |
530 | #define SAOE_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 |
531 | #define SAOE_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 |
532 | #define SAOE_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 |
533 | #define SAOE_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 |
534 | #define SAOE_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa |
535 | #define SAOE_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb |
536 | #define SAOE_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc |
537 | #define SAOE_SUVD_CGC_GATE__SCLR__SHIFT 0xd |
538 | #define SAOE_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe |
539 | #define SAOE_SUVD_CGC_GATE__ENT__SHIFT 0xf |
540 | #define SAOE_SUVD_CGC_GATE__IME__SHIFT 0x10 |
541 | #define SAOE_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 |
542 | #define SAOE_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 |
543 | #define SAOE_SUVD_CGC_GATE__SITE__SHIFT 0x13 |
544 | #define SAOE_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 |
545 | #define SAOE_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 |
546 | #define SAOE_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 |
547 | #define SAOE_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 |
548 | #define SAOE_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 |
549 | #define SAOE_SUVD_CGC_GATE__EFC__SHIFT 0x19 |
550 | #define SAOE_SUVD_CGC_GATE__SAOE__SHIFT 0x1a |
551 | #define SAOE_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b |
552 | #define SAOE_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c |
553 | #define SAOE_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d |
554 | #define SAOE_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e |
555 | #define SAOE_SUVD_CGC_GATE__SMPA__SHIFT 0x1f |
556 | #define SAOE_SUVD_CGC_GATE__SRE_MASK 0x00000001L |
557 | #define SAOE_SUVD_CGC_GATE__SIT_MASK 0x00000002L |
558 | #define SAOE_SUVD_CGC_GATE__SMP_MASK 0x00000004L |
559 | #define SAOE_SUVD_CGC_GATE__SCM_MASK 0x00000008L |
560 | #define SAOE_SUVD_CGC_GATE__SDB_MASK 0x00000010L |
561 | #define SAOE_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L |
562 | #define SAOE_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L |
563 | #define SAOE_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L |
564 | #define SAOE_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L |
565 | #define SAOE_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L |
566 | #define SAOE_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L |
567 | #define SAOE_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L |
568 | #define SAOE_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L |
569 | #define SAOE_SUVD_CGC_GATE__SCLR_MASK 0x00002000L |
570 | #define SAOE_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L |
571 | #define SAOE_SUVD_CGC_GATE__ENT_MASK 0x00008000L |
572 | #define SAOE_SUVD_CGC_GATE__IME_MASK 0x00010000L |
573 | #define SAOE_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L |
574 | #define SAOE_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L |
575 | #define SAOE_SUVD_CGC_GATE__SITE_MASK 0x00080000L |
576 | #define SAOE_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L |
577 | #define SAOE_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L |
578 | #define SAOE_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L |
579 | #define SAOE_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L |
580 | #define SAOE_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L |
581 | #define SAOE_SUVD_CGC_GATE__EFC_MASK 0x02000000L |
582 | #define SAOE_SUVD_CGC_GATE__SAOE_MASK 0x04000000L |
583 | #define SAOE_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L |
584 | #define SAOE_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L |
585 | #define SAOE_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L |
586 | #define SAOE_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L |
587 | #define SAOE_SUVD_CGC_GATE__SMPA_MASK 0x80000000L |
588 | //SCM_SUVD_CGC_GATE |
589 | #define SCM_SUVD_CGC_GATE__SRE__SHIFT 0x0 |
590 | #define SCM_SUVD_CGC_GATE__SIT__SHIFT 0x1 |
591 | #define SCM_SUVD_CGC_GATE__SMP__SHIFT 0x2 |
592 | #define SCM_SUVD_CGC_GATE__SCM__SHIFT 0x3 |
593 | #define SCM_SUVD_CGC_GATE__SDB__SHIFT 0x4 |
594 | #define SCM_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 |
595 | #define SCM_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 |
596 | #define SCM_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 |
597 | #define SCM_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 |
598 | #define SCM_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 |
599 | #define SCM_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa |
600 | #define SCM_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb |
601 | #define SCM_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc |
602 | #define SCM_SUVD_CGC_GATE__SCLR__SHIFT 0xd |
603 | #define SCM_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe |
604 | #define SCM_SUVD_CGC_GATE__ENT__SHIFT 0xf |
605 | #define SCM_SUVD_CGC_GATE__IME__SHIFT 0x10 |
606 | #define SCM_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 |
607 | #define SCM_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 |
608 | #define SCM_SUVD_CGC_GATE__SITE__SHIFT 0x13 |
609 | #define SCM_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 |
610 | #define SCM_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 |
611 | #define SCM_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 |
612 | #define SCM_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 |
613 | #define SCM_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 |
614 | #define SCM_SUVD_CGC_GATE__EFC__SHIFT 0x19 |
615 | #define SCM_SUVD_CGC_GATE__SAOE__SHIFT 0x1a |
616 | #define SCM_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b |
617 | #define SCM_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c |
618 | #define SCM_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d |
619 | #define SCM_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e |
620 | #define SCM_SUVD_CGC_GATE__SMPA__SHIFT 0x1f |
621 | #define SCM_SUVD_CGC_GATE__SRE_MASK 0x00000001L |
622 | #define SCM_SUVD_CGC_GATE__SIT_MASK 0x00000002L |
623 | #define SCM_SUVD_CGC_GATE__SMP_MASK 0x00000004L |
624 | #define SCM_SUVD_CGC_GATE__SCM_MASK 0x00000008L |
625 | #define SCM_SUVD_CGC_GATE__SDB_MASK 0x00000010L |
626 | #define SCM_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L |
627 | #define SCM_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L |
628 | #define SCM_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L |
629 | #define SCM_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L |
630 | #define SCM_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L |
631 | #define SCM_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L |
632 | #define SCM_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L |
633 | #define SCM_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L |
634 | #define SCM_SUVD_CGC_GATE__SCLR_MASK 0x00002000L |
635 | #define SCM_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L |
636 | #define SCM_SUVD_CGC_GATE__ENT_MASK 0x00008000L |
637 | #define SCM_SUVD_CGC_GATE__IME_MASK 0x00010000L |
638 | #define SCM_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L |
639 | #define SCM_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L |
640 | #define SCM_SUVD_CGC_GATE__SITE_MASK 0x00080000L |
641 | #define SCM_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L |
642 | #define SCM_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L |
643 | #define SCM_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L |
644 | #define SCM_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L |
645 | #define SCM_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L |
646 | #define SCM_SUVD_CGC_GATE__EFC_MASK 0x02000000L |
647 | #define SCM_SUVD_CGC_GATE__SAOE_MASK 0x04000000L |
648 | #define SCM_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L |
649 | #define SCM_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L |
650 | #define SCM_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L |
651 | #define SCM_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L |
652 | #define SCM_SUVD_CGC_GATE__SMPA_MASK 0x80000000L |
653 | //SDB_SUVD_CGC_GATE |
654 | #define SDB_SUVD_CGC_GATE__SRE__SHIFT 0x0 |
655 | #define SDB_SUVD_CGC_GATE__SIT__SHIFT 0x1 |
656 | #define SDB_SUVD_CGC_GATE__SMP__SHIFT 0x2 |
657 | #define SDB_SUVD_CGC_GATE__SCM__SHIFT 0x3 |
658 | #define SDB_SUVD_CGC_GATE__SDB__SHIFT 0x4 |
659 | #define SDB_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 |
660 | #define SDB_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 |
661 | #define SDB_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 |
662 | #define SDB_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 |
663 | #define SDB_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 |
664 | #define SDB_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa |
665 | #define SDB_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb |
666 | #define SDB_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc |
667 | #define SDB_SUVD_CGC_GATE__SCLR__SHIFT 0xd |
668 | #define SDB_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe |
669 | #define SDB_SUVD_CGC_GATE__ENT__SHIFT 0xf |
670 | #define SDB_SUVD_CGC_GATE__IME__SHIFT 0x10 |
671 | #define SDB_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 |
672 | #define SDB_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 |
673 | #define SDB_SUVD_CGC_GATE__SITE__SHIFT 0x13 |
674 | #define SDB_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 |
675 | #define SDB_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 |
676 | #define SDB_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 |
677 | #define SDB_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 |
678 | #define SDB_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 |
679 | #define SDB_SUVD_CGC_GATE__EFC__SHIFT 0x19 |
680 | #define SDB_SUVD_CGC_GATE__SAOE__SHIFT 0x1a |
681 | #define SDB_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b |
682 | #define SDB_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c |
683 | #define SDB_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d |
684 | #define SDB_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e |
685 | #define SDB_SUVD_CGC_GATE__SMPA__SHIFT 0x1f |
686 | #define SDB_SUVD_CGC_GATE__SRE_MASK 0x00000001L |
687 | #define SDB_SUVD_CGC_GATE__SIT_MASK 0x00000002L |
688 | #define SDB_SUVD_CGC_GATE__SMP_MASK 0x00000004L |
689 | #define SDB_SUVD_CGC_GATE__SCM_MASK 0x00000008L |
690 | #define SDB_SUVD_CGC_GATE__SDB_MASK 0x00000010L |
691 | #define SDB_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L |
692 | #define SDB_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L |
693 | #define SDB_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L |
694 | #define SDB_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L |
695 | #define SDB_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L |
696 | #define SDB_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L |
697 | #define SDB_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L |
698 | #define SDB_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L |
699 | #define SDB_SUVD_CGC_GATE__SCLR_MASK 0x00002000L |
700 | #define SDB_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L |
701 | #define SDB_SUVD_CGC_GATE__ENT_MASK 0x00008000L |
702 | #define SDB_SUVD_CGC_GATE__IME_MASK 0x00010000L |
703 | #define SDB_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L |
704 | #define SDB_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L |
705 | #define SDB_SUVD_CGC_GATE__SITE_MASK 0x00080000L |
706 | #define SDB_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L |
707 | #define SDB_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L |
708 | #define SDB_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L |
709 | #define SDB_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L |
710 | #define SDB_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L |
711 | #define SDB_SUVD_CGC_GATE__EFC_MASK 0x02000000L |
712 | #define SDB_SUVD_CGC_GATE__SAOE_MASK 0x04000000L |
713 | #define SDB_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L |
714 | #define SDB_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L |
715 | #define SDB_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L |
716 | #define SDB_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L |
717 | #define SDB_SUVD_CGC_GATE__SMPA_MASK 0x80000000L |
718 | //SIT0_NXT_SUVD_CGC_GATE |
719 | #define SIT0_NXT_SUVD_CGC_GATE__SRE__SHIFT 0x0 |
720 | #define SIT0_NXT_SUVD_CGC_GATE__SIT__SHIFT 0x1 |
721 | #define SIT0_NXT_SUVD_CGC_GATE__SMP__SHIFT 0x2 |
722 | #define SIT0_NXT_SUVD_CGC_GATE__SCM__SHIFT 0x3 |
723 | #define SIT0_NXT_SUVD_CGC_GATE__SDB__SHIFT 0x4 |
724 | #define SIT0_NXT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 |
725 | #define SIT0_NXT_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 |
726 | #define SIT0_NXT_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 |
727 | #define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 |
728 | #define SIT0_NXT_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 |
729 | #define SIT0_NXT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa |
730 | #define SIT0_NXT_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb |
731 | #define SIT0_NXT_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc |
732 | #define SIT0_NXT_SUVD_CGC_GATE__SCLR__SHIFT 0xd |
733 | #define SIT0_NXT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe |
734 | #define SIT0_NXT_SUVD_CGC_GATE__ENT__SHIFT 0xf |
735 | #define SIT0_NXT_SUVD_CGC_GATE__IME__SHIFT 0x10 |
736 | #define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 |
737 | #define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 |
738 | #define SIT0_NXT_SUVD_CGC_GATE__SITE__SHIFT 0x13 |
739 | #define SIT0_NXT_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 |
740 | #define SIT0_NXT_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 |
741 | #define SIT0_NXT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 |
742 | #define SIT0_NXT_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 |
743 | #define SIT0_NXT_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 |
744 | #define SIT0_NXT_SUVD_CGC_GATE__EFC__SHIFT 0x19 |
745 | #define SIT0_NXT_SUVD_CGC_GATE__SAOE__SHIFT 0x1a |
746 | #define SIT0_NXT_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b |
747 | #define SIT0_NXT_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c |
748 | #define SIT0_NXT_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d |
749 | #define SIT0_NXT_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e |
750 | #define SIT0_NXT_SUVD_CGC_GATE__SMPA__SHIFT 0x1f |
751 | #define SIT0_NXT_SUVD_CGC_GATE__SRE_MASK 0x00000001L |
752 | #define SIT0_NXT_SUVD_CGC_GATE__SIT_MASK 0x00000002L |
753 | #define SIT0_NXT_SUVD_CGC_GATE__SMP_MASK 0x00000004L |
754 | #define SIT0_NXT_SUVD_CGC_GATE__SCM_MASK 0x00000008L |
755 | #define SIT0_NXT_SUVD_CGC_GATE__SDB_MASK 0x00000010L |
756 | #define SIT0_NXT_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L |
757 | #define SIT0_NXT_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L |
758 | #define SIT0_NXT_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L |
759 | #define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L |
760 | #define SIT0_NXT_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L |
761 | #define SIT0_NXT_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L |
762 | #define SIT0_NXT_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L |
763 | #define SIT0_NXT_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L |
764 | #define SIT0_NXT_SUVD_CGC_GATE__SCLR_MASK 0x00002000L |
765 | #define SIT0_NXT_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L |
766 | #define SIT0_NXT_SUVD_CGC_GATE__ENT_MASK 0x00008000L |
767 | #define SIT0_NXT_SUVD_CGC_GATE__IME_MASK 0x00010000L |
768 | #define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L |
769 | #define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L |
770 | #define SIT0_NXT_SUVD_CGC_GATE__SITE_MASK 0x00080000L |
771 | #define SIT0_NXT_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L |
772 | #define SIT0_NXT_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L |
773 | #define SIT0_NXT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L |
774 | #define SIT0_NXT_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L |
775 | #define SIT0_NXT_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L |
776 | #define SIT0_NXT_SUVD_CGC_GATE__EFC_MASK 0x02000000L |
777 | #define SIT0_NXT_SUVD_CGC_GATE__SAOE_MASK 0x04000000L |
778 | #define SIT0_NXT_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L |
779 | #define SIT0_NXT_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L |
780 | #define SIT0_NXT_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L |
781 | #define SIT0_NXT_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L |
782 | #define SIT0_NXT_SUVD_CGC_GATE__SMPA_MASK 0x80000000L |
783 | //SIT1_NXT_SUVD_CGC_GATE |
784 | #define SIT1_NXT_SUVD_CGC_GATE__SRE__SHIFT 0x0 |
785 | #define SIT1_NXT_SUVD_CGC_GATE__SIT__SHIFT 0x1 |
786 | #define SIT1_NXT_SUVD_CGC_GATE__SMP__SHIFT 0x2 |
787 | #define SIT1_NXT_SUVD_CGC_GATE__SCM__SHIFT 0x3 |
788 | #define SIT1_NXT_SUVD_CGC_GATE__SDB__SHIFT 0x4 |
789 | #define SIT1_NXT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 |
790 | #define SIT1_NXT_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 |
791 | #define SIT1_NXT_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 |
792 | #define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 |
793 | #define SIT1_NXT_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 |
794 | #define SIT1_NXT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa |
795 | #define SIT1_NXT_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb |
796 | #define SIT1_NXT_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc |
797 | #define SIT1_NXT_SUVD_CGC_GATE__SCLR__SHIFT 0xd |
798 | #define SIT1_NXT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe |
799 | #define SIT1_NXT_SUVD_CGC_GATE__ENT__SHIFT 0xf |
800 | #define SIT1_NXT_SUVD_CGC_GATE__IME__SHIFT 0x10 |
801 | #define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 |
802 | #define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 |
803 | #define SIT1_NXT_SUVD_CGC_GATE__SITE__SHIFT 0x13 |
804 | #define SIT1_NXT_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 |
805 | #define SIT1_NXT_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 |
806 | #define SIT1_NXT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 |
807 | #define SIT1_NXT_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 |
808 | #define SIT1_NXT_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 |
809 | #define SIT1_NXT_SUVD_CGC_GATE__EFC__SHIFT 0x19 |
810 | #define SIT1_NXT_SUVD_CGC_GATE__SAOE__SHIFT 0x1a |
811 | #define SIT1_NXT_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b |
812 | #define SIT1_NXT_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c |
813 | #define SIT1_NXT_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d |
814 | #define SIT1_NXT_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e |
815 | #define SIT1_NXT_SUVD_CGC_GATE__SMPA__SHIFT 0x1f |
816 | #define SIT1_NXT_SUVD_CGC_GATE__SRE_MASK 0x00000001L |
817 | #define SIT1_NXT_SUVD_CGC_GATE__SIT_MASK 0x00000002L |
818 | #define SIT1_NXT_SUVD_CGC_GATE__SMP_MASK 0x00000004L |
819 | #define SIT1_NXT_SUVD_CGC_GATE__SCM_MASK 0x00000008L |
820 | #define SIT1_NXT_SUVD_CGC_GATE__SDB_MASK 0x00000010L |
821 | #define SIT1_NXT_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L |
822 | #define SIT1_NXT_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L |
823 | #define SIT1_NXT_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L |
824 | #define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L |
825 | #define SIT1_NXT_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L |
826 | #define SIT1_NXT_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L |
827 | #define SIT1_NXT_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L |
828 | #define SIT1_NXT_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L |
829 | #define SIT1_NXT_SUVD_CGC_GATE__SCLR_MASK 0x00002000L |
830 | #define SIT1_NXT_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L |
831 | #define SIT1_NXT_SUVD_CGC_GATE__ENT_MASK 0x00008000L |
832 | #define SIT1_NXT_SUVD_CGC_GATE__IME_MASK 0x00010000L |
833 | #define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L |
834 | #define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L |
835 | #define SIT1_NXT_SUVD_CGC_GATE__SITE_MASK 0x00080000L |
836 | #define SIT1_NXT_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L |
837 | #define SIT1_NXT_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L |
838 | #define SIT1_NXT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L |
839 | #define SIT1_NXT_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L |
840 | #define SIT1_NXT_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L |
841 | #define SIT1_NXT_SUVD_CGC_GATE__EFC_MASK 0x02000000L |
842 | #define SIT1_NXT_SUVD_CGC_GATE__SAOE_MASK 0x04000000L |
843 | #define SIT1_NXT_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L |
844 | #define SIT1_NXT_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L |
845 | #define SIT1_NXT_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L |
846 | #define SIT1_NXT_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L |
847 | #define SIT1_NXT_SUVD_CGC_GATE__SMPA_MASK 0x80000000L |
848 | //SIT2_NXT_SUVD_CGC_GATE |
849 | #define SIT2_NXT_SUVD_CGC_GATE__SRE__SHIFT 0x0 |
850 | #define SIT2_NXT_SUVD_CGC_GATE__SIT__SHIFT 0x1 |
851 | #define SIT2_NXT_SUVD_CGC_GATE__SMP__SHIFT 0x2 |
852 | #define SIT2_NXT_SUVD_CGC_GATE__SCM__SHIFT 0x3 |
853 | #define SIT2_NXT_SUVD_CGC_GATE__SDB__SHIFT 0x4 |
854 | #define SIT2_NXT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 |
855 | #define SIT2_NXT_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 |
856 | #define SIT2_NXT_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 |
857 | #define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 |
858 | #define SIT2_NXT_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 |
859 | #define SIT2_NXT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa |
860 | #define SIT2_NXT_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb |
861 | #define SIT2_NXT_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc |
862 | #define SIT2_NXT_SUVD_CGC_GATE__SCLR__SHIFT 0xd |
863 | #define SIT2_NXT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe |
864 | #define SIT2_NXT_SUVD_CGC_GATE__ENT__SHIFT 0xf |
865 | #define SIT2_NXT_SUVD_CGC_GATE__IME__SHIFT 0x10 |
866 | #define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 |
867 | #define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 |
868 | #define SIT2_NXT_SUVD_CGC_GATE__SITE__SHIFT 0x13 |
869 | #define SIT2_NXT_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 |
870 | #define SIT2_NXT_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 |
871 | #define SIT2_NXT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 |
872 | #define SIT2_NXT_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 |
873 | #define SIT2_NXT_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 |
874 | #define SIT2_NXT_SUVD_CGC_GATE__EFC__SHIFT 0x19 |
875 | #define SIT2_NXT_SUVD_CGC_GATE__SAOE__SHIFT 0x1a |
876 | #define SIT2_NXT_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b |
877 | #define SIT2_NXT_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c |
878 | #define SIT2_NXT_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d |
879 | #define SIT2_NXT_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e |
880 | #define SIT2_NXT_SUVD_CGC_GATE__SMPA__SHIFT 0x1f |
881 | #define SIT2_NXT_SUVD_CGC_GATE__SRE_MASK 0x00000001L |
882 | #define SIT2_NXT_SUVD_CGC_GATE__SIT_MASK 0x00000002L |
883 | #define SIT2_NXT_SUVD_CGC_GATE__SMP_MASK 0x00000004L |
884 | #define SIT2_NXT_SUVD_CGC_GATE__SCM_MASK 0x00000008L |
885 | #define SIT2_NXT_SUVD_CGC_GATE__SDB_MASK 0x00000010L |
886 | #define SIT2_NXT_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L |
887 | #define SIT2_NXT_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L |
888 | #define SIT2_NXT_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L |
889 | #define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L |
890 | #define SIT2_NXT_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L |
891 | #define SIT2_NXT_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L |
892 | #define SIT2_NXT_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L |
893 | #define SIT2_NXT_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L |
894 | #define SIT2_NXT_SUVD_CGC_GATE__SCLR_MASK 0x00002000L |
895 | #define SIT2_NXT_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L |
896 | #define SIT2_NXT_SUVD_CGC_GATE__ENT_MASK 0x00008000L |
897 | #define SIT2_NXT_SUVD_CGC_GATE__IME_MASK 0x00010000L |
898 | #define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L |
899 | #define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L |
900 | #define SIT2_NXT_SUVD_CGC_GATE__SITE_MASK 0x00080000L |
901 | #define SIT2_NXT_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L |
902 | #define SIT2_NXT_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L |
903 | #define SIT2_NXT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L |
904 | #define SIT2_NXT_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L |
905 | #define SIT2_NXT_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L |
906 | #define SIT2_NXT_SUVD_CGC_GATE__EFC_MASK 0x02000000L |
907 | #define SIT2_NXT_SUVD_CGC_GATE__SAOE_MASK 0x04000000L |
908 | #define SIT2_NXT_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L |
909 | #define SIT2_NXT_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L |
910 | #define SIT2_NXT_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L |
911 | #define SIT2_NXT_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L |
912 | #define SIT2_NXT_SUVD_CGC_GATE__SMPA_MASK 0x80000000L |
913 | //SIT_SUVD_CGC_GATE |
914 | #define SIT_SUVD_CGC_GATE__SRE__SHIFT 0x0 |
915 | #define SIT_SUVD_CGC_GATE__SIT__SHIFT 0x1 |
916 | #define SIT_SUVD_CGC_GATE__SMP__SHIFT 0x2 |
917 | #define SIT_SUVD_CGC_GATE__SCM__SHIFT 0x3 |
918 | #define SIT_SUVD_CGC_GATE__SDB__SHIFT 0x4 |
919 | #define SIT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 |
920 | #define SIT_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 |
921 | #define SIT_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 |
922 | #define SIT_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 |
923 | #define SIT_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 |
924 | #define SIT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa |
925 | #define SIT_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb |
926 | #define SIT_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc |
927 | #define SIT_SUVD_CGC_GATE__SCLR__SHIFT 0xd |
928 | #define SIT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe |
929 | #define SIT_SUVD_CGC_GATE__ENT__SHIFT 0xf |
930 | #define SIT_SUVD_CGC_GATE__IME__SHIFT 0x10 |
931 | #define SIT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 |
932 | #define SIT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 |
933 | #define SIT_SUVD_CGC_GATE__SITE__SHIFT 0x13 |
934 | #define SIT_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 |
935 | #define SIT_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 |
936 | #define SIT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 |
937 | #define SIT_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 |
938 | #define SIT_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 |
939 | #define SIT_SUVD_CGC_GATE__EFC__SHIFT 0x19 |
940 | #define SIT_SUVD_CGC_GATE__SAOE__SHIFT 0x1a |
941 | #define SIT_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b |
942 | #define SIT_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c |
943 | #define SIT_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d |
944 | #define SIT_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e |
945 | #define SIT_SUVD_CGC_GATE__SMPA__SHIFT 0x1f |
946 | #define SIT_SUVD_CGC_GATE__SRE_MASK 0x00000001L |
947 | #define SIT_SUVD_CGC_GATE__SIT_MASK 0x00000002L |
948 | #define SIT_SUVD_CGC_GATE__SMP_MASK 0x00000004L |
949 | #define SIT_SUVD_CGC_GATE__SCM_MASK 0x00000008L |
950 | #define SIT_SUVD_CGC_GATE__SDB_MASK 0x00000010L |
951 | #define SIT_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L |
952 | #define SIT_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L |
953 | #define SIT_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L |
954 | #define SIT_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L |
955 | #define SIT_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L |
956 | #define SIT_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L |
957 | #define SIT_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L |
958 | #define SIT_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L |
959 | #define SIT_SUVD_CGC_GATE__SCLR_MASK 0x00002000L |
960 | #define SIT_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L |
961 | #define SIT_SUVD_CGC_GATE__ENT_MASK 0x00008000L |
962 | #define SIT_SUVD_CGC_GATE__IME_MASK 0x00010000L |
963 | #define SIT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L |
964 | #define SIT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L |
965 | #define SIT_SUVD_CGC_GATE__SITE_MASK 0x00080000L |
966 | #define SIT_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L |
967 | #define SIT_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L |
968 | #define SIT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L |
969 | #define SIT_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L |
970 | #define SIT_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L |
971 | #define SIT_SUVD_CGC_GATE__EFC_MASK 0x02000000L |
972 | #define SIT_SUVD_CGC_GATE__SAOE_MASK 0x04000000L |
973 | #define SIT_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L |
974 | #define SIT_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L |
975 | #define SIT_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L |
976 | #define SIT_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L |
977 | #define SIT_SUVD_CGC_GATE__SMPA_MASK 0x80000000L |
978 | //SMPA_SUVD_CGC_GATE |
979 | #define SMPA_SUVD_CGC_GATE__SRE__SHIFT 0x0 |
980 | #define SMPA_SUVD_CGC_GATE__SIT__SHIFT 0x1 |
981 | #define SMPA_SUVD_CGC_GATE__SMP__SHIFT 0x2 |
982 | #define SMPA_SUVD_CGC_GATE__SCM__SHIFT 0x3 |
983 | #define SMPA_SUVD_CGC_GATE__SDB__SHIFT 0x4 |
984 | #define SMPA_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 |
985 | #define SMPA_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 |
986 | #define SMPA_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 |
987 | #define SMPA_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 |
988 | #define SMPA_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 |
989 | #define SMPA_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa |
990 | #define SMPA_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb |
991 | #define SMPA_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc |
992 | #define SMPA_SUVD_CGC_GATE__SCLR__SHIFT 0xd |
993 | #define SMPA_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe |
994 | #define SMPA_SUVD_CGC_GATE__ENT__SHIFT 0xf |
995 | #define SMPA_SUVD_CGC_GATE__IME__SHIFT 0x10 |
996 | #define SMPA_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 |
997 | #define SMPA_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 |
998 | #define SMPA_SUVD_CGC_GATE__SITE__SHIFT 0x13 |
999 | #define SMPA_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 |
1000 | #define SMPA_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 |
1001 | #define SMPA_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 |
1002 | #define SMPA_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 |
1003 | #define SMPA_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 |
1004 | #define SMPA_SUVD_CGC_GATE__EFC__SHIFT 0x19 |
1005 | #define SMPA_SUVD_CGC_GATE__SAOE__SHIFT 0x1a |
1006 | #define SMPA_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b |
1007 | #define SMPA_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c |
1008 | #define SMPA_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d |
1009 | #define SMPA_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e |
1010 | #define SMPA_SUVD_CGC_GATE__SMPA__SHIFT 0x1f |
1011 | #define SMPA_SUVD_CGC_GATE__SRE_MASK 0x00000001L |
1012 | #define SMPA_SUVD_CGC_GATE__SIT_MASK 0x00000002L |
1013 | #define SMPA_SUVD_CGC_GATE__SMP_MASK 0x00000004L |
1014 | #define SMPA_SUVD_CGC_GATE__SCM_MASK 0x00000008L |
1015 | #define SMPA_SUVD_CGC_GATE__SDB_MASK 0x00000010L |
1016 | #define SMPA_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L |
1017 | #define SMPA_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L |
1018 | #define SMPA_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L |
1019 | #define SMPA_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L |
1020 | #define SMPA_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L |
1021 | #define SMPA_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L |
1022 | #define SMPA_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L |
1023 | #define SMPA_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L |
1024 | #define SMPA_SUVD_CGC_GATE__SCLR_MASK 0x00002000L |
1025 | #define SMPA_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L |
1026 | #define SMPA_SUVD_CGC_GATE__ENT_MASK 0x00008000L |
1027 | #define SMPA_SUVD_CGC_GATE__IME_MASK 0x00010000L |
1028 | #define SMPA_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L |
1029 | #define SMPA_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L |
1030 | #define SMPA_SUVD_CGC_GATE__SITE_MASK 0x00080000L |
1031 | #define SMPA_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L |
1032 | #define SMPA_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L |
1033 | #define SMPA_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L |
1034 | #define SMPA_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L |
1035 | #define SMPA_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L |
1036 | #define SMPA_SUVD_CGC_GATE__EFC_MASK 0x02000000L |
1037 | #define SMPA_SUVD_CGC_GATE__SAOE_MASK 0x04000000L |
1038 | #define SMPA_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L |
1039 | #define SMPA_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L |
1040 | #define SMPA_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L |
1041 | #define SMPA_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L |
1042 | #define SMPA_SUVD_CGC_GATE__SMPA_MASK 0x80000000L |
1043 | //SMP_SUVD_CGC_GATE |
1044 | #define SMP_SUVD_CGC_GATE__SRE__SHIFT 0x0 |
1045 | #define SMP_SUVD_CGC_GATE__SIT__SHIFT 0x1 |
1046 | #define SMP_SUVD_CGC_GATE__SMP__SHIFT 0x2 |
1047 | #define SMP_SUVD_CGC_GATE__SCM__SHIFT 0x3 |
1048 | #define SMP_SUVD_CGC_GATE__SDB__SHIFT 0x4 |
1049 | #define SMP_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 |
1050 | #define SMP_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 |
1051 | #define SMP_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 |
1052 | #define SMP_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 |
1053 | #define SMP_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 |
1054 | #define SMP_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa |
1055 | #define SMP_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb |
1056 | #define SMP_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc |
1057 | #define SMP_SUVD_CGC_GATE__SCLR__SHIFT 0xd |
1058 | #define SMP_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe |
1059 | #define SMP_SUVD_CGC_GATE__ENT__SHIFT 0xf |
1060 | #define SMP_SUVD_CGC_GATE__IME__SHIFT 0x10 |
1061 | #define SMP_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 |
1062 | #define SMP_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 |
1063 | #define SMP_SUVD_CGC_GATE__SITE__SHIFT 0x13 |
1064 | #define SMP_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 |
1065 | #define SMP_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 |
1066 | #define SMP_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 |
1067 | #define SMP_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 |
1068 | #define SMP_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 |
1069 | #define SMP_SUVD_CGC_GATE__EFC__SHIFT 0x19 |
1070 | #define SMP_SUVD_CGC_GATE__SAOE__SHIFT 0x1a |
1071 | #define SMP_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b |
1072 | #define SMP_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c |
1073 | #define SMP_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d |
1074 | #define SMP_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e |
1075 | #define SMP_SUVD_CGC_GATE__SMPA__SHIFT 0x1f |
1076 | #define SMP_SUVD_CGC_GATE__SRE_MASK 0x00000001L |
1077 | #define SMP_SUVD_CGC_GATE__SIT_MASK 0x00000002L |
1078 | #define SMP_SUVD_CGC_GATE__SMP_MASK 0x00000004L |
1079 | #define SMP_SUVD_CGC_GATE__SCM_MASK 0x00000008L |
1080 | #define SMP_SUVD_CGC_GATE__SDB_MASK 0x00000010L |
1081 | #define SMP_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L |
1082 | #define SMP_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L |
1083 | #define SMP_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L |
1084 | #define SMP_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L |
1085 | #define SMP_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L |
1086 | #define SMP_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L |
1087 | #define SMP_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L |
1088 | #define SMP_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L |
1089 | #define SMP_SUVD_CGC_GATE__SCLR_MASK 0x00002000L |
1090 | #define SMP_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L |
1091 | #define SMP_SUVD_CGC_GATE__ENT_MASK 0x00008000L |
1092 | #define SMP_SUVD_CGC_GATE__IME_MASK 0x00010000L |
1093 | #define SMP_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L |
1094 | #define SMP_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L |
1095 | #define SMP_SUVD_CGC_GATE__SITE_MASK 0x00080000L |
1096 | #define SMP_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L |
1097 | #define SMP_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L |
1098 | #define SMP_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L |
1099 | #define SMP_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L |
1100 | #define SMP_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L |
1101 | #define SMP_SUVD_CGC_GATE__EFC_MASK 0x02000000L |
1102 | #define SMP_SUVD_CGC_GATE__SAOE_MASK 0x04000000L |
1103 | #define SMP_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L |
1104 | #define SMP_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L |
1105 | #define SMP_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L |
1106 | #define SMP_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L |
1107 | #define SMP_SUVD_CGC_GATE__SMPA_MASK 0x80000000L |
1108 | //SRE_SUVD_CGC_GATE |
1109 | #define SRE_SUVD_CGC_GATE__SRE__SHIFT 0x0 |
1110 | #define SRE_SUVD_CGC_GATE__SIT__SHIFT 0x1 |
1111 | #define SRE_SUVD_CGC_GATE__SMP__SHIFT 0x2 |
1112 | #define SRE_SUVD_CGC_GATE__SCM__SHIFT 0x3 |
1113 | #define SRE_SUVD_CGC_GATE__SDB__SHIFT 0x4 |
1114 | #define SRE_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 |
1115 | #define SRE_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 |
1116 | #define SRE_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 |
1117 | #define SRE_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 |
1118 | #define SRE_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 |
1119 | #define SRE_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa |
1120 | #define SRE_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb |
1121 | #define SRE_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc |
1122 | #define SRE_SUVD_CGC_GATE__SCLR__SHIFT 0xd |
1123 | #define SRE_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe |
1124 | #define SRE_SUVD_CGC_GATE__ENT__SHIFT 0xf |
1125 | #define SRE_SUVD_CGC_GATE__IME__SHIFT 0x10 |
1126 | #define SRE_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 |
1127 | #define SRE_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 |
1128 | #define SRE_SUVD_CGC_GATE__SITE__SHIFT 0x13 |
1129 | #define SRE_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 |
1130 | #define SRE_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 |
1131 | #define SRE_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 |
1132 | #define SRE_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 |
1133 | #define SRE_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 |
1134 | #define SRE_SUVD_CGC_GATE__EFC__SHIFT 0x19 |
1135 | #define SRE_SUVD_CGC_GATE__SAOE__SHIFT 0x1a |
1136 | #define SRE_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b |
1137 | #define SRE_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c |
1138 | #define SRE_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d |
1139 | #define SRE_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e |
1140 | #define SRE_SUVD_CGC_GATE__SMPA__SHIFT 0x1f |
1141 | #define SRE_SUVD_CGC_GATE__SRE_MASK 0x00000001L |
1142 | #define SRE_SUVD_CGC_GATE__SIT_MASK 0x00000002L |
1143 | #define SRE_SUVD_CGC_GATE__SMP_MASK 0x00000004L |
1144 | #define SRE_SUVD_CGC_GATE__SCM_MASK 0x00000008L |
1145 | #define SRE_SUVD_CGC_GATE__SDB_MASK 0x00000010L |
1146 | #define SRE_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L |
1147 | #define SRE_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L |
1148 | #define SRE_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L |
1149 | #define SRE_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L |
1150 | #define SRE_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L |
1151 | #define SRE_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L |
1152 | #define SRE_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L |
1153 | #define SRE_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L |
1154 | #define SRE_SUVD_CGC_GATE__SCLR_MASK 0x00002000L |
1155 | #define SRE_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L |
1156 | #define SRE_SUVD_CGC_GATE__ENT_MASK 0x00008000L |
1157 | #define SRE_SUVD_CGC_GATE__IME_MASK 0x00010000L |
1158 | #define SRE_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L |
1159 | #define SRE_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L |
1160 | #define SRE_SUVD_CGC_GATE__SITE_MASK 0x00080000L |
1161 | #define SRE_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L |
1162 | #define SRE_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L |
1163 | #define SRE_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L |
1164 | #define SRE_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L |
1165 | #define SRE_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L |
1166 | #define SRE_SUVD_CGC_GATE__EFC_MASK 0x02000000L |
1167 | #define SRE_SUVD_CGC_GATE__SAOE_MASK 0x04000000L |
1168 | #define SRE_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L |
1169 | #define SRE_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L |
1170 | #define SRE_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L |
1171 | #define SRE_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L |
1172 | #define SRE_SUVD_CGC_GATE__SMPA_MASK 0x80000000L |
1173 | //UVD_MPBE0_SUVD_CGC_GATE |
1174 | #define UVD_MPBE0_SUVD_CGC_GATE__SRE__SHIFT 0x0 |
1175 | #define UVD_MPBE0_SUVD_CGC_GATE__SIT__SHIFT 0x1 |
1176 | #define UVD_MPBE0_SUVD_CGC_GATE__SMP__SHIFT 0x2 |
1177 | #define UVD_MPBE0_SUVD_CGC_GATE__SCM__SHIFT 0x3 |
1178 | #define UVD_MPBE0_SUVD_CGC_GATE__SDB__SHIFT 0x4 |
1179 | #define UVD_MPBE0_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 |
1180 | #define UVD_MPBE0_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 |
1181 | #define UVD_MPBE0_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 |
1182 | #define UVD_MPBE0_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 |
1183 | #define UVD_MPBE0_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 |
1184 | #define UVD_MPBE0_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa |
1185 | #define UVD_MPBE0_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb |
1186 | #define UVD_MPBE0_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc |
1187 | #define UVD_MPBE0_SUVD_CGC_GATE__SCLR__SHIFT 0xd |
1188 | #define UVD_MPBE0_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe |
1189 | #define UVD_MPBE0_SUVD_CGC_GATE__ENT__SHIFT 0xf |
1190 | #define UVD_MPBE0_SUVD_CGC_GATE__IME__SHIFT 0x10 |
1191 | #define UVD_MPBE0_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 |
1192 | #define UVD_MPBE0_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 |
1193 | #define UVD_MPBE0_SUVD_CGC_GATE__SITE__SHIFT 0x13 |
1194 | #define UVD_MPBE0_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 |
1195 | #define UVD_MPBE0_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 |
1196 | #define UVD_MPBE0_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 |
1197 | #define UVD_MPBE0_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 |
1198 | #define UVD_MPBE0_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 |
1199 | #define UVD_MPBE0_SUVD_CGC_GATE__EFC__SHIFT 0x19 |
1200 | #define UVD_MPBE0_SUVD_CGC_GATE__SAOE__SHIFT 0x1a |
1201 | #define UVD_MPBE0_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b |
1202 | #define UVD_MPBE0_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c |
1203 | #define UVD_MPBE0_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d |
1204 | #define UVD_MPBE0_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e |
1205 | #define UVD_MPBE0_SUVD_CGC_GATE__SMPA__SHIFT 0x1f |
1206 | #define UVD_MPBE0_SUVD_CGC_GATE__SRE_MASK 0x00000001L |
1207 | #define UVD_MPBE0_SUVD_CGC_GATE__SIT_MASK 0x00000002L |
1208 | #define UVD_MPBE0_SUVD_CGC_GATE__SMP_MASK 0x00000004L |
1209 | #define UVD_MPBE0_SUVD_CGC_GATE__SCM_MASK 0x00000008L |
1210 | #define UVD_MPBE0_SUVD_CGC_GATE__SDB_MASK 0x00000010L |
1211 | #define UVD_MPBE0_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L |
1212 | #define UVD_MPBE0_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L |
1213 | #define UVD_MPBE0_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L |
1214 | #define UVD_MPBE0_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L |
1215 | #define UVD_MPBE0_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L |
1216 | #define UVD_MPBE0_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L |
1217 | #define UVD_MPBE0_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L |
1218 | #define UVD_MPBE0_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L |
1219 | #define UVD_MPBE0_SUVD_CGC_GATE__SCLR_MASK 0x00002000L |
1220 | #define UVD_MPBE0_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L |
1221 | #define UVD_MPBE0_SUVD_CGC_GATE__ENT_MASK 0x00008000L |
1222 | #define UVD_MPBE0_SUVD_CGC_GATE__IME_MASK 0x00010000L |
1223 | #define UVD_MPBE0_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L |
1224 | #define UVD_MPBE0_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L |
1225 | #define UVD_MPBE0_SUVD_CGC_GATE__SITE_MASK 0x00080000L |
1226 | #define UVD_MPBE0_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L |
1227 | #define UVD_MPBE0_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L |
1228 | #define UVD_MPBE0_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L |
1229 | #define UVD_MPBE0_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L |
1230 | #define UVD_MPBE0_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L |
1231 | #define UVD_MPBE0_SUVD_CGC_GATE__EFC_MASK 0x02000000L |
1232 | #define UVD_MPBE0_SUVD_CGC_GATE__SAOE_MASK 0x04000000L |
1233 | #define UVD_MPBE0_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L |
1234 | #define UVD_MPBE0_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L |
1235 | #define UVD_MPBE0_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L |
1236 | #define UVD_MPBE0_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L |
1237 | #define UVD_MPBE0_SUVD_CGC_GATE__SMPA_MASK 0x80000000L |
1238 | //UVD_MPBE1_SUVD_CGC_GATE |
1239 | #define UVD_MPBE1_SUVD_CGC_GATE__SRE__SHIFT 0x0 |
1240 | #define UVD_MPBE1_SUVD_CGC_GATE__SIT__SHIFT 0x1 |
1241 | #define UVD_MPBE1_SUVD_CGC_GATE__SMP__SHIFT 0x2 |
1242 | #define UVD_MPBE1_SUVD_CGC_GATE__SCM__SHIFT 0x3 |
1243 | #define UVD_MPBE1_SUVD_CGC_GATE__SDB__SHIFT 0x4 |
1244 | #define UVD_MPBE1_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 |
1245 | #define UVD_MPBE1_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 |
1246 | #define UVD_MPBE1_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 |
1247 | #define UVD_MPBE1_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 |
1248 | #define UVD_MPBE1_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 |
1249 | #define UVD_MPBE1_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa |
1250 | #define UVD_MPBE1_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb |
1251 | #define UVD_MPBE1_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc |
1252 | #define UVD_MPBE1_SUVD_CGC_GATE__SCLR__SHIFT 0xd |
1253 | #define UVD_MPBE1_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe |
1254 | #define UVD_MPBE1_SUVD_CGC_GATE__ENT__SHIFT 0xf |
1255 | #define UVD_MPBE1_SUVD_CGC_GATE__IME__SHIFT 0x10 |
1256 | #define UVD_MPBE1_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 |
1257 | #define UVD_MPBE1_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 |
1258 | #define UVD_MPBE1_SUVD_CGC_GATE__SITE__SHIFT 0x13 |
1259 | #define UVD_MPBE1_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 |
1260 | #define UVD_MPBE1_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 |
1261 | #define UVD_MPBE1_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 |
1262 | #define UVD_MPBE1_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 |
1263 | #define UVD_MPBE1_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 |
1264 | #define UVD_MPBE1_SUVD_CGC_GATE__EFC__SHIFT 0x19 |
1265 | #define UVD_MPBE1_SUVD_CGC_GATE__SAOE__SHIFT 0x1a |
1266 | #define UVD_MPBE1_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b |
1267 | #define UVD_MPBE1_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c |
1268 | #define UVD_MPBE1_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d |
1269 | #define UVD_MPBE1_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e |
1270 | #define UVD_MPBE1_SUVD_CGC_GATE__SMPA__SHIFT 0x1f |
1271 | #define UVD_MPBE1_SUVD_CGC_GATE__SRE_MASK 0x00000001L |
1272 | #define UVD_MPBE1_SUVD_CGC_GATE__SIT_MASK 0x00000002L |
1273 | #define UVD_MPBE1_SUVD_CGC_GATE__SMP_MASK 0x00000004L |
1274 | #define UVD_MPBE1_SUVD_CGC_GATE__SCM_MASK 0x00000008L |
1275 | #define UVD_MPBE1_SUVD_CGC_GATE__SDB_MASK 0x00000010L |
1276 | #define UVD_MPBE1_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L |
1277 | #define UVD_MPBE1_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L |
1278 | #define UVD_MPBE1_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L |
1279 | #define UVD_MPBE1_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L |
1280 | #define UVD_MPBE1_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L |
1281 | #define UVD_MPBE1_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L |
1282 | #define UVD_MPBE1_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L |
1283 | #define UVD_MPBE1_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L |
1284 | #define UVD_MPBE1_SUVD_CGC_GATE__SCLR_MASK 0x00002000L |
1285 | #define UVD_MPBE1_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L |
1286 | #define UVD_MPBE1_SUVD_CGC_GATE__ENT_MASK 0x00008000L |
1287 | #define UVD_MPBE1_SUVD_CGC_GATE__IME_MASK 0x00010000L |
1288 | #define UVD_MPBE1_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L |
1289 | #define UVD_MPBE1_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L |
1290 | #define UVD_MPBE1_SUVD_CGC_GATE__SITE_MASK 0x00080000L |
1291 | #define UVD_MPBE1_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L |
1292 | #define UVD_MPBE1_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L |
1293 | #define UVD_MPBE1_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L |
1294 | #define UVD_MPBE1_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L |
1295 | #define UVD_MPBE1_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L |
1296 | #define UVD_MPBE1_SUVD_CGC_GATE__EFC_MASK 0x02000000L |
1297 | #define UVD_MPBE1_SUVD_CGC_GATE__SAOE_MASK 0x04000000L |
1298 | #define UVD_MPBE1_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L |
1299 | #define UVD_MPBE1_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L |
1300 | #define UVD_MPBE1_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L |
1301 | #define UVD_MPBE1_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L |
1302 | #define UVD_MPBE1_SUVD_CGC_GATE__SMPA_MASK 0x80000000L |
1303 | //UVD_SUVD_CGC_GATE |
1304 | #define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 |
1305 | #define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 |
1306 | #define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 |
1307 | #define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 |
1308 | #define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 |
1309 | #define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 |
1310 | #define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 |
1311 | #define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 |
1312 | #define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 |
1313 | #define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 |
1314 | #define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa |
1315 | #define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb |
1316 | #define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc |
1317 | #define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd |
1318 | #define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe |
1319 | #define UVD_SUVD_CGC_GATE__ENT__SHIFT 0xf |
1320 | #define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10 |
1321 | #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 |
1322 | #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 |
1323 | #define UVD_SUVD_CGC_GATE__SITE__SHIFT 0x13 |
1324 | #define UVD_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 |
1325 | #define UVD_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 |
1326 | #define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 |
1327 | #define UVD_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 |
1328 | #define UVD_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 |
1329 | #define UVD_SUVD_CGC_GATE__EFC__SHIFT 0x19 |
1330 | #define UVD_SUVD_CGC_GATE__SAOE__SHIFT 0x1a |
1331 | #define UVD_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b |
1332 | #define UVD_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c |
1333 | #define UVD_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d |
1334 | #define UVD_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e |
1335 | #define UVD_SUVD_CGC_GATE__SMPA__SHIFT 0x1f |
1336 | #define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L |
1337 | #define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L |
1338 | #define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L |
1339 | #define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L |
1340 | #define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L |
1341 | #define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L |
1342 | #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L |
1343 | #define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L |
1344 | #define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L |
1345 | #define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L |
1346 | #define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L |
1347 | #define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L |
1348 | #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L |
1349 | #define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L |
1350 | #define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L |
1351 | #define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L |
1352 | #define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L |
1353 | #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L |
1354 | #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L |
1355 | #define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L |
1356 | #define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L |
1357 | #define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L |
1358 | #define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L |
1359 | #define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L |
1360 | #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L |
1361 | #define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L |
1362 | #define UVD_SUVD_CGC_GATE__SAOE_MASK 0x04000000L |
1363 | #define UVD_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L |
1364 | #define UVD_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L |
1365 | #define UVD_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L |
1366 | #define UVD_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L |
1367 | #define UVD_SUVD_CGC_GATE__SMPA_MASK 0x80000000L |
1368 | //AVM_SUVD_CGC_GATE2 |
1369 | #define AVM_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 |
1370 | #define AVM_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 |
1371 | #define AVM_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 |
1372 | #define AVM_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 |
1373 | #define AVM_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 |
1374 | #define AVM_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 |
1375 | #define AVM_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 |
1376 | #define AVM_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 |
1377 | #define AVM_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 |
1378 | #define AVM_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 |
1379 | #define AVM_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa |
1380 | #define AVM_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb |
1381 | #define AVM_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L |
1382 | #define AVM_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L |
1383 | #define AVM_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L |
1384 | #define AVM_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L |
1385 | #define AVM_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L |
1386 | #define AVM_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L |
1387 | #define AVM_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L |
1388 | #define AVM_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L |
1389 | #define AVM_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L |
1390 | #define AVM_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L |
1391 | #define AVM_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L |
1392 | #define AVM_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L |
1393 | //CDEFE_SUVD_CGC_GATE2 |
1394 | #define CDEFE_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 |
1395 | #define CDEFE_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 |
1396 | #define CDEFE_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 |
1397 | #define CDEFE_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 |
1398 | #define CDEFE_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 |
1399 | #define CDEFE_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 |
1400 | #define CDEFE_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 |
1401 | #define CDEFE_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 |
1402 | #define CDEFE_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 |
1403 | #define CDEFE_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 |
1404 | #define CDEFE_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa |
1405 | #define CDEFE_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb |
1406 | #define CDEFE_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L |
1407 | #define CDEFE_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L |
1408 | #define CDEFE_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L |
1409 | #define CDEFE_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L |
1410 | #define CDEFE_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L |
1411 | #define CDEFE_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L |
1412 | #define CDEFE_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L |
1413 | #define CDEFE_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L |
1414 | #define CDEFE_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L |
1415 | #define CDEFE_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L |
1416 | #define CDEFE_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L |
1417 | #define CDEFE_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L |
1418 | //DBR_SUVD_CGC_GATE2 |
1419 | #define DBR_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 |
1420 | #define DBR_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 |
1421 | #define DBR_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 |
1422 | #define DBR_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 |
1423 | #define DBR_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 |
1424 | #define DBR_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 |
1425 | #define DBR_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 |
1426 | #define DBR_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 |
1427 | #define DBR_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 |
1428 | #define DBR_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 |
1429 | #define DBR_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa |
1430 | #define DBR_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb |
1431 | #define DBR_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L |
1432 | #define DBR_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L |
1433 | #define DBR_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L |
1434 | #define DBR_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L |
1435 | #define DBR_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L |
1436 | #define DBR_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L |
1437 | #define DBR_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L |
1438 | #define DBR_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L |
1439 | #define DBR_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L |
1440 | #define DBR_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L |
1441 | #define DBR_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L |
1442 | #define DBR_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L |
1443 | //ENT_SUVD_CGC_GATE2 |
1444 | #define ENT_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 |
1445 | #define ENT_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 |
1446 | #define ENT_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 |
1447 | #define ENT_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 |
1448 | #define ENT_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 |
1449 | #define ENT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 |
1450 | #define ENT_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 |
1451 | #define ENT_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 |
1452 | #define ENT_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 |
1453 | #define ENT_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 |
1454 | #define ENT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa |
1455 | #define ENT_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb |
1456 | #define ENT_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L |
1457 | #define ENT_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L |
1458 | #define ENT_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L |
1459 | #define ENT_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L |
1460 | #define ENT_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L |
1461 | #define ENT_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L |
1462 | #define ENT_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L |
1463 | #define ENT_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L |
1464 | #define ENT_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L |
1465 | #define ENT_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L |
1466 | #define ENT_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L |
1467 | #define ENT_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L |
1468 | //IME_SUVD_CGC_GATE2 |
1469 | #define IME_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 |
1470 | #define IME_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 |
1471 | #define IME_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 |
1472 | #define IME_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 |
1473 | #define IME_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 |
1474 | #define IME_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 |
1475 | #define IME_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 |
1476 | #define IME_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 |
1477 | #define IME_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 |
1478 | #define IME_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 |
1479 | #define IME_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa |
1480 | #define IME_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb |
1481 | #define IME_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L |
1482 | #define IME_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L |
1483 | #define IME_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L |
1484 | #define IME_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L |
1485 | #define IME_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L |
1486 | #define IME_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L |
1487 | #define IME_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L |
1488 | #define IME_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L |
1489 | #define IME_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L |
1490 | #define IME_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L |
1491 | #define IME_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L |
1492 | #define IME_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L |
1493 | //MPC1_SUVD_CGC_GATE2 |
1494 | #define MPC1_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 |
1495 | #define MPC1_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 |
1496 | #define MPC1_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 |
1497 | #define MPC1_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 |
1498 | #define MPC1_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 |
1499 | #define MPC1_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 |
1500 | #define MPC1_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 |
1501 | #define MPC1_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 |
1502 | #define MPC1_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 |
1503 | #define MPC1_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 |
1504 | #define MPC1_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa |
1505 | #define MPC1_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb |
1506 | #define MPC1_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L |
1507 | #define MPC1_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L |
1508 | #define MPC1_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L |
1509 | #define MPC1_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L |
1510 | #define MPC1_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L |
1511 | #define MPC1_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L |
1512 | #define MPC1_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L |
1513 | #define MPC1_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L |
1514 | #define MPC1_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L |
1515 | #define MPC1_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L |
1516 | #define MPC1_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L |
1517 | #define MPC1_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L |
1518 | //SAOE_SUVD_CGC_GATE2 |
1519 | #define SAOE_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 |
1520 | #define SAOE_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 |
1521 | #define SAOE_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 |
1522 | #define SAOE_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 |
1523 | #define SAOE_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 |
1524 | #define SAOE_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 |
1525 | #define SAOE_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 |
1526 | #define SAOE_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 |
1527 | #define SAOE_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 |
1528 | #define SAOE_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 |
1529 | #define SAOE_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa |
1530 | #define SAOE_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb |
1531 | #define SAOE_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L |
1532 | #define SAOE_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L |
1533 | #define SAOE_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L |
1534 | #define SAOE_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L |
1535 | #define SAOE_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L |
1536 | #define SAOE_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L |
1537 | #define SAOE_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L |
1538 | #define SAOE_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L |
1539 | #define SAOE_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L |
1540 | #define SAOE_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L |
1541 | #define SAOE_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L |
1542 | #define SAOE_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L |
1543 | //SDB_SUVD_CGC_GATE2 |
1544 | #define SDB_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 |
1545 | #define SDB_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 |
1546 | #define SDB_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 |
1547 | #define SDB_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 |
1548 | #define SDB_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 |
1549 | #define SDB_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 |
1550 | #define SDB_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 |
1551 | #define SDB_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 |
1552 | #define SDB_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 |
1553 | #define SDB_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 |
1554 | #define SDB_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa |
1555 | #define SDB_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb |
1556 | #define SDB_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L |
1557 | #define SDB_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L |
1558 | #define SDB_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L |
1559 | #define SDB_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L |
1560 | #define SDB_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L |
1561 | #define SDB_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L |
1562 | #define SDB_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L |
1563 | #define SDB_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L |
1564 | #define SDB_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L |
1565 | #define SDB_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L |
1566 | #define SDB_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L |
1567 | #define SDB_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L |
1568 | //SIT0_NXT_SUVD_CGC_GATE2 |
1569 | #define SIT0_NXT_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 |
1570 | #define SIT0_NXT_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 |
1571 | #define SIT0_NXT_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 |
1572 | #define SIT0_NXT_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 |
1573 | #define SIT0_NXT_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 |
1574 | #define SIT0_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 |
1575 | #define SIT0_NXT_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 |
1576 | #define SIT0_NXT_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 |
1577 | #define SIT0_NXT_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 |
1578 | #define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 |
1579 | #define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa |
1580 | #define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb |
1581 | #define SIT0_NXT_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L |
1582 | #define SIT0_NXT_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L |
1583 | #define SIT0_NXT_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L |
1584 | #define SIT0_NXT_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L |
1585 | #define SIT0_NXT_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L |
1586 | #define SIT0_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L |
1587 | #define SIT0_NXT_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L |
1588 | #define SIT0_NXT_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L |
1589 | #define SIT0_NXT_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L |
1590 | #define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L |
1591 | #define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L |
1592 | #define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L |
1593 | //SIT1_NXT_SUVD_CGC_GATE2 |
1594 | #define SIT1_NXT_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 |
1595 | #define SIT1_NXT_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 |
1596 | #define SIT1_NXT_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 |
1597 | #define SIT1_NXT_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 |
1598 | #define SIT1_NXT_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 |
1599 | #define SIT1_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 |
1600 | #define SIT1_NXT_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 |
1601 | #define SIT1_NXT_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 |
1602 | #define SIT1_NXT_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 |
1603 | #define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 |
1604 | #define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa |
1605 | #define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb |
1606 | #define SIT1_NXT_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L |
1607 | #define SIT1_NXT_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L |
1608 | #define SIT1_NXT_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L |
1609 | #define SIT1_NXT_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L |
1610 | #define SIT1_NXT_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L |
1611 | #define SIT1_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L |
1612 | #define SIT1_NXT_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L |
1613 | #define SIT1_NXT_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L |
1614 | #define SIT1_NXT_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L |
1615 | #define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L |
1616 | #define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L |
1617 | #define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L |
1618 | //SIT2_NXT_SUVD_CGC_GATE2 |
1619 | #define SIT2_NXT_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 |
1620 | #define SIT2_NXT_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 |
1621 | #define SIT2_NXT_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 |
1622 | #define SIT2_NXT_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 |
1623 | #define SIT2_NXT_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 |
1624 | #define SIT2_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 |
1625 | #define SIT2_NXT_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 |
1626 | #define SIT2_NXT_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 |
1627 | #define SIT2_NXT_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 |
1628 | #define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 |
1629 | #define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa |
1630 | #define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb |
1631 | #define SIT2_NXT_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L |
1632 | #define SIT2_NXT_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L |
1633 | #define SIT2_NXT_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L |
1634 | #define SIT2_NXT_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L |
1635 | #define SIT2_NXT_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L |
1636 | #define SIT2_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L |
1637 | #define SIT2_NXT_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L |
1638 | #define SIT2_NXT_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L |
1639 | #define SIT2_NXT_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L |
1640 | #define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L |
1641 | #define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L |
1642 | #define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L |
1643 | //SIT_SUVD_CGC_GATE2 |
1644 | #define SIT_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 |
1645 | #define SIT_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 |
1646 | #define SIT_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 |
1647 | #define SIT_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 |
1648 | #define SIT_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 |
1649 | #define SIT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 |
1650 | #define SIT_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 |
1651 | #define SIT_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 |
1652 | #define SIT_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 |
1653 | #define SIT_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 |
1654 | #define SIT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa |
1655 | #define SIT_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb |
1656 | #define SIT_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L |
1657 | #define SIT_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L |
1658 | #define SIT_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L |
1659 | #define SIT_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L |
1660 | #define SIT_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L |
1661 | #define SIT_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L |
1662 | #define SIT_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L |
1663 | #define SIT_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L |
1664 | #define SIT_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L |
1665 | #define SIT_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L |
1666 | #define SIT_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L |
1667 | #define SIT_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L |
1668 | //SMPA_SUVD_CGC_GATE2 |
1669 | #define SMPA_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 |
1670 | #define SMPA_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 |
1671 | #define SMPA_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 |
1672 | #define SMPA_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 |
1673 | #define SMPA_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 |
1674 | #define SMPA_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 |
1675 | #define SMPA_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 |
1676 | #define SMPA_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 |
1677 | #define SMPA_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 |
1678 | #define SMPA_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 |
1679 | #define SMPA_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa |
1680 | #define SMPA_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb |
1681 | #define SMPA_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L |
1682 | #define SMPA_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L |
1683 | #define SMPA_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L |
1684 | #define SMPA_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L |
1685 | #define SMPA_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L |
1686 | #define SMPA_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L |
1687 | #define SMPA_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L |
1688 | #define SMPA_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L |
1689 | #define SMPA_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L |
1690 | #define SMPA_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L |
1691 | #define SMPA_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L |
1692 | #define SMPA_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L |
1693 | //SMP_SUVD_CGC_GATE2 |
1694 | #define SMP_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 |
1695 | #define SMP_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 |
1696 | #define SMP_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 |
1697 | #define SMP_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 |
1698 | #define SMP_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 |
1699 | #define SMP_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 |
1700 | #define SMP_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 |
1701 | #define SMP_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 |
1702 | #define SMP_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 |
1703 | #define SMP_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 |
1704 | #define SMP_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa |
1705 | #define SMP_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb |
1706 | #define SMP_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L |
1707 | #define SMP_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L |
1708 | #define SMP_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L |
1709 | #define SMP_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L |
1710 | #define SMP_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L |
1711 | #define SMP_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L |
1712 | #define SMP_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L |
1713 | #define SMP_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L |
1714 | #define SMP_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L |
1715 | #define SMP_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L |
1716 | #define SMP_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L |
1717 | #define SMP_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L |
1718 | //SRE_SUVD_CGC_GATE2 |
1719 | #define SRE_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 |
1720 | #define SRE_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 |
1721 | #define SRE_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 |
1722 | #define SRE_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 |
1723 | #define SRE_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 |
1724 | #define SRE_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 |
1725 | #define SRE_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 |
1726 | #define SRE_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 |
1727 | #define SRE_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 |
1728 | #define SRE_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 |
1729 | #define SRE_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa |
1730 | #define SRE_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb |
1731 | #define SRE_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L |
1732 | #define SRE_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L |
1733 | #define SRE_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L |
1734 | #define SRE_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L |
1735 | #define SRE_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L |
1736 | #define SRE_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L |
1737 | #define SRE_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L |
1738 | #define SRE_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L |
1739 | #define SRE_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L |
1740 | #define SRE_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L |
1741 | #define SRE_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L |
1742 | #define SRE_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L |
1743 | //UVD_MPBE0_SUVD_CGC_GATE2 |
1744 | #define UVD_MPBE0_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 |
1745 | #define UVD_MPBE0_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 |
1746 | #define UVD_MPBE0_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 |
1747 | #define UVD_MPBE0_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 |
1748 | #define UVD_MPBE0_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 |
1749 | #define UVD_MPBE0_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 |
1750 | #define UVD_MPBE0_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 |
1751 | #define UVD_MPBE0_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L |
1752 | #define UVD_MPBE0_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L |
1753 | #define UVD_MPBE0_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L |
1754 | #define UVD_MPBE0_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L |
1755 | #define UVD_MPBE0_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L |
1756 | #define UVD_MPBE0_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L |
1757 | #define UVD_MPBE0_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L |
1758 | //UVD_MPBE1_SUVD_CGC_GATE2 |
1759 | #define UVD_MPBE1_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 |
1760 | #define UVD_MPBE1_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 |
1761 | #define UVD_MPBE1_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 |
1762 | #define UVD_MPBE1_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 |
1763 | #define UVD_MPBE1_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 |
1764 | #define UVD_MPBE1_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 |
1765 | #define UVD_MPBE1_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 |
1766 | #define UVD_MPBE1_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L |
1767 | #define UVD_MPBE1_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L |
1768 | #define UVD_MPBE1_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L |
1769 | #define UVD_MPBE1_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L |
1770 | #define UVD_MPBE1_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L |
1771 | #define UVD_MPBE1_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L |
1772 | #define UVD_MPBE1_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L |
1773 | //UVD_SUVD_CGC_GATE2 |
1774 | #define UVD_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 |
1775 | #define UVD_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 |
1776 | #define UVD_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 |
1777 | #define UVD_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 |
1778 | #define UVD_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 |
1779 | #define UVD_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 |
1780 | #define UVD_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 |
1781 | #define UVD_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 |
1782 | #define UVD_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 |
1783 | #define UVD_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 |
1784 | #define UVD_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa |
1785 | #define UVD_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb |
1786 | #define UVD_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L |
1787 | #define UVD_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L |
1788 | #define UVD_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L |
1789 | #define UVD_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L |
1790 | #define UVD_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L |
1791 | #define UVD_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L |
1792 | #define UVD_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L |
1793 | #define UVD_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L |
1794 | #define UVD_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L |
1795 | #define UVD_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L |
1796 | #define UVD_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L |
1797 | #define UVD_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L |
1798 | //AVM_SUVD_CGC_CTRL |
1799 | #define AVM_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 |
1800 | #define AVM_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 |
1801 | #define AVM_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 |
1802 | #define AVM_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 |
1803 | #define AVM_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 |
1804 | #define AVM_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 |
1805 | #define AVM_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 |
1806 | #define AVM_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 |
1807 | #define AVM_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 |
1808 | #define AVM_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 |
1809 | #define AVM_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa |
1810 | #define AVM_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb |
1811 | #define AVM_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc |
1812 | #define AVM_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd |
1813 | #define AVM_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe |
1814 | #define AVM_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf |
1815 | #define AVM_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 |
1816 | #define AVM_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 |
1817 | #define AVM_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 |
1818 | #define AVM_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 |
1819 | #define AVM_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 |
1820 | #define AVM_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 |
1821 | #define AVM_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 |
1822 | #define AVM_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c |
1823 | #define AVM_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d |
1824 | #define AVM_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e |
1825 | #define AVM_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L |
1826 | #define AVM_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L |
1827 | #define AVM_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L |
1828 | #define AVM_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L |
1829 | #define AVM_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L |
1830 | #define AVM_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L |
1831 | #define AVM_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L |
1832 | #define AVM_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L |
1833 | #define AVM_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L |
1834 | #define AVM_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L |
1835 | #define AVM_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L |
1836 | #define AVM_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L |
1837 | #define AVM_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L |
1838 | #define AVM_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L |
1839 | #define AVM_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L |
1840 | #define AVM_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L |
1841 | #define AVM_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L |
1842 | #define AVM_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L |
1843 | #define AVM_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L |
1844 | #define AVM_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L |
1845 | #define AVM_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L |
1846 | #define AVM_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L |
1847 | #define AVM_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L |
1848 | #define AVM_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L |
1849 | #define AVM_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L |
1850 | #define AVM_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L |
1851 | //CDEFE_SUVD_CGC_CTRL |
1852 | #define CDEFE_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 |
1853 | #define CDEFE_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 |
1854 | #define CDEFE_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 |
1855 | #define CDEFE_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 |
1856 | #define CDEFE_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 |
1857 | #define CDEFE_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 |
1858 | #define CDEFE_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 |
1859 | #define CDEFE_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 |
1860 | #define CDEFE_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 |
1861 | #define CDEFE_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 |
1862 | #define CDEFE_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa |
1863 | #define CDEFE_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb |
1864 | #define CDEFE_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc |
1865 | #define CDEFE_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd |
1866 | #define CDEFE_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe |
1867 | #define CDEFE_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf |
1868 | #define CDEFE_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 |
1869 | #define CDEFE_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 |
1870 | #define CDEFE_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 |
1871 | #define CDEFE_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 |
1872 | #define CDEFE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 |
1873 | #define CDEFE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 |
1874 | #define CDEFE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 |
1875 | #define CDEFE_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c |
1876 | #define CDEFE_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d |
1877 | #define CDEFE_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e |
1878 | #define CDEFE_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L |
1879 | #define CDEFE_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L |
1880 | #define CDEFE_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L |
1881 | #define CDEFE_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L |
1882 | #define CDEFE_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L |
1883 | #define CDEFE_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L |
1884 | #define CDEFE_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L |
1885 | #define CDEFE_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L |
1886 | #define CDEFE_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L |
1887 | #define CDEFE_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L |
1888 | #define CDEFE_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L |
1889 | #define CDEFE_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L |
1890 | #define CDEFE_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L |
1891 | #define CDEFE_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L |
1892 | #define CDEFE_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L |
1893 | #define CDEFE_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L |
1894 | #define CDEFE_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L |
1895 | #define CDEFE_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L |
1896 | #define CDEFE_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L |
1897 | #define CDEFE_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L |
1898 | #define CDEFE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L |
1899 | #define CDEFE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L |
1900 | #define CDEFE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L |
1901 | #define CDEFE_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L |
1902 | #define CDEFE_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L |
1903 | #define CDEFE_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L |
1904 | //DBR_SUVD_CGC_CTRL |
1905 | #define DBR_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 |
1906 | #define DBR_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 |
1907 | #define DBR_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 |
1908 | #define DBR_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 |
1909 | #define DBR_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 |
1910 | #define DBR_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 |
1911 | #define DBR_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 |
1912 | #define DBR_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 |
1913 | #define DBR_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 |
1914 | #define DBR_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 |
1915 | #define DBR_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa |
1916 | #define DBR_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb |
1917 | #define DBR_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc |
1918 | #define DBR_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd |
1919 | #define DBR_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe |
1920 | #define DBR_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf |
1921 | #define DBR_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 |
1922 | #define DBR_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 |
1923 | #define DBR_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 |
1924 | #define DBR_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 |
1925 | #define DBR_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 |
1926 | #define DBR_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 |
1927 | #define DBR_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 |
1928 | #define DBR_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c |
1929 | #define DBR_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d |
1930 | #define DBR_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e |
1931 | #define DBR_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L |
1932 | #define DBR_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L |
1933 | #define DBR_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L |
1934 | #define DBR_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L |
1935 | #define DBR_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L |
1936 | #define DBR_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L |
1937 | #define DBR_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L |
1938 | #define DBR_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L |
1939 | #define DBR_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L |
1940 | #define DBR_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L |
1941 | #define DBR_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L |
1942 | #define DBR_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L |
1943 | #define DBR_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L |
1944 | #define DBR_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L |
1945 | #define DBR_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L |
1946 | #define DBR_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L |
1947 | #define DBR_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L |
1948 | #define DBR_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L |
1949 | #define DBR_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L |
1950 | #define DBR_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L |
1951 | #define DBR_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L |
1952 | #define DBR_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L |
1953 | #define DBR_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L |
1954 | #define DBR_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L |
1955 | #define DBR_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L |
1956 | #define DBR_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L |
1957 | //EFC_SUVD_CGC_CTRL |
1958 | #define EFC_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 |
1959 | #define EFC_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 |
1960 | #define EFC_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 |
1961 | #define EFC_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 |
1962 | #define EFC_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 |
1963 | #define EFC_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 |
1964 | #define EFC_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 |
1965 | #define EFC_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 |
1966 | #define EFC_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 |
1967 | #define EFC_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 |
1968 | #define EFC_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa |
1969 | #define EFC_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb |
1970 | #define EFC_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc |
1971 | #define EFC_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd |
1972 | #define EFC_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe |
1973 | #define EFC_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf |
1974 | #define EFC_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 |
1975 | #define EFC_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 |
1976 | #define EFC_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 |
1977 | #define EFC_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 |
1978 | #define EFC_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 |
1979 | #define EFC_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 |
1980 | #define EFC_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 |
1981 | #define EFC_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c |
1982 | #define EFC_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d |
1983 | #define EFC_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e |
1984 | #define EFC_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L |
1985 | #define EFC_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L |
1986 | #define EFC_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L |
1987 | #define EFC_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L |
1988 | #define EFC_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L |
1989 | #define EFC_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L |
1990 | #define EFC_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L |
1991 | #define EFC_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L |
1992 | #define EFC_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L |
1993 | #define EFC_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L |
1994 | #define EFC_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L |
1995 | #define EFC_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L |
1996 | #define EFC_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L |
1997 | #define EFC_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L |
1998 | #define EFC_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L |
1999 | #define EFC_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L |
2000 | #define EFC_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L |
2001 | #define EFC_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L |
2002 | #define EFC_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L |
2003 | #define EFC_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L |
2004 | #define EFC_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L |
2005 | #define EFC_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L |
2006 | #define EFC_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L |
2007 | #define EFC_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L |
2008 | #define EFC_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L |
2009 | #define EFC_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L |
2010 | //ENT_SUVD_CGC_CTRL |
2011 | #define ENT_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 |
2012 | #define ENT_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 |
2013 | #define ENT_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 |
2014 | #define ENT_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 |
2015 | #define ENT_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 |
2016 | #define ENT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 |
2017 | #define ENT_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 |
2018 | #define ENT_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 |
2019 | #define ENT_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 |
2020 | #define ENT_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 |
2021 | #define ENT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa |
2022 | #define ENT_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb |
2023 | #define ENT_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc |
2024 | #define ENT_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd |
2025 | #define ENT_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe |
2026 | #define ENT_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf |
2027 | #define ENT_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 |
2028 | #define ENT_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 |
2029 | #define ENT_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 |
2030 | #define ENT_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 |
2031 | #define ENT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 |
2032 | #define ENT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 |
2033 | #define ENT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 |
2034 | #define ENT_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c |
2035 | #define ENT_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d |
2036 | #define ENT_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e |
2037 | #define ENT_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L |
2038 | #define ENT_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L |
2039 | #define ENT_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L |
2040 | #define ENT_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L |
2041 | #define ENT_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L |
2042 | #define ENT_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L |
2043 | #define ENT_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L |
2044 | #define ENT_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L |
2045 | #define ENT_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L |
2046 | #define ENT_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L |
2047 | #define ENT_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L |
2048 | #define ENT_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L |
2049 | #define ENT_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L |
2050 | #define ENT_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L |
2051 | #define ENT_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L |
2052 | #define ENT_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L |
2053 | #define ENT_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L |
2054 | #define ENT_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L |
2055 | #define ENT_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L |
2056 | #define ENT_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L |
2057 | #define ENT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L |
2058 | #define ENT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L |
2059 | #define ENT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L |
2060 | #define ENT_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L |
2061 | #define ENT_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L |
2062 | #define ENT_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L |
2063 | //IME_SUVD_CGC_CTRL |
2064 | #define IME_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 |
2065 | #define IME_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 |
2066 | #define IME_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 |
2067 | #define IME_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 |
2068 | #define IME_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 |
2069 | #define IME_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 |
2070 | #define IME_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 |
2071 | #define IME_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 |
2072 | #define IME_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 |
2073 | #define IME_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 |
2074 | #define IME_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa |
2075 | #define IME_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb |
2076 | #define IME_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc |
2077 | #define IME_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd |
2078 | #define IME_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe |
2079 | #define IME_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf |
2080 | #define IME_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 |
2081 | #define IME_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 |
2082 | #define IME_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 |
2083 | #define IME_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 |
2084 | #define IME_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 |
2085 | #define IME_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 |
2086 | #define IME_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 |
2087 | #define IME_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c |
2088 | #define IME_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d |
2089 | #define IME_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e |
2090 | #define IME_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L |
2091 | #define IME_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L |
2092 | #define IME_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L |
2093 | #define IME_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L |
2094 | #define IME_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L |
2095 | #define IME_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L |
2096 | #define IME_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L |
2097 | #define IME_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L |
2098 | #define IME_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L |
2099 | #define IME_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L |
2100 | #define IME_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L |
2101 | #define IME_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L |
2102 | #define IME_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L |
2103 | #define IME_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L |
2104 | #define IME_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L |
2105 | #define IME_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L |
2106 | #define IME_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L |
2107 | #define IME_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L |
2108 | #define IME_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L |
2109 | #define IME_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L |
2110 | #define IME_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L |
2111 | #define IME_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L |
2112 | #define IME_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L |
2113 | #define IME_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L |
2114 | #define IME_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L |
2115 | #define IME_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L |
2116 | //MPC1_SUVD_CGC_CTRL |
2117 | #define MPC1_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 |
2118 | #define MPC1_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 |
2119 | #define MPC1_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 |
2120 | #define MPC1_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 |
2121 | #define MPC1_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 |
2122 | #define MPC1_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 |
2123 | #define MPC1_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 |
2124 | #define MPC1_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 |
2125 | #define MPC1_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 |
2126 | #define MPC1_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 |
2127 | #define MPC1_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa |
2128 | #define MPC1_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb |
2129 | #define MPC1_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc |
2130 | #define MPC1_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd |
2131 | #define MPC1_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe |
2132 | #define MPC1_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf |
2133 | #define MPC1_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 |
2134 | #define MPC1_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 |
2135 | #define MPC1_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 |
2136 | #define MPC1_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 |
2137 | #define MPC1_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 |
2138 | #define MPC1_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 |
2139 | #define MPC1_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 |
2140 | #define MPC1_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c |
2141 | #define MPC1_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d |
2142 | #define MPC1_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e |
2143 | #define MPC1_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L |
2144 | #define MPC1_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L |
2145 | #define MPC1_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L |
2146 | #define MPC1_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L |
2147 | #define MPC1_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L |
2148 | #define MPC1_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L |
2149 | #define MPC1_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L |
2150 | #define MPC1_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L |
2151 | #define MPC1_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L |
2152 | #define MPC1_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L |
2153 | #define MPC1_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L |
2154 | #define MPC1_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L |
2155 | #define MPC1_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L |
2156 | #define MPC1_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L |
2157 | #define MPC1_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L |
2158 | #define MPC1_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L |
2159 | #define MPC1_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L |
2160 | #define MPC1_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L |
2161 | #define MPC1_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L |
2162 | #define MPC1_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L |
2163 | #define MPC1_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L |
2164 | #define MPC1_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L |
2165 | #define MPC1_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L |
2166 | #define MPC1_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L |
2167 | #define MPC1_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L |
2168 | #define MPC1_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L |
2169 | //PPU_SUVD_CGC_CTRL |
2170 | #define PPU_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 |
2171 | #define PPU_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 |
2172 | #define PPU_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 |
2173 | #define PPU_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 |
2174 | #define PPU_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 |
2175 | #define PPU_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 |
2176 | #define PPU_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 |
2177 | #define PPU_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 |
2178 | #define PPU_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 |
2179 | #define PPU_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 |
2180 | #define PPU_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa |
2181 | #define PPU_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb |
2182 | #define PPU_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc |
2183 | #define PPU_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd |
2184 | #define PPU_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe |
2185 | #define PPU_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf |
2186 | #define PPU_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 |
2187 | #define PPU_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 |
2188 | #define PPU_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 |
2189 | #define PPU_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 |
2190 | #define PPU_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 |
2191 | #define PPU_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 |
2192 | #define PPU_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 |
2193 | #define PPU_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c |
2194 | #define PPU_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d |
2195 | #define PPU_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e |
2196 | #define PPU_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L |
2197 | #define PPU_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L |
2198 | #define PPU_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L |
2199 | #define PPU_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L |
2200 | #define PPU_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L |
2201 | #define PPU_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L |
2202 | #define PPU_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L |
2203 | #define PPU_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L |
2204 | #define PPU_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L |
2205 | #define PPU_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L |
2206 | #define PPU_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L |
2207 | #define PPU_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L |
2208 | #define PPU_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L |
2209 | #define PPU_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L |
2210 | #define PPU_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L |
2211 | #define PPU_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L |
2212 | #define PPU_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L |
2213 | #define PPU_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L |
2214 | #define PPU_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L |
2215 | #define PPU_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L |
2216 | #define PPU_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L |
2217 | #define PPU_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L |
2218 | #define PPU_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L |
2219 | #define PPU_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L |
2220 | #define PPU_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L |
2221 | #define PPU_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L |
2222 | //SAOE_SUVD_CGC_CTRL |
2223 | #define SAOE_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 |
2224 | #define SAOE_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 |
2225 | #define SAOE_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 |
2226 | #define SAOE_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 |
2227 | #define SAOE_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 |
2228 | #define SAOE_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 |
2229 | #define SAOE_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 |
2230 | #define SAOE_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 |
2231 | #define SAOE_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 |
2232 | #define SAOE_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 |
2233 | #define SAOE_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa |
2234 | #define SAOE_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb |
2235 | #define SAOE_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc |
2236 | #define SAOE_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd |
2237 | #define SAOE_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe |
2238 | #define SAOE_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf |
2239 | #define SAOE_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 |
2240 | #define SAOE_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 |
2241 | #define SAOE_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 |
2242 | #define SAOE_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 |
2243 | #define SAOE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 |
2244 | #define SAOE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 |
2245 | #define SAOE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 |
2246 | #define SAOE_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c |
2247 | #define SAOE_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d |
2248 | #define SAOE_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e |
2249 | #define SAOE_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L |
2250 | #define SAOE_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L |
2251 | #define SAOE_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L |
2252 | #define SAOE_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L |
2253 | #define SAOE_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L |
2254 | #define SAOE_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L |
2255 | #define SAOE_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L |
2256 | #define SAOE_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L |
2257 | #define SAOE_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L |
2258 | #define SAOE_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L |
2259 | #define SAOE_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L |
2260 | #define SAOE_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L |
2261 | #define SAOE_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L |
2262 | #define SAOE_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L |
2263 | #define SAOE_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L |
2264 | #define SAOE_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L |
2265 | #define SAOE_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L |
2266 | #define SAOE_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L |
2267 | #define SAOE_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L |
2268 | #define SAOE_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L |
2269 | #define SAOE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L |
2270 | #define SAOE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L |
2271 | #define SAOE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L |
2272 | #define SAOE_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L |
2273 | #define SAOE_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L |
2274 | #define SAOE_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L |
2275 | //SCM_SUVD_CGC_CTRL |
2276 | #define SCM_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 |
2277 | #define SCM_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 |
2278 | #define SCM_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 |
2279 | #define SCM_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 |
2280 | #define SCM_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 |
2281 | #define SCM_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 |
2282 | #define SCM_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 |
2283 | #define SCM_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 |
2284 | #define SCM_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 |
2285 | #define SCM_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 |
2286 | #define SCM_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa |
2287 | #define SCM_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb |
2288 | #define SCM_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc |
2289 | #define SCM_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd |
2290 | #define SCM_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe |
2291 | #define SCM_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf |
2292 | #define SCM_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 |
2293 | #define SCM_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 |
2294 | #define SCM_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 |
2295 | #define SCM_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 |
2296 | #define SCM_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 |
2297 | #define SCM_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 |
2298 | #define SCM_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 |
2299 | #define SCM_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c |
2300 | #define SCM_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d |
2301 | #define SCM_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e |
2302 | #define SCM_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L |
2303 | #define SCM_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L |
2304 | #define SCM_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L |
2305 | #define SCM_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L |
2306 | #define SCM_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L |
2307 | #define SCM_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L |
2308 | #define SCM_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L |
2309 | #define SCM_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L |
2310 | #define SCM_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L |
2311 | #define SCM_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L |
2312 | #define SCM_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L |
2313 | #define SCM_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L |
2314 | #define SCM_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L |
2315 | #define SCM_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L |
2316 | #define SCM_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L |
2317 | #define SCM_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L |
2318 | #define SCM_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L |
2319 | #define SCM_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L |
2320 | #define SCM_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L |
2321 | #define SCM_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L |
2322 | #define SCM_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L |
2323 | #define SCM_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L |
2324 | #define SCM_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L |
2325 | #define SCM_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L |
2326 | #define SCM_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L |
2327 | #define SCM_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L |
2328 | //SDB_SUVD_CGC_CTRL |
2329 | #define SDB_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 |
2330 | #define SDB_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 |
2331 | #define SDB_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 |
2332 | #define SDB_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 |
2333 | #define SDB_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 |
2334 | #define SDB_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 |
2335 | #define SDB_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 |
2336 | #define SDB_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 |
2337 | #define SDB_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 |
2338 | #define SDB_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 |
2339 | #define SDB_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa |
2340 | #define SDB_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb |
2341 | #define SDB_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc |
2342 | #define SDB_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd |
2343 | #define SDB_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe |
2344 | #define SDB_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf |
2345 | #define SDB_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 |
2346 | #define SDB_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 |
2347 | #define SDB_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 |
2348 | #define SDB_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 |
2349 | #define SDB_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 |
2350 | #define SDB_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 |
2351 | #define SDB_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 |
2352 | #define SDB_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c |
2353 | #define SDB_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d |
2354 | #define SDB_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e |
2355 | #define SDB_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L |
2356 | #define SDB_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L |
2357 | #define SDB_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L |
2358 | #define SDB_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L |
2359 | #define SDB_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L |
2360 | #define SDB_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L |
2361 | #define SDB_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L |
2362 | #define SDB_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L |
2363 | #define SDB_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L |
2364 | #define SDB_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L |
2365 | #define SDB_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L |
2366 | #define SDB_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L |
2367 | #define SDB_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L |
2368 | #define SDB_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L |
2369 | #define SDB_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L |
2370 | #define SDB_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L |
2371 | #define SDB_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L |
2372 | #define SDB_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L |
2373 | #define SDB_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L |
2374 | #define SDB_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L |
2375 | #define SDB_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L |
2376 | #define SDB_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L |
2377 | #define SDB_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L |
2378 | #define SDB_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L |
2379 | #define SDB_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L |
2380 | #define SDB_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L |
2381 | //SIT0_NXT_SUVD_CGC_CTRL |
2382 | #define SIT0_NXT_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 |
2383 | #define SIT0_NXT_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 |
2384 | #define SIT0_NXT_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 |
2385 | #define SIT0_NXT_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 |
2386 | #define SIT0_NXT_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 |
2387 | #define SIT0_NXT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 |
2388 | #define SIT0_NXT_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 |
2389 | #define SIT0_NXT_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 |
2390 | #define SIT0_NXT_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 |
2391 | #define SIT0_NXT_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 |
2392 | #define SIT0_NXT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa |
2393 | #define SIT0_NXT_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb |
2394 | #define SIT0_NXT_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc |
2395 | #define SIT0_NXT_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd |
2396 | #define SIT0_NXT_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe |
2397 | #define SIT0_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf |
2398 | #define SIT0_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 |
2399 | #define SIT0_NXT_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 |
2400 | #define SIT0_NXT_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 |
2401 | #define SIT0_NXT_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 |
2402 | #define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 |
2403 | #define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 |
2404 | #define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 |
2405 | #define SIT0_NXT_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c |
2406 | #define SIT0_NXT_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d |
2407 | #define SIT0_NXT_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e |
2408 | #define SIT0_NXT_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L |
2409 | #define SIT0_NXT_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L |
2410 | #define SIT0_NXT_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L |
2411 | #define SIT0_NXT_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L |
2412 | #define SIT0_NXT_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L |
2413 | #define SIT0_NXT_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L |
2414 | #define SIT0_NXT_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L |
2415 | #define SIT0_NXT_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L |
2416 | #define SIT0_NXT_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L |
2417 | #define SIT0_NXT_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L |
2418 | #define SIT0_NXT_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L |
2419 | #define SIT0_NXT_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L |
2420 | #define SIT0_NXT_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L |
2421 | #define SIT0_NXT_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L |
2422 | #define SIT0_NXT_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L |
2423 | #define SIT0_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L |
2424 | #define SIT0_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L |
2425 | #define SIT0_NXT_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L |
2426 | #define SIT0_NXT_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L |
2427 | #define SIT0_NXT_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L |
2428 | #define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L |
2429 | #define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L |
2430 | #define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L |
2431 | #define SIT0_NXT_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L |
2432 | #define SIT0_NXT_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L |
2433 | #define SIT0_NXT_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L |
2434 | //SIT1_NXT_SUVD_CGC_CTRL |
2435 | #define SIT1_NXT_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 |
2436 | #define SIT1_NXT_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 |
2437 | #define SIT1_NXT_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 |
2438 | #define SIT1_NXT_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 |
2439 | #define SIT1_NXT_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 |
2440 | #define SIT1_NXT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 |
2441 | #define SIT1_NXT_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 |
2442 | #define SIT1_NXT_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 |
2443 | #define SIT1_NXT_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 |
2444 | #define SIT1_NXT_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 |
2445 | #define SIT1_NXT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa |
2446 | #define SIT1_NXT_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb |
2447 | #define SIT1_NXT_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc |
2448 | #define SIT1_NXT_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd |
2449 | #define SIT1_NXT_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe |
2450 | #define SIT1_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf |
2451 | #define SIT1_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 |
2452 | #define SIT1_NXT_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 |
2453 | #define SIT1_NXT_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 |
2454 | #define SIT1_NXT_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 |
2455 | #define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 |
2456 | #define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 |
2457 | #define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 |
2458 | #define SIT1_NXT_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c |
2459 | #define SIT1_NXT_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d |
2460 | #define SIT1_NXT_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e |
2461 | #define SIT1_NXT_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L |
2462 | #define SIT1_NXT_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L |
2463 | #define SIT1_NXT_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L |
2464 | #define SIT1_NXT_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L |
2465 | #define SIT1_NXT_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L |
2466 | #define SIT1_NXT_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L |
2467 | #define SIT1_NXT_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L |
2468 | #define SIT1_NXT_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L |
2469 | #define SIT1_NXT_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L |
2470 | #define SIT1_NXT_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L |
2471 | #define SIT1_NXT_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L |
2472 | #define SIT1_NXT_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L |
2473 | #define SIT1_NXT_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L |
2474 | #define SIT1_NXT_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L |
2475 | #define SIT1_NXT_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L |
2476 | #define SIT1_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L |
2477 | #define SIT1_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L |
2478 | #define SIT1_NXT_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L |
2479 | #define SIT1_NXT_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L |
2480 | #define SIT1_NXT_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L |
2481 | #define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L |
2482 | #define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L |
2483 | #define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L |
2484 | #define SIT1_NXT_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L |
2485 | #define SIT1_NXT_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L |
2486 | #define SIT1_NXT_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L |
2487 | //SIT2_NXT_SUVD_CGC_CTRL |
2488 | #define SIT2_NXT_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 |
2489 | #define SIT2_NXT_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 |
2490 | #define SIT2_NXT_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 |
2491 | #define SIT2_NXT_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 |
2492 | #define SIT2_NXT_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 |
2493 | #define SIT2_NXT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 |
2494 | #define SIT2_NXT_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 |
2495 | #define SIT2_NXT_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 |
2496 | #define SIT2_NXT_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 |
2497 | #define SIT2_NXT_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 |
2498 | #define SIT2_NXT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa |
2499 | #define SIT2_NXT_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb |
2500 | #define SIT2_NXT_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc |
2501 | #define SIT2_NXT_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd |
2502 | #define SIT2_NXT_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe |
2503 | #define SIT2_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf |
2504 | #define SIT2_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 |
2505 | #define SIT2_NXT_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 |
2506 | #define SIT2_NXT_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 |
2507 | #define SIT2_NXT_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 |
2508 | #define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 |
2509 | #define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 |
2510 | #define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 |
2511 | #define SIT2_NXT_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c |
2512 | #define SIT2_NXT_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d |
2513 | #define SIT2_NXT_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e |
2514 | #define SIT2_NXT_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L |
2515 | #define SIT2_NXT_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L |
2516 | #define SIT2_NXT_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L |
2517 | #define SIT2_NXT_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L |
2518 | #define SIT2_NXT_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L |
2519 | #define SIT2_NXT_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L |
2520 | #define SIT2_NXT_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L |
2521 | #define SIT2_NXT_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L |
2522 | #define SIT2_NXT_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L |
2523 | #define SIT2_NXT_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L |
2524 | #define SIT2_NXT_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L |
2525 | #define SIT2_NXT_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L |
2526 | #define SIT2_NXT_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L |
2527 | #define SIT2_NXT_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L |
2528 | #define SIT2_NXT_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L |
2529 | #define SIT2_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L |
2530 | #define SIT2_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L |
2531 | #define SIT2_NXT_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L |
2532 | #define SIT2_NXT_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L |
2533 | #define SIT2_NXT_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L |
2534 | #define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L |
2535 | #define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L |
2536 | #define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L |
2537 | #define SIT2_NXT_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L |
2538 | #define SIT2_NXT_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L |
2539 | #define SIT2_NXT_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L |
2540 | //SIT_SUVD_CGC_CTRL |
2541 | #define SIT_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 |
2542 | #define SIT_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 |
2543 | #define SIT_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 |
2544 | #define SIT_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 |
2545 | #define SIT_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 |
2546 | #define SIT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 |
2547 | #define SIT_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 |
2548 | #define SIT_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 |
2549 | #define SIT_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 |
2550 | #define SIT_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 |
2551 | #define SIT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa |
2552 | #define SIT_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb |
2553 | #define SIT_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc |
2554 | #define SIT_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd |
2555 | #define SIT_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe |
2556 | #define SIT_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf |
2557 | #define SIT_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 |
2558 | #define SIT_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 |
2559 | #define SIT_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 |
2560 | #define SIT_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 |
2561 | #define SIT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 |
2562 | #define SIT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 |
2563 | #define SIT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 |
2564 | #define SIT_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c |
2565 | #define SIT_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d |
2566 | #define SIT_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e |
2567 | #define SIT_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L |
2568 | #define SIT_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L |
2569 | #define SIT_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L |
2570 | #define SIT_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L |
2571 | #define SIT_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L |
2572 | #define SIT_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L |
2573 | #define SIT_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L |
2574 | #define SIT_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L |
2575 | #define SIT_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L |
2576 | #define SIT_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L |
2577 | #define SIT_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L |
2578 | #define SIT_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L |
2579 | #define SIT_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L |
2580 | #define SIT_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L |
2581 | #define SIT_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L |
2582 | #define SIT_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L |
2583 | #define SIT_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L |
2584 | #define SIT_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L |
2585 | #define SIT_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L |
2586 | #define SIT_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L |
2587 | #define SIT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L |
2588 | #define SIT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L |
2589 | #define SIT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L |
2590 | #define SIT_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L |
2591 | #define SIT_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L |
2592 | #define SIT_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L |
2593 | //SMPA_SUVD_CGC_CTRL |
2594 | #define SMPA_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 |
2595 | #define SMPA_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 |
2596 | #define SMPA_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 |
2597 | #define SMPA_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 |
2598 | #define SMPA_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 |
2599 | #define SMPA_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 |
2600 | #define SMPA_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 |
2601 | #define SMPA_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 |
2602 | #define SMPA_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 |
2603 | #define SMPA_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 |
2604 | #define SMPA_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa |
2605 | #define SMPA_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb |
2606 | #define SMPA_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc |
2607 | #define SMPA_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd |
2608 | #define SMPA_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe |
2609 | #define SMPA_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf |
2610 | #define SMPA_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 |
2611 | #define SMPA_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 |
2612 | #define SMPA_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 |
2613 | #define SMPA_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 |
2614 | #define SMPA_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 |
2615 | #define SMPA_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 |
2616 | #define SMPA_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 |
2617 | #define SMPA_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c |
2618 | #define SMPA_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d |
2619 | #define SMPA_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e |
2620 | #define SMPA_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L |
2621 | #define SMPA_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L |
2622 | #define SMPA_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L |
2623 | #define SMPA_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L |
2624 | #define SMPA_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L |
2625 | #define SMPA_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L |
2626 | #define SMPA_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L |
2627 | #define SMPA_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L |
2628 | #define SMPA_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L |
2629 | #define SMPA_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L |
2630 | #define SMPA_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L |
2631 | #define SMPA_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L |
2632 | #define SMPA_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L |
2633 | #define SMPA_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L |
2634 | #define SMPA_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L |
2635 | #define SMPA_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L |
2636 | #define SMPA_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L |
2637 | #define SMPA_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L |
2638 | #define SMPA_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L |
2639 | #define SMPA_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L |
2640 | #define SMPA_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L |
2641 | #define SMPA_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L |
2642 | #define SMPA_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L |
2643 | #define SMPA_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L |
2644 | #define SMPA_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L |
2645 | #define SMPA_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L |
2646 | //SMP_SUVD_CGC_CTRL |
2647 | #define SMP_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 |
2648 | #define SMP_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 |
2649 | #define SMP_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 |
2650 | #define SMP_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 |
2651 | #define SMP_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 |
2652 | #define SMP_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 |
2653 | #define SMP_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 |
2654 | #define SMP_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 |
2655 | #define SMP_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 |
2656 | #define SMP_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 |
2657 | #define SMP_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa |
2658 | #define SMP_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb |
2659 | #define SMP_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc |
2660 | #define SMP_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd |
2661 | #define SMP_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe |
2662 | #define SMP_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf |
2663 | #define SMP_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 |
2664 | #define SMP_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 |
2665 | #define SMP_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 |
2666 | #define SMP_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 |
2667 | #define SMP_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 |
2668 | #define SMP_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 |
2669 | #define SMP_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 |
2670 | #define SMP_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c |
2671 | #define SMP_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d |
2672 | #define SMP_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e |
2673 | #define SMP_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L |
2674 | #define SMP_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L |
2675 | #define SMP_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L |
2676 | #define SMP_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L |
2677 | #define SMP_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L |
2678 | #define SMP_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L |
2679 | #define SMP_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L |
2680 | #define SMP_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L |
2681 | #define SMP_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L |
2682 | #define SMP_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L |
2683 | #define SMP_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L |
2684 | #define SMP_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L |
2685 | #define SMP_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L |
2686 | #define SMP_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L |
2687 | #define SMP_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L |
2688 | #define SMP_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L |
2689 | #define SMP_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L |
2690 | #define SMP_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L |
2691 | #define SMP_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L |
2692 | #define SMP_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L |
2693 | #define SMP_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L |
2694 | #define SMP_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L |
2695 | #define SMP_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L |
2696 | #define SMP_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L |
2697 | #define SMP_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L |
2698 | #define SMP_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L |
2699 | //SRE_SUVD_CGC_CTRL |
2700 | #define SRE_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 |
2701 | #define SRE_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 |
2702 | #define SRE_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 |
2703 | #define SRE_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 |
2704 | #define SRE_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 |
2705 | #define SRE_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 |
2706 | #define SRE_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 |
2707 | #define SRE_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 |
2708 | #define SRE_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 |
2709 | #define SRE_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 |
2710 | #define SRE_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa |
2711 | #define SRE_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb |
2712 | #define SRE_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc |
2713 | #define SRE_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd |
2714 | #define SRE_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe |
2715 | #define SRE_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf |
2716 | #define SRE_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 |
2717 | #define SRE_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 |
2718 | #define SRE_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 |
2719 | #define SRE_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 |
2720 | #define SRE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 |
2721 | #define SRE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 |
2722 | #define SRE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 |
2723 | #define SRE_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c |
2724 | #define SRE_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d |
2725 | #define SRE_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e |
2726 | #define SRE_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L |
2727 | #define SRE_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L |
2728 | #define SRE_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L |
2729 | #define SRE_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L |
2730 | #define SRE_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L |
2731 | #define SRE_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L |
2732 | #define SRE_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L |
2733 | #define SRE_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L |
2734 | #define SRE_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L |
2735 | #define SRE_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L |
2736 | #define SRE_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L |
2737 | #define SRE_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L |
2738 | #define SRE_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L |
2739 | #define SRE_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L |
2740 | #define SRE_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L |
2741 | #define SRE_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L |
2742 | #define SRE_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L |
2743 | #define SRE_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L |
2744 | #define SRE_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L |
2745 | #define SRE_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L |
2746 | #define SRE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L |
2747 | #define SRE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L |
2748 | #define SRE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L |
2749 | #define SRE_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L |
2750 | #define SRE_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L |
2751 | #define SRE_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L |
2752 | //UVD_MPBE0_SUVD_CGC_CTRL |
2753 | #define UVD_MPBE0_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 |
2754 | #define UVD_MPBE0_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 |
2755 | #define UVD_MPBE0_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 |
2756 | #define UVD_MPBE0_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 |
2757 | #define UVD_MPBE0_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 |
2758 | #define UVD_MPBE0_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 |
2759 | #define UVD_MPBE0_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 |
2760 | #define UVD_MPBE0_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 |
2761 | #define UVD_MPBE0_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 |
2762 | #define UVD_MPBE0_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 |
2763 | #define UVD_MPBE0_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa |
2764 | #define UVD_MPBE0_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb |
2765 | #define UVD_MPBE0_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc |
2766 | #define UVD_MPBE0_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd |
2767 | #define UVD_MPBE0_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe |
2768 | #define UVD_MPBE0_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf |
2769 | #define UVD_MPBE0_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 |
2770 | #define UVD_MPBE0_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 |
2771 | #define UVD_MPBE0_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c |
2772 | #define UVD_MPBE0_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d |
2773 | #define UVD_MPBE0_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e |
2774 | #define UVD_MPBE0_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L |
2775 | #define UVD_MPBE0_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L |
2776 | #define UVD_MPBE0_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L |
2777 | #define UVD_MPBE0_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L |
2778 | #define UVD_MPBE0_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L |
2779 | #define UVD_MPBE0_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L |
2780 | #define UVD_MPBE0_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L |
2781 | #define UVD_MPBE0_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L |
2782 | #define UVD_MPBE0_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L |
2783 | #define UVD_MPBE0_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L |
2784 | #define UVD_MPBE0_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L |
2785 | #define UVD_MPBE0_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L |
2786 | #define UVD_MPBE0_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L |
2787 | #define UVD_MPBE0_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L |
2788 | #define UVD_MPBE0_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L |
2789 | #define UVD_MPBE0_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L |
2790 | #define UVD_MPBE0_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L |
2791 | #define UVD_MPBE0_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L |
2792 | #define UVD_MPBE0_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L |
2793 | #define UVD_MPBE0_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L |
2794 | #define UVD_MPBE0_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L |
2795 | //UVD_MPBE1_SUVD_CGC_CTRL |
2796 | #define UVD_MPBE1_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 |
2797 | #define UVD_MPBE1_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 |
2798 | #define UVD_MPBE1_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 |
2799 | #define UVD_MPBE1_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 |
2800 | #define UVD_MPBE1_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 |
2801 | #define UVD_MPBE1_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 |
2802 | #define UVD_MPBE1_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 |
2803 | #define UVD_MPBE1_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 |
2804 | #define UVD_MPBE1_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 |
2805 | #define UVD_MPBE1_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 |
2806 | #define UVD_MPBE1_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa |
2807 | #define UVD_MPBE1_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb |
2808 | #define UVD_MPBE1_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc |
2809 | #define UVD_MPBE1_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd |
2810 | #define UVD_MPBE1_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe |
2811 | #define UVD_MPBE1_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf |
2812 | #define UVD_MPBE1_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 |
2813 | #define UVD_MPBE1_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 |
2814 | #define UVD_MPBE1_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c |
2815 | #define UVD_MPBE1_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d |
2816 | #define UVD_MPBE1_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e |
2817 | #define UVD_MPBE1_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L |
2818 | #define UVD_MPBE1_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L |
2819 | #define UVD_MPBE1_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L |
2820 | #define UVD_MPBE1_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L |
2821 | #define UVD_MPBE1_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L |
2822 | #define UVD_MPBE1_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L |
2823 | #define UVD_MPBE1_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L |
2824 | #define UVD_MPBE1_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L |
2825 | #define UVD_MPBE1_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L |
2826 | #define UVD_MPBE1_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L |
2827 | #define UVD_MPBE1_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L |
2828 | #define UVD_MPBE1_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L |
2829 | #define UVD_MPBE1_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L |
2830 | #define UVD_MPBE1_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L |
2831 | #define UVD_MPBE1_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L |
2832 | #define UVD_MPBE1_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L |
2833 | #define UVD_MPBE1_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L |
2834 | #define UVD_MPBE1_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L |
2835 | #define UVD_MPBE1_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L |
2836 | #define UVD_MPBE1_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L |
2837 | #define UVD_MPBE1_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L |
2838 | //UVD_SUVD_CGC_CTRL |
2839 | #define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 |
2840 | #define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 |
2841 | #define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 |
2842 | #define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 |
2843 | #define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 |
2844 | #define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 |
2845 | #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 |
2846 | #define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 |
2847 | #define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 |
2848 | #define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 |
2849 | #define UVD_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa |
2850 | #define UVD_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb |
2851 | #define UVD_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc |
2852 | #define UVD_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd |
2853 | #define UVD_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe |
2854 | #define UVD_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf |
2855 | #define UVD_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 |
2856 | #define UVD_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 |
2857 | #define UVD_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 |
2858 | #define UVD_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 |
2859 | #define UVD_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 |
2860 | #define UVD_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 |
2861 | #define UVD_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 |
2862 | #define UVD_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c |
2863 | #define UVD_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d |
2864 | #define UVD_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e |
2865 | #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L |
2866 | #define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L |
2867 | #define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L |
2868 | #define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L |
2869 | #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L |
2870 | #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L |
2871 | #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L |
2872 | #define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L |
2873 | #define UVD_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L |
2874 | #define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L |
2875 | #define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L |
2876 | #define UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L |
2877 | #define UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L |
2878 | #define UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L |
2879 | #define UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L |
2880 | #define UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L |
2881 | #define UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L |
2882 | #define UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L |
2883 | #define UVD_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L |
2884 | #define UVD_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L |
2885 | #define UVD_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L |
2886 | #define UVD_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L |
2887 | #define UVD_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L |
2888 | #define UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L |
2889 | #define UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L |
2890 | #define UVD_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L |
2891 | //UVD_CGC_CTRL3 |
2892 | #define UVD_CGC_CTRL3__CGC_CLK_OFF_DELAY__SHIFT 0x0 |
2893 | #define UVD_CGC_CTRL3__LCM0_MODE__SHIFT 0xb |
2894 | #define UVD_CGC_CTRL3__LCM1_MODE__SHIFT 0xc |
2895 | #define UVD_CGC_CTRL3__MIF_MODE__SHIFT 0xd |
2896 | #define UVD_CGC_CTRL3__VREG_MODE__SHIFT 0xe |
2897 | #define UVD_CGC_CTRL3__PE_MODE__SHIFT 0xf |
2898 | #define UVD_CGC_CTRL3__PPU_MODE__SHIFT 0x10 |
2899 | #define UVD_CGC_CTRL3__CGC_CLK_OFF_DELAY_MASK 0x000000FFL |
2900 | #define UVD_CGC_CTRL3__LCM0_MODE_MASK 0x00000800L |
2901 | #define UVD_CGC_CTRL3__LCM1_MODE_MASK 0x00001000L |
2902 | #define UVD_CGC_CTRL3__MIF_MODE_MASK 0x00002000L |
2903 | #define UVD_CGC_CTRL3__VREG_MODE_MASK 0x00004000L |
2904 | #define UVD_CGC_CTRL3__PE_MODE_MASK 0x00008000L |
2905 | #define UVD_CGC_CTRL3__PPU_MODE_MASK 0x00010000L |
2906 | //UVD_GPCOM_VCPU_DATA0 |
2907 | #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 |
2908 | #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xFFFFFFFFL |
2909 | //UVD_GPCOM_VCPU_DATA1 |
2910 | #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 |
2911 | #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL |
2912 | //UVD_GPCOM_SYS_CMD |
2913 | #define UVD_GPCOM_SYS_CMD__CMD_SEND__SHIFT 0x0 |
2914 | #define UVD_GPCOM_SYS_CMD__CMD__SHIFT 0x1 |
2915 | #define UVD_GPCOM_SYS_CMD__CMD_SOURCE__SHIFT 0x1f |
2916 | #define UVD_GPCOM_SYS_CMD__CMD_SEND_MASK 0x00000001L |
2917 | #define UVD_GPCOM_SYS_CMD__CMD_MASK 0x7FFFFFFEL |
2918 | #define UVD_GPCOM_SYS_CMD__CMD_SOURCE_MASK 0x80000000L |
2919 | //UVD_GPCOM_SYS_DATA0 |
2920 | #define UVD_GPCOM_SYS_DATA0__DATA0__SHIFT 0x0 |
2921 | #define UVD_GPCOM_SYS_DATA0__DATA0_MASK 0xFFFFFFFFL |
2922 | //UVD_GPCOM_SYS_DATA1 |
2923 | #define UVD_GPCOM_SYS_DATA1__DATA1__SHIFT 0x0 |
2924 | #define UVD_GPCOM_SYS_DATA1__DATA1_MASK 0xFFFFFFFFL |
2925 | //UVD_VCPU_INT_EN |
2926 | #define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 |
2927 | #define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 |
2928 | #define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 |
2929 | #define UVD_VCPU_INT_EN__NJ_PF_RPT_EN__SHIFT 0x3 |
2930 | #define UVD_VCPU_INT_EN__SW_RB1_INT_EN__SHIFT 0x4 |
2931 | #define UVD_VCPU_INT_EN__SW_RB2_INT_EN__SHIFT 0x5 |
2932 | #define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 |
2933 | #define UVD_VCPU_INT_EN__SW_RB3_INT_EN__SHIFT 0x7 |
2934 | #define UVD_VCPU_INT_EN__SW_RB4_INT_EN__SHIFT 0x9 |
2935 | #define UVD_VCPU_INT_EN__SW_RB5_INT_EN__SHIFT 0xa |
2936 | #define UVD_VCPU_INT_EN__LBSI_EN__SHIFT 0xb |
2937 | #define UVD_VCPU_INT_EN__UDEC_EN__SHIFT 0xc |
2938 | #define UVD_VCPU_INT_EN__SUVD_EN__SHIFT 0xf |
2939 | #define UVD_VCPU_INT_EN__RPTR_WR_EN__SHIFT 0x10 |
2940 | #define UVD_VCPU_INT_EN__JOB_START_EN__SHIFT 0x11 |
2941 | #define UVD_VCPU_INT_EN__NJ_PF_EN__SHIFT 0x12 |
2942 | #define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 |
2943 | #define UVD_VCPU_INT_EN__IDCT_EN__SHIFT 0x18 |
2944 | #define UVD_VCPU_INT_EN__MPRD_EN__SHIFT 0x19 |
2945 | #define UVD_VCPU_INT_EN__AVM_INT_EN__SHIFT 0x1a |
2946 | #define UVD_VCPU_INT_EN__CLK_SWT_EN__SHIFT 0x1b |
2947 | #define UVD_VCPU_INT_EN__MIF_HWINT_EN__SHIFT 0x1c |
2948 | #define UVD_VCPU_INT_EN__MPRD_ERR_EN__SHIFT 0x1d |
2949 | #define UVD_VCPU_INT_EN__DRV_FW_REQ_EN__SHIFT 0x1e |
2950 | #define UVD_VCPU_INT_EN__DRV_FW_ACK_EN__SHIFT 0x1f |
2951 | #define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L |
2952 | #define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L |
2953 | #define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L |
2954 | #define UVD_VCPU_INT_EN__NJ_PF_RPT_EN_MASK 0x00000008L |
2955 | #define UVD_VCPU_INT_EN__SW_RB1_INT_EN_MASK 0x00000010L |
2956 | #define UVD_VCPU_INT_EN__SW_RB2_INT_EN_MASK 0x00000020L |
2957 | #define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L |
2958 | #define UVD_VCPU_INT_EN__SW_RB3_INT_EN_MASK 0x00000080L |
2959 | #define UVD_VCPU_INT_EN__SW_RB4_INT_EN_MASK 0x00000200L |
2960 | #define UVD_VCPU_INT_EN__SW_RB5_INT_EN_MASK 0x00000400L |
2961 | #define UVD_VCPU_INT_EN__LBSI_EN_MASK 0x00000800L |
2962 | #define UVD_VCPU_INT_EN__UDEC_EN_MASK 0x00001000L |
2963 | #define UVD_VCPU_INT_EN__SUVD_EN_MASK 0x00008000L |
2964 | #define UVD_VCPU_INT_EN__RPTR_WR_EN_MASK 0x00010000L |
2965 | #define UVD_VCPU_INT_EN__JOB_START_EN_MASK 0x00020000L |
2966 | #define UVD_VCPU_INT_EN__NJ_PF_EN_MASK 0x00040000L |
2967 | #define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L |
2968 | #define UVD_VCPU_INT_EN__IDCT_EN_MASK 0x01000000L |
2969 | #define UVD_VCPU_INT_EN__MPRD_EN_MASK 0x02000000L |
2970 | #define UVD_VCPU_INT_EN__AVM_INT_EN_MASK 0x04000000L |
2971 | #define UVD_VCPU_INT_EN__CLK_SWT_EN_MASK 0x08000000L |
2972 | #define UVD_VCPU_INT_EN__MIF_HWINT_EN_MASK 0x10000000L |
2973 | #define UVD_VCPU_INT_EN__MPRD_ERR_EN_MASK 0x20000000L |
2974 | #define UVD_VCPU_INT_EN__DRV_FW_REQ_EN_MASK 0x40000000L |
2975 | #define UVD_VCPU_INT_EN__DRV_FW_ACK_EN_MASK 0x80000000L |
2976 | //UVD_VCPU_INT_STATUS |
2977 | #define UVD_VCPU_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0 |
2978 | #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1 |
2979 | #define UVD_VCPU_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2 |
2980 | #define UVD_VCPU_INT_STATUS__NJ_PF_RPT_INT__SHIFT 0x3 |
2981 | #define UVD_VCPU_INT_STATUS__SW_RB1_INT__SHIFT 0x4 |
2982 | #define UVD_VCPU_INT_STATUS__SW_RB2_INT__SHIFT 0x5 |
2983 | #define UVD_VCPU_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6 |
2984 | #define UVD_VCPU_INT_STATUS__SW_RB3_INT__SHIFT 0x7 |
2985 | #define UVD_VCPU_INT_STATUS__SW_RB4_INT__SHIFT 0x9 |
2986 | #define UVD_VCPU_INT_STATUS__SW_RB5_INT__SHIFT 0xa |
2987 | #define UVD_VCPU_INT_STATUS__LBSI_INT__SHIFT 0xb |
2988 | #define UVD_VCPU_INT_STATUS__UDEC_INT__SHIFT 0xc |
2989 | #define UVD_VCPU_INT_STATUS__SUVD_INT__SHIFT 0xf |
2990 | #define UVD_VCPU_INT_STATUS__RPTR_WR_INT__SHIFT 0x10 |
2991 | #define UVD_VCPU_INT_STATUS__JOB_START_INT__SHIFT 0x11 |
2992 | #define UVD_VCPU_INT_STATUS__NJ_PF_INT__SHIFT 0x12 |
2993 | #define UVD_VCPU_INT_STATUS__GPCOM_INT__SHIFT 0x14 |
2994 | #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17 |
2995 | #define UVD_VCPU_INT_STATUS__IDCT_INT__SHIFT 0x18 |
2996 | #define UVD_VCPU_INT_STATUS__MPRD_INT__SHIFT 0x19 |
2997 | #define UVD_VCPU_INT_STATUS__AVM_INT__SHIFT 0x1a |
2998 | #define UVD_VCPU_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b |
2999 | #define UVD_VCPU_INT_STATUS__MIF_HWINT__SHIFT 0x1c |
3000 | #define UVD_VCPU_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d |
3001 | #define UVD_VCPU_INT_STATUS__DRV_FW_REQ_INT__SHIFT 0x1e |
3002 | #define UVD_VCPU_INT_STATUS__DRV_FW_ACK_INT__SHIFT 0x1f |
3003 | #define UVD_VCPU_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L |
3004 | #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L |
3005 | #define UVD_VCPU_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L |
3006 | #define UVD_VCPU_INT_STATUS__NJ_PF_RPT_INT_MASK 0x00000008L |
3007 | #define UVD_VCPU_INT_STATUS__SW_RB1_INT_MASK 0x00000010L |
3008 | #define UVD_VCPU_INT_STATUS__SW_RB2_INT_MASK 0x00000020L |
3009 | #define UVD_VCPU_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L |
3010 | #define UVD_VCPU_INT_STATUS__SW_RB3_INT_MASK 0x00000080L |
3011 | #define UVD_VCPU_INT_STATUS__SW_RB4_INT_MASK 0x00000200L |
3012 | #define UVD_VCPU_INT_STATUS__SW_RB5_INT_MASK 0x00000400L |
3013 | #define UVD_VCPU_INT_STATUS__LBSI_INT_MASK 0x00000800L |
3014 | #define UVD_VCPU_INT_STATUS__UDEC_INT_MASK 0x00001000L |
3015 | #define UVD_VCPU_INT_STATUS__SUVD_INT_MASK 0x00008000L |
3016 | #define UVD_VCPU_INT_STATUS__RPTR_WR_INT_MASK 0x00010000L |
3017 | #define UVD_VCPU_INT_STATUS__JOB_START_INT_MASK 0x00020000L |
3018 | #define UVD_VCPU_INT_STATUS__NJ_PF_INT_MASK 0x00040000L |
3019 | #define UVD_VCPU_INT_STATUS__GPCOM_INT_MASK 0x00100000L |
3020 | #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L |
3021 | #define UVD_VCPU_INT_STATUS__IDCT_INT_MASK 0x01000000L |
3022 | #define UVD_VCPU_INT_STATUS__MPRD_INT_MASK 0x02000000L |
3023 | #define UVD_VCPU_INT_STATUS__AVM_INT_MASK 0x04000000L |
3024 | #define UVD_VCPU_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L |
3025 | #define UVD_VCPU_INT_STATUS__MIF_HWINT_MASK 0x10000000L |
3026 | #define UVD_VCPU_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L |
3027 | #define UVD_VCPU_INT_STATUS__DRV_FW_REQ_INT_MASK 0x40000000L |
3028 | #define UVD_VCPU_INT_STATUS__DRV_FW_ACK_INT_MASK 0x80000000L |
3029 | //UVD_VCPU_INT_ACK |
3030 | #define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 |
3031 | #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 |
3032 | #define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 |
3033 | #define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK__SHIFT 0x3 |
3034 | #define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK__SHIFT 0x4 |
3035 | #define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK__SHIFT 0x5 |
3036 | #define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 |
3037 | #define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK__SHIFT 0x7 |
3038 | #define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK__SHIFT 0x9 |
3039 | #define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK__SHIFT 0xa |
3040 | #define UVD_VCPU_INT_ACK__LBSI_ACK__SHIFT 0xb |
3041 | #define UVD_VCPU_INT_ACK__UDEC_ACK__SHIFT 0xc |
3042 | #define UVD_VCPU_INT_ACK__SUVD_ACK__SHIFT 0xf |
3043 | #define UVD_VCPU_INT_ACK__RPTR_WR_ACK__SHIFT 0x10 |
3044 | #define UVD_VCPU_INT_ACK__JOB_START_ACK__SHIFT 0x11 |
3045 | #define UVD_VCPU_INT_ACK__NJ_PF_ACK__SHIFT 0x12 |
3046 | #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 |
3047 | #define UVD_VCPU_INT_ACK__IDCT_ACK__SHIFT 0x18 |
3048 | #define UVD_VCPU_INT_ACK__MPRD_ACK__SHIFT 0x19 |
3049 | #define UVD_VCPU_INT_ACK__AVM_INT_ACK__SHIFT 0x1a |
3050 | #define UVD_VCPU_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b |
3051 | #define UVD_VCPU_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c |
3052 | #define UVD_VCPU_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d |
3053 | #define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK__SHIFT 0x1e |
3054 | #define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK__SHIFT 0x1f |
3055 | #define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L |
3056 | #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L |
3057 | #define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L |
3058 | #define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK_MASK 0x00000008L |
3059 | #define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK_MASK 0x00000010L |
3060 | #define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK_MASK 0x00000020L |
3061 | #define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L |
3062 | #define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK_MASK 0x00000080L |
3063 | #define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK_MASK 0x00000200L |
3064 | #define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK_MASK 0x00000400L |
3065 | #define UVD_VCPU_INT_ACK__LBSI_ACK_MASK 0x00000800L |
3066 | #define UVD_VCPU_INT_ACK__UDEC_ACK_MASK 0x00001000L |
3067 | #define UVD_VCPU_INT_ACK__SUVD_ACK_MASK 0x00008000L |
3068 | #define UVD_VCPU_INT_ACK__RPTR_WR_ACK_MASK 0x00010000L |
3069 | #define UVD_VCPU_INT_ACK__JOB_START_ACK_MASK 0x00020000L |
3070 | #define UVD_VCPU_INT_ACK__NJ_PF_ACK_MASK 0x00040000L |
3071 | #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L |
3072 | #define UVD_VCPU_INT_ACK__IDCT_ACK_MASK 0x01000000L |
3073 | #define UVD_VCPU_INT_ACK__MPRD_ACK_MASK 0x02000000L |
3074 | #define UVD_VCPU_INT_ACK__AVM_INT_ACK_MASK 0x04000000L |
3075 | #define UVD_VCPU_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L |
3076 | #define UVD_VCPU_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L |
3077 | #define UVD_VCPU_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L |
3078 | #define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK_MASK 0x40000000L |
3079 | #define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK_MASK 0x80000000L |
3080 | //UVD_VCPU_INT_ROUTE |
3081 | #define UVD_VCPU_INT_ROUTE__DRV_FW_MSG__SHIFT 0x0 |
3082 | #define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK__SHIFT 0x1 |
3083 | #define UVD_VCPU_INT_ROUTE__VCPU_GPCOM__SHIFT 0x2 |
3084 | #define UVD_VCPU_INT_ROUTE__DRV_FW_MSG_MASK 0x00000001L |
3085 | #define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK_MASK 0x00000002L |
3086 | #define UVD_VCPU_INT_ROUTE__VCPU_GPCOM_MASK 0x00000004L |
3087 | //UVD_DRV_FW_MSG |
3088 | #define UVD_DRV_FW_MSG__MSG__SHIFT 0x0 |
3089 | #define UVD_DRV_FW_MSG__MSG_MASK 0xFFFFFFFFL |
3090 | //UVD_FW_DRV_MSG_ACK |
3091 | #define UVD_FW_DRV_MSG_ACK__ACK__SHIFT 0x0 |
3092 | #define UVD_FW_DRV_MSG_ACK__ACK_MASK 0x00000001L |
3093 | //UVD_SUVD_INT_EN |
3094 | #define UVD_SUVD_INT_EN__SRE_FUNC_INT_EN__SHIFT 0x0 |
3095 | #define UVD_SUVD_INT_EN__SRE_ERR_INT_EN__SHIFT 0x5 |
3096 | #define UVD_SUVD_INT_EN__SIT_FUNC_INT_EN__SHIFT 0x6 |
3097 | #define UVD_SUVD_INT_EN__SIT_ERR_INT_EN__SHIFT 0xb |
3098 | #define UVD_SUVD_INT_EN__SMP_FUNC_INT_EN__SHIFT 0xc |
3099 | #define UVD_SUVD_INT_EN__SMP_ERR_INT_EN__SHIFT 0x11 |
3100 | #define UVD_SUVD_INT_EN__SCM_FUNC_INT_EN__SHIFT 0x12 |
3101 | #define UVD_SUVD_INT_EN__SCM_ERR_INT_EN__SHIFT 0x17 |
3102 | #define UVD_SUVD_INT_EN__SDB_FUNC_INT_EN__SHIFT 0x18 |
3103 | #define UVD_SUVD_INT_EN__SDB_ERR_INT_EN__SHIFT 0x1d |
3104 | #define UVD_SUVD_INT_EN__FBC_ERR_INT_EN__SHIFT 0x1e |
3105 | #define UVD_SUVD_INT_EN__SRE_FUNC_INT_EN_MASK 0x0000001FL |
3106 | #define UVD_SUVD_INT_EN__SRE_ERR_INT_EN_MASK 0x00000020L |
3107 | #define UVD_SUVD_INT_EN__SIT_FUNC_INT_EN_MASK 0x000007C0L |
3108 | #define UVD_SUVD_INT_EN__SIT_ERR_INT_EN_MASK 0x00000800L |
3109 | #define UVD_SUVD_INT_EN__SMP_FUNC_INT_EN_MASK 0x0001F000L |
3110 | #define UVD_SUVD_INT_EN__SMP_ERR_INT_EN_MASK 0x00020000L |
3111 | #define UVD_SUVD_INT_EN__SCM_FUNC_INT_EN_MASK 0x007C0000L |
3112 | #define UVD_SUVD_INT_EN__SCM_ERR_INT_EN_MASK 0x00800000L |
3113 | #define UVD_SUVD_INT_EN__SDB_FUNC_INT_EN_MASK 0x1F000000L |
3114 | #define UVD_SUVD_INT_EN__SDB_ERR_INT_EN_MASK 0x20000000L |
3115 | #define UVD_SUVD_INT_EN__FBC_ERR_INT_EN_MASK 0x40000000L |
3116 | //UVD_SUVD_INT_STATUS |
3117 | #define UVD_SUVD_INT_STATUS__SRE_FUNC_INT__SHIFT 0x0 |
3118 | #define UVD_SUVD_INT_STATUS__SRE_ERR_INT__SHIFT 0x5 |
3119 | #define UVD_SUVD_INT_STATUS__SIT_FUNC_INT__SHIFT 0x6 |
3120 | #define UVD_SUVD_INT_STATUS__SIT_ERR_INT__SHIFT 0xb |
3121 | #define UVD_SUVD_INT_STATUS__SMP_FUNC_INT__SHIFT 0xc |
3122 | #define UVD_SUVD_INT_STATUS__SMP_ERR_INT__SHIFT 0x11 |
3123 | #define UVD_SUVD_INT_STATUS__SCM_FUNC_INT__SHIFT 0x12 |
3124 | #define UVD_SUVD_INT_STATUS__SCM_ERR_INT__SHIFT 0x17 |
3125 | #define UVD_SUVD_INT_STATUS__SDB_FUNC_INT__SHIFT 0x18 |
3126 | #define UVD_SUVD_INT_STATUS__SDB_ERR_INT__SHIFT 0x1d |
3127 | #define UVD_SUVD_INT_STATUS__FBC_ERR_INT__SHIFT 0x1e |
3128 | #define UVD_SUVD_INT_STATUS__SRE_FUNC_INT_MASK 0x0000001FL |
3129 | #define UVD_SUVD_INT_STATUS__SRE_ERR_INT_MASK 0x00000020L |
3130 | #define UVD_SUVD_INT_STATUS__SIT_FUNC_INT_MASK 0x000007C0L |
3131 | #define UVD_SUVD_INT_STATUS__SIT_ERR_INT_MASK 0x00000800L |
3132 | #define UVD_SUVD_INT_STATUS__SMP_FUNC_INT_MASK 0x0001F000L |
3133 | #define UVD_SUVD_INT_STATUS__SMP_ERR_INT_MASK 0x00020000L |
3134 | #define UVD_SUVD_INT_STATUS__SCM_FUNC_INT_MASK 0x007C0000L |
3135 | #define UVD_SUVD_INT_STATUS__SCM_ERR_INT_MASK 0x00800000L |
3136 | #define UVD_SUVD_INT_STATUS__SDB_FUNC_INT_MASK 0x1F000000L |
3137 | #define UVD_SUVD_INT_STATUS__SDB_ERR_INT_MASK 0x20000000L |
3138 | #define UVD_SUVD_INT_STATUS__FBC_ERR_INT_MASK 0x40000000L |
3139 | //UVD_SUVD_INT_ACK |
3140 | #define UVD_SUVD_INT_ACK__SRE_FUNC_INT_ACK__SHIFT 0x0 |
3141 | #define UVD_SUVD_INT_ACK__SRE_ERR_INT_ACK__SHIFT 0x5 |
3142 | #define UVD_SUVD_INT_ACK__SIT_FUNC_INT_ACK__SHIFT 0x6 |
3143 | #define UVD_SUVD_INT_ACK__SIT_ERR_INT_ACK__SHIFT 0xb |
3144 | #define UVD_SUVD_INT_ACK__SMP_FUNC_INT_ACK__SHIFT 0xc |
3145 | #define UVD_SUVD_INT_ACK__SMP_ERR_INT_ACK__SHIFT 0x11 |
3146 | #define UVD_SUVD_INT_ACK__SCM_FUNC_INT_ACK__SHIFT 0x12 |
3147 | #define UVD_SUVD_INT_ACK__SCM_ERR_INT_ACK__SHIFT 0x17 |
3148 | #define UVD_SUVD_INT_ACK__SDB_FUNC_INT_ACK__SHIFT 0x18 |
3149 | #define UVD_SUVD_INT_ACK__SDB_ERR_INT_ACK__SHIFT 0x1d |
3150 | #define UVD_SUVD_INT_ACK__FBC_ERR_INT_ACK__SHIFT 0x1e |
3151 | #define UVD_SUVD_INT_ACK__SRE_FUNC_INT_ACK_MASK 0x0000001FL |
3152 | #define UVD_SUVD_INT_ACK__SRE_ERR_INT_ACK_MASK 0x00000020L |
3153 | #define UVD_SUVD_INT_ACK__SIT_FUNC_INT_ACK_MASK 0x000007C0L |
3154 | #define UVD_SUVD_INT_ACK__SIT_ERR_INT_ACK_MASK 0x00000800L |
3155 | #define UVD_SUVD_INT_ACK__SMP_FUNC_INT_ACK_MASK 0x0001F000L |
3156 | #define UVD_SUVD_INT_ACK__SMP_ERR_INT_ACK_MASK 0x00020000L |
3157 | #define UVD_SUVD_INT_ACK__SCM_FUNC_INT_ACK_MASK 0x007C0000L |
3158 | #define UVD_SUVD_INT_ACK__SCM_ERR_INT_ACK_MASK 0x00800000L |
3159 | #define UVD_SUVD_INT_ACK__SDB_FUNC_INT_ACK_MASK 0x1F000000L |
3160 | #define UVD_SUVD_INT_ACK__SDB_ERR_INT_ACK_MASK 0x20000000L |
3161 | #define UVD_SUVD_INT_ACK__FBC_ERR_INT_ACK_MASK 0x40000000L |
3162 | //UVD_ENC_VCPU_INT_EN |
3163 | #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN__SHIFT 0x0 |
3164 | #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN__SHIFT 0x1 |
3165 | #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN__SHIFT 0x2 |
3166 | #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN_MASK 0x00000001L |
3167 | #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN_MASK 0x00000002L |
3168 | #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN_MASK 0x00000004L |
3169 | //UVD_ENC_VCPU_INT_STATUS |
3170 | #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR_INT__SHIFT 0x0 |
3171 | #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR2_INT__SHIFT 0x1 |
3172 | #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR3_INT__SHIFT 0x2 |
3173 | #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR_INT_MASK 0x00000001L |
3174 | #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR2_INT_MASK 0x00000002L |
3175 | #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR3_INT_MASK 0x00000004L |
3176 | //UVD_ENC_VCPU_INT_ACK |
3177 | #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK__SHIFT 0x0 |
3178 | #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK__SHIFT 0x1 |
3179 | #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK__SHIFT 0x2 |
3180 | #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK_MASK 0x00000001L |
3181 | #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK_MASK 0x00000002L |
3182 | #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK_MASK 0x00000004L |
3183 | //UVD_MASTINT_EN |
3184 | #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 |
3185 | #define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 |
3186 | #define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 |
3187 | #define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 |
3188 | #define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L |
3189 | #define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L |
3190 | #define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L |
3191 | #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x00FFFFF0L |
3192 | //UVD_SYS_INT_EN |
3193 | #define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 |
3194 | #define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 |
3195 | #define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 |
3196 | #define UVD_SYS_INT_EN__CXW_WR_EN__SHIFT 0x3 |
3197 | #define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 |
3198 | #define UVD_SYS_INT_EN__LBSI_EN__SHIFT 0xb |
3199 | #define UVD_SYS_INT_EN__UDEC_EN__SHIFT 0xc |
3200 | #define UVD_SYS_INT_EN__SUVD_EN__SHIFT 0xf |
3201 | #define UVD_SYS_INT_EN__JOB_DONE_EN__SHIFT 0x10 |
3202 | #define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 |
3203 | #define UVD_SYS_INT_EN__IDCT_EN__SHIFT 0x18 |
3204 | #define UVD_SYS_INT_EN__MPRD_EN__SHIFT 0x19 |
3205 | #define UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN__SHIFT 0x1a |
3206 | #define UVD_SYS_INT_EN__CLK_SWT_EN__SHIFT 0x1b |
3207 | #define UVD_SYS_INT_EN__MIF_HWINT_EN__SHIFT 0x1c |
3208 | #define UVD_SYS_INT_EN__MPRD_ERR_EN__SHIFT 0x1d |
3209 | #define UVD_SYS_INT_EN__AVM_INT_EN__SHIFT 0x1f |
3210 | #define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L |
3211 | #define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L |
3212 | #define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L |
3213 | #define UVD_SYS_INT_EN__CXW_WR_EN_MASK 0x00000008L |
3214 | #define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L |
3215 | #define UVD_SYS_INT_EN__LBSI_EN_MASK 0x00000800L |
3216 | #define UVD_SYS_INT_EN__UDEC_EN_MASK 0x00001000L |
3217 | #define UVD_SYS_INT_EN__SUVD_EN_MASK 0x00008000L |
3218 | #define UVD_SYS_INT_EN__JOB_DONE_EN_MASK 0x00010000L |
3219 | #define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L |
3220 | #define UVD_SYS_INT_EN__IDCT_EN_MASK 0x01000000L |
3221 | #define UVD_SYS_INT_EN__MPRD_EN_MASK 0x02000000L |
3222 | #define UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK 0x04000000L |
3223 | #define UVD_SYS_INT_EN__CLK_SWT_EN_MASK 0x08000000L |
3224 | #define UVD_SYS_INT_EN__MIF_HWINT_EN_MASK 0x10000000L |
3225 | #define UVD_SYS_INT_EN__MPRD_ERR_EN_MASK 0x20000000L |
3226 | #define UVD_SYS_INT_EN__AVM_INT_EN_MASK 0x80000000L |
3227 | //UVD_SYS_INT_STATUS |
3228 | #define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0 |
3229 | #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1 |
3230 | #define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2 |
3231 | #define UVD_SYS_INT_STATUS__CXW_WR_INT__SHIFT 0x3 |
3232 | #define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6 |
3233 | #define UVD_SYS_INT_STATUS__LBSI_INT__SHIFT 0xb |
3234 | #define UVD_SYS_INT_STATUS__UDEC_INT__SHIFT 0xc |
3235 | #define UVD_SYS_INT_STATUS__SUVD_INT__SHIFT 0xf |
3236 | #define UVD_SYS_INT_STATUS__JOB_DONE_INT__SHIFT 0x10 |
3237 | #define UVD_SYS_INT_STATUS__GPCOM_INT__SHIFT 0x12 |
3238 | #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17 |
3239 | #define UVD_SYS_INT_STATUS__IDCT_INT__SHIFT 0x18 |
3240 | #define UVD_SYS_INT_STATUS__MPRD_INT__SHIFT 0x19 |
3241 | #define UVD_SYS_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b |
3242 | #define UVD_SYS_INT_STATUS__MIF_HWINT__SHIFT 0x1c |
3243 | #define UVD_SYS_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d |
3244 | #define UVD_SYS_INT_STATUS__RASCNTL_VCPU_VCODEC_INT__SHIFT 0x1e |
3245 | #define UVD_SYS_INT_STATUS__AVM_INT__SHIFT 0x1f |
3246 | #define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L |
3247 | #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L |
3248 | #define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L |
3249 | #define UVD_SYS_INT_STATUS__CXW_WR_INT_MASK 0x00000008L |
3250 | #define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L |
3251 | #define UVD_SYS_INT_STATUS__LBSI_INT_MASK 0x00000800L |
3252 | #define UVD_SYS_INT_STATUS__UDEC_INT_MASK 0x00001000L |
3253 | #define UVD_SYS_INT_STATUS__SUVD_INT_MASK 0x00008000L |
3254 | #define UVD_SYS_INT_STATUS__JOB_DONE_INT_MASK 0x00010000L |
3255 | #define UVD_SYS_INT_STATUS__GPCOM_INT_MASK 0x00040000L |
3256 | #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L |
3257 | #define UVD_SYS_INT_STATUS__IDCT_INT_MASK 0x01000000L |
3258 | #define UVD_SYS_INT_STATUS__MPRD_INT_MASK 0x02000000L |
3259 | #define UVD_SYS_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L |
3260 | #define UVD_SYS_INT_STATUS__MIF_HWINT_MASK 0x10000000L |
3261 | #define UVD_SYS_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L |
3262 | #define UVD_SYS_INT_STATUS__RASCNTL_VCPU_VCODEC_INT_MASK 0x40000000L |
3263 | #define UVD_SYS_INT_STATUS__AVM_INT_MASK 0x80000000L |
3264 | //UVD_SYS_INT_ACK |
3265 | #define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 |
3266 | #define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 |
3267 | #define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 |
3268 | #define UVD_SYS_INT_ACK__CXW_WR_ACK__SHIFT 0x3 |
3269 | #define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 |
3270 | #define UVD_SYS_INT_ACK__LBSI_ACK__SHIFT 0xb |
3271 | #define UVD_SYS_INT_ACK__UDEC_ACK__SHIFT 0xc |
3272 | #define UVD_SYS_INT_ACK__SUVD_ACK__SHIFT 0xf |
3273 | #define UVD_SYS_INT_ACK__JOB_DONE_ACK__SHIFT 0x10 |
3274 | #define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 |
3275 | #define UVD_SYS_INT_ACK__IDCT_ACK__SHIFT 0x18 |
3276 | #define UVD_SYS_INT_ACK__MPRD_ACK__SHIFT 0x19 |
3277 | #define UVD_SYS_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b |
3278 | #define UVD_SYS_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c |
3279 | #define UVD_SYS_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d |
3280 | #define UVD_SYS_INT_ACK__RASCNTL_VCPU_VCODEC_ACK__SHIFT 0x1e |
3281 | #define UVD_SYS_INT_ACK__AVM_INT_ACK__SHIFT 0x1f |
3282 | #define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L |
3283 | #define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L |
3284 | #define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L |
3285 | #define UVD_SYS_INT_ACK__CXW_WR_ACK_MASK 0x00000008L |
3286 | #define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L |
3287 | #define UVD_SYS_INT_ACK__LBSI_ACK_MASK 0x00000800L |
3288 | #define UVD_SYS_INT_ACK__UDEC_ACK_MASK 0x00001000L |
3289 | #define UVD_SYS_INT_ACK__SUVD_ACK_MASK 0x00008000L |
3290 | #define UVD_SYS_INT_ACK__JOB_DONE_ACK_MASK 0x00010000L |
3291 | #define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L |
3292 | #define UVD_SYS_INT_ACK__IDCT_ACK_MASK 0x01000000L |
3293 | #define UVD_SYS_INT_ACK__MPRD_ACK_MASK 0x02000000L |
3294 | #define UVD_SYS_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L |
3295 | #define UVD_SYS_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L |
3296 | #define UVD_SYS_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L |
3297 | #define UVD_SYS_INT_ACK__RASCNTL_VCPU_VCODEC_ACK_MASK 0x40000000L |
3298 | #define UVD_SYS_INT_ACK__AVM_INT_ACK_MASK 0x80000000L |
3299 | //UVD_JOB_DONE |
3300 | #define UVD_JOB_DONE__JOB_DONE__SHIFT 0x0 |
3301 | #define UVD_JOB_DONE__JOB_DONE_MASK 0x00000003L |
3302 | //UVD_CBUF_ID |
3303 | #define UVD_CBUF_ID__CBUF_ID__SHIFT 0x0 |
3304 | #define UVD_CBUF_ID__CBUF_ID_MASK 0xFFFFFFFFL |
3305 | //UVD_CONTEXT_ID |
3306 | #define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 |
3307 | #define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xFFFFFFFFL |
3308 | //UVD_CONTEXT_ID2 |
3309 | #define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT 0x0 |
3310 | #define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK 0xFFFFFFFFL |
3311 | //UVD_NO_OP |
3312 | #define UVD_NO_OP__NO_OP__SHIFT 0x0 |
3313 | #define UVD_NO_OP__NO_OP_MASK 0xFFFFFFFFL |
3314 | //UVD_RB_BASE_LO |
3315 | #define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 |
3316 | #define UVD_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L |
3317 | //UVD_RB_BASE_HI |
3318 | #define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 |
3319 | #define UVD_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL |
3320 | //UVD_RB_SIZE |
3321 | #define UVD_RB_SIZE__RB_SIZE__SHIFT 0x4 |
3322 | #define UVD_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L |
3323 | //UVD_RB_BASE_LO2 |
3324 | #define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6 |
3325 | #define UVD_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L |
3326 | //UVD_RB_BASE_HI2 |
3327 | #define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0 |
3328 | #define UVD_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL |
3329 | //UVD_RB_SIZE2 |
3330 | #define UVD_RB_SIZE2__RB_SIZE__SHIFT 0x4 |
3331 | #define UVD_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L |
3332 | //UVD_RB_BASE_LO3 |
3333 | #define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6 |
3334 | #define UVD_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L |
3335 | //UVD_RB_BASE_HI3 |
3336 | #define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0 |
3337 | #define UVD_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL |
3338 | //UVD_RB_SIZE3 |
3339 | #define UVD_RB_SIZE3__RB_SIZE__SHIFT 0x4 |
3340 | #define UVD_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L |
3341 | //UVD_RB_BASE_LO4 |
3342 | #define UVD_RB_BASE_LO4__RB_BASE_LO__SHIFT 0x6 |
3343 | #define UVD_RB_BASE_LO4__RB_BASE_LO_MASK 0xFFFFFFC0L |
3344 | //UVD_RB_BASE_HI4 |
3345 | #define UVD_RB_BASE_HI4__RB_BASE_HI__SHIFT 0x0 |
3346 | #define UVD_RB_BASE_HI4__RB_BASE_HI_MASK 0xFFFFFFFFL |
3347 | //UVD_RB_SIZE4 |
3348 | #define UVD_RB_SIZE4__RB_SIZE__SHIFT 0x4 |
3349 | #define UVD_RB_SIZE4__RB_SIZE_MASK 0x007FFFF0L |
3350 | //UVD_OUT_RB_BASE_LO |
3351 | #define UVD_OUT_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 |
3352 | #define UVD_OUT_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L |
3353 | //UVD_OUT_RB_BASE_HI |
3354 | #define UVD_OUT_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 |
3355 | #define UVD_OUT_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL |
3356 | //UVD_OUT_RB_SIZE |
3357 | #define UVD_OUT_RB_SIZE__RB_SIZE__SHIFT 0x4 |
3358 | #define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L |
3359 | //UVD_IOV_MAILBOX |
3360 | #define UVD_IOV_MAILBOX__MAILBOX__SHIFT 0x0 |
3361 | #define UVD_IOV_MAILBOX__MAILBOX_MASK 0xFFFFFFFFL |
3362 | //UVD_IOV_MAILBOX_RESP |
3363 | #define UVD_IOV_MAILBOX_RESP__RESP__SHIFT 0x0 |
3364 | #define UVD_IOV_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL |
3365 | //UVD_RB_ARB_CTRL |
3366 | #define UVD_RB_ARB_CTRL__SRBM_DROP__SHIFT 0x0 |
3367 | #define UVD_RB_ARB_CTRL__SRBM_DIS__SHIFT 0x1 |
3368 | #define UVD_RB_ARB_CTRL__VCPU_DROP__SHIFT 0x2 |
3369 | #define UVD_RB_ARB_CTRL__VCPU_DIS__SHIFT 0x3 |
3370 | #define UVD_RB_ARB_CTRL__RBC_DROP__SHIFT 0x4 |
3371 | #define UVD_RB_ARB_CTRL__RBC_DIS__SHIFT 0x5 |
3372 | #define UVD_RB_ARB_CTRL__FWOFLD_DROP__SHIFT 0x6 |
3373 | #define UVD_RB_ARB_CTRL__FWOFLD_DIS__SHIFT 0x7 |
3374 | #define UVD_RB_ARB_CTRL__FAST_PATH_EN__SHIFT 0x8 |
3375 | #define UVD_RB_ARB_CTRL__SRBM_DROP_MASK 0x00000001L |
3376 | #define UVD_RB_ARB_CTRL__SRBM_DIS_MASK 0x00000002L |
3377 | #define UVD_RB_ARB_CTRL__VCPU_DROP_MASK 0x00000004L |
3378 | #define UVD_RB_ARB_CTRL__VCPU_DIS_MASK 0x00000008L |
3379 | #define UVD_RB_ARB_CTRL__RBC_DROP_MASK 0x00000010L |
3380 | #define UVD_RB_ARB_CTRL__RBC_DIS_MASK 0x00000020L |
3381 | #define UVD_RB_ARB_CTRL__FWOFLD_DROP_MASK 0x00000040L |
3382 | #define UVD_RB_ARB_CTRL__FWOFLD_DIS_MASK 0x00000080L |
3383 | #define UVD_RB_ARB_CTRL__FAST_PATH_EN_MASK 0x00000100L |
3384 | //UVD_CTX_INDEX |
3385 | #define UVD_CTX_INDEX__INDEX__SHIFT 0x0 |
3386 | #define UVD_CTX_INDEX__INDEX_MASK 0x000001FFL |
3387 | //UVD_CTX_DATA |
3388 | #define UVD_CTX_DATA__DATA__SHIFT 0x0 |
3389 | #define UVD_CTX_DATA__DATA_MASK 0xFFFFFFFFL |
3390 | //UVD_CXW_WR |
3391 | #define UVD_CXW_WR__DAT__SHIFT 0x0 |
3392 | #define UVD_CXW_WR__STAT__SHIFT 0x1f |
3393 | #define UVD_CXW_WR__DAT_MASK 0x0FFFFFFFL |
3394 | #define UVD_CXW_WR__STAT_MASK 0x80000000L |
3395 | //UVD_CXW_WR_INT_ID |
3396 | #define UVD_CXW_WR_INT_ID__ID__SHIFT 0x0 |
3397 | #define UVD_CXW_WR_INT_ID__ID_MASK 0x000000FFL |
3398 | //UVD_CXW_WR_INT_CTX_ID |
3399 | #define UVD_CXW_WR_INT_CTX_ID__ID__SHIFT 0x0 |
3400 | #define UVD_CXW_WR_INT_CTX_ID__ID_MASK 0x0FFFFFFFL |
3401 | //UVD_CXW_INT_ID |
3402 | #define UVD_CXW_INT_ID__ID__SHIFT 0x0 |
3403 | #define UVD_CXW_INT_ID__ID_MASK 0x000000FFL |
3404 | //UVD_MPEG2_ERROR |
3405 | #define UVD_MPEG2_ERROR__STATUS__SHIFT 0x0 |
3406 | #define UVD_MPEG2_ERROR__STATUS_MASK 0xFFFFFFFFL |
3407 | //UVD_YBASE |
3408 | #define UVD_YBASE__DUM__SHIFT 0x0 |
3409 | #define UVD_YBASE__DUM_MASK 0xFFFFFFFFL |
3410 | //UVD_UVBASE |
3411 | #define UVD_UVBASE__DUM__SHIFT 0x0 |
3412 | #define UVD_UVBASE__DUM_MASK 0xFFFFFFFFL |
3413 | //UVD_PITCH |
3414 | #define UVD_PITCH__DUM__SHIFT 0x0 |
3415 | #define UVD_PITCH__DUM_MASK 0xFFFFFFFFL |
3416 | //UVD_WIDTH |
3417 | #define UVD_WIDTH__DUM__SHIFT 0x0 |
3418 | #define UVD_WIDTH__DUM_MASK 0xFFFFFFFFL |
3419 | //UVD_HEIGHT |
3420 | #define UVD_HEIGHT__DUM__SHIFT 0x0 |
3421 | #define UVD_HEIGHT__DUM_MASK 0xFFFFFFFFL |
3422 | //UVD_PICCOUNT |
3423 | #define UVD_PICCOUNT__DUM__SHIFT 0x0 |
3424 | #define UVD_PICCOUNT__DUM_MASK 0xFFFFFFFFL |
3425 | //UVD_MPRD_INITIAL_XY |
3426 | #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_X__SHIFT 0x0 |
3427 | #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_Y__SHIFT 0x10 |
3428 | #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_X_MASK 0x00000FFFL |
3429 | #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_Y_MASK 0x0FFF0000L |
3430 | //UVD_MPEG2_CTRL |
3431 | #define UVD_MPEG2_CTRL__EN__SHIFT 0x0 |
3432 | #define UVD_MPEG2_CTRL__TRICK_MODE__SHIFT 0x1 |
3433 | #define UVD_MPEG2_CTRL__NUM_MB_PER_JOB__SHIFT 0x10 |
3434 | #define UVD_MPEG2_CTRL__EN_MASK 0x00000001L |
3435 | #define UVD_MPEG2_CTRL__TRICK_MODE_MASK 0x00000002L |
3436 | #define UVD_MPEG2_CTRL__NUM_MB_PER_JOB_MASK 0xFFFF0000L |
3437 | //UVD_MB_CTL_BUF_BASE |
3438 | #define UVD_MB_CTL_BUF_BASE__BASE__SHIFT 0x0 |
3439 | #define UVD_MB_CTL_BUF_BASE__BASE_MASK 0xFFFFFFFFL |
3440 | //UVD_PIC_CTL_BUF_BASE |
3441 | #define UVD_PIC_CTL_BUF_BASE__BASE__SHIFT 0x0 |
3442 | #define UVD_PIC_CTL_BUF_BASE__BASE_MASK 0xFFFFFFFFL |
3443 | //UVD_DXVA_BUF_SIZE |
3444 | #define UVD_DXVA_BUF_SIZE__PIC_SIZE__SHIFT 0x0 |
3445 | #define UVD_DXVA_BUF_SIZE__MB_SIZE__SHIFT 0x10 |
3446 | #define UVD_DXVA_BUF_SIZE__PIC_SIZE_MASK 0x0000FFFFL |
3447 | #define UVD_DXVA_BUF_SIZE__MB_SIZE_MASK 0xFFFF0000L |
3448 | //UVD_SCRATCH_NP |
3449 | #define UVD_SCRATCH_NP__DATA__SHIFT 0x0 |
3450 | #define UVD_SCRATCH_NP__DATA_MASK 0xFFFFFFFFL |
3451 | //UVD_CLK_SWT_HANDSHAKE |
3452 | #define UVD_CLK_SWT_HANDSHAKE__CLK_SWT_TYPE__SHIFT 0x0 |
3453 | #define UVD_CLK_SWT_HANDSHAKE__CLK_DOMAIN_SWT__SHIFT 0x8 |
3454 | #define UVD_CLK_SWT_HANDSHAKE__CLK_SWT_TYPE_MASK 0x00000003L |
3455 | #define UVD_CLK_SWT_HANDSHAKE__CLK_DOMAIN_SWT_MASK 0x00000300L |
3456 | //UVD_GP_SCRATCH0 |
3457 | #define UVD_GP_SCRATCH0__DATA__SHIFT 0x0 |
3458 | #define UVD_GP_SCRATCH0__DATA_MASK 0xFFFFFFFFL |
3459 | //UVD_GP_SCRATCH1 |
3460 | #define UVD_GP_SCRATCH1__DATA__SHIFT 0x0 |
3461 | #define UVD_GP_SCRATCH1__DATA_MASK 0xFFFFFFFFL |
3462 | //UVD_GP_SCRATCH2 |
3463 | #define UVD_GP_SCRATCH2__DATA__SHIFT 0x0 |
3464 | #define UVD_GP_SCRATCH2__DATA_MASK 0xFFFFFFFFL |
3465 | //UVD_GP_SCRATCH3 |
3466 | #define UVD_GP_SCRATCH3__DATA__SHIFT 0x0 |
3467 | #define UVD_GP_SCRATCH3__DATA_MASK 0xFFFFFFFFL |
3468 | //UVD_GP_SCRATCH4 |
3469 | #define UVD_GP_SCRATCH4__DATA__SHIFT 0x0 |
3470 | #define UVD_GP_SCRATCH4__DATA_MASK 0xFFFFFFFFL |
3471 | //UVD_GP_SCRATCH5 |
3472 | #define UVD_GP_SCRATCH5__DATA__SHIFT 0x0 |
3473 | #define UVD_GP_SCRATCH5__DATA_MASK 0xFFFFFFFFL |
3474 | //UVD_GP_SCRATCH6 |
3475 | #define UVD_GP_SCRATCH6__DATA__SHIFT 0x0 |
3476 | #define UVD_GP_SCRATCH6__DATA_MASK 0xFFFFFFFFL |
3477 | //UVD_GP_SCRATCH7 |
3478 | #define UVD_GP_SCRATCH7__DATA__SHIFT 0x0 |
3479 | #define UVD_GP_SCRATCH7__DATA_MASK 0xFFFFFFFFL |
3480 | //UVD_GP_SCRATCH8 |
3481 | #define UVD_GP_SCRATCH8__DATA__SHIFT 0x0 |
3482 | #define UVD_GP_SCRATCH8__DATA_MASK 0xFFFFFFFFL |
3483 | //UVD_GP_SCRATCH9 |
3484 | #define UVD_GP_SCRATCH9__DATA__SHIFT 0x0 |
3485 | #define UVD_GP_SCRATCH9__DATA_MASK 0xFFFFFFFFL |
3486 | //UVD_GP_SCRATCH10 |
3487 | #define UVD_GP_SCRATCH10__DATA__SHIFT 0x0 |
3488 | #define UVD_GP_SCRATCH10__DATA_MASK 0xFFFFFFFFL |
3489 | //UVD_GP_SCRATCH11 |
3490 | #define UVD_GP_SCRATCH11__DATA__SHIFT 0x0 |
3491 | #define UVD_GP_SCRATCH11__DATA_MASK 0xFFFFFFFFL |
3492 | //UVD_GP_SCRATCH12 |
3493 | #define UVD_GP_SCRATCH12__DATA__SHIFT 0x0 |
3494 | #define UVD_GP_SCRATCH12__DATA_MASK 0xFFFFFFFFL |
3495 | //UVD_GP_SCRATCH13 |
3496 | #define UVD_GP_SCRATCH13__DATA__SHIFT 0x0 |
3497 | #define UVD_GP_SCRATCH13__DATA_MASK 0xFFFFFFFFL |
3498 | //UVD_GP_SCRATCH14 |
3499 | #define UVD_GP_SCRATCH14__DATA__SHIFT 0x0 |
3500 | #define UVD_GP_SCRATCH14__DATA_MASK 0xFFFFFFFFL |
3501 | //UVD_GP_SCRATCH15 |
3502 | #define UVD_GP_SCRATCH15__DATA__SHIFT 0x0 |
3503 | #define UVD_GP_SCRATCH15__DATA_MASK 0xFFFFFFFFL |
3504 | //UVD_GP_SCRATCH16 |
3505 | #define UVD_GP_SCRATCH16__DATA__SHIFT 0x0 |
3506 | #define UVD_GP_SCRATCH16__DATA_MASK 0xFFFFFFFFL |
3507 | //UVD_GP_SCRATCH17 |
3508 | #define UVD_GP_SCRATCH17__DATA__SHIFT 0x0 |
3509 | #define UVD_GP_SCRATCH17__DATA_MASK 0xFFFFFFFFL |
3510 | //UVD_GP_SCRATCH18 |
3511 | #define UVD_GP_SCRATCH18__DATA__SHIFT 0x0 |
3512 | #define UVD_GP_SCRATCH18__DATA_MASK 0xFFFFFFFFL |
3513 | //UVD_GP_SCRATCH19 |
3514 | #define UVD_GP_SCRATCH19__DATA__SHIFT 0x0 |
3515 | #define UVD_GP_SCRATCH19__DATA_MASK 0xFFFFFFFFL |
3516 | //UVD_GP_SCRATCH20 |
3517 | #define UVD_GP_SCRATCH20__DATA__SHIFT 0x0 |
3518 | #define UVD_GP_SCRATCH20__DATA_MASK 0xFFFFFFFFL |
3519 | //UVD_GP_SCRATCH21 |
3520 | #define UVD_GP_SCRATCH21__DATA__SHIFT 0x0 |
3521 | #define UVD_GP_SCRATCH21__DATA_MASK 0xFFFFFFFFL |
3522 | //UVD_GP_SCRATCH22 |
3523 | #define UVD_GP_SCRATCH22__DATA__SHIFT 0x0 |
3524 | #define UVD_GP_SCRATCH22__DATA_MASK 0xFFFFFFFFL |
3525 | //UVD_GP_SCRATCH23 |
3526 | #define UVD_GP_SCRATCH23__DATA__SHIFT 0x0 |
3527 | #define UVD_GP_SCRATCH23__DATA_MASK 0xFFFFFFFFL |
3528 | //UVD_AUDIO_RB_BASE_LO |
3529 | #define UVD_AUDIO_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 |
3530 | #define UVD_AUDIO_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L |
3531 | //UVD_AUDIO_RB_BASE_HI |
3532 | #define UVD_AUDIO_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 |
3533 | #define UVD_AUDIO_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL |
3534 | //UVD_AUDIO_RB_SIZE |
3535 | #define UVD_AUDIO_RB_SIZE__RB_SIZE__SHIFT 0x4 |
3536 | #define UVD_AUDIO_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L |
3537 | //UVD_VCPU_INT_STATUS2 |
3538 | #define UVD_VCPU_INT_STATUS2__SW_RB6_INT__SHIFT 0x0 |
3539 | #define UVD_VCPU_INT_STATUS2__RASCNTL_VCPU_VCODEC_INT__SHIFT 0x15 |
3540 | #define UVD_VCPU_INT_STATUS2__SW_RB6_INT_MASK 0x00000001L |
3541 | #define UVD_VCPU_INT_STATUS2__RASCNTL_VCPU_VCODEC_INT_MASK 0x00200000L |
3542 | //UVD_VCPU_INT_ACK2 |
3543 | #define UVD_VCPU_INT_ACK2__SW_RB6_INT_ACK__SHIFT 0x0 |
3544 | #define UVD_VCPU_INT_ACK2__RASCNTL_VCPU_VCODEC_ACK__SHIFT 0x16 |
3545 | #define UVD_VCPU_INT_ACK2__SW_RB6_INT_ACK_MASK 0x00000001L |
3546 | #define UVD_VCPU_INT_ACK2__RASCNTL_VCPU_VCODEC_ACK_MASK 0x00400000L |
3547 | //UVD_VCPU_INT_EN2 |
3548 | #define UVD_VCPU_INT_EN2__SW_RB6_INT_EN__SHIFT 0x0 |
3549 | #define UVD_VCPU_INT_EN2__RASCNTL_VCPU_VCODEC_EN__SHIFT 0x1 |
3550 | #define UVD_VCPU_INT_EN2__SW_RB6_INT_EN_MASK 0x00000001L |
3551 | #define UVD_VCPU_INT_EN2__RASCNTL_VCPU_VCODEC_EN_MASK 0x00000002L |
3552 | //UVD_SUVD_CGC_STATUS2 |
3553 | #define UVD_SUVD_CGC_STATUS2__SMPA_VCLK__SHIFT 0x0 |
3554 | #define UVD_SUVD_CGC_STATUS2__SMPA_DCLK__SHIFT 0x1 |
3555 | #define UVD_SUVD_CGC_STATUS2__MPBE1_DCLK__SHIFT 0x3 |
3556 | #define UVD_SUVD_CGC_STATUS2__SIT_AV1_DCLK__SHIFT 0x4 |
3557 | #define UVD_SUVD_CGC_STATUS2__SDB_AV1_DCLK__SHIFT 0x5 |
3558 | #define UVD_SUVD_CGC_STATUS2__MPC1_DCLK__SHIFT 0x6 |
3559 | #define UVD_SUVD_CGC_STATUS2__MPC1_SCLK__SHIFT 0x7 |
3560 | #define UVD_SUVD_CGC_STATUS2__MPC1_VCLK__SHIFT 0x8 |
3561 | #define UVD_SUVD_CGC_STATUS2__SRE_AV1_ENC_DCLK__SHIFT 0x9 |
3562 | #define UVD_SUVD_CGC_STATUS2__CDEFE_DCLK__SHIFT 0xa |
3563 | #define UVD_SUVD_CGC_STATUS2__SIT0_DCLK__SHIFT 0xb |
3564 | #define UVD_SUVD_CGC_STATUS2__SIT1_DCLK__SHIFT 0xc |
3565 | #define UVD_SUVD_CGC_STATUS2__SIT2_DCLK__SHIFT 0xd |
3566 | #define UVD_SUVD_CGC_STATUS2__FBC_PCLK__SHIFT 0x1c |
3567 | #define UVD_SUVD_CGC_STATUS2__FBC_CCLK__SHIFT 0x1d |
3568 | #define UVD_SUVD_CGC_STATUS2__SMPA_VCLK_MASK 0x00000001L |
3569 | #define UVD_SUVD_CGC_STATUS2__SMPA_DCLK_MASK 0x00000002L |
3570 | #define UVD_SUVD_CGC_STATUS2__MPBE1_DCLK_MASK 0x00000008L |
3571 | #define UVD_SUVD_CGC_STATUS2__SIT_AV1_DCLK_MASK 0x00000010L |
3572 | #define UVD_SUVD_CGC_STATUS2__SDB_AV1_DCLK_MASK 0x00000020L |
3573 | #define UVD_SUVD_CGC_STATUS2__MPC1_DCLK_MASK 0x00000040L |
3574 | #define UVD_SUVD_CGC_STATUS2__MPC1_SCLK_MASK 0x00000080L |
3575 | #define UVD_SUVD_CGC_STATUS2__MPC1_VCLK_MASK 0x00000100L |
3576 | #define UVD_SUVD_CGC_STATUS2__SRE_AV1_ENC_DCLK_MASK 0x00000200L |
3577 | #define UVD_SUVD_CGC_STATUS2__CDEFE_DCLK_MASK 0x00000400L |
3578 | #define UVD_SUVD_CGC_STATUS2__SIT0_DCLK_MASK 0x00000800L |
3579 | #define UVD_SUVD_CGC_STATUS2__SIT1_DCLK_MASK 0x00001000L |
3580 | #define UVD_SUVD_CGC_STATUS2__SIT2_DCLK_MASK 0x00002000L |
3581 | #define UVD_SUVD_CGC_STATUS2__FBC_PCLK_MASK 0x10000000L |
3582 | #define UVD_SUVD_CGC_STATUS2__FBC_CCLK_MASK 0x20000000L |
3583 | //UVD_SUVD_INT_STATUS2 |
3584 | #define UVD_SUVD_INT_STATUS2__SMPA_FUNC_INT__SHIFT 0x0 |
3585 | #define UVD_SUVD_INT_STATUS2__SMPA_ERR_INT__SHIFT 0x5 |
3586 | #define UVD_SUVD_INT_STATUS2__SDB_AV1_FUNC_INT__SHIFT 0x6 |
3587 | #define UVD_SUVD_INT_STATUS2__SDB_AV1_ERR_INT__SHIFT 0xb |
3588 | #define UVD_SUVD_INT_STATUS2__SMPA_FUNC_INT_MASK 0x0000001FL |
3589 | #define UVD_SUVD_INT_STATUS2__SMPA_ERR_INT_MASK 0x00000020L |
3590 | #define UVD_SUVD_INT_STATUS2__SDB_AV1_FUNC_INT_MASK 0x000007C0L |
3591 | #define UVD_SUVD_INT_STATUS2__SDB_AV1_ERR_INT_MASK 0x00000800L |
3592 | //UVD_SUVD_INT_EN2 |
3593 | #define UVD_SUVD_INT_EN2__SMPA_FUNC_INT_EN__SHIFT 0x0 |
3594 | #define UVD_SUVD_INT_EN2__SMPA_ERR_INT_EN__SHIFT 0x5 |
3595 | #define UVD_SUVD_INT_EN2__SDB_AV1_FUNC_INT_EN__SHIFT 0x6 |
3596 | #define UVD_SUVD_INT_EN2__SDB_AV1_ERR_INT_EN__SHIFT 0xb |
3597 | #define UVD_SUVD_INT_EN2__SMPA_FUNC_INT_EN_MASK 0x0000001FL |
3598 | #define UVD_SUVD_INT_EN2__SMPA_ERR_INT_EN_MASK 0x00000020L |
3599 | #define UVD_SUVD_INT_EN2__SDB_AV1_FUNC_INT_EN_MASK 0x000007C0L |
3600 | #define UVD_SUVD_INT_EN2__SDB_AV1_ERR_INT_EN_MASK 0x00000800L |
3601 | //UVD_SUVD_INT_ACK2 |
3602 | #define UVD_SUVD_INT_ACK2__SMPA_FUNC_INT_ACK__SHIFT 0x0 |
3603 | #define UVD_SUVD_INT_ACK2__SMPA_ERR_INT_ACK__SHIFT 0x5 |
3604 | #define UVD_SUVD_INT_ACK2__SDB_AV1_FUNC_INT_ACK__SHIFT 0x6 |
3605 | #define UVD_SUVD_INT_ACK2__SDB_AV1_ERR_INT_ACK__SHIFT 0xb |
3606 | #define UVD_SUVD_INT_ACK2__SMPA_FUNC_INT_ACK_MASK 0x0000001FL |
3607 | #define UVD_SUVD_INT_ACK2__SMPA_ERR_INT_ACK_MASK 0x00000020L |
3608 | #define UVD_SUVD_INT_ACK2__SDB_AV1_FUNC_INT_ACK_MASK 0x000007C0L |
3609 | #define UVD_SUVD_INT_ACK2__SDB_AV1_ERR_INT_ACK_MASK 0x00000800L |
3610 | //UVD_STATUS |
3611 | #define UVD_STATUS__RBC_BUSY__SHIFT 0x0 |
3612 | #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 |
3613 | #define UVD_STATUS__FILL_0__SHIFT 0x8 |
3614 | #define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10 |
3615 | #define UVD_STATUS__FILL_1__SHIFT 0x12 |
3616 | #define UVD_STATUS__SYS_GPCOM_REQ__SHIFT 0x1f |
3617 | #define UVD_STATUS__RBC_BUSY_MASK 0x00000001L |
3618 | #define UVD_STATUS__VCPU_REPORT_MASK 0x000000FEL |
3619 | #define UVD_STATUS__FILL_0_MASK 0x0000FF00L |
3620 | #define UVD_STATUS__RBC_ACCESS_GPCOM_MASK 0x00010000L |
3621 | #define UVD_STATUS__FILL_1_MASK 0x7FFC0000L |
3622 | #define UVD_STATUS__SYS_GPCOM_REQ_MASK 0x80000000L |
3623 | //UVD_ENC_PIPE_BUSY |
3624 | #define UVD_ENC_PIPE_BUSY__IME_BUSY__SHIFT 0x0 |
3625 | #define UVD_ENC_PIPE_BUSY__SMP_BUSY__SHIFT 0x1 |
3626 | #define UVD_ENC_PIPE_BUSY__SIT_BUSY__SHIFT 0x2 |
3627 | #define UVD_ENC_PIPE_BUSY__SDB_BUSY__SHIFT 0x3 |
3628 | #define UVD_ENC_PIPE_BUSY__ENT_BUSY__SHIFT 0x4 |
3629 | #define 0x5 |
3630 | #define UVD_ENC_PIPE_BUSY__LCM_BUSY__SHIFT 0x6 |
3631 | #define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x7 |
3632 | #define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x8 |
3633 | #define UVD_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY__SHIFT 0x9 |
3634 | #define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0xa |
3635 | #define UVD_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY__SHIFT 0xb |
3636 | #define UVD_ENC_PIPE_BUSY__EFC_BUSY__SHIFT 0xc |
3637 | #define UVD_ENC_PIPE_BUSY__MDM_PPU_BUSY__SHIFT 0xd |
3638 | #define UVD_ENC_PIPE_BUSY__MIF_AUTODMA_BUSY__SHIFT 0xe |
3639 | #define UVD_ENC_PIPE_BUSY__CDEFE_BUSY__SHIFT 0xf |
3640 | #define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0x10 |
3641 | #define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0x11 |
3642 | #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0x12 |
3643 | #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0x13 |
3644 | #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0x14 |
3645 | #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0x15 |
3646 | #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x16 |
3647 | #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x17 |
3648 | #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x18 |
3649 | #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x19 |
3650 | #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x1a |
3651 | #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x1b |
3652 | #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x1c |
3653 | #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY__SHIFT 0x1d |
3654 | #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY__SHIFT 0x1e |
3655 | #define UVD_ENC_PIPE_BUSY__SAOE_BUSY__SHIFT 0x1f |
3656 | #define UVD_ENC_PIPE_BUSY__IME_BUSY_MASK 0x00000001L |
3657 | #define UVD_ENC_PIPE_BUSY__SMP_BUSY_MASK 0x00000002L |
3658 | #define UVD_ENC_PIPE_BUSY__SIT_BUSY_MASK 0x00000004L |
3659 | #define UVD_ENC_PIPE_BUSY__SDB_BUSY_MASK 0x00000008L |
3660 | #define UVD_ENC_PIPE_BUSY__ENT_BUSY_MASK 0x00000010L |
3661 | #define 0x00000020L |
3662 | #define UVD_ENC_PIPE_BUSY__LCM_BUSY_MASK 0x00000040L |
3663 | #define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000080L |
3664 | #define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000100L |
3665 | #define UVD_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY_MASK 0x00000200L |
3666 | #define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000400L |
3667 | #define UVD_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY_MASK 0x00000800L |
3668 | #define UVD_ENC_PIPE_BUSY__EFC_BUSY_MASK 0x00001000L |
3669 | #define UVD_ENC_PIPE_BUSY__MDM_PPU_BUSY_MASK 0x00002000L |
3670 | #define UVD_ENC_PIPE_BUSY__MIF_AUTODMA_BUSY_MASK 0x00004000L |
3671 | #define UVD_ENC_PIPE_BUSY__CDEFE_BUSY_MASK 0x00008000L |
3672 | #define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00010000L |
3673 | #define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00020000L |
3674 | #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00040000L |
3675 | #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00080000L |
3676 | #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00100000L |
3677 | #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00200000L |
3678 | #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00400000L |
3679 | #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00800000L |
3680 | #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x01000000L |
3681 | #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x02000000L |
3682 | #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x04000000L |
3683 | #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x08000000L |
3684 | #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x10000000L |
3685 | #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY_MASK 0x20000000L |
3686 | #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY_MASK 0x40000000L |
3687 | #define UVD_ENC_PIPE_BUSY__SAOE_BUSY_MASK 0x80000000L |
3688 | //UVD_FW_POWER_STATUS |
3689 | #define UVD_FW_POWER_STATUS__UVDF_PWR_OFF__SHIFT 0x0 |
3690 | #define UVD_FW_POWER_STATUS__UVDTC_PWR_OFF__SHIFT 0x1 |
3691 | #define UVD_FW_POWER_STATUS__UVDB_PWR_OFF__SHIFT 0x2 |
3692 | #define UVD_FW_POWER_STATUS__UVDTA_PWR_OFF__SHIFT 0x3 |
3693 | #define UVD_FW_POWER_STATUS__UVDTD_PWR_OFF__SHIFT 0x4 |
3694 | #define UVD_FW_POWER_STATUS__UVDTE_PWR_OFF__SHIFT 0x5 |
3695 | #define UVD_FW_POWER_STATUS__UVDE_PWR_OFF__SHIFT 0x6 |
3696 | #define UVD_FW_POWER_STATUS__UVDAB_PWR_OFF__SHIFT 0x7 |
3697 | #define UVD_FW_POWER_STATUS__UVDTB_PWR_OFF__SHIFT 0x8 |
3698 | #define UVD_FW_POWER_STATUS__UVDNA_PWR_OFF__SHIFT 0x9 |
3699 | #define UVD_FW_POWER_STATUS__UVDF_PWR_OFF_MASK 0x00000001L |
3700 | #define UVD_FW_POWER_STATUS__UVDTC_PWR_OFF_MASK 0x00000002L |
3701 | #define UVD_FW_POWER_STATUS__UVDB_PWR_OFF_MASK 0x00000004L |
3702 | #define UVD_FW_POWER_STATUS__UVDTA_PWR_OFF_MASK 0x00000008L |
3703 | #define UVD_FW_POWER_STATUS__UVDTD_PWR_OFF_MASK 0x00000010L |
3704 | #define UVD_FW_POWER_STATUS__UVDTE_PWR_OFF_MASK 0x00000020L |
3705 | #define UVD_FW_POWER_STATUS__UVDE_PWR_OFF_MASK 0x00000040L |
3706 | #define UVD_FW_POWER_STATUS__UVDAB_PWR_OFF_MASK 0x00000080L |
3707 | #define UVD_FW_POWER_STATUS__UVDTB_PWR_OFF_MASK 0x00000100L |
3708 | #define UVD_FW_POWER_STATUS__UVDNA_PWR_OFF_MASK 0x00000200L |
3709 | //UVD_CNTL |
3710 | #define UVD_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11 |
3711 | #define UVD_CNTL__SUVD_EN__SHIFT 0x13 |
3712 | #define UVD_CNTL__CABAC_MB_ACC__SHIFT 0x1c |
3713 | #define UVD_CNTL__LRBBM_SAFE_SYNC_DIS__SHIFT 0x1f |
3714 | #define UVD_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x00020000L |
3715 | #define UVD_CNTL__SUVD_EN_MASK 0x00080000L |
3716 | #define UVD_CNTL__CABAC_MB_ACC_MASK 0x10000000L |
3717 | #define UVD_CNTL__LRBBM_SAFE_SYNC_DIS_MASK 0x80000000L |
3718 | //UVD_SOFT_RESET |
3719 | #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 |
3720 | #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 |
3721 | #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 |
3722 | #define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 |
3723 | #define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 |
3724 | #define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 |
3725 | #define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 |
3726 | #define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 |
3727 | #define UVD_SOFT_RESET__EFC_SOFT_RESET__SHIFT 0x9 |
3728 | #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa |
3729 | #define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb |
3730 | #define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc |
3731 | #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd |
3732 | #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe |
3733 | #define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf |
3734 | #define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 |
3735 | #define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 |
3736 | #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 |
3737 | #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 |
3738 | #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 |
3739 | #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 |
3740 | #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 |
3741 | #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17 |
3742 | #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18 |
3743 | #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19 |
3744 | #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a |
3745 | #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b |
3746 | #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c |
3747 | #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d |
3748 | #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e |
3749 | #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f |
3750 | #define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L |
3751 | #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L |
3752 | #define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L |
3753 | #define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L |
3754 | #define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L |
3755 | #define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L |
3756 | #define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L |
3757 | #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L |
3758 | #define UVD_SOFT_RESET__EFC_SOFT_RESET_MASK 0x00000200L |
3759 | #define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L |
3760 | #define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x00000800L |
3761 | #define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x00001000L |
3762 | #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L |
3763 | #define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L |
3764 | #define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L |
3765 | #define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L |
3766 | #define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x00020000L |
3767 | #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x00040000L |
3768 | #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x00080000L |
3769 | #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x00100000L |
3770 | #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x00200000L |
3771 | #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x00400000L |
3772 | #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x00800000L |
3773 | #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x01000000L |
3774 | #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x02000000L |
3775 | #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x04000000L |
3776 | #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x08000000L |
3777 | #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L |
3778 | #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000L |
3779 | #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000L |
3780 | #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000L |
3781 | //UVD_SOFT_RESET2 |
3782 | #define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 |
3783 | #define UVD_SOFT_RESET2__PPU_SOFT_RESET__SHIFT 0x1 |
3784 | #define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS__SHIFT 0x10 |
3785 | #define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS__SHIFT 0x11 |
3786 | #define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L |
3787 | #define UVD_SOFT_RESET2__PPU_SOFT_RESET_MASK 0x00000002L |
3788 | #define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS_MASK 0x00010000L |
3789 | #define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS_MASK 0x00020000L |
3790 | //UVD_MMSCH_SOFT_RESET |
3791 | #define UVD_MMSCH_SOFT_RESET__MMSCH_RESET__SHIFT 0x0 |
3792 | #define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x1 |
3793 | #define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK__SHIFT 0x1f |
3794 | #define UVD_MMSCH_SOFT_RESET__MMSCH_RESET_MASK 0x00000001L |
3795 | #define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000002L |
3796 | #define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK_MASK 0x80000000L |
3797 | //UVD_WIG_CTRL |
3798 | #define UVD_WIG_CTRL__AVM_SOFT_RESET__SHIFT 0x0 |
3799 | #define UVD_WIG_CTRL__ACAP_SOFT_RESET__SHIFT 0x1 |
3800 | #define UVD_WIG_CTRL__WIG_SOFT_RESET__SHIFT 0x2 |
3801 | #define UVD_WIG_CTRL__WIG_REGCLK_FORCE_ON__SHIFT 0x3 |
3802 | #define UVD_WIG_CTRL__AVM_REGCLK_FORCE_ON__SHIFT 0x4 |
3803 | #define UVD_WIG_CTRL__AVM_SOFT_RESET_MASK 0x00000001L |
3804 | #define UVD_WIG_CTRL__ACAP_SOFT_RESET_MASK 0x00000002L |
3805 | #define UVD_WIG_CTRL__WIG_SOFT_RESET_MASK 0x00000004L |
3806 | #define UVD_WIG_CTRL__WIG_REGCLK_FORCE_ON_MASK 0x00000008L |
3807 | #define UVD_WIG_CTRL__AVM_REGCLK_FORCE_ON_MASK 0x00000010L |
3808 | //UVD_CGC_STATUS |
3809 | #define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 |
3810 | #define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 |
3811 | #define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 |
3812 | #define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 |
3813 | #define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 |
3814 | #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 |
3815 | #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 |
3816 | #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 |
3817 | #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 |
3818 | #define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 |
3819 | #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa |
3820 | #define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb |
3821 | #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc |
3822 | #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd |
3823 | #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe |
3824 | #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf |
3825 | #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 |
3826 | #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 |
3827 | #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 |
3828 | #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 |
3829 | #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 |
3830 | #define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 |
3831 | #define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 |
3832 | #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 |
3833 | #define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 |
3834 | #define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 |
3835 | #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a |
3836 | #define UVD_CGC_STATUS__MMSCH_SCLK__SHIFT 0x1b |
3837 | #define UVD_CGC_STATUS__MMSCH_VCLK__SHIFT 0x1c |
3838 | #define UVD_CGC_STATUS__ALL_ENC_ACTIVE__SHIFT 0x1d |
3839 | #define UVD_CGC_STATUS__LRBBM_DCLK__SHIFT 0x1e |
3840 | #define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f |
3841 | #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L |
3842 | #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L |
3843 | #define UVD_CGC_STATUS__SYS_VCLK_MASK 0x00000004L |
3844 | #define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x00000008L |
3845 | #define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L |
3846 | #define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x00000020L |
3847 | #define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L |
3848 | #define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x00000080L |
3849 | #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x00000100L |
3850 | #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L |
3851 | #define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L |
3852 | #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L |
3853 | #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L |
3854 | #define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x00002000L |
3855 | #define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x00004000L |
3856 | #define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x00008000L |
3857 | #define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x00010000L |
3858 | #define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L |
3859 | #define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L |
3860 | #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L |
3861 | #define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L |
3862 | #define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x00200000L |
3863 | #define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x00400000L |
3864 | #define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L |
3865 | #define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L |
3866 | #define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x02000000L |
3867 | #define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x04000000L |
3868 | #define UVD_CGC_STATUS__MMSCH_SCLK_MASK 0x08000000L |
3869 | #define UVD_CGC_STATUS__MMSCH_VCLK_MASK 0x10000000L |
3870 | #define UVD_CGC_STATUS__ALL_ENC_ACTIVE_MASK 0x20000000L |
3871 | #define UVD_CGC_STATUS__LRBBM_DCLK_MASK 0x40000000L |
3872 | #define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000L |
3873 | //UVD_CGC_UDEC_STATUS |
3874 | #define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 |
3875 | #define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 |
3876 | #define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 |
3877 | #define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 |
3878 | #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 |
3879 | #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 |
3880 | #define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 |
3881 | #define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 |
3882 | #define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 |
3883 | #define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 |
3884 | #define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa |
3885 | #define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb |
3886 | #define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc |
3887 | #define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd |
3888 | #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe |
3889 | #define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x00000001L |
3890 | #define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x00000002L |
3891 | #define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x00000004L |
3892 | #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x00000008L |
3893 | #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x00000010L |
3894 | #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x00000020L |
3895 | #define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x00000040L |
3896 | #define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x00000080L |
3897 | #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x00000100L |
3898 | #define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x00000200L |
3899 | #define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x00000400L |
3900 | #define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x00000800L |
3901 | #define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x00001000L |
3902 | #define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L |
3903 | #define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x00004000L |
3904 | //UVD_SUVD_CGC_STATUS |
3905 | #define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0 |
3906 | #define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1 |
3907 | #define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2 |
3908 | #define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3 |
3909 | #define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4 |
3910 | #define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5 |
3911 | #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 |
3912 | #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7 |
3913 | #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8 |
3914 | #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9 |
3915 | #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa |
3916 | #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb |
3917 | #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc |
3918 | #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd |
3919 | #define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe |
3920 | #define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf |
3921 | #define UVD_SUVD_CGC_STATUS__ENT_DCLK__SHIFT 0x10 |
3922 | #define UVD_SUVD_CGC_STATUS__IME_DCLK__SHIFT 0x11 |
3923 | #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT 0x12 |
3924 | #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK__SHIFT 0x13 |
3925 | #define UVD_SUVD_CGC_STATUS__SITE_DCLK__SHIFT 0x14 |
3926 | #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT 0x15 |
3927 | #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT 0x16 |
3928 | #define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK__SHIFT 0x17 |
3929 | #define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK__SHIFT 0x18 |
3930 | #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK__SHIFT 0x19 |
3931 | #define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK__SHIFT 0x1a |
3932 | #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT 0x1b |
3933 | #define UVD_SUVD_CGC_STATUS__EFC_DCLK__SHIFT 0x1c |
3934 | #define UVD_SUVD_CGC_STATUS__SAOE_DCLK__SHIFT 0x1d |
3935 | #define UVD_SUVD_CGC_STATUS__SRE_AV1_VCLK__SHIFT 0x1e |
3936 | #define UVD_SUVD_CGC_STATUS__SCM_AV1_DCLK__SHIFT 0x1f |
3937 | #define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x00000001L |
3938 | #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x00000002L |
3939 | #define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x00000004L |
3940 | #define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x00000008L |
3941 | #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x00000010L |
3942 | #define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x00000020L |
3943 | #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x00000040L |
3944 | #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L |
3945 | #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x00000100L |
3946 | #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x00000200L |
3947 | #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x00000400L |
3948 | #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x00000800L |
3949 | #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x00001000L |
3950 | #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x00002000L |
3951 | #define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x00004000L |
3952 | #define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x00008000L |
3953 | #define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK 0x00010000L |
3954 | #define UVD_SUVD_CGC_STATUS__IME_DCLK_MASK 0x00020000L |
3955 | #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK_MASK 0x00040000L |
3956 | #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK 0x00080000L |
3957 | #define UVD_SUVD_CGC_STATUS__SITE_DCLK_MASK 0x00100000L |
3958 | #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK_MASK 0x00200000L |
3959 | #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK_MASK 0x00400000L |
3960 | #define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK_MASK 0x00800000L |
3961 | #define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK_MASK 0x01000000L |
3962 | #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK 0x02000000L |
3963 | #define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK_MASK 0x04000000L |
3964 | #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK 0x08000000L |
3965 | #define UVD_SUVD_CGC_STATUS__EFC_DCLK_MASK 0x10000000L |
3966 | #define UVD_SUVD_CGC_STATUS__SAOE_DCLK_MASK 0x20000000L |
3967 | #define UVD_SUVD_CGC_STATUS__SRE_AV1_VCLK_MASK 0x40000000L |
3968 | #define UVD_SUVD_CGC_STATUS__SCM_AV1_DCLK_MASK 0x80000000L |
3969 | //UVD_GPCOM_VCPU_CMD |
3970 | #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 |
3971 | #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 |
3972 | #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f |
3973 | #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L |
3974 | #define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7FFFFFFEL |
3975 | #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L |
3976 | |
3977 | |
3978 | // addressBlock: uvd0_ecpudec |
3979 | //UVD_VCPU_CACHE_OFFSET0 |
3980 | #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 |
3981 | #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x001FFFFFL |
3982 | //UVD_VCPU_CACHE_SIZE0 |
3983 | #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 |
3984 | #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001FFFFFL |
3985 | //UVD_VCPU_CACHE_OFFSET1 |
3986 | #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 |
3987 | #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x001FFFFFL |
3988 | //UVD_VCPU_CACHE_SIZE1 |
3989 | #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 |
3990 | #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001FFFFFL |
3991 | //UVD_VCPU_CACHE_OFFSET2 |
3992 | #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 |
3993 | #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x001FFFFFL |
3994 | //UVD_VCPU_CACHE_SIZE2 |
3995 | #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 |
3996 | #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL |
3997 | //UVD_VCPU_CACHE_OFFSET3 |
3998 | #define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3__SHIFT 0x0 |
3999 | #define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3_MASK 0x001FFFFFL |
4000 | //UVD_VCPU_CACHE_SIZE3 |
4001 | #define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3__SHIFT 0x0 |
4002 | #define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3_MASK 0x001FFFFFL |
4003 | //UVD_VCPU_CACHE_OFFSET4 |
4004 | #define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4__SHIFT 0x0 |
4005 | #define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4_MASK 0x001FFFFFL |
4006 | //UVD_VCPU_CACHE_SIZE4 |
4007 | #define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4__SHIFT 0x0 |
4008 | #define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4_MASK 0x001FFFFFL |
4009 | //UVD_VCPU_CACHE_OFFSET5 |
4010 | #define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5__SHIFT 0x0 |
4011 | #define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5_MASK 0x001FFFFFL |
4012 | //UVD_VCPU_CACHE_SIZE5 |
4013 | #define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5__SHIFT 0x0 |
4014 | #define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK 0x001FFFFFL |
4015 | //UVD_VCPU_CACHE_OFFSET6 |
4016 | #define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6__SHIFT 0x0 |
4017 | #define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6_MASK 0x001FFFFFL |
4018 | //UVD_VCPU_CACHE_SIZE6 |
4019 | #define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6__SHIFT 0x0 |
4020 | #define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6_MASK 0x001FFFFFL |
4021 | //UVD_VCPU_CACHE_OFFSET7 |
4022 | #define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7__SHIFT 0x0 |
4023 | #define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7_MASK 0x001FFFFFL |
4024 | //UVD_VCPU_CACHE_SIZE7 |
4025 | #define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7__SHIFT 0x0 |
4026 | #define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7_MASK 0x001FFFFFL |
4027 | //UVD_VCPU_CACHE_OFFSET8 |
4028 | #define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8__SHIFT 0x0 |
4029 | #define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8_MASK 0x001FFFFFL |
4030 | //UVD_VCPU_CACHE_SIZE8 |
4031 | #define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8__SHIFT 0x0 |
4032 | #define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8_MASK 0x001FFFFFL |
4033 | //UVD_VCPU_NONCACHE_OFFSET0 |
4034 | #define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0__SHIFT 0x0 |
4035 | #define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0_MASK 0x01FFFFFFL |
4036 | //UVD_VCPU_NONCACHE_SIZE0 |
4037 | #define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0__SHIFT 0x0 |
4038 | #define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0_MASK 0x001FFFFFL |
4039 | //UVD_VCPU_NONCACHE_OFFSET1 |
4040 | #define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1__SHIFT 0x0 |
4041 | #define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1_MASK 0x01FFFFFFL |
4042 | //UVD_VCPU_NONCACHE_SIZE1 |
4043 | #define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1__SHIFT 0x0 |
4044 | #define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1_MASK 0x001FFFFFL |
4045 | //UVD_VCPU_CNTL |
4046 | #define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 |
4047 | #define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 |
4048 | #define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 |
4049 | #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 |
4050 | #define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 |
4051 | #define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 |
4052 | #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa |
4053 | #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb |
4054 | #define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 |
4055 | #define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 |
4056 | #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 |
4057 | #define UVD_VCPU_CNTL__BLK_RST__SHIFT 0x1c |
4058 | #define UVD_VCPU_CNTL__RUNSTALL__SHIFT 0x1d |
4059 | #define UVD_VCPU_CNTL__SRE_CMDIF_DRST__SHIFT 0x1e |
4060 | #define UVD_VCPU_CNTL__SRE_CMDIF_VRST__SHIFT 0x1f |
4061 | #define UVD_VCPU_CNTL__IRQ_ERR_MASK 0x0000000FL |
4062 | #define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x00000020L |
4063 | #define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x00000040L |
4064 | #define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00000080L |
4065 | #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x00000100L |
4066 | #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L |
4067 | #define UVD_VCPU_CNTL__TRCE_EN_MASK 0x00000400L |
4068 | #define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x00001800L |
4069 | #define UVD_VCPU_CNTL__JTAG_EN_MASK 0x00010000L |
4070 | #define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x00040000L |
4071 | #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L |
4072 | #define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L |
4073 | #define UVD_VCPU_CNTL__RUNSTALL_MASK 0x20000000L |
4074 | #define UVD_VCPU_CNTL__SRE_CMDIF_DRST_MASK 0x40000000L |
4075 | #define UVD_VCPU_CNTL__SRE_CMDIF_VRST_MASK 0x80000000L |
4076 | //UVD_VCPU_PRID |
4077 | #define UVD_VCPU_PRID__PRID__SHIFT 0x0 |
4078 | #define UVD_VCPU_PRID__PRID_MASK 0x0000FFFFL |
4079 | //UVD_VCPU_TRCE |
4080 | #define UVD_VCPU_TRCE__PC__SHIFT 0x0 |
4081 | #define UVD_VCPU_TRCE__PC_MASK 0x0FFFFFFFL |
4082 | //UVD_VCPU_TRCE_RD |
4083 | #define UVD_VCPU_TRCE_RD__DATA__SHIFT 0x0 |
4084 | #define UVD_VCPU_TRCE_RD__DATA_MASK 0xFFFFFFFFL |
4085 | //UVD_VCPU_IND_INDEX |
4086 | #define UVD_VCPU_IND_INDEX__INDEX__SHIFT 0x0 |
4087 | #define UVD_VCPU_IND_INDEX__INDEX_MASK 0x000001FFL |
4088 | //UVD_VCPU_IND_DATA |
4089 | #define UVD_VCPU_IND_DATA__DATA__SHIFT 0x0 |
4090 | #define UVD_VCPU_IND_DATA__DATA_MASK 0xFFFFFFFFL |
4091 | |
4092 | |
4093 | // addressBlock: uvd0_uvd_mpcdec |
4094 | //UVD_MP_SWAP_CNTL |
4095 | #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 |
4096 | #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 |
4097 | #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 |
4098 | #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 |
4099 | #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 |
4100 | #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa |
4101 | #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc |
4102 | #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe |
4103 | #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 |
4104 | #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 |
4105 | #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 |
4106 | #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 |
4107 | #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 |
4108 | #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a |
4109 | #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c |
4110 | #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e |
4111 | #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x00000003L |
4112 | #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0x0000000CL |
4113 | #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x00000030L |
4114 | #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0x000000C0L |
4115 | #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x00000300L |
4116 | #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0x00000C00L |
4117 | #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x00003000L |
4118 | #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0x0000C000L |
4119 | #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x00030000L |
4120 | #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0x000C0000L |
4121 | #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x00300000L |
4122 | #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0x00C00000L |
4123 | #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x03000000L |
4124 | #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0x0C000000L |
4125 | #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000L |
4126 | #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xC0000000L |
4127 | //UVD_MP_SWAP_CNTL2 |
4128 | #define UVD_MP_SWAP_CNTL2__MP_REF16_MC_SWAP__SHIFT 0x0 |
4129 | #define UVD_MP_SWAP_CNTL2__MP_REF16_MC_SWAP_MASK 0x00000003L |
4130 | //UVD_MPC_LUMA_SRCH |
4131 | #define UVD_MPC_LUMA_SRCH__CNTR__SHIFT 0x0 |
4132 | #define UVD_MPC_LUMA_SRCH__CNTR_MASK 0xFFFFFFFFL |
4133 | //UVD_MPC_LUMA_HIT |
4134 | #define UVD_MPC_LUMA_HIT__CNTR__SHIFT 0x0 |
4135 | #define UVD_MPC_LUMA_HIT__CNTR_MASK 0xFFFFFFFFL |
4136 | //UVD_MPC_LUMA_HITPEND |
4137 | #define UVD_MPC_LUMA_HITPEND__CNTR__SHIFT 0x0 |
4138 | #define UVD_MPC_LUMA_HITPEND__CNTR_MASK 0xFFFFFFFFL |
4139 | //UVD_MPC_CHROMA_SRCH |
4140 | #define UVD_MPC_CHROMA_SRCH__CNTR__SHIFT 0x0 |
4141 | #define UVD_MPC_CHROMA_SRCH__CNTR_MASK 0xFFFFFFFFL |
4142 | //UVD_MPC_CHROMA_HIT |
4143 | #define UVD_MPC_CHROMA_HIT__CNTR__SHIFT 0x0 |
4144 | #define UVD_MPC_CHROMA_HIT__CNTR_MASK 0xFFFFFFFFL |
4145 | //UVD_MPC_CHROMA_HITPEND |
4146 | #define UVD_MPC_CHROMA_HITPEND__CNTR__SHIFT 0x0 |
4147 | #define UVD_MPC_CHROMA_HITPEND__CNTR_MASK 0xFFFFFFFFL |
4148 | //UVD_MPC_CNTL |
4149 | #define UVD_MPC_CNTL__BLK_RST__SHIFT 0x0 |
4150 | #define UVD_MPC_CNTL__REG_MPC1_PERF_SELECT__SHIFT 0x1 |
4151 | #define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 |
4152 | #define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 |
4153 | #define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 |
4154 | #define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 |
4155 | #define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP__SHIFT 0x13 |
4156 | #define UVD_MPC_CNTL__TEST_MODE_EN__SHIFT 0x14 |
4157 | #define UVD_MPC_CNTL__BLK_RST_MASK 0x00000001L |
4158 | #define UVD_MPC_CNTL__REG_MPC1_PERF_SELECT_MASK 0x00000002L |
4159 | #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L |
4160 | #define UVD_MPC_CNTL__PERF_RST_MASK 0x00000040L |
4161 | #define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x00030000L |
4162 | #define UVD_MPC_CNTL__URGENT_EN_MASK 0x00040000L |
4163 | #define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP_MASK 0x00080000L |
4164 | #define UVD_MPC_CNTL__TEST_MODE_EN_MASK 0x00300000L |
4165 | //UVD_MPC_PITCH |
4166 | #define UVD_MPC_PITCH__LUMA_PITCH__SHIFT 0x0 |
4167 | #define UVD_MPC_PITCH__LUMA_PITCH_MASK 0x000007FFL |
4168 | //UVD_MPC_SET_MUXA0 |
4169 | #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 |
4170 | #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 |
4171 | #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc |
4172 | #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 |
4173 | #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 |
4174 | #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003FL |
4175 | #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000FC0L |
4176 | #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003F000L |
4177 | #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00FC0000L |
4178 | #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3F000000L |
4179 | //UVD_MPC_SET_MUXA1 |
4180 | #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 |
4181 | #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 |
4182 | #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc |
4183 | #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003FL |
4184 | #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000FC0L |
4185 | #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003F000L |
4186 | //UVD_MPC_SET_MUXB0 |
4187 | #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 |
4188 | #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 |
4189 | #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc |
4190 | #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 |
4191 | #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 |
4192 | #define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003FL |
4193 | #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000FC0L |
4194 | #define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003F000L |
4195 | #define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00FC0000L |
4196 | #define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3F000000L |
4197 | //UVD_MPC_SET_MUXB1 |
4198 | #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 |
4199 | #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 |
4200 | #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc |
4201 | #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003FL |
4202 | #define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000FC0L |
4203 | #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003F000L |
4204 | //UVD_MPC_SET_MUX |
4205 | #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 |
4206 | #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 |
4207 | #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 |
4208 | #define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L |
4209 | #define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L |
4210 | #define UVD_MPC_SET_MUX__SET_2_MASK 0x000001C0L |
4211 | //UVD_MPC_SET_ALU |
4212 | #define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 |
4213 | #define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 |
4214 | #define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L |
4215 | #define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000FF0L |
4216 | //UVD_MPC_PERF0 |
4217 | #define UVD_MPC_PERF0__MAX_LAT__SHIFT 0x0 |
4218 | #define UVD_MPC_PERF0__MAX_LAT_MASK 0x000003FFL |
4219 | //UVD_MPC_PERF1 |
4220 | #define UVD_MPC_PERF1__AVE_LAT__SHIFT 0x0 |
4221 | #define UVD_MPC_PERF1__AVE_LAT_MASK 0x000003FFL |
4222 | //UVD_MPC_IND_INDEX |
4223 | #define UVD_MPC_IND_INDEX__INDEX__SHIFT 0x0 |
4224 | #define UVD_MPC_IND_INDEX__INDEX_MASK 0x000001FFL |
4225 | //UVD_MPC_IND_DATA |
4226 | #define UVD_MPC_IND_DATA__DATA__SHIFT 0x0 |
4227 | #define UVD_MPC_IND_DATA__DATA_MASK 0xFFFFFFFFL |
4228 | |
4229 | |
4230 | // addressBlock: uvd0_uvd_rbcdec |
4231 | //UVD_RBC_IB_SIZE |
4232 | #define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 |
4233 | #define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L |
4234 | //UVD_RBC_IB_SIZE_UPDATE |
4235 | #define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 |
4236 | #define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L |
4237 | //UVD_RBC_RB_CNTL |
4238 | #define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 |
4239 | #define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 |
4240 | #define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 |
4241 | #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 |
4242 | #define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 |
4243 | #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c |
4244 | #define UVD_RBC_RB_CNTL__BLK_RST__SHIFT 0x1d |
4245 | #define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001FL |
4246 | #define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001F00L |
4247 | #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L |
4248 | #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L |
4249 | #define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L |
4250 | #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L |
4251 | #define UVD_RBC_RB_CNTL__BLK_RST_MASK 0x20000000L |
4252 | //UVD_RBC_RB_RPTR_ADDR |
4253 | #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 |
4254 | #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFFL |
4255 | //UVD_RBC_VCPU_ACCESS |
4256 | #define UVD_RBC_VCPU_ACCESS__ENABLE_RBC__SHIFT 0x0 |
4257 | #define UVD_RBC_VCPU_ACCESS__ENABLE_RBC_MASK 0x00000001L |
4258 | //UVD_FW_SEMAPHORE_CNTL |
4259 | #define UVD_FW_SEMAPHORE_CNTL__START__SHIFT 0x0 |
4260 | #define UVD_FW_SEMAPHORE_CNTL__BUSY__SHIFT 0x8 |
4261 | #define UVD_FW_SEMAPHORE_CNTL__PASS__SHIFT 0x9 |
4262 | #define UVD_FW_SEMAPHORE_CNTL__START_MASK 0x00000001L |
4263 | #define UVD_FW_SEMAPHORE_CNTL__BUSY_MASK 0x00000100L |
4264 | #define UVD_FW_SEMAPHORE_CNTL__PASS_MASK 0x00000200L |
4265 | //UVD_RBC_READ_REQ_URGENT_CNTL |
4266 | #define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 |
4267 | #define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L |
4268 | //UVD_RBC_RB_WPTR_CNTL |
4269 | #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x0 |
4270 | #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK 0x00007FFFL |
4271 | //UVD_RBC_WPTR_STATUS |
4272 | #define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE__SHIFT 0x4 |
4273 | #define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE_MASK 0x007FFFF0L |
4274 | //UVD_RBC_WPTR_POLL_CNTL |
4275 | #define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ__SHIFT 0x0 |
4276 | #define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
4277 | #define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ_MASK 0x0000FFFFL |
4278 | #define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
4279 | //UVD_RBC_WPTR_POLL_ADDR |
4280 | #define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR__SHIFT 0x2 |
4281 | #define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR_MASK 0xFFFFFFFCL |
4282 | //UVD_SEMA_CMD |
4283 | #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 |
4284 | #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 |
4285 | #define UVD_SEMA_CMD__MODE__SHIFT 0x6 |
4286 | #define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 |
4287 | #define UVD_SEMA_CMD__VMID__SHIFT 0x8 |
4288 | #define UVD_SEMA_CMD__REQ_CMD_MASK 0x0000000FL |
4289 | #define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L |
4290 | #define UVD_SEMA_CMD__MODE_MASK 0x00000040L |
4291 | #define UVD_SEMA_CMD__VMID_EN_MASK 0x00000080L |
4292 | #define UVD_SEMA_CMD__VMID_MASK 0x00000F00L |
4293 | //UVD_SEMA_ADDR_LOW |
4294 | #define UVD_SEMA_ADDR_LOW__ADDR_26_3__SHIFT 0x0 |
4295 | #define UVD_SEMA_ADDR_LOW__ADDR_26_3_MASK 0x00FFFFFFL |
4296 | //UVD_SEMA_ADDR_HIGH |
4297 | #define UVD_SEMA_ADDR_HIGH__ADDR_47_27__SHIFT 0x0 |
4298 | #define UVD_SEMA_ADDR_HIGH__ADDR_47_27_MASK 0x001FFFFFL |
4299 | //UVD_ENGINE_CNTL |
4300 | #define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 |
4301 | #define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 |
4302 | #define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE__SHIFT 0x2 |
4303 | #define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x00000001L |
4304 | #define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x00000002L |
4305 | #define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE_MASK 0x00000004L |
4306 | //UVD_SEMA_TIMEOUT_STATUS |
4307 | #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 |
4308 | #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 |
4309 | #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 |
4310 | #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 |
4311 | #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L |
4312 | #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L |
4313 | #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L |
4314 | #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L |
4315 | //UVD_SEMA_CNTL |
4316 | #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 |
4317 | #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 |
4318 | #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L |
4319 | #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L |
4320 | //UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL |
4321 | #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 |
4322 | #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 |
4323 | #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 |
4324 | #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L |
4325 | #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001FFFFEL |
4326 | #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L |
4327 | //UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL |
4328 | #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 |
4329 | #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 |
4330 | #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 |
4331 | #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L |
4332 | #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001FFFFEL |
4333 | #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L |
4334 | //UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL |
4335 | #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 |
4336 | #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 |
4337 | #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 |
4338 | #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L |
4339 | #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001FFFFEL |
4340 | #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L |
4341 | //UVD_JOB_START |
4342 | #define UVD_JOB_START__JOB_START__SHIFT 0x0 |
4343 | #define UVD_JOB_START__JOB_START_MASK 0x00000001L |
4344 | //UVD_RBC_BUF_STATUS |
4345 | #define UVD_RBC_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 |
4346 | #define UVD_RBC_BUF_STATUS__IB_BUF_VALID__SHIFT 0x8 |
4347 | #define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 |
4348 | #define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x13 |
4349 | #define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x16 |
4350 | #define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x19 |
4351 | #define UVD_RBC_BUF_STATUS__RB_BUF_VALID_MASK 0x000000FFL |
4352 | #define UVD_RBC_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FF00L |
4353 | #define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x00070000L |
4354 | #define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x00380000L |
4355 | #define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x01C00000L |
4356 | #define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x0E000000L |
4357 | //UVD_RBC_SWAP_CNTL |
4358 | #define UVD_RBC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 |
4359 | #define UVD_RBC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 |
4360 | #define UVD_RBC_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 |
4361 | #define UVD_RBC_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a |
4362 | #define UVD_RBC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L |
4363 | #define UVD_RBC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL |
4364 | #define UVD_RBC_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x00000030L |
4365 | #define UVD_RBC_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L |
4366 | |
4367 | |
4368 | // addressBlock: uvd0_lmi_adpdec |
4369 | //UVD_LMI_RE_64BIT_BAR_LOW |
4370 | #define UVD_LMI_RE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4371 | #define UVD_LMI_RE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4372 | //UVD_LMI_RE_64BIT_BAR_HIGH |
4373 | #define UVD_LMI_RE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4374 | #define UVD_LMI_RE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4375 | //UVD_LMI_IT_64BIT_BAR_LOW |
4376 | #define UVD_LMI_IT_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4377 | #define UVD_LMI_IT_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4378 | //UVD_LMI_IT_64BIT_BAR_HIGH |
4379 | #define UVD_LMI_IT_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4380 | #define UVD_LMI_IT_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4381 | //UVD_LMI_MP_64BIT_BAR_LOW |
4382 | #define UVD_LMI_MP_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4383 | #define UVD_LMI_MP_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4384 | //UVD_LMI_MP_64BIT_BAR_HIGH |
4385 | #define UVD_LMI_MP_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4386 | #define UVD_LMI_MP_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4387 | //UVD_LMI_CM_64BIT_BAR_LOW |
4388 | #define UVD_LMI_CM_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4389 | #define UVD_LMI_CM_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4390 | //UVD_LMI_CM_64BIT_BAR_HIGH |
4391 | #define UVD_LMI_CM_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4392 | #define UVD_LMI_CM_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4393 | //UVD_LMI_DB_64BIT_BAR_LOW |
4394 | #define UVD_LMI_DB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4395 | #define UVD_LMI_DB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4396 | //UVD_LMI_DB_64BIT_BAR_HIGH |
4397 | #define UVD_LMI_DB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4398 | #define UVD_LMI_DB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4399 | //UVD_LMI_DBW_64BIT_BAR_LOW |
4400 | #define UVD_LMI_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4401 | #define UVD_LMI_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4402 | //UVD_LMI_DBW_64BIT_BAR_HIGH |
4403 | #define UVD_LMI_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4404 | #define UVD_LMI_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4405 | //UVD_LMI_IDCT_64BIT_BAR_LOW |
4406 | #define UVD_LMI_IDCT_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4407 | #define UVD_LMI_IDCT_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4408 | //UVD_LMI_IDCT_64BIT_BAR_HIGH |
4409 | #define UVD_LMI_IDCT_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4410 | #define UVD_LMI_IDCT_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4411 | //UVD_LMI_MPRD_S0_64BIT_BAR_LOW |
4412 | #define UVD_LMI_MPRD_S0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4413 | #define UVD_LMI_MPRD_S0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4414 | //UVD_LMI_MPRD_S0_64BIT_BAR_HIGH |
4415 | #define UVD_LMI_MPRD_S0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4416 | #define UVD_LMI_MPRD_S0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4417 | //UVD_LMI_MPRD_S1_64BIT_BAR_LOW |
4418 | #define UVD_LMI_MPRD_S1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4419 | #define UVD_LMI_MPRD_S1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4420 | //UVD_LMI_MPRD_S1_64BIT_BAR_HIGH |
4421 | #define UVD_LMI_MPRD_S1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4422 | #define UVD_LMI_MPRD_S1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4423 | //UVD_LMI_MPRD_DBW_64BIT_BAR_LOW |
4424 | #define UVD_LMI_MPRD_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4425 | #define UVD_LMI_MPRD_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4426 | //UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH |
4427 | #define UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4428 | #define UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4429 | //UVD_LMI_MPC_64BIT_BAR_LOW |
4430 | #define UVD_LMI_MPC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4431 | #define UVD_LMI_MPC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4432 | //UVD_LMI_MPC_64BIT_BAR_HIGH |
4433 | #define UVD_LMI_MPC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4434 | #define UVD_LMI_MPC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4435 | //UVD_LMI_RBC_RB_64BIT_BAR_LOW |
4436 | #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4437 | #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4438 | //UVD_LMI_RBC_RB_64BIT_BAR_HIGH |
4439 | #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4440 | #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4441 | //UVD_LMI_RBC_IB_64BIT_BAR_LOW |
4442 | #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4443 | #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4444 | //UVD_LMI_RBC_IB_64BIT_BAR_HIGH |
4445 | #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4446 | #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4447 | //UVD_LMI_LBSI_64BIT_BAR_LOW |
4448 | #define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4449 | #define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4450 | //UVD_LMI_LBSI_64BIT_BAR_HIGH |
4451 | #define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4452 | #define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4453 | //UVD_LMI_VCPU_NC0_64BIT_BAR_LOW |
4454 | #define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4455 | #define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4456 | //UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH |
4457 | #define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4458 | #define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4459 | //UVD_LMI_VCPU_NC1_64BIT_BAR_LOW |
4460 | #define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4461 | #define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4462 | //UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH |
4463 | #define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4464 | #define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4465 | //UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW |
4466 | #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4467 | #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4468 | //UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH |
4469 | #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4470 | #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4471 | //UVD_LMI_CENC_64BIT_BAR_LOW |
4472 | #define UVD_LMI_CENC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4473 | #define UVD_LMI_CENC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4474 | //UVD_LMI_CENC_64BIT_BAR_HIGH |
4475 | #define UVD_LMI_CENC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4476 | #define UVD_LMI_CENC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4477 | //UVD_LMI_SRE_64BIT_BAR_LOW |
4478 | #define UVD_LMI_SRE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4479 | #define UVD_LMI_SRE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4480 | //UVD_LMI_SRE_64BIT_BAR_HIGH |
4481 | #define UVD_LMI_SRE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4482 | #define UVD_LMI_SRE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4483 | //UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW |
4484 | #define UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4485 | #define UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4486 | //UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH |
4487 | #define UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4488 | #define UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4489 | //UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW |
4490 | #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4491 | #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4492 | //UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH |
4493 | #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4494 | #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4495 | //UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW |
4496 | #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4497 | #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4498 | //UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH |
4499 | #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4500 | #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4501 | //UVD_LMI_MIF_REF_64BIT_BAR_LOW |
4502 | #define UVD_LMI_MIF_REF_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4503 | #define UVD_LMI_MIF_REF_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4504 | //UVD_LMI_MIF_REF_64BIT_BAR_HIGH |
4505 | #define UVD_LMI_MIF_REF_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4506 | #define UVD_LMI_MIF_REF_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4507 | //UVD_LMI_MIF_DBW_64BIT_BAR_LOW |
4508 | #define UVD_LMI_MIF_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4509 | #define UVD_LMI_MIF_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4510 | //UVD_LMI_MIF_DBW_64BIT_BAR_HIGH |
4511 | #define UVD_LMI_MIF_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4512 | #define UVD_LMI_MIF_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4513 | //UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW |
4514 | #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4515 | #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4516 | //UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH |
4517 | #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4518 | #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4519 | //UVD_LMI_MIF_BSP0_64BIT_BAR_LOW |
4520 | #define UVD_LMI_MIF_BSP0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4521 | #define UVD_LMI_MIF_BSP0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4522 | //UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH |
4523 | #define UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4524 | #define UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4525 | //UVD_LMI_MIF_BSP1_64BIT_BAR_LOW |
4526 | #define UVD_LMI_MIF_BSP1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4527 | #define UVD_LMI_MIF_BSP1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4528 | //UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH |
4529 | #define UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4530 | #define UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4531 | //UVD_LMI_MIF_BSP2_64BIT_BAR_LOW |
4532 | #define UVD_LMI_MIF_BSP2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4533 | #define UVD_LMI_MIF_BSP2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4534 | //UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH |
4535 | #define UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4536 | #define UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4537 | //UVD_LMI_MIF_BSP3_64BIT_BAR_LOW |
4538 | #define UVD_LMI_MIF_BSP3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4539 | #define UVD_LMI_MIF_BSP3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4540 | //UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH |
4541 | #define UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4542 | #define UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4543 | //UVD_LMI_MIF_BSD0_64BIT_BAR_LOW |
4544 | #define UVD_LMI_MIF_BSD0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4545 | #define UVD_LMI_MIF_BSD0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4546 | //UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH |
4547 | #define UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4548 | #define UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4549 | //UVD_LMI_MIF_BSD1_64BIT_BAR_LOW |
4550 | #define UVD_LMI_MIF_BSD1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4551 | #define UVD_LMI_MIF_BSD1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4552 | //UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH |
4553 | #define UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4554 | #define UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4555 | //UVD_LMI_MIF_BSD2_64BIT_BAR_LOW |
4556 | #define UVD_LMI_MIF_BSD2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4557 | #define UVD_LMI_MIF_BSD2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4558 | //UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH |
4559 | #define UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4560 | #define UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4561 | //UVD_LMI_MIF_BSD3_64BIT_BAR_LOW |
4562 | #define UVD_LMI_MIF_BSD3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4563 | #define UVD_LMI_MIF_BSD3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4564 | //UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH |
4565 | #define UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4566 | #define UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4567 | //UVD_LMI_MIF_BSD4_64BIT_BAR_LOW |
4568 | #define UVD_LMI_MIF_BSD4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4569 | #define UVD_LMI_MIF_BSD4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4570 | //UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH |
4571 | #define UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4572 | #define UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4573 | //UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW |
4574 | #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4575 | #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4576 | //UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH |
4577 | #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4578 | #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4579 | //UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW |
4580 | #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4581 | #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4582 | //UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH |
4583 | #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4584 | #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4585 | //UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW |
4586 | #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4587 | #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4588 | //UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH |
4589 | #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4590 | #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4591 | //UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW |
4592 | #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4593 | #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4594 | //UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH |
4595 | #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4596 | #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4597 | //UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW |
4598 | #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4599 | #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4600 | //UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH |
4601 | #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4602 | #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4603 | //UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW |
4604 | #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4605 | #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4606 | //UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH |
4607 | #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4608 | #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4609 | //UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW |
4610 | #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4611 | #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4612 | //UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH |
4613 | #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4614 | #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4615 | //UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW |
4616 | #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4617 | #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4618 | //UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH |
4619 | #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4620 | #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4621 | //UVD_LMI_MIF_SCLR_64BIT_BAR_LOW |
4622 | #define UVD_LMI_MIF_SCLR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4623 | #define UVD_LMI_MIF_SCLR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4624 | //UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH |
4625 | #define UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4626 | #define UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4627 | //UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW |
4628 | #define UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4629 | #define UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4630 | //UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH |
4631 | #define UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4632 | #define UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4633 | //UVD_LMI_SPH_64BIT_BAR_HIGH |
4634 | #define UVD_LMI_SPH_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4635 | #define UVD_LMI_SPH_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4636 | //UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW |
4637 | #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4638 | #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4639 | //UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH |
4640 | #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4641 | #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4642 | //UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW |
4643 | #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4644 | #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4645 | //UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH |
4646 | #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4647 | #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4648 | //UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW |
4649 | #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4650 | #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4651 | //UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH |
4652 | #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4653 | #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4654 | //UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW |
4655 | #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4656 | #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4657 | //UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH |
4658 | #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4659 | #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4660 | //UVD_ADP_ATOMIC_CONFIG |
4661 | #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER0_WR_CACHE__SHIFT 0x0 |
4662 | #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER1_WR_CACHE__SHIFT 0x4 |
4663 | #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER2_WR_CACHE__SHIFT 0x8 |
4664 | #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER3_WR_CACHE__SHIFT 0xc |
4665 | #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_RD_URG__SHIFT 0x10 |
4666 | #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER0_WR_CACHE_MASK 0x0000000FL |
4667 | #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER1_WR_CACHE_MASK 0x000000F0L |
4668 | #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER2_WR_CACHE_MASK 0x00000F00L |
4669 | #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER3_WR_CACHE_MASK 0x0000F000L |
4670 | #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_RD_URG_MASK 0x000F0000L |
4671 | //UVD_LMI_ARB_CTRL2 |
4672 | #define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN__SHIFT 0x0 |
4673 | #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN__SHIFT 0x1 |
4674 | #define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST__SHIFT 0x2 |
4675 | #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST__SHIFT 0x6 |
4676 | #define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX__SHIFT 0xa |
4677 | #define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX__SHIFT 0x14 |
4678 | #define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN_MASK 0x00000001L |
4679 | #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN_MASK 0x00000002L |
4680 | #define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST_MASK 0x0000003CL |
4681 | #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST_MASK 0x000003C0L |
4682 | #define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX_MASK 0x000FFC00L |
4683 | #define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX_MASK 0xFFF00000L |
4684 | //UVD_LMI_VCPU_CACHE_VMIDS_MULTI |
4685 | #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID__SHIFT 0x0 |
4686 | #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID__SHIFT 0x4 |
4687 | #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID__SHIFT 0x8 |
4688 | #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID__SHIFT 0xc |
4689 | #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID__SHIFT 0x10 |
4690 | #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID__SHIFT 0x14 |
4691 | #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID__SHIFT 0x18 |
4692 | #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID__SHIFT 0x1c |
4693 | #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID_MASK 0x0000000FL |
4694 | #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID_MASK 0x000000F0L |
4695 | #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID_MASK 0x00000F00L |
4696 | #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID_MASK 0x0000F000L |
4697 | #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID_MASK 0x000F0000L |
4698 | #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID_MASK 0x00F00000L |
4699 | #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID_MASK 0x0F000000L |
4700 | #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID_MASK 0xF0000000L |
4701 | //UVD_LMI_VCPU_NC_VMIDS_MULTI |
4702 | #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID__SHIFT 0x4 |
4703 | #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID__SHIFT 0x8 |
4704 | #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID__SHIFT 0xc |
4705 | #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID__SHIFT 0x10 |
4706 | #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID__SHIFT 0x14 |
4707 | #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID__SHIFT 0x18 |
4708 | #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID_MASK 0x000000F0L |
4709 | #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID_MASK 0x00000F00L |
4710 | #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID_MASK 0x0000F000L |
4711 | #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID_MASK 0x000F0000L |
4712 | #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID_MASK 0x00F00000L |
4713 | #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID_MASK 0x0F000000L |
4714 | //UVD_LMI_LAT_CTRL |
4715 | #define UVD_LMI_LAT_CTRL__SCALE__SHIFT 0x0 |
4716 | #define UVD_LMI_LAT_CTRL__MAX_START__SHIFT 0x8 |
4717 | #define UVD_LMI_LAT_CTRL__MIN_START__SHIFT 0x9 |
4718 | #define UVD_LMI_LAT_CTRL__AVG_START__SHIFT 0xa |
4719 | #define UVD_LMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb |
4720 | #define UVD_LMI_LAT_CTRL__SKIP__SHIFT 0x10 |
4721 | #define UVD_LMI_LAT_CTRL__SCALE_MASK 0x000000FFL |
4722 | #define UVD_LMI_LAT_CTRL__MAX_START_MASK 0x00000100L |
4723 | #define UVD_LMI_LAT_CTRL__MIN_START_MASK 0x00000200L |
4724 | #define UVD_LMI_LAT_CTRL__AVG_START_MASK 0x00000400L |
4725 | #define UVD_LMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L |
4726 | #define UVD_LMI_LAT_CTRL__SKIP_MASK 0x000F0000L |
4727 | //UVD_LMI_LAT_CNTR |
4728 | #define UVD_LMI_LAT_CNTR__MAX_LAT__SHIFT 0x0 |
4729 | #define UVD_LMI_LAT_CNTR__MIN_LAT__SHIFT 0x8 |
4730 | #define UVD_LMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL |
4731 | #define UVD_LMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L |
4732 | //UVD_LMI_AVG_LAT_CNTR |
4733 | #define UVD_LMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0 |
4734 | #define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8 |
4735 | #define UVD_LMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10 |
4736 | #define UVD_LMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL |
4737 | #define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L |
4738 | #define UVD_LMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L |
4739 | //UVD_LMI_SPH |
4740 | #define UVD_LMI_SPH__ADDR__SHIFT 0x0 |
4741 | #define UVD_LMI_SPH__STS__SHIFT 0x1c |
4742 | #define UVD_LMI_SPH__STS_VALID__SHIFT 0x1e |
4743 | #define UVD_LMI_SPH__STS_OVERFLOW__SHIFT 0x1f |
4744 | #define UVD_LMI_SPH__ADDR_MASK 0x0FFFFFFFL |
4745 | #define UVD_LMI_SPH__STS_MASK 0x30000000L |
4746 | #define UVD_LMI_SPH__STS_VALID_MASK 0x40000000L |
4747 | #define UVD_LMI_SPH__STS_OVERFLOW_MASK 0x80000000L |
4748 | //UVD_LMI_VCPU_CACHE_VMID |
4749 | #define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 |
4750 | #define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL |
4751 | //UVD_LMI_CTRL2 |
4752 | #define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 |
4753 | #define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 |
4754 | #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 |
4755 | #define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 |
4756 | #define UVD_LMI_CTRL2__CRC1_RESET__SHIFT 0x4 |
4757 | #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 |
4758 | #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 |
4759 | #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 |
4760 | #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb |
4761 | #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd |
4762 | #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe |
4763 | #define 0xf |
4764 | #define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 |
4765 | #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 |
4766 | #define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP__SHIFT 0x19 |
4767 | #define UVD_LMI_CTRL2__NJ_MIF_GATING__SHIFT 0x1a |
4768 | #define UVD_LMI_CTRL2__CRC1_SEL__SHIFT 0x1b |
4769 | #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L |
4770 | #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L |
4771 | #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L |
4772 | #define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L |
4773 | #define UVD_LMI_CTRL2__CRC1_RESET_MASK 0x00000010L |
4774 | #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L |
4775 | #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L |
4776 | #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L |
4777 | #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L |
4778 | #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x00002000L |
4779 | #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x00004000L |
4780 | #define 0x00008000L |
4781 | #define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x00010000L |
4782 | #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x01FE0000L |
4783 | #define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP_MASK 0x02000000L |
4784 | #define UVD_LMI_CTRL2__NJ_MIF_GATING_MASK 0x04000000L |
4785 | #define UVD_LMI_CTRL2__CRC1_SEL_MASK 0xF8000000L |
4786 | //UVD_LMI_URGENT_CTRL |
4787 | #define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0 |
4788 | #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL__SHIFT 0x1 |
4789 | #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x2 |
4790 | #define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x8 |
4791 | #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL__SHIFT 0x9 |
4792 | #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0xa |
4793 | #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL__SHIFT 0x10 |
4794 | #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL__SHIFT 0x11 |
4795 | #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT__SHIFT 0x12 |
4796 | #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL__SHIFT 0x18 |
4797 | #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL__SHIFT 0x19 |
4798 | #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT__SHIFT 0x1a |
4799 | #define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L |
4800 | #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL_MASK 0x00000002L |
4801 | #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x0000003CL |
4802 | #define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00000100L |
4803 | #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL_MASK 0x00000200L |
4804 | #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00003C00L |
4805 | #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL_MASK 0x00010000L |
4806 | #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL_MASK 0x00020000L |
4807 | #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT_MASK 0x003C0000L |
4808 | #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL_MASK 0x01000000L |
4809 | #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL_MASK 0x02000000L |
4810 | #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT_MASK 0x3C000000L |
4811 | //UVD_LMI_CTRL |
4812 | #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 |
4813 | #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 |
4814 | #define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 |
4815 | #define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb |
4816 | #define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc |
4817 | #define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd |
4818 | #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe |
4819 | #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf |
4820 | #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14 |
4821 | #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 |
4822 | #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 |
4823 | #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 |
4824 | #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 |
4825 | #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 |
4826 | #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a |
4827 | #define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ__SHIFT 0x1b |
4828 | #define UVD_LMI_CTRL__MC_BLK_RST__SHIFT 0x1c |
4829 | #define UVD_LMI_CTRL__UMC_BLK_RST__SHIFT 0x1d |
4830 | #define UVD_LMI_CTRL__RFU__SHIFT 0x1e |
4831 | #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000FFL |
4832 | #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L |
4833 | #define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L |
4834 | #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L |
4835 | #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L |
4836 | #define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L |
4837 | #define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L |
4838 | #define UVD_LMI_CTRL__CRC_SEL_MASK 0x000F8000L |
4839 | #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x00100000L |
4840 | #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L |
4841 | #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L |
4842 | #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L |
4843 | #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L |
4844 | #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L |
4845 | #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x04000000L |
4846 | #define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ_MASK 0x08000000L |
4847 | #define UVD_LMI_CTRL__MC_BLK_RST_MASK 0x10000000L |
4848 | #define UVD_LMI_CTRL__UMC_BLK_RST_MASK 0x20000000L |
4849 | #define UVD_LMI_CTRL__RFU_MASK 0xC0000000L |
4850 | //UVD_LMI_STATUS |
4851 | #define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 |
4852 | #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 |
4853 | #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 |
4854 | #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 |
4855 | #define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 |
4856 | #define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 |
4857 | #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 |
4858 | #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 |
4859 | #define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 |
4860 | #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 |
4861 | #define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa |
4862 | #define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb |
4863 | #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc |
4864 | #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd |
4865 | #define UVD_LMI_STATUS__BSP0_WRITE_CLEAN__SHIFT 0x12 |
4866 | #define UVD_LMI_STATUS__BSP1_WRITE_CLEAN__SHIFT 0x13 |
4867 | #define UVD_LMI_STATUS__BSP2_WRITE_CLEAN__SHIFT 0x14 |
4868 | #define UVD_LMI_STATUS__BSP3_WRITE_CLEAN__SHIFT 0x15 |
4869 | #define UVD_LMI_STATUS__CENC_READ_CLEAN__SHIFT 0x16 |
4870 | #define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L |
4871 | #define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L |
4872 | #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L |
4873 | #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L |
4874 | #define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x00000010L |
4875 | #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x00000020L |
4876 | #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L |
4877 | #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x00000080L |
4878 | #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x00000100L |
4879 | #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L |
4880 | #define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x00000400L |
4881 | #define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x00000800L |
4882 | #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x00001000L |
4883 | #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x00002000L |
4884 | #define UVD_LMI_STATUS__BSP0_WRITE_CLEAN_MASK 0x00040000L |
4885 | #define UVD_LMI_STATUS__BSP1_WRITE_CLEAN_MASK 0x00080000L |
4886 | #define UVD_LMI_STATUS__BSP2_WRITE_CLEAN_MASK 0x00100000L |
4887 | #define UVD_LMI_STATUS__BSP3_WRITE_CLEAN_MASK 0x00200000L |
4888 | #define UVD_LMI_STATUS__CENC_READ_CLEAN_MASK 0x00400000L |
4889 | //UVD_LMI_PERFMON_CTRL |
4890 | #define UVD_LMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 |
4891 | #define UVD_LMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 |
4892 | #define UVD_LMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L |
4893 | #define UVD_LMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00001F00L |
4894 | //UVD_LMI_PERFMON_COUNT_LO |
4895 | #define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 |
4896 | #define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL |
4897 | //UVD_LMI_PERFMON_COUNT_HI |
4898 | #define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 |
4899 | #define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL |
4900 | //UVD_LMI_ADP_SWAP_CNTL |
4901 | #define UVD_LMI_ADP_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 |
4902 | #define UVD_LMI_ADP_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 |
4903 | #define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa |
4904 | #define UVD_LMI_ADP_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc |
4905 | #define UVD_LMI_ADP_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe |
4906 | #define UVD_LMI_ADP_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 |
4907 | #define UVD_LMI_ADP_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 |
4908 | #define UVD_LMI_ADP_SWAP_CNTL__PREF_MC_SWAP__SHIFT 0x14 |
4909 | #define UVD_LMI_ADP_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 |
4910 | #define UVD_LMI_ADP_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c |
4911 | #define UVD_LMI_ADP_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e |
4912 | #define UVD_LMI_ADP_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0x000000C0L |
4913 | #define UVD_LMI_ADP_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000300L |
4914 | #define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP_MASK 0x00000C00L |
4915 | #define UVD_LMI_ADP_SWAP_CNTL__IT_MC_SWAP_MASK 0x00003000L |
4916 | #define UVD_LMI_ADP_SWAP_CNTL__DB_R_MC_SWAP_MASK 0x0000C000L |
4917 | #define UVD_LMI_ADP_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x00030000L |
4918 | #define UVD_LMI_ADP_SWAP_CNTL__CSM_MC_SWAP_MASK 0x000C0000L |
4919 | #define UVD_LMI_ADP_SWAP_CNTL__PREF_MC_SWAP_MASK 0x00300000L |
4920 | #define UVD_LMI_ADP_SWAP_CNTL__DBW_MC_SWAP_MASK 0x03000000L |
4921 | #define UVD_LMI_ADP_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L |
4922 | #define UVD_LMI_ADP_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L |
4923 | //UVD_LMI_RBC_RB_VMID |
4924 | #define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0 |
4925 | #define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0x0000000FL |
4926 | //UVD_LMI_RBC_IB_VMID |
4927 | #define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 |
4928 | #define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0x0000000FL |
4929 | //UVD_LMI_MC_CREDITS |
4930 | #define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS__SHIFT 0x0 |
4931 | #define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS__SHIFT 0x8 |
4932 | #define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS__SHIFT 0x10 |
4933 | #define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS__SHIFT 0x18 |
4934 | #define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS_MASK 0x0000003FL |
4935 | #define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS_MASK 0x00003F00L |
4936 | #define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS_MASK 0x003F0000L |
4937 | #define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS_MASK 0x3F000000L |
4938 | //UVD_LMI_ADP_IND_INDEX |
4939 | #define UVD_LMI_ADP_IND_INDEX__INDEX__SHIFT 0x0 |
4940 | #define UVD_LMI_ADP_IND_INDEX__INDEX_MASK 0x00001FFFL |
4941 | //UVD_LMI_ADP_IND_DATA |
4942 | #define UVD_LMI_ADP_IND_DATA__DATA__SHIFT 0x0 |
4943 | #define UVD_LMI_ADP_IND_DATA__DATA_MASK 0xFFFFFFFFL |
4944 | //UVD_LMI_PREF_CTRL |
4945 | #define UVD_LMI_PREF_CTRL__PREF_RST__SHIFT 0x0 |
4946 | #define UVD_LMI_PREF_CTRL__PREF_BUSY_STATUS__SHIFT 0x1 |
4947 | #define UVD_LMI_PREF_CTRL__PREF_WSTRB__SHIFT 0x2 |
4948 | #define UVD_LMI_PREF_CTRL__PREF_WRITE_SIZE__SHIFT 0x3 |
4949 | #define UVD_LMI_PREF_CTRL__PREF_STEP_SIZE__SHIFT 0x4 |
4950 | #define UVD_LMI_PREF_CTRL__PREF_SIZE__SHIFT 0x13 |
4951 | #define UVD_LMI_PREF_CTRL__PREF_RST_MASK 0x00000001L |
4952 | #define UVD_LMI_PREF_CTRL__PREF_BUSY_STATUS_MASK 0x00000002L |
4953 | #define UVD_LMI_PREF_CTRL__PREF_WSTRB_MASK 0x00000004L |
4954 | #define UVD_LMI_PREF_CTRL__PREF_WRITE_SIZE_MASK 0x00000008L |
4955 | #define UVD_LMI_PREF_CTRL__PREF_STEP_SIZE_MASK 0x00000070L |
4956 | #define UVD_LMI_PREF_CTRL__PREF_SIZE_MASK 0xFFF80000L |
4957 | //UVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW |
4958 | #define UVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
4959 | #define UVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
4960 | //UVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH |
4961 | #define UVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
4962 | #define UVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
4963 | //VCN_RAS_CNTL |
4964 | #define VCN_RAS_CNTL__VCPU_VCODEC_IH_EN__SHIFT 0x0 |
4965 | #define VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN__SHIFT 0x4 |
4966 | #define VCN_RAS_CNTL__VCPU_VCODEC_REARM__SHIFT 0x8 |
4967 | #define VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN__SHIFT 0xc |
4968 | #define VCN_RAS_CNTL__VCPU_VCODEC_READY__SHIFT 0x10 |
4969 | #define VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK 0x00000001L |
4970 | #define VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK 0x00000010L |
4971 | #define VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK 0x00000100L |
4972 | #define VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK 0x00001000L |
4973 | #define VCN_RAS_CNTL__VCPU_VCODEC_READY_MASK 0x00010000L |
4974 | |
4975 | |
4976 | // addressBlock: uvd0_jpegnpdec |
4977 | //UVD_JPEG_CNTL |
4978 | #define UVD_JPEG_CNTL__REQUEST_EN__SHIFT 0x1 |
4979 | #define UVD_JPEG_CNTL__ERR_RST_EN__SHIFT 0x2 |
4980 | #define UVD_JPEG_CNTL__REQUEST_EN_MASK 0x00000002L |
4981 | #define UVD_JPEG_CNTL__ERR_RST_EN_MASK 0x00000004L |
4982 | //UVD_JPEG_RB_BASE |
4983 | #define UVD_JPEG_RB_BASE__RB_BYTE_OFF__SHIFT 0x0 |
4984 | #define UVD_JPEG_RB_BASE__RB_BASE__SHIFT 0x6 |
4985 | #define UVD_JPEG_RB_BASE__RB_BYTE_OFF_MASK 0x0000003FL |
4986 | #define UVD_JPEG_RB_BASE__RB_BASE_MASK 0xFFFFFFC0L |
4987 | //UVD_JPEG_RB_WPTR |
4988 | #define UVD_JPEG_RB_WPTR__RB_WPTR__SHIFT 0x4 |
4989 | #define UVD_JPEG_RB_WPTR__RB_WPTR_MASK 0x3FFFFFF0L |
4990 | //UVD_JPEG_RB_RPTR |
4991 | #define UVD_JPEG_RB_RPTR__RB_RPTR__SHIFT 0x4 |
4992 | #define UVD_JPEG_RB_RPTR__RB_RPTR_MASK 0x3FFFFFF0L |
4993 | //UVD_JPEG_RB_SIZE |
4994 | #define UVD_JPEG_RB_SIZE__RB_SIZE__SHIFT 0x4 |
4995 | #define UVD_JPEG_RB_SIZE__RB_SIZE_MASK 0x3FFFFFF0L |
4996 | //UVD_JPEG_DEC_CNT |
4997 | #define UVD_JPEG_DEC_CNT__DECODE_COUNT__SHIFT 0x0 |
4998 | #define UVD_JPEG_DEC_CNT__DECODE_COUNT_MASK 0xFFFFFFFFL |
4999 | //UVD_JPEG_SPS_INFO |
5000 | #define UVD_JPEG_SPS_INFO__PIC_WIDTH__SHIFT 0x0 |
5001 | #define UVD_JPEG_SPS_INFO__PIC_HEIGHT__SHIFT 0x10 |
5002 | #define UVD_JPEG_SPS_INFO__PIC_WIDTH_MASK 0x0000FFFFL |
5003 | #define UVD_JPEG_SPS_INFO__PIC_HEIGHT_MASK 0xFFFF0000L |
5004 | //UVD_JPEG_SPS1_INFO |
5005 | #define UVD_JPEG_SPS1_INFO__CHROMA_FORMAT_IDC__SHIFT 0x0 |
5006 | #define UVD_JPEG_SPS1_INFO__YUV422_SUBFORMAT__SHIFT 0x3 |
5007 | #define UVD_JPEG_SPS1_INFO__OUT_FMT_422__SHIFT 0x4 |
5008 | #define UVD_JPEG_SPS1_INFO__CHROMA_FORMAT_IDC_MASK 0x00000007L |
5009 | #define UVD_JPEG_SPS1_INFO__YUV422_SUBFORMAT_MASK 0x00000008L |
5010 | #define UVD_JPEG_SPS1_INFO__OUT_FMT_422_MASK 0x00000010L |
5011 | //UVD_JPEG_RE_TIMER |
5012 | #define UVD_JPEG_RE_TIMER__TIMER_OUT__SHIFT 0x0 |
5013 | #define UVD_JPEG_RE_TIMER__TIMER_OUT_EN__SHIFT 0x10 |
5014 | #define UVD_JPEG_RE_TIMER__TIMER_OUT_MASK 0x000000FFL |
5015 | #define UVD_JPEG_RE_TIMER__TIMER_OUT_EN_MASK 0x00010000L |
5016 | //UVD_JPEG_DEC_SCRATCH0 |
5017 | #define UVD_JPEG_DEC_SCRATCH0__SCRATCH0__SHIFT 0x0 |
5018 | #define UVD_JPEG_DEC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL |
5019 | //UVD_JPEG_INT_EN |
5020 | #define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN__SHIFT 0x0 |
5021 | #define UVD_JPEG_INT_EN__JOB_AVAIL_EN__SHIFT 0x1 |
5022 | #define UVD_JPEG_INT_EN__FENCE_VAL_EN__SHIFT 0x2 |
5023 | #define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN__SHIFT 0x6 |
5024 | #define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN__SHIFT 0x7 |
5025 | #define UVD_JPEG_INT_EN__EOI_ERR_EN__SHIFT 0x8 |
5026 | #define UVD_JPEG_INT_EN__HFM_ERR_EN__SHIFT 0x9 |
5027 | #define UVD_JPEG_INT_EN__RST_ERR_EN__SHIFT 0xa |
5028 | #define UVD_JPEG_INT_EN__ECS_MK_ERR_EN__SHIFT 0xb |
5029 | #define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN__SHIFT 0xc |
5030 | #define UVD_JPEG_INT_EN__MARKER_ERR_EN__SHIFT 0xd |
5031 | #define UVD_JPEG_INT_EN__FMT_ERR_EN__SHIFT 0xe |
5032 | #define UVD_JPEG_INT_EN__PROFILE_ERR_EN__SHIFT 0xf |
5033 | #define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN_MASK 0x00000001L |
5034 | #define UVD_JPEG_INT_EN__JOB_AVAIL_EN_MASK 0x00000002L |
5035 | #define UVD_JPEG_INT_EN__FENCE_VAL_EN_MASK 0x00000004L |
5036 | #define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN_MASK 0x00000040L |
5037 | #define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN_MASK 0x00000080L |
5038 | #define UVD_JPEG_INT_EN__EOI_ERR_EN_MASK 0x00000100L |
5039 | #define UVD_JPEG_INT_EN__HFM_ERR_EN_MASK 0x00000200L |
5040 | #define UVD_JPEG_INT_EN__RST_ERR_EN_MASK 0x00000400L |
5041 | #define UVD_JPEG_INT_EN__ECS_MK_ERR_EN_MASK 0x00000800L |
5042 | #define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN_MASK 0x00001000L |
5043 | #define UVD_JPEG_INT_EN__MARKER_ERR_EN_MASK 0x00002000L |
5044 | #define UVD_JPEG_INT_EN__FMT_ERR_EN_MASK 0x00004000L |
5045 | #define UVD_JPEG_INT_EN__PROFILE_ERR_EN_MASK 0x00008000L |
5046 | //UVD_JPEG_INT_STAT |
5047 | #define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT__SHIFT 0x0 |
5048 | #define UVD_JPEG_INT_STAT__JOB_AVAIL_INT__SHIFT 0x1 |
5049 | #define UVD_JPEG_INT_STAT__FENCE_VAL_INT__SHIFT 0x2 |
5050 | #define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT__SHIFT 0x6 |
5051 | #define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT__SHIFT 0x7 |
5052 | #define UVD_JPEG_INT_STAT__EOI_ERR_INT__SHIFT 0x8 |
5053 | #define UVD_JPEG_INT_STAT__HFM_ERR_INT__SHIFT 0x9 |
5054 | #define UVD_JPEG_INT_STAT__RST_ERR_INT__SHIFT 0xa |
5055 | #define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT__SHIFT 0xb |
5056 | #define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT__SHIFT 0xc |
5057 | #define UVD_JPEG_INT_STAT__MARKER_ERR_INT__SHIFT 0xd |
5058 | #define UVD_JPEG_INT_STAT__FMT_ERR_INT__SHIFT 0xe |
5059 | #define UVD_JPEG_INT_STAT__PROFILE_ERR_INT__SHIFT 0xf |
5060 | #define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT_MASK 0x00000001L |
5061 | #define UVD_JPEG_INT_STAT__JOB_AVAIL_INT_MASK 0x00000002L |
5062 | #define UVD_JPEG_INT_STAT__FENCE_VAL_INT_MASK 0x00000004L |
5063 | #define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT_MASK 0x00000040L |
5064 | #define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT_MASK 0x00000080L |
5065 | #define UVD_JPEG_INT_STAT__EOI_ERR_INT_MASK 0x00000100L |
5066 | #define UVD_JPEG_INT_STAT__HFM_ERR_INT_MASK 0x00000200L |
5067 | #define UVD_JPEG_INT_STAT__RST_ERR_INT_MASK 0x00000400L |
5068 | #define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT_MASK 0x00000800L |
5069 | #define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT_MASK 0x00001000L |
5070 | #define UVD_JPEG_INT_STAT__MARKER_ERR_INT_MASK 0x00002000L |
5071 | #define UVD_JPEG_INT_STAT__FMT_ERR_INT_MASK 0x00004000L |
5072 | #define UVD_JPEG_INT_STAT__PROFILE_ERR_INT_MASK 0x00008000L |
5073 | //UVD_JPEG_TIER_CNTL0 |
5074 | #define UVD_JPEG_TIER_CNTL0__TIER_SEL__SHIFT 0x0 |
5075 | #define UVD_JPEG_TIER_CNTL0__Y_COMP_ID__SHIFT 0x2 |
5076 | #define UVD_JPEG_TIER_CNTL0__U_COMP_ID__SHIFT 0x4 |
5077 | #define UVD_JPEG_TIER_CNTL0__V_COMP_ID__SHIFT 0x6 |
5078 | #define UVD_JPEG_TIER_CNTL0__Y_H_SAMP_FAC__SHIFT 0x8 |
5079 | #define UVD_JPEG_TIER_CNTL0__Y_V_SAMP_FAC__SHIFT 0xb |
5080 | #define UVD_JPEG_TIER_CNTL0__U_H_SAMP_FAC__SHIFT 0xe |
5081 | #define UVD_JPEG_TIER_CNTL0__U_V_SAMP_FAC__SHIFT 0x11 |
5082 | #define UVD_JPEG_TIER_CNTL0__V_H_SAMP_FAC__SHIFT 0x14 |
5083 | #define UVD_JPEG_TIER_CNTL0__V_V_SAMP_FAC__SHIFT 0x17 |
5084 | #define UVD_JPEG_TIER_CNTL0__Y_TQ__SHIFT 0x1a |
5085 | #define UVD_JPEG_TIER_CNTL0__U_TQ__SHIFT 0x1c |
5086 | #define UVD_JPEG_TIER_CNTL0__V_TQ__SHIFT 0x1e |
5087 | #define UVD_JPEG_TIER_CNTL0__TIER_SEL_MASK 0x00000003L |
5088 | #define UVD_JPEG_TIER_CNTL0__Y_COMP_ID_MASK 0x0000000CL |
5089 | #define UVD_JPEG_TIER_CNTL0__U_COMP_ID_MASK 0x00000030L |
5090 | #define UVD_JPEG_TIER_CNTL0__V_COMP_ID_MASK 0x000000C0L |
5091 | #define UVD_JPEG_TIER_CNTL0__Y_H_SAMP_FAC_MASK 0x00000700L |
5092 | #define UVD_JPEG_TIER_CNTL0__Y_V_SAMP_FAC_MASK 0x00003800L |
5093 | #define UVD_JPEG_TIER_CNTL0__U_H_SAMP_FAC_MASK 0x0001C000L |
5094 | #define UVD_JPEG_TIER_CNTL0__U_V_SAMP_FAC_MASK 0x000E0000L |
5095 | #define UVD_JPEG_TIER_CNTL0__V_H_SAMP_FAC_MASK 0x00700000L |
5096 | #define UVD_JPEG_TIER_CNTL0__V_V_SAMP_FAC_MASK 0x03800000L |
5097 | #define UVD_JPEG_TIER_CNTL0__Y_TQ_MASK 0x0C000000L |
5098 | #define UVD_JPEG_TIER_CNTL0__U_TQ_MASK 0x30000000L |
5099 | #define UVD_JPEG_TIER_CNTL0__V_TQ_MASK 0xC0000000L |
5100 | //UVD_JPEG_TIER_CNTL1 |
5101 | #define UVD_JPEG_TIER_CNTL1__SRC_WIDTH__SHIFT 0x0 |
5102 | #define UVD_JPEG_TIER_CNTL1__SRC_HEIGHT__SHIFT 0x10 |
5103 | #define UVD_JPEG_TIER_CNTL1__SRC_WIDTH_MASK 0x0000FFFFL |
5104 | #define UVD_JPEG_TIER_CNTL1__SRC_HEIGHT_MASK 0xFFFF0000L |
5105 | //UVD_JPEG_TIER_CNTL2 |
5106 | #define UVD_JPEG_TIER_CNTL2__TBL_ECS_SEL__SHIFT 0x0 |
5107 | #define UVD_JPEG_TIER_CNTL2__TBL_TYPE__SHIFT 0x1 |
5108 | #define UVD_JPEG_TIER_CNTL2__TQ__SHIFT 0x2 |
5109 | #define UVD_JPEG_TIER_CNTL2__TH__SHIFT 0x4 |
5110 | #define UVD_JPEG_TIER_CNTL2__TC__SHIFT 0x6 |
5111 | #define UVD_JPEG_TIER_CNTL2__TD__SHIFT 0x7 |
5112 | #define UVD_JPEG_TIER_CNTL2__TA__SHIFT 0xa |
5113 | #define UVD_JPEG_TIER_CNTL2__TIER2_HTBL_CNTLEN__SHIFT 0xe |
5114 | #define UVD_JPEG_TIER_CNTL2__DRI_VAL__SHIFT 0x10 |
5115 | #define UVD_JPEG_TIER_CNTL2__TBL_ECS_SEL_MASK 0x00000001L |
5116 | #define UVD_JPEG_TIER_CNTL2__TBL_TYPE_MASK 0x00000002L |
5117 | #define UVD_JPEG_TIER_CNTL2__TQ_MASK 0x0000000CL |
5118 | #define UVD_JPEG_TIER_CNTL2__TH_MASK 0x00000030L |
5119 | #define UVD_JPEG_TIER_CNTL2__TC_MASK 0x00000040L |
5120 | #define UVD_JPEG_TIER_CNTL2__TD_MASK 0x00000380L |
5121 | #define UVD_JPEG_TIER_CNTL2__TA_MASK 0x00001C00L |
5122 | #define UVD_JPEG_TIER_CNTL2__TIER2_HTBL_CNTLEN_MASK 0x00004000L |
5123 | #define UVD_JPEG_TIER_CNTL2__DRI_VAL_MASK 0xFFFF0000L |
5124 | //UVD_JPEG_TIER_STATUS |
5125 | #define UVD_JPEG_TIER_STATUS__BSI_FETCH_DONE__SHIFT 0x0 |
5126 | #define UVD_JPEG_TIER_STATUS__DECODE_DONE__SHIFT 0x1 |
5127 | #define UVD_JPEG_TIER_STATUS__BSI_FETCH_DONE_MASK 0x00000001L |
5128 | #define UVD_JPEG_TIER_STATUS__DECODE_DONE_MASK 0x00000002L |
5129 | //UVD_JPEG_OUTBUF_CNTL |
5130 | #define UVD_JPEG_OUTBUF_CNTL__OUTBUF_CNT__SHIFT 0x0 |
5131 | #define UVD_JPEG_OUTBUF_CNTL__HGT_ALIGN__SHIFT 0x2 |
5132 | #define UVD_JPEG_OUTBUF_CNTL__JPEG0_DECODE_DONE_FIX__SHIFT 0x6 |
5133 | #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_MAX_CNT__SHIFT 0x7 |
5134 | #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_TIMER__SHIFT 0x9 |
5135 | #define UVD_JPEG_OUTBUF_CNTL__OUTBUF_CNT_MASK 0x00000003L |
5136 | #define UVD_JPEG_OUTBUF_CNTL__HGT_ALIGN_MASK 0x00000004L |
5137 | #define UVD_JPEG_OUTBUF_CNTL__JPEG0_DECODE_DONE_FIX_MASK 0x00000040L |
5138 | #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_MAX_CNT_MASK 0x00000180L |
5139 | #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_TIMER_MASK 0x00001E00L |
5140 | //UVD_JPEG_OUTBUF_WPTR |
5141 | #define UVD_JPEG_OUTBUF_WPTR__OUTBUF_WPTR__SHIFT 0x0 |
5142 | #define UVD_JPEG_OUTBUF_WPTR__OUTBUF_WPTR_MASK 0xFFFFFFFFL |
5143 | //UVD_JPEG_OUTBUF_RPTR |
5144 | #define UVD_JPEG_OUTBUF_RPTR__OUTBUF_RPTR__SHIFT 0x0 |
5145 | #define UVD_JPEG_OUTBUF_RPTR__OUTBUF_RPTR_MASK 0xFFFFFFFFL |
5146 | //UVD_JPEG_PITCH |
5147 | #define UVD_JPEG_PITCH__PITCH__SHIFT 0x0 |
5148 | #define UVD_JPEG_PITCH__PITCH_MASK 0xFFFFFFFFL |
5149 | //UVD_JPEG_UV_PITCH |
5150 | #define UVD_JPEG_UV_PITCH__UV_PITCH__SHIFT 0x0 |
5151 | #define UVD_JPEG_UV_PITCH__UV_PITCH_MASK 0xFFFFFFFFL |
5152 | //JPEG_DEC_Y_GFX8_TILING_SURFACE |
5153 | #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0 |
5154 | #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2 |
5155 | #define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4 |
5156 | #define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6 |
5157 | #define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8 |
5158 | #define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd |
5159 | #define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10 |
5160 | #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L |
5161 | #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL |
5162 | #define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L |
5163 | #define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L |
5164 | #define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L |
5165 | #define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L |
5166 | #define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L |
5167 | //JPEG_DEC_UV_GFX8_TILING_SURFACE |
5168 | #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0 |
5169 | #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2 |
5170 | #define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4 |
5171 | #define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6 |
5172 | #define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8 |
5173 | #define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd |
5174 | #define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10 |
5175 | #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L |
5176 | #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL |
5177 | #define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L |
5178 | #define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L |
5179 | #define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L |
5180 | #define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L |
5181 | #define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L |
5182 | //JPEG_DEC_GFX8_ADDR_CONFIG |
5183 | #define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 |
5184 | #define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L |
5185 | //JPEG_DEC_Y_GFX10_TILING_SURFACE |
5186 | #define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 |
5187 | #define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL |
5188 | //JPEG_DEC_UV_GFX10_TILING_SURFACE |
5189 | #define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 |
5190 | #define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL |
5191 | //JPEG_DEC_GFX10_ADDR_CONFIG |
5192 | #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 |
5193 | #define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
5194 | #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 |
5195 | #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc |
5196 | #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 |
5197 | #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L |
5198 | #define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
5199 | #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L |
5200 | #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L |
5201 | #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L |
5202 | //JPEG_DEC_ADDR_MODE |
5203 | #define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0 |
5204 | #define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2 |
5205 | #define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc |
5206 | #define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L |
5207 | #define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL |
5208 | #define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L |
5209 | //UVD_JPEG_OUTPUT_XY |
5210 | #define UVD_JPEG_OUTPUT_XY__OUTPUT_X__SHIFT 0x0 |
5211 | #define UVD_JPEG_OUTPUT_XY__OUTPUT_Y__SHIFT 0x10 |
5212 | #define UVD_JPEG_OUTPUT_XY__OUTPUT_X_MASK 0x00003FFFL |
5213 | #define UVD_JPEG_OUTPUT_XY__OUTPUT_Y_MASK 0x3FFF0000L |
5214 | //UVD_JPEG_GPCOM_CMD |
5215 | #define UVD_JPEG_GPCOM_CMD__CMD__SHIFT 0x1 |
5216 | #define UVD_JPEG_GPCOM_CMD__CMD_MASK 0x0000000EL |
5217 | //UVD_JPEG_GPCOM_DATA0 |
5218 | #define UVD_JPEG_GPCOM_DATA0__DATA0__SHIFT 0x0 |
5219 | #define UVD_JPEG_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL |
5220 | //UVD_JPEG_GPCOM_DATA1 |
5221 | #define UVD_JPEG_GPCOM_DATA1__DATA1__SHIFT 0x0 |
5222 | #define UVD_JPEG_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL |
5223 | //UVD_JPEG_INDEX |
5224 | #define UVD_JPEG_INDEX__INDEX__SHIFT 0x0 |
5225 | #define UVD_JPEG_INDEX__INDEX_MASK 0x000001FFL |
5226 | //UVD_JPEG_DATA |
5227 | #define UVD_JPEG_DATA__DATA__SHIFT 0x0 |
5228 | #define UVD_JPEG_DATA__DATA_MASK 0xFFFFFFFFL |
5229 | //UVD_JPEG_SCRATCH1 |
5230 | #define UVD_JPEG_SCRATCH1__SCRATCH1__SHIFT 0x0 |
5231 | #define UVD_JPEG_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL |
5232 | //UVD_JPEG_DEC_SOFT_RST |
5233 | #define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET__SHIFT 0x0 |
5234 | #define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS__SHIFT 0x10 |
5235 | #define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET_MASK 0x00000001L |
5236 | #define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS_MASK 0x00010000L |
5237 | |
5238 | |
5239 | // addressBlock: uvd0_uvd_jrbc_dec |
5240 | //UVD_JRBC_RB_WPTR |
5241 | #define UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 |
5242 | #define UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L |
5243 | //UVD_JRBC_RB_CNTL |
5244 | #define UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 |
5245 | #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 |
5246 | #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 |
5247 | #define UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L |
5248 | #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L |
5249 | #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L |
5250 | //UVD_JRBC_IB_SIZE |
5251 | #define UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 |
5252 | #define UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L |
5253 | //UVD_JRBC_URGENT_CNTL |
5254 | #define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 |
5255 | #define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L |
5256 | //UVD_JRBC_RB_REF_DATA |
5257 | #define UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0 |
5258 | #define UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL |
5259 | //UVD_JRBC_RB_COND_RD_TIMER |
5260 | #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 |
5261 | #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 |
5262 | #define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 |
5263 | #define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 |
5264 | #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL |
5265 | #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L |
5266 | #define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L |
5267 | #define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L |
5268 | //UVD_JRBC_SOFT_RESET |
5269 | #define UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 |
5270 | #define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 |
5271 | #define UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L |
5272 | #define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L |
5273 | //UVD_JRBC_STATUS |
5274 | #define UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 |
5275 | #define UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 |
5276 | #define UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 |
5277 | #define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 |
5278 | #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 |
5279 | #define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 |
5280 | #define UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 |
5281 | #define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 |
5282 | #define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 |
5283 | #define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 |
5284 | #define UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa |
5285 | #define UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb |
5286 | #define UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc |
5287 | #define UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 |
5288 | #define UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 |
5289 | #define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L |
5290 | #define UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L |
5291 | #define UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L |
5292 | #define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L |
5293 | #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L |
5294 | #define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L |
5295 | #define UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L |
5296 | #define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L |
5297 | #define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L |
5298 | #define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L |
5299 | #define UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L |
5300 | #define UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L |
5301 | #define UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L |
5302 | #define UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L |
5303 | #define UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L |
5304 | //UVD_JRBC_RB_RPTR |
5305 | #define UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 |
5306 | #define UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L |
5307 | //UVD_JRBC_RB_BUF_STATUS |
5308 | #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 |
5309 | #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 |
5310 | #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 |
5311 | #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL |
5312 | #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L |
5313 | #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L |
5314 | //UVD_JRBC_IB_BUF_STATUS |
5315 | #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 |
5316 | #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 |
5317 | #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 |
5318 | #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL |
5319 | #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L |
5320 | #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L |
5321 | //UVD_JRBC_IB_SIZE_UPDATE |
5322 | #define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 |
5323 | #define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L |
5324 | //UVD_JRBC_IB_COND_RD_TIMER |
5325 | #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 |
5326 | #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 |
5327 | #define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 |
5328 | #define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 |
5329 | #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL |
5330 | #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L |
5331 | #define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L |
5332 | #define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L |
5333 | //UVD_JRBC_IB_REF_DATA |
5334 | #define UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0 |
5335 | #define UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL |
5336 | //UVD_JPEG_PREEMPT_CMD |
5337 | #define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 |
5338 | #define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 |
5339 | #define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 |
5340 | #define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L |
5341 | #define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L |
5342 | #define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L |
5343 | //UVD_JPEG_PREEMPT_FENCE_DATA0 |
5344 | #define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 |
5345 | #define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL |
5346 | //UVD_JPEG_PREEMPT_FENCE_DATA1 |
5347 | #define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 |
5348 | #define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL |
5349 | //UVD_JRBC_RB_SIZE |
5350 | #define UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4 |
5351 | #define UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L |
5352 | //UVD_JRBC_SCRATCH0 |
5353 | #define UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0 |
5354 | #define UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL |
5355 | |
5356 | |
5357 | // addressBlock: uvd0_uvd_jmi_dec |
5358 | //UVD_JADP_MCIF_URGENT_CTRL |
5359 | #define UVD_JADP_MCIF_URGENT_CTRL__WR_WATERMARK__SHIFT 0x0 |
5360 | #define UVD_JADP_MCIF_URGENT_CTRL__RD_WATERMARK__SHIFT 0x6 |
5361 | #define UVD_JADP_MCIF_URGENT_CTRL__WR_RD_URGENT_TIMER__SHIFT 0xb |
5362 | #define UVD_JADP_MCIF_URGENT_CTRL__WR_URGENT_PROG_STEP__SHIFT 0x11 |
5363 | #define UVD_JADP_MCIF_URGENT_CTRL__RD_URGENT_PROG_STEP__SHIFT 0x15 |
5364 | #define UVD_JADP_MCIF_URGENT_CTRL__WR_QOS_EN__SHIFT 0x19 |
5365 | #define UVD_JADP_MCIF_URGENT_CTRL__RD_QOS_EN__SHIFT 0x1a |
5366 | #define UVD_JADP_MCIF_URGENT_CTRL__WR_WATERMARK_MASK 0x0000003FL |
5367 | #define UVD_JADP_MCIF_URGENT_CTRL__RD_WATERMARK_MASK 0x000007C0L |
5368 | #define UVD_JADP_MCIF_URGENT_CTRL__WR_RD_URGENT_TIMER_MASK 0x0001F800L |
5369 | #define UVD_JADP_MCIF_URGENT_CTRL__WR_URGENT_PROG_STEP_MASK 0x001E0000L |
5370 | #define UVD_JADP_MCIF_URGENT_CTRL__RD_URGENT_PROG_STEP_MASK 0x01E00000L |
5371 | #define UVD_JADP_MCIF_URGENT_CTRL__WR_QOS_EN_MASK 0x02000000L |
5372 | #define UVD_JADP_MCIF_URGENT_CTRL__RD_QOS_EN_MASK 0x04000000L |
5373 | //UVD_JMI_URGENT_CTRL |
5374 | #define UVD_JMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0 |
5375 | #define UVD_JMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x4 |
5376 | #define UVD_JMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x10 |
5377 | #define UVD_JMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0x14 |
5378 | #define UVD_JMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L |
5379 | #define UVD_JMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x000000F0L |
5380 | #define UVD_JMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00010000L |
5381 | #define UVD_JMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00F00000L |
5382 | //UVD_JPEG_DEC_PF_CTRL |
5383 | #define UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS__SHIFT 0x0 |
5384 | #define UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING__SHIFT 0x1 |
5385 | #define UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS_MASK 0x00000001L |
5386 | #define UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING_MASK 0x00000002L |
5387 | //UVD_JPEG_ENC_PF_CTRL |
5388 | #define UVD_JPEG_ENC_PF_CTRL__ENC_PF_HANDLING_DIS__SHIFT 0x0 |
5389 | #define UVD_JPEG_ENC_PF_CTRL__ENC_PF_SW_GATING__SHIFT 0x1 |
5390 | #define UVD_JPEG_ENC_PF_CTRL__ENC_PF_HANDLING_DIS_MASK 0x00000001L |
5391 | #define UVD_JPEG_ENC_PF_CTRL__ENC_PF_SW_GATING_MASK 0x00000002L |
5392 | //UVD_JMI_CTRL |
5393 | #define UVD_JMI_CTRL__STALL_MC_ARB__SHIFT 0x0 |
5394 | #define UVD_JMI_CTRL__MASK_MC_URGENT__SHIFT 0x1 |
5395 | #define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2 |
5396 | #define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER__SHIFT 0x8 |
5397 | #define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER__SHIFT 0x10 |
5398 | #define UVD_JMI_CTRL__CRC_RESET__SHIFT 0x18 |
5399 | #define UVD_JMI_CTRL__CRC_SEL__SHIFT 0x19 |
5400 | #define UVD_JMI_CTRL__STALL_MC_ARB_MASK 0x00000001L |
5401 | #define UVD_JMI_CTRL__MASK_MC_URGENT_MASK 0x00000002L |
5402 | #define UVD_JMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000004L |
5403 | #define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER_MASK 0x0000FF00L |
5404 | #define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER_MASK 0x00FF0000L |
5405 | #define UVD_JMI_CTRL__CRC_RESET_MASK 0x01000000L |
5406 | #define UVD_JMI_CTRL__CRC_SEL_MASK 0x1E000000L |
5407 | //UVD_LMI_JRBC_CTRL |
5408 | #define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 |
5409 | #define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 |
5410 | #define UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 |
5411 | #define UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 |
5412 | #define UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT 0x14 |
5413 | #define UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT 0x16 |
5414 | #define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L |
5415 | #define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L |
5416 | #define UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L |
5417 | #define UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L |
5418 | #define UVD_LMI_JRBC_CTRL__RD_SWAP_MASK 0x00300000L |
5419 | #define UVD_LMI_JRBC_CTRL__WR_SWAP_MASK 0x00C00000L |
5420 | //UVD_LMI_JPEG_CTRL |
5421 | #define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 |
5422 | #define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 |
5423 | #define UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 |
5424 | #define UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 |
5425 | #define UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT 0x14 |
5426 | #define UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT 0x16 |
5427 | #define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L |
5428 | #define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L |
5429 | #define UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L |
5430 | #define UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L |
5431 | #define UVD_LMI_JPEG_CTRL__RD_SWAP_MASK 0x00300000L |
5432 | #define UVD_LMI_JPEG_CTRL__WR_SWAP_MASK 0x00C00000L |
5433 | //UVD_JMI_EJRBC_CTRL |
5434 | #define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 |
5435 | #define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 |
5436 | #define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 |
5437 | #define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 |
5438 | #define UVD_JMI_EJRBC_CTRL__RD_SWAP__SHIFT 0x14 |
5439 | #define UVD_JMI_EJRBC_CTRL__WR_SWAP__SHIFT 0x16 |
5440 | #define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L |
5441 | #define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L |
5442 | #define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L |
5443 | #define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L |
5444 | #define UVD_JMI_EJRBC_CTRL__RD_SWAP_MASK 0x00300000L |
5445 | #define UVD_JMI_EJRBC_CTRL__WR_SWAP_MASK 0x00C00000L |
5446 | //UVD_LMI_EJPEG_CTRL |
5447 | #define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 |
5448 | #define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 |
5449 | #define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 |
5450 | #define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 |
5451 | #define UVD_LMI_EJPEG_CTRL__RD_SWAP__SHIFT 0x14 |
5452 | #define UVD_LMI_EJPEG_CTRL__WR_SWAP__SHIFT 0x16 |
5453 | #define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L |
5454 | #define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L |
5455 | #define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L |
5456 | #define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L |
5457 | #define UVD_LMI_EJPEG_CTRL__RD_SWAP_MASK 0x00300000L |
5458 | #define UVD_LMI_EJPEG_CTRL__WR_SWAP_MASK 0x00C00000L |
5459 | //UVD_JMI_SCALER_CTRL |
5460 | #define UVD_JMI_SCALER_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 |
5461 | #define UVD_JMI_SCALER_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 |
5462 | #define UVD_JMI_SCALER_CTRL__RD_MAX_BURST__SHIFT 0x4 |
5463 | #define UVD_JMI_SCALER_CTRL__WR_MAX_BURST__SHIFT 0x8 |
5464 | #define UVD_JMI_SCALER_CTRL__RD_SWAP__SHIFT 0x14 |
5465 | #define UVD_JMI_SCALER_CTRL__WR_SWAP__SHIFT 0x16 |
5466 | #define UVD_JMI_SCALER_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L |
5467 | #define UVD_JMI_SCALER_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L |
5468 | #define UVD_JMI_SCALER_CTRL__RD_MAX_BURST_MASK 0x000000F0L |
5469 | #define UVD_JMI_SCALER_CTRL__WR_MAX_BURST_MASK 0x00000F00L |
5470 | #define UVD_JMI_SCALER_CTRL__RD_SWAP_MASK 0x00300000L |
5471 | #define UVD_JMI_SCALER_CTRL__WR_SWAP_MASK 0x00C00000L |
5472 | //JPEG_LMI_DROP |
5473 | #define JPEG_LMI_DROP__JPEG_WR_DROP__SHIFT 0x0 |
5474 | #define JPEG_LMI_DROP__JRBC_WR_DROP__SHIFT 0x1 |
5475 | #define JPEG_LMI_DROP__JPEG_RD_DROP__SHIFT 0x2 |
5476 | #define JPEG_LMI_DROP__JRBC_RD_DROP__SHIFT 0x3 |
5477 | #define JPEG_LMI_DROP__JPEG_WR_DROP_MASK 0x00000001L |
5478 | #define JPEG_LMI_DROP__JRBC_WR_DROP_MASK 0x00000002L |
5479 | #define JPEG_LMI_DROP__JPEG_RD_DROP_MASK 0x00000004L |
5480 | #define JPEG_LMI_DROP__JRBC_RD_DROP_MASK 0x00000008L |
5481 | //UVD_JMI_EJPEG_DROP |
5482 | #define UVD_JMI_EJPEG_DROP__EJRBC_RD_DROP__SHIFT 0x0 |
5483 | #define UVD_JMI_EJPEG_DROP__EJRBC_WR_DROP__SHIFT 0x1 |
5484 | #define UVD_JMI_EJPEG_DROP__EJPEG_RD_DROP__SHIFT 0x2 |
5485 | #define UVD_JMI_EJPEG_DROP__EJPEG_WR_DROP__SHIFT 0x3 |
5486 | #define UVD_JMI_EJPEG_DROP__SCALAR_RD_DROP__SHIFT 0x4 |
5487 | #define UVD_JMI_EJPEG_DROP__SCALAR_WR_DROP__SHIFT 0x5 |
5488 | #define UVD_JMI_EJPEG_DROP__EJRBC_RD_DROP_MASK 0x00000001L |
5489 | #define UVD_JMI_EJPEG_DROP__EJRBC_WR_DROP_MASK 0x00000002L |
5490 | #define UVD_JMI_EJPEG_DROP__EJPEG_RD_DROP_MASK 0x00000004L |
5491 | #define UVD_JMI_EJPEG_DROP__EJPEG_WR_DROP_MASK 0x00000008L |
5492 | #define UVD_JMI_EJPEG_DROP__SCALAR_RD_DROP_MASK 0x00000010L |
5493 | #define UVD_JMI_EJPEG_DROP__SCALAR_WR_DROP_MASK 0x00000020L |
5494 | //JPEG_MEMCHECK_CLAMPING |
5495 | #define JPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN__SHIFT 0xd |
5496 | #define JPEG_MEMCHECK_CLAMPING__JPEG2_WR_CLAMPING_EN__SHIFT 0xe |
5497 | #define JPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN__SHIFT 0x16 |
5498 | #define JPEG_MEMCHECK_CLAMPING__JPEG2_RD_CLAMPING_EN__SHIFT 0x17 |
5499 | #define JPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN__SHIFT 0x19 |
5500 | #define JPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN__SHIFT 0x1a |
5501 | #define JPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN__SHIFT 0x1f |
5502 | #define JPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN_MASK 0x00002000L |
5503 | #define JPEG_MEMCHECK_CLAMPING__JPEG2_WR_CLAMPING_EN_MASK 0x00004000L |
5504 | #define JPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN_MASK 0x00400000L |
5505 | #define JPEG_MEMCHECK_CLAMPING__JPEG2_RD_CLAMPING_EN_MASK 0x00800000L |
5506 | #define JPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN_MASK 0x02000000L |
5507 | #define JPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN_MASK 0x04000000L |
5508 | #define JPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN_MASK 0x80000000L |
5509 | //UVD_JMI_EJPEG_MEMCHECK_CLAMPING |
5510 | #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN__SHIFT 0x0 |
5511 | #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN__SHIFT 0x1 |
5512 | #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN__SHIFT 0x2 |
5513 | #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN__SHIFT 0x3 |
5514 | #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_RD_CLAMPING_EN__SHIFT 0x4 |
5515 | #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_WR_CLAMPING_EN__SHIFT 0x5 |
5516 | #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN__SHIFT 0x1f |
5517 | #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN_MASK 0x00000001L |
5518 | #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN_MASK 0x00000002L |
5519 | #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN_MASK 0x00000004L |
5520 | #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN_MASK 0x00000008L |
5521 | #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_RD_CLAMPING_EN_MASK 0x00000010L |
5522 | #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_WR_CLAMPING_EN_MASK 0x00000020L |
5523 | #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN_MASK 0x80000000L |
5524 | //UVD_LMI_JRBC_IB_VMID |
5525 | #define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 |
5526 | #define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 |
5527 | #define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 |
5528 | #define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL |
5529 | #define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L |
5530 | #define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L |
5531 | //UVD_LMI_JRBC_RB_VMID |
5532 | #define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 |
5533 | #define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 |
5534 | #define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 |
5535 | #define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL |
5536 | #define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L |
5537 | #define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L |
5538 | //UVD_LMI_JPEG_VMID |
5539 | #define UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT 0x0 |
5540 | #define UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT 0x4 |
5541 | #define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT 0x8 |
5542 | #define UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK 0x0000000FL |
5543 | #define UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK 0x000000F0L |
5544 | #define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK 0x00000F00L |
5545 | //UVD_JMI_ENC_JRBC_IB_VMID |
5546 | #define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 |
5547 | #define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 |
5548 | #define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 |
5549 | #define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL |
5550 | #define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L |
5551 | #define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L |
5552 | //UVD_JMI_ENC_JRBC_RB_VMID |
5553 | #define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 |
5554 | #define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 |
5555 | #define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 |
5556 | #define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL |
5557 | #define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L |
5558 | #define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L |
5559 | //UVD_JMI_ENC_JPEG_VMID |
5560 | #define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID__SHIFT 0x0 |
5561 | #define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID__SHIFT 0x5 |
5562 | #define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID__SHIFT 0xa |
5563 | #define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID__SHIFT 0xf |
5564 | #define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID__SHIFT 0x13 |
5565 | #define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID__SHIFT 0x17 |
5566 | #define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID_MASK 0x0000000FL |
5567 | #define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID_MASK 0x000001E0L |
5568 | #define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID_MASK 0x00003C00L |
5569 | #define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID_MASK 0x00078000L |
5570 | #define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID_MASK 0x00780000L |
5571 | #define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID_MASK 0x07800000L |
5572 | //JPEG_MEMCHECK_SAFE_ADDR |
5573 | #define JPEG_MEMCHECK_SAFE_ADDR__MEMCHECK_SAFE_ADDR__SHIFT 0x0 |
5574 | #define JPEG_MEMCHECK_SAFE_ADDR__MEMCHECK_SAFE_ADDR_MASK 0xFFFFFFFFL |
5575 | //JPEG_MEMCHECK_SAFE_ADDR_64BIT |
5576 | #define JPEG_MEMCHECK_SAFE_ADDR_64BIT__MEMCHECK_SAFE_ADDR_64BIT__SHIFT 0x0 |
5577 | #define JPEG_MEMCHECK_SAFE_ADDR_64BIT__MEMCHECK_SAFE_ADDR_64BIT_MASK 0xFFFFFFFFL |
5578 | //UVD_JMI_LAT_CTRL |
5579 | #define UVD_JMI_LAT_CTRL__SCALE__SHIFT 0x0 |
5580 | #define UVD_JMI_LAT_CTRL__MAX_START__SHIFT 0x8 |
5581 | #define UVD_JMI_LAT_CTRL__MIN_START__SHIFT 0x9 |
5582 | #define UVD_JMI_LAT_CTRL__AVG_START__SHIFT 0xa |
5583 | #define UVD_JMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb |
5584 | #define UVD_JMI_LAT_CTRL__SKIP__SHIFT 0x10 |
5585 | #define UVD_JMI_LAT_CTRL__SCALE_MASK 0x000000FFL |
5586 | #define UVD_JMI_LAT_CTRL__MAX_START_MASK 0x00000100L |
5587 | #define UVD_JMI_LAT_CTRL__MIN_START_MASK 0x00000200L |
5588 | #define UVD_JMI_LAT_CTRL__AVG_START_MASK 0x00000400L |
5589 | #define UVD_JMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L |
5590 | #define UVD_JMI_LAT_CTRL__SKIP_MASK 0x000F0000L |
5591 | //UVD_JMI_LAT_CNTR |
5592 | #define UVD_JMI_LAT_CNTR__MAX_LAT__SHIFT 0x0 |
5593 | #define UVD_JMI_LAT_CNTR__MIN_LAT__SHIFT 0x8 |
5594 | #define UVD_JMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL |
5595 | #define UVD_JMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L |
5596 | //UVD_JMI_AVG_LAT_CNTR |
5597 | #define UVD_JMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0 |
5598 | #define UVD_JMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8 |
5599 | #define UVD_JMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10 |
5600 | #define UVD_JMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL |
5601 | #define UVD_JMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L |
5602 | #define UVD_JMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L |
5603 | //UVD_JMI_PERFMON_CTRL |
5604 | #define UVD_JMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 |
5605 | #define UVD_JMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 |
5606 | #define UVD_JMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L |
5607 | #define UVD_JMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00000F00L |
5608 | //UVD_JMI_PERFMON_COUNT_LO |
5609 | #define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 |
5610 | #define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL |
5611 | //UVD_JMI_PERFMON_COUNT_HI |
5612 | #define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 |
5613 | #define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL |
5614 | //UVD_JMI_CLEAN_STATUS |
5615 | #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN__SHIFT 0x0 |
5616 | #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_RAW__SHIFT 0x1 |
5617 | #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN__SHIFT 0x2 |
5618 | #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_RAW__SHIFT 0x3 |
5619 | #define UVD_JMI_CLEAN_STATUS__DJRBC_READ_CLEAN__SHIFT 0x4 |
5620 | #define UVD_JMI_CLEAN_STATUS__EJRBC_READ_CLEAN__SHIFT 0x5 |
5621 | #define UVD_JMI_CLEAN_STATUS__JPEG_READ_CLEAN__SHIFT 0x6 |
5622 | #define UVD_JMI_CLEAN_STATUS__PEL_READ_CLEAN__SHIFT 0x7 |
5623 | #define UVD_JMI_CLEAN_STATUS__SCALAR_READ_CLEAN__SHIFT 0x8 |
5624 | #define UVD_JMI_CLEAN_STATUS__DJRBC_WRITE_CLEAN__SHIFT 0x9 |
5625 | #define UVD_JMI_CLEAN_STATUS__EJRBC_WRITE_CLEAN__SHIFT 0xa |
5626 | #define UVD_JMI_CLEAN_STATUS__BS_WRITE_CLEAN__SHIFT 0xb |
5627 | #define UVD_JMI_CLEAN_STATUS__JPEG_WRITE_CLEAN__SHIFT 0xc |
5628 | #define UVD_JMI_CLEAN_STATUS__SCALAR_WRITE_CLEAN__SHIFT 0xd |
5629 | #define UVD_JMI_CLEAN_STATUS__MC_WRITE_PENDING__SHIFT 0xe |
5630 | #define UVD_JMI_CLEAN_STATUS__JPEG2_WRITE_CLEAN__SHIFT 0xf |
5631 | #define UVD_JMI_CLEAN_STATUS__JPEG2_READ_CLEAN__SHIFT 0x10 |
5632 | #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_MASK 0x00000001L |
5633 | #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_RAW_MASK 0x00000002L |
5634 | #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_MASK 0x00000004L |
5635 | #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_RAW_MASK 0x00000008L |
5636 | #define UVD_JMI_CLEAN_STATUS__DJRBC_READ_CLEAN_MASK 0x00000010L |
5637 | #define UVD_JMI_CLEAN_STATUS__EJRBC_READ_CLEAN_MASK 0x00000020L |
5638 | #define UVD_JMI_CLEAN_STATUS__JPEG_READ_CLEAN_MASK 0x00000040L |
5639 | #define UVD_JMI_CLEAN_STATUS__PEL_READ_CLEAN_MASK 0x00000080L |
5640 | #define UVD_JMI_CLEAN_STATUS__SCALAR_READ_CLEAN_MASK 0x00000100L |
5641 | #define UVD_JMI_CLEAN_STATUS__DJRBC_WRITE_CLEAN_MASK 0x00000200L |
5642 | #define UVD_JMI_CLEAN_STATUS__EJRBC_WRITE_CLEAN_MASK 0x00000400L |
5643 | #define UVD_JMI_CLEAN_STATUS__BS_WRITE_CLEAN_MASK 0x00000800L |
5644 | #define UVD_JMI_CLEAN_STATUS__JPEG_WRITE_CLEAN_MASK 0x00001000L |
5645 | #define UVD_JMI_CLEAN_STATUS__SCALAR_WRITE_CLEAN_MASK 0x00002000L |
5646 | #define UVD_JMI_CLEAN_STATUS__MC_WRITE_PENDING_MASK 0x00004000L |
5647 | #define UVD_JMI_CLEAN_STATUS__JPEG2_WRITE_CLEAN_MASK 0x00008000L |
5648 | #define UVD_JMI_CLEAN_STATUS__JPEG2_READ_CLEAN_MASK 0x00010000L |
5649 | //UVD_LMI_JPEG_READ_64BIT_BAR_LOW |
5650 | #define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
5651 | #define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
5652 | //UVD_LMI_JPEG_READ_64BIT_BAR_HIGH |
5653 | #define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
5654 | #define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
5655 | //UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW |
5656 | #define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
5657 | #define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
5658 | //UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH |
5659 | #define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
5660 | #define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
5661 | //UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW |
5662 | #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
5663 | #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
5664 | //UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH |
5665 | #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
5666 | #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
5667 | //UVD_LMI_JRBC_RB_64BIT_BAR_LOW |
5668 | #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
5669 | #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
5670 | //UVD_LMI_JRBC_RB_64BIT_BAR_HIGH |
5671 | #define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
5672 | #define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
5673 | //UVD_LMI_JRBC_IB_64BIT_BAR_LOW |
5674 | #define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
5675 | #define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
5676 | //UVD_LMI_JRBC_IB_64BIT_BAR_HIGH |
5677 | #define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
5678 | #define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
5679 | //UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW |
5680 | #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
5681 | #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
5682 | //UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH |
5683 | #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
5684 | #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
5685 | //UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW |
5686 | #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
5687 | #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
5688 | //UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH |
5689 | #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
5690 | #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
5691 | //UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW |
5692 | #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
5693 | #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
5694 | //UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH |
5695 | #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
5696 | #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
5697 | //UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW |
5698 | #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
5699 | #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
5700 | //UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH |
5701 | #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
5702 | #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
5703 | //UVD_JMI_PEL_RD_64BIT_BAR_LOW |
5704 | #define UVD_JMI_PEL_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
5705 | #define UVD_JMI_PEL_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
5706 | //UVD_JMI_PEL_RD_64BIT_BAR_HIGH |
5707 | #define UVD_JMI_PEL_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
5708 | #define UVD_JMI_PEL_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
5709 | //UVD_JMI_BS_WR_64BIT_BAR_LOW |
5710 | #define UVD_JMI_BS_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
5711 | #define UVD_JMI_BS_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
5712 | //UVD_JMI_BS_WR_64BIT_BAR_HIGH |
5713 | #define UVD_JMI_BS_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
5714 | #define UVD_JMI_BS_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
5715 | //UVD_JMI_SCALAR_RD_64BIT_BAR_LOW |
5716 | #define UVD_JMI_SCALAR_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
5717 | #define UVD_JMI_SCALAR_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
5718 | //UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH |
5719 | #define UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
5720 | #define UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
5721 | //UVD_JMI_SCALAR_WR_64BIT_BAR_LOW |
5722 | #define UVD_JMI_SCALAR_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
5723 | #define UVD_JMI_SCALAR_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
5724 | //UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH |
5725 | #define UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
5726 | #define UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
5727 | //UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW |
5728 | #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
5729 | #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
5730 | //UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH |
5731 | #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
5732 | #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
5733 | //UVD_LMI_EJRBC_RB_64BIT_BAR_LOW |
5734 | #define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
5735 | #define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
5736 | //UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH |
5737 | #define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
5738 | #define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
5739 | //UVD_LMI_EJRBC_IB_64BIT_BAR_LOW |
5740 | #define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
5741 | #define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
5742 | //UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH |
5743 | #define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
5744 | #define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
5745 | //UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW |
5746 | #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
5747 | #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
5748 | //UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH |
5749 | #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
5750 | #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
5751 | //UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW |
5752 | #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
5753 | #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
5754 | //UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH |
5755 | #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
5756 | #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
5757 | //UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW |
5758 | #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
5759 | #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
5760 | //UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH |
5761 | #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
5762 | #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
5763 | //UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW |
5764 | #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
5765 | #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
5766 | //UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH |
5767 | #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
5768 | #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
5769 | //UVD_LMI_JPEG_PREEMPT_VMID |
5770 | #define UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 |
5771 | #define UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL |
5772 | //UVD_LMI_ENC_JPEG_PREEMPT_VMID |
5773 | #define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 |
5774 | #define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL |
5775 | //UVD_LMI_JPEG2_VMID |
5776 | #define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID__SHIFT 0x0 |
5777 | #define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID__SHIFT 0x4 |
5778 | #define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID_MASK 0x0000000FL |
5779 | #define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID_MASK 0x000000F0L |
5780 | //UVD_LMI_JPEG2_READ_64BIT_BAR_LOW |
5781 | #define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
5782 | #define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
5783 | //UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH |
5784 | #define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
5785 | #define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
5786 | //UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW |
5787 | #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
5788 | #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
5789 | //UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH |
5790 | #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
5791 | #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
5792 | //UVD_LMI_JPEG_CTRL2 |
5793 | #define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN__SHIFT 0x0 |
5794 | #define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN__SHIFT 0x1 |
5795 | #define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST__SHIFT 0x4 |
5796 | #define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST__SHIFT 0x8 |
5797 | #define UVD_LMI_JPEG_CTRL2__RD_SWAP__SHIFT 0x14 |
5798 | #define UVD_LMI_JPEG_CTRL2__WR_SWAP__SHIFT 0x16 |
5799 | #define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN_MASK 0x00000001L |
5800 | #define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN_MASK 0x00000002L |
5801 | #define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST_MASK 0x000000F0L |
5802 | #define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST_MASK 0x00000F00L |
5803 | #define UVD_LMI_JPEG_CTRL2__RD_SWAP_MASK 0x00300000L |
5804 | #define UVD_LMI_JPEG_CTRL2__WR_SWAP_MASK 0x00C00000L |
5805 | //UVD_JMI_DEC_SWAP_CNTL |
5806 | #define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 |
5807 | #define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 |
5808 | #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 |
5809 | #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 |
5810 | #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 |
5811 | #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa |
5812 | #define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc |
5813 | #define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT 0xe |
5814 | #define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT 0x10 |
5815 | #define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L |
5816 | #define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL |
5817 | #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L |
5818 | #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L |
5819 | #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L |
5820 | #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L |
5821 | #define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L |
5822 | #define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK 0x0000C000L |
5823 | #define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK 0x00030000L |
5824 | //UVD_JMI_ENC_SWAP_CNTL |
5825 | #define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 |
5826 | #define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 |
5827 | #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 |
5828 | #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 |
5829 | #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 |
5830 | #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa |
5831 | #define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc |
5832 | #define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP__SHIFT 0xe |
5833 | #define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP__SHIFT 0x10 |
5834 | #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP__SHIFT 0x12 |
5835 | #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP__SHIFT 0x14 |
5836 | #define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP__SHIFT 0x16 |
5837 | #define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L |
5838 | #define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL |
5839 | #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L |
5840 | #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L |
5841 | #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L |
5842 | #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L |
5843 | #define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L |
5844 | #define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP_MASK 0x0000C000L |
5845 | #define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP_MASK 0x00030000L |
5846 | #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP_MASK 0x000C0000L |
5847 | #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP_MASK 0x00300000L |
5848 | #define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP_MASK 0x00C00000L |
5849 | //UVD_JMI_CNTL |
5850 | #define UVD_JMI_CNTL__SOFT_RESET__SHIFT 0x0 |
5851 | #define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8 |
5852 | #define UVD_JMI_CNTL__SOFT_RESET_MASK 0x00000001L |
5853 | #define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX_MASK 0x0003FF00L |
5854 | //UVD_JMI_ATOMIC_CNTL |
5855 | #define UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en__SHIFT 0x0 |
5856 | #define UVD_JMI_ATOMIC_CNTL__atomic_max_burst__SHIFT 0x1 |
5857 | #define UVD_JMI_ATOMIC_CNTL__atomic_wr_drop__SHIFT 0x5 |
5858 | #define UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en__SHIFT 0x6 |
5859 | #define UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG__SHIFT 0x7 |
5860 | #define UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE__SHIFT 0xb |
5861 | #define UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en_MASK 0x00000001L |
5862 | #define UVD_JMI_ATOMIC_CNTL__atomic_max_burst_MASK 0x0000001EL |
5863 | #define UVD_JMI_ATOMIC_CNTL__atomic_wr_drop_MASK 0x00000020L |
5864 | #define UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en_MASK 0x00000040L |
5865 | #define UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG_MASK 0x00000780L |
5866 | #define UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE_MASK 0x00000800L |
5867 | //UVD_JMI_ATOMIC_CNTL2 |
5868 | #define UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap__SHIFT 0x10 |
5869 | #define UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP__SHIFT 0x18 |
5870 | #define UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap_MASK 0x00FF0000L |
5871 | #define UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP_MASK 0xFF000000L |
5872 | //UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW |
5873 | #define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
5874 | #define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
5875 | //UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH |
5876 | #define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
5877 | #define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
5878 | //UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW |
5879 | #define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
5880 | #define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
5881 | //UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH |
5882 | #define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
5883 | #define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
5884 | //JPEG2_LMI_DROP |
5885 | #define JPEG2_LMI_DROP__JPEG2_WR_DROP__SHIFT 0x0 |
5886 | #define JPEG2_LMI_DROP__JPEG2_RD_DROP__SHIFT 0x1 |
5887 | #define JPEG2_LMI_DROP__JPEG2_WR_DROP_MASK 0x00000001L |
5888 | #define JPEG2_LMI_DROP__JPEG2_RD_DROP_MASK 0x00000002L |
5889 | //UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW |
5890 | #define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
5891 | #define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
5892 | //UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH |
5893 | #define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
5894 | #define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
5895 | //UVD_JMI_DEC_SWAP_CNTL2 |
5896 | #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP__SHIFT 0x0 |
5897 | #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP__SHIFT 0x2 |
5898 | #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP_MASK 0x00000003L |
5899 | #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP_MASK 0x0000000CL |
5900 | //UVD_JMI_DJPEG_RAS_CNTL |
5901 | #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_IH_EN__SHIFT 0x0 |
5902 | #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_PMI_EN__SHIFT 0x1 |
5903 | #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_REARM__SHIFT 0x2 |
5904 | #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_STALL_EN__SHIFT 0x3 |
5905 | #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_READY__SHIFT 0x4 |
5906 | #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_IH_EN_MASK 0x00000001L |
5907 | #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_PMI_EN_MASK 0x00000002L |
5908 | #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_REARM_MASK 0x00000004L |
5909 | #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_STALL_EN_MASK 0x00000008L |
5910 | #define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_READY_MASK 0x00000010L |
5911 | //UVD_JMI_EJPEG_RAS_CNTL |
5912 | #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_IH_EN__SHIFT 0x0 |
5913 | #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_PMI_EN__SHIFT 0x1 |
5914 | #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_REARM__SHIFT 0x2 |
5915 | #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_STALL_EN__SHIFT 0x3 |
5916 | #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_READY__SHIFT 0x4 |
5917 | #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_IH_EN_MASK 0x00000001L |
5918 | #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_PMI_EN_MASK 0x00000002L |
5919 | #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_REARM_MASK 0x00000004L |
5920 | #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_STALL_EN_MASK 0x00000008L |
5921 | #define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_READY_MASK 0x00000010L |
5922 | //UVD_JPEG_DEC2_PF_CTRL |
5923 | #define UVD_JPEG_DEC2_PF_CTRL__DEC2_PF_HANDLING_DIS__SHIFT 0x0 |
5924 | #define UVD_JPEG_DEC2_PF_CTRL__DEC2_PF_SW_GATING__SHIFT 0x1 |
5925 | #define UVD_JPEG_DEC2_PF_CTRL__DEC2_PF_HANDLING_DIS_MASK 0x00000001L |
5926 | #define UVD_JPEG_DEC2_PF_CTRL__DEC2_PF_SW_GATING_MASK 0x00000002L |
5927 | |
5928 | |
5929 | // addressBlock: uvd0_uvd_jpeg_common_dec |
5930 | //JPEG_SOFT_RESET_STATUS |
5931 | #define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS__SHIFT 0x0 |
5932 | #define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS__SHIFT 0x1 |
5933 | #define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS__SHIFT 0x2 |
5934 | #define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS__SHIFT 0x3 |
5935 | #define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS__SHIFT 0x4 |
5936 | #define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS__SHIFT 0x5 |
5937 | #define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS_MASK 0x00000001L |
5938 | #define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS_MASK 0x00000002L |
5939 | #define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS_MASK 0x00000004L |
5940 | #define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS_MASK 0x00000008L |
5941 | #define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS_MASK 0x00000010L |
5942 | #define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS_MASK 0x00000020L |
5943 | //JPEG_SYS_INT_EN |
5944 | #define JPEG_SYS_INT_EN__DJPEG_CORE__SHIFT 0x0 |
5945 | #define JPEG_SYS_INT_EN__DJRBC__SHIFT 0x1 |
5946 | #define JPEG_SYS_INT_EN__DJPEG_PF_RPT__SHIFT 0x2 |
5947 | #define JPEG_SYS_INT_EN__EJPEG_PF_RPT__SHIFT 0x3 |
5948 | #define JPEG_SYS_INT_EN__EJPEG_CORE__SHIFT 0x4 |
5949 | #define JPEG_SYS_INT_EN__EJRBC__SHIFT 0x5 |
5950 | #define JPEG_SYS_INT_EN__DJPEG_CORE2__SHIFT 0x6 |
5951 | #define JPEG_SYS_INT_EN__DJPEG2_PF_RPT__SHIFT 0x7 |
5952 | #define JPEG_SYS_INT_EN__DJPEG_RAS_CNTL__SHIFT 0x8 |
5953 | #define JPEG_SYS_INT_EN__EJPEG_RAS_CNTL__SHIFT 0x9 |
5954 | #define JPEG_SYS_INT_EN__DJPEG_CORE_MASK 0x00000001L |
5955 | #define JPEG_SYS_INT_EN__DJRBC_MASK 0x00000002L |
5956 | #define JPEG_SYS_INT_EN__DJPEG_PF_RPT_MASK 0x00000004L |
5957 | #define JPEG_SYS_INT_EN__EJPEG_PF_RPT_MASK 0x00000008L |
5958 | #define JPEG_SYS_INT_EN__EJPEG_CORE_MASK 0x00000010L |
5959 | #define JPEG_SYS_INT_EN__EJRBC_MASK 0x00000020L |
5960 | #define JPEG_SYS_INT_EN__DJPEG_CORE2_MASK 0x00000040L |
5961 | #define JPEG_SYS_INT_EN__DJPEG2_PF_RPT_MASK 0x00000080L |
5962 | #define JPEG_SYS_INT_EN__DJPEG_RAS_CNTL_MASK 0x00000100L |
5963 | #define JPEG_SYS_INT_EN__EJPEG_RAS_CNTL_MASK 0x00000200L |
5964 | //JPEG_SYS_INT_STATUS |
5965 | #define JPEG_SYS_INT_STATUS__DJPEG_CORE__SHIFT 0x0 |
5966 | #define JPEG_SYS_INT_STATUS__DJRBC__SHIFT 0x1 |
5967 | #define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT__SHIFT 0x2 |
5968 | #define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT__SHIFT 0x3 |
5969 | #define JPEG_SYS_INT_STATUS__EJPEG_CORE__SHIFT 0x4 |
5970 | #define JPEG_SYS_INT_STATUS__EJRBC__SHIFT 0x5 |
5971 | #define JPEG_SYS_INT_STATUS__DJPEG_CORE2__SHIFT 0x6 |
5972 | #define JPEG_SYS_INT_STATUS__DJPEG2_PF_RPT__SHIFT 0x7 |
5973 | #define JPEG_SYS_INT_STATUS__DJPEG_RAS_CNTL__SHIFT 0x8 |
5974 | #define JPEG_SYS_INT_STATUS__EJPEG_RAS_CNTL__SHIFT 0x9 |
5975 | #define JPEG_SYS_INT_STATUS__DJPEG_CORE_MASK 0x00000001L |
5976 | #define JPEG_SYS_INT_STATUS__DJRBC_MASK 0x00000002L |
5977 | #define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT_MASK 0x00000004L |
5978 | #define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT_MASK 0x00000008L |
5979 | #define JPEG_SYS_INT_STATUS__EJPEG_CORE_MASK 0x00000010L |
5980 | #define JPEG_SYS_INT_STATUS__EJRBC_MASK 0x00000020L |
5981 | #define JPEG_SYS_INT_STATUS__DJPEG_CORE2_MASK 0x00000040L |
5982 | #define JPEG_SYS_INT_STATUS__DJPEG2_PF_RPT_MASK 0x00000080L |
5983 | #define JPEG_SYS_INT_STATUS__DJPEG_RAS_CNTL_MASK 0x00000100L |
5984 | #define JPEG_SYS_INT_STATUS__EJPEG_RAS_CNTL_MASK 0x00000200L |
5985 | //JPEG_SYS_INT_ACK |
5986 | #define JPEG_SYS_INT_ACK__DJPEG_CORE__SHIFT 0x0 |
5987 | #define JPEG_SYS_INT_ACK__DJRBC__SHIFT 0x1 |
5988 | #define JPEG_SYS_INT_ACK__DJPEG_PF_RPT__SHIFT 0x2 |
5989 | #define JPEG_SYS_INT_ACK__EJPEG_PF_RPT__SHIFT 0x3 |
5990 | #define JPEG_SYS_INT_ACK__EJPEG_CORE__SHIFT 0x4 |
5991 | #define JPEG_SYS_INT_ACK__EJRBC__SHIFT 0x5 |
5992 | #define JPEG_SYS_INT_ACK__DJPEG_CORE2__SHIFT 0x6 |
5993 | #define JPEG_SYS_INT_ACK__DJPEG2_PF_RPT__SHIFT 0x7 |
5994 | #define JPEG_SYS_INT_ACK__DJPEG_RAS_CNTL__SHIFT 0x8 |
5995 | #define JPEG_SYS_INT_ACK__EJPEG_RAS_CNTL__SHIFT 0x9 |
5996 | #define JPEG_SYS_INT_ACK__DJPEG_CORE_MASK 0x00000001L |
5997 | #define JPEG_SYS_INT_ACK__DJRBC_MASK 0x00000002L |
5998 | #define JPEG_SYS_INT_ACK__DJPEG_PF_RPT_MASK 0x00000004L |
5999 | #define JPEG_SYS_INT_ACK__EJPEG_PF_RPT_MASK 0x00000008L |
6000 | #define JPEG_SYS_INT_ACK__EJPEG_CORE_MASK 0x00000010L |
6001 | #define JPEG_SYS_INT_ACK__EJRBC_MASK 0x00000020L |
6002 | #define JPEG_SYS_INT_ACK__DJPEG_CORE2_MASK 0x00000040L |
6003 | #define JPEG_SYS_INT_ACK__DJPEG2_PF_RPT_MASK 0x00000080L |
6004 | #define JPEG_SYS_INT_ACK__DJPEG_RAS_CNTL_MASK 0x00000100L |
6005 | #define JPEG_SYS_INT_ACK__EJPEG_RAS_CNTL_MASK 0x00000200L |
6006 | //JPEG_MEMCHECK_SYS_INT_EN |
6007 | #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_RD_ERR_EN__SHIFT 0x0 |
6008 | #define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_RD_ERR_EN__SHIFT 0x1 |
6009 | #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH_RD_ERR_EN__SHIFT 0x2 |
6010 | #define JPEG_MEMCHECK_SYS_INT_EN__PELFETCH_RD_ERR_EN__SHIFT 0x3 |
6011 | #define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_RD_ERR_EN__SHIFT 0x4 |
6012 | #define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_RD_ERR_EN__SHIFT 0x5 |
6013 | #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_WR_ERR_EN__SHIFT 0x6 |
6014 | #define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_WR_ERR_EN__SHIFT 0x7 |
6015 | #define JPEG_MEMCHECK_SYS_INT_EN__BS_WR_ERR_EN__SHIFT 0x8 |
6016 | #define JPEG_MEMCHECK_SYS_INT_EN__OBUF_WR_ERR_EN__SHIFT 0x9 |
6017 | #define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_WR_ERR_EN__SHIFT 0xa |
6018 | #define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_WR_ERR_EN__SHIFT 0xb |
6019 | #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_RD_ERR_EN_MASK 0x00000001L |
6020 | #define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_RD_ERR_EN_MASK 0x00000002L |
6021 | #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH_RD_ERR_EN_MASK 0x00000004L |
6022 | #define JPEG_MEMCHECK_SYS_INT_EN__PELFETCH_RD_ERR_EN_MASK 0x00000008L |
6023 | #define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_RD_ERR_EN_MASK 0x00000010L |
6024 | #define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_RD_ERR_EN_MASK 0x00000020L |
6025 | #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_WR_ERR_EN_MASK 0x00000040L |
6026 | #define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_WR_ERR_EN_MASK 0x00000080L |
6027 | #define JPEG_MEMCHECK_SYS_INT_EN__BS_WR_ERR_EN_MASK 0x00000100L |
6028 | #define JPEG_MEMCHECK_SYS_INT_EN__OBUF_WR_ERR_EN_MASK 0x00000200L |
6029 | #define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_WR_ERR_EN_MASK 0x00000400L |
6030 | #define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_WR_ERR_EN_MASK 0x00000800L |
6031 | //JPEG_MEMCHECK_SYS_INT_STAT |
6032 | #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_HI_ERR__SHIFT 0x0 |
6033 | #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_LO_ERR__SHIFT 0x1 |
6034 | #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_HI_ERR__SHIFT 0x2 |
6035 | #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_LO_ERR__SHIFT 0x3 |
6036 | #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_HI_ERR__SHIFT 0x4 |
6037 | #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_LO_ERR__SHIFT 0x5 |
6038 | #define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_HI_ERR__SHIFT 0x6 |
6039 | #define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_LO_ERR__SHIFT 0x7 |
6040 | #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_HI_ERR__SHIFT 0x8 |
6041 | #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_LO_ERR__SHIFT 0x9 |
6042 | #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_HI_ERR__SHIFT 0xa |
6043 | #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_LO_ERR__SHIFT 0xb |
6044 | #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_HI_ERR__SHIFT 0xc |
6045 | #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_LO_ERR__SHIFT 0xd |
6046 | #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_HI_ERR__SHIFT 0xe |
6047 | #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_LO_ERR__SHIFT 0xf |
6048 | #define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_HI_ERR__SHIFT 0x10 |
6049 | #define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_LO_ERR__SHIFT 0x11 |
6050 | #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_HI_ERR__SHIFT 0x12 |
6051 | #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_LO_ERR__SHIFT 0x13 |
6052 | #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_HI_ERR__SHIFT 0x14 |
6053 | #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_LO_ERR__SHIFT 0x15 |
6054 | #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_HI_ERR__SHIFT 0x16 |
6055 | #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_LO_ERR__SHIFT 0x17 |
6056 | #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_HI_ERR_MASK 0x00000001L |
6057 | #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_LO_ERR_MASK 0x00000002L |
6058 | #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_HI_ERR_MASK 0x00000004L |
6059 | #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_LO_ERR_MASK 0x00000008L |
6060 | #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_HI_ERR_MASK 0x00000010L |
6061 | #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_LO_ERR_MASK 0x00000020L |
6062 | #define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_HI_ERR_MASK 0x00000040L |
6063 | #define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_LO_ERR_MASK 0x00000080L |
6064 | #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_HI_ERR_MASK 0x00000100L |
6065 | #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_LO_ERR_MASK 0x00000200L |
6066 | #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_HI_ERR_MASK 0x00000400L |
6067 | #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_LO_ERR_MASK 0x00000800L |
6068 | #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_HI_ERR_MASK 0x00001000L |
6069 | #define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_LO_ERR_MASK 0x00002000L |
6070 | #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_HI_ERR_MASK 0x00004000L |
6071 | #define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_LO_ERR_MASK 0x00008000L |
6072 | #define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_HI_ERR_MASK 0x00010000L |
6073 | #define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_LO_ERR_MASK 0x00020000L |
6074 | #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_HI_ERR_MASK 0x00040000L |
6075 | #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_LO_ERR_MASK 0x00080000L |
6076 | #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_HI_ERR_MASK 0x00100000L |
6077 | #define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_LO_ERR_MASK 0x00200000L |
6078 | #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_HI_ERR_MASK 0x00400000L |
6079 | #define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_LO_ERR_MASK 0x00800000L |
6080 | //JPEG_MEMCHECK_SYS_INT_ACK |
6081 | #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_HI_ERR__SHIFT 0x0 |
6082 | #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_LO_ERR__SHIFT 0x1 |
6083 | #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_HI_ERR__SHIFT 0x2 |
6084 | #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_LO_ERR__SHIFT 0x3 |
6085 | #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_HI_ERR__SHIFT 0x4 |
6086 | #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_LO_ERR__SHIFT 0x5 |
6087 | #define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_HI_ERR__SHIFT 0x6 |
6088 | #define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_LO_ERR__SHIFT 0x7 |
6089 | #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_HI_ERR__SHIFT 0x8 |
6090 | #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_LO_ERR__SHIFT 0x9 |
6091 | #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_HI_ERR__SHIFT 0xa |
6092 | #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_LO_ERR__SHIFT 0xb |
6093 | #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_HI_ERR__SHIFT 0xc |
6094 | #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_LO_ERR__SHIFT 0xd |
6095 | #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_HI_ERR__SHIFT 0xe |
6096 | #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_LO_ERR__SHIFT 0xf |
6097 | #define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_HI_ERR__SHIFT 0x10 |
6098 | #define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_LO_ERR__SHIFT 0x11 |
6099 | #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_HI_ERR__SHIFT 0x12 |
6100 | #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_LO_ERR__SHIFT 0x13 |
6101 | #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_HI_ERR__SHIFT 0x14 |
6102 | #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_LO_ERR__SHIFT 0x15 |
6103 | #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_HI_ERR__SHIFT 0x16 |
6104 | #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_LO_ERR__SHIFT 0x17 |
6105 | #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_HI_ERR_MASK 0x00000001L |
6106 | #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_LO_ERR_MASK 0x00000002L |
6107 | #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_HI_ERR_MASK 0x00000004L |
6108 | #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_LO_ERR_MASK 0x00000008L |
6109 | #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_HI_ERR_MASK 0x00000010L |
6110 | #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_LO_ERR_MASK 0x00000020L |
6111 | #define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_HI_ERR_MASK 0x00000040L |
6112 | #define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_LO_ERR_MASK 0x00000080L |
6113 | #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_HI_ERR_MASK 0x00000100L |
6114 | #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_LO_ERR_MASK 0x00000200L |
6115 | #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_HI_ERR_MASK 0x00000400L |
6116 | #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_LO_ERR_MASK 0x00000800L |
6117 | #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_HI_ERR_MASK 0x00001000L |
6118 | #define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_LO_ERR_MASK 0x00002000L |
6119 | #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_HI_ERR_MASK 0x00004000L |
6120 | #define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_LO_ERR_MASK 0x00008000L |
6121 | #define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_HI_ERR_MASK 0x00010000L |
6122 | #define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_LO_ERR_MASK 0x00020000L |
6123 | #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_HI_ERR_MASK 0x00040000L |
6124 | #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_LO_ERR_MASK 0x00080000L |
6125 | #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_HI_ERR_MASK 0x00100000L |
6126 | #define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_LO_ERR_MASK 0x00200000L |
6127 | #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_HI_ERR_MASK 0x00400000L |
6128 | #define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_LO_ERR_MASK 0x00800000L |
6129 | //JPEG_MASTINT_EN |
6130 | #define JPEG_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 |
6131 | #define JPEG_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 |
6132 | #define JPEG_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L |
6133 | #define JPEG_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L |
6134 | //JPEG_IH_CTRL |
6135 | #define JPEG_IH_CTRL__IH_SOFT_RESET__SHIFT 0x0 |
6136 | #define JPEG_IH_CTRL__IH_STALL_EN__SHIFT 0x1 |
6137 | #define JPEG_IH_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 |
6138 | #define JPEG_IH_CTRL__IH_VMID__SHIFT 0x3 |
6139 | #define JPEG_IH_CTRL__IH_USER_DATA__SHIFT 0x7 |
6140 | #define JPEG_IH_CTRL__IH_RINGID__SHIFT 0x13 |
6141 | #define JPEG_IH_CTRL__IH_SOFT_RESET_MASK 0x00000001L |
6142 | #define JPEG_IH_CTRL__IH_STALL_EN_MASK 0x00000002L |
6143 | #define JPEG_IH_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L |
6144 | #define JPEG_IH_CTRL__IH_VMID_MASK 0x00000078L |
6145 | #define JPEG_IH_CTRL__IH_USER_DATA_MASK 0x0007FF80L |
6146 | #define JPEG_IH_CTRL__IH_RINGID_MASK 0x07F80000L |
6147 | //JRBBM_ARB_CTRL |
6148 | #define JRBBM_ARB_CTRL__DJRBC_DROP__SHIFT 0x0 |
6149 | #define JRBBM_ARB_CTRL__EJRBC_DROP__SHIFT 0x1 |
6150 | #define JRBBM_ARB_CTRL__SRBM_DROP__SHIFT 0x2 |
6151 | #define JRBBM_ARB_CTRL__DJRBC_DROP_MASK 0x00000001L |
6152 | #define JRBBM_ARB_CTRL__EJRBC_DROP_MASK 0x00000002L |
6153 | #define JRBBM_ARB_CTRL__SRBM_DROP_MASK 0x00000004L |
6154 | |
6155 | |
6156 | // addressBlock: uvd0_uvd_jpeg_common_sclk_dec |
6157 | //JPEG_CGC_GATE |
6158 | #define JPEG_CGC_GATE__JPEG_DEC__SHIFT 0x0 |
6159 | #define JPEG_CGC_GATE__JPEG2_DEC__SHIFT 0x1 |
6160 | #define JPEG_CGC_GATE__JPEG_ENC__SHIFT 0x2 |
6161 | #define JPEG_CGC_GATE__JMCIF__SHIFT 0x3 |
6162 | #define JPEG_CGC_GATE__JRBBM__SHIFT 0x4 |
6163 | #define JPEG_CGC_GATE__JPEG_DEC_MASK 0x00000001L |
6164 | #define JPEG_CGC_GATE__JPEG2_DEC_MASK 0x00000002L |
6165 | #define JPEG_CGC_GATE__JPEG_ENC_MASK 0x00000004L |
6166 | #define JPEG_CGC_GATE__JMCIF_MASK 0x00000008L |
6167 | #define JPEG_CGC_GATE__JRBBM_MASK 0x00000010L |
6168 | //JPEG_CGC_CTRL |
6169 | #define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 |
6170 | #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x1 |
6171 | #define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x5 |
6172 | #define JPEG_CGC_CTRL__JPEG_DEC_MODE__SHIFT 0x10 |
6173 | #define JPEG_CGC_CTRL__JPEG2_DEC_MODE__SHIFT 0x11 |
6174 | #define JPEG_CGC_CTRL__JPEG_ENC_MODE__SHIFT 0x12 |
6175 | #define JPEG_CGC_CTRL__JMCIF_MODE__SHIFT 0x13 |
6176 | #define JPEG_CGC_CTRL__JRBBM_MODE__SHIFT 0x14 |
6177 | #define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L |
6178 | #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL |
6179 | #define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK 0x00001FE0L |
6180 | #define JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK 0x00010000L |
6181 | #define JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK 0x00020000L |
6182 | #define JPEG_CGC_CTRL__JPEG_ENC_MODE_MASK 0x00040000L |
6183 | #define JPEG_CGC_CTRL__JMCIF_MODE_MASK 0x00080000L |
6184 | #define JPEG_CGC_CTRL__JRBBM_MODE_MASK 0x00100000L |
6185 | //JPEG_CGC_STATUS |
6186 | #define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE__SHIFT 0x0 |
6187 | #define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE__SHIFT 0x1 |
6188 | #define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE__SHIFT 0x2 |
6189 | #define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE__SHIFT 0x3 |
6190 | #define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE__SHIFT 0x4 |
6191 | #define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE__SHIFT 0x5 |
6192 | #define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE__SHIFT 0x6 |
6193 | #define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE__SHIFT 0x7 |
6194 | #define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE__SHIFT 0x8 |
6195 | #define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE_MASK 0x00000001L |
6196 | #define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE_MASK 0x00000002L |
6197 | #define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE_MASK 0x00000004L |
6198 | #define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE_MASK 0x00000008L |
6199 | #define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE_MASK 0x00000010L |
6200 | #define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE_MASK 0x00000020L |
6201 | #define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE_MASK 0x00000040L |
6202 | #define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE_MASK 0x00000080L |
6203 | #define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE_MASK 0x00000100L |
6204 | //JPEG_COMN_CGC_MEM_CTRL |
6205 | #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN__SHIFT 0x0 |
6206 | #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN__SHIFT 0x1 |
6207 | #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN__SHIFT 0x2 |
6208 | #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_SW_EN__SHIFT 0x3 |
6209 | #define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 |
6210 | #define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 |
6211 | #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN_MASK 0x00000001L |
6212 | #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN_MASK 0x00000002L |
6213 | #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN_MASK 0x00000004L |
6214 | #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_SW_EN_MASK 0x00000008L |
6215 | #define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000F0000L |
6216 | #define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00F00000L |
6217 | //JPEG_DEC_CGC_MEM_CTRL |
6218 | #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN__SHIFT 0x0 |
6219 | #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN__SHIFT 0x1 |
6220 | #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN__SHIFT 0x2 |
6221 | #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_SW_EN__SHIFT 0x3 |
6222 | #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN_MASK 0x00000001L |
6223 | #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN_MASK 0x00000002L |
6224 | #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN_MASK 0x00000004L |
6225 | #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_SW_EN_MASK 0x00000008L |
6226 | //JPEG2_DEC_CGC_MEM_CTRL |
6227 | #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN__SHIFT 0x0 |
6228 | #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN__SHIFT 0x1 |
6229 | #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN__SHIFT 0x2 |
6230 | #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_SW_EN__SHIFT 0x3 |
6231 | #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN_MASK 0x00000001L |
6232 | #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN_MASK 0x00000002L |
6233 | #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN_MASK 0x00000004L |
6234 | #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_SW_EN_MASK 0x00000008L |
6235 | //JPEG_ENC_CGC_MEM_CTRL |
6236 | #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN__SHIFT 0x0 |
6237 | #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN__SHIFT 0x1 |
6238 | #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN__SHIFT 0x2 |
6239 | #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_SW_EN__SHIFT 0x3 |
6240 | #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN_MASK 0x00000001L |
6241 | #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN_MASK 0x00000002L |
6242 | #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN_MASK 0x00000004L |
6243 | #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_SW_EN_MASK 0x00000008L |
6244 | //JPEG_SOFT_RESET2 |
6245 | #define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 |
6246 | #define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L |
6247 | //JPEG_PERF_BANK_CONF |
6248 | #define JPEG_PERF_BANK_CONF__RESET__SHIFT 0x0 |
6249 | #define JPEG_PERF_BANK_CONF__PEEK__SHIFT 0x8 |
6250 | #define JPEG_PERF_BANK_CONF__CONCATENATE__SHIFT 0x10 |
6251 | #define JPEG_PERF_BANK_CONF__RESET_MASK 0x0000000FL |
6252 | #define JPEG_PERF_BANK_CONF__PEEK_MASK 0x00000F00L |
6253 | #define JPEG_PERF_BANK_CONF__CONCATENATE_MASK 0x00030000L |
6254 | //JPEG_PERF_BANK_EVENT_SEL |
6255 | #define JPEG_PERF_BANK_EVENT_SEL__SEL0__SHIFT 0x0 |
6256 | #define JPEG_PERF_BANK_EVENT_SEL__SEL1__SHIFT 0x8 |
6257 | #define JPEG_PERF_BANK_EVENT_SEL__SEL2__SHIFT 0x10 |
6258 | #define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18 |
6259 | #define JPEG_PERF_BANK_EVENT_SEL__SEL0_MASK 0x000000FFL |
6260 | #define JPEG_PERF_BANK_EVENT_SEL__SEL1_MASK 0x0000FF00L |
6261 | #define JPEG_PERF_BANK_EVENT_SEL__SEL2_MASK 0x00FF0000L |
6262 | #define JPEG_PERF_BANK_EVENT_SEL__SEL3_MASK 0xFF000000L |
6263 | //JPEG_PERF_BANK_COUNT0 |
6264 | #define JPEG_PERF_BANK_COUNT0__COUNT__SHIFT 0x0 |
6265 | #define JPEG_PERF_BANK_COUNT0__COUNT_MASK 0xFFFFFFFFL |
6266 | //JPEG_PERF_BANK_COUNT1 |
6267 | #define JPEG_PERF_BANK_COUNT1__COUNT__SHIFT 0x0 |
6268 | #define JPEG_PERF_BANK_COUNT1__COUNT_MASK 0xFFFFFFFFL |
6269 | //JPEG_PERF_BANK_COUNT2 |
6270 | #define JPEG_PERF_BANK_COUNT2__COUNT__SHIFT 0x0 |
6271 | #define JPEG_PERF_BANK_COUNT2__COUNT_MASK 0xFFFFFFFFL |
6272 | //JPEG_PERF_BANK_COUNT3 |
6273 | #define JPEG_PERF_BANK_COUNT3__COUNT__SHIFT 0x0 |
6274 | #define JPEG_PERF_BANK_COUNT3__COUNT_MASK 0xFFFFFFFFL |
6275 | |
6276 | |
6277 | // addressBlock: uvd0_uvd_pg_dec |
6278 | //UVD_PGFSM_CONFIG |
6279 | #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0 |
6280 | #define UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 0x2 |
6281 | #define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4 |
6282 | #define UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 0x6 |
6283 | #define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8 |
6284 | #define UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 0xa |
6285 | #define UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 0xc |
6286 | #define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe |
6287 | #define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10 |
6288 | #define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12 |
6289 | #define UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 0x14 |
6290 | #define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT 0x16 |
6291 | #define UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 0x18 |
6292 | #define UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 0x1a |
6293 | #define UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT 0x1c |
6294 | #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L |
6295 | #define UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG_MASK 0x0000000CL |
6296 | #define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG_MASK 0x00000030L |
6297 | #define UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG_MASK 0x000000C0L |
6298 | #define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG_MASK 0x00000300L |
6299 | #define UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG_MASK 0x00000C00L |
6300 | #define UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG_MASK 0x00003000L |
6301 | #define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG_MASK 0x0000C000L |
6302 | #define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG_MASK 0x00030000L |
6303 | #define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG_MASK 0x000C0000L |
6304 | #define UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG_MASK 0x00300000L |
6305 | #define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG_MASK 0x00C00000L |
6306 | #define UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG_MASK 0x03000000L |
6307 | #define UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG_MASK 0x0C000000L |
6308 | //UVD_PGFSM_STATUS |
6309 | #define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0 |
6310 | #define UVD_PGFSM_STATUS__UVDS_PWR_STATUS__SHIFT 0x2 |
6311 | #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4 |
6312 | #define UVD_PGFSM_STATUS__UVDTC_PWR_STATUS__SHIFT 0x6 |
6313 | #define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8 |
6314 | #define UVD_PGFSM_STATUS__UVDTA_PWR_STATUS__SHIFT 0xa |
6315 | #define UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 0xc |
6316 | #define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe |
6317 | #define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10 |
6318 | #define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12 |
6319 | #define UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 0x14 |
6320 | #define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT 0x16 |
6321 | #define UVD_PGFSM_STATUS__UVDTB_PWR_STATUS__SHIFT 0x18 |
6322 | #define UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 0x1a |
6323 | #define UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT 0x1c |
6324 | #define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L |
6325 | #define UVD_PGFSM_STATUS__UVDS_PWR_STATUS_MASK 0x0000000CL |
6326 | #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L |
6327 | #define UVD_PGFSM_STATUS__UVDTC_PWR_STATUS_MASK 0x000000C0L |
6328 | #define UVD_PGFSM_STATUS__UVDB_PWR_STATUS_MASK 0x00000300L |
6329 | #define UVD_PGFSM_STATUS__UVDTA_PWR_STATUS_MASK 0x00000C00L |
6330 | #define UVD_PGFSM_STATUS__UVDLM_PWR_STATUS_MASK 0x00003000L |
6331 | #define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS_MASK 0x0000C000L |
6332 | #define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L |
6333 | #define UVD_PGFSM_STATUS__UVDE_PWR_STATUS_MASK 0x000C0000L |
6334 | #define UVD_PGFSM_STATUS__UVDAB_PWR_STATUS_MASK 0x00300000L |
6335 | #define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK 0x00C00000L |
6336 | #define UVD_PGFSM_STATUS__UVDTB_PWR_STATUS_MASK 0x03000000L |
6337 | #define UVD_PGFSM_STATUS__UVDNA_PWR_STATUS_MASK 0x0C000000L |
6338 | #define UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG_MASK 0x30000000L |
6339 | //UVD_POWER_STATUS |
6340 | #define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 |
6341 | #define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 |
6342 | #define UVD_POWER_STATUS__UVD_CG_MODE__SHIFT 0x4 |
6343 | #define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 |
6344 | #define UVD_POWER_STATUS__RBC_SNOOP_DIS__SHIFT 0x9 |
6345 | #define UVD_POWER_STATUS__SW_RB_SNOOP_DIS__SHIFT 0xb |
6346 | #define UVD_POWER_STATUS__STALL_DPG_POWER_UP__SHIFT 0x1f |
6347 | #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L |
6348 | #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L |
6349 | #define UVD_POWER_STATUS__UVD_CG_MODE_MASK 0x00000030L |
6350 | #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L |
6351 | #define UVD_POWER_STATUS__RBC_SNOOP_DIS_MASK 0x00000200L |
6352 | #define UVD_POWER_STATUS__SW_RB_SNOOP_DIS_MASK 0x00000800L |
6353 | #define UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK 0x80000000L |
6354 | //UVD_JPEG_POWER_STATUS |
6355 | #define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0 |
6356 | #define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4 |
6357 | #define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS__SHIFT 0x8 |
6358 | #define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS__SHIFT 0x9 |
6359 | #define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP__SHIFT 0x1f |
6360 | #define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK 0x00000001L |
6361 | #define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK 0x00000010L |
6362 | #define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS_MASK 0x00000100L |
6363 | #define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS_MASK 0x00000200L |
6364 | #define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP_MASK 0x80000000L |
6365 | //UVD_PG_IND_INDEX |
6366 | #define UVD_PG_IND_INDEX__INDEX__SHIFT 0x0 |
6367 | #define UVD_PG_IND_INDEX__INDEX_MASK 0x0000003FL |
6368 | //UVD_PG_IND_DATA |
6369 | #define UVD_PG_IND_DATA__DATA__SHIFT 0x0 |
6370 | #define UVD_PG_IND_DATA__DATA_MASK 0xFFFFFFFFL |
6371 | //CC_UVD_HARVESTING |
6372 | #define CC_UVD_HARVESTING__MMSCH_DISABLE__SHIFT 0x0 |
6373 | #define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 |
6374 | #define CC_UVD_HARVESTING__MMSCH_DISABLE_MASK 0x00000001L |
6375 | #define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L |
6376 | //UVD_DPG_LMA_CTL |
6377 | #define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 |
6378 | #define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1 |
6379 | #define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2 |
6380 | #define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4 |
6381 | #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10 |
6382 | #define UVD_DPG_LMA_CTL__READ_WRITE_MASK 0x00000001L |
6383 | #define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L |
6384 | #define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK 0x00000004L |
6385 | #define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L |
6386 | #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK 0xFFFF0000L |
6387 | //UVD_DPG_LMA_DATA |
6388 | #define UVD_DPG_LMA_DATA__LMA_DATA__SHIFT 0x0 |
6389 | #define UVD_DPG_LMA_DATA__LMA_DATA_MASK 0xFFFFFFFFL |
6390 | //UVD_DPG_LMA_MASK |
6391 | #define UVD_DPG_LMA_MASK__LMA_MASK__SHIFT 0x0 |
6392 | #define UVD_DPG_LMA_MASK__LMA_MASK_MASK 0xFFFFFFFFL |
6393 | //UVD_DPG_PAUSE |
6394 | #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT 0x0 |
6395 | #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1 |
6396 | #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2 |
6397 | #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT 0x3 |
6398 | #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK 0x00000001L |
6399 | #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK 0x00000002L |
6400 | #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L |
6401 | #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L |
6402 | //UVD_SCRATCH1 |
6403 | #define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT 0x0 |
6404 | #define UVD_SCRATCH1__SCRATCH1_DATA_MASK 0xFFFFFFFFL |
6405 | //UVD_SCRATCH2 |
6406 | #define UVD_SCRATCH2__SCRATCH2_DATA__SHIFT 0x0 |
6407 | #define UVD_SCRATCH2__SCRATCH2_DATA_MASK 0xFFFFFFFFL |
6408 | //UVD_SCRATCH3 |
6409 | #define UVD_SCRATCH3__SCRATCH3_DATA__SHIFT 0x0 |
6410 | #define UVD_SCRATCH3__SCRATCH3_DATA_MASK 0xFFFFFFFFL |
6411 | //UVD_SCRATCH4 |
6412 | #define UVD_SCRATCH4__SCRATCH4_DATA__SHIFT 0x0 |
6413 | #define UVD_SCRATCH4__SCRATCH4_DATA_MASK 0xFFFFFFFFL |
6414 | //UVD_SCRATCH5 |
6415 | #define UVD_SCRATCH5__SCRATCH5_DATA__SHIFT 0x0 |
6416 | #define UVD_SCRATCH5__SCRATCH5_DATA_MASK 0xFFFFFFFFL |
6417 | //UVD_SCRATCH6 |
6418 | #define UVD_SCRATCH6__SCRATCH6_DATA__SHIFT 0x0 |
6419 | #define UVD_SCRATCH6__SCRATCH6_DATA_MASK 0xFFFFFFFFL |
6420 | //UVD_SCRATCH7 |
6421 | #define UVD_SCRATCH7__SCRATCH7_DATA__SHIFT 0x0 |
6422 | #define UVD_SCRATCH7__SCRATCH7_DATA_MASK 0xFFFFFFFFL |
6423 | //UVD_SCRATCH8 |
6424 | #define UVD_SCRATCH8__SCRATCH8_DATA__SHIFT 0x0 |
6425 | #define UVD_SCRATCH8__SCRATCH8_DATA_MASK 0xFFFFFFFFL |
6426 | //UVD_SCRATCH9 |
6427 | #define UVD_SCRATCH9__SCRATCH9_DATA__SHIFT 0x0 |
6428 | #define UVD_SCRATCH9__SCRATCH9_DATA_MASK 0xFFFFFFFFL |
6429 | //UVD_SCRATCH10 |
6430 | #define UVD_SCRATCH10__SCRATCH10_DATA__SHIFT 0x0 |
6431 | #define UVD_SCRATCH10__SCRATCH10_DATA_MASK 0xFFFFFFFFL |
6432 | //UVD_SCRATCH11 |
6433 | #define UVD_SCRATCH11__SCRATCH11_DATA__SHIFT 0x0 |
6434 | #define UVD_SCRATCH11__SCRATCH11_DATA_MASK 0xFFFFFFFFL |
6435 | //UVD_SCRATCH12 |
6436 | #define UVD_SCRATCH12__SCRATCH12_DATA__SHIFT 0x0 |
6437 | #define UVD_SCRATCH12__SCRATCH12_DATA_MASK 0xFFFFFFFFL |
6438 | //UVD_SCRATCH13 |
6439 | #define UVD_SCRATCH13__SCRATCH13_DATA__SHIFT 0x0 |
6440 | #define UVD_SCRATCH13__SCRATCH13_DATA_MASK 0xFFFFFFFFL |
6441 | //UVD_SCRATCH14 |
6442 | #define UVD_SCRATCH14__SCRATCH14_DATA__SHIFT 0x0 |
6443 | #define UVD_SCRATCH14__SCRATCH14_DATA_MASK 0xFFFFFFFFL |
6444 | //UVD_FREE_COUNTER_REG |
6445 | #define UVD_FREE_COUNTER_REG__FREE_COUNTER__SHIFT 0x0 |
6446 | #define UVD_FREE_COUNTER_REG__FREE_COUNTER_MASK 0xFFFFFFFFL |
6447 | //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW |
6448 | #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
6449 | #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
6450 | //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH |
6451 | #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
6452 | #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
6453 | //UVD_DPG_VCPU_CACHE_OFFSET0 |
6454 | #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 |
6455 | #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL |
6456 | //UVD_DPG_LMI_VCPU_CACHE_VMID |
6457 | #define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 |
6458 | #define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL |
6459 | //UVD_FW_VERSION |
6460 | #define UVD_FW_VERSION__FW_VERSION__SHIFT 0x0 |
6461 | #define UVD_FW_VERSION__FW_VERSION_MASK 0xFFFFFFFFL |
6462 | //UVD_PF_STATUS |
6463 | #define UVD_PF_STATUS__JPEG_PF_OCCURED__SHIFT 0x0 |
6464 | #define UVD_PF_STATUS__NJ_PF_OCCURED__SHIFT 0x1 |
6465 | #define UVD_PF_STATUS__ENCODER0_PF_OCCURED__SHIFT 0x2 |
6466 | #define UVD_PF_STATUS__ENCODER1_PF_OCCURED__SHIFT 0x3 |
6467 | #define UVD_PF_STATUS__ENCODER2_PF_OCCURED__SHIFT 0x4 |
6468 | #define UVD_PF_STATUS__ENCODER3_PF_OCCURED__SHIFT 0x5 |
6469 | #define UVD_PF_STATUS__ENCODER4_PF_OCCURED__SHIFT 0x6 |
6470 | #define UVD_PF_STATUS__EJPEG_PF_OCCURED__SHIFT 0x7 |
6471 | #define UVD_PF_STATUS__JPEG_PF_CLEAR__SHIFT 0x8 |
6472 | #define UVD_PF_STATUS__NJ_PF_CLEAR__SHIFT 0x9 |
6473 | #define UVD_PF_STATUS__ENCODER0_PF_CLEAR__SHIFT 0xa |
6474 | #define UVD_PF_STATUS__ENCODER1_PF_CLEAR__SHIFT 0xb |
6475 | #define UVD_PF_STATUS__ENCODER2_PF_CLEAR__SHIFT 0xc |
6476 | #define UVD_PF_STATUS__ENCODER3_PF_CLEAR__SHIFT 0xd |
6477 | #define UVD_PF_STATUS__ENCODER4_PF_CLEAR__SHIFT 0xe |
6478 | #define UVD_PF_STATUS__EJPEG_PF_CLEAR__SHIFT 0xf |
6479 | #define UVD_PF_STATUS__NJ_ATM_PF_OCCURED__SHIFT 0x10 |
6480 | #define UVD_PF_STATUS__DJ_ATM_PF_OCCURED__SHIFT 0x11 |
6481 | #define UVD_PF_STATUS__EJ_ATM_PF_OCCURED__SHIFT 0x12 |
6482 | #define UVD_PF_STATUS__JPEG2_PF_OCCURED__SHIFT 0x13 |
6483 | #define UVD_PF_STATUS__DJ2_ATM_PF_OCCURED__SHIFT 0x14 |
6484 | #define UVD_PF_STATUS__JPEG2_PF_CLEAR__SHIFT 0x15 |
6485 | #define UVD_PF_STATUS__ENCODER5_PF_OCCURED__SHIFT 0x16 |
6486 | #define UVD_PF_STATUS__ENCODER5_PF_CLEAR__SHIFT 0x17 |
6487 | #define UVD_PF_STATUS__JPEG_PF_OCCURED_MASK 0x00000001L |
6488 | #define UVD_PF_STATUS__NJ_PF_OCCURED_MASK 0x00000002L |
6489 | #define UVD_PF_STATUS__ENCODER0_PF_OCCURED_MASK 0x00000004L |
6490 | #define UVD_PF_STATUS__ENCODER1_PF_OCCURED_MASK 0x00000008L |
6491 | #define UVD_PF_STATUS__ENCODER2_PF_OCCURED_MASK 0x00000010L |
6492 | #define UVD_PF_STATUS__ENCODER3_PF_OCCURED_MASK 0x00000020L |
6493 | #define UVD_PF_STATUS__ENCODER4_PF_OCCURED_MASK 0x00000040L |
6494 | #define UVD_PF_STATUS__EJPEG_PF_OCCURED_MASK 0x00000080L |
6495 | #define UVD_PF_STATUS__JPEG_PF_CLEAR_MASK 0x00000100L |
6496 | #define UVD_PF_STATUS__NJ_PF_CLEAR_MASK 0x00000200L |
6497 | #define UVD_PF_STATUS__ENCODER0_PF_CLEAR_MASK 0x00000400L |
6498 | #define UVD_PF_STATUS__ENCODER1_PF_CLEAR_MASK 0x00000800L |
6499 | #define UVD_PF_STATUS__ENCODER2_PF_CLEAR_MASK 0x00001000L |
6500 | #define UVD_PF_STATUS__ENCODER3_PF_CLEAR_MASK 0x00002000L |
6501 | #define UVD_PF_STATUS__ENCODER4_PF_CLEAR_MASK 0x00004000L |
6502 | #define UVD_PF_STATUS__EJPEG_PF_CLEAR_MASK 0x00008000L |
6503 | #define UVD_PF_STATUS__NJ_ATM_PF_OCCURED_MASK 0x00010000L |
6504 | #define UVD_PF_STATUS__DJ_ATM_PF_OCCURED_MASK 0x00020000L |
6505 | #define UVD_PF_STATUS__EJ_ATM_PF_OCCURED_MASK 0x00040000L |
6506 | #define UVD_PF_STATUS__JPEG2_PF_OCCURED_MASK 0x00080000L |
6507 | #define UVD_PF_STATUS__DJ2_ATM_PF_OCCURED_MASK 0x00100000L |
6508 | #define UVD_PF_STATUS__JPEG2_PF_CLEAR_MASK 0x00200000L |
6509 | #define UVD_PF_STATUS__ENCODER5_PF_OCCURED_MASK 0x00400000L |
6510 | #define UVD_PF_STATUS__ENCODER5_PF_CLEAR_MASK 0x00800000L |
6511 | //UVD_DPG_CLK_EN_VCPU_REPORT |
6512 | #define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN__SHIFT 0x0 |
6513 | #define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT__SHIFT 0x1 |
6514 | #define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN_MASK 0x00000001L |
6515 | #define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT_MASK 0x000000FEL |
6516 | //UVD_GFX8_ADDR_CONFIG |
6517 | #define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 |
6518 | #define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L |
6519 | //UVD_GFX10_ADDR_CONFIG |
6520 | #define UVD_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 |
6521 | #define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
6522 | #define UVD_GFX10_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
6523 | #define UVD_GFX10_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 |
6524 | #define UVD_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc |
6525 | #define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 |
6526 | #define UVD_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L |
6527 | #define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
6528 | #define UVD_GFX10_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
6529 | #define UVD_GFX10_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L |
6530 | #define UVD_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L |
6531 | #define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L |
6532 | //UVD_GPCNT2_CNTL |
6533 | #define UVD_GPCNT2_CNTL__CLR__SHIFT 0x0 |
6534 | #define UVD_GPCNT2_CNTL__START__SHIFT 0x1 |
6535 | #define UVD_GPCNT2_CNTL__COUNTUP__SHIFT 0x2 |
6536 | #define UVD_GPCNT2_CNTL__CLR_MASK 0x00000001L |
6537 | #define UVD_GPCNT2_CNTL__START_MASK 0x00000002L |
6538 | #define UVD_GPCNT2_CNTL__COUNTUP_MASK 0x00000004L |
6539 | //UVD_GPCNT2_TARGET_LOWER |
6540 | #define UVD_GPCNT2_TARGET_LOWER__TARGET__SHIFT 0x0 |
6541 | #define UVD_GPCNT2_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL |
6542 | //UVD_GPCNT2_STATUS_LOWER |
6543 | #define UVD_GPCNT2_STATUS_LOWER__COUNT__SHIFT 0x0 |
6544 | #define UVD_GPCNT2_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL |
6545 | //UVD_GPCNT2_TARGET_UPPER |
6546 | #define UVD_GPCNT2_TARGET_UPPER__TARGET__SHIFT 0x0 |
6547 | #define UVD_GPCNT2_TARGET_UPPER__TARGET_MASK 0x0000FFFFL |
6548 | //UVD_GPCNT2_STATUS_UPPER |
6549 | #define UVD_GPCNT2_STATUS_UPPER__COUNT__SHIFT 0x0 |
6550 | #define UVD_GPCNT2_STATUS_UPPER__COUNT_MASK 0x0000FFFFL |
6551 | //UVD_GPCNT3_CNTL |
6552 | #define UVD_GPCNT3_CNTL__CLR__SHIFT 0x0 |
6553 | #define UVD_GPCNT3_CNTL__START__SHIFT 0x1 |
6554 | #define UVD_GPCNT3_CNTL__COUNTUP__SHIFT 0x2 |
6555 | #define UVD_GPCNT3_CNTL__FREQ__SHIFT 0x3 |
6556 | #define UVD_GPCNT3_CNTL__DIV__SHIFT 0xa |
6557 | #define UVD_GPCNT3_CNTL__CLR_MASK 0x00000001L |
6558 | #define UVD_GPCNT3_CNTL__START_MASK 0x00000002L |
6559 | #define UVD_GPCNT3_CNTL__COUNTUP_MASK 0x00000004L |
6560 | #define UVD_GPCNT3_CNTL__FREQ_MASK 0x000003F8L |
6561 | #define UVD_GPCNT3_CNTL__DIV_MASK 0x0001FC00L |
6562 | //UVD_GPCNT3_TARGET_LOWER |
6563 | #define UVD_GPCNT3_TARGET_LOWER__TARGET__SHIFT 0x0 |
6564 | #define UVD_GPCNT3_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL |
6565 | //UVD_GPCNT3_STATUS_LOWER |
6566 | #define UVD_GPCNT3_STATUS_LOWER__COUNT__SHIFT 0x0 |
6567 | #define UVD_GPCNT3_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL |
6568 | //UVD_GPCNT3_TARGET_UPPER |
6569 | #define UVD_GPCNT3_TARGET_UPPER__TARGET__SHIFT 0x0 |
6570 | #define UVD_GPCNT3_TARGET_UPPER__TARGET_MASK 0x0000FFFFL |
6571 | //UVD_GPCNT3_STATUS_UPPER |
6572 | #define UVD_GPCNT3_STATUS_UPPER__COUNT__SHIFT 0x0 |
6573 | #define UVD_GPCNT3_STATUS_UPPER__COUNT_MASK 0x0000FFFFL |
6574 | //UVD_VCLK_DS_CNTL |
6575 | #define UVD_VCLK_DS_CNTL__VCLK_DS_EN__SHIFT 0x0 |
6576 | #define UVD_VCLK_DS_CNTL__VCLK_DS_STATUS__SHIFT 0x4 |
6577 | #define UVD_VCLK_DS_CNTL__VCLK_DS_HYSTERESIS_CNT__SHIFT 0x10 |
6578 | #define UVD_VCLK_DS_CNTL__VCLK_DS_EN_MASK 0x00000001L |
6579 | #define UVD_VCLK_DS_CNTL__VCLK_DS_STATUS_MASK 0x00000010L |
6580 | #define UVD_VCLK_DS_CNTL__VCLK_DS_HYSTERESIS_CNT_MASK 0xFFFF0000L |
6581 | //UVD_DCLK_DS_CNTL |
6582 | #define UVD_DCLK_DS_CNTL__DCLK_DS_EN__SHIFT 0x0 |
6583 | #define UVD_DCLK_DS_CNTL__DCLK_DS_STATUS__SHIFT 0x4 |
6584 | #define UVD_DCLK_DS_CNTL__DCLK_DS_HYSTERESIS_CNT__SHIFT 0x10 |
6585 | #define UVD_DCLK_DS_CNTL__DCLK_DS_EN_MASK 0x00000001L |
6586 | #define UVD_DCLK_DS_CNTL__DCLK_DS_STATUS_MASK 0x00000010L |
6587 | #define UVD_DCLK_DS_CNTL__DCLK_DS_HYSTERESIS_CNT_MASK 0xFFFF0000L |
6588 | //UVD_TSC_LOWER |
6589 | #define UVD_TSC_LOWER__COUNT__SHIFT 0x0 |
6590 | #define UVD_TSC_LOWER__COUNT_MASK 0xFFFFFFFFL |
6591 | //UVD_TSC_UPPER |
6592 | #define UVD_TSC_UPPER__COUNT__SHIFT 0x0 |
6593 | #define UVD_TSC_UPPER__COUNT_MASK 0x00FFFFFFL |
6594 | //VCN_FEATURES |
6595 | #define VCN_FEATURES__HAS_VIDEO_DEC__SHIFT 0x0 |
6596 | #define VCN_FEATURES__HAS_VIDEO_ENC__SHIFT 0x1 |
6597 | #define VCN_FEATURES__HAS_MJPEG_DEC__SHIFT 0x2 |
6598 | #define VCN_FEATURES__HAS_MJPEG_ENC__SHIFT 0x3 |
6599 | #define VCN_FEATURES__HAS_VIDEO_VIRT__SHIFT 0x4 |
6600 | #define VCN_FEATURES__HAS_H264_LEGACY_DEC__SHIFT 0x5 |
6601 | #define VCN_FEATURES__HAS_UDEC_DEC__SHIFT 0x6 |
6602 | #define VCN_FEATURES__HAS_MJPEG2_IDCT_DEC__SHIFT 0x7 |
6603 | #define VCN_FEATURES__HAS_SCLR_DEC__SHIFT 0x8 |
6604 | #define VCN_FEATURES__HAS_VP9_DEC__SHIFT 0x9 |
6605 | #define VCN_FEATURES__HAS_AV1_DEC__SHIFT 0xa |
6606 | #define VCN_FEATURES__HAS_EFC_ENC__SHIFT 0xb |
6607 | #define VCN_FEATURES__HAS_EFC_HDR2SDR_ENC__SHIFT 0xc |
6608 | #define VCN_FEATURES__HAS_DUAL_MJPEG_DEC__SHIFT 0xd |
6609 | #define VCN_FEATURES__HAS_AV1_ENC__SHIFT 0xe |
6610 | #define VCN_FEATURES__INSTANCE_ID__SHIFT 0x1c |
6611 | #define VCN_FEATURES__HAS_VIDEO_DEC_MASK 0x00000001L |
6612 | #define VCN_FEATURES__HAS_VIDEO_ENC_MASK 0x00000002L |
6613 | #define VCN_FEATURES__HAS_MJPEG_DEC_MASK 0x00000004L |
6614 | #define VCN_FEATURES__HAS_MJPEG_ENC_MASK 0x00000008L |
6615 | #define VCN_FEATURES__HAS_VIDEO_VIRT_MASK 0x00000010L |
6616 | #define VCN_FEATURES__HAS_H264_LEGACY_DEC_MASK 0x00000020L |
6617 | #define VCN_FEATURES__HAS_UDEC_DEC_MASK 0x00000040L |
6618 | #define VCN_FEATURES__HAS_MJPEG2_IDCT_DEC_MASK 0x00000080L |
6619 | #define VCN_FEATURES__HAS_SCLR_DEC_MASK 0x00000100L |
6620 | #define VCN_FEATURES__HAS_VP9_DEC_MASK 0x00000200L |
6621 | #define VCN_FEATURES__HAS_AV1_DEC_MASK 0x00000400L |
6622 | #define VCN_FEATURES__HAS_EFC_ENC_MASK 0x00000800L |
6623 | #define VCN_FEATURES__HAS_EFC_HDR2SDR_ENC_MASK 0x00001000L |
6624 | #define VCN_FEATURES__HAS_DUAL_MJPEG_DEC_MASK 0x00002000L |
6625 | #define VCN_FEATURES__HAS_AV1_ENC_MASK 0x00004000L |
6626 | #define VCN_FEATURES__INSTANCE_ID_MASK 0xF0000000L |
6627 | //UVD_GPUIOV_STATUS |
6628 | #define UVD_GPUIOV_STATUS__UVD_GPUIOV_STATUS_VF_ENABLE__SHIFT 0x0 |
6629 | #define UVD_GPUIOV_STATUS__UVD_GPUIOV_STATUS_VF_ENABLE_MASK 0x00000001L |
6630 | //UVD_RAS_VCPU_VCODEC_STATUS |
6631 | #define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_VF__SHIFT 0x0 |
6632 | #define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_PF__SHIFT 0x1f |
6633 | #define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_VF_MASK 0x7FFFFFFFL |
6634 | #define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_PF_MASK 0x80000000L |
6635 | //UVD_RAS_MMSCH_FATAL_ERROR |
6636 | #define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_VF__SHIFT 0x0 |
6637 | #define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_PF__SHIFT 0x1f |
6638 | #define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_VF_MASK 0x7FFFFFFFL |
6639 | #define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_PF_MASK 0x80000000L |
6640 | //UVD_RAS_JPEG0_STATUS |
6641 | #define UVD_RAS_JPEG0_STATUS__POISONED_VF__SHIFT 0x0 |
6642 | #define UVD_RAS_JPEG0_STATUS__POISONED_PF__SHIFT 0x1f |
6643 | #define UVD_RAS_JPEG0_STATUS__POISONED_VF_MASK 0x7FFFFFFFL |
6644 | #define UVD_RAS_JPEG0_STATUS__POISONED_PF_MASK 0x80000000L |
6645 | //UVD_RAS_JPEG1_STATUS |
6646 | #define UVD_RAS_JPEG1_STATUS__POISONED_VF__SHIFT 0x0 |
6647 | #define UVD_RAS_JPEG1_STATUS__POISONED_PF__SHIFT 0x1f |
6648 | #define UVD_RAS_JPEG1_STATUS__POISONED_VF_MASK 0x7FFFFFFFL |
6649 | #define UVD_RAS_JPEG1_STATUS__POISONED_PF_MASK 0x80000000L |
6650 | //UVD_RAS_CNTL_PMI_ARB |
6651 | #define UVD_RAS_CNTL_PMI_ARB__STAT_VCPU_VCODEC__SHIFT 0x0 |
6652 | #define UVD_RAS_CNTL_PMI_ARB__ACK_VCPU_VCODEC__SHIFT 0x1 |
6653 | #define UVD_RAS_CNTL_PMI_ARB__STAT_MMSCH__SHIFT 0x2 |
6654 | #define UVD_RAS_CNTL_PMI_ARB__ACK_MMSCH__SHIFT 0x3 |
6655 | #define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG0__SHIFT 0x4 |
6656 | #define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG0__SHIFT 0x5 |
6657 | #define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG1__SHIFT 0x6 |
6658 | #define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG1__SHIFT 0x7 |
6659 | #define UVD_RAS_CNTL_PMI_ARB__STAT_VCPU_VCODEC_MASK 0x00000001L |
6660 | #define UVD_RAS_CNTL_PMI_ARB__ACK_VCPU_VCODEC_MASK 0x00000002L |
6661 | #define UVD_RAS_CNTL_PMI_ARB__STAT_MMSCH_MASK 0x00000004L |
6662 | #define UVD_RAS_CNTL_PMI_ARB__ACK_MMSCH_MASK 0x00000008L |
6663 | #define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG0_MASK 0x00000010L |
6664 | #define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG0_MASK 0x00000020L |
6665 | #define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG1_MASK 0x00000040L |
6666 | #define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG1_MASK 0x00000080L |
6667 | //UVD_SCRATCH15 |
6668 | #define UVD_SCRATCH15__SCRATCH15_DATA__SHIFT 0x0 |
6669 | #define UVD_SCRATCH15__SCRATCH15_DATA_MASK 0xFFFFFFFFL |
6670 | //UVD_SCRATCH16 |
6671 | #define UVD_SCRATCH16__SCRATCH16_DATA__SHIFT 0x0 |
6672 | #define UVD_SCRATCH16__SCRATCH16_DATA_MASK 0xFFFFFFFFL |
6673 | //UVD_SCRATCH17 |
6674 | #define UVD_SCRATCH17__SCRATCH17_DATA__SHIFT 0x0 |
6675 | #define UVD_SCRATCH17__SCRATCH17_DATA_MASK 0xFFFFFFFFL |
6676 | //UVD_SCRATCH18 |
6677 | #define UVD_SCRATCH18__SCRATCH18_DATA__SHIFT 0x0 |
6678 | #define UVD_SCRATCH18__SCRATCH18_DATA_MASK 0xFFFFFFFFL |
6679 | //UVD_SCRATCH19 |
6680 | #define UVD_SCRATCH19__SCRATCH19_DATA__SHIFT 0x0 |
6681 | #define UVD_SCRATCH19__SCRATCH19_DATA_MASK 0xFFFFFFFFL |
6682 | //UVD_SCRATCH20 |
6683 | #define UVD_SCRATCH20__SCRATCH20_DATA__SHIFT 0x0 |
6684 | #define UVD_SCRATCH20__SCRATCH20_DATA_MASK 0xFFFFFFFFL |
6685 | //UVD_SCRATCH21 |
6686 | #define UVD_SCRATCH21__SCRATCH21_DATA__SHIFT 0x0 |
6687 | #define UVD_SCRATCH21__SCRATCH21_DATA_MASK 0xFFFFFFFFL |
6688 | //UVD_SCRATCH22 |
6689 | #define UVD_SCRATCH22__SCRATCH22_DATA__SHIFT 0x0 |
6690 | #define UVD_SCRATCH22__SCRATCH22_DATA_MASK 0xFFFFFFFFL |
6691 | //UVD_SCRATCH23 |
6692 | #define UVD_SCRATCH23__SCRATCH23_DATA__SHIFT 0x0 |
6693 | #define UVD_SCRATCH23__SCRATCH23_DATA_MASK 0xFFFFFFFFL |
6694 | //UVD_SCRATCH24 |
6695 | #define UVD_SCRATCH24__SCRATCH24_DATA__SHIFT 0x0 |
6696 | #define UVD_SCRATCH24__SCRATCH24_DATA_MASK 0xFFFFFFFFL |
6697 | //UVD_SCRATCH25 |
6698 | #define UVD_SCRATCH25__SCRATCH25_DATA__SHIFT 0x0 |
6699 | #define UVD_SCRATCH25__SCRATCH25_DATA_MASK 0xFFFFFFFFL |
6700 | //UVD_SCRATCH26 |
6701 | #define UVD_SCRATCH26__SCRATCH26_DATA__SHIFT 0x0 |
6702 | #define UVD_SCRATCH26__SCRATCH26_DATA_MASK 0xFFFFFFFFL |
6703 | //UVD_SCRATCH27 |
6704 | #define UVD_SCRATCH27__SCRATCH27_DATA__SHIFT 0x0 |
6705 | #define UVD_SCRATCH27__SCRATCH27_DATA_MASK 0xFFFFFFFFL |
6706 | //UVD_SCRATCH28 |
6707 | #define UVD_SCRATCH28__SCRATCH28_DATA__SHIFT 0x0 |
6708 | #define UVD_SCRATCH28__SCRATCH28_DATA_MASK 0xFFFFFFFFL |
6709 | //UVD_SCRATCH29 |
6710 | #define UVD_SCRATCH29__SCRATCH29_DATA__SHIFT 0x0 |
6711 | #define UVD_SCRATCH29__SCRATCH29_DATA_MASK 0xFFFFFFFFL |
6712 | //UVD_SCRATCH30 |
6713 | #define UVD_SCRATCH30__SCRATCH30_DATA__SHIFT 0x0 |
6714 | #define UVD_SCRATCH30__SCRATCH30_DATA_MASK 0xFFFFFFFFL |
6715 | //UVD_SCRATCH31 |
6716 | #define UVD_SCRATCH31__SCRATCH31_DATA__SHIFT 0x0 |
6717 | #define UVD_SCRATCH31__SCRATCH31_DATA_MASK 0xFFFFFFFFL |
6718 | //UVD_SCRATCH32 |
6719 | #define UVD_SCRATCH32__SCRATCH32_DATA__SHIFT 0x0 |
6720 | #define UVD_SCRATCH32__SCRATCH32_DATA_MASK 0xFFFFFFFFL |
6721 | //UVD_VERSION |
6722 | #define UVD_VERSION__VARIANT_TYPE__SHIFT 0x0 |
6723 | #define UVD_VERSION__MINOR_VERSION__SHIFT 0x8 |
6724 | #define UVD_VERSION__MAJOR_VERSION__SHIFT 0x10 |
6725 | #define UVD_VERSION__INSTANCE_ID__SHIFT 0x1c |
6726 | #define UVD_VERSION__VARIANT_TYPE_MASK 0x000000FFL |
6727 | #define UVD_VERSION__MINOR_VERSION_MASK 0x0000FF00L |
6728 | #define UVD_VERSION__MAJOR_VERSION_MASK 0x0FFF0000L |
6729 | #define UVD_VERSION__INSTANCE_ID_MASK 0xF0000000L |
6730 | //VCN_RB_DB_CTRL |
6731 | #define VCN_RB_DB_CTRL__OFFSET__SHIFT 0x2 |
6732 | #define VCN_RB_DB_CTRL__EN__SHIFT 0x1e |
6733 | #define VCN_RB_DB_CTRL__HIT__SHIFT 0x1f |
6734 | #define VCN_RB_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL |
6735 | #define VCN_RB_DB_CTRL__EN_MASK 0x40000000L |
6736 | #define VCN_RB_DB_CTRL__HIT_MASK 0x80000000L |
6737 | //VCN_JPEG_DB_CTRL |
6738 | #define VCN_JPEG_DB_CTRL__OFFSET__SHIFT 0x2 |
6739 | #define VCN_JPEG_DB_CTRL__EN__SHIFT 0x1e |
6740 | #define VCN_JPEG_DB_CTRL__HIT__SHIFT 0x1f |
6741 | #define VCN_JPEG_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL |
6742 | #define VCN_JPEG_DB_CTRL__EN_MASK 0x40000000L |
6743 | #define VCN_JPEG_DB_CTRL__HIT_MASK 0x80000000L |
6744 | //VCN_RB1_DB_CTRL |
6745 | #define VCN_RB1_DB_CTRL__OFFSET__SHIFT 0x2 |
6746 | #define VCN_RB1_DB_CTRL__EN__SHIFT 0x1e |
6747 | #define VCN_RB1_DB_CTRL__HIT__SHIFT 0x1f |
6748 | #define VCN_RB1_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL |
6749 | #define VCN_RB1_DB_CTRL__EN_MASK 0x40000000L |
6750 | #define VCN_RB1_DB_CTRL__HIT_MASK 0x80000000L |
6751 | //VCN_RB2_DB_CTRL |
6752 | #define VCN_RB2_DB_CTRL__OFFSET__SHIFT 0x2 |
6753 | #define VCN_RB2_DB_CTRL__EN__SHIFT 0x1e |
6754 | #define VCN_RB2_DB_CTRL__HIT__SHIFT 0x1f |
6755 | #define VCN_RB2_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL |
6756 | #define VCN_RB2_DB_CTRL__EN_MASK 0x40000000L |
6757 | #define VCN_RB2_DB_CTRL__HIT_MASK 0x80000000L |
6758 | //VCN_RB3_DB_CTRL |
6759 | #define VCN_RB3_DB_CTRL__OFFSET__SHIFT 0x2 |
6760 | #define VCN_RB3_DB_CTRL__EN__SHIFT 0x1e |
6761 | #define VCN_RB3_DB_CTRL__HIT__SHIFT 0x1f |
6762 | #define VCN_RB3_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL |
6763 | #define VCN_RB3_DB_CTRL__EN_MASK 0x40000000L |
6764 | #define VCN_RB3_DB_CTRL__HIT_MASK 0x80000000L |
6765 | //VCN_RB4_DB_CTRL |
6766 | #define VCN_RB4_DB_CTRL__OFFSET__SHIFT 0x2 |
6767 | #define VCN_RB4_DB_CTRL__EN__SHIFT 0x1e |
6768 | #define VCN_RB4_DB_CTRL__HIT__SHIFT 0x1f |
6769 | #define VCN_RB4_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL |
6770 | #define VCN_RB4_DB_CTRL__EN_MASK 0x40000000L |
6771 | #define VCN_RB4_DB_CTRL__HIT_MASK 0x80000000L |
6772 | //VCN_UMSCH_RB_DB_CTRL |
6773 | #define VCN_UMSCH_RB_DB_CTRL__OFFSET__SHIFT 0x2 |
6774 | #define VCN_UMSCH_RB_DB_CTRL__EN__SHIFT 0x1e |
6775 | #define VCN_UMSCH_RB_DB_CTRL__HIT__SHIFT 0x1f |
6776 | #define VCN_UMSCH_RB_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL |
6777 | #define VCN_UMSCH_RB_DB_CTRL__EN_MASK 0x40000000L |
6778 | #define VCN_UMSCH_RB_DB_CTRL__HIT_MASK 0x80000000L |
6779 | //VCN_AGDB_CTRL0 |
6780 | #define VCN_AGDB_CTRL0__OFFSET__SHIFT 0x2 |
6781 | #define VCN_AGDB_CTRL0__EN__SHIFT 0x1e |
6782 | #define VCN_AGDB_CTRL0__HIT__SHIFT 0x1f |
6783 | #define VCN_AGDB_CTRL0__OFFSET_MASK 0x0FFFFFFCL |
6784 | #define VCN_AGDB_CTRL0__EN_MASK 0x40000000L |
6785 | #define VCN_AGDB_CTRL0__HIT_MASK 0x80000000L |
6786 | //VCN_AGDB_CTRL1 |
6787 | #define VCN_AGDB_CTRL1__OFFSET__SHIFT 0x2 |
6788 | #define VCN_AGDB_CTRL1__EN__SHIFT 0x1e |
6789 | #define VCN_AGDB_CTRL1__HIT__SHIFT 0x1f |
6790 | #define VCN_AGDB_CTRL1__OFFSET_MASK 0x0FFFFFFCL |
6791 | #define VCN_AGDB_CTRL1__EN_MASK 0x40000000L |
6792 | #define VCN_AGDB_CTRL1__HIT_MASK 0x80000000L |
6793 | //VCN_AGDB_CTRL2 |
6794 | #define VCN_AGDB_CTRL2__OFFSET__SHIFT 0x2 |
6795 | #define VCN_AGDB_CTRL2__EN__SHIFT 0x1e |
6796 | #define VCN_AGDB_CTRL2__HIT__SHIFT 0x1f |
6797 | #define VCN_AGDB_CTRL2__OFFSET_MASK 0x0FFFFFFCL |
6798 | #define VCN_AGDB_CTRL2__EN_MASK 0x40000000L |
6799 | #define VCN_AGDB_CTRL2__HIT_MASK 0x80000000L |
6800 | //VCN_AGDB_CTRL3 |
6801 | #define VCN_AGDB_CTRL3__OFFSET__SHIFT 0x2 |
6802 | #define VCN_AGDB_CTRL3__EN__SHIFT 0x1e |
6803 | #define VCN_AGDB_CTRL3__HIT__SHIFT 0x1f |
6804 | #define VCN_AGDB_CTRL3__OFFSET_MASK 0x0FFFFFFCL |
6805 | #define VCN_AGDB_CTRL3__EN_MASK 0x40000000L |
6806 | #define VCN_AGDB_CTRL3__HIT_MASK 0x80000000L |
6807 | //VCN_AGDB_CTRL4 |
6808 | #define VCN_AGDB_CTRL4__OFFSET__SHIFT 0x2 |
6809 | #define VCN_AGDB_CTRL4__EN__SHIFT 0x1e |
6810 | #define VCN_AGDB_CTRL4__HIT__SHIFT 0x1f |
6811 | #define VCN_AGDB_CTRL4__OFFSET_MASK 0x0FFFFFFCL |
6812 | #define VCN_AGDB_CTRL4__EN_MASK 0x40000000L |
6813 | #define VCN_AGDB_CTRL4__HIT_MASK 0x80000000L |
6814 | //VCN_AGDB_CTRL5 |
6815 | #define VCN_AGDB_CTRL5__OFFSET__SHIFT 0x2 |
6816 | #define VCN_AGDB_CTRL5__EN__SHIFT 0x1e |
6817 | #define VCN_AGDB_CTRL5__HIT__SHIFT 0x1f |
6818 | #define VCN_AGDB_CTRL5__OFFSET_MASK 0x0FFFFFFCL |
6819 | #define VCN_AGDB_CTRL5__EN_MASK 0x40000000L |
6820 | #define VCN_AGDB_CTRL5__HIT_MASK 0x80000000L |
6821 | //VCN_AGDB_MASK0 |
6822 | #define VCN_AGDB_MASK0__MASK__SHIFT 0x2 |
6823 | #define VCN_AGDB_MASK0__MASK_MASK 0x0FFFFFFCL |
6824 | //VCN_AGDB_MASK1 |
6825 | #define VCN_AGDB_MASK1__MASK__SHIFT 0x2 |
6826 | #define VCN_AGDB_MASK1__MASK_MASK 0x0FFFFFFCL |
6827 | //VCN_AGDB_MASK2 |
6828 | #define VCN_AGDB_MASK2__MASK__SHIFT 0x2 |
6829 | #define VCN_AGDB_MASK2__MASK_MASK 0x0FFFFFFCL |
6830 | //VCN_AGDB_MASK3 |
6831 | #define VCN_AGDB_MASK3__MASK__SHIFT 0x2 |
6832 | #define VCN_AGDB_MASK3__MASK_MASK 0x0FFFFFFCL |
6833 | //VCN_AGDB_MASK4 |
6834 | #define VCN_AGDB_MASK4__MASK__SHIFT 0x2 |
6835 | #define VCN_AGDB_MASK4__MASK_MASK 0x0FFFFFFCL |
6836 | //VCN_AGDB_MASK5 |
6837 | #define VCN_AGDB_MASK5__MASK__SHIFT 0x2 |
6838 | #define VCN_AGDB_MASK5__MASK_MASK 0x0FFFFFFCL |
6839 | //VCN_RB_ENABLE |
6840 | #define VCN_RB_ENABLE__RB_EN__SHIFT 0x0 |
6841 | #define VCN_RB_ENABLE__JPEG_RB_EN__SHIFT 0x1 |
6842 | #define VCN_RB_ENABLE__RB1_EN__SHIFT 0x2 |
6843 | #define VCN_RB_ENABLE__RB2_EN__SHIFT 0x3 |
6844 | #define VCN_RB_ENABLE__RB3_EN__SHIFT 0x4 |
6845 | #define VCN_RB_ENABLE__RB4_EN__SHIFT 0x5 |
6846 | #define VCN_RB_ENABLE__UMSCH_RB_EN__SHIFT 0x6 |
6847 | #define VCN_RB_ENABLE__EJPEG_RB_EN__SHIFT 0x7 |
6848 | #define VCN_RB_ENABLE__AUDIO_RB_EN__SHIFT 0x8 |
6849 | #define VCN_RB_ENABLE__RB_EN_MASK 0x00000001L |
6850 | #define VCN_RB_ENABLE__JPEG_RB_EN_MASK 0x00000002L |
6851 | #define VCN_RB_ENABLE__RB1_EN_MASK 0x00000004L |
6852 | #define VCN_RB_ENABLE__RB2_EN_MASK 0x00000008L |
6853 | #define VCN_RB_ENABLE__RB3_EN_MASK 0x00000010L |
6854 | #define VCN_RB_ENABLE__RB4_EN_MASK 0x00000020L |
6855 | #define VCN_RB_ENABLE__UMSCH_RB_EN_MASK 0x00000040L |
6856 | #define VCN_RB_ENABLE__EJPEG_RB_EN_MASK 0x00000080L |
6857 | #define VCN_RB_ENABLE__AUDIO_RB_EN_MASK 0x00000100L |
6858 | //VCN_RB_WPTR_CTRL |
6859 | #define VCN_RB_WPTR_CTRL__RB_CS_EN__SHIFT 0x0 |
6860 | #define VCN_RB_WPTR_CTRL__JPEG_CS_EN__SHIFT 0x1 |
6861 | #define VCN_RB_WPTR_CTRL__RB1_CS_EN__SHIFT 0x2 |
6862 | #define VCN_RB_WPTR_CTRL__RB2_CS_EN__SHIFT 0x3 |
6863 | #define VCN_RB_WPTR_CTRL__RB3_CS_EN__SHIFT 0x4 |
6864 | #define VCN_RB_WPTR_CTRL__RB4_CS_EN__SHIFT 0x5 |
6865 | #define VCN_RB_WPTR_CTRL__UMSCH_RB_CS_EN__SHIFT 0x6 |
6866 | #define VCN_RB_WPTR_CTRL__EJPEG_RB_CS_EN__SHIFT 0x7 |
6867 | #define VCN_RB_WPTR_CTRL__AUDIO_RB_CS_EN__SHIFT 0x8 |
6868 | #define VCN_RB_WPTR_CTRL__RB_CS_EN_MASK 0x00000001L |
6869 | #define VCN_RB_WPTR_CTRL__JPEG_CS_EN_MASK 0x00000002L |
6870 | #define VCN_RB_WPTR_CTRL__RB1_CS_EN_MASK 0x00000004L |
6871 | #define VCN_RB_WPTR_CTRL__RB2_CS_EN_MASK 0x00000008L |
6872 | #define VCN_RB_WPTR_CTRL__RB3_CS_EN_MASK 0x00000010L |
6873 | #define VCN_RB_WPTR_CTRL__RB4_CS_EN_MASK 0x00000020L |
6874 | #define VCN_RB_WPTR_CTRL__UMSCH_RB_CS_EN_MASK 0x00000040L |
6875 | #define VCN_RB_WPTR_CTRL__EJPEG_RB_CS_EN_MASK 0x00000080L |
6876 | #define VCN_RB_WPTR_CTRL__AUDIO_RB_CS_EN_MASK 0x00000100L |
6877 | //UVD_RB_RPTR |
6878 | #define UVD_RB_RPTR__RB_RPTR__SHIFT 0x4 |
6879 | #define UVD_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L |
6880 | //UVD_RB_WPTR |
6881 | #define UVD_RB_WPTR__RB_WPTR__SHIFT 0x4 |
6882 | #define UVD_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L |
6883 | //UVD_RB_RPTR2 |
6884 | #define UVD_RB_RPTR2__RB_RPTR__SHIFT 0x4 |
6885 | #define UVD_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L |
6886 | //UVD_RB_WPTR2 |
6887 | #define UVD_RB_WPTR2__RB_WPTR__SHIFT 0x4 |
6888 | #define UVD_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L |
6889 | //UVD_RB_RPTR3 |
6890 | #define UVD_RB_RPTR3__RB_RPTR__SHIFT 0x4 |
6891 | #define UVD_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L |
6892 | //UVD_RB_WPTR3 |
6893 | #define UVD_RB_WPTR3__RB_WPTR__SHIFT 0x4 |
6894 | #define UVD_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L |
6895 | //UVD_RB_RPTR4 |
6896 | #define UVD_RB_RPTR4__RB_RPTR__SHIFT 0x4 |
6897 | #define UVD_RB_RPTR4__RB_RPTR_MASK 0x007FFFF0L |
6898 | //UVD_RB_WPTR4 |
6899 | #define UVD_RB_WPTR4__RB_WPTR__SHIFT 0x4 |
6900 | #define UVD_RB_WPTR4__RB_WPTR_MASK 0x007FFFF0L |
6901 | //UVD_OUT_RB_RPTR |
6902 | #define UVD_OUT_RB_RPTR__RB_RPTR__SHIFT 0x4 |
6903 | #define UVD_OUT_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L |
6904 | //UVD_OUT_RB_WPTR |
6905 | #define UVD_OUT_RB_WPTR__RB_WPTR__SHIFT 0x4 |
6906 | #define UVD_OUT_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L |
6907 | //UVD_AUDIO_RB_RPTR |
6908 | #define UVD_AUDIO_RB_RPTR__RB_RPTR__SHIFT 0x4 |
6909 | #define UVD_AUDIO_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L |
6910 | //UVD_AUDIO_RB_WPTR |
6911 | #define UVD_AUDIO_RB_WPTR__RB_WPTR__SHIFT 0x4 |
6912 | #define UVD_AUDIO_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L |
6913 | //UVD_RBC_RB_RPTR |
6914 | #define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 |
6915 | #define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L |
6916 | //UVD_RBC_RB_WPTR |
6917 | #define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 |
6918 | #define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L |
6919 | //UVD_DPG_LMA_CTL2 |
6920 | #define UVD_DPG_LMA_CTL2__DIRECT_ACCESS_SRAM_SEL__SHIFT 0x0 |
6921 | #define UVD_DPG_LMA_CTL2__FIFO_DIRECT_ACCESS_EN__SHIFT 0x1 |
6922 | #define UVD_DPG_LMA_CTL2__VID_WRITE_PTR__SHIFT 0x2 |
6923 | #define UVD_DPG_LMA_CTL2__JPEG_WRITE_PTR__SHIFT 0x9 |
6924 | #define UVD_DPG_LMA_CTL2__DIRECT_ACCESS_SRAM_SEL_MASK 0x00000001L |
6925 | #define UVD_DPG_LMA_CTL2__FIFO_DIRECT_ACCESS_EN_MASK 0x00000002L |
6926 | #define UVD_DPG_LMA_CTL2__VID_WRITE_PTR_MASK 0x000001FCL |
6927 | #define UVD_DPG_LMA_CTL2__JPEG_WRITE_PTR_MASK 0x0000FE00L |
6928 | |
6929 | |
6930 | // addressBlock: uvd0_mmsch_dec |
6931 | //MMSCH_UCODE_ADDR |
6932 | #define MMSCH_UCODE_ADDR__UCODE_ADDR__SHIFT 0x2 |
6933 | #define MMSCH_UCODE_ADDR__UCODE_LOCK__SHIFT 0x1f |
6934 | #define MMSCH_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFCL |
6935 | #define MMSCH_UCODE_ADDR__UCODE_LOCK_MASK 0x80000000L |
6936 | //MMSCH_UCODE_DATA |
6937 | #define MMSCH_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
6938 | #define MMSCH_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
6939 | //MMSCH_SRAM_ADDR |
6940 | #define MMSCH_SRAM_ADDR__SRAM_ADDR__SHIFT 0x2 |
6941 | #define MMSCH_SRAM_ADDR__SRAM_LOCK__SHIFT 0x1f |
6942 | #define MMSCH_SRAM_ADDR__SRAM_ADDR_MASK 0x00001FFCL |
6943 | #define MMSCH_SRAM_ADDR__SRAM_LOCK_MASK 0x80000000L |
6944 | //MMSCH_SRAM_DATA |
6945 | #define MMSCH_SRAM_DATA__SRAM_DATA__SHIFT 0x0 |
6946 | #define MMSCH_SRAM_DATA__SRAM_DATA_MASK 0xFFFFFFFFL |
6947 | //MMSCH_VF_SRAM_OFFSET |
6948 | #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET__SHIFT 0x2 |
6949 | #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF__SHIFT 0x10 |
6950 | #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET_MASK 0x00001FFCL |
6951 | #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF_MASK 0x00FF0000L |
6952 | //MMSCH_DB_SRAM_OFFSET |
6953 | #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET__SHIFT 0x2 |
6954 | #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG__SHIFT 0x10 |
6955 | #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG__SHIFT 0x18 |
6956 | #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET_MASK 0x00001FFCL |
6957 | #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG_MASK 0x00FF0000L |
6958 | #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG_MASK 0xFF000000L |
6959 | //MMSCH_CTX_SRAM_OFFSET |
6960 | #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET__SHIFT 0x2 |
6961 | #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE__SHIFT 0x10 |
6962 | #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET_MASK 0x00001FFCL |
6963 | #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE_MASK 0xFFFF0000L |
6964 | //MMSCH_INTR |
6965 | #define MMSCH_INTR__INTR__SHIFT 0x0 |
6966 | #define MMSCH_INTR__INTR_MASK 0x00001FFFL |
6967 | //MMSCH_INTR_ACK |
6968 | #define MMSCH_INTR_ACK__INTR__SHIFT 0x0 |
6969 | #define MMSCH_INTR_ACK__INTR_MASK 0x00001FFFL |
6970 | //MMSCH_INTR_STATUS |
6971 | #define MMSCH_INTR_STATUS__INTR__SHIFT 0x0 |
6972 | #define MMSCH_INTR_STATUS__INTR_MASK 0x00001FFFL |
6973 | //MMSCH_VF_VMID |
6974 | #define MMSCH_VF_VMID__VF_CTX_VMID__SHIFT 0x0 |
6975 | #define MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT 0x5 |
6976 | #define MMSCH_VF_VMID__VF_CTX_VMID_MASK 0x0000001FL |
6977 | #define MMSCH_VF_VMID__VF_GPCOM_VMID_MASK 0x000003E0L |
6978 | //MMSCH_VF_CTX_ADDR_LO |
6979 | #define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO__SHIFT 0x6 |
6980 | #define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO_MASK 0xFFFFFFC0L |
6981 | //MMSCH_VF_CTX_ADDR_HI |
6982 | #define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI__SHIFT 0x0 |
6983 | #define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI_MASK 0xFFFFFFFFL |
6984 | //MMSCH_VF_CTX_SIZE |
6985 | #define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE__SHIFT 0x0 |
6986 | #define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE_MASK 0xFFFFFFFFL |
6987 | //MMSCH_VF_GPCOM_ADDR_LO |
6988 | #define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO__SHIFT 0x6 |
6989 | #define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO_MASK 0xFFFFFFC0L |
6990 | //MMSCH_VF_GPCOM_ADDR_HI |
6991 | #define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI__SHIFT 0x0 |
6992 | #define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI_MASK 0xFFFFFFFFL |
6993 | //MMSCH_VF_GPCOM_SIZE |
6994 | #define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE__SHIFT 0x0 |
6995 | #define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE_MASK 0xFFFFFFFFL |
6996 | //MMSCH_VF_MAILBOX_HOST |
6997 | #define MMSCH_VF_MAILBOX_HOST__DATA__SHIFT 0x0 |
6998 | #define MMSCH_VF_MAILBOX_HOST__DATA_MASK 0xFFFFFFFFL |
6999 | //MMSCH_VF_MAILBOX_RESP |
7000 | #define MMSCH_VF_MAILBOX_RESP__RESP__SHIFT 0x0 |
7001 | #define MMSCH_VF_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL |
7002 | //MMSCH_VF_MAILBOX_0 |
7003 | #define MMSCH_VF_MAILBOX_0__DATA__SHIFT 0x0 |
7004 | #define MMSCH_VF_MAILBOX_0__DATA_MASK 0xFFFFFFFFL |
7005 | //MMSCH_VF_MAILBOX_0_RESP |
7006 | #define MMSCH_VF_MAILBOX_0_RESP__RESP__SHIFT 0x0 |
7007 | #define MMSCH_VF_MAILBOX_0_RESP__RESP_MASK 0xFFFFFFFFL |
7008 | //MMSCH_VF_MAILBOX_1 |
7009 | #define MMSCH_VF_MAILBOX_1__DATA__SHIFT 0x0 |
7010 | #define MMSCH_VF_MAILBOX_1__DATA_MASK 0xFFFFFFFFL |
7011 | //MMSCH_VF_MAILBOX_1_RESP |
7012 | #define MMSCH_VF_MAILBOX_1_RESP__RESP__SHIFT 0x0 |
7013 | #define MMSCH_VF_MAILBOX_1_RESP__RESP_MASK 0xFFFFFFFFL |
7014 | //MMSCH_CNTL |
7015 | #define MMSCH_CNTL__CLK_EN__SHIFT 0x0 |
7016 | #define MMSCH_CNTL__ED_ENABLE__SHIFT 0x1 |
7017 | #define MMSCH_CNTL__MMSCH_IRQ_ERR__SHIFT 0x5 |
7018 | #define MMSCH_CNTL__MMSCH_NACK_INTR_EN__SHIFT 0x9 |
7019 | #define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN__SHIFT 0xa |
7020 | #define MMSCH_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 |
7021 | #define MMSCH_CNTL__TIMEOUT_DIS__SHIFT 0x1c |
7022 | #define MMSCH_CNTL__MMSCH_IDLE__SHIFT 0x1d |
7023 | #define MMSCH_CNTL__CLK_EN_MASK 0x00000001L |
7024 | #define MMSCH_CNTL__ED_ENABLE_MASK 0x00000002L |
7025 | #define MMSCH_CNTL__MMSCH_IRQ_ERR_MASK 0x000001E0L |
7026 | #define MMSCH_CNTL__MMSCH_NACK_INTR_EN_MASK 0x00000200L |
7027 | #define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN_MASK 0x00000400L |
7028 | #define MMSCH_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L |
7029 | #define MMSCH_CNTL__TIMEOUT_DIS_MASK 0x10000000L |
7030 | #define MMSCH_CNTL__MMSCH_IDLE_MASK 0x20000000L |
7031 | //MMSCH_NONCACHE_OFFSET0 |
7032 | #define MMSCH_NONCACHE_OFFSET0__OFFSET__SHIFT 0x0 |
7033 | #define MMSCH_NONCACHE_OFFSET0__OFFSET_MASK 0x0FFFFFFFL |
7034 | //MMSCH_NONCACHE_SIZE0 |
7035 | #define MMSCH_NONCACHE_SIZE0__SIZE__SHIFT 0x0 |
7036 | #define MMSCH_NONCACHE_SIZE0__SIZE_MASK 0x00FFFFFFL |
7037 | //MMSCH_NONCACHE_OFFSET1 |
7038 | #define MMSCH_NONCACHE_OFFSET1__OFFSET__SHIFT 0x0 |
7039 | #define MMSCH_NONCACHE_OFFSET1__OFFSET_MASK 0x0FFFFFFFL |
7040 | //MMSCH_NONCACHE_SIZE1 |
7041 | #define MMSCH_NONCACHE_SIZE1__SIZE__SHIFT 0x0 |
7042 | #define MMSCH_NONCACHE_SIZE1__SIZE_MASK 0x00FFFFFFL |
7043 | //MMSCH_PROC_STATE1 |
7044 | #define MMSCH_PROC_STATE1__PC__SHIFT 0x0 |
7045 | #define MMSCH_PROC_STATE1__PC_MASK 0xFFFFFFFFL |
7046 | //MMSCH_LAST_MC_ADDR |
7047 | #define MMSCH_LAST_MC_ADDR__MC_ADDR__SHIFT 0x0 |
7048 | #define MMSCH_LAST_MC_ADDR__RW__SHIFT 0x1f |
7049 | #define MMSCH_LAST_MC_ADDR__MC_ADDR_MASK 0x0FFFFFFFL |
7050 | #define MMSCH_LAST_MC_ADDR__RW_MASK 0x80000000L |
7051 | //MMSCH_LAST_MEM_ACCESS_HI |
7052 | #define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD__SHIFT 0x0 |
7053 | #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR__SHIFT 0x8 |
7054 | #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR__SHIFT 0xc |
7055 | #define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD_MASK 0x00000007L |
7056 | #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR_MASK 0x00000700L |
7057 | #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR_MASK 0x00007000L |
7058 | //MMSCH_LAST_MEM_ACCESS_LO |
7059 | #define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR__SHIFT 0x0 |
7060 | #define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR_MASK 0xFFFFFFFFL |
7061 | //MMSCH_SCRATCH_0 |
7062 | #define MMSCH_SCRATCH_0__SCRATCH_0__SHIFT 0x0 |
7063 | #define MMSCH_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL |
7064 | //MMSCH_SCRATCH_1 |
7065 | #define MMSCH_SCRATCH_1__SCRATCH_1__SHIFT 0x0 |
7066 | #define MMSCH_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL |
7067 | //MMSCH_GPUIOV_SCH_BLOCK_0 |
7068 | #define MMSCH_GPUIOV_SCH_BLOCK_0__ID__SHIFT 0x0 |
7069 | #define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION__SHIFT 0x4 |
7070 | #define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE__SHIFT 0x8 |
7071 | #define MMSCH_GPUIOV_SCH_BLOCK_0__ID_MASK 0x0000000FL |
7072 | #define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION_MASK 0x000000F0L |
7073 | #define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE_MASK 0x0000FF00L |
7074 | //MMSCH_GPUIOV_CMD_CONTROL_0 |
7075 | #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE__SHIFT 0x0 |
7076 | #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE__SHIFT 0x4 |
7077 | #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN__SHIFT 0x5 |
7078 | #define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN__SHIFT 0x6 |
7079 | #define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID__SHIFT 0x8 |
7080 | #define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID__SHIFT 0x10 |
7081 | #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE_MASK 0x0000000FL |
7082 | #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_MASK 0x00000010L |
7083 | #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN_MASK 0x00000020L |
7084 | #define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN_MASK 0x00000040L |
7085 | #define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID_MASK 0x0000FF00L |
7086 | #define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID_MASK 0x00FF0000L |
7087 | //MMSCH_GPUIOV_CMD_STATUS_0 |
7088 | #define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS__SHIFT 0x0 |
7089 | #define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS_MASK 0x0000000FL |
7090 | //MMSCH_GPUIOV_VM_BUSY_STATUS_0 |
7091 | #define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0 |
7092 | #define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL |
7093 | //MMSCH_GPUIOV_ACTIVE_FCNS_0 |
7094 | #define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS__SHIFT 0x0 |
7095 | #define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS_MASK 0xFFFFFFFFL |
7096 | //MMSCH_GPUIOV_DW6_0 |
7097 | #define MMSCH_GPUIOV_DW6_0__DATA__SHIFT 0x0 |
7098 | #define MMSCH_GPUIOV_DW6_0__DATA_MASK 0xFFFFFFFFL |
7099 | //MMSCH_GPUIOV_DW7_0 |
7100 | #define MMSCH_GPUIOV_DW7_0__DATA__SHIFT 0x0 |
7101 | #define MMSCH_GPUIOV_DW7_0__DATA_MASK 0xFFFFFFFFL |
7102 | //MMSCH_GPUIOV_DW8_0 |
7103 | #define MMSCH_GPUIOV_DW8_0__DATA__SHIFT 0x0 |
7104 | #define MMSCH_GPUIOV_DW8_0__DATA_MASK 0xFFFFFFFFL |
7105 | //MMSCH_GPUIOV_SCH_BLOCK_1 |
7106 | #define MMSCH_GPUIOV_SCH_BLOCK_1__ID__SHIFT 0x0 |
7107 | #define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION__SHIFT 0x4 |
7108 | #define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE__SHIFT 0x8 |
7109 | #define MMSCH_GPUIOV_SCH_BLOCK_1__ID_MASK 0x0000000FL |
7110 | #define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION_MASK 0x000000F0L |
7111 | #define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE_MASK 0x0000FF00L |
7112 | //MMSCH_GPUIOV_CMD_CONTROL_1 |
7113 | #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE__SHIFT 0x0 |
7114 | #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE__SHIFT 0x4 |
7115 | #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 |
7116 | #define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN__SHIFT 0x6 |
7117 | #define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID__SHIFT 0x8 |
7118 | #define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID__SHIFT 0x10 |
7119 | #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE_MASK 0x0000000FL |
7120 | #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_MASK 0x00000010L |
7121 | #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L |
7122 | #define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN_MASK 0x00000040L |
7123 | #define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID_MASK 0x0000FF00L |
7124 | #define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID_MASK 0x00FF0000L |
7125 | //MMSCH_GPUIOV_CMD_STATUS_1 |
7126 | #define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS__SHIFT 0x0 |
7127 | #define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS_MASK 0x0000000FL |
7128 | //MMSCH_GPUIOV_VM_BUSY_STATUS_1 |
7129 | #define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0 |
7130 | #define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL |
7131 | //MMSCH_GPUIOV_ACTIVE_FCNS_1 |
7132 | #define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS__SHIFT 0x0 |
7133 | #define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS_MASK 0xFFFFFFFFL |
7134 | //MMSCH_GPUIOV_DW6_1 |
7135 | #define MMSCH_GPUIOV_DW6_1__DATA__SHIFT 0x0 |
7136 | #define MMSCH_GPUIOV_DW6_1__DATA_MASK 0xFFFFFFFFL |
7137 | //MMSCH_GPUIOV_DW7_1 |
7138 | #define MMSCH_GPUIOV_DW7_1__DATA__SHIFT 0x0 |
7139 | #define MMSCH_GPUIOV_DW7_1__DATA_MASK 0xFFFFFFFFL |
7140 | //MMSCH_GPUIOV_DW8_1 |
7141 | #define MMSCH_GPUIOV_DW8_1__DATA__SHIFT 0x0 |
7142 | #define MMSCH_GPUIOV_DW8_1__DATA_MASK 0xFFFFFFFFL |
7143 | //MMSCH_GPUIOV_CNTXT |
7144 | #define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE__SHIFT 0x0 |
7145 | #define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION__SHIFT 0x7 |
7146 | #define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET__SHIFT 0xa |
7147 | #define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE_MASK 0x0000007FL |
7148 | #define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION_MASK 0x00000080L |
7149 | #define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET_MASK 0xFFFFFC00L |
7150 | //MMSCH_SCRATCH_2 |
7151 | #define MMSCH_SCRATCH_2__SCRATCH_2__SHIFT 0x0 |
7152 | #define MMSCH_SCRATCH_2__SCRATCH_2_MASK 0xFFFFFFFFL |
7153 | //MMSCH_SCRATCH_3 |
7154 | #define MMSCH_SCRATCH_3__SCRATCH_3__SHIFT 0x0 |
7155 | #define MMSCH_SCRATCH_3__SCRATCH_3_MASK 0xFFFFFFFFL |
7156 | //MMSCH_SCRATCH_4 |
7157 | #define MMSCH_SCRATCH_4__SCRATCH_4__SHIFT 0x0 |
7158 | #define MMSCH_SCRATCH_4__SCRATCH_4_MASK 0xFFFFFFFFL |
7159 | //MMSCH_SCRATCH_5 |
7160 | #define MMSCH_SCRATCH_5__SCRATCH_5__SHIFT 0x0 |
7161 | #define MMSCH_SCRATCH_5__SCRATCH_5_MASK 0xFFFFFFFFL |
7162 | //MMSCH_SCRATCH_6 |
7163 | #define MMSCH_SCRATCH_6__SCRATCH_6__SHIFT 0x0 |
7164 | #define MMSCH_SCRATCH_6__SCRATCH_6_MASK 0xFFFFFFFFL |
7165 | //MMSCH_SCRATCH_7 |
7166 | #define MMSCH_SCRATCH_7__SCRATCH_7__SHIFT 0x0 |
7167 | #define MMSCH_SCRATCH_7__SCRATCH_7_MASK 0xFFFFFFFFL |
7168 | //MMSCH_VFID_FIFO_HEAD_0 |
7169 | #define MMSCH_VFID_FIFO_HEAD_0__HEAD__SHIFT 0x0 |
7170 | #define MMSCH_VFID_FIFO_HEAD_0__HEAD_MASK 0x0000003FL |
7171 | //MMSCH_VFID_FIFO_TAIL_0 |
7172 | #define MMSCH_VFID_FIFO_TAIL_0__TAIL__SHIFT 0x0 |
7173 | #define MMSCH_VFID_FIFO_TAIL_0__TAIL_MASK 0x0000003FL |
7174 | //MMSCH_VFID_FIFO_HEAD_1 |
7175 | #define MMSCH_VFID_FIFO_HEAD_1__HEAD__SHIFT 0x0 |
7176 | #define MMSCH_VFID_FIFO_HEAD_1__HEAD_MASK 0x0000003FL |
7177 | //MMSCH_VFID_FIFO_TAIL_1 |
7178 | #define MMSCH_VFID_FIFO_TAIL_1__TAIL__SHIFT 0x0 |
7179 | #define MMSCH_VFID_FIFO_TAIL_1__TAIL_MASK 0x0000003FL |
7180 | //MMSCH_NACK_STATUS |
7181 | #define MMSCH_NACK_STATUS__WR_NACK_STATUS__SHIFT 0x0 |
7182 | #define MMSCH_NACK_STATUS__RD_NACK_STATUS__SHIFT 0x2 |
7183 | #define MMSCH_NACK_STATUS__WR_NACK_STATUS_MASK 0x00000003L |
7184 | #define MMSCH_NACK_STATUS__RD_NACK_STATUS_MASK 0x0000000CL |
7185 | //MMSCH_VF_MAILBOX0_DATA |
7186 | #define MMSCH_VF_MAILBOX0_DATA__DATA__SHIFT 0x0 |
7187 | #define MMSCH_VF_MAILBOX0_DATA__DATA_MASK 0xFFFFFFFFL |
7188 | //MMSCH_VF_MAILBOX1_DATA |
7189 | #define MMSCH_VF_MAILBOX1_DATA__DATA__SHIFT 0x0 |
7190 | #define MMSCH_VF_MAILBOX1_DATA__DATA_MASK 0xFFFFFFFFL |
7191 | //MMSCH_GPUIOV_SCH_BLOCK_IP_0 |
7192 | #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID__SHIFT 0x0 |
7193 | #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION__SHIFT 0x4 |
7194 | #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE__SHIFT 0x8 |
7195 | #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID_MASK 0x0000000FL |
7196 | #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION_MASK 0x000000F0L |
7197 | #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE_MASK 0x0000FF00L |
7198 | //MMSCH_GPUIOV_CMD_STATUS_IP_0 |
7199 | #define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS__SHIFT 0x0 |
7200 | #define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS_MASK 0x0000000FL |
7201 | //MMSCH_GPUIOV_SCH_BLOCK_IP_1 |
7202 | #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID__SHIFT 0x0 |
7203 | #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION__SHIFT 0x4 |
7204 | #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE__SHIFT 0x8 |
7205 | #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID_MASK 0x0000000FL |
7206 | #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION_MASK 0x000000F0L |
7207 | #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE_MASK 0x0000FF00L |
7208 | //MMSCH_GPUIOV_CMD_STATUS_IP_1 |
7209 | #define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS__SHIFT 0x0 |
7210 | #define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS_MASK 0x0000000FL |
7211 | //MMSCH_GPUIOV_CNTXT_IP |
7212 | #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE__SHIFT 0x0 |
7213 | #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION__SHIFT 0x7 |
7214 | #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE_MASK 0x0000007FL |
7215 | #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION_MASK 0x00000080L |
7216 | //MMSCH_GPUIOV_SCH_BLOCK_2 |
7217 | #define MMSCH_GPUIOV_SCH_BLOCK_2__ID__SHIFT 0x0 |
7218 | #define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION__SHIFT 0x4 |
7219 | #define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE__SHIFT 0x8 |
7220 | #define MMSCH_GPUIOV_SCH_BLOCK_2__ID_MASK 0x0000000FL |
7221 | #define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION_MASK 0x000000F0L |
7222 | #define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE_MASK 0x0000FF00L |
7223 | //MMSCH_GPUIOV_CMD_CONTROL_2 |
7224 | #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE__SHIFT 0x0 |
7225 | #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE__SHIFT 0x4 |
7226 | #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN__SHIFT 0x5 |
7227 | #define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN__SHIFT 0x6 |
7228 | #define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID__SHIFT 0x8 |
7229 | #define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID__SHIFT 0x10 |
7230 | #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE_MASK 0x0000000FL |
7231 | #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_MASK 0x00000010L |
7232 | #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN_MASK 0x00000020L |
7233 | #define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN_MASK 0x00000040L |
7234 | #define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID_MASK 0x0000FF00L |
7235 | #define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID_MASK 0x00FF0000L |
7236 | //MMSCH_GPUIOV_CMD_STATUS_2 |
7237 | #define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS__SHIFT 0x0 |
7238 | #define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS_MASK 0x0000000FL |
7239 | //MMSCH_GPUIOV_VM_BUSY_STATUS_2 |
7240 | #define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0 |
7241 | #define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL |
7242 | //MMSCH_GPUIOV_ACTIVE_FCNS_2 |
7243 | #define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS__SHIFT 0x0 |
7244 | #define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS_MASK 0xFFFFFFFFL |
7245 | //MMSCH_GPUIOV_DW6_2 |
7246 | #define MMSCH_GPUIOV_DW6_2__DATA__SHIFT 0x0 |
7247 | #define MMSCH_GPUIOV_DW6_2__DATA_MASK 0xFFFFFFFFL |
7248 | //MMSCH_GPUIOV_DW7_2 |
7249 | #define MMSCH_GPUIOV_DW7_2__DATA__SHIFT 0x0 |
7250 | #define MMSCH_GPUIOV_DW7_2__DATA_MASK 0xFFFFFFFFL |
7251 | //MMSCH_GPUIOV_DW8_2 |
7252 | #define MMSCH_GPUIOV_DW8_2__DATA__SHIFT 0x0 |
7253 | #define MMSCH_GPUIOV_DW8_2__DATA_MASK 0xFFFFFFFFL |
7254 | //MMSCH_GPUIOV_SCH_BLOCK_IP_2 |
7255 | #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID__SHIFT 0x0 |
7256 | #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION__SHIFT 0x4 |
7257 | #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE__SHIFT 0x8 |
7258 | #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID_MASK 0x0000000FL |
7259 | #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION_MASK 0x000000F0L |
7260 | #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE_MASK 0x0000FF00L |
7261 | //MMSCH_GPUIOV_CMD_STATUS_IP_2 |
7262 | #define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS__SHIFT 0x0 |
7263 | #define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS_MASK 0x0000000FL |
7264 | //MMSCH_VFID_FIFO_HEAD_2 |
7265 | #define MMSCH_VFID_FIFO_HEAD_2__HEAD__SHIFT 0x0 |
7266 | #define MMSCH_VFID_FIFO_HEAD_2__HEAD_MASK 0x0000003FL |
7267 | //MMSCH_VFID_FIFO_TAIL_2 |
7268 | #define MMSCH_VFID_FIFO_TAIL_2__TAIL__SHIFT 0x0 |
7269 | #define MMSCH_VFID_FIFO_TAIL_2__TAIL_MASK 0x0000003FL |
7270 | //MMSCH_VM_BUSY_STATUS_0 |
7271 | #define MMSCH_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0 |
7272 | #define MMSCH_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL |
7273 | //MMSCH_VM_BUSY_STATUS_1 |
7274 | #define MMSCH_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0 |
7275 | #define MMSCH_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL |
7276 | //MMSCH_VM_BUSY_STATUS_2 |
7277 | #define MMSCH_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0 |
7278 | #define MMSCH_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL |
7279 | |
7280 | |
7281 | // addressBlock: uvd0_slmi_adpdec |
7282 | //UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW |
7283 | #define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
7284 | #define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
7285 | //UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH |
7286 | #define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
7287 | #define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
7288 | //UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW |
7289 | #define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
7290 | #define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
7291 | //UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH |
7292 | #define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
7293 | #define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
7294 | //UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW |
7295 | #define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
7296 | #define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
7297 | //UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH |
7298 | #define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
7299 | #define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
7300 | //UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW |
7301 | #define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
7302 | #define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
7303 | //UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH |
7304 | #define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
7305 | #define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
7306 | //UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW |
7307 | #define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
7308 | #define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
7309 | //UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH |
7310 | #define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
7311 | #define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
7312 | //UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW |
7313 | #define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
7314 | #define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
7315 | //UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH |
7316 | #define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
7317 | #define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
7318 | //UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW |
7319 | #define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
7320 | #define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
7321 | //UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH |
7322 | #define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
7323 | #define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
7324 | //UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW |
7325 | #define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
7326 | #define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
7327 | //UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH |
7328 | #define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
7329 | #define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
7330 | //UVD_LMI_MMSCH_NC_VMID |
7331 | #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID__SHIFT 0x0 |
7332 | #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID__SHIFT 0x4 |
7333 | #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID__SHIFT 0x8 |
7334 | #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID__SHIFT 0xc |
7335 | #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID__SHIFT 0x10 |
7336 | #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID__SHIFT 0x14 |
7337 | #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID__SHIFT 0x18 |
7338 | #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID__SHIFT 0x1c |
7339 | #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID_MASK 0x0000000FL |
7340 | #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID_MASK 0x000000F0L |
7341 | #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID_MASK 0x00000F00L |
7342 | #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID_MASK 0x0000F000L |
7343 | #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID_MASK 0x000F0000L |
7344 | #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID_MASK 0x00F00000L |
7345 | #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID_MASK 0x0F000000L |
7346 | #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID_MASK 0xF0000000L |
7347 | //UVD_LMI_MMSCH_CTRL |
7348 | #define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN__SHIFT 0x0 |
7349 | #define UVD_LMI_MMSCH_CTRL__MMSCH_VM__SHIFT 0x1 |
7350 | #define UVD_LMI_MMSCH_CTRL__PRIV_CLIENT_MMSCH__SHIFT 0x2 |
7351 | #define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP__SHIFT 0x3 |
7352 | #define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP__SHIFT 0x5 |
7353 | #define UVD_LMI_MMSCH_CTRL__MMSCH_RD__SHIFT 0x7 |
7354 | #define UVD_LMI_MMSCH_CTRL__MMSCH_WR__SHIFT 0x9 |
7355 | #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP__SHIFT 0xb |
7356 | #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP__SHIFT 0xc |
7357 | #define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN_MASK 0x00000001L |
7358 | #define UVD_LMI_MMSCH_CTRL__MMSCH_VM_MASK 0x00000002L |
7359 | #define UVD_LMI_MMSCH_CTRL__PRIV_CLIENT_MMSCH_MASK 0x00000004L |
7360 | #define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP_MASK 0x00000018L |
7361 | #define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP_MASK 0x00000060L |
7362 | #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_MASK 0x00000180L |
7363 | #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_MASK 0x00000600L |
7364 | #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP_MASK 0x00000800L |
7365 | #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP_MASK 0x00001000L |
7366 | //UVD_MMSCH_LMI_STATUS |
7367 | #define UVD_MMSCH_LMI_STATUS__MMSCH_LMI_WRITE_CLEAN__SHIFT 0x2 |
7368 | #define UVD_MMSCH_LMI_STATUS__MMSCH_RD_CLEAN__SHIFT 0xd |
7369 | #define UVD_MMSCH_LMI_STATUS__MMSCH_WR_CLEAN__SHIFT 0xe |
7370 | #define UVD_MMSCH_LMI_STATUS__MMSCH_LMI_WRITE_CLEAN_MASK 0x00000004L |
7371 | #define UVD_MMSCH_LMI_STATUS__MMSCH_RD_CLEAN_MASK 0x00002000L |
7372 | #define UVD_MMSCH_LMI_STATUS__MMSCH_WR_CLEAN_MASK 0x00004000L |
7373 | //VCN_RAS_CNTL_MMSCH |
7374 | #define VCN_RAS_CNTL_MMSCH__MMSCH_FATAL_ERROR_EN__SHIFT 0x1 |
7375 | #define VCN_RAS_CNTL_MMSCH__MMSCH_PMI_EN__SHIFT 0x5 |
7376 | #define VCN_RAS_CNTL_MMSCH__MMSCH_REARM__SHIFT 0x9 |
7377 | #define VCN_RAS_CNTL_MMSCH__MMSCH_READY__SHIFT 0x11 |
7378 | #define VCN_RAS_CNTL_MMSCH__MMSCH_FATAL_ERROR_EN_MASK 0x00000002L |
7379 | #define VCN_RAS_CNTL_MMSCH__MMSCH_PMI_EN_MASK 0x00000020L |
7380 | #define VCN_RAS_CNTL_MMSCH__MMSCH_REARM_MASK 0x00000200L |
7381 | #define VCN_RAS_CNTL_MMSCH__MMSCH_READY_MASK 0x00020000L |
7382 | |
7383 | |
7384 | // addressBlock: uvdctxind |
7385 | //UVD_CGC_MEM_CTRL |
7386 | #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0 |
7387 | #define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1 |
7388 | #define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2 |
7389 | #define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3 |
7390 | #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4 |
7391 | #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5 |
7392 | #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6 |
7393 | #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7 |
7394 | #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8 |
7395 | #define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9 |
7396 | #define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa |
7397 | #define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc |
7398 | #define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd |
7399 | #define UVD_CGC_MEM_CTRL__MMSCH_LS_EN__SHIFT 0xe |
7400 | #define UVD_CGC_MEM_CTRL__MPC1_LS_EN__SHIFT 0xf |
7401 | #define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 |
7402 | #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 |
7403 | #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x00000001L |
7404 | #define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x00000002L |
7405 | #define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x00000004L |
7406 | #define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x00000008L |
7407 | #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x00000010L |
7408 | #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x00000020L |
7409 | #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x00000040L |
7410 | #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x00000080L |
7411 | #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x00000100L |
7412 | #define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x00000200L |
7413 | #define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x00000400L |
7414 | #define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x00001000L |
7415 | #define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x00002000L |
7416 | #define UVD_CGC_MEM_CTRL__MMSCH_LS_EN_MASK 0x00004000L |
7417 | #define UVD_CGC_MEM_CTRL__MPC1_LS_EN_MASK 0x00008000L |
7418 | #define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000F0000L |
7419 | #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00F00000L |
7420 | //UVD_CGC_CTRL2 |
7421 | #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0 |
7422 | #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1 |
7423 | #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2 |
7424 | #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L |
7425 | #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L |
7426 | #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001CL |
7427 | //UVD_CGC_MEM_DS_CTRL |
7428 | #define UVD_CGC_MEM_DS_CTRL__LMI_MC_DS_EN__SHIFT 0x0 |
7429 | #define UVD_CGC_MEM_DS_CTRL__MPC_DS_EN__SHIFT 0x1 |
7430 | #define UVD_CGC_MEM_DS_CTRL__MPRD_DS_EN__SHIFT 0x2 |
7431 | #define UVD_CGC_MEM_DS_CTRL__WCB_DS_EN__SHIFT 0x3 |
7432 | #define UVD_CGC_MEM_DS_CTRL__UDEC_RE_DS_EN__SHIFT 0x4 |
7433 | #define UVD_CGC_MEM_DS_CTRL__UDEC_CM_DS_EN__SHIFT 0x5 |
7434 | #define UVD_CGC_MEM_DS_CTRL__UDEC_IT_DS_EN__SHIFT 0x6 |
7435 | #define UVD_CGC_MEM_DS_CTRL__UDEC_DB_DS_EN__SHIFT 0x7 |
7436 | #define UVD_CGC_MEM_DS_CTRL__UDEC_MP_DS_EN__SHIFT 0x8 |
7437 | #define UVD_CGC_MEM_DS_CTRL__SYS_DS_EN__SHIFT 0x9 |
7438 | #define UVD_CGC_MEM_DS_CTRL__VCPU_DS_EN__SHIFT 0xa |
7439 | #define UVD_CGC_MEM_DS_CTRL__MIF_DS_EN__SHIFT 0xc |
7440 | #define UVD_CGC_MEM_DS_CTRL__LCM_DS_EN__SHIFT 0xd |
7441 | #define UVD_CGC_MEM_DS_CTRL__MMSCH_DS_EN__SHIFT 0xe |
7442 | #define UVD_CGC_MEM_DS_CTRL__MPC1_DS_EN__SHIFT 0xf |
7443 | #define UVD_CGC_MEM_DS_CTRL__LMI_MC_DS_EN_MASK 0x00000001L |
7444 | #define UVD_CGC_MEM_DS_CTRL__MPC_DS_EN_MASK 0x00000002L |
7445 | #define UVD_CGC_MEM_DS_CTRL__MPRD_DS_EN_MASK 0x00000004L |
7446 | #define UVD_CGC_MEM_DS_CTRL__WCB_DS_EN_MASK 0x00000008L |
7447 | #define UVD_CGC_MEM_DS_CTRL__UDEC_RE_DS_EN_MASK 0x00000010L |
7448 | #define UVD_CGC_MEM_DS_CTRL__UDEC_CM_DS_EN_MASK 0x00000020L |
7449 | #define UVD_CGC_MEM_DS_CTRL__UDEC_IT_DS_EN_MASK 0x00000040L |
7450 | #define UVD_CGC_MEM_DS_CTRL__UDEC_DB_DS_EN_MASK 0x00000080L |
7451 | #define UVD_CGC_MEM_DS_CTRL__UDEC_MP_DS_EN_MASK 0x00000100L |
7452 | #define UVD_CGC_MEM_DS_CTRL__SYS_DS_EN_MASK 0x00000200L |
7453 | #define UVD_CGC_MEM_DS_CTRL__VCPU_DS_EN_MASK 0x00000400L |
7454 | #define UVD_CGC_MEM_DS_CTRL__MIF_DS_EN_MASK 0x00001000L |
7455 | #define UVD_CGC_MEM_DS_CTRL__LCM_DS_EN_MASK 0x00002000L |
7456 | #define UVD_CGC_MEM_DS_CTRL__MMSCH_DS_EN_MASK 0x00004000L |
7457 | #define UVD_CGC_MEM_DS_CTRL__MPC1_DS_EN_MASK 0x00008000L |
7458 | //UVD_CGC_MEM_SD_CTRL |
7459 | #define UVD_CGC_MEM_SD_CTRL__LMI_MC_SD_EN__SHIFT 0x0 |
7460 | #define UVD_CGC_MEM_SD_CTRL__MPC_SD_EN__SHIFT 0x1 |
7461 | #define UVD_CGC_MEM_SD_CTRL__MPRD_SD_EN__SHIFT 0x2 |
7462 | #define UVD_CGC_MEM_SD_CTRL__WCB_SD_EN__SHIFT 0x3 |
7463 | #define UVD_CGC_MEM_SD_CTRL__UDEC_RE_SD_EN__SHIFT 0x4 |
7464 | #define UVD_CGC_MEM_SD_CTRL__UDEC_CM_SD_EN__SHIFT 0x5 |
7465 | #define UVD_CGC_MEM_SD_CTRL__UDEC_IT_SD_EN__SHIFT 0x6 |
7466 | #define UVD_CGC_MEM_SD_CTRL__UDEC_DB_SD_EN__SHIFT 0x7 |
7467 | #define UVD_CGC_MEM_SD_CTRL__UDEC_MP_SD_EN__SHIFT 0x8 |
7468 | #define UVD_CGC_MEM_SD_CTRL__SYS_SD_EN__SHIFT 0x9 |
7469 | #define UVD_CGC_MEM_SD_CTRL__VCPU_SD_EN__SHIFT 0xa |
7470 | #define UVD_CGC_MEM_SD_CTRL__MIF_SD_EN__SHIFT 0xc |
7471 | #define UVD_CGC_MEM_SD_CTRL__LCM_SD_EN__SHIFT 0xd |
7472 | #define UVD_CGC_MEM_SD_CTRL__MMSCH_SD_EN__SHIFT 0xe |
7473 | #define UVD_CGC_MEM_SD_CTRL__MPC1_SD_EN__SHIFT 0xf |
7474 | #define UVD_CGC_MEM_SD_CTRL__LMI_MC_SD_EN_MASK 0x00000001L |
7475 | #define UVD_CGC_MEM_SD_CTRL__MPC_SD_EN_MASK 0x00000002L |
7476 | #define UVD_CGC_MEM_SD_CTRL__MPRD_SD_EN_MASK 0x00000004L |
7477 | #define UVD_CGC_MEM_SD_CTRL__WCB_SD_EN_MASK 0x00000008L |
7478 | #define UVD_CGC_MEM_SD_CTRL__UDEC_RE_SD_EN_MASK 0x00000010L |
7479 | #define UVD_CGC_MEM_SD_CTRL__UDEC_CM_SD_EN_MASK 0x00000020L |
7480 | #define UVD_CGC_MEM_SD_CTRL__UDEC_IT_SD_EN_MASK 0x00000040L |
7481 | #define UVD_CGC_MEM_SD_CTRL__UDEC_DB_SD_EN_MASK 0x00000080L |
7482 | #define UVD_CGC_MEM_SD_CTRL__UDEC_MP_SD_EN_MASK 0x00000100L |
7483 | #define UVD_CGC_MEM_SD_CTRL__SYS_SD_EN_MASK 0x00000200L |
7484 | #define UVD_CGC_MEM_SD_CTRL__VCPU_SD_EN_MASK 0x00000400L |
7485 | #define UVD_CGC_MEM_SD_CTRL__MIF_SD_EN_MASK 0x00001000L |
7486 | #define UVD_CGC_MEM_SD_CTRL__LCM_SD_EN_MASK 0x00002000L |
7487 | #define UVD_CGC_MEM_SD_CTRL__MMSCH_SD_EN_MASK 0x00004000L |
7488 | #define UVD_CGC_MEM_SD_CTRL__MPC1_SD_EN_MASK 0x00008000L |
7489 | //UVD_SW_SCRATCH_00 |
7490 | #define UVD_SW_SCRATCH_00__DATA__SHIFT 0x0 |
7491 | #define UVD_SW_SCRATCH_00__DATA_MASK 0xFFFFFFFFL |
7492 | //UVD_SW_SCRATCH_01 |
7493 | #define UVD_SW_SCRATCH_01__DATA__SHIFT 0x0 |
7494 | #define UVD_SW_SCRATCH_01__DATA_MASK 0xFFFFFFFFL |
7495 | //UVD_SW_SCRATCH_02 |
7496 | #define UVD_SW_SCRATCH_02__DATA__SHIFT 0x0 |
7497 | #define UVD_SW_SCRATCH_02__DATA_MASK 0xFFFFFFFFL |
7498 | //UVD_SW_SCRATCH_03 |
7499 | #define UVD_SW_SCRATCH_03__DATA__SHIFT 0x0 |
7500 | #define UVD_SW_SCRATCH_03__DATA_MASK 0xFFFFFFFFL |
7501 | //UVD_SW_SCRATCH_04 |
7502 | #define UVD_SW_SCRATCH_04__DATA__SHIFT 0x0 |
7503 | #define UVD_SW_SCRATCH_04__DATA_MASK 0xFFFFFFFFL |
7504 | //UVD_SW_SCRATCH_05 |
7505 | #define UVD_SW_SCRATCH_05__DATA__SHIFT 0x0 |
7506 | #define UVD_SW_SCRATCH_05__DATA_MASK 0xFFFFFFFFL |
7507 | //UVD_SW_SCRATCH_06 |
7508 | #define UVD_SW_SCRATCH_06__DATA__SHIFT 0x0 |
7509 | #define UVD_SW_SCRATCH_06__DATA_MASK 0xFFFFFFFFL |
7510 | //UVD_SW_SCRATCH_07 |
7511 | #define UVD_SW_SCRATCH_07__DATA__SHIFT 0x0 |
7512 | #define UVD_SW_SCRATCH_07__DATA_MASK 0xFFFFFFFFL |
7513 | //UVD_SW_SCRATCH_08 |
7514 | #define UVD_SW_SCRATCH_08__DATA__SHIFT 0x0 |
7515 | #define UVD_SW_SCRATCH_08__DATA_MASK 0xFFFFFFFFL |
7516 | //UVD_SW_SCRATCH_09 |
7517 | #define UVD_SW_SCRATCH_09__DATA__SHIFT 0x0 |
7518 | #define UVD_SW_SCRATCH_09__DATA_MASK 0xFFFFFFFFL |
7519 | //UVD_SW_SCRATCH_10 |
7520 | #define UVD_SW_SCRATCH_10__DATA__SHIFT 0x0 |
7521 | #define UVD_SW_SCRATCH_10__DATA_MASK 0xFFFFFFFFL |
7522 | //UVD_SW_SCRATCH_11 |
7523 | #define UVD_SW_SCRATCH_11__DATA__SHIFT 0x0 |
7524 | #define UVD_SW_SCRATCH_11__DATA_MASK 0xFFFFFFFFL |
7525 | //UVD_SW_SCRATCH_12 |
7526 | #define UVD_SW_SCRATCH_12__DATA__SHIFT 0x0 |
7527 | #define UVD_SW_SCRATCH_12__DATA_MASK 0xFFFFFFFFL |
7528 | //UVD_SW_SCRATCH_13 |
7529 | #define UVD_SW_SCRATCH_13__DATA__SHIFT 0x0 |
7530 | #define UVD_SW_SCRATCH_13__DATA_MASK 0xFFFFFFFFL |
7531 | //UVD_SW_SCRATCH_14 |
7532 | #define UVD_SW_SCRATCH_14__DATA__SHIFT 0x0 |
7533 | #define UVD_SW_SCRATCH_14__DATA_MASK 0xFFFFFFFFL |
7534 | //UVD_SW_SCRATCH_15 |
7535 | #define UVD_SW_SCRATCH_15__DATA__SHIFT 0x0 |
7536 | #define UVD_SW_SCRATCH_15__DATA_MASK 0xFFFFFFFFL |
7537 | //UVD_IH_SEM_CTRL |
7538 | #define UVD_IH_SEM_CTRL__IH_STALL_EN__SHIFT 0x0 |
7539 | #define UVD_IH_SEM_CTRL__SEM_STALL_EN__SHIFT 0x1 |
7540 | #define UVD_IH_SEM_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 |
7541 | #define UVD_IH_SEM_CTRL__SEM_STATUS_CLEAN__SHIFT 0x3 |
7542 | #define UVD_IH_SEM_CTRL__IH_VMID__SHIFT 0x4 |
7543 | #define UVD_IH_SEM_CTRL__IH_USER_DATA__SHIFT 0x8 |
7544 | #define UVD_IH_SEM_CTRL__IH_RINGID__SHIFT 0x14 |
7545 | #define UVD_IH_SEM_CTRL__IH_STALL_EN_MASK 0x00000001L |
7546 | #define UVD_IH_SEM_CTRL__SEM_STALL_EN_MASK 0x00000002L |
7547 | #define UVD_IH_SEM_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L |
7548 | #define UVD_IH_SEM_CTRL__SEM_STATUS_CLEAN_MASK 0x00000008L |
7549 | #define UVD_IH_SEM_CTRL__IH_VMID_MASK 0x000000F0L |
7550 | #define UVD_IH_SEM_CTRL__IH_USER_DATA_MASK 0x000FFF00L |
7551 | #define UVD_IH_SEM_CTRL__IH_RINGID_MASK 0x0FF00000L |
7552 | |
7553 | |
7554 | // addressBlock: lmi_adp_indirect |
7555 | //UVD_LMI_CRC0 |
7556 | #define UVD_LMI_CRC0__CRC32__SHIFT 0x0 |
7557 | #define UVD_LMI_CRC0__CRC32_MASK 0xFFFFFFFFL |
7558 | //UVD_LMI_CRC1 |
7559 | #define UVD_LMI_CRC1__CRC32__SHIFT 0x0 |
7560 | #define UVD_LMI_CRC1__CRC32_MASK 0xFFFFFFFFL |
7561 | //UVD_LMI_CRC2 |
7562 | #define UVD_LMI_CRC2__CRC32__SHIFT 0x0 |
7563 | #define UVD_LMI_CRC2__CRC32_MASK 0xFFFFFFFFL |
7564 | //UVD_LMI_CRC3 |
7565 | #define UVD_LMI_CRC3__CRC32__SHIFT 0x0 |
7566 | #define UVD_LMI_CRC3__CRC32_MASK 0xFFFFFFFFL |
7567 | //UVD_LMI_CRC10 |
7568 | #define UVD_LMI_CRC10__CRC32__SHIFT 0x0 |
7569 | #define UVD_LMI_CRC10__CRC32_MASK 0xFFFFFFFFL |
7570 | //UVD_LMI_CRC11 |
7571 | #define UVD_LMI_CRC11__CRC32__SHIFT 0x0 |
7572 | #define UVD_LMI_CRC11__CRC32_MASK 0xFFFFFFFFL |
7573 | //UVD_LMI_CRC12 |
7574 | #define UVD_LMI_CRC12__CRC32__SHIFT 0x0 |
7575 | #define UVD_LMI_CRC12__CRC32_MASK 0xFFFFFFFFL |
7576 | //UVD_LMI_CRC13 |
7577 | #define UVD_LMI_CRC13__CRC32__SHIFT 0x0 |
7578 | #define UVD_LMI_CRC13__CRC32_MASK 0xFFFFFFFFL |
7579 | //UVD_LMI_CRC14 |
7580 | #define UVD_LMI_CRC14__CRC32__SHIFT 0x0 |
7581 | #define UVD_LMI_CRC14__CRC32_MASK 0xFFFFFFFFL |
7582 | //UVD_LMI_CRC15 |
7583 | #define UVD_LMI_CRC15__CRC32__SHIFT 0x0 |
7584 | #define UVD_LMI_CRC15__CRC32_MASK 0xFFFFFFFFL |
7585 | //UVD_LMI_SWAP_CNTL2 |
7586 | #define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0 |
7587 | #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2 |
7588 | #define UVD_LMI_SWAP_CNTL2__ATOMIC_MC_SWAP__SHIFT 0x4 |
7589 | #define UVD_LMI_SWAP_CNTL2__CENC_MC_SWAP__SHIFT 0xc |
7590 | #define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x00000003L |
7591 | #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0x0000000CL |
7592 | #define UVD_LMI_SWAP_CNTL2__ATOMIC_MC_SWAP_MASK 0x00000FF0L |
7593 | #define UVD_LMI_SWAP_CNTL2__CENC_MC_SWAP_MASK 0x00003000L |
7594 | //UVD_MEMCHECK_SYS_INT_EN |
7595 | #define UVD_MEMCHECK_SYS_INT_EN__RE_ERR_EN__SHIFT 0x0 |
7596 | #define UVD_MEMCHECK_SYS_INT_EN__IT_ERR_EN__SHIFT 0x1 |
7597 | #define UVD_MEMCHECK_SYS_INT_EN__MP_ERR_EN__SHIFT 0x2 |
7598 | #define UVD_MEMCHECK_SYS_INT_EN__DB_ERR_EN__SHIFT 0x3 |
7599 | #define UVD_MEMCHECK_SYS_INT_EN__DBW_ERR_EN__SHIFT 0x4 |
7600 | #define UVD_MEMCHECK_SYS_INT_EN__CM_ERR_EN__SHIFT 0x5 |
7601 | #define UVD_MEMCHECK_SYS_INT_EN__MIF_REF_ERR_EN__SHIFT 0x6 |
7602 | #define UVD_MEMCHECK_SYS_INT_EN__MIF_DBW_ERR_EN__SHIFT 0x8 |
7603 | #define UVD_MEMCHECK_SYS_INT_EN__MIF_CM_COLOC_ERR_EN__SHIFT 0x9 |
7604 | #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP0_ERR_EN__SHIFT 0xa |
7605 | #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP1_ERR_EN__SHIFT 0xb |
7606 | #define UVD_MEMCHECK_SYS_INT_EN__SRE_ERR_EN__SHIFT 0xc |
7607 | #define UVD_MEMCHECK_SYS_INT_EN__IT_RD_ERR_EN__SHIFT 0xf |
7608 | #define UVD_MEMCHECK_SYS_INT_EN__CM_RD_ERR_EN__SHIFT 0x10 |
7609 | #define UVD_MEMCHECK_SYS_INT_EN__DB_RD_ERR_EN__SHIFT 0x11 |
7610 | #define UVD_MEMCHECK_SYS_INT_EN__MIF_RD_ERR_EN__SHIFT 0x12 |
7611 | #define UVD_MEMCHECK_SYS_INT_EN__IDCT_RD_ERR_EN__SHIFT 0x13 |
7612 | #define UVD_MEMCHECK_SYS_INT_EN__MPC_RD_ERR_EN__SHIFT 0x14 |
7613 | #define UVD_MEMCHECK_SYS_INT_EN__LBSI_RD_ERR_EN__SHIFT 0x15 |
7614 | #define UVD_MEMCHECK_SYS_INT_EN__RBC_RD_ERR_EN__SHIFT 0x18 |
7615 | #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP2_ERR_EN__SHIFT 0x1b |
7616 | #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP3_ERR_EN__SHIFT 0x1c |
7617 | #define UVD_MEMCHECK_SYS_INT_EN__MIF_SCLR_ERR_EN__SHIFT 0x1d |
7618 | #define UVD_MEMCHECK_SYS_INT_EN__MIF_SCLR2_ERR_EN__SHIFT 0x1e |
7619 | #define UVD_MEMCHECK_SYS_INT_EN__PREF_ERR_EN__SHIFT 0x1f |
7620 | #define UVD_MEMCHECK_SYS_INT_EN__RE_ERR_EN_MASK 0x00000001L |
7621 | #define UVD_MEMCHECK_SYS_INT_EN__IT_ERR_EN_MASK 0x00000002L |
7622 | #define UVD_MEMCHECK_SYS_INT_EN__MP_ERR_EN_MASK 0x00000004L |
7623 | #define UVD_MEMCHECK_SYS_INT_EN__DB_ERR_EN_MASK 0x00000008L |
7624 | #define UVD_MEMCHECK_SYS_INT_EN__DBW_ERR_EN_MASK 0x00000010L |
7625 | #define UVD_MEMCHECK_SYS_INT_EN__CM_ERR_EN_MASK 0x00000020L |
7626 | #define UVD_MEMCHECK_SYS_INT_EN__MIF_REF_ERR_EN_MASK 0x00000040L |
7627 | #define UVD_MEMCHECK_SYS_INT_EN__MIF_DBW_ERR_EN_MASK 0x00000100L |
7628 | #define UVD_MEMCHECK_SYS_INT_EN__MIF_CM_COLOC_ERR_EN_MASK 0x00000200L |
7629 | #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP0_ERR_EN_MASK 0x00000400L |
7630 | #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP1_ERR_EN_MASK 0x00000800L |
7631 | #define UVD_MEMCHECK_SYS_INT_EN__SRE_ERR_EN_MASK 0x00001000L |
7632 | #define UVD_MEMCHECK_SYS_INT_EN__IT_RD_ERR_EN_MASK 0x00008000L |
7633 | #define UVD_MEMCHECK_SYS_INT_EN__CM_RD_ERR_EN_MASK 0x00010000L |
7634 | #define UVD_MEMCHECK_SYS_INT_EN__DB_RD_ERR_EN_MASK 0x00020000L |
7635 | #define UVD_MEMCHECK_SYS_INT_EN__MIF_RD_ERR_EN_MASK 0x00040000L |
7636 | #define UVD_MEMCHECK_SYS_INT_EN__IDCT_RD_ERR_EN_MASK 0x00080000L |
7637 | #define UVD_MEMCHECK_SYS_INT_EN__MPC_RD_ERR_EN_MASK 0x00100000L |
7638 | #define UVD_MEMCHECK_SYS_INT_EN__LBSI_RD_ERR_EN_MASK 0x00200000L |
7639 | #define UVD_MEMCHECK_SYS_INT_EN__RBC_RD_ERR_EN_MASK 0x01000000L |
7640 | #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP2_ERR_EN_MASK 0x08000000L |
7641 | #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP3_ERR_EN_MASK 0x10000000L |
7642 | #define UVD_MEMCHECK_SYS_INT_EN__MIF_SCLR_ERR_EN_MASK 0x20000000L |
7643 | #define UVD_MEMCHECK_SYS_INT_EN__MIF_SCLR2_ERR_EN_MASK 0x40000000L |
7644 | #define UVD_MEMCHECK_SYS_INT_EN__PREF_ERR_EN_MASK 0x80000000L |
7645 | //UVD_MEMCHECK_SYS_INT_STAT |
7646 | #define UVD_MEMCHECK_SYS_INT_STAT__RE_LO_ERR__SHIFT 0x0 |
7647 | #define UVD_MEMCHECK_SYS_INT_STAT__RE_HI_ERR__SHIFT 0x1 |
7648 | #define UVD_MEMCHECK_SYS_INT_STAT__IT_LO_ERR__SHIFT 0x2 |
7649 | #define UVD_MEMCHECK_SYS_INT_STAT__IT_HI_ERR__SHIFT 0x3 |
7650 | #define UVD_MEMCHECK_SYS_INT_STAT__MP_LO_ERR__SHIFT 0x4 |
7651 | #define UVD_MEMCHECK_SYS_INT_STAT__MP_HI_ERR__SHIFT 0x5 |
7652 | #define UVD_MEMCHECK_SYS_INT_STAT__DB_LO_ERR__SHIFT 0x6 |
7653 | #define UVD_MEMCHECK_SYS_INT_STAT__DB_HI_ERR__SHIFT 0x7 |
7654 | #define UVD_MEMCHECK_SYS_INT_STAT__DBW_LO_ERR__SHIFT 0x8 |
7655 | #define UVD_MEMCHECK_SYS_INT_STAT__DBW_HI_ERR__SHIFT 0x9 |
7656 | #define UVD_MEMCHECK_SYS_INT_STAT__CM_LO_ERR__SHIFT 0xa |
7657 | #define UVD_MEMCHECK_SYS_INT_STAT__CM_HI_ERR__SHIFT 0xb |
7658 | #define UVD_MEMCHECK_SYS_INT_STAT__MIF_REF_LO_ERR__SHIFT 0xc |
7659 | #define UVD_MEMCHECK_SYS_INT_STAT__MIF_REF_HI_ERR__SHIFT 0xd |
7660 | #define UVD_MEMCHECK_SYS_INT_STAT__VCPU_LO_ERR__SHIFT 0xe |
7661 | #define UVD_MEMCHECK_SYS_INT_STAT__VCPU_HI_ERR__SHIFT 0xf |
7662 | #define UVD_MEMCHECK_SYS_INT_STAT__MIF_DBW_LO_ERR__SHIFT 0x10 |
7663 | #define UVD_MEMCHECK_SYS_INT_STAT__MIF_DBW_HI_ERR__SHIFT 0x11 |
7664 | #define UVD_MEMCHECK_SYS_INT_STAT__MIF_CM_COLOC_LO_ERR__SHIFT 0x12 |
7665 | #define UVD_MEMCHECK_SYS_INT_STAT__MIF_CM_COLOC_HI_ERR__SHIFT 0x13 |
7666 | #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP0_LO_ERR__SHIFT 0x14 |
7667 | #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP0_HI_ERR__SHIFT 0x15 |
7668 | #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP1_LO_ERR__SHIFT 0x16 |
7669 | #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP1_HI_ERR__SHIFT 0x17 |
7670 | #define UVD_MEMCHECK_SYS_INT_STAT__SRE_LO_ERR__SHIFT 0x18 |
7671 | #define UVD_MEMCHECK_SYS_INT_STAT__SRE_HI_ERR__SHIFT 0x19 |
7672 | #define UVD_MEMCHECK_SYS_INT_STAT__IT_RD_LO_ERR__SHIFT 0x1e |
7673 | #define UVD_MEMCHECK_SYS_INT_STAT__IT_RD_HI_ERR__SHIFT 0x1f |
7674 | #define UVD_MEMCHECK_SYS_INT_STAT__RE_LO_ERR_MASK 0x00000001L |
7675 | #define UVD_MEMCHECK_SYS_INT_STAT__RE_HI_ERR_MASK 0x00000002L |
7676 | #define UVD_MEMCHECK_SYS_INT_STAT__IT_LO_ERR_MASK 0x00000004L |
7677 | #define UVD_MEMCHECK_SYS_INT_STAT__IT_HI_ERR_MASK 0x00000008L |
7678 | #define UVD_MEMCHECK_SYS_INT_STAT__MP_LO_ERR_MASK 0x00000010L |
7679 | #define UVD_MEMCHECK_SYS_INT_STAT__MP_HI_ERR_MASK 0x00000020L |
7680 | #define UVD_MEMCHECK_SYS_INT_STAT__DB_LO_ERR_MASK 0x00000040L |
7681 | #define UVD_MEMCHECK_SYS_INT_STAT__DB_HI_ERR_MASK 0x00000080L |
7682 | #define UVD_MEMCHECK_SYS_INT_STAT__DBW_LO_ERR_MASK 0x00000100L |
7683 | #define UVD_MEMCHECK_SYS_INT_STAT__DBW_HI_ERR_MASK 0x00000200L |
7684 | #define UVD_MEMCHECK_SYS_INT_STAT__CM_LO_ERR_MASK 0x00000400L |
7685 | #define UVD_MEMCHECK_SYS_INT_STAT__CM_HI_ERR_MASK 0x00000800L |
7686 | #define UVD_MEMCHECK_SYS_INT_STAT__MIF_REF_LO_ERR_MASK 0x00001000L |
7687 | #define UVD_MEMCHECK_SYS_INT_STAT__MIF_REF_HI_ERR_MASK 0x00002000L |
7688 | #define UVD_MEMCHECK_SYS_INT_STAT__VCPU_LO_ERR_MASK 0x00004000L |
7689 | #define UVD_MEMCHECK_SYS_INT_STAT__VCPU_HI_ERR_MASK 0x00008000L |
7690 | #define UVD_MEMCHECK_SYS_INT_STAT__MIF_DBW_LO_ERR_MASK 0x00010000L |
7691 | #define UVD_MEMCHECK_SYS_INT_STAT__MIF_DBW_HI_ERR_MASK 0x00020000L |
7692 | #define UVD_MEMCHECK_SYS_INT_STAT__MIF_CM_COLOC_LO_ERR_MASK 0x00040000L |
7693 | #define UVD_MEMCHECK_SYS_INT_STAT__MIF_CM_COLOC_HI_ERR_MASK 0x00080000L |
7694 | #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP0_LO_ERR_MASK 0x00100000L |
7695 | #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP0_HI_ERR_MASK 0x00200000L |
7696 | #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP1_LO_ERR_MASK 0x00400000L |
7697 | #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP1_HI_ERR_MASK 0x00800000L |
7698 | #define UVD_MEMCHECK_SYS_INT_STAT__SRE_LO_ERR_MASK 0x01000000L |
7699 | #define UVD_MEMCHECK_SYS_INT_STAT__SRE_HI_ERR_MASK 0x02000000L |
7700 | #define UVD_MEMCHECK_SYS_INT_STAT__IT_RD_LO_ERR_MASK 0x40000000L |
7701 | #define UVD_MEMCHECK_SYS_INT_STAT__IT_RD_HI_ERR_MASK 0x80000000L |
7702 | //UVD_MEMCHECK_SYS_INT_ACK |
7703 | #define UVD_MEMCHECK_SYS_INT_ACK__RE_LO_ACK__SHIFT 0x0 |
7704 | #define UVD_MEMCHECK_SYS_INT_ACK__RE_HI_ACK__SHIFT 0x1 |
7705 | #define UVD_MEMCHECK_SYS_INT_ACK__IT_LO_ACK__SHIFT 0x2 |
7706 | #define UVD_MEMCHECK_SYS_INT_ACK__IT_HI_ACK__SHIFT 0x3 |
7707 | #define UVD_MEMCHECK_SYS_INT_ACK__MP_LO_ACK__SHIFT 0x4 |
7708 | #define UVD_MEMCHECK_SYS_INT_ACK__MP_HI_ACK__SHIFT 0x5 |
7709 | #define UVD_MEMCHECK_SYS_INT_ACK__DB_LO_ACK__SHIFT 0x6 |
7710 | #define UVD_MEMCHECK_SYS_INT_ACK__DB_HI_ACK__SHIFT 0x7 |
7711 | #define UVD_MEMCHECK_SYS_INT_ACK__DBW_LO_ACK__SHIFT 0x8 |
7712 | #define UVD_MEMCHECK_SYS_INT_ACK__DBW_HI_ACK__SHIFT 0x9 |
7713 | #define UVD_MEMCHECK_SYS_INT_ACK__CM_LO_ACK__SHIFT 0xa |
7714 | #define UVD_MEMCHECK_SYS_INT_ACK__CM_HI_ACK__SHIFT 0xb |
7715 | #define UVD_MEMCHECK_SYS_INT_ACK__MIF_REF_LO_ACK__SHIFT 0xc |
7716 | #define UVD_MEMCHECK_SYS_INT_ACK__MIF_REF_HI_ACK__SHIFT 0xd |
7717 | #define UVD_MEMCHECK_SYS_INT_ACK__VCPU_LO_ACK__SHIFT 0xe |
7718 | #define UVD_MEMCHECK_SYS_INT_ACK__VCPU_HI_ACK__SHIFT 0xf |
7719 | #define UVD_MEMCHECK_SYS_INT_ACK__MIF_DBW_LO_ACK__SHIFT 0x10 |
7720 | #define UVD_MEMCHECK_SYS_INT_ACK__MIF_DBW_HI_ACK__SHIFT 0x11 |
7721 | #define UVD_MEMCHECK_SYS_INT_ACK__MIF_CM_COLOC_LO_ACK__SHIFT 0x12 |
7722 | #define UVD_MEMCHECK_SYS_INT_ACK__MIF_CM_COLOC_HI_ACK__SHIFT 0x13 |
7723 | #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP0_LO_ACK__SHIFT 0x14 |
7724 | #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP0_HI_ACK__SHIFT 0x15 |
7725 | #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP1_LO_ACK__SHIFT 0x16 |
7726 | #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP1_HI_ACK__SHIFT 0x17 |
7727 | #define UVD_MEMCHECK_SYS_INT_ACK__SRE_LO_ACK__SHIFT 0x18 |
7728 | #define UVD_MEMCHECK_SYS_INT_ACK__SRE_HI_ACK__SHIFT 0x19 |
7729 | #define UVD_MEMCHECK_SYS_INT_ACK__IT_RD_LO_ACK__SHIFT 0x1e |
7730 | #define UVD_MEMCHECK_SYS_INT_ACK__IT_RD_HI_ACK__SHIFT 0x1f |
7731 | #define UVD_MEMCHECK_SYS_INT_ACK__RE_LO_ACK_MASK 0x00000001L |
7732 | #define UVD_MEMCHECK_SYS_INT_ACK__RE_HI_ACK_MASK 0x00000002L |
7733 | #define UVD_MEMCHECK_SYS_INT_ACK__IT_LO_ACK_MASK 0x00000004L |
7734 | #define UVD_MEMCHECK_SYS_INT_ACK__IT_HI_ACK_MASK 0x00000008L |
7735 | #define UVD_MEMCHECK_SYS_INT_ACK__MP_LO_ACK_MASK 0x00000010L |
7736 | #define UVD_MEMCHECK_SYS_INT_ACK__MP_HI_ACK_MASK 0x00000020L |
7737 | #define UVD_MEMCHECK_SYS_INT_ACK__DB_LO_ACK_MASK 0x00000040L |
7738 | #define UVD_MEMCHECK_SYS_INT_ACK__DB_HI_ACK_MASK 0x00000080L |
7739 | #define UVD_MEMCHECK_SYS_INT_ACK__DBW_LO_ACK_MASK 0x00000100L |
7740 | #define UVD_MEMCHECK_SYS_INT_ACK__DBW_HI_ACK_MASK 0x00000200L |
7741 | #define UVD_MEMCHECK_SYS_INT_ACK__CM_LO_ACK_MASK 0x00000400L |
7742 | #define UVD_MEMCHECK_SYS_INT_ACK__CM_HI_ACK_MASK 0x00000800L |
7743 | #define UVD_MEMCHECK_SYS_INT_ACK__MIF_REF_LO_ACK_MASK 0x00001000L |
7744 | #define UVD_MEMCHECK_SYS_INT_ACK__MIF_REF_HI_ACK_MASK 0x00002000L |
7745 | #define UVD_MEMCHECK_SYS_INT_ACK__VCPU_LO_ACK_MASK 0x00004000L |
7746 | #define UVD_MEMCHECK_SYS_INT_ACK__VCPU_HI_ACK_MASK 0x00008000L |
7747 | #define UVD_MEMCHECK_SYS_INT_ACK__MIF_DBW_LO_ACK_MASK 0x00010000L |
7748 | #define UVD_MEMCHECK_SYS_INT_ACK__MIF_DBW_HI_ACK_MASK 0x00020000L |
7749 | #define UVD_MEMCHECK_SYS_INT_ACK__MIF_CM_COLOC_LO_ACK_MASK 0x00040000L |
7750 | #define UVD_MEMCHECK_SYS_INT_ACK__MIF_CM_COLOC_HI_ACK_MASK 0x00080000L |
7751 | #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP0_LO_ACK_MASK 0x00100000L |
7752 | #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP0_HI_ACK_MASK 0x00200000L |
7753 | #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP1_LO_ACK_MASK 0x00400000L |
7754 | #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP1_HI_ACK_MASK 0x00800000L |
7755 | #define UVD_MEMCHECK_SYS_INT_ACK__SRE_LO_ACK_MASK 0x01000000L |
7756 | #define UVD_MEMCHECK_SYS_INT_ACK__SRE_HI_ACK_MASK 0x02000000L |
7757 | #define UVD_MEMCHECK_SYS_INT_ACK__IT_RD_LO_ACK_MASK 0x40000000L |
7758 | #define UVD_MEMCHECK_SYS_INT_ACK__IT_RD_HI_ACK_MASK 0x80000000L |
7759 | //UVD_MEMCHECK_VCPU_INT_EN |
7760 | #define UVD_MEMCHECK_VCPU_INT_EN__RE_ERR_EN__SHIFT 0x0 |
7761 | #define UVD_MEMCHECK_VCPU_INT_EN__IT_ERR_EN__SHIFT 0x1 |
7762 | #define UVD_MEMCHECK_VCPU_INT_EN__MP_ERR_EN__SHIFT 0x2 |
7763 | #define UVD_MEMCHECK_VCPU_INT_EN__DB_ERR_EN__SHIFT 0x3 |
7764 | #define UVD_MEMCHECK_VCPU_INT_EN__DBW_ERR_EN__SHIFT 0x4 |
7765 | #define UVD_MEMCHECK_VCPU_INT_EN__CM_ERR_EN__SHIFT 0x5 |
7766 | #define UVD_MEMCHECK_VCPU_INT_EN__MIF_REF_ERR_EN__SHIFT 0x6 |
7767 | #define UVD_MEMCHECK_VCPU_INT_EN__MIF_DBW_ERR_EN__SHIFT 0x8 |
7768 | #define UVD_MEMCHECK_VCPU_INT_EN__MIF_CM_COLOC_ERR_EN__SHIFT 0x9 |
7769 | #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP0_ERR_EN__SHIFT 0xa |
7770 | #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP1_ERR_EN__SHIFT 0xb |
7771 | #define UVD_MEMCHECK_VCPU_INT_EN__SRE_ERR_EN__SHIFT 0xc |
7772 | #define UVD_MEMCHECK_VCPU_INT_EN__IT_RD_ERR_EN__SHIFT 0xf |
7773 | #define UVD_MEMCHECK_VCPU_INT_EN__CM_RD_ERR_EN__SHIFT 0x10 |
7774 | #define UVD_MEMCHECK_VCPU_INT_EN__DB_RD_ERR_EN__SHIFT 0x11 |
7775 | #define UVD_MEMCHECK_VCPU_INT_EN__MIF_RD_ERR_EN__SHIFT 0x12 |
7776 | #define UVD_MEMCHECK_VCPU_INT_EN__IDCT_RD_ERR_EN__SHIFT 0x13 |
7777 | #define UVD_MEMCHECK_VCPU_INT_EN__MPC_RD_ERR_EN__SHIFT 0x14 |
7778 | #define UVD_MEMCHECK_VCPU_INT_EN__LBSI_RD_ERR_EN__SHIFT 0x15 |
7779 | #define UVD_MEMCHECK_VCPU_INT_EN__RBC_RD_ERR_EN__SHIFT 0x18 |
7780 | #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP2_ERR_EN__SHIFT 0x19 |
7781 | #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP3_ERR_EN__SHIFT 0x1a |
7782 | #define UVD_MEMCHECK_VCPU_INT_EN__MIF_SCLR_ERR_EN__SHIFT 0x1b |
7783 | #define UVD_MEMCHECK_VCPU_INT_EN__MIF_SCLR2_ERR_EN__SHIFT 0x1c |
7784 | #define UVD_MEMCHECK_VCPU_INT_EN__PREF_ERR_EN__SHIFT 0x1d |
7785 | #define UVD_MEMCHECK_VCPU_INT_EN__RE_ERR_EN_MASK 0x00000001L |
7786 | #define UVD_MEMCHECK_VCPU_INT_EN__IT_ERR_EN_MASK 0x00000002L |
7787 | #define UVD_MEMCHECK_VCPU_INT_EN__MP_ERR_EN_MASK 0x00000004L |
7788 | #define UVD_MEMCHECK_VCPU_INT_EN__DB_ERR_EN_MASK 0x00000008L |
7789 | #define UVD_MEMCHECK_VCPU_INT_EN__DBW_ERR_EN_MASK 0x00000010L |
7790 | #define UVD_MEMCHECK_VCPU_INT_EN__CM_ERR_EN_MASK 0x00000020L |
7791 | #define UVD_MEMCHECK_VCPU_INT_EN__MIF_REF_ERR_EN_MASK 0x00000040L |
7792 | #define UVD_MEMCHECK_VCPU_INT_EN__MIF_DBW_ERR_EN_MASK 0x00000100L |
7793 | #define UVD_MEMCHECK_VCPU_INT_EN__MIF_CM_COLOC_ERR_EN_MASK 0x00000200L |
7794 | #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP0_ERR_EN_MASK 0x00000400L |
7795 | #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP1_ERR_EN_MASK 0x00000800L |
7796 | #define UVD_MEMCHECK_VCPU_INT_EN__SRE_ERR_EN_MASK 0x00001000L |
7797 | #define UVD_MEMCHECK_VCPU_INT_EN__IT_RD_ERR_EN_MASK 0x00008000L |
7798 | #define UVD_MEMCHECK_VCPU_INT_EN__CM_RD_ERR_EN_MASK 0x00010000L |
7799 | #define UVD_MEMCHECK_VCPU_INT_EN__DB_RD_ERR_EN_MASK 0x00020000L |
7800 | #define UVD_MEMCHECK_VCPU_INT_EN__MIF_RD_ERR_EN_MASK 0x00040000L |
7801 | #define UVD_MEMCHECK_VCPU_INT_EN__IDCT_RD_ERR_EN_MASK 0x00080000L |
7802 | #define UVD_MEMCHECK_VCPU_INT_EN__MPC_RD_ERR_EN_MASK 0x00100000L |
7803 | #define UVD_MEMCHECK_VCPU_INT_EN__LBSI_RD_ERR_EN_MASK 0x00200000L |
7804 | #define UVD_MEMCHECK_VCPU_INT_EN__RBC_RD_ERR_EN_MASK 0x01000000L |
7805 | #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP2_ERR_EN_MASK 0x02000000L |
7806 | #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP3_ERR_EN_MASK 0x04000000L |
7807 | #define UVD_MEMCHECK_VCPU_INT_EN__MIF_SCLR_ERR_EN_MASK 0x08000000L |
7808 | #define UVD_MEMCHECK_VCPU_INT_EN__MIF_SCLR2_ERR_EN_MASK 0x10000000L |
7809 | #define UVD_MEMCHECK_VCPU_INT_EN__PREF_ERR_EN_MASK 0x20000000L |
7810 | //UVD_MEMCHECK_VCPU_INT_STAT |
7811 | #define UVD_MEMCHECK_VCPU_INT_STAT__RE_LO_ERR__SHIFT 0x0 |
7812 | #define UVD_MEMCHECK_VCPU_INT_STAT__RE_HI_ERR__SHIFT 0x1 |
7813 | #define UVD_MEMCHECK_VCPU_INT_STAT__IT_LO_ERR__SHIFT 0x2 |
7814 | #define UVD_MEMCHECK_VCPU_INT_STAT__IT_HI_ERR__SHIFT 0x3 |
7815 | #define UVD_MEMCHECK_VCPU_INT_STAT__MP_LO_ERR__SHIFT 0x4 |
7816 | #define UVD_MEMCHECK_VCPU_INT_STAT__MP_HI_ERR__SHIFT 0x5 |
7817 | #define UVD_MEMCHECK_VCPU_INT_STAT__DB_LO_ERR__SHIFT 0x6 |
7818 | #define UVD_MEMCHECK_VCPU_INT_STAT__DB_HI_ERR__SHIFT 0x7 |
7819 | #define UVD_MEMCHECK_VCPU_INT_STAT__DBW_LO_ERR__SHIFT 0x8 |
7820 | #define UVD_MEMCHECK_VCPU_INT_STAT__DBW_HI_ERR__SHIFT 0x9 |
7821 | #define UVD_MEMCHECK_VCPU_INT_STAT__CM_LO_ERR__SHIFT 0xa |
7822 | #define UVD_MEMCHECK_VCPU_INT_STAT__CM_HI_ERR__SHIFT 0xb |
7823 | #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_REF_LO_ERR__SHIFT 0xc |
7824 | #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_REF_HI_ERR__SHIFT 0xd |
7825 | #define UVD_MEMCHECK_VCPU_INT_STAT__VCPU_LO_ERR__SHIFT 0xe |
7826 | #define UVD_MEMCHECK_VCPU_INT_STAT__VCPU_HI_ERR__SHIFT 0xf |
7827 | #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_DBW_LO_ERR__SHIFT 0x10 |
7828 | #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_DBW_HI_ERR__SHIFT 0x11 |
7829 | #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_CM_COLOC_LO_ERR__SHIFT 0x12 |
7830 | #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_CM_COLOC_HI_ERR__SHIFT 0x13 |
7831 | #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP0_LO_ERR__SHIFT 0x14 |
7832 | #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP0_HI_ERR__SHIFT 0x15 |
7833 | #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP1_LO_ERR__SHIFT 0x16 |
7834 | #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP1_HI_ERR__SHIFT 0x17 |
7835 | #define UVD_MEMCHECK_VCPU_INT_STAT__SRE_LO_ERR__SHIFT 0x18 |
7836 | #define UVD_MEMCHECK_VCPU_INT_STAT__SRE_HI_ERR__SHIFT 0x19 |
7837 | #define UVD_MEMCHECK_VCPU_INT_STAT__IT_RD_LO_ERR__SHIFT 0x1e |
7838 | #define UVD_MEMCHECK_VCPU_INT_STAT__IT_RD_HI_ERR__SHIFT 0x1f |
7839 | #define UVD_MEMCHECK_VCPU_INT_STAT__RE_LO_ERR_MASK 0x00000001L |
7840 | #define UVD_MEMCHECK_VCPU_INT_STAT__RE_HI_ERR_MASK 0x00000002L |
7841 | #define UVD_MEMCHECK_VCPU_INT_STAT__IT_LO_ERR_MASK 0x00000004L |
7842 | #define UVD_MEMCHECK_VCPU_INT_STAT__IT_HI_ERR_MASK 0x00000008L |
7843 | #define UVD_MEMCHECK_VCPU_INT_STAT__MP_LO_ERR_MASK 0x00000010L |
7844 | #define UVD_MEMCHECK_VCPU_INT_STAT__MP_HI_ERR_MASK 0x00000020L |
7845 | #define UVD_MEMCHECK_VCPU_INT_STAT__DB_LO_ERR_MASK 0x00000040L |
7846 | #define UVD_MEMCHECK_VCPU_INT_STAT__DB_HI_ERR_MASK 0x00000080L |
7847 | #define UVD_MEMCHECK_VCPU_INT_STAT__DBW_LO_ERR_MASK 0x00000100L |
7848 | #define UVD_MEMCHECK_VCPU_INT_STAT__DBW_HI_ERR_MASK 0x00000200L |
7849 | #define UVD_MEMCHECK_VCPU_INT_STAT__CM_LO_ERR_MASK 0x00000400L |
7850 | #define UVD_MEMCHECK_VCPU_INT_STAT__CM_HI_ERR_MASK 0x00000800L |
7851 | #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_REF_LO_ERR_MASK 0x00001000L |
7852 | #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_REF_HI_ERR_MASK 0x00002000L |
7853 | #define UVD_MEMCHECK_VCPU_INT_STAT__VCPU_LO_ERR_MASK 0x00004000L |
7854 | #define UVD_MEMCHECK_VCPU_INT_STAT__VCPU_HI_ERR_MASK 0x00008000L |
7855 | #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_DBW_LO_ERR_MASK 0x00010000L |
7856 | #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_DBW_HI_ERR_MASK 0x00020000L |
7857 | #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_CM_COLOC_LO_ERR_MASK 0x00040000L |
7858 | #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_CM_COLOC_HI_ERR_MASK 0x00080000L |
7859 | #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP0_LO_ERR_MASK 0x00100000L |
7860 | #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP0_HI_ERR_MASK 0x00200000L |
7861 | #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP1_LO_ERR_MASK 0x00400000L |
7862 | #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP1_HI_ERR_MASK 0x00800000L |
7863 | #define UVD_MEMCHECK_VCPU_INT_STAT__SRE_LO_ERR_MASK 0x01000000L |
7864 | #define UVD_MEMCHECK_VCPU_INT_STAT__SRE_HI_ERR_MASK 0x02000000L |
7865 | #define UVD_MEMCHECK_VCPU_INT_STAT__IT_RD_LO_ERR_MASK 0x40000000L |
7866 | #define UVD_MEMCHECK_VCPU_INT_STAT__IT_RD_HI_ERR_MASK 0x80000000L |
7867 | //UVD_MEMCHECK_VCPU_INT_ACK |
7868 | #define UVD_MEMCHECK_VCPU_INT_ACK__RE_LO_ACK__SHIFT 0x0 |
7869 | #define UVD_MEMCHECK_VCPU_INT_ACK__RE_HI_ACK__SHIFT 0x1 |
7870 | #define UVD_MEMCHECK_VCPU_INT_ACK__IT_LO_ACK__SHIFT 0x2 |
7871 | #define UVD_MEMCHECK_VCPU_INT_ACK__IT_HI_ACK__SHIFT 0x3 |
7872 | #define UVD_MEMCHECK_VCPU_INT_ACK__MP_LO_ACK__SHIFT 0x4 |
7873 | #define UVD_MEMCHECK_VCPU_INT_ACK__MP_HI_ACK__SHIFT 0x5 |
7874 | #define UVD_MEMCHECK_VCPU_INT_ACK__DB_LO_ACK__SHIFT 0x6 |
7875 | #define UVD_MEMCHECK_VCPU_INT_ACK__DB_HI_ACK__SHIFT 0x7 |
7876 | #define UVD_MEMCHECK_VCPU_INT_ACK__DBW_LO_ACK__SHIFT 0x8 |
7877 | #define UVD_MEMCHECK_VCPU_INT_ACK__DBW_HI_ACK__SHIFT 0x9 |
7878 | #define UVD_MEMCHECK_VCPU_INT_ACK__CM_LO_ACK__SHIFT 0xa |
7879 | #define UVD_MEMCHECK_VCPU_INT_ACK__CM_HI_ACK__SHIFT 0xb |
7880 | #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_REF_LO_ACK__SHIFT 0xc |
7881 | #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_REF_HI_ACK__SHIFT 0xd |
7882 | #define UVD_MEMCHECK_VCPU_INT_ACK__VCPU_LO_ACK__SHIFT 0xe |
7883 | #define UVD_MEMCHECK_VCPU_INT_ACK__VCPU_HI_ACK__SHIFT 0xf |
7884 | #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_DBW_LO_ACK__SHIFT 0x10 |
7885 | #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_DBW_HI_ACK__SHIFT 0x11 |
7886 | #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_CM_COLOC_LO_ACK__SHIFT 0x12 |
7887 | #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_CM_COLOC_HI_ACK__SHIFT 0x13 |
7888 | #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP0_LO_ACK__SHIFT 0x14 |
7889 | #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP0_HI_ACK__SHIFT 0x15 |
7890 | #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP1_LO_ACK__SHIFT 0x16 |
7891 | #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP1_HI_ACK__SHIFT 0x17 |
7892 | #define UVD_MEMCHECK_VCPU_INT_ACK__SRE_LO_ACK__SHIFT 0x18 |
7893 | #define UVD_MEMCHECK_VCPU_INT_ACK__SRE_HI_ACK__SHIFT 0x19 |
7894 | #define UVD_MEMCHECK_VCPU_INT_ACK__IT_RD_LO_ACK__SHIFT 0x1e |
7895 | #define UVD_MEMCHECK_VCPU_INT_ACK__IT_RD_HI_ACK__SHIFT 0x1f |
7896 | #define UVD_MEMCHECK_VCPU_INT_ACK__RE_LO_ACK_MASK 0x00000001L |
7897 | #define UVD_MEMCHECK_VCPU_INT_ACK__RE_HI_ACK_MASK 0x00000002L |
7898 | #define UVD_MEMCHECK_VCPU_INT_ACK__IT_LO_ACK_MASK 0x00000004L |
7899 | #define UVD_MEMCHECK_VCPU_INT_ACK__IT_HI_ACK_MASK 0x00000008L |
7900 | #define UVD_MEMCHECK_VCPU_INT_ACK__MP_LO_ACK_MASK 0x00000010L |
7901 | #define UVD_MEMCHECK_VCPU_INT_ACK__MP_HI_ACK_MASK 0x00000020L |
7902 | #define UVD_MEMCHECK_VCPU_INT_ACK__DB_LO_ACK_MASK 0x00000040L |
7903 | #define UVD_MEMCHECK_VCPU_INT_ACK__DB_HI_ACK_MASK 0x00000080L |
7904 | #define UVD_MEMCHECK_VCPU_INT_ACK__DBW_LO_ACK_MASK 0x00000100L |
7905 | #define UVD_MEMCHECK_VCPU_INT_ACK__DBW_HI_ACK_MASK 0x00000200L |
7906 | #define UVD_MEMCHECK_VCPU_INT_ACK__CM_LO_ACK_MASK 0x00000400L |
7907 | #define UVD_MEMCHECK_VCPU_INT_ACK__CM_HI_ACK_MASK 0x00000800L |
7908 | #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_REF_LO_ACK_MASK 0x00001000L |
7909 | #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_REF_HI_ACK_MASK 0x00002000L |
7910 | #define UVD_MEMCHECK_VCPU_INT_ACK__VCPU_LO_ACK_MASK 0x00004000L |
7911 | #define UVD_MEMCHECK_VCPU_INT_ACK__VCPU_HI_ACK_MASK 0x00008000L |
7912 | #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_DBW_LO_ACK_MASK 0x00010000L |
7913 | #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_DBW_HI_ACK_MASK 0x00020000L |
7914 | #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_CM_COLOC_LO_ACK_MASK 0x00040000L |
7915 | #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_CM_COLOC_HI_ACK_MASK 0x00080000L |
7916 | #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP0_LO_ACK_MASK 0x00100000L |
7917 | #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP0_HI_ACK_MASK 0x00200000L |
7918 | #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP1_LO_ACK_MASK 0x00400000L |
7919 | #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP1_HI_ACK_MASK 0x00800000L |
7920 | #define UVD_MEMCHECK_VCPU_INT_ACK__SRE_LO_ACK_MASK 0x01000000L |
7921 | #define UVD_MEMCHECK_VCPU_INT_ACK__SRE_HI_ACK_MASK 0x02000000L |
7922 | #define UVD_MEMCHECK_VCPU_INT_ACK__IT_RD_LO_ACK_MASK 0x40000000L |
7923 | #define UVD_MEMCHECK_VCPU_INT_ACK__IT_RD_HI_ACK_MASK 0x80000000L |
7924 | //UVD_MEMCHECK2_SYS_INT_STAT |
7925 | #define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_LO_ERR__SHIFT 0x0 |
7926 | #define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_HI_ERR__SHIFT 0x1 |
7927 | #define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_LO_ERR__SHIFT 0x2 |
7928 | #define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_HI_ERR__SHIFT 0x3 |
7929 | #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_LO_ERR__SHIFT 0x4 |
7930 | #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_HI_ERR__SHIFT 0x5 |
7931 | #define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_LO_ERR__SHIFT 0x6 |
7932 | #define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_HI_ERR__SHIFT 0x7 |
7933 | #define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_LO_ERR__SHIFT 0x8 |
7934 | #define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_HI_ERR__SHIFT 0x9 |
7935 | #define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_LO_ERR__SHIFT 0xa |
7936 | #define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_HI_ERR__SHIFT 0xb |
7937 | #define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_LO_ERR__SHIFT 0x10 |
7938 | #define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_HI_ERR__SHIFT 0x11 |
7939 | #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_LO_ERR__SHIFT 0x16 |
7940 | #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_HI_ERR__SHIFT 0x17 |
7941 | #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_LO_ERR__SHIFT 0x18 |
7942 | #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_HI_ERR__SHIFT 0x19 |
7943 | #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_LO_ERR__SHIFT 0x1a |
7944 | #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_HI_ERR__SHIFT 0x1b |
7945 | #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_LO_ERR__SHIFT 0x1c |
7946 | #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_HI_ERR__SHIFT 0x1d |
7947 | #define UVD_MEMCHECK2_SYS_INT_STAT__PREF_LO_ERR__SHIFT 0x1e |
7948 | #define UVD_MEMCHECK2_SYS_INT_STAT__PREF_HI_ERR__SHIFT 0x1f |
7949 | #define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_LO_ERR_MASK 0x00000001L |
7950 | #define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_HI_ERR_MASK 0x00000002L |
7951 | #define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_LO_ERR_MASK 0x00000004L |
7952 | #define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_HI_ERR_MASK 0x00000008L |
7953 | #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_LO_ERR_MASK 0x00000010L |
7954 | #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_HI_ERR_MASK 0x00000020L |
7955 | #define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_LO_ERR_MASK 0x00000040L |
7956 | #define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_HI_ERR_MASK 0x00000080L |
7957 | #define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_LO_ERR_MASK 0x00000100L |
7958 | #define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_HI_ERR_MASK 0x00000200L |
7959 | #define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_LO_ERR_MASK 0x00000400L |
7960 | #define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_HI_ERR_MASK 0x00000800L |
7961 | #define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_LO_ERR_MASK 0x00010000L |
7962 | #define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_HI_ERR_MASK 0x00020000L |
7963 | #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_LO_ERR_MASK 0x00400000L |
7964 | #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_HI_ERR_MASK 0x00800000L |
7965 | #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_LO_ERR_MASK 0x01000000L |
7966 | #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_HI_ERR_MASK 0x02000000L |
7967 | #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_LO_ERR_MASK 0x04000000L |
7968 | #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_HI_ERR_MASK 0x08000000L |
7969 | #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_LO_ERR_MASK 0x10000000L |
7970 | #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_HI_ERR_MASK 0x20000000L |
7971 | #define UVD_MEMCHECK2_SYS_INT_STAT__PREF_LO_ERR_MASK 0x40000000L |
7972 | #define UVD_MEMCHECK2_SYS_INT_STAT__PREF_HI_ERR_MASK 0x80000000L |
7973 | //UVD_MEMCHECK2_SYS_INT_ACK |
7974 | #define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_LO_ACK__SHIFT 0x0 |
7975 | #define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_HI_ACK__SHIFT 0x1 |
7976 | #define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_LO_ACK__SHIFT 0x2 |
7977 | #define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_HI_ACK__SHIFT 0x3 |
7978 | #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_LO_ACK__SHIFT 0x4 |
7979 | #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_HI_ACK__SHIFT 0x5 |
7980 | #define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_LO_ACK__SHIFT 0x6 |
7981 | #define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_HI_ACK__SHIFT 0x7 |
7982 | #define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_LO_ACK__SHIFT 0x8 |
7983 | #define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_HI_ACK__SHIFT 0x9 |
7984 | #define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_LO_ACK__SHIFT 0xa |
7985 | #define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_HI_ACK__SHIFT 0xb |
7986 | #define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_LO_ACK__SHIFT 0x10 |
7987 | #define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_HI_ACK__SHIFT 0x11 |
7988 | #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_LO_ACK__SHIFT 0x16 |
7989 | #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_HI_ACK__SHIFT 0x17 |
7990 | #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_LO_ACK__SHIFT 0x18 |
7991 | #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_HI_ACK__SHIFT 0x19 |
7992 | #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_LO_ACK__SHIFT 0x1a |
7993 | #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_HI_ACK__SHIFT 0x1b |
7994 | #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_LO_ACK__SHIFT 0x1c |
7995 | #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_HI_ACK__SHIFT 0x1d |
7996 | #define UVD_MEMCHECK2_SYS_INT_ACK__PREF_LO_ACK__SHIFT 0x1e |
7997 | #define UVD_MEMCHECK2_SYS_INT_ACK__PREF_HI_ACK__SHIFT 0x1f |
7998 | #define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_LO_ACK_MASK 0x00000001L |
7999 | #define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_HI_ACK_MASK 0x00000002L |
8000 | #define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_LO_ACK_MASK 0x00000004L |
8001 | #define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_HI_ACK_MASK 0x00000008L |
8002 | #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_LO_ACK_MASK 0x00000010L |
8003 | #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_HI_ACK_MASK 0x00000020L |
8004 | #define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_LO_ACK_MASK 0x00000040L |
8005 | #define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_HI_ACK_MASK 0x00000080L |
8006 | #define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_LO_ACK_MASK 0x00000100L |
8007 | #define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_HI_ACK_MASK 0x00000200L |
8008 | #define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_LO_ACK_MASK 0x00000400L |
8009 | #define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_HI_ACK_MASK 0x00000800L |
8010 | #define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_LO_ACK_MASK 0x00010000L |
8011 | #define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_HI_ACK_MASK 0x00020000L |
8012 | #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_LO_ACK_MASK 0x00400000L |
8013 | #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_HI_ACK_MASK 0x00800000L |
8014 | #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_LO_ACK_MASK 0x01000000L |
8015 | #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_HI_ACK_MASK 0x02000000L |
8016 | #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_LO_ACK_MASK 0x04000000L |
8017 | #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_HI_ACK_MASK 0x08000000L |
8018 | #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_LO_ACK_MASK 0x10000000L |
8019 | #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_HI_ACK_MASK 0x20000000L |
8020 | #define UVD_MEMCHECK2_SYS_INT_ACK__PREF_LO_ACK_MASK 0x40000000L |
8021 | #define UVD_MEMCHECK2_SYS_INT_ACK__PREF_HI_ACK_MASK 0x80000000L |
8022 | //UVD_MEMCHECK2_VCPU_INT_STAT |
8023 | #define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_LO_ERR__SHIFT 0x0 |
8024 | #define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_HI_ERR__SHIFT 0x1 |
8025 | #define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_LO_ERR__SHIFT 0x2 |
8026 | #define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_HI_ERR__SHIFT 0x3 |
8027 | #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_LO_ERR__SHIFT 0x4 |
8028 | #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_HI_ERR__SHIFT 0x5 |
8029 | #define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_LO_ERR__SHIFT 0x6 |
8030 | #define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_HI_ERR__SHIFT 0x7 |
8031 | #define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_LO_ERR__SHIFT 0x8 |
8032 | #define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_HI_ERR__SHIFT 0x9 |
8033 | #define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_LO_ERR__SHIFT 0xa |
8034 | #define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_HI_ERR__SHIFT 0xb |
8035 | #define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_LO_ERR__SHIFT 0x10 |
8036 | #define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_HI_ERR__SHIFT 0x11 |
8037 | #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_LO_ERR__SHIFT 0x12 |
8038 | #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_HI_ERR__SHIFT 0x13 |
8039 | #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_LO_ERR__SHIFT 0x14 |
8040 | #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_HI_ERR__SHIFT 0x15 |
8041 | #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_LO_ERR__SHIFT 0x16 |
8042 | #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_HI_ERR__SHIFT 0x17 |
8043 | #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_LO_ERR__SHIFT 0x18 |
8044 | #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_HI_ERR__SHIFT 0x19 |
8045 | #define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_LO_ERR__SHIFT 0x1a |
8046 | #define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_HI_ERR__SHIFT 0x1b |
8047 | #define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_LO_ERR_MASK 0x00000001L |
8048 | #define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_HI_ERR_MASK 0x00000002L |
8049 | #define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_LO_ERR_MASK 0x00000004L |
8050 | #define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_HI_ERR_MASK 0x00000008L |
8051 | #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_LO_ERR_MASK 0x00000010L |
8052 | #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_HI_ERR_MASK 0x00000020L |
8053 | #define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_LO_ERR_MASK 0x00000040L |
8054 | #define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_HI_ERR_MASK 0x00000080L |
8055 | #define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_LO_ERR_MASK 0x00000100L |
8056 | #define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_HI_ERR_MASK 0x00000200L |
8057 | #define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_LO_ERR_MASK 0x00000400L |
8058 | #define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_HI_ERR_MASK 0x00000800L |
8059 | #define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_LO_ERR_MASK 0x00010000L |
8060 | #define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_HI_ERR_MASK 0x00020000L |
8061 | #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_LO_ERR_MASK 0x00040000L |
8062 | #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_HI_ERR_MASK 0x00080000L |
8063 | #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_LO_ERR_MASK 0x00100000L |
8064 | #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_HI_ERR_MASK 0x00200000L |
8065 | #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_LO_ERR_MASK 0x00400000L |
8066 | #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_HI_ERR_MASK 0x00800000L |
8067 | #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_LO_ERR_MASK 0x01000000L |
8068 | #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_HI_ERR_MASK 0x02000000L |
8069 | #define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_LO_ERR_MASK 0x04000000L |
8070 | #define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_HI_ERR_MASK 0x08000000L |
8071 | //UVD_MEMCHECK2_VCPU_INT_ACK |
8072 | #define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_LO_ACK__SHIFT 0x0 |
8073 | #define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_HI_ACK__SHIFT 0x1 |
8074 | #define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_LO_ACK__SHIFT 0x2 |
8075 | #define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_HI_ACK__SHIFT 0x3 |
8076 | #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_LO_ACK__SHIFT 0x4 |
8077 | #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_HI_ACK__SHIFT 0x5 |
8078 | #define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_LO_ACK__SHIFT 0x6 |
8079 | #define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_HI_ACK__SHIFT 0x7 |
8080 | #define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_LO_ACK__SHIFT 0x8 |
8081 | #define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_HI_ACK__SHIFT 0x9 |
8082 | #define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_LO_ACK__SHIFT 0xa |
8083 | #define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_HI_ACK__SHIFT 0xb |
8084 | #define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_LO_ACK__SHIFT 0x10 |
8085 | #define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_HI_ACK__SHIFT 0x11 |
8086 | #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_LO_ACK__SHIFT 0x12 |
8087 | #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_HI_ACK__SHIFT 0x13 |
8088 | #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_LO_ACK__SHIFT 0x14 |
8089 | #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_HI_ACK__SHIFT 0x15 |
8090 | #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_LO_ACK__SHIFT 0x16 |
8091 | #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_HI_ACK__SHIFT 0x17 |
8092 | #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_LO_ACK__SHIFT 0x18 |
8093 | #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_HI_ACK__SHIFT 0x19 |
8094 | #define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_LO_ACK__SHIFT 0x1a |
8095 | #define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_HI_ACK__SHIFT 0x1b |
8096 | #define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_LO_ACK_MASK 0x00000001L |
8097 | #define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_HI_ACK_MASK 0x00000002L |
8098 | #define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_LO_ACK_MASK 0x00000004L |
8099 | #define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_HI_ACK_MASK 0x00000008L |
8100 | #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_LO_ACK_MASK 0x00000010L |
8101 | #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_HI_ACK_MASK 0x00000020L |
8102 | #define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_LO_ACK_MASK 0x00000040L |
8103 | #define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_HI_ACK_MASK 0x00000080L |
8104 | #define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_LO_ACK_MASK 0x00000100L |
8105 | #define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_HI_ACK_MASK 0x00000200L |
8106 | #define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_LO_ACK_MASK 0x00000400L |
8107 | #define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_HI_ACK_MASK 0x00000800L |
8108 | #define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_LO_ACK_MASK 0x00010000L |
8109 | #define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_HI_ACK_MASK 0x00020000L |
8110 | #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_LO_ACK_MASK 0x00040000L |
8111 | #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_HI_ACK_MASK 0x00080000L |
8112 | #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_LO_ACK_MASK 0x00100000L |
8113 | #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_HI_ACK_MASK 0x00200000L |
8114 | #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_LO_ACK_MASK 0x00400000L |
8115 | #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_HI_ACK_MASK 0x00800000L |
8116 | #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_LO_ACK_MASK 0x01000000L |
8117 | #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_HI_ACK_MASK 0x02000000L |
8118 | #define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_LO_ACK_MASK 0x04000000L |
8119 | #define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_HI_ACK_MASK 0x08000000L |
8120 | |
8121 | //VCN_UMSCH_MES_UTCL1_CNTL |
8122 | #define VCN_UMSCH_MES_UTCL1_CNTL__REDO_LATENCY__SHIFT 0x0 |
8123 | #define VCN_UMSCH_MES_UTCL1_CNTL__ForceSnoop__SHIFT 0x14 |
8124 | #define VCN_UMSCH_MES_UTCL1_CNTL__FragLimitMode__SHIFT 0x15 |
8125 | #define VCN_UMSCH_MES_UTCL1_CNTL__DropMode__SHIFT 0x16 |
8126 | #define VCN_UMSCH_MES_UTCL1_CNTL__Invalidate__SHIFT 0x17 |
8127 | #define VCN_UMSCH_MES_UTCL1_CNTL__REDO_LATENCY_MASK 0x000FFFFFL |
8128 | #define VCN_UMSCH_MES_UTCL1_CNTL__ForceSnoop_MASK 0x00100000L |
8129 | #define VCN_UMSCH_MES_UTCL1_CNTL__FragLimitMode_MASK 0x00200000L |
8130 | #define VCN_UMSCH_MES_UTCL1_CNTL__DropMode_MASK 0x00400000L |
8131 | #define VCN_UMSCH_MES_UTCL1_CNTL__Invalidate_MASK 0x00800000L |
8132 | //VCN_UMSCH_MES_BUSY |
8133 | #define VCN_UMSCH_MES_BUSY__MesScratchRamBusy__SHIFT 0x0 |
8134 | #define VCN_UMSCH_MES_BUSY__MesInstrCacheBusy__SHIFT 0x1 |
8135 | #define VCN_UMSCH_MES_BUSY__MesDataCacheBusy__SHIFT 0x2 |
8136 | #define VCN_UMSCH_MES_BUSY__MesBusy__SHIFT 0x3 |
8137 | #define VCN_UMSCH_MES_BUSY__MesLoadBusy__SHIFT 0x4 |
8138 | #define VCN_UMSCH_MES_BUSY__MesMutexBusy__SHIFT 0x5 |
8139 | #define VCN_UMSCH_MES_BUSY__MesThreadBusy__SHIFT 0x6 |
8140 | #define VCN_UMSCH_MES_BUSY__MesMessageBusy__SHIFT 0x8 |
8141 | #define VCN_UMSCH_MES_BUSY__MesTcBusy__SHIFT 0xa |
8142 | #define VCN_UMSCH_MES_BUSY__MesDmaPending__SHIFT 0xc |
8143 | #define VCN_UMSCH_MES_BUSY__MesScratchRamBusy_MASK 0x00000001L |
8144 | #define VCN_UMSCH_MES_BUSY__MesInstrCacheBusy_MASK 0x00000002L |
8145 | #define VCN_UMSCH_MES_BUSY__MesDataCacheBusy_MASK 0x00000004L |
8146 | #define VCN_UMSCH_MES_BUSY__MesBusy_MASK 0x00000008L |
8147 | #define VCN_UMSCH_MES_BUSY__MesLoadBusy_MASK 0x00000010L |
8148 | #define VCN_UMSCH_MES_BUSY__MesMutexBusy_MASK 0x00000020L |
8149 | #define VCN_UMSCH_MES_BUSY__MesThreadBusy_MASK 0x000000C0L |
8150 | #define VCN_UMSCH_MES_BUSY__MesMessageBusy_MASK 0x00000300L |
8151 | #define VCN_UMSCH_MES_BUSY__MesTcBusy_MASK 0x00000C00L |
8152 | #define VCN_UMSCH_MES_BUSY__MesDmaPending_MASK 0x00003000L |
8153 | //VCN_UMSCH_RB_BASE_LO |
8154 | #define VCN_UMSCH_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 |
8155 | #define VCN_UMSCH_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L |
8156 | //VCN_UMSCH_RB_BASE_HI |
8157 | #define VCN_UMSCH_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 |
8158 | #define VCN_UMSCH_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL |
8159 | //VCN_UMSCH_RB_SIZE |
8160 | #define VCN_UMSCH_RB_SIZE__WPTR__SHIFT 0x4 |
8161 | #define VCN_UMSCH_RB_SIZE__WPTR_MASK 0x007FFFF0L |
8162 | //VCN_UMSCH_RB_RPTR |
8163 | #define VCN_UMSCH_RB_RPTR__WPTR__SHIFT 0x4 |
8164 | #define VCN_UMSCH_RB_RPTR__WPTR_MASK 0x007FFFF0L |
8165 | //VCN_UMSCH_RB_WPTR |
8166 | #define VCN_UMSCH_RB_WPTR__WPTR__SHIFT 0x4 |
8167 | #define VCN_UMSCH_RB_WPTR__WPTR_MASK 0x007FFFF0L |
8168 | //VCN_UMSCH_MASTINT_EN |
8169 | #define VCN_UMSCH_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 |
8170 | #define VCN_UMSCH_MASTINT_EN__SYS_EN__SHIFT 0x2 |
8171 | #define VCN_UMSCH_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 |
8172 | #define VCN_UMSCH_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L |
8173 | #define VCN_UMSCH_MASTINT_EN__SYS_EN_MASK 0x00000004L |
8174 | #define VCN_UMSCH_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L |
8175 | //VCN_UMSCH_IH_CTRL |
8176 | #define VCN_UMSCH_IH_CTRL__IH_SOFT_RESET__SHIFT 0x0 |
8177 | #define VCN_UMSCH_IH_CTRL__IH_STALL_EN__SHIFT 0x1 |
8178 | #define VCN_UMSCH_IH_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 |
8179 | #define VCN_UMSCH_IH_CTRL__IH_VMID__SHIFT 0x3 |
8180 | #define VCN_UMSCH_IH_CTRL__IH_USER_DATA__SHIFT 0x7 |
8181 | #define VCN_UMSCH_IH_CTRL__IH_RINGID__SHIFT 0x13 |
8182 | #define VCN_UMSCH_IH_CTRL__IH_SOFT_RESET_MASK 0x00000001L |
8183 | #define VCN_UMSCH_IH_CTRL__IH_STALL_EN_MASK 0x00000002L |
8184 | #define VCN_UMSCH_IH_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L |
8185 | #define VCN_UMSCH_IH_CTRL__IH_VMID_MASK 0x00000078L |
8186 | #define VCN_UMSCH_IH_CTRL__IH_USER_DATA_MASK 0x0007FF80L |
8187 | #define VCN_UMSCH_IH_CTRL__IH_RINGID_MASK 0x07F80000L |
8188 | //VCN_UMSCH_SYS_INT_EN |
8189 | #define VCN_UMSCH_SYS_INT_EN__INT0__SHIFT 0x0 |
8190 | #define VCN_UMSCH_SYS_INT_EN__INT1__SHIFT 0x1 |
8191 | #define VCN_UMSCH_SYS_INT_EN__INT2__SHIFT 0x2 |
8192 | #define VCN_UMSCH_SYS_INT_EN__INT3__SHIFT 0x3 |
8193 | #define VCN_UMSCH_SYS_INT_EN__INT4__SHIFT 0x4 |
8194 | #define VCN_UMSCH_SYS_INT_EN__INT5__SHIFT 0x5 |
8195 | #define VCN_UMSCH_SYS_INT_EN__INT6__SHIFT 0x6 |
8196 | #define VCN_UMSCH_SYS_INT_EN__INT7__SHIFT 0x7 |
8197 | #define VCN_UMSCH_SYS_INT_EN__INT0_MASK 0x00000001L |
8198 | #define VCN_UMSCH_SYS_INT_EN__INT1_MASK 0x00000002L |
8199 | #define VCN_UMSCH_SYS_INT_EN__INT2_MASK 0x00000004L |
8200 | #define VCN_UMSCH_SYS_INT_EN__INT3_MASK 0x00000008L |
8201 | #define VCN_UMSCH_SYS_INT_EN__INT4_MASK 0x00000010L |
8202 | #define VCN_UMSCH_SYS_INT_EN__INT5_MASK 0x00000020L |
8203 | #define VCN_UMSCH_SYS_INT_EN__INT6_MASK 0x00000040L |
8204 | #define VCN_UMSCH_SYS_INT_EN__INT7_MASK 0x00000080L |
8205 | //VCN_UMSCH_SYS_INT_STATUS |
8206 | #define VCN_UMSCH_SYS_INT_STATUS__INT0__SHIFT 0x0 |
8207 | #define VCN_UMSCH_SYS_INT_STATUS__INT1__SHIFT 0x1 |
8208 | #define VCN_UMSCH_SYS_INT_STATUS__INT2__SHIFT 0x2 |
8209 | #define VCN_UMSCH_SYS_INT_STATUS__INT3__SHIFT 0x3 |
8210 | #define VCN_UMSCH_SYS_INT_STATUS__INT4__SHIFT 0x4 |
8211 | #define VCN_UMSCH_SYS_INT_STATUS__INT5__SHIFT 0x5 |
8212 | #define VCN_UMSCH_SYS_INT_STATUS__INT6__SHIFT 0x6 |
8213 | #define VCN_UMSCH_SYS_INT_STATUS__INT7__SHIFT 0x7 |
8214 | #define VCN_UMSCH_SYS_INT_STATUS__INT0_MASK 0x00000001L |
8215 | #define VCN_UMSCH_SYS_INT_STATUS__INT1_MASK 0x00000002L |
8216 | #define VCN_UMSCH_SYS_INT_STATUS__INT2_MASK 0x00000004L |
8217 | #define VCN_UMSCH_SYS_INT_STATUS__INT3_MASK 0x00000008L |
8218 | #define VCN_UMSCH_SYS_INT_STATUS__INT4_MASK 0x00000010L |
8219 | #define VCN_UMSCH_SYS_INT_STATUS__INT5_MASK 0x00000020L |
8220 | #define VCN_UMSCH_SYS_INT_STATUS__INT6_MASK 0x00000040L |
8221 | #define VCN_UMSCH_SYS_INT_STATUS__INT7_MASK 0x00000080L |
8222 | //VCN_UMSCH_SYS_INT_ACK |
8223 | #define VCN_UMSCH_SYS_INT_ACK__INT0__SHIFT 0x0 |
8224 | #define VCN_UMSCH_SYS_INT_ACK__INT1__SHIFT 0x1 |
8225 | #define VCN_UMSCH_SYS_INT_ACK__INT2__SHIFT 0x2 |
8226 | #define VCN_UMSCH_SYS_INT_ACK__INT3__SHIFT 0x3 |
8227 | #define VCN_UMSCH_SYS_INT_ACK__INT4__SHIFT 0x4 |
8228 | #define VCN_UMSCH_SYS_INT_ACK__INT5__SHIFT 0x5 |
8229 | #define VCN_UMSCH_SYS_INT_ACK__INT6__SHIFT 0x6 |
8230 | #define VCN_UMSCH_SYS_INT_ACK__INT7__SHIFT 0x7 |
8231 | #define VCN_UMSCH_SYS_INT_ACK__INT0_MASK 0x00000001L |
8232 | #define VCN_UMSCH_SYS_INT_ACK__INT1_MASK 0x00000002L |
8233 | #define VCN_UMSCH_SYS_INT_ACK__INT2_MASK 0x00000004L |
8234 | #define VCN_UMSCH_SYS_INT_ACK__INT3_MASK 0x00000008L |
8235 | #define VCN_UMSCH_SYS_INT_ACK__INT4_MASK 0x00000010L |
8236 | #define VCN_UMSCH_SYS_INT_ACK__INT5_MASK 0x00000020L |
8237 | #define VCN_UMSCH_SYS_INT_ACK__INT6_MASK 0x00000040L |
8238 | #define VCN_UMSCH_SYS_INT_ACK__INT7_MASK 0x00000080L |
8239 | //VCN_UMSCH_SYS_INT_SRC |
8240 | #define VCN_UMSCH_SYS_INT_SRC__INT0__SHIFT 0x0 |
8241 | #define VCN_UMSCH_SYS_INT_SRC__INT1__SHIFT 0x1 |
8242 | #define VCN_UMSCH_SYS_INT_SRC__INT2__SHIFT 0x2 |
8243 | #define VCN_UMSCH_SYS_INT_SRC__INT3__SHIFT 0x3 |
8244 | #define VCN_UMSCH_SYS_INT_SRC__INT4__SHIFT 0x4 |
8245 | #define VCN_UMSCH_SYS_INT_SRC__INT5__SHIFT 0x5 |
8246 | #define VCN_UMSCH_SYS_INT_SRC__INT6__SHIFT 0x6 |
8247 | #define VCN_UMSCH_SYS_INT_SRC__INT7__SHIFT 0x7 |
8248 | #define VCN_UMSCH_SYS_INT_SRC__INT0_MASK 0x00000001L |
8249 | #define VCN_UMSCH_SYS_INT_SRC__INT1_MASK 0x00000002L |
8250 | #define VCN_UMSCH_SYS_INT_SRC__INT2_MASK 0x00000004L |
8251 | #define VCN_UMSCH_SYS_INT_SRC__INT3_MASK 0x00000008L |
8252 | #define VCN_UMSCH_SYS_INT_SRC__INT4_MASK 0x00000010L |
8253 | #define VCN_UMSCH_SYS_INT_SRC__INT5_MASK 0x00000020L |
8254 | #define VCN_UMSCH_SYS_INT_SRC__INT6_MASK 0x00000040L |
8255 | #define VCN_UMSCH_SYS_INT_SRC__INT7_MASK 0x00000080L |
8256 | //VCN_UMSCH_IH_CTX_CTRL |
8257 | #define VCN_UMSCH_IH_CTX_CTRL__IH_CTX_ID__SHIFT 0x0 |
8258 | #define VCN_UMSCH_IH_CTX_CTRL__IH_CTX_ID_MASK 0x0FFFFFFFL |
8259 | //VCN_UMSCH_CGC_CTRL |
8260 | #define VCN_UMSCH_CGC_CTRL__UMSCH_MODE__SHIFT 0x0 |
8261 | #define VCN_UMSCH_CGC_CTRL__UMSCH__SHIFT 0x1 |
8262 | #define VCN_UMSCH_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 |
8263 | #define VCN_UMSCH_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 |
8264 | #define VCN_UMSCH_CGC_CTRL__UMSCH_REG_CG_MODE__SHIFT 0xe |
8265 | #define VCN_UMSCH_CGC_CTRL__UMSCH_MODE_MASK 0x00000001L |
8266 | #define VCN_UMSCH_CGC_CTRL__UMSCH_MASK 0x00000002L |
8267 | #define VCN_UMSCH_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL |
8268 | #define VCN_UMSCH_CGC_CTRL__CLK_OFF_DELAY_MASK 0x00003FC0L |
8269 | #define VCN_UMSCH_CGC_CTRL__UMSCH_REG_CG_MODE_MASK 0x00004000L |
8270 | //VCN_UMSCH_CGC_STATUS |
8271 | #define VCN_UMSCH_CGC_STATUS__UMSCH_CORE_ACTIVE__SHIFT 0x0 |
8272 | #define VCN_UMSCH_CGC_STATUS__UMSCH_CORE_ACTIVE_MASK 0x00000001L |
8273 | //VCN_UMSCH_CGC_MEM_CTRL |
8274 | #define VCN_UMSCH_CGC_MEM_CTRL__UMSCH_LS_EN_HW_ON__SHIFT 0x0 |
8275 | #define VCN_UMSCH_CGC_MEM_CTRL__UMSCH_LS_EN_SW_ON__SHIFT 0x1 |
8276 | #define VCN_UMSCH_CGC_MEM_CTRL__UMSCH_DS_EN__SHIFT 0x2 |
8277 | #define VCN_UMSCH_CGC_MEM_CTRL__UMSCH_SD_EN__SHIFT 0x3 |
8278 | #define VCN_UMSCH_CGC_MEM_CTRL__UMSCH_LS_EN_HW_ON_MASK 0x00000001L |
8279 | #define VCN_UMSCH_CGC_MEM_CTRL__UMSCH_LS_EN_SW_ON_MASK 0x00000002L |
8280 | #define VCN_UMSCH_CGC_MEM_CTRL__UMSCH_DS_EN_MASK 0x00000004L |
8281 | #define VCN_UMSCH_CGC_MEM_CTRL__UMSCH_SD_EN_MASK 0x00000008L |
8282 | //UVD_INTERNAL_REG_VIOLATION_8 |
8283 | #define UVD_INTERNAL_REG_VIOLATION_8__UVD_INTERNAL_REG_VIOLATION_8_ADDR__SHIFT 0x2 |
8284 | #define UVD_INTERNAL_REG_VIOLATION_8__UVD_INTERNAL_REG_VIOLATION_8_MASTER_ID__SHIFT 0x14 |
8285 | #define UVD_INTERNAL_REG_VIOLATION_8__UVD_INTERNAL_REG_VIOLATION_8_OP__SHIFT 0x18 |
8286 | #define UVD_INTERNAL_REG_VIOLATION_8__UVD_INTERNAL_REG_VIOLATION_8_ADDR_MASK 0x000FFFFCL |
8287 | #define UVD_INTERNAL_REG_VIOLATION_8__UVD_INTERNAL_REG_VIOLATION_8_MASTER_ID_MASK 0x00F00000L |
8288 | #define UVD_INTERNAL_REG_VIOLATION_8__UVD_INTERNAL_REG_VIOLATION_8_OP_MASK 0x01000000L |
8289 | //UVD_UMSCH_FORCE |
8290 | #define UVD_UMSCH_FORCE__IC_FORCE_GPUVM__SHIFT 0x0 |
8291 | #define UVD_UMSCH_FORCE__DC_FORCE_GPUVM__SHIFT 0x1 |
8292 | #define UVD_UMSCH_FORCE__FORCE_DROP_DISABLE__SHIFT 0x2 |
8293 | #define UVD_UMSCH_FORCE__IC_FORCE_GPUVM_MASK 0x00000001L |
8294 | #define UVD_UMSCH_FORCE__DC_FORCE_GPUVM_MASK 0x00000002L |
8295 | #define UVD_UMSCH_FORCE__FORCE_DROP_DISABLE_MASK 0x00000004L |
8296 | //UVD_UMSCH_DEBUG_INDEX |
8297 | #define UVD_UMSCH_DEBUG_INDEX__DEBUG_READ_ADDR__SHIFT 0x0 |
8298 | #define UVD_UMSCH_DEBUG_INDEX__DEBUG_ADDR_FREE_STR_DIS__SHIFT 0x1e |
8299 | #define UVD_UMSCH_DEBUG_INDEX__DEBUG_RESET__SHIFT 0x1f |
8300 | #define UVD_UMSCH_DEBUG_INDEX__DEBUG_READ_ADDR_MASK 0x0000001FL |
8301 | #define UVD_UMSCH_DEBUG_INDEX__DEBUG_ADDR_FREE_STR_DIS_MASK 0x40000000L |
8302 | #define UVD_UMSCH_DEBUG_INDEX__DEBUG_RESET_MASK 0x80000000L |
8303 | //UVD_UMSCH_DEBUG_DATA_LO |
8304 | #define UVD_UMSCH_DEBUG_DATA_LO__DEBUG_DATA_LO__SHIFT 0x0 |
8305 | #define UVD_UMSCH_DEBUG_DATA_LO__DEBUG_DATA_LO_MASK 0xFFFFFFFFL |
8306 | //UVD_UMSCH_DEBUG_DATA_HI |
8307 | #define UVD_UMSCH_DEBUG_DATA_HI__DEBUG_DATA_HI__SHIFT 0x0 |
8308 | #define UVD_UMSCH_DEBUG_DATA_HI__DEBUG_DATA_HI_MASK 0xFFFFFFFFL |
8309 | //UVD_UMSCH_DEBUG_UTCL2_TCIU_IF |
8310 | #define UVD_UMSCH_DEBUG_UTCL2_TCIU_IF__UTCL2_IC_NACK__SHIFT 0x0 |
8311 | #define UVD_UMSCH_DEBUG_UTCL2_TCIU_IF__UTCL2_DC_NACK__SHIFT 0x2 |
8312 | #define UVD_UMSCH_DEBUG_UTCL2_TCIU_IF__TCIU_IC_DROP__SHIFT 0x4 |
8313 | #define UVD_UMSCH_DEBUG_UTCL2_TCIU_IF__TCIU_DC_DROP__SHIFT 0x5 |
8314 | #define UVD_UMSCH_DEBUG_UTCL2_TCIU_IF__UTCL2_IC_NACK_MASK 0x00000003L |
8315 | #define UVD_UMSCH_DEBUG_UTCL2_TCIU_IF__UTCL2_DC_NACK_MASK 0x0000000CL |
8316 | #define UVD_UMSCH_DEBUG_UTCL2_TCIU_IF__TCIU_IC_DROP_MASK 0x00000010L |
8317 | #define UVD_UMSCH_DEBUG_UTCL2_TCIU_IF__TCIU_DC_DROP_MASK 0x00000020L |
8318 | //UMSCH_MES_RESET_CTRL |
8319 | #define UMSCH_MES_RESET_CTRL__MES_CORE_SOFT_RESET__SHIFT 0x0 |
8320 | #define UMSCH_MES_RESET_CTRL__MES_CORE_SOFT_RESET_MASK 0x00000001L |
8321 | |
8322 | //VCN_MES_PRGRM_CNTR_START |
8323 | #define VCN_MES_PRGRM_CNTR_START__IP_START__SHIFT 0x0 |
8324 | #define VCN_MES_PRGRM_CNTR_START__IP_START_MASK 0xFFFFFFFFL |
8325 | //VCN_MES_INTR_ROUTINE_START |
8326 | #define VCN_MES_INTR_ROUTINE_START__IR_START__SHIFT 0x0 |
8327 | #define VCN_MES_INTR_ROUTINE_START__IR_START_MASK 0xFFFFFFFFL |
8328 | //VCN_MES_MTVEC_LO |
8329 | #define VCN_MES_MTVEC_LO__ADDR_LO__SHIFT 0x0 |
8330 | #define VCN_MES_MTVEC_LO__ADDR_LO_MASK 0xFFFFFFFFL |
8331 | //VCN_MES_INTR_ROUTINE_START_HI |
8332 | #define VCN_MES_INTR_ROUTINE_START_HI__IR_START__SHIFT 0x0 |
8333 | #define VCN_MES_INTR_ROUTINE_START_HI__IR_START_MASK 0xFFFFFFFFL |
8334 | //VCN_MES_MTVEC_HI |
8335 | #define VCN_MES_MTVEC_HI__ADDR_LO__SHIFT 0x0 |
8336 | #define VCN_MES_MTVEC_HI__ADDR_LO_MASK 0xFFFFFFFFL |
8337 | //VCN_MES_CNTL |
8338 | #define VCN_MES_CNTL__MES_INVALIDATE_ICACHE__SHIFT 0x4 |
8339 | #define VCN_MES_CNTL__MES_PIPE0_RESET__SHIFT 0x10 |
8340 | #define VCN_MES_CNTL__MES_PIPE1_RESET__SHIFT 0x11 |
8341 | #define VCN_MES_CNTL__MES_PIPE2_RESET__SHIFT 0x12 |
8342 | #define VCN_MES_CNTL__MES_PIPE3_RESET__SHIFT 0x13 |
8343 | #define VCN_MES_CNTL__MES_PIPE0_ACTIVE__SHIFT 0x1a |
8344 | #define VCN_MES_CNTL__MES_PIPE1_ACTIVE__SHIFT 0x1b |
8345 | #define VCN_MES_CNTL__MES_PIPE2_ACTIVE__SHIFT 0x1c |
8346 | #define VCN_MES_CNTL__MES_PIPE3_ACTIVE__SHIFT 0x1d |
8347 | #define VCN_MES_CNTL__MES_HALT__SHIFT 0x1e |
8348 | #define VCN_MES_CNTL__MES_STEP__SHIFT 0x1f |
8349 | #define VCN_MES_CNTL__MES_INVALIDATE_ICACHE_MASK 0x00000010L |
8350 | #define VCN_MES_CNTL__MES_PIPE0_RESET_MASK 0x00010000L |
8351 | #define VCN_MES_CNTL__MES_PIPE1_RESET_MASK 0x00020000L |
8352 | #define VCN_MES_CNTL__MES_PIPE2_RESET_MASK 0x00040000L |
8353 | #define VCN_MES_CNTL__MES_PIPE3_RESET_MASK 0x00080000L |
8354 | #define VCN_MES_CNTL__MES_PIPE0_ACTIVE_MASK 0x04000000L |
8355 | #define VCN_MES_CNTL__MES_PIPE1_ACTIVE_MASK 0x08000000L |
8356 | #define VCN_MES_CNTL__MES_PIPE2_ACTIVE_MASK 0x10000000L |
8357 | #define VCN_MES_CNTL__MES_PIPE3_ACTIVE_MASK 0x20000000L |
8358 | #define VCN_MES_CNTL__MES_HALT_MASK 0x40000000L |
8359 | #define VCN_MES_CNTL__MES_STEP_MASK 0x80000000L |
8360 | //VCN_MES_PIPE_PRIORITY_CNTS |
8361 | #define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 |
8362 | #define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 |
8363 | #define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 |
8364 | #define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 |
8365 | #define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL |
8366 | #define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L |
8367 | #define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L |
8368 | #define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L |
8369 | //VCN_MES_PIPE0_PRIORITY |
8370 | #define VCN_MES_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 |
8371 | #define VCN_MES_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L |
8372 | //VCN_MES_PIPE1_PRIORITY |
8373 | #define VCN_MES_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 |
8374 | #define VCN_MES_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L |
8375 | //VCN_MES_PIPE2_PRIORITY |
8376 | #define VCN_MES_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 |
8377 | #define VCN_MES_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L |
8378 | //VCN_MES_PIPE3_PRIORITY |
8379 | #define VCN_MES_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 |
8380 | #define VCN_MES_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L |
8381 | //VCN_MES_HEADER_DUMP |
8382 | #define 0x0 |
8383 | #define 0xFFFFFFFFL |
8384 | //VCN_MES_MIE_LO |
8385 | #define VCN_MES_MIE_LO__MES_INT__SHIFT 0x0 |
8386 | #define VCN_MES_MIE_LO__MES_INT_MASK 0xFFFFFFFFL |
8387 | //VCN_MES_MIE_HI |
8388 | #define VCN_MES_MIE_HI__MES_INT__SHIFT 0x0 |
8389 | #define VCN_MES_MIE_HI__MES_INT_MASK 0xFFFFFFFFL |
8390 | //VCN_MES_INTERRUPT |
8391 | #define VCN_MES_INTERRUPT__MES_INT__SHIFT 0x0 |
8392 | #define VCN_MES_INTERRUPT__MES_INT_MASK 0xFFFFFFFFL |
8393 | //VCN_MES_SCRATCH_INDEX |
8394 | #define VCN_MES_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 |
8395 | #define VCN_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f |
8396 | #define VCN_MES_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL |
8397 | #define VCN_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L |
8398 | //VCN_MES_SCRATCH_DATA |
8399 | #define VCN_MES_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 |
8400 | #define VCN_MES_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL |
8401 | //VCN_MES_INSTR_PNTR |
8402 | #define VCN_MES_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
8403 | #define VCN_MES_INSTR_PNTR__INSTR_PNTR_MASK 0x000FFFFFL |
8404 | //VCN_MES_MSCRATCH_HI |
8405 | #define VCN_MES_MSCRATCH_HI__DATA__SHIFT 0x0 |
8406 | #define VCN_MES_MSCRATCH_HI__DATA_MASK 0xFFFFFFFFL |
8407 | //VCN_MES_MSCRATCH_LO |
8408 | #define VCN_MES_MSCRATCH_LO__DATA__SHIFT 0x0 |
8409 | #define VCN_MES_MSCRATCH_LO__DATA_MASK 0xFFFFFFFFL |
8410 | //VCN_MES_MSTATUS_LO |
8411 | #define VCN_MES_MSTATUS_LO__STATUS_LO__SHIFT 0x0 |
8412 | #define VCN_MES_MSTATUS_LO__STATUS_LO_MASK 0xFFFFFFFFL |
8413 | //VCN_MES_MSTATUS_HI |
8414 | #define VCN_MES_MSTATUS_HI__STATUS_HI__SHIFT 0x0 |
8415 | #define VCN_MES_MSTATUS_HI__STATUS_HI_MASK 0xFFFFFFFFL |
8416 | //VCN_MES_MEPC_LO |
8417 | #define VCN_MES_MEPC_LO__MEPC_LO__SHIFT 0x0 |
8418 | #define VCN_MES_MEPC_LO__MEPC_LO_MASK 0xFFFFFFFFL |
8419 | //VCN_MES_MEPC_HI |
8420 | #define VCN_MES_MEPC_HI__MEPC_HI__SHIFT 0x0 |
8421 | #define VCN_MES_MEPC_HI__MEPC_HI_MASK 0xFFFFFFFFL |
8422 | //VCN_MES_MCAUSE_LO |
8423 | #define VCN_MES_MCAUSE_LO__CAUSE_LO__SHIFT 0x0 |
8424 | #define VCN_MES_MCAUSE_LO__CAUSE_LO_MASK 0xFFFFFFFFL |
8425 | //VCN_MES_MCAUSE_HI |
8426 | #define VCN_MES_MCAUSE_HI__CAUSE_HI__SHIFT 0x0 |
8427 | #define VCN_MES_MCAUSE_HI__CAUSE_HI_MASK 0xFFFFFFFFL |
8428 | //VCN_MES_MBADADDR_LO |
8429 | #define VCN_MES_MBADADDR_LO__ADDR_LO__SHIFT 0x0 |
8430 | #define VCN_MES_MBADADDR_LO__ADDR_LO_MASK 0xFFFFFFFFL |
8431 | //VCN_MES_MBADADDR_HI |
8432 | #define VCN_MES_MBADADDR_HI__ADDR_HI__SHIFT 0x0 |
8433 | #define VCN_MES_MBADADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL |
8434 | //VCN_MES_MIP_LO |
8435 | #define VCN_MES_MIP_LO__MIP_LO__SHIFT 0x0 |
8436 | #define VCN_MES_MIP_LO__MIP_LO_MASK 0xFFFFFFFFL |
8437 | //VCN_MES_MIP_HI |
8438 | #define VCN_MES_MIP_HI__MIP_HI__SHIFT 0x0 |
8439 | #define VCN_MES_MIP_HI__MIP_HI_MASK 0xFFFFFFFFL |
8440 | //VCN_MES_IC_OP_CNTL |
8441 | #define VCN_MES_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 |
8442 | #define VCN_MES_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 |
8443 | #define VCN_MES_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 |
8444 | #define VCN_MES_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L |
8445 | #define VCN_MES_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L |
8446 | #define VCN_MES_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L |
8447 | //VCN_MES_MCYCLE_LO |
8448 | #define VCN_MES_MCYCLE_LO__CYCLE_LO__SHIFT 0x0 |
8449 | #define VCN_MES_MCYCLE_LO__CYCLE_LO_MASK 0xFFFFFFFFL |
8450 | //VCN_MES_MCYCLE_HI |
8451 | #define VCN_MES_MCYCLE_HI__CYCLE_HI__SHIFT 0x0 |
8452 | #define VCN_MES_MCYCLE_HI__CYCLE_HI_MASK 0xFFFFFFFFL |
8453 | //VCN_MES_MTIME_LO |
8454 | #define VCN_MES_MTIME_LO__TIME_LO__SHIFT 0x0 |
8455 | #define VCN_MES_MTIME_LO__TIME_LO_MASK 0xFFFFFFFFL |
8456 | //VCN_MES_MTIME_HI |
8457 | #define VCN_MES_MTIME_HI__TIME_HI__SHIFT 0x0 |
8458 | #define VCN_MES_MTIME_HI__TIME_HI_MASK 0xFFFFFFFFL |
8459 | //VCN_MES_MINSTRET_LO |
8460 | #define VCN_MES_MINSTRET_LO__INSTRET_LO__SHIFT 0x0 |
8461 | #define VCN_MES_MINSTRET_LO__INSTRET_LO_MASK 0xFFFFFFFFL |
8462 | //VCN_MES_MINSTRET_HI |
8463 | #define VCN_MES_MINSTRET_HI__INSTRET_HI__SHIFT 0x0 |
8464 | #define VCN_MES_MINSTRET_HI__INSTRET_HI_MASK 0xFFFFFFFFL |
8465 | //VCN_MES_MISA_LO |
8466 | #define VCN_MES_MISA_LO__MISA_LO__SHIFT 0x0 |
8467 | #define VCN_MES_MISA_LO__MISA_LO_MASK 0xFFFFFFFFL |
8468 | //VCN_MES_MISA_HI |
8469 | #define VCN_MES_MISA_HI__MISA_HI__SHIFT 0x0 |
8470 | #define VCN_MES_MISA_HI__MISA_HI_MASK 0xFFFFFFFFL |
8471 | //VCN_MES_MVENDORID_LO |
8472 | #define VCN_MES_MVENDORID_LO__MVENDORID_LO__SHIFT 0x0 |
8473 | #define VCN_MES_MVENDORID_LO__MVENDORID_LO_MASK 0xFFFFFFFFL |
8474 | //VCN_MES_MVENDORID_HI |
8475 | #define VCN_MES_MVENDORID_HI__MVENDORID_HI__SHIFT 0x0 |
8476 | #define VCN_MES_MVENDORID_HI__MVENDORID_HI_MASK 0xFFFFFFFFL |
8477 | //VCN_MES_MARCHID_LO |
8478 | #define VCN_MES_MARCHID_LO__MARCHID_LO__SHIFT 0x0 |
8479 | #define VCN_MES_MARCHID_LO__MARCHID_LO_MASK 0xFFFFFFFFL |
8480 | //VCN_MES_MARCHID_HI |
8481 | #define VCN_MES_MARCHID_HI__MARCHID_HI__SHIFT 0x0 |
8482 | #define VCN_MES_MARCHID_HI__MARCHID_HI_MASK 0xFFFFFFFFL |
8483 | //VCN_MES_MIMPID_LO |
8484 | #define VCN_MES_MIMPID_LO__MIMPID_LO__SHIFT 0x0 |
8485 | #define VCN_MES_MIMPID_LO__MIMPID_LO_MASK 0xFFFFFFFFL |
8486 | //VCN_MES_MIMPID_HI |
8487 | #define VCN_MES_MIMPID_HI__MIMPID_HI__SHIFT 0x0 |
8488 | #define VCN_MES_MIMPID_HI__MIMPID_HI_MASK 0xFFFFFFFFL |
8489 | //VCN_MES_MHARTID_LO |
8490 | #define VCN_MES_MHARTID_LO__MHARTID_LO__SHIFT 0x0 |
8491 | #define VCN_MES_MHARTID_LO__MHARTID_LO_MASK 0xFFFFFFFFL |
8492 | //VCN_MES_MHARTID_HI |
8493 | #define VCN_MES_MHARTID_HI__MHARTID_HI__SHIFT 0x0 |
8494 | #define VCN_MES_MHARTID_HI__MHARTID_HI_MASK 0xFFFFFFFFL |
8495 | //VCN_MES_DC_BASE_CNTL |
8496 | #define VCN_MES_DC_BASE_CNTL__VMID__SHIFT 0x0 |
8497 | #define VCN_MES_DC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 |
8498 | #define VCN_MES_DC_BASE_CNTL__VMID_MASK 0x0000000FL |
8499 | #define VCN_MES_DC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L |
8500 | //VCN_MES_DC_OP_CNTL |
8501 | #define VCN_MES_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT 0x0 |
8502 | #define VCN_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT 0x1 |
8503 | #define VCN_MES_DC_OP_CNTL__BYPASS_ALL__SHIFT 0x2 |
8504 | #define VCN_MES_DC_OP_CNTL__DEPRECATED__SHIFT 0x3 |
8505 | #define VCN_MES_DC_OP_CNTL__DEPRACATED__SHIFT 0x4 |
8506 | #define VCN_MES_DC_OP_CNTL__INVALIDATE_DCACHE_MASK 0x00000001L |
8507 | #define VCN_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK 0x00000002L |
8508 | #define VCN_MES_DC_OP_CNTL__BYPASS_ALL_MASK 0x00000004L |
8509 | #define VCN_MES_DC_OP_CNTL__DEPRECATED_MASK 0x00000008L |
8510 | #define VCN_MES_DC_OP_CNTL__DEPRACATED_MASK 0x00000010L |
8511 | //VCN_MES_MTIMECMP_LO |
8512 | #define VCN_MES_MTIMECMP_LO__TIME_LO__SHIFT 0x0 |
8513 | #define VCN_MES_MTIMECMP_LO__TIME_LO_MASK 0xFFFFFFFFL |
8514 | //VCN_MES_MTIMECMP_HI |
8515 | #define VCN_MES_MTIMECMP_HI__TIME_HI__SHIFT 0x0 |
8516 | #define VCN_MES_MTIMECMP_HI__TIME_HI_MASK 0xFFFFFFFFL |
8517 | //VCN_MES_DEBUG_INTERRUPT_INSTR_PNTR |
8518 | #define VCN_MES_DEBUG_INTERRUPT_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
8519 | #define VCN_MES_DEBUG_INTERRUPT_INSTR_PNTR__INSTR_PNTR_MASK 0xFFFFFFFFL |
8520 | //VCN_MES_GP0_LO |
8521 | #define VCN_MES_GP0_LO__PG_VIRT_HALTED__SHIFT 0x0 |
8522 | #define VCN_MES_GP0_LO__DATA__SHIFT 0x1 |
8523 | #define VCN_MES_GP0_LO__PG_VIRT_HALTED_MASK 0x00000001L |
8524 | #define VCN_MES_GP0_LO__DATA_MASK 0xFFFFFFFEL |
8525 | //VCN_MES_GP0_HI |
8526 | #define VCN_MES_GP0_HI__M_RET_ADDR__SHIFT 0x0 |
8527 | #define VCN_MES_GP0_HI__M_RET_ADDR_MASK 0xFFFFFFFFL |
8528 | //VCN_MES_GP1_LO |
8529 | #define VCN_MES_GP1_LO__RD_WR_SELECT_LO__SHIFT 0x0 |
8530 | #define VCN_MES_GP1_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL |
8531 | //VCN_MES_GP1_HI |
8532 | #define VCN_MES_GP1_HI__RD_WR_SELECT_HI__SHIFT 0x0 |
8533 | #define VCN_MES_GP1_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL |
8534 | //VCN_MES_GP2_LO |
8535 | #define VCN_MES_GP2_LO__STACK_PNTR_LO__SHIFT 0x0 |
8536 | #define VCN_MES_GP2_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL |
8537 | //VCN_MES_GP2_HI |
8538 | #define VCN_MES_GP2_HI__STACK_PNTR_HI__SHIFT 0x0 |
8539 | #define VCN_MES_GP2_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL |
8540 | //VCN_MES_GP3_LO |
8541 | #define VCN_MES_GP3_LO__DATA__SHIFT 0x0 |
8542 | #define VCN_MES_GP3_LO__DATA_MASK 0xFFFFFFFFL |
8543 | //VCN_MES_GP3_HI |
8544 | #define VCN_MES_GP3_HI__DATA__SHIFT 0x0 |
8545 | #define VCN_MES_GP3_HI__DATA_MASK 0xFFFFFFFFL |
8546 | //VCN_MES_GP4_LO |
8547 | #define VCN_MES_GP4_LO__DATA__SHIFT 0x0 |
8548 | #define VCN_MES_GP4_LO__DATA_MASK 0xFFFFFFFFL |
8549 | //VCN_MES_GP4_HI |
8550 | #define VCN_MES_GP4_HI__DATA__SHIFT 0x0 |
8551 | #define VCN_MES_GP4_HI__DATA_MASK 0xFFFFFFFFL |
8552 | //VCN_MES_GP5_LO |
8553 | #define VCN_MES_GP5_LO__PG_VIRT_HALTED__SHIFT 0x0 |
8554 | #define VCN_MES_GP5_LO__DATA__SHIFT 0x1 |
8555 | #define VCN_MES_GP5_LO__PG_VIRT_HALTED_MASK 0x00000001L |
8556 | #define VCN_MES_GP5_LO__DATA_MASK 0xFFFFFFFEL |
8557 | //VCN_MES_GP5_HI |
8558 | #define VCN_MES_GP5_HI__M_RET_ADDR__SHIFT 0x0 |
8559 | #define VCN_MES_GP5_HI__M_RET_ADDR_MASK 0xFFFFFFFFL |
8560 | //VCN_MES_GP6_LO |
8561 | #define VCN_MES_GP6_LO__RD_WR_SELECT_LO__SHIFT 0x0 |
8562 | #define VCN_MES_GP6_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL |
8563 | //VCN_MES_GP6_HI |
8564 | #define VCN_MES_GP6_HI__RD_WR_SELECT_HI__SHIFT 0x0 |
8565 | #define VCN_MES_GP6_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL |
8566 | //VCN_MES_GP7_LO |
8567 | #define VCN_MES_GP7_LO__STACK_PNTR_LO__SHIFT 0x0 |
8568 | #define VCN_MES_GP7_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL |
8569 | //VCN_MES_GP7_HI |
8570 | #define VCN_MES_GP7_HI__STACK_PNTR_HI__SHIFT 0x0 |
8571 | #define VCN_MES_GP7_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL |
8572 | //VCN_MES_GP8_LO |
8573 | #define VCN_MES_GP8_LO__DATA__SHIFT 0x0 |
8574 | #define VCN_MES_GP8_LO__DATA_MASK 0xFFFFFFFFL |
8575 | //VCN_MES_GP8_HI |
8576 | #define VCN_MES_GP8_HI__DATA__SHIFT 0x0 |
8577 | #define VCN_MES_GP8_HI__DATA_MASK 0xFFFFFFFFL |
8578 | //VCN_MES_GP9_LO |
8579 | #define VCN_MES_GP9_LO__DATA__SHIFT 0x0 |
8580 | #define VCN_MES_GP9_LO__DATA_MASK 0xFFFFFFFFL |
8581 | //VCN_MES_GP9_HI |
8582 | #define VCN_MES_GP9_HI__DATA__SHIFT 0x0 |
8583 | #define VCN_MES_GP9_HI__DATA_MASK 0xFFFFFFFFL |
8584 | //VCN_MES_DM_INDEX_ADDR |
8585 | #define VCN_MES_DM_INDEX_ADDR__ADDR__SHIFT 0x0 |
8586 | #define VCN_MES_DM_INDEX_ADDR__ADDR_MASK 0xFFFFFFFFL |
8587 | //VCN_MES_DM_INDEX_DATA |
8588 | #define VCN_MES_DM_INDEX_DATA__DATA__SHIFT 0x0 |
8589 | #define VCN_MES_DM_INDEX_DATA__DATA_MASK 0xFFFFFFFFL |
8590 | //VCN_MES_DBG_FROM_RST |
8591 | #define VCN_MES_DBG_FROM_RST__CONTROL__SHIFT 0x0 |
8592 | #define VCN_MES_DBG_FROM_RST__CONTROL_MASK 0x00000001L |
8593 | //VCN_MES_LOCAL_BASE0_LO |
8594 | #define VCN_MES_LOCAL_BASE0_LO__BASE0_LO__SHIFT 0x10 |
8595 | #define VCN_MES_LOCAL_BASE0_LO__BASE0_LO_MASK 0xFFFF0000L |
8596 | //VCN_MES_LOCAL_BASE0_HI |
8597 | #define VCN_MES_LOCAL_BASE0_HI__BASE0_HI__SHIFT 0x0 |
8598 | #define VCN_MES_LOCAL_BASE0_HI__BASE0_HI_MASK 0x0000FFFFL |
8599 | //VCN_MES_LOCAL_MASK0_LO |
8600 | #define VCN_MES_LOCAL_MASK0_LO__MASK0_LO__SHIFT 0x10 |
8601 | #define VCN_MES_LOCAL_MASK0_LO__MASK0_LO_MASK 0xFFFF0000L |
8602 | //VCN_MES_LOCAL_MASK0_HI |
8603 | #define VCN_MES_LOCAL_MASK0_HI__MASK0_HI__SHIFT 0x0 |
8604 | #define VCN_MES_LOCAL_MASK0_HI__MASK0_HI_MASK 0x0000FFFFL |
8605 | //VCN_MES_LOCAL_APERTURE |
8606 | #define VCN_MES_LOCAL_APERTURE__APERTURE__SHIFT 0x0 |
8607 | #define VCN_MES_LOCAL_APERTURE__APERTURE_MASK 0x00000007L |
8608 | //VCN_MES_LOCAL_INSTR_BASE_LO |
8609 | #define VCN_MES_LOCAL_INSTR_BASE_LO__BASE_LO__SHIFT 0x10 |
8610 | #define VCN_MES_LOCAL_INSTR_BASE_LO__BASE_LO_MASK 0xFFFF0000L |
8611 | //VCN_MES_LOCAL_INSTR_BASE_HI |
8612 | #define VCN_MES_LOCAL_INSTR_BASE_HI__BASE_HI__SHIFT 0x0 |
8613 | #define VCN_MES_LOCAL_INSTR_BASE_HI__BASE_HI_MASK 0x0000FFFFL |
8614 | //VCN_MES_LOCAL_INSTR_MASK_LO |
8615 | #define VCN_MES_LOCAL_INSTR_MASK_LO__MASK_LO__SHIFT 0x10 |
8616 | #define VCN_MES_LOCAL_INSTR_MASK_LO__MASK_LO_MASK 0xFFFF0000L |
8617 | //VCN_MES_LOCAL_INSTR_MASK_HI |
8618 | #define VCN_MES_LOCAL_INSTR_MASK_HI__MASK_HI__SHIFT 0x0 |
8619 | #define VCN_MES_LOCAL_INSTR_MASK_HI__MASK_HI_MASK 0x0000FFFFL |
8620 | //VCN_MES_LOCAL_INSTR_APERTURE |
8621 | #define VCN_MES_LOCAL_INSTR_APERTURE__APERTURE__SHIFT 0x0 |
8622 | #define VCN_MES_LOCAL_INSTR_APERTURE__APERTURE_MASK 0x00000007L |
8623 | //VCN_MES_LOCAL_SCRATCH_APERTURE |
8624 | #define VCN_MES_LOCAL_SCRATCH_APERTURE__APERTURE__SHIFT 0x0 |
8625 | #define VCN_MES_LOCAL_SCRATCH_APERTURE__APERTURE_MASK 0x00000007L |
8626 | //VCN_MES_LOCAL_SCRATCH_BASE_LO |
8627 | #define VCN_MES_LOCAL_SCRATCH_BASE_LO__BASE_LO__SHIFT 0x10 |
8628 | #define VCN_MES_LOCAL_SCRATCH_BASE_LO__BASE_LO_MASK 0xFFFF0000L |
8629 | //VCN_MES_LOCAL_SCRATCH_BASE_HI |
8630 | #define VCN_MES_LOCAL_SCRATCH_BASE_HI__BASE_HI__SHIFT 0x0 |
8631 | #define VCN_MES_LOCAL_SCRATCH_BASE_HI__BASE_HI_MASK 0x0000FFFFL |
8632 | //VCN_MES_PERFCOUNT_CNTL |
8633 | #define VCN_MES_PERFCOUNT_CNTL__EVENT_SEL__SHIFT 0x0 |
8634 | #define VCN_MES_PERFCOUNT_CNTL__EVENT_SEL_MASK 0x0000001FL |
8635 | //VCN_MES_PENDING_INTERRUPT |
8636 | #define VCN_MES_PENDING_INTERRUPT__PENDING_INTERRUPT__SHIFT 0x0 |
8637 | #define VCN_MES_PENDING_INTERRUPT__PENDING_INTERRUPT_MASK 0xFFFFFFFFL |
8638 | //VCN_MES_PRIV_LEVEL |
8639 | #define VCN_MES_PRIV_LEVEL__PRIV_LEVEL__SHIFT 0x0 |
8640 | #define VCN_MES_PRIV_LEVEL__GRBM_PRIV_LEVEL__SHIFT 0x1 |
8641 | #define VCN_MES_PRIV_LEVEL__PRIV_LEVEL_MASK 0x00000001L |
8642 | #define VCN_MES_PRIV_LEVEL__GRBM_PRIV_LEVEL_MASK 0x00000002L |
8643 | //VCN_MES_PRIV_LEVEL_VIOLATION_STATUS |
8644 | #define VCN_MES_PRIV_LEVEL_VIOLATION_STATUS__PRIV_LEVEL_VIOLATION_OCCURRED__SHIFT 0x0 |
8645 | #define VCN_MES_PRIV_LEVEL_VIOLATION_STATUS__PRIV_LEVEL_VIOLATION_OP__SHIFT 0x1 |
8646 | #define VCN_MES_PRIV_LEVEL_VIOLATION_STATUS__PRIV_LEVEL_VIOLATION_ADDR__SHIFT 0x2 |
8647 | #define VCN_MES_PRIV_LEVEL_VIOLATION_STATUS__PRIV_LEVEL_VIOLATION_APERTURE__SHIFT 0x16 |
8648 | #define VCN_MES_PRIV_LEVEL_VIOLATION_STATUS__PRIV_LEVEL_VIOLATION_OCCURRED_MASK 0x00000001L |
8649 | #define VCN_MES_PRIV_LEVEL_VIOLATION_STATUS__PRIV_LEVEL_VIOLATION_OP_MASK 0x00000002L |
8650 | #define VCN_MES_PRIV_LEVEL_VIOLATION_STATUS__PRIV_LEVEL_VIOLATION_ADDR_MASK 0x003FFFFCL |
8651 | #define VCN_MES_PRIV_LEVEL_VIOLATION_STATUS__PRIV_LEVEL_VIOLATION_APERTURE_MASK 0x01C00000L |
8652 | //VCN_MES_PRGRM_CNTR_START_HI |
8653 | #define VCN_MES_PRGRM_CNTR_START_HI__IP_START__SHIFT 0x0 |
8654 | #define VCN_MES_PRGRM_CNTR_START_HI__IP_START_MASK 0x3FFFFFFFL |
8655 | //VCN_MES_DEBUG_INTERRUPT_INSTR_PNTR_HI |
8656 | #define VCN_MES_DEBUG_INTERRUPT_INSTR_PNTR_HI__INSTR_PNTR__SHIFT 0x0 |
8657 | #define VCN_MES_DEBUG_INTERRUPT_INSTR_PNTR_HI__INSTR_PNTR_MASK 0x3FFFFFFFL |
8658 | //VCN_MES_INTERRUPT_DATA_16 |
8659 | #define VCN_MES_INTERRUPT_DATA_16__DATA__SHIFT 0x0 |
8660 | #define VCN_MES_INTERRUPT_DATA_16__DATA_MASK 0xFFFFFFFFL |
8661 | //VCN_MES_INTERRUPT_DATA_17 |
8662 | #define VCN_MES_INTERRUPT_DATA_17__DATA__SHIFT 0x0 |
8663 | #define VCN_MES_INTERRUPT_DATA_17__DATA_MASK 0xFFFFFFFFL |
8664 | //VCN_MES_INTERRUPT_DATA_18 |
8665 | #define VCN_MES_INTERRUPT_DATA_18__DATA__SHIFT 0x0 |
8666 | #define VCN_MES_INTERRUPT_DATA_18__DATA_MASK 0xFFFFFFFFL |
8667 | //VCN_MES_INTERRUPT_DATA_19 |
8668 | #define VCN_MES_INTERRUPT_DATA_19__DATA__SHIFT 0x0 |
8669 | #define VCN_MES_INTERRUPT_DATA_19__DATA_MASK 0xFFFFFFFFL |
8670 | //VCN_MES_INTERRUPT_DATA_20 |
8671 | #define VCN_MES_INTERRUPT_DATA_20__DATA__SHIFT 0x0 |
8672 | #define VCN_MES_INTERRUPT_DATA_20__DATA_MASK 0xFFFFFFFFL |
8673 | //VCN_MES_INTERRUPT_DATA_21 |
8674 | #define VCN_MES_INTERRUPT_DATA_21__DATA__SHIFT 0x0 |
8675 | #define VCN_MES_INTERRUPT_DATA_21__DATA_MASK 0xFFFFFFFFL |
8676 | //VCN_MES_INTERRUPT_DATA_22 |
8677 | #define VCN_MES_INTERRUPT_DATA_22__DATA__SHIFT 0x0 |
8678 | #define VCN_MES_INTERRUPT_DATA_22__DATA_MASK 0xFFFFFFFFL |
8679 | //VCN_MES_INTERRUPT_DATA_23 |
8680 | #define VCN_MES_INTERRUPT_DATA_23__DATA__SHIFT 0x0 |
8681 | #define VCN_MES_INTERRUPT_DATA_23__DATA_MASK 0xFFFFFFFFL |
8682 | //VCN_MES_INTERRUPT_DATA_24 |
8683 | #define VCN_MES_INTERRUPT_DATA_24__DATA__SHIFT 0x0 |
8684 | #define VCN_MES_INTERRUPT_DATA_24__DATA_MASK 0xFFFFFFFFL |
8685 | //VCN_MES_INTERRUPT_DATA_25 |
8686 | #define VCN_MES_INTERRUPT_DATA_25__DATA__SHIFT 0x0 |
8687 | #define VCN_MES_INTERRUPT_DATA_25__DATA_MASK 0xFFFFFFFFL |
8688 | //VCN_MES_INTERRUPT_DATA_26 |
8689 | #define VCN_MES_INTERRUPT_DATA_26__DATA__SHIFT 0x0 |
8690 | #define VCN_MES_INTERRUPT_DATA_26__DATA_MASK 0xFFFFFFFFL |
8691 | //VCN_MES_INTERRUPT_DATA_27 |
8692 | #define VCN_MES_INTERRUPT_DATA_27__DATA__SHIFT 0x0 |
8693 | #define VCN_MES_INTERRUPT_DATA_27__DATA_MASK 0xFFFFFFFFL |
8694 | //VCN_MES_INTERRUPT_DATA_28 |
8695 | #define VCN_MES_INTERRUPT_DATA_28__DATA__SHIFT 0x0 |
8696 | #define VCN_MES_INTERRUPT_DATA_28__DATA_MASK 0xFFFFFFFFL |
8697 | //VCN_MES_INTERRUPT_DATA_29 |
8698 | #define VCN_MES_INTERRUPT_DATA_29__DATA__SHIFT 0x0 |
8699 | #define VCN_MES_INTERRUPT_DATA_29__DATA_MASK 0xFFFFFFFFL |
8700 | //VCN_MES_INTERRUPT_DATA_30 |
8701 | #define VCN_MES_INTERRUPT_DATA_30__DATA__SHIFT 0x0 |
8702 | #define VCN_MES_INTERRUPT_DATA_30__DATA_MASK 0xFFFFFFFFL |
8703 | //VCN_MES_INTERRUPT_DATA_31 |
8704 | #define VCN_MES_INTERRUPT_DATA_31__DATA__SHIFT 0x0 |
8705 | #define VCN_MES_INTERRUPT_DATA_31__DATA_MASK 0xFFFFFFFFL |
8706 | //VCN_MES_DC_APERTURE0_BASE |
8707 | #define VCN_MES_DC_APERTURE0_BASE__BASE__SHIFT 0x0 |
8708 | #define VCN_MES_DC_APERTURE0_BASE__BASE_MASK 0xFFFFFFFFL |
8709 | //VCN_MES_DC_APERTURE0_MASK |
8710 | #define VCN_MES_DC_APERTURE0_MASK__MASK__SHIFT 0x0 |
8711 | #define VCN_MES_DC_APERTURE0_MASK__MASK_MASK 0xFFFFFFFFL |
8712 | //VCN_MES_DC_APERTURE0_CNTL |
8713 | #define VCN_MES_DC_APERTURE0_CNTL__VMID__SHIFT 0x0 |
8714 | #define VCN_MES_DC_APERTURE0_CNTL__BYPASS_MODE__SHIFT 0x4 |
8715 | #define VCN_MES_DC_APERTURE0_CNTL__VMID_MASK 0x0000000FL |
8716 | #define VCN_MES_DC_APERTURE0_CNTL__BYPASS_MODE_MASK 0x00000010L |
8717 | //VCN_MES_DC_APERTURE1_BASE |
8718 | #define VCN_MES_DC_APERTURE1_BASE__BASE__SHIFT 0x0 |
8719 | #define VCN_MES_DC_APERTURE1_BASE__BASE_MASK 0xFFFFFFFFL |
8720 | //VCN_MES_DC_APERTURE1_MASK |
8721 | #define VCN_MES_DC_APERTURE1_MASK__MASK__SHIFT 0x0 |
8722 | #define VCN_MES_DC_APERTURE1_MASK__MASK_MASK 0xFFFFFFFFL |
8723 | //VCN_MES_DC_APERTURE1_CNTL |
8724 | #define VCN_MES_DC_APERTURE1_CNTL__VMID__SHIFT 0x0 |
8725 | #define VCN_MES_DC_APERTURE1_CNTL__BYPASS_MODE__SHIFT 0x4 |
8726 | #define VCN_MES_DC_APERTURE1_CNTL__VMID_MASK 0x0000000FL |
8727 | #define VCN_MES_DC_APERTURE1_CNTL__BYPASS_MODE_MASK 0x00000010L |
8728 | //VCN_MES_DC_APERTURE2_BASE |
8729 | #define VCN_MES_DC_APERTURE2_BASE__BASE__SHIFT 0x0 |
8730 | #define VCN_MES_DC_APERTURE2_BASE__BASE_MASK 0xFFFFFFFFL |
8731 | //VCN_MES_DC_APERTURE2_MASK |
8732 | #define VCN_MES_DC_APERTURE2_MASK__MASK__SHIFT 0x0 |
8733 | #define VCN_MES_DC_APERTURE2_MASK__MASK_MASK 0xFFFFFFFFL |
8734 | //VCN_MES_DC_APERTURE2_CNTL |
8735 | #define VCN_MES_DC_APERTURE2_CNTL__VMID__SHIFT 0x0 |
8736 | #define VCN_MES_DC_APERTURE2_CNTL__BYPASS_MODE__SHIFT 0x4 |
8737 | #define VCN_MES_DC_APERTURE2_CNTL__VMID_MASK 0x0000000FL |
8738 | #define VCN_MES_DC_APERTURE2_CNTL__BYPASS_MODE_MASK 0x00000010L |
8739 | //VCN_MES_DC_APERTURE3_BASE |
8740 | #define VCN_MES_DC_APERTURE3_BASE__BASE__SHIFT 0x0 |
8741 | #define VCN_MES_DC_APERTURE3_BASE__BASE_MASK 0xFFFFFFFFL |
8742 | //VCN_MES_DC_APERTURE3_MASK |
8743 | #define VCN_MES_DC_APERTURE3_MASK__MASK__SHIFT 0x0 |
8744 | #define VCN_MES_DC_APERTURE3_MASK__MASK_MASK 0xFFFFFFFFL |
8745 | //VCN_MES_DC_APERTURE3_CNTL |
8746 | #define VCN_MES_DC_APERTURE3_CNTL__VMID__SHIFT 0x0 |
8747 | #define VCN_MES_DC_APERTURE3_CNTL__BYPASS_MODE__SHIFT 0x4 |
8748 | #define VCN_MES_DC_APERTURE3_CNTL__VMID_MASK 0x0000000FL |
8749 | #define VCN_MES_DC_APERTURE3_CNTL__BYPASS_MODE_MASK 0x00000010L |
8750 | //VCN_MES_DC_APERTURE4_BASE |
8751 | #define VCN_MES_DC_APERTURE4_BASE__BASE__SHIFT 0x0 |
8752 | #define VCN_MES_DC_APERTURE4_BASE__BASE_MASK 0xFFFFFFFFL |
8753 | //VCN_MES_DC_APERTURE4_MASK |
8754 | #define VCN_MES_DC_APERTURE4_MASK__MASK__SHIFT 0x0 |
8755 | #define VCN_MES_DC_APERTURE4_MASK__MASK_MASK 0xFFFFFFFFL |
8756 | //VCN_MES_DC_APERTURE4_CNTL |
8757 | #define VCN_MES_DC_APERTURE4_CNTL__VMID__SHIFT 0x0 |
8758 | #define VCN_MES_DC_APERTURE4_CNTL__BYPASS_MODE__SHIFT 0x4 |
8759 | #define VCN_MES_DC_APERTURE4_CNTL__VMID_MASK 0x0000000FL |
8760 | #define VCN_MES_DC_APERTURE4_CNTL__BYPASS_MODE_MASK 0x00000010L |
8761 | //VCN_MES_DC_APERTURE5_BASE |
8762 | #define VCN_MES_DC_APERTURE5_BASE__BASE__SHIFT 0x0 |
8763 | #define VCN_MES_DC_APERTURE5_BASE__BASE_MASK 0xFFFFFFFFL |
8764 | //VCN_MES_DC_APERTURE5_MASK |
8765 | #define VCN_MES_DC_APERTURE5_MASK__MASK__SHIFT 0x0 |
8766 | #define VCN_MES_DC_APERTURE5_MASK__MASK_MASK 0xFFFFFFFFL |
8767 | //VCN_MES_DC_APERTURE5_CNTL |
8768 | #define VCN_MES_DC_APERTURE5_CNTL__VMID__SHIFT 0x0 |
8769 | #define VCN_MES_DC_APERTURE5_CNTL__BYPASS_MODE__SHIFT 0x4 |
8770 | #define VCN_MES_DC_APERTURE5_CNTL__VMID_MASK 0x0000000FL |
8771 | #define VCN_MES_DC_APERTURE5_CNTL__BYPASS_MODE_MASK 0x00000010L |
8772 | //VCN_MES_DC_APERTURE6_BASE |
8773 | #define VCN_MES_DC_APERTURE6_BASE__BASE__SHIFT 0x0 |
8774 | #define VCN_MES_DC_APERTURE6_BASE__BASE_MASK 0xFFFFFFFFL |
8775 | //VCN_MES_DC_APERTURE6_MASK |
8776 | #define VCN_MES_DC_APERTURE6_MASK__MASK__SHIFT 0x0 |
8777 | #define VCN_MES_DC_APERTURE6_MASK__MASK_MASK 0xFFFFFFFFL |
8778 | //VCN_MES_DC_APERTURE6_CNTL |
8779 | #define VCN_MES_DC_APERTURE6_CNTL__VMID__SHIFT 0x0 |
8780 | #define VCN_MES_DC_APERTURE6_CNTL__BYPASS_MODE__SHIFT 0x4 |
8781 | #define VCN_MES_DC_APERTURE6_CNTL__VMID_MASK 0x0000000FL |
8782 | #define VCN_MES_DC_APERTURE6_CNTL__BYPASS_MODE_MASK 0x00000010L |
8783 | //VCN_MES_DC_APERTURE7_BASE |
8784 | #define VCN_MES_DC_APERTURE7_BASE__BASE__SHIFT 0x0 |
8785 | #define VCN_MES_DC_APERTURE7_BASE__BASE_MASK 0xFFFFFFFFL |
8786 | //VCN_MES_DC_APERTURE7_MASK |
8787 | #define VCN_MES_DC_APERTURE7_MASK__MASK__SHIFT 0x0 |
8788 | #define VCN_MES_DC_APERTURE7_MASK__MASK_MASK 0xFFFFFFFFL |
8789 | //VCN_MES_DC_APERTURE7_CNTL |
8790 | #define VCN_MES_DC_APERTURE7_CNTL__VMID__SHIFT 0x0 |
8791 | #define VCN_MES_DC_APERTURE7_CNTL__BYPASS_MODE__SHIFT 0x4 |
8792 | #define VCN_MES_DC_APERTURE7_CNTL__VMID_MASK 0x0000000FL |
8793 | #define VCN_MES_DC_APERTURE7_CNTL__BYPASS_MODE_MASK 0x00000010L |
8794 | //VCN_MES_DC_APERTURE8_BASE |
8795 | #define VCN_MES_DC_APERTURE8_BASE__BASE__SHIFT 0x0 |
8796 | #define VCN_MES_DC_APERTURE8_BASE__BASE_MASK 0xFFFFFFFFL |
8797 | //VCN_MES_DC_APERTURE8_MASK |
8798 | #define VCN_MES_DC_APERTURE8_MASK__MASK__SHIFT 0x0 |
8799 | #define VCN_MES_DC_APERTURE8_MASK__MASK_MASK 0xFFFFFFFFL |
8800 | //VCN_MES_DC_APERTURE8_CNTL |
8801 | #define VCN_MES_DC_APERTURE8_CNTL__VMID__SHIFT 0x0 |
8802 | #define VCN_MES_DC_APERTURE8_CNTL__BYPASS_MODE__SHIFT 0x4 |
8803 | #define VCN_MES_DC_APERTURE8_CNTL__VMID_MASK 0x0000000FL |
8804 | #define VCN_MES_DC_APERTURE8_CNTL__BYPASS_MODE_MASK 0x00000010L |
8805 | //VCN_MES_DC_APERTURE9_BASE |
8806 | #define VCN_MES_DC_APERTURE9_BASE__BASE__SHIFT 0x0 |
8807 | #define VCN_MES_DC_APERTURE9_BASE__BASE_MASK 0xFFFFFFFFL |
8808 | //VCN_MES_DC_APERTURE9_MASK |
8809 | #define VCN_MES_DC_APERTURE9_MASK__MASK__SHIFT 0x0 |
8810 | #define VCN_MES_DC_APERTURE9_MASK__MASK_MASK 0xFFFFFFFFL |
8811 | //VCN_MES_DC_APERTURE9_CNTL |
8812 | #define VCN_MES_DC_APERTURE9_CNTL__VMID__SHIFT 0x0 |
8813 | #define VCN_MES_DC_APERTURE9_CNTL__BYPASS_MODE__SHIFT 0x4 |
8814 | #define VCN_MES_DC_APERTURE9_CNTL__VMID_MASK 0x0000000FL |
8815 | #define VCN_MES_DC_APERTURE9_CNTL__BYPASS_MODE_MASK 0x00000010L |
8816 | //VCN_MES_DC_APERTURE10_BASE |
8817 | #define VCN_MES_DC_APERTURE10_BASE__BASE__SHIFT 0x0 |
8818 | #define VCN_MES_DC_APERTURE10_BASE__BASE_MASK 0xFFFFFFFFL |
8819 | //VCN_MES_DC_APERTURE10_MASK |
8820 | #define VCN_MES_DC_APERTURE10_MASK__MASK__SHIFT 0x0 |
8821 | #define VCN_MES_DC_APERTURE10_MASK__MASK_MASK 0xFFFFFFFFL |
8822 | //VCN_MES_DC_APERTURE10_CNTL |
8823 | #define VCN_MES_DC_APERTURE10_CNTL__VMID__SHIFT 0x0 |
8824 | #define VCN_MES_DC_APERTURE10_CNTL__BYPASS_MODE__SHIFT 0x4 |
8825 | #define VCN_MES_DC_APERTURE10_CNTL__VMID_MASK 0x0000000FL |
8826 | #define VCN_MES_DC_APERTURE10_CNTL__BYPASS_MODE_MASK 0x00000010L |
8827 | //VCN_MES_DC_APERTURE11_BASE |
8828 | #define VCN_MES_DC_APERTURE11_BASE__BASE__SHIFT 0x0 |
8829 | #define VCN_MES_DC_APERTURE11_BASE__BASE_MASK 0xFFFFFFFFL |
8830 | //VCN_MES_DC_APERTURE11_MASK |
8831 | #define VCN_MES_DC_APERTURE11_MASK__MASK__SHIFT 0x0 |
8832 | #define VCN_MES_DC_APERTURE11_MASK__MASK_MASK 0xFFFFFFFFL |
8833 | //VCN_MES_DC_APERTURE11_CNTL |
8834 | #define VCN_MES_DC_APERTURE11_CNTL__VMID__SHIFT 0x0 |
8835 | #define VCN_MES_DC_APERTURE11_CNTL__BYPASS_MODE__SHIFT 0x4 |
8836 | #define VCN_MES_DC_APERTURE11_CNTL__VMID_MASK 0x0000000FL |
8837 | #define VCN_MES_DC_APERTURE11_CNTL__BYPASS_MODE_MASK 0x00000010L |
8838 | //VCN_MES_DC_APERTURE12_BASE |
8839 | #define VCN_MES_DC_APERTURE12_BASE__BASE__SHIFT 0x0 |
8840 | #define VCN_MES_DC_APERTURE12_BASE__BASE_MASK 0xFFFFFFFFL |
8841 | //VCN_MES_DC_APERTURE12_MASK |
8842 | #define VCN_MES_DC_APERTURE12_MASK__MASK__SHIFT 0x0 |
8843 | #define VCN_MES_DC_APERTURE12_MASK__MASK_MASK 0xFFFFFFFFL |
8844 | //VCN_MES_DC_APERTURE12_CNTL |
8845 | #define VCN_MES_DC_APERTURE12_CNTL__VMID__SHIFT 0x0 |
8846 | #define VCN_MES_DC_APERTURE12_CNTL__BYPASS_MODE__SHIFT 0x4 |
8847 | #define VCN_MES_DC_APERTURE12_CNTL__VMID_MASK 0x0000000FL |
8848 | #define VCN_MES_DC_APERTURE12_CNTL__BYPASS_MODE_MASK 0x00000010L |
8849 | //VCN_MES_DC_APERTURE13_BASE |
8850 | #define VCN_MES_DC_APERTURE13_BASE__BASE__SHIFT 0x0 |
8851 | #define VCN_MES_DC_APERTURE13_BASE__BASE_MASK 0xFFFFFFFFL |
8852 | //VCN_MES_DC_APERTURE13_MASK |
8853 | #define VCN_MES_DC_APERTURE13_MASK__MASK__SHIFT 0x0 |
8854 | #define VCN_MES_DC_APERTURE13_MASK__MASK_MASK 0xFFFFFFFFL |
8855 | //VCN_MES_DC_APERTURE13_CNTL |
8856 | #define VCN_MES_DC_APERTURE13_CNTL__VMID__SHIFT 0x0 |
8857 | #define VCN_MES_DC_APERTURE13_CNTL__BYPASS_MODE__SHIFT 0x4 |
8858 | #define VCN_MES_DC_APERTURE13_CNTL__VMID_MASK 0x0000000FL |
8859 | #define VCN_MES_DC_APERTURE13_CNTL__BYPASS_MODE_MASK 0x00000010L |
8860 | //VCN_MES_DC_APERTURE14_BASE |
8861 | #define VCN_MES_DC_APERTURE14_BASE__BASE__SHIFT 0x0 |
8862 | #define VCN_MES_DC_APERTURE14_BASE__BASE_MASK 0xFFFFFFFFL |
8863 | //VCN_MES_DC_APERTURE14_MASK |
8864 | #define VCN_MES_DC_APERTURE14_MASK__MASK__SHIFT 0x0 |
8865 | #define VCN_MES_DC_APERTURE14_MASK__MASK_MASK 0xFFFFFFFFL |
8866 | //VCN_MES_DC_APERTURE14_CNTL |
8867 | #define VCN_MES_DC_APERTURE14_CNTL__VMID__SHIFT 0x0 |
8868 | #define VCN_MES_DC_APERTURE14_CNTL__BYPASS_MODE__SHIFT 0x4 |
8869 | #define VCN_MES_DC_APERTURE14_CNTL__VMID_MASK 0x0000000FL |
8870 | #define VCN_MES_DC_APERTURE14_CNTL__BYPASS_MODE_MASK 0x00000010L |
8871 | //VCN_MES_DC_APERTURE15_BASE |
8872 | #define VCN_MES_DC_APERTURE15_BASE__BASE__SHIFT 0x0 |
8873 | #define VCN_MES_DC_APERTURE15_BASE__BASE_MASK 0xFFFFFFFFL |
8874 | //VCN_MES_DC_APERTURE15_MASK |
8875 | #define VCN_MES_DC_APERTURE15_MASK__MASK__SHIFT 0x0 |
8876 | #define VCN_MES_DC_APERTURE15_MASK__MASK_MASK 0xFFFFFFFFL |
8877 | //VCN_MES_DC_APERTURE15_CNTL |
8878 | #define VCN_MES_DC_APERTURE15_CNTL__VMID__SHIFT 0x0 |
8879 | #define VCN_MES_DC_APERTURE15_CNTL__BYPASS_MODE__SHIFT 0x4 |
8880 | #define VCN_MES_DC_APERTURE15_CNTL__VMID_MASK 0x0000000FL |
8881 | #define VCN_MES_DC_APERTURE15_CNTL__BYPASS_MODE_MASK 0x00000010L |
8882 | |
8883 | //VCN_HYP_ME1_PIPE0_VMID_CNTL |
8884 | #define VCN_HYP_ME1_PIPE0_VMID_CNTL__VMID_ALLOWED_MASK__SHIFT 0x0 |
8885 | #define VCN_HYP_ME1_PIPE0_VMID_CNTL__VMID_DEFAULT__SHIFT 0x10 |
8886 | #define VCN_HYP_ME1_PIPE0_VMID_CNTL__VMID_ALLOWED_MASK_MASK 0x0000FFFFL |
8887 | #define VCN_HYP_ME1_PIPE0_VMID_CNTL__VMID_DEFAULT_MASK 0x000F0000L |
8888 | //VCN_HYP_ME1_PIPE1_VMID_CNTL |
8889 | #define VCN_HYP_ME1_PIPE1_VMID_CNTL__VMID_ALLOWED_MASK__SHIFT 0x0 |
8890 | #define VCN_HYP_ME1_PIPE1_VMID_CNTL__VMID_DEFAULT__SHIFT 0x10 |
8891 | #define VCN_HYP_ME1_PIPE1_VMID_CNTL__VMID_ALLOWED_MASK_MASK 0x0000FFFFL |
8892 | #define VCN_HYP_ME1_PIPE1_VMID_CNTL__VMID_DEFAULT_MASK 0x000F0000L |
8893 | //VCN_MES_IC_BASE_LO |
8894 | #define VCN_MES_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc |
8895 | #define VCN_MES_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L |
8896 | //VCN_MES_MIBASE_LO |
8897 | #define VCN_MES_MIBASE_LO__IC_BASE_LO__SHIFT 0xc |
8898 | #define VCN_MES_MIBASE_LO__IC_BASE_LO_MASK 0xFFFFF000L |
8899 | //VCN_MES_IC_BASE_HI |
8900 | #define VCN_MES_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 |
8901 | #define VCN_MES_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL |
8902 | //VCN_MES_MIBASE_HI |
8903 | #define VCN_MES_MIBASE_HI__IC_BASE_HI__SHIFT 0x0 |
8904 | #define VCN_MES_MIBASE_HI__IC_BASE_HI_MASK 0x0000FFFFL |
8905 | //VCN_MES_IC_BASE_CNTL |
8906 | #define VCN_MES_IC_BASE_CNTL__VMID__SHIFT 0x0 |
8907 | #define VCN_MES_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 |
8908 | #define VCN_MES_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 |
8909 | #define VCN_MES_IC_BASE_CNTL__VMID_MASK 0x0000000FL |
8910 | #define VCN_MES_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L |
8911 | #define VCN_MES_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L |
8912 | //VCN_MES_DC_BASE_LO |
8913 | #define VCN_MES_DC_BASE_LO__DC_BASE_LO__SHIFT 0x10 |
8914 | #define VCN_MES_DC_BASE_LO__DC_BASE_LO_MASK 0xFFFF0000L |
8915 | //VCN_MES_MDBASE_LO |
8916 | #define VCN_MES_MDBASE_LO__BASE_LO__SHIFT 0x10 |
8917 | #define VCN_MES_MDBASE_LO__BASE_LO_MASK 0xFFFF0000L |
8918 | //VCN_MES_DC_BASE_HI |
8919 | #define VCN_MES_DC_BASE_HI__DC_BASE_HI__SHIFT 0x0 |
8920 | #define VCN_MES_DC_BASE_HI__DC_BASE_HI_MASK 0x0000FFFFL |
8921 | //VCN_MES_MDBASE_HI |
8922 | #define VCN_MES_MDBASE_HI__BASE_HI__SHIFT 0x0 |
8923 | #define VCN_MES_MDBASE_HI__BASE_HI_MASK 0x0000FFFFL |
8924 | //VCN_MES_MIBOUND_LO |
8925 | #define VCN_MES_MIBOUND_LO__BOUND_LO__SHIFT 0x0 |
8926 | #define VCN_MES_MIBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL |
8927 | //VCN_MES_MIBOUND_HI |
8928 | #define VCN_MES_MIBOUND_HI__BOUND_HI__SHIFT 0x0 |
8929 | #define VCN_MES_MIBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL |
8930 | //VCN_MES_MDBOUND_LO |
8931 | #define VCN_MES_MDBOUND_LO__BOUND_LO__SHIFT 0x0 |
8932 | #define VCN_MES_MDBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL |
8933 | //VCN_MES_MDBOUND_HI |
8934 | #define VCN_MES_MDBOUND_HI__BOUND_HI__SHIFT 0x0 |
8935 | #define VCN_MES_MDBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL |
8936 | |
8937 | #endif |
8938 | |