1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __MES_API_DEF_H__
25#define __MES_API_DEF_H__
26
27#pragma pack(push, 4)
28
29#define MES_API_VERSION 1
30
31/* Driver submits one API(cmd) as a single Frame and this command size is same
32 * for all API to ease the debugging and parsing of ring buffer.
33 */
34enum { API_FRAME_SIZE_IN_DWORDS = 64 };
35
36/* To avoid command in scheduler context to be overwritten whenever multiple
37 * interrupts come in, this creates another queue.
38 */
39enum { API_NUMBER_OF_COMMAND_MAX = 32 };
40
41enum MES_API_TYPE {
42 MES_API_TYPE_SCHEDULER = 1,
43 MES_API_TYPE_MAX
44};
45
46enum MES_SCH_API_OPCODE {
47 MES_SCH_API_SET_HW_RSRC = 0,
48 MES_SCH_API_SET_SCHEDULING_CONFIG = 1, /* agreegated db, quantums, etc */
49 MES_SCH_API_ADD_QUEUE = 2,
50 MES_SCH_API_REMOVE_QUEUE = 3,
51 MES_SCH_API_PERFORM_YIELD = 4,
52 MES_SCH_API_SET_GANG_PRIORITY_LEVEL = 5,
53 MES_SCH_API_SUSPEND = 6,
54 MES_SCH_API_RESUME = 7,
55 MES_SCH_API_RESET = 8,
56 MES_SCH_API_SET_LOG_BUFFER = 9,
57 MES_SCH_API_CHANGE_GANG_PRORITY = 10,
58 MES_SCH_API_QUERY_SCHEDULER_STATUS = 11,
59 MES_SCH_API_PROGRAM_GDS = 12,
60 MES_SCH_API_SET_DEBUG_VMID = 13,
61 MES_SCH_API_MISC = 14,
62 MES_SCH_API_UPDATE_ROOT_PAGE_TABLE = 15,
63 MES_SCH_API_AMD_LOG = 16,
64 MES_SCH_API_MAX = 0xFF
65};
66
67union MES_API_HEADER {
68 struct {
69 uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */
70 uint32_t opcode : 8;
71 uint32_t dwsize : 8; /* including header */
72 uint32_t reserved : 12;
73 };
74
75 uint32_t u32All;
76};
77
78enum MES_AMD_PRIORITY_LEVEL {
79 AMD_PRIORITY_LEVEL_LOW = 0,
80 AMD_PRIORITY_LEVEL_NORMAL = 1,
81 AMD_PRIORITY_LEVEL_MEDIUM = 2,
82 AMD_PRIORITY_LEVEL_HIGH = 3,
83 AMD_PRIORITY_LEVEL_REALTIME = 4,
84 AMD_PRIORITY_NUM_LEVELS
85};
86
87enum MES_QUEUE_TYPE {
88 MES_QUEUE_TYPE_GFX,
89 MES_QUEUE_TYPE_COMPUTE,
90 MES_QUEUE_TYPE_SDMA,
91 MES_QUEUE_TYPE_MAX,
92};
93
94struct MES_API_STATUS {
95 uint64_t api_completion_fence_addr;
96 uint64_t api_completion_fence_value;
97};
98
99enum { MAX_COMPUTE_PIPES = 8 };
100enum { MAX_GFX_PIPES = 2 };
101enum { MAX_SDMA_PIPES = 2 };
102
103enum { MAX_COMPUTE_HQD_PER_PIPE = 8 };
104enum { MAX_GFX_HQD_PER_PIPE = 8 };
105enum { MAX_SDMA_HQD_PER_PIPE = 10 };
106
107enum { MAX_QUEUES_IN_A_GANG = 8 };
108
109enum VM_HUB_TYPE {
110 VM_HUB_TYPE_GC = 0,
111 VM_HUB_TYPE_MM = 1,
112 VM_HUB_TYPE_MAX,
113};
114
115enum { VMID_INVALID = 0xffff };
116
117enum { MAX_VMID_GCHUB = 16 };
118enum { MAX_VMID_MMHUB = 16 };
119
120enum MES_LOG_OPERATION {
121 MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0,
122 MES_LOG_OPERATION_QUEUE_NEW_WORK = 1,
123 MES_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT = 2,
124 MES_LOG_OPERATION_QUEUE_NO_MORE_WORK = 3,
125 MES_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT = 4,
126 MES_LOG_OPERATION_QUEUE_INVALID = 0xF,
127};
128
129enum MES_LOG_CONTEXT_STATE {
130 MES_LOG_CONTEXT_STATE_IDLE = 0,
131 MES_LOG_CONTEXT_STATE_RUNNING = 1,
132 MES_LOG_CONTEXT_STATE_READY = 2,
133 MES_LOG_CONTEXT_STATE_READY_STANDBY = 3,
134 MES_LOG_CONTEXT_STATE_INVALID = 0xF,
135};
136
137struct MES_LOG_CONTEXT_STATE_CHANGE {
138 void *h_context;
139 enum MES_LOG_CONTEXT_STATE new_context_state;
140};
141
142struct MES_LOG_QUEUE_NEW_WORK {
143 uint64_t h_queue;
144 uint64_t reserved;
145};
146
147struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT {
148 uint64_t h_queue;
149 uint64_t h_sync_object;
150};
151
152struct MES_LOG_QUEUE_NO_MORE_WORK {
153 uint64_t h_queue;
154 uint64_t reserved;
155};
156
157struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT {
158 uint64_t h_queue;
159 uint64_t h_sync_object;
160};
161
162struct MES_LOG_ENTRY_HEADER {
163 uint32_t first_free_entry_index;
164 uint32_t wraparound_count;
165 uint64_t number_of_entries;
166 uint64_t reserved[2];
167};
168
169struct MES_LOG_ENTRY_DATA {
170 uint64_t gpu_time_stamp;
171 uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */
172 uint32_t reserved_operation_type_bits;
173 union {
174 struct MES_LOG_CONTEXT_STATE_CHANGE context_state_change;
175 struct MES_LOG_QUEUE_NEW_WORK queue_new_work;
176 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object;
177 struct MES_LOG_QUEUE_NO_MORE_WORK queue_no_more_work;
178 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT queue_wait_sync_object;
179 uint64_t all[2];
180 };
181};
182
183struct MES_LOG_BUFFER {
184 struct MES_LOG_ENTRY_HEADER header;
185 struct MES_LOG_ENTRY_DATA entries[1];
186};
187
188enum MES_SWIP_TO_HWIP_DEF {
189 MES_MAX_HWIP_SEGMENT = 6,
190};
191
192union MESAPI_SET_HW_RESOURCES {
193 struct {
194 union MES_API_HEADER header;
195 uint32_t vmid_mask_mmhub;
196 uint32_t vmid_mask_gfxhub;
197 uint32_t gds_size;
198 uint32_t paging_vmid;
199 uint32_t compute_hqd_mask[MAX_COMPUTE_PIPES];
200 uint32_t gfx_hqd_mask[MAX_GFX_PIPES];
201 uint32_t sdma_hqd_mask[MAX_SDMA_PIPES];
202 uint32_t aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS];
203 uint64_t g_sch_ctx_gpu_mc_ptr;
204 uint64_t query_status_fence_gpu_mc_ptr;
205 uint32_t gc_base[MES_MAX_HWIP_SEGMENT];
206 uint32_t mmhub_base[MES_MAX_HWIP_SEGMENT];
207 uint32_t osssys_base[MES_MAX_HWIP_SEGMENT];
208 struct MES_API_STATUS api_status;
209 union {
210 struct {
211 uint32_t disable_reset : 1;
212 uint32_t use_different_vmid_compute : 1;
213 uint32_t disable_mes_log : 1;
214 uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1;
215 uint32_t apply_grbm_remote_register_dummy_read_wa : 1;
216 uint32_t second_gfx_pipe_enabled : 1;
217 uint32_t enable_level_process_quantum_check : 1;
218 uint32_t apply_cwsr_program_all_vmid_sq_shader_tba_registers_wa : 1;
219 uint32_t enable_mqd_active_poll : 1;
220 uint32_t disable_timer_int : 1;
221 uint32_t reserved : 22;
222 };
223 uint32_t uint32_t_all;
224 };
225 };
226
227 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
228};
229
230union MESAPI__ADD_QUEUE {
231 struct {
232 union MES_API_HEADER header;
233 uint32_t process_id;
234 uint64_t page_table_base_addr;
235 uint64_t process_va_start;
236 uint64_t process_va_end;
237 uint64_t process_quantum;
238 uint64_t process_context_addr;
239 uint64_t gang_quantum;
240 uint64_t gang_context_addr;
241 uint32_t inprocess_gang_priority;
242 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
243 uint32_t doorbell_offset;
244 uint64_t mqd_addr;
245 uint64_t wptr_addr;
246 uint64_t h_context;
247 uint64_t h_queue;
248 enum MES_QUEUE_TYPE queue_type;
249 uint32_t gds_base;
250 uint32_t gds_size;
251 uint32_t gws_base;
252 uint32_t gws_size;
253 uint32_t oa_mask;
254 uint64_t trap_handler_addr;
255 uint32_t vm_context_cntl;
256
257 struct {
258 uint32_t paging : 1;
259 uint32_t debug_vmid : 4;
260 uint32_t program_gds : 1;
261 uint32_t is_gang_suspended : 1;
262 uint32_t is_tmz_queue : 1;
263 uint32_t map_kiq_utility_queue : 1;
264 uint32_t reserved : 23;
265 };
266 struct MES_API_STATUS api_status;
267 };
268
269 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
270};
271
272union MESAPI__REMOVE_QUEUE {
273 struct {
274 union MES_API_HEADER header;
275 uint32_t doorbell_offset;
276 uint64_t gang_context_addr;
277
278 struct {
279 uint32_t unmap_legacy_gfx_queue : 1;
280 uint32_t unmap_kiq_utility_queue : 1;
281 uint32_t preempt_legacy_gfx_queue : 1;
282 uint32_t reserved : 29;
283 };
284 struct MES_API_STATUS api_status;
285
286 uint32_t pipe_id;
287 uint32_t queue_id;
288
289 uint64_t tf_addr;
290 uint32_t tf_data;
291 };
292
293 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
294};
295
296union MESAPI__SET_SCHEDULING_CONFIG {
297 struct {
298 union MES_API_HEADER header;
299 /* Grace period when preempting another priority band for this
300 * priority band. The value for idle priority band is ignored,
301 * as it never preempts other bands.
302 */
303 uint64_t grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS];
304 /* Default quantum for scheduling across processes within
305 * a priority band.
306 */
307 uint64_t process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS];
308 /* Default grace period for processes that preempt each other
309 * within a priority band.
310 */
311 uint64_t process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS];
312 /* For normal level this field specifies the target GPU
313 * percentage in situations when it's starved by the high level.
314 * Valid values are between 0 and 50, with the default being 10.
315 */
316 uint32_t normal_yield_percent;
317 struct MES_API_STATUS api_status;
318 };
319
320 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
321};
322
323union MESAPI__PERFORM_YIELD {
324 struct {
325 union MES_API_HEADER header;
326 uint32_t dummy;
327 struct MES_API_STATUS api_status;
328 };
329
330 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
331};
332
333union MESAPI__CHANGE_GANG_PRIORITY_LEVEL {
334 struct {
335 union MES_API_HEADER header;
336 uint32_t inprocess_gang_priority;
337 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
338 uint64_t gang_quantum;
339 uint64_t gang_context_addr;
340 struct MES_API_STATUS api_status;
341 };
342
343 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
344};
345
346union MESAPI__SUSPEND {
347 struct {
348 union MES_API_HEADER header;
349 /* false - suspend all gangs; true - specific gang */
350 struct {
351 uint32_t suspend_all_gangs : 1;
352 uint32_t reserved : 31;
353 };
354 /* gang_context_addr is valid only if suspend_all = false */
355 uint64_t gang_context_addr;
356
357 uint64_t suspend_fence_addr;
358 uint32_t suspend_fence_value;
359
360 struct MES_API_STATUS api_status;
361 };
362
363 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
364};
365
366union MESAPI__RESUME {
367 struct {
368 union MES_API_HEADER header;
369 /* false - resume all gangs; true - specified gang */
370 struct {
371 uint32_t resume_all_gangs : 1;
372 uint32_t reserved : 31;
373 };
374 /* valid only if resume_all_gangs = false */
375 uint64_t gang_context_addr;
376
377 struct MES_API_STATUS api_status;
378 };
379
380 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
381};
382
383union MESAPI__RESET {
384 struct {
385 union MES_API_HEADER header;
386
387 struct {
388 /* Only reset the queue given by doorbell_offset (not entire gang) */
389 uint32_t reset_queue_only : 1;
390 /* Hang detection first then reset any queues that are hung */
391 uint32_t hang_detect_then_reset : 1;
392 /* Only do hang detection (no reset) */
393 uint32_t hang_detect_only : 1;
394 /* Rest HP and LP kernel queues not managed by MES */
395 uint32_t reset_legacy_gfx : 1;
396 uint32_t reserved : 28;
397 };
398
399 uint64_t gang_context_addr;
400
401 /* valid only if reset_queue_only = true */
402 uint32_t doorbell_offset;
403
404 /* valid only if hang_detect_then_reset = true */
405 uint64_t doorbell_offset_addr;
406 enum MES_QUEUE_TYPE queue_type;
407
408 /* valid only if reset_legacy_gfx = true */
409 uint32_t pipe_id_lp;
410 uint32_t queue_id_lp;
411 uint32_t vmid_id_lp;
412 uint64_t mqd_mc_addr_lp;
413 uint32_t doorbell_offset_lp;
414 uint64_t wptr_addr_lp;
415
416 uint32_t pipe_id_hp;
417 uint32_t queue_id_hp;
418 uint32_t vmid_id_hp;
419 uint64_t mqd_mc_addr_hp;
420 uint32_t doorbell_offset_hp;
421 uint64_t wptr_addr_hp;
422
423 struct MES_API_STATUS api_status;
424 };
425
426 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
427};
428
429union MESAPI__SET_LOGGING_BUFFER {
430 struct {
431 union MES_API_HEADER header;
432 /* There are separate log buffers for each queue type */
433 enum MES_QUEUE_TYPE log_type;
434 /* Log buffer GPU Address */
435 uint64_t logging_buffer_addr;
436 /* number of entries in the log buffer */
437 uint32_t number_of_entries;
438 /* Entry index at which CPU interrupt needs to be signalled */
439 uint32_t interrupt_entry;
440
441 struct MES_API_STATUS api_status;
442 };
443
444 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
445};
446
447union MESAPI__QUERY_MES_STATUS {
448 struct {
449 union MES_API_HEADER header;
450 bool mes_healthy; /* 0 - not healthy, 1 - healthy */
451 struct MES_API_STATUS api_status;
452 };
453
454 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
455};
456
457union MESAPI__PROGRAM_GDS {
458 struct {
459 union MES_API_HEADER header;
460 uint64_t process_context_addr;
461 uint32_t gds_base;
462 uint32_t gds_size;
463 uint32_t gws_base;
464 uint32_t gws_size;
465 uint32_t oa_mask;
466 struct MES_API_STATUS api_status;
467 };
468
469 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
470};
471
472union MESAPI__SET_DEBUG_VMID {
473 struct {
474 union MES_API_HEADER header;
475 struct MES_API_STATUS api_status;
476 union {
477 struct {
478 uint32_t use_gds : 1;
479 uint32_t reserved : 31;
480 } flags;
481 uint32_t u32All;
482 };
483 uint32_t reserved;
484 uint32_t debug_vmid;
485 uint64_t process_context_addr;
486 uint64_t page_table_base_addr;
487 uint64_t process_va_start;
488 uint64_t process_va_end;
489 uint32_t gds_base;
490 uint32_t gds_size;
491 uint32_t gws_base;
492 uint32_t gws_size;
493 uint32_t oa_mask;
494 };
495
496 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
497};
498
499enum MESAPI_MISC_OPCODE {
500 MESAPI_MISC__MODIFY_REG,
501 MESAPI_MISC__INV_GART,
502 MESAPI_MISC__QUERY_STATUS,
503 MESAPI_MISC__MAX,
504};
505
506enum MODIFY_REG_SUBCODE {
507 MODIFY_REG__OVERWRITE,
508 MODIFY_REG__RMW_OR,
509 MODIFY_REG__RMW_AND,
510 MODIFY_REG__MAX,
511};
512
513enum { MISC_DATA_MAX_SIZE_IN_DWORDS = 20 };
514
515struct MODIFY_REG {
516 enum MODIFY_REG_SUBCODE subcode;
517 uint32_t reg_offset;
518 uint32_t reg_value;
519};
520
521struct INV_GART {
522 uint64_t inv_range_va_start;
523 uint64_t inv_range_size;
524};
525
526struct QUERY_STATUS {
527 uint32_t context_id;
528};
529
530union MESAPI__MISC {
531 struct {
532 union MES_API_HEADER header;
533 enum MESAPI_MISC_OPCODE opcode;
534 struct MES_API_STATUS api_status;
535
536 union {
537 struct MODIFY_REG modify_reg;
538 struct INV_GART inv_gart;
539 struct QUERY_STATUS query_status;
540 uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS];
541 };
542 };
543
544 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
545};
546
547union MESAPI__UPDATE_ROOT_PAGE_TABLE {
548 struct {
549 union MES_API_HEADER header;
550 uint64_t page_table_base_addr;
551 uint64_t process_context_addr;
552 struct MES_API_STATUS api_status;
553 };
554
555 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
556};
557
558union MESAPI_AMD_LOG {
559 struct {
560 union MES_API_HEADER header;
561 uint64_t p_buffer_memory;
562 uint64_t p_buffer_size_used;
563 struct MES_API_STATUS api_status;
564 };
565
566 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
567};
568
569#pragma pack(pop)
570#endif
571

source code of linux/drivers/gpu/drm/amd/include/mes_api_def.h