1 | /* |
2 | * Copyright 2017 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | |
24 | #ifndef SMU10_DRIVER_IF_H |
25 | #define SMU10_DRIVER_IF_H |
26 | |
27 | #define SMU10_DRIVER_IF_VERSION 0x6 |
28 | |
29 | #define NUM_DSPCLK_LEVELS 8 |
30 | |
31 | typedef struct { |
32 | int32_t value; |
33 | uint32_t numFractionalBits; |
34 | } FloatInIntFormat_t; |
35 | |
36 | typedef enum { |
37 | DSPCLK_DCEFCLK = 0, |
38 | DSPCLK_DISPCLK, |
39 | DSPCLK_PIXCLK, |
40 | DSPCLK_PHYCLK, |
41 | DSPCLK_COUNT, |
42 | } DSPCLK_e; |
43 | |
44 | typedef struct { |
45 | uint16_t Freq; |
46 | uint16_t Vid; |
47 | } DisplayClockTable_t; |
48 | |
49 | |
50 | typedef struct { |
51 | uint16_t MinClock; /* This is either DCFCLK or SOCCLK (in MHz) */ |
52 | uint16_t MaxClock; /* This is either DCFCLK or SOCCLK (in MHz) */ |
53 | uint16_t MinMclk; |
54 | uint16_t MaxMclk; |
55 | |
56 | uint8_t WmSetting; |
57 | uint8_t WmType; |
58 | uint8_t Padding[2]; |
59 | } WatermarkRowGeneric_t; |
60 | |
61 | #define NUM_WM_RANGES 4 |
62 | |
63 | typedef enum { |
64 | WM_SOCCLK = 0, |
65 | WM_DCFCLK, |
66 | WM_COUNT, |
67 | } WM_CLOCK_e; |
68 | |
69 | typedef struct { |
70 | WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; |
71 | uint32_t MmHubPadding[7]; |
72 | } Watermarks_t; |
73 | |
74 | typedef enum { |
75 | CUSTOM_DPM_SETTING_GFXCLK, |
76 | CUSTOM_DPM_SETTING_CCLK, |
77 | CUSTOM_DPM_SETTING_FCLK_CCX, |
78 | CUSTOM_DPM_SETTING_FCLK_GFX, |
79 | CUSTOM_DPM_SETTING_FCLK_STALLS, |
80 | CUSTOM_DPM_SETTING_LCLK, |
81 | CUSTOM_DPM_SETTING_COUNT, |
82 | } CUSTOM_DPM_SETTING_e; |
83 | |
84 | typedef struct { |
85 | uint8_t ActiveHystLimit; |
86 | uint8_t IdleHystLimit; |
87 | uint8_t FPS; |
88 | uint8_t MinActiveFreqType; |
89 | FloatInIntFormat_t MinActiveFreq; |
90 | FloatInIntFormat_t PD_Data_limit; |
91 | FloatInIntFormat_t PD_Data_time_constant; |
92 | FloatInIntFormat_t PD_Data_error_coeff; |
93 | FloatInIntFormat_t PD_Data_error_rate_coeff; |
94 | } DpmActivityMonitorCoeffExt_t; |
95 | |
96 | typedef struct { |
97 | DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT]; |
98 | } CustomDpmSettings_t; |
99 | |
100 | #define NUM_SOCCLK_DPM_LEVELS 8 |
101 | #define NUM_DCEFCLK_DPM_LEVELS 4 |
102 | #define NUM_FCLK_DPM_LEVELS 4 |
103 | #define NUM_MEMCLK_DPM_LEVELS 4 |
104 | |
105 | typedef struct { |
106 | uint32_t Freq; /* In MHz */ |
107 | uint32_t Vol; /* Millivolts with 2 fractional bits */ |
108 | } DpmClock_t; |
109 | |
110 | typedef struct { |
111 | DpmClock_t DcefClocks[NUM_DCEFCLK_DPM_LEVELS]; |
112 | DpmClock_t SocClocks[NUM_SOCCLK_DPM_LEVELS]; |
113 | DpmClock_t FClocks[NUM_FCLK_DPM_LEVELS]; |
114 | DpmClock_t MemClocks[NUM_MEMCLK_DPM_LEVELS]; |
115 | } DpmClocks_t; |
116 | |
117 | #endif |
118 | |