| 1 | /* |
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| 2 | * Copyright 2015 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | */ |
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| 23 | |
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| 24 | #ifndef DGPU_VI_PP_SMC_H |
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| 25 | #define DGPU_VI_PP_SMC_H |
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| 26 | |
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| 27 | |
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| 28 | #pragma pack(push, 1) |
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| 29 | |
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| 30 | #define PPSMC_MSG_SetGBDroopSettings ((uint16_t) 0x305) |
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| 31 | |
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| 32 | #define PPSMC_SWSTATE_FLAG_DC 0x01 |
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| 33 | #define PPSMC_SWSTATE_FLAG_UVD 0x02 |
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| 34 | #define PPSMC_SWSTATE_FLAG_VCE 0x04 |
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| 35 | |
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| 36 | #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00 |
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| 37 | #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01 |
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| 38 | #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff |
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| 39 | |
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| 40 | #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01 |
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| 41 | #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02 |
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| 42 | #define PPSMC_SYSTEMFLAG_GDDR5 0x04 |
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| 43 | |
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| 44 | #define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08 |
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| 45 | |
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| 46 | #define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10 |
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| 47 | #define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20 |
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| 48 | |
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| 49 | #define 0x07 |
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| 50 | #define 0x08 |
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| 51 | |
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| 52 | #define 0x00 |
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| 53 | #define 0x01 |
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| 54 | |
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| 55 | |
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| 56 | #define PPSMC_DPM2FLAGS_TDPCLMP 0x01 |
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| 57 | #define PPSMC_DPM2FLAGS_PWRSHFT 0x02 |
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| 58 | #define PPSMC_DPM2FLAGS_OCP 0x04 |
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| 59 | |
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| 60 | |
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| 61 | #define PPSMC_DISPLAY_WATERMARK_LOW 0 |
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| 62 | #define PPSMC_DISPLAY_WATERMARK_HIGH 1 |
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| 63 | |
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| 64 | |
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| 65 | #define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01 |
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| 66 | #define PPSMC_STATEFLAG_POWERBOOST 0x02 |
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| 67 | #define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04 |
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| 68 | #define PPSMC_STATEFLAG_POWERSHIFT 0x08 |
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| 69 | #define PPSMC_STATEFLAG_SLOW_READ_MARGIN 0x10 |
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| 70 | #define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20 |
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| 71 | #define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40 |
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| 72 | |
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| 73 | |
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| 74 | #define FDO_MODE_HARDWARE 0 |
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| 75 | #define FDO_MODE_PIECE_WISE_LINEAR 1 |
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| 76 | |
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| 77 | enum FAN_CONTROL { |
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| 78 | FAN_CONTROL_FUZZY, |
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| 79 | FAN_CONTROL_TABLE |
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| 80 | }; |
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| 81 | |
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| 82 | |
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| 83 | #define PPSMC_Result_OK ((uint16_t)0x01) |
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| 84 | #define PPSMC_Result_NoMore ((uint16_t)0x02) |
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| 85 | |
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| 86 | #define PPSMC_Result_NotNow ((uint16_t)0x03) |
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| 87 | #define PPSMC_Result_Failed ((uint16_t)0xFF) |
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| 88 | #define PPSMC_Result_UnknownCmd ((uint16_t)0xFE) |
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| 89 | #define PPSMC_Result_UnknownVT ((uint16_t)0xFD) |
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| 90 | |
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| 91 | typedef uint16_t PPSMC_Result; |
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| 92 | |
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| 93 | #define PPSMC_isERROR(x) ((uint16_t)0x80 & (x)) |
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| 94 | |
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| 95 | |
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| 96 | #define PPSMC_MSG_Halt ((uint16_t)0x10) |
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| 97 | #define PPSMC_MSG_Resume ((uint16_t)0x11) |
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| 98 | #define PPSMC_MSG_EnableDPMLevel ((uint16_t)0x12) |
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| 99 | #define PPSMC_MSG_ZeroLevelsDisabled ((uint16_t)0x13) |
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| 100 | #define PPSMC_MSG_OneLevelsDisabled ((uint16_t)0x14) |
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| 101 | #define PPSMC_MSG_TwoLevelsDisabled ((uint16_t)0x15) |
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| 102 | #define PPSMC_MSG_EnableThermalInterrupt ((uint16_t)0x16) |
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| 103 | #define PPSMC_MSG_RunningOnAC ((uint16_t)0x17) |
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| 104 | #define PPSMC_MSG_LevelUp ((uint16_t)0x18) |
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| 105 | #define PPSMC_MSG_LevelDown ((uint16_t)0x19) |
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| 106 | #define PPSMC_MSG_ResetDPMCounters ((uint16_t)0x1a) |
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| 107 | #define PPSMC_MSG_SwitchToSwState ((uint16_t)0x20) |
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| 108 | #define PPSMC_MSG_SwitchToSwStateLast ((uint16_t)0x3f) |
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| 109 | #define PPSMC_MSG_SwitchToInitialState ((uint16_t)0x40) |
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| 110 | #define PPSMC_MSG_NoForcedLevel ((uint16_t)0x41) |
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| 111 | #define PPSMC_MSG_ForceHigh ((uint16_t)0x42) |
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| 112 | #define PPSMC_MSG_ForceMediumOrHigh ((uint16_t)0x43) |
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| 113 | #define PPSMC_MSG_SwitchToMinimumPower ((uint16_t)0x51) |
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| 114 | #define PPSMC_MSG_ResumeFromMinimumPower ((uint16_t)0x52) |
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| 115 | #define PPSMC_MSG_EnableCac ((uint16_t)0x53) |
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| 116 | #define PPSMC_MSG_DisableCac ((uint16_t)0x54) |
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| 117 | #define PPSMC_DPMStateHistoryStart ((uint16_t)0x55) |
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| 118 | #define PPSMC_DPMStateHistoryStop ((uint16_t)0x56) |
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| 119 | #define PPSMC_CACHistoryStart ((uint16_t)0x57) |
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| 120 | #define PPSMC_CACHistoryStop ((uint16_t)0x58) |
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| 121 | #define PPSMC_TDPClampingActive ((uint16_t)0x59) |
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| 122 | #define PPSMC_TDPClampingInactive ((uint16_t)0x5A) |
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| 123 | #define PPSMC_StartFanControl ((uint16_t)0x5B) |
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| 124 | #define PPSMC_StopFanControl ((uint16_t)0x5C) |
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| 125 | #define PPSMC_NoDisplay ((uint16_t)0x5D) |
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| 126 | #define PPSMC_HasDisplay ((uint16_t)0x5E) |
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| 127 | #define PPSMC_MSG_UVDPowerOFF ((uint16_t)0x60) |
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| 128 | #define PPSMC_MSG_UVDPowerON ((uint16_t)0x61) |
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| 129 | #define PPSMC_MSG_EnableULV ((uint16_t)0x62) |
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| 130 | #define PPSMC_MSG_DisableULV ((uint16_t)0x63) |
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| 131 | #define PPSMC_MSG_EnterULV ((uint16_t)0x64) |
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| 132 | #define PPSMC_MSG_ExitULV ((uint16_t)0x65) |
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| 133 | #define PPSMC_PowerShiftActive ((uint16_t)0x6A) |
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| 134 | #define PPSMC_PowerShiftInactive ((uint16_t)0x6B) |
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| 135 | #define PPSMC_OCPActive ((uint16_t)0x6C) |
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| 136 | #define PPSMC_OCPInactive ((uint16_t)0x6D) |
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| 137 | #define PPSMC_CACLongTermAvgEnable ((uint16_t)0x6E) |
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| 138 | #define PPSMC_CACLongTermAvgDisable ((uint16_t)0x6F) |
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| 139 | #define PPSMC_MSG_InferredStateSweep_Start ((uint16_t)0x70) |
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| 140 | #define PPSMC_MSG_InferredStateSweep_Stop ((uint16_t)0x71) |
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| 141 | #define PPSMC_MSG_SwitchToLowestInfState ((uint16_t)0x72) |
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| 142 | #define PPSMC_MSG_SwitchToNonInfState ((uint16_t)0x73) |
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| 143 | #define PPSMC_MSG_AllStateSweep_Start ((uint16_t)0x74) |
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| 144 | #define PPSMC_MSG_AllStateSweep_Stop ((uint16_t)0x75) |
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| 145 | #define PPSMC_MSG_SwitchNextLowerInfState ((uint16_t)0x76) |
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| 146 | #define PPSMC_MSG_SwitchNextHigherInfState ((uint16_t)0x77) |
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| 147 | #define PPSMC_MSG_MclkRetrainingTest ((uint16_t)0x78) |
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| 148 | #define PPSMC_MSG_ForceTDPClamping ((uint16_t)0x79) |
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| 149 | #define PPSMC_MSG_CollectCAC_PowerCorreln ((uint16_t)0x7A) |
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| 150 | #define PPSMC_MSG_CollectCAC_WeightCalib ((uint16_t)0x7B) |
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| 151 | #define PPSMC_MSG_CollectCAC_SQonly ((uint16_t)0x7C) |
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| 152 | #define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0x7D) |
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| 153 | |
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| 154 | #define PPSMC_MSG_ExtremitiesTest_Start ((uint16_t)0x7E) |
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| 155 | #define PPSMC_MSG_ExtremitiesTest_Stop ((uint16_t)0x7F) |
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| 156 | #define PPSMC_FlushDataCache ((uint16_t)0x80) |
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| 157 | #define PPSMC_FlushInstrCache ((uint16_t)0x81) |
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| 158 | |
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| 159 | #define PPSMC_MSG_SetEnabledLevels ((uint16_t)0x82) |
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| 160 | #define PPSMC_MSG_SetForcedLevels ((uint16_t)0x83) |
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| 161 | |
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| 162 | #define PPSMC_MSG_ResetToDefaults ((uint16_t)0x84) |
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| 163 | |
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| 164 | #define PPSMC_MSG_SetForcedLevelsAndJump ((uint16_t)0x85) |
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| 165 | #define PPSMC_MSG_SetCACHistoryMode ((uint16_t)0x86) |
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| 166 | #define PPSMC_MSG_EnableDTE ((uint16_t)0x87) |
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| 167 | #define PPSMC_MSG_DisableDTE ((uint16_t)0x88) |
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| 168 | |
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| 169 | #define PPSMC_MSG_SmcSpaceSetAddress ((uint16_t)0x89) |
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| 170 | #define PPSM_MSG_SmcSpaceWriteDWordInc ((uint16_t)0x8A) |
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| 171 | #define PPSM_MSG_SmcSpaceWriteWordInc ((uint16_t)0x8B) |
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| 172 | #define PPSM_MSG_SmcSpaceWriteByteInc ((uint16_t)0x8C) |
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| 173 | |
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| 174 | #define PPSMC_MSG_BREAK ((uint16_t)0xF8) |
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| 175 | |
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| 176 | #define PPSMC_MSG_Test ((uint16_t) 0x100) |
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| 177 | #define PPSMC_MSG_DPM_Voltage_Pwrmgt ((uint16_t) 0x101) |
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| 178 | #define PPSMC_MSG_DPM_Config ((uint16_t) 0x102) |
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| 179 | #define PPSMC_MSG_PM_Controller_Start ((uint16_t) 0x103) |
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| 180 | #define PPSMC_MSG_DPM_ForceState ((uint16_t) 0x104) |
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| 181 | #define PPSMC_MSG_PG_PowerDownSIMD ((uint16_t) 0x105) |
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| 182 | #define PPSMC_MSG_PG_PowerUpSIMD ((uint16_t) 0x106) |
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| 183 | #define PPSMC_MSG_PM_Controller_Stop ((uint16_t) 0x107) |
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| 184 | #define PPSMC_MSG_PG_SIMD_Config ((uint16_t) 0x108) |
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| 185 | #define PPSMC_MSG_Voltage_Cntl_Enable ((uint16_t) 0x109) |
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| 186 | #define PPSMC_MSG_Thermal_Cntl_Enable ((uint16_t) 0x10a) |
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| 187 | #define PPSMC_MSG_Reset_Service ((uint16_t) 0x10b) |
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| 188 | #define PPSMC_MSG_VCEPowerOFF ((uint16_t) 0x10e) |
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| 189 | #define PPSMC_MSG_VCEPowerON ((uint16_t) 0x10f) |
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| 190 | #define PPSMC_MSG_DPM_Disable_VCE_HS ((uint16_t) 0x110) |
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| 191 | #define PPSMC_MSG_DPM_Enable_VCE_HS ((uint16_t) 0x111) |
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| 192 | #define PPSMC_MSG_DPM_N_LevelsDisabled ((uint16_t) 0x112) |
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| 193 | #define PPSMC_MSG_DCEPowerOFF ((uint16_t) 0x113) |
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| 194 | #define PPSMC_MSG_DCEPowerON ((uint16_t) 0x114) |
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| 195 | #define PPSMC_MSG_PCIE_DDIPowerDown ((uint16_t) 0x117) |
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| 196 | #define PPSMC_MSG_PCIE_DDIPowerUp ((uint16_t) 0x118) |
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| 197 | #define PPSMC_MSG_PCIE_CascadePLLPowerDown ((uint16_t) 0x119) |
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| 198 | #define PPSMC_MSG_PCIE_CascadePLLPowerUp ((uint16_t) 0x11a) |
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| 199 | #define PPSMC_MSG_SYSPLLPowerOff ((uint16_t) 0x11b) |
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| 200 | #define PPSMC_MSG_SYSPLLPowerOn ((uint16_t) 0x11c) |
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| 201 | #define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint16_t) 0x11d) |
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| 202 | #define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint16_t) 0x11e) |
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| 203 | #define PPSMC_MSG_DISPLAYPHYStatusNotify ((uint16_t) 0x11f) |
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| 204 | #define PPSMC_MSG_EnableBAPM ((uint16_t) 0x120) |
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| 205 | #define PPSMC_MSG_DisableBAPM ((uint16_t) 0x121) |
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| 206 | #define PPSMC_MSG_Spmi_Enable ((uint16_t) 0x122) |
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| 207 | #define PPSMC_MSG_Spmi_Timer ((uint16_t) 0x123) |
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| 208 | #define PPSMC_MSG_LCLK_DPM_Config ((uint16_t) 0x124) |
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| 209 | #define PPSMC_MSG_VddNB_Request ((uint16_t) 0x125) |
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| 210 | #define PPSMC_MSG_PCIE_DDIPhyPowerDown ((uint32_t) 0x126) |
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| 211 | #define PPSMC_MSG_PCIE_DDIPhyPowerUp ((uint32_t) 0x127) |
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| 212 | #define PPSMC_MSG_MCLKDPM_Config ((uint16_t) 0x128) |
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| 213 | |
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| 214 | #define PPSMC_MSG_UVDDPM_Config ((uint16_t) 0x129) |
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| 215 | #define PPSMC_MSG_VCEDPM_Config ((uint16_t) 0x12A) |
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| 216 | #define PPSMC_MSG_ACPDPM_Config ((uint16_t) 0x12B) |
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| 217 | #define PPSMC_MSG_SAMUDPM_Config ((uint16_t) 0x12C) |
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| 218 | #define PPSMC_MSG_UVDDPM_SetEnabledMask ((uint16_t) 0x12D) |
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| 219 | #define PPSMC_MSG_VCEDPM_SetEnabledMask ((uint16_t) 0x12E) |
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| 220 | #define PPSMC_MSG_ACPDPM_SetEnabledMask ((uint16_t) 0x12F) |
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| 221 | #define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130) |
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| 222 | #define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131) |
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| 223 | #define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132) |
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| 224 | #define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133) |
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| 225 | #define PPSMC_MSG_SetTDPLimit ((uint16_t) 0x134) |
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| 226 | #define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135) |
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| 227 | #define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136) |
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| 228 | #define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0x137) |
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| 229 | #define PPSMC_MSG_ACPPowerON ((uint16_t) 0x138) |
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| 230 | #define PPSMC_MSG_SAMPowerOFF ((uint16_t) 0x139) |
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| 231 | #define PPSMC_MSG_SAMPowerON ((uint16_t) 0x13a) |
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| 232 | #define PPSMC_MSG_SDMAPowerOFF ((uint16_t) 0x13b) |
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| 233 | #define PPSMC_MSG_SDMAPowerON ((uint16_t) 0x13c) |
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| 234 | #define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d) |
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| 235 | #define PPSMC_MSG_IOMMUPowerOFF ((uint16_t) 0x13e) |
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| 236 | #define PPSMC_MSG_IOMMUPowerON ((uint16_t) 0x13f) |
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| 237 | #define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0x140) |
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| 238 | #define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141) |
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| 239 | #define PPSMC_MSG_NBDPM_ForceNominal ((uint16_t) 0x142) |
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| 240 | #define PPSMC_MSG_NBDPM_ForcePerformance ((uint16_t) 0x143) |
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| 241 | #define PPSMC_MSG_NBDPM_UnForce ((uint16_t) 0x144) |
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| 242 | #define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145) |
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| 243 | #define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146) |
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| 244 | #define PPSMC_MSG_PCIeDPM_ForceLevel ((uint16_t) 0x147) |
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| 245 | #define PPSMC_MSG_PCIeDPM_UnForceLevel ((uint16_t) 0x148) |
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| 246 | #define PPSMC_MSG_EnableACDCGPIOInterrupt ((uint16_t) 0x149) |
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| 247 | #define PPSMC_MSG_EnableVRHotGPIOInterrupt ((uint16_t) 0x14a) |
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| 248 | #define PPSMC_MSG_SwitchToAC ((uint16_t) 0x14b) |
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| 249 | #define PPSMC_MSG_XDMAPowerOFF ((uint16_t) 0x14c) |
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| 250 | #define PPSMC_MSG_XDMAPowerON ((uint16_t) 0x14d) |
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| 251 | |
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| 252 | #define PPSMC_MSG_DPM_Enable ((uint16_t) 0x14e) |
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| 253 | #define PPSMC_MSG_DPM_Disable ((uint16_t) 0x14f) |
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| 254 | #define PPSMC_MSG_MCLKDPM_Enable ((uint16_t) 0x150) |
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| 255 | #define PPSMC_MSG_MCLKDPM_Disable ((uint16_t) 0x151) |
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| 256 | #define PPSMC_MSG_LCLKDPM_Enable ((uint16_t) 0x152) |
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| 257 | #define PPSMC_MSG_LCLKDPM_Disable ((uint16_t) 0x153) |
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| 258 | #define PPSMC_MSG_UVDDPM_Enable ((uint16_t) 0x154) |
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| 259 | #define PPSMC_MSG_UVDDPM_Disable ((uint16_t) 0x155) |
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| 260 | #define PPSMC_MSG_SAMUDPM_Enable ((uint16_t) 0x156) |
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| 261 | #define PPSMC_MSG_SAMUDPM_Disable ((uint16_t) 0x157) |
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| 262 | #define PPSMC_MSG_ACPDPM_Enable ((uint16_t) 0x158) |
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| 263 | #define PPSMC_MSG_ACPDPM_Disable ((uint16_t) 0x159) |
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| 264 | #define PPSMC_MSG_VCEDPM_Enable ((uint16_t) 0x15a) |
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| 265 | #define PPSMC_MSG_VCEDPM_Disable ((uint16_t) 0x15b) |
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| 266 | #define PPSMC_MSG_LCLKDPM_SetEnabledMask ((uint16_t) 0x15c) |
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| 267 | #define PPSMC_MSG_DPM_FPS_Mode ((uint16_t) 0x15d) |
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| 268 | #define PPSMC_MSG_DPM_Activity_Mode ((uint16_t) 0x15e) |
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| 269 | #define PPSMC_MSG_VddC_Request ((uint16_t) 0x15f) |
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| 270 | #define PPSMC_MSG_MCLKDPM_GetEnabledMask ((uint16_t) 0x160) |
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| 271 | #define PPSMC_MSG_LCLKDPM_GetEnabledMask ((uint16_t) 0x161) |
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| 272 | #define PPSMC_MSG_SCLKDPM_GetEnabledMask ((uint16_t) 0x162) |
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| 273 | #define PPSMC_MSG_UVDDPM_GetEnabledMask ((uint16_t) 0x163) |
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| 274 | #define PPSMC_MSG_SAMUDPM_GetEnabledMask ((uint16_t) 0x164) |
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| 275 | #define PPSMC_MSG_ACPDPM_GetEnabledMask ((uint16_t) 0x165) |
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| 276 | #define PPSMC_MSG_VCEDPM_GetEnabledMask ((uint16_t) 0x166) |
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| 277 | #define PPSMC_MSG_PCIeDPM_SetEnabledMask ((uint16_t) 0x167) |
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| 278 | #define PPSMC_MSG_PCIeDPM_GetEnabledMask ((uint16_t) 0x168) |
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| 279 | #define PPSMC_MSG_TDCLimitEnable ((uint16_t) 0x169) |
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| 280 | #define PPSMC_MSG_TDCLimitDisable ((uint16_t) 0x16a) |
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| 281 | #define PPSMC_MSG_DPM_AutoRotate_Mode ((uint16_t) 0x16b) |
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| 282 | #define PPSMC_MSG_DISPCLK_FROM_FCH ((uint16_t) 0x16c) |
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| 283 | #define PPSMC_MSG_DISPCLK_FROM_DFS ((uint16_t) 0x16d) |
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| 284 | #define PPSMC_MSG_DPREFCLK_FROM_FCH ((uint16_t) 0x16e) |
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| 285 | #define PPSMC_MSG_DPREFCLK_FROM_DFS ((uint16_t) 0x16f) |
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| 286 | #define PPSMC_MSG_PmStatusLogStart ((uint16_t) 0x170) |
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| 287 | #define PPSMC_MSG_PmStatusLogSample ((uint16_t) 0x171) |
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| 288 | #define PPSMC_MSG_SCLK_AutoDPM_ON ((uint16_t) 0x172) |
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| 289 | #define PPSMC_MSG_MCLK_AutoDPM_ON ((uint16_t) 0x173) |
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| 290 | #define PPSMC_MSG_LCLK_AutoDPM_ON ((uint16_t) 0x174) |
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| 291 | #define PPSMC_MSG_UVD_AutoDPM_ON ((uint16_t) 0x175) |
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| 292 | #define PPSMC_MSG_SAMU_AutoDPM_ON ((uint16_t) 0x176) |
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| 293 | #define PPSMC_MSG_ACP_AutoDPM_ON ((uint16_t) 0x177) |
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| 294 | #define PPSMC_MSG_VCE_AutoDPM_ON ((uint16_t) 0x178) |
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| 295 | #define PPSMC_MSG_PCIe_AutoDPM_ON ((uint16_t) 0x179) |
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| 296 | #define PPSMC_MSG_MASTER_AutoDPM_ON ((uint16_t) 0x17a) |
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| 297 | #define PPSMC_MSG_MASTER_AutoDPM_OFF ((uint16_t) 0x17b) |
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| 298 | #define PPSMC_MSG_DYNAMICDISPPHYPOWER ((uint16_t) 0x17c) |
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| 299 | #define PPSMC_MSG_CAC_COLLECTION_ON ((uint16_t) 0x17d) |
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| 300 | #define PPSMC_MSG_CAC_COLLECTION_OFF ((uint16_t) 0x17e) |
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| 301 | #define PPSMC_MSG_CAC_CORRELATION_ON ((uint16_t) 0x17f) |
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| 302 | #define PPSMC_MSG_CAC_CORRELATION_OFF ((uint16_t) 0x180) |
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| 303 | #define PPSMC_MSG_PM_STATUS_TO_DRAM_ON ((uint16_t) 0x181) |
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| 304 | #define PPSMC_MSG_PM_STATUS_TO_DRAM_OFF ((uint16_t) 0x182) |
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| 305 | #define PPSMC_MSG_ALLOW_LOWSCLK_INTERRUPT ((uint16_t) 0x184) |
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| 306 | #define PPSMC_MSG_PkgPwrLimitEnable ((uint16_t) 0x185) |
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| 307 | #define PPSMC_MSG_PkgPwrLimitDisable ((uint16_t) 0x186) |
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| 308 | #define PPSMC_MSG_PkgPwrSetLimit ((uint16_t) 0x187) |
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| 309 | #define PPSMC_MSG_OverDriveSetTargetTdp ((uint16_t) 0x188) |
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| 310 | #define PPSMC_MSG_SCLKDPM_FreezeLevel ((uint16_t) 0x189) |
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| 311 | #define PPSMC_MSG_SCLKDPM_UnfreezeLevel ((uint16_t) 0x18A) |
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| 312 | #define PPSMC_MSG_MCLKDPM_FreezeLevel ((uint16_t) 0x18B) |
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| 313 | #define PPSMC_MSG_MCLKDPM_UnfreezeLevel ((uint16_t) 0x18C) |
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| 314 | #define PPSMC_MSG_START_DRAM_LOGGING ((uint16_t) 0x18D) |
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| 315 | #define PPSMC_MSG_STOP_DRAM_LOGGING ((uint16_t) 0x18E) |
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| 316 | #define PPSMC_MSG_MASTER_DeepSleep_ON ((uint16_t) 0x18F) |
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| 317 | #define PPSMC_MSG_MASTER_DeepSleep_OFF ((uint16_t) 0x190) |
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| 318 | #define PPSMC_MSG_Remove_DC_Clamp ((uint16_t) 0x191) |
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| 319 | #define PPSMC_MSG_DisableACDCGPIOInterrupt ((uint16_t) 0x192) |
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| 320 | #define PPSMC_MSG_OverrideVoltageControl_SetVddc ((uint16_t) 0x193) |
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| 321 | #define PPSMC_MSG_OverrideVoltageControl_SetVddci ((uint16_t) 0x194) |
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| 322 | #define PPSMC_MSG_SetVidOffset_1 ((uint16_t) 0x195) |
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| 323 | #define PPSMC_MSG_SetVidOffset_2 ((uint16_t) 0x207) |
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| 324 | #define PPSMC_MSG_GetVidOffset_1 ((uint16_t) 0x196) |
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| 325 | #define PPSMC_MSG_GetVidOffset_2 ((uint16_t) 0x208) |
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| 326 | #define PPSMC_MSG_THERMAL_OVERDRIVE_Enable ((uint16_t) 0x197) |
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| 327 | #define PPSMC_MSG_THERMAL_OVERDRIVE_Disable ((uint16_t) 0x198) |
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| 328 | #define PPSMC_MSG_SetTjMax ((uint16_t) 0x199) |
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| 329 | #define PPSMC_MSG_SetFanPwmMax ((uint16_t) 0x19A) |
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| 330 | #define PPSMC_MSG_WaitForMclkSwitchFinish ((uint16_t) 0x19B) |
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| 331 | #define PPSMC_MSG_ENABLE_THERMAL_DPM ((uint16_t) 0x19C) |
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| 332 | #define PPSMC_MSG_DISABLE_THERMAL_DPM ((uint16_t) 0x19D) |
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| 333 | |
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| 334 | #define PPSMC_MSG_API_GetSclkFrequency ((uint16_t) 0x200) |
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| 335 | #define PPSMC_MSG_API_GetMclkFrequency ((uint16_t) 0x201) |
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| 336 | #define PPSMC_MSG_API_GetSclkBusy ((uint16_t) 0x202) |
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| 337 | #define PPSMC_MSG_API_GetMclkBusy ((uint16_t) 0x203) |
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| 338 | #define PPSMC_MSG_API_GetAsicPower ((uint16_t) 0x204) |
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| 339 | #define PPSMC_MSG_SetFanRpmMax ((uint16_t) 0x205) |
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| 340 | #define PPSMC_MSG_SetFanSclkTarget ((uint16_t) 0x206) |
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| 341 | #define PPSMC_MSG_SetFanMinPwm ((uint16_t) 0x209) |
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| 342 | #define PPSMC_MSG_SetFanTemperatureTarget ((uint16_t) 0x20A) |
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| 343 | |
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| 344 | #define PPSMC_MSG_BACO_StartMonitor ((uint16_t) 0x240) |
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| 345 | #define PPSMC_MSG_BACO_Cancel ((uint16_t) 0x241) |
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| 346 | #define PPSMC_MSG_EnableVddGfx ((uint16_t) 0x242) |
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| 347 | #define PPSMC_MSG_DisableVddGfx ((uint16_t) 0x243) |
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| 348 | #define PPSMC_MSG_UcodeAddressLow ((uint16_t) 0x244) |
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| 349 | #define PPSMC_MSG_UcodeAddressHigh ((uint16_t) 0x245) |
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| 350 | #define PPSMC_MSG_UcodeLoadStatus ((uint16_t) 0x246) |
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| 351 | |
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| 352 | #define PPSMC_MSG_DRV_DRAM_ADDR_HI ((uint16_t) 0x250) |
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| 353 | #define PPSMC_MSG_DRV_DRAM_ADDR_LO ((uint16_t) 0x251) |
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| 354 | #define PPSMC_MSG_SMU_DRAM_ADDR_HI ((uint16_t) 0x252) |
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| 355 | #define PPSMC_MSG_SMU_DRAM_ADDR_LO ((uint16_t) 0x253) |
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| 356 | #define PPSMC_MSG_LoadUcodes ((uint16_t) 0x254) |
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| 357 | #define PPSMC_MSG_PowerStateNotify ((uint16_t) 0x255) |
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| 358 | #define PPSMC_MSG_COND_EXEC_DRAM_ADDR_HI ((uint16_t) 0x256) |
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| 359 | #define PPSMC_MSG_COND_EXEC_DRAM_ADDR_LO ((uint16_t) 0x257) |
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| 360 | #define PPSMC_MSG_VBIOS_DRAM_ADDR_HI ((uint16_t) 0x258) |
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| 361 | #define PPSMC_MSG_VBIOS_DRAM_ADDR_LO ((uint16_t) 0x259) |
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| 362 | #define PPSMC_MSG_LoadVBios ((uint16_t) 0x25A) |
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| 363 | #define PPSMC_MSG_GetUcodeVersion ((uint16_t) 0x25B) |
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| 364 | #define DMCUSMC_MSG_PSREntry ((uint16_t) 0x25C) |
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| 365 | #define DMCUSMC_MSG_PSRExit ((uint16_t) 0x25D) |
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| 366 | #define PPSMC_MSG_EnableClockGatingFeature ((uint16_t) 0x260) |
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| 367 | #define PPSMC_MSG_DisableClockGatingFeature ((uint16_t) 0x261) |
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| 368 | #define PPSMC_MSG_IsDeviceRunning ((uint16_t) 0x262) |
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| 369 | #define PPSMC_MSG_LoadMetaData ((uint16_t) 0x263) |
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| 370 | #define PPSMC_MSG_TMON_AutoCaliberate_Enable ((uint16_t) 0x264) |
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| 371 | #define PPSMC_MSG_TMON_AutoCaliberate_Disable ((uint16_t) 0x265) |
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| 372 | #define PPSMC_MSG_GetTelemetry1Slope ((uint16_t) 0x266) |
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| 373 | #define PPSMC_MSG_GetTelemetry1Offset ((uint16_t) 0x267) |
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| 374 | #define PPSMC_MSG_GetTelemetry2Slope ((uint16_t) 0x268) |
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| 375 | #define PPSMC_MSG_GetTelemetry2Offset ((uint16_t) 0x269) |
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| 376 | #define PPSMC_MSG_EnableAvfs ((uint16_t) 0x26A) |
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| 377 | #define PPSMC_MSG_DisableAvfs ((uint16_t) 0x26B) |
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| 378 | |
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| 379 | #define PPSMC_MSG_PerformBtc ((uint16_t) 0x26C) |
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| 380 | #define PPSMC_MSG_LedConfig ((uint16_t) 0x274) |
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| 381 | #define PPSMC_MSG_VftTableIsValid ((uint16_t) 0x275) |
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| 382 | #define PPSMC_MSG_UseNewGPIOScheme ((uint16_t) 0x277) |
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| 383 | #define PPSMC_MSG_GetEnabledPsm ((uint16_t) 0x400) |
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| 384 | #define PPSMC_MSG_AgmStartPsm ((uint16_t) 0x401) |
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| 385 | #define PPSMC_MSG_AgmReadPsm ((uint16_t) 0x402) |
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| 386 | #define PPSMC_MSG_AgmResetPsm ((uint16_t) 0x403) |
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| 387 | #define PPSMC_MSG_ReadVftCell ((uint16_t) 0x404) |
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| 388 | |
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| 389 | #define PPSMC_MSG_ApplyAvfsCksOffVoltage ((uint16_t) 0x415) |
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| 390 | |
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| 391 | #define PPSMC_MSG_GFX_CU_PG_ENABLE ((uint16_t) 0x280) |
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| 392 | #define PPSMC_MSG_GFX_CU_PG_DISABLE ((uint16_t) 0x281) |
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| 393 | #define PPSMC_MSG_GetCurrPkgPwr ((uint16_t) 0x282) |
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| 394 | |
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| 395 | #define PPSMC_MSG_SetGpuPllDfsForSclk ((uint16_t) 0x300) |
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| 396 | #define PPSMC_MSG_Didt_Block_Function ((uint16_t) 0x301) |
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| 397 | #define PPSMC_MSG_EnableZeroRpm ((uint16_t) 0x302) |
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| 398 | |
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| 399 | #define PPSMC_MSG_SetVBITimeout ((uint16_t) 0x306) |
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| 400 | |
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| 401 | #define PPSMC_MSG_EnableFFC ((uint16_t) 0x307) |
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| 402 | #define PPSMC_MSG_DisableFFC ((uint16_t) 0x308) |
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| 403 | |
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| 404 | #define PPSMC_MSG_EnableDpmDidt ((uint16_t) 0x309) |
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| 405 | #define PPSMC_MSG_DisableDpmDidt ((uint16_t) 0x30A) |
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| 406 | #define PPSMC_MSG_EnableDpmMcBlackout ((uint16_t) 0x30B) |
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| 407 | #define PPSMC_MSG_DisableDpmMcBlackout ((uint16_t) 0x30C) |
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| 408 | |
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| 409 | #define PPSMC_MSG_EnableEDCController ((uint16_t) 0x316) |
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| 410 | #define PPSMC_MSG_DisableEDCController ((uint16_t) 0x317) |
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| 411 | |
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| 412 | #define PPSMC_MSG_SecureSRBMWrite ((uint16_t) 0x600) |
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| 413 | #define PPSMC_MSG_SecureSRBMRead ((uint16_t) 0x601) |
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| 414 | #define PPSMC_MSG_SetAddress ((uint16_t) 0x800) |
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| 415 | #define PPSMC_MSG_GetData ((uint16_t) 0x801) |
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| 416 | #define PPSMC_MSG_SetData ((uint16_t) 0x802) |
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| 417 | |
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| 418 | typedef uint16_t PPSMC_Msg; |
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| 419 | |
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| 420 | #define PPSMC_EVENT_STATUS_THERMAL 0x00000001 |
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| 421 | #define PPSMC_EVENT_STATUS_REGULATORHOT 0x00000002 |
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| 422 | #define PPSMC_EVENT_STATUS_DC 0x00000004 |
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| 423 | |
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| 424 | #pragma pack(pop) |
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| 425 | |
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| 426 | #endif |
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| 427 | |
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| 428 | |
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