| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. |
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| 4 | * Author: Liviu Dudau <Liviu.Dudau@arm.com> |
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| 5 | * |
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| 6 | * ARM Mali DP500/DP550/DP650 registers definition. |
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| 7 | */ |
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| 8 | |
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| 9 | #ifndef __MALIDP_REGS_H__ |
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| 10 | #define __MALIDP_REGS_H__ |
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| 11 | |
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| 12 | /* |
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| 13 | * abbreviations used: |
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| 14 | * - DC - display core (general settings) |
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| 15 | * - DE - display engine |
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| 16 | * - SE - scaling engine |
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| 17 | */ |
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| 18 | |
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| 19 | /* interrupt bit masks */ |
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| 20 | #define MALIDP_DE_IRQ_UNDERRUN (1 << 0) |
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| 21 | |
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| 22 | #define MALIDP500_DE_IRQ_AXI_ERR (1 << 4) |
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| 23 | #define MALIDP500_DE_IRQ_VSYNC (1 << 5) |
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| 24 | #define MALIDP500_DE_IRQ_PROG_LINE (1 << 6) |
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| 25 | #define MALIDP500_DE_IRQ_SATURATION (1 << 7) |
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| 26 | #define MALIDP500_DE_IRQ_CONF_VALID (1 << 8) |
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| 27 | #define MALIDP500_DE_IRQ_CONF_MODE (1 << 11) |
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| 28 | #define MALIDP500_DE_IRQ_CONF_ACTIVE (1 << 17) |
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| 29 | #define MALIDP500_DE_IRQ_PM_ACTIVE (1 << 18) |
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| 30 | #define MALIDP500_DE_IRQ_TESTMODE_ACTIVE (1 << 19) |
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| 31 | #define MALIDP500_DE_IRQ_FORCE_BLNK_ACTIVE (1 << 24) |
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| 32 | #define MALIDP500_DE_IRQ_AXI_BUSY (1 << 28) |
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| 33 | #define MALIDP500_DE_IRQ_GLOBAL (1 << 31) |
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| 34 | #define MALIDP500_SE_IRQ_CONF_MODE (1 << 0) |
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| 35 | #define MALIDP500_SE_IRQ_CONF_VALID (1 << 4) |
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| 36 | #define MALIDP500_SE_IRQ_INIT_BUSY (1 << 5) |
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| 37 | #define MALIDP500_SE_IRQ_AXI_ERROR (1 << 8) |
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| 38 | #define MALIDP500_SE_IRQ_OVERRUN (1 << 9) |
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| 39 | #define MALIDP500_SE_IRQ_PROG_LINE1 (1 << 12) |
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| 40 | #define MALIDP500_SE_IRQ_PROG_LINE2 (1 << 13) |
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| 41 | #define MALIDP500_SE_IRQ_CONF_ACTIVE (1 << 17) |
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| 42 | #define MALIDP500_SE_IRQ_PM_ACTIVE (1 << 18) |
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| 43 | #define MALIDP500_SE_IRQ_AXI_BUSY (1 << 28) |
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| 44 | #define MALIDP500_SE_IRQ_GLOBAL (1 << 31) |
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| 45 | |
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| 46 | #define MALIDP550_DE_IRQ_SATURATION (1 << 8) |
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| 47 | #define MALIDP550_DE_IRQ_VSYNC (1 << 12) |
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| 48 | #define MALIDP550_DE_IRQ_PROG_LINE (1 << 13) |
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| 49 | #define MALIDP550_DE_IRQ_AXI_ERR (1 << 16) |
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| 50 | #define MALIDP550_SE_IRQ_EOW (1 << 0) |
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| 51 | #define MALIDP550_SE_IRQ_AXI_ERR (1 << 16) |
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| 52 | #define MALIDP550_SE_IRQ_OVR (1 << 17) |
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| 53 | #define MALIDP550_SE_IRQ_IBSY (1 << 18) |
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| 54 | #define MALIDP550_DC_IRQ_CONF_VALID (1 << 0) |
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| 55 | #define MALIDP550_DC_IRQ_CONF_MODE (1 << 4) |
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| 56 | #define MALIDP550_DC_IRQ_CONF_ACTIVE (1 << 16) |
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| 57 | #define MALIDP550_DC_IRQ_DE (1 << 20) |
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| 58 | #define MALIDP550_DC_IRQ_SE (1 << 24) |
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| 59 | |
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| 60 | #define MALIDP650_DE_IRQ_DRIFT (1 << 4) |
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| 61 | #define MALIDP650_DE_IRQ_ACEV1 (1 << 17) |
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| 62 | #define MALIDP650_DE_IRQ_ACEV2 (1 << 18) |
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| 63 | #define MALIDP650_DE_IRQ_ACEG (1 << 19) |
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| 64 | #define MALIDP650_DE_IRQ_AXIEP (1 << 28) |
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| 65 | |
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| 66 | /* bit masks that are common between products */ |
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| 67 | #define MALIDP_CFG_VALID (1 << 0) |
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| 68 | #define MALIDP_DISP_FUNC_GAMMA (1 << 0) |
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| 69 | #define MALIDP_DISP_FUNC_CADJ (1 << 4) |
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| 70 | #define MALIDP_DISP_FUNC_ILACED (1 << 8) |
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| 71 | #define MALIDP_SCALE_ENGINE_EN (1 << 16) |
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| 72 | #define MALIDP_SE_MEMWRITE_EN (2 << 5) |
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| 73 | |
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| 74 | /* register offsets for IRQ management */ |
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| 75 | #define MALIDP_REG_STATUS 0x00000 |
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| 76 | #define MALIDP_REG_SETIRQ 0x00004 |
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| 77 | #define MALIDP_REG_MASKIRQ 0x00008 |
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| 78 | #define MALIDP_REG_CLEARIRQ 0x0000c |
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| 79 | |
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| 80 | /* register offsets */ |
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| 81 | #define MALIDP_DE_CORE_ID 0x00018 |
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| 82 | #define MALIDP_DE_DISPLAY_FUNC 0x00020 |
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| 83 | |
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| 84 | /* these offsets are relative to MALIDP5x0_TIMINGS_BASE */ |
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| 85 | #define MALIDP_DE_H_TIMINGS 0x0 |
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| 86 | #define MALIDP_DE_V_TIMINGS 0x4 |
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| 87 | #define MALIDP_DE_SYNC_WIDTH 0x8 |
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| 88 | #define MALIDP_DE_HV_ACTIVE 0xc |
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| 89 | |
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| 90 | /* Stride register offsets relative to Lx_BASE */ |
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| 91 | #define MALIDP_DE_LG_STRIDE 0x18 |
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| 92 | #define MALIDP_DE_LV_STRIDE0 0x18 |
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| 93 | #define MALIDP550_DE_LS_R1_STRIDE 0x28 |
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| 94 | |
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| 95 | /* macros to set values into registers */ |
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| 96 | #define MALIDP_DE_H_FRONTPORCH(x) (((x) & 0xfff) << 0) |
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| 97 | #define MALIDP_DE_H_BACKPORCH(x) (((x) & 0x3ff) << 16) |
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| 98 | #define MALIDP500_DE_V_FRONTPORCH(x) (((x) & 0xff) << 0) |
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| 99 | #define MALIDP550_DE_V_FRONTPORCH(x) (((x) & 0xfff) << 0) |
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| 100 | #define MALIDP_DE_V_BACKPORCH(x) (((x) & 0xff) << 16) |
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| 101 | #define MALIDP_DE_H_SYNCWIDTH(x) (((x) & 0x3ff) << 0) |
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| 102 | #define MALIDP_DE_V_SYNCWIDTH(x) (((x) & 0xff) << 16) |
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| 103 | #define MALIDP_DE_H_ACTIVE(x) (((x) & 0x1fff) << 0) |
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| 104 | #define MALIDP_DE_V_ACTIVE(x) (((x) & 0x1fff) << 16) |
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| 105 | |
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| 106 | #define MALIDP_PRODUCT_ID(__core_id) ((u32)(__core_id) >> 16) |
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| 107 | |
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| 108 | /* register offsets relative to MALIDP5x0_COEFFS_BASE */ |
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| 109 | #define MALIDP_COLOR_ADJ_COEF 0x00000 |
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| 110 | #define MALIDP_COEF_TABLE_ADDR 0x00030 |
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| 111 | #define MALIDP_COEF_TABLE_DATA 0x00034 |
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| 112 | |
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| 113 | /* Scaling engine registers and masks. */ |
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| 114 | #define MALIDP_SE_SCALING_EN (1 << 0) |
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| 115 | #define MALIDP_SE_ALPHA_EN (1 << 1) |
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| 116 | #define MALIDP_SE_ENH_MASK 3 |
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| 117 | #define MALIDP_SE_ENH(x) (((x) & MALIDP_SE_ENH_MASK) << 2) |
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| 118 | #define MALIDP_SE_RGBO_IF_EN (1 << 4) |
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| 119 | #define MALIDP550_SE_CTL_SEL_MASK 7 |
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| 120 | #define MALIDP550_SE_CTL_VCSEL(x) \ |
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| 121 | (((x) & MALIDP550_SE_CTL_SEL_MASK) << 20) |
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| 122 | #define MALIDP550_SE_CTL_HCSEL(x) \ |
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| 123 | (((x) & MALIDP550_SE_CTL_SEL_MASK) << 16) |
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| 124 | |
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| 125 | /* Blocks with offsets from SE_CONTROL register. */ |
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| 126 | #define MALIDP_SE_LAYER_CONTROL 0x14 |
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| 127 | #define MALIDP_SE_L0_IN_SIZE 0x00 |
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| 128 | #define MALIDP_SE_L0_OUT_SIZE 0x04 |
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| 129 | #define MALIDP_SE_SET_V_SIZE(x) (((x) & 0x1fff) << 16) |
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| 130 | #define MALIDP_SE_SET_H_SIZE(x) (((x) & 0x1fff) << 0) |
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| 131 | #define MALIDP_SE_SCALING_CONTROL 0x24 |
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| 132 | #define MALIDP_SE_H_INIT_PH 0x00 |
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| 133 | #define MALIDP_SE_H_DELTA_PH 0x04 |
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| 134 | #define MALIDP_SE_V_INIT_PH 0x08 |
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| 135 | #define MALIDP_SE_V_DELTA_PH 0x0c |
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| 136 | #define MALIDP_SE_COEFFTAB_ADDR 0x10 |
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| 137 | #define MALIDP_SE_COEFFTAB_ADDR_MASK 0x7f |
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| 138 | #define MALIDP_SE_V_COEFFTAB (1 << 8) |
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| 139 | #define MALIDP_SE_H_COEFFTAB (1 << 9) |
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| 140 | #define MALIDP_SE_SET_V_COEFFTAB_ADDR(x) \ |
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| 141 | (MALIDP_SE_V_COEFFTAB | ((x) & MALIDP_SE_COEFFTAB_ADDR_MASK)) |
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| 142 | #define MALIDP_SE_SET_H_COEFFTAB_ADDR(x) \ |
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| 143 | (MALIDP_SE_H_COEFFTAB | ((x) & MALIDP_SE_COEFFTAB_ADDR_MASK)) |
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| 144 | #define MALIDP_SE_COEFFTAB_DATA 0x14 |
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| 145 | #define MALIDP_SE_COEFFTAB_DATA_MASK 0x3fff |
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| 146 | #define MALIDP_SE_SET_COEFFTAB_DATA(x) \ |
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| 147 | ((x) & MALIDP_SE_COEFFTAB_DATA_MASK) |
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| 148 | /* Enhance coefficients register offset */ |
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| 149 | #define MALIDP_SE_IMAGE_ENH 0x3C |
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| 150 | /* ENH_LIMITS offset 0x0 */ |
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| 151 | #define MALIDP_SE_ENH_LOW_LEVEL 24 |
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| 152 | #define MALIDP_SE_ENH_HIGH_LEVEL 63 |
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| 153 | #define MALIDP_SE_ENH_LIMIT_MASK 0xfff |
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| 154 | #define MALIDP_SE_SET_ENH_LIMIT_LOW(x) \ |
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| 155 | ((x) & MALIDP_SE_ENH_LIMIT_MASK) |
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| 156 | #define MALIDP_SE_SET_ENH_LIMIT_HIGH(x) \ |
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| 157 | (((x) & MALIDP_SE_ENH_LIMIT_MASK) << 16) |
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| 158 | #define MALIDP_SE_ENH_COEFF0 0x04 |
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| 159 | |
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| 160 | |
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| 161 | /* register offsets relative to MALIDP5x0_SE_MEMWRITE_BASE */ |
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| 162 | #define MALIDP_MW_FORMAT 0x00000 |
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| 163 | #define MALIDP_MW_P1_STRIDE 0x00004 |
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| 164 | #define MALIDP_MW_P2_STRIDE 0x00008 |
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| 165 | #define MALIDP_MW_P1_PTR_LOW 0x0000c |
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| 166 | #define MALIDP_MW_P1_PTR_HIGH 0x00010 |
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| 167 | #define MALIDP_MW_P2_PTR_LOW 0x0002c |
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| 168 | #define MALIDP_MW_P2_PTR_HIGH 0x00030 |
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| 169 | |
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| 170 | /* register offsets and bits specific to DP500 */ |
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| 171 | #define MALIDP500_ADDR_SPACE_SIZE 0x01000 |
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| 172 | #define MALIDP500_DC_BASE 0x00000 |
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| 173 | #define MALIDP500_DC_CONTROL 0x0000c |
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| 174 | #define MALIDP500_DC_CONFIG_REQ (1 << 17) |
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| 175 | #define MALIDP500_HSYNCPOL (1 << 20) |
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| 176 | #define MALIDP500_VSYNCPOL (1 << 21) |
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| 177 | #define MALIDP500_DC_CLEAR_MASK 0x300fff |
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| 178 | #define MALIDP500_DE_LINE_COUNTER 0x00010 |
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| 179 | #define MALIDP500_DE_AXI_CONTROL 0x00014 |
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| 180 | #define MALIDP500_DE_SECURE_CTRL 0x0001c |
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| 181 | #define MALIDP500_DE_CHROMA_KEY 0x00024 |
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| 182 | #define MALIDP500_TIMINGS_BASE 0x00028 |
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| 183 | |
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| 184 | #define MALIDP500_CONFIG_3D 0x00038 |
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| 185 | #define MALIDP500_BGND_COLOR 0x0003c |
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| 186 | #define MALIDP500_OUTPUT_DEPTH 0x00044 |
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| 187 | #define MALIDP500_COEFFS_BASE 0x00078 |
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| 188 | |
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| 189 | /* |
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| 190 | * The YUV2RGB coefficients on the DP500 are not in the video layer's register |
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| 191 | * block. They belong in a separate block above the layer's registers, hence |
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| 192 | * the negative offset. |
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| 193 | */ |
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| 194 | #define MALIDP500_LV_YUV2RGB ((s16)(-0xB8)) |
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| 195 | #define MALIDP500_DE_LV_BASE 0x00100 |
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| 196 | #define MALIDP500_DE_LV_PTR_BASE 0x00124 |
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| 197 | #define MALIDP500_DE_LV_AD_CTRL 0x00400 |
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| 198 | #define MALIDP500_DE_LG1_BASE 0x00200 |
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| 199 | #define MALIDP500_DE_LG1_PTR_BASE 0x0021c |
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| 200 | #define MALIDP500_DE_LG1_AD_CTRL 0x0040c |
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| 201 | #define MALIDP500_DE_LG2_BASE 0x00300 |
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| 202 | #define MALIDP500_DE_LG2_PTR_BASE 0x0031c |
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| 203 | #define MALIDP500_DE_LG2_AD_CTRL 0x00418 |
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| 204 | #define MALIDP500_SE_BASE 0x00c00 |
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| 205 | #define MALIDP500_SE_CONTROL 0x00c0c |
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| 206 | #define MALIDP500_SE_MEMWRITE_OUT_SIZE 0x00c2c |
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| 207 | #define MALIDP500_SE_RGB_YUV_COEFFS 0x00C74 |
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| 208 | #define MALIDP500_SE_MEMWRITE_BASE 0x00e00 |
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| 209 | #define MALIDP500_DC_IRQ_BASE 0x00f00 |
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| 210 | #define MALIDP500_CONFIG_VALID 0x00f00 |
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| 211 | #define MALIDP500_CONFIG_ID 0x00fd4 |
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| 212 | |
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| 213 | /* |
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| 214 | * The quality of service (QoS) register on the DP500. RQOS register values |
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| 215 | * are driven by the ARQOS signal, using AXI transacations, dependent on the |
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| 216 | * FIFO input level. |
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| 217 | * The RQOS register can also set QoS levels for: |
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| 218 | * - RED_ARQOS @ A 4-bit signal value for close to underflow conditions |
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| 219 | * - GREEN_ARQOS @ A 4-bit signal value for normal conditions |
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| 220 | */ |
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| 221 | #define MALIDP500_RQOS_QUALITY 0x00500 |
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| 222 | |
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| 223 | /* register offsets and bits specific to DP550/DP650 */ |
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| 224 | #define MALIDP550_ADDR_SPACE_SIZE 0x10000 |
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| 225 | #define MALIDP550_DE_CONTROL 0x00010 |
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| 226 | #define MALIDP550_DE_LINE_COUNTER 0x00014 |
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| 227 | #define MALIDP550_DE_AXI_CONTROL 0x00018 |
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| 228 | #define MALIDP550_DE_QOS 0x0001c |
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| 229 | #define MALIDP550_TIMINGS_BASE 0x00030 |
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| 230 | #define MALIDP550_HSYNCPOL (1 << 12) |
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| 231 | #define MALIDP550_VSYNCPOL (1 << 28) |
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| 232 | |
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| 233 | #define MALIDP550_DE_DISP_SIDEBAND 0x00040 |
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| 234 | #define MALIDP550_DE_BGND_COLOR 0x00044 |
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| 235 | #define MALIDP550_DE_OUTPUT_DEPTH 0x0004c |
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| 236 | #define MALIDP550_COEFFS_BASE 0x00050 |
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| 237 | #define MALIDP550_LV_YUV2RGB 0x00084 |
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| 238 | #define MALIDP550_DE_LV1_BASE 0x00100 |
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| 239 | #define MALIDP550_DE_LV1_PTR_BASE 0x00124 |
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| 240 | #define MALIDP550_DE_LV1_AD_CTRL 0x001B8 |
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| 241 | #define MALIDP550_DE_LV2_BASE 0x00200 |
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| 242 | #define MALIDP550_DE_LV2_PTR_BASE 0x00224 |
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| 243 | #define MALIDP550_DE_LV2_AD_CTRL 0x002B8 |
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| 244 | #define MALIDP550_DE_LG_BASE 0x00300 |
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| 245 | #define MALIDP550_DE_LG_PTR_BASE 0x0031c |
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| 246 | #define MALIDP550_DE_LG_AD_CTRL 0x00330 |
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| 247 | #define MALIDP550_DE_LS_BASE 0x00400 |
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| 248 | #define MALIDP550_DE_LS_PTR_BASE 0x0042c |
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| 249 | #define MALIDP550_DE_PERF_BASE 0x00500 |
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| 250 | #define MALIDP550_SE_BASE 0x08000 |
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| 251 | #define MALIDP550_SE_CONTROL 0x08010 |
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| 252 | #define MALIDP550_SE_MEMWRITE_ONESHOT (1 << 7) |
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| 253 | #define MALIDP550_SE_MEMWRITE_OUT_SIZE 0x08030 |
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| 254 | #define MALIDP550_SE_RGB_YUV_COEFFS 0x08078 |
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| 255 | #define MALIDP550_SE_MEMWRITE_BASE 0x08100 |
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| 256 | #define MALIDP550_DC_BASE 0x0c000 |
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| 257 | #define MALIDP550_DC_CONTROL 0x0c010 |
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| 258 | #define MALIDP550_DC_CONFIG_REQ (1 << 16) |
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| 259 | #define MALIDP550_CONFIG_VALID 0x0c014 |
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| 260 | #define MALIDP550_CONFIG_ID 0x0ffd4 |
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| 261 | |
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| 262 | /* register offsets specific to DP650 */ |
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| 263 | #define MALIDP650_DE_LV_MMU_CTRL 0x000D0 |
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| 264 | #define MALIDP650_DE_LG_MMU_CTRL 0x00048 |
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| 265 | #define MALIDP650_DE_LS_MMU_CTRL 0x00078 |
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| 266 | |
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| 267 | /* bit masks to set the MMU control register */ |
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| 268 | #define MALIDP_MMU_CTRL_EN (1 << 0) |
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| 269 | #define MALIDP_MMU_CTRL_MODE (1 << 4) |
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| 270 | #define MALIDP_MMU_CTRL_PX_PS(x) (1 << (8 + (x))) |
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| 271 | #define MALIDP_MMU_CTRL_PP_NUM_REQ(x) (((x) & 0x7f) << 12) |
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| 272 | |
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| 273 | /* AFBC register offsets relative to MALIDPXXX_DE_LX_AD_CTRL */ |
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| 274 | /* The following register offsets are common for DP500, DP550 and DP650 */ |
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| 275 | #define MALIDP_AD_CROP_H 0x4 |
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| 276 | #define MALIDP_AD_CROP_V 0x8 |
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| 277 | #define MALIDP_AD_END_PTR_LOW 0xc |
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| 278 | #define MALIDP_AD_END_PTR_HIGH 0x10 |
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| 279 | |
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| 280 | /* AFBC decoder Registers */ |
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| 281 | #define MALIDP_AD_EN BIT(0) |
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| 282 | #define MALIDP_AD_YTR BIT(4) |
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| 283 | #define MALIDP_AD_BS BIT(8) |
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| 284 | #define MALIDP_AD_CROP_RIGHT_OFFSET 16 |
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| 285 | #define MALIDP_AD_CROP_BOTTOM_OFFSET 16 |
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| 286 | |
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| 287 | /* |
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| 288 | * Starting with DP550 the register map blocks has been standardised to the |
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| 289 | * following layout: |
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| 290 | * |
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| 291 | * Offset Block registers |
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| 292 | * 0x00000 Display Engine |
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| 293 | * 0x08000 Scaling Engine |
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| 294 | * 0x0c000 Display Core |
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| 295 | * 0x10000 Secure control |
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| 296 | * |
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| 297 | * The old DP500 IP mixes some DC with the DE registers, hence the need |
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| 298 | * for a mapping structure. |
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| 299 | */ |
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| 300 | |
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| 301 | #endif /* __MALIDP_REGS_H__ */ |
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| 302 | |
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