1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright (C) 2012 Russell King |
4 | * Rewritten from the dovefb driver, and Armada510 manuals. |
5 | */ |
6 | #ifndef ARMADA_HW_H |
7 | #define ARMADA_HW_H |
8 | |
9 | /* |
10 | * Note: the following registers are written from IRQ context: |
11 | * LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL |
12 | * LCD_SPU_DMA_START_ADDR_[YUV][01], LCD_SPU_DMA_PITCH_YC, |
13 | * LCD_SPU_DMA_PITCH_UV, LCD_SPU_DMA_OVSA_HPXL_VLN, |
14 | * LCD_SPU_DMA_HPXL_VLN, LCD_SPU_DZM_HPXL_VLN, LCD_SPU_DMA_CTRL0 |
15 | */ |
16 | enum { |
17 | LCD_SPU_ADV_REG = 0x0084, /* Armada 510 */ |
18 | LCD_SPU_DMA_START_ADDR_Y0 = 0x00c0, |
19 | LCD_SPU_DMA_START_ADDR_U0 = 0x00c4, |
20 | LCD_SPU_DMA_START_ADDR_V0 = 0x00c8, |
21 | LCD_CFG_DMA_START_ADDR_0 = 0x00cc, |
22 | LCD_SPU_DMA_START_ADDR_Y1 = 0x00d0, |
23 | LCD_SPU_DMA_START_ADDR_U1 = 0x00d4, |
24 | LCD_SPU_DMA_START_ADDR_V1 = 0x00d8, |
25 | LCD_CFG_DMA_START_ADDR_1 = 0x00dc, |
26 | LCD_SPU_DMA_PITCH_YC = 0x00e0, |
27 | LCD_SPU_DMA_PITCH_UV = 0x00e4, |
28 | LCD_SPU_DMA_OVSA_HPXL_VLN = 0x00e8, |
29 | LCD_SPU_DMA_HPXL_VLN = 0x00ec, |
30 | LCD_SPU_DZM_HPXL_VLN = 0x00f0, |
31 | LCD_CFG_GRA_START_ADDR0 = 0x00f4, |
32 | LCD_CFG_GRA_START_ADDR1 = 0x00f8, |
33 | LCD_CFG_GRA_PITCH = 0x00fc, |
34 | LCD_SPU_GRA_OVSA_HPXL_VLN = 0x0100, |
35 | LCD_SPU_GRA_HPXL_VLN = 0x0104, |
36 | LCD_SPU_GZM_HPXL_VLN = 0x0108, |
37 | LCD_SPU_HWC_OVSA_HPXL_VLN = 0x010c, |
38 | LCD_SPU_HWC_HPXL_VLN = 0x0110, |
39 | LCD_SPUT_V_H_TOTAL = 0x0114, |
40 | LCD_SPU_V_H_ACTIVE = 0x0118, |
41 | LCD_SPU_H_PORCH = 0x011c, |
42 | LCD_SPU_V_PORCH = 0x0120, |
43 | LCD_SPU_BLANKCOLOR = 0x0124, |
44 | LCD_SPU_ALPHA_COLOR1 = 0x0128, |
45 | LCD_SPU_ALPHA_COLOR2 = 0x012c, |
46 | LCD_SPU_COLORKEY_Y = 0x0130, |
47 | LCD_SPU_COLORKEY_U = 0x0134, |
48 | LCD_SPU_COLORKEY_V = 0x0138, |
49 | LCD_CFG_RDREG4F = 0x013c, /* Armada 510 */ |
50 | LCD_SPU_SPI_RXDATA = 0x0140, |
51 | LCD_SPU_ISA_RXDATA = 0x0144, |
52 | LCD_SPU_HWC_RDDAT = 0x0158, |
53 | LCD_SPU_GAMMA_RDDAT = 0x015c, |
54 | LCD_SPU_PALETTE_RDDAT = 0x0160, |
55 | LCD_SPU_IOPAD_IN = 0x0178, |
56 | LCD_CFG_RDREG5F = 0x017c, |
57 | LCD_SPU_SPI_CTRL = 0x0180, |
58 | LCD_SPU_SPI_TXDATA = 0x0184, |
59 | LCD_SPU_SMPN_CTRL = 0x0188, |
60 | LCD_SPU_DMA_CTRL0 = 0x0190, |
61 | LCD_SPU_DMA_CTRL1 = 0x0194, |
62 | LCD_SPU_SRAM_CTRL = 0x0198, |
63 | LCD_SPU_SRAM_WRDAT = 0x019c, |
64 | LCD_SPU_SRAM_PARA0 = 0x01a0, /* Armada 510 */ |
65 | LCD_SPU_SRAM_PARA1 = 0x01a4, |
66 | LCD_CFG_SCLK_DIV = 0x01a8, |
67 | LCD_SPU_CONTRAST = 0x01ac, |
68 | LCD_SPU_SATURATION = 0x01b0, |
69 | LCD_SPU_CBSH_HUE = 0x01b4, |
70 | LCD_SPU_DUMB_CTRL = 0x01b8, |
71 | LCD_SPU_IOPAD_CONTROL = 0x01bc, |
72 | LCD_SPU_IRQ_ENA = 0x01c0, |
73 | LCD_SPU_IRQ_ISR = 0x01c4, |
74 | }; |
75 | |
76 | /* For LCD_SPU_ADV_REG */ |
77 | enum { |
78 | ADV_VSYNC_L_OFF = 0xfff << 20, |
79 | ADV_GRACOLORKEY = 1 << 19, |
80 | ADV_VIDCOLORKEY = 1 << 18, |
81 | ADV_HWC32BLEND = 1 << 15, |
82 | ADV_HWC32ARGB = 1 << 14, |
83 | ADV_HWC32ENABLE = 1 << 13, |
84 | ADV_VSYNCOFFEN = 1 << 12, |
85 | ADV_VSYNC_H_OFF = 0xfff << 0, |
86 | }; |
87 | |
88 | /* LCD_CFG_RDREG4F - Armada 510 only */ |
89 | enum { |
90 | CFG_SRAM_WAIT = BIT(11), |
91 | CFG_SMPN_FASTTX = BIT(10), |
92 | CFG_DMA_ARB = BIT(9), |
93 | CFG_DMA_WM_EN = BIT(8), |
94 | CFG_DMA_WM_MASK = 0xff, |
95 | #define CFG_DMA_WM(x) ((x) & CFG_DMA_WM_MASK) |
96 | }; |
97 | |
98 | enum { |
99 | CFG_565 = 0, |
100 | CFG_1555 = 1, |
101 | CFG_888PACK = 2, |
102 | CFG_X888 = 3, |
103 | CFG_8888 = 4, |
104 | CFG_422PACK = 5, |
105 | CFG_422 = 6, |
106 | CFG_420 = 7, |
107 | CFG_PSEUDO4 = 9, |
108 | CFG_PSEUDO8 = 10, |
109 | CFG_SWAPRB = 1 << 4, |
110 | CFG_SWAPUV = 1 << 3, |
111 | CFG_SWAPYU = 1 << 2, |
112 | CFG_YUV2RGB = 1 << 1, |
113 | }; |
114 | |
115 | /* For LCD_SPU_DMA_CTRL0 */ |
116 | enum { |
117 | CFG_NOBLENDING = 1 << 31, |
118 | CFG_GAMMA_ENA = 1 << 30, |
119 | CFG_CBSH_ENA = 1 << 29, |
120 | CFG_PALETTE_ENA = 1 << 28, |
121 | CFG_ARBFAST_ENA = 1 << 27, |
122 | CFG_HWC_1BITMOD = 1 << 26, |
123 | CFG_HWC_1BITENA = 1 << 25, |
124 | CFG_HWC_ENA = 1 << 24, |
125 | CFG_DMAFORMAT = 0xf << 20, |
126 | #define CFG_DMA_FMT(x) ((x) << 20) |
127 | CFG_GRAFORMAT = 0xf << 16, |
128 | #define CFG_GRA_FMT(x) ((x) << 16) |
129 | #define CFG_GRA_MOD(x) ((x) << 8) |
130 | CFG_GRA_FTOGGLE = 1 << 15, |
131 | CFG_GRA_HSMOOTH = 1 << 14, |
132 | CFG_GRA_TSTMODE = 1 << 13, |
133 | CFG_GRA_ENA = 1 << 8, |
134 | #define CFG_DMA_MOD(x) ((x) << 0) |
135 | CFG_DMA_FTOGGLE = 1 << 7, |
136 | CFG_DMA_HSMOOTH = 1 << 6, |
137 | CFG_DMA_TSTMODE = 1 << 5, |
138 | CFG_DMA_ENA = 1 << 0, |
139 | }; |
140 | |
141 | enum { |
142 | CKMODE_DISABLE = 0, |
143 | CKMODE_Y = 1, |
144 | CKMODE_U = 2, |
145 | CKMODE_RGB = 3, |
146 | CKMODE_V = 4, |
147 | CKMODE_R = 5, |
148 | CKMODE_G = 6, |
149 | CKMODE_B = 7, |
150 | }; |
151 | |
152 | /* For LCD_SPU_DMA_CTRL1 */ |
153 | enum { |
154 | CFG_FRAME_TRIG = 1 << 31, |
155 | CFG_VSYNC_INV = 1 << 27, |
156 | CFG_CKMODE_MASK = 0x7 << 24, |
157 | #define CFG_CKMODE(x) ((x) << 24) |
158 | CFG_CARRY = 1 << 23, |
159 | CFG_GATED_CLK = 1 << 21, |
160 | CFG_PWRDN_ENA = 1 << 20, |
161 | CFG_DSCALE_MASK = 0x3 << 18, |
162 | CFG_DSCALE_NONE = 0x0 << 18, |
163 | CFG_DSCALE_HALF = 0x1 << 18, |
164 | CFG_DSCALE_QUAR = 0x2 << 18, |
165 | CFG_ALPHAM_MASK = 0x3 << 16, |
166 | CFG_ALPHAM_VIDEO = 0x0 << 16, |
167 | CFG_ALPHAM_GRA = 0x1 << 16, |
168 | CFG_ALPHAM_CFG = 0x2 << 16, |
169 | CFG_ALPHA_MASK = 0xff << 8, |
170 | #define CFG_ALPHA(x) ((x) << 8) |
171 | CFG_PIXCMD_MASK = 0xff, |
172 | }; |
173 | |
174 | /* For LCD_SPU_SRAM_CTRL */ |
175 | enum { |
176 | SRAM_READ = 0 << 14, |
177 | SRAM_WRITE = 2 << 14, |
178 | SRAM_INIT = 3 << 14, |
179 | SRAM_GAMMA_YR = 0x0 << 8, |
180 | SRAM_GAMMA_UG = 0x1 << 8, |
181 | SRAM_GAMMA_VB = 0x2 << 8, |
182 | SRAM_PALETTE = 0x3 << 8, |
183 | SRAM_HWC32_RAM1 = 0xc << 8, |
184 | SRAM_HWC32_RAM2 = 0xd << 8, |
185 | SRAM_HWC32_RAMR = SRAM_HWC32_RAM1, |
186 | SRAM_HWC32_RAMG = SRAM_HWC32_RAM2, |
187 | SRAM_HWC32_RAMB = 0xe << 8, |
188 | SRAM_HWC32_TRAN = 0xf << 8, |
189 | SRAM_HWC = 0xf << 8, |
190 | }; |
191 | |
192 | /* For LCD_SPU_SRAM_PARA1 */ |
193 | enum { |
194 | CFG_CSB_256x32 = 1 << 15, /* cursor */ |
195 | CFG_CSB_256x24 = 1 << 14, /* palette */ |
196 | CFG_CSB_256x8 = 1 << 13, /* gamma */ |
197 | CFG_PDWN1920x32 = 1 << 8, /* Armada 510: power down vscale ram */ |
198 | CFG_PDWN256x32 = 1 << 7, /* power down cursor */ |
199 | CFG_PDWN256x24 = 1 << 6, /* power down palette */ |
200 | CFG_PDWN256x8 = 1 << 5, /* power down gamma */ |
201 | CFG_PDWNHWC = 1 << 4, /* Armada 510: power down all hwc ram */ |
202 | CFG_PDWN32x32 = 1 << 3, /* power down slave->smart ram */ |
203 | CFG_PDWN16x66 = 1 << 2, /* power down UV fifo */ |
204 | CFG_PDWN32x66 = 1 << 1, /* power down Y fifo */ |
205 | CFG_PDWN64x66 = 1 << 0, /* power down graphic fifo */ |
206 | }; |
207 | |
208 | /* For LCD_CFG_SCLK_DIV */ |
209 | enum { |
210 | /* Armada 510 */ |
211 | SCLK_510_AXI = 0x0 << 30, |
212 | SCLK_510_EXTCLK0 = 0x1 << 30, |
213 | SCLK_510_PLL = 0x2 << 30, |
214 | SCLK_510_EXTCLK1 = 0x3 << 30, |
215 | SCLK_510_DIV_CHANGE = 1 << 29, |
216 | SCLK_510_FRAC_DIV_MASK = 0xfff << 16, |
217 | SCLK_510_INT_DIV_MASK = 0xffff << 0, |
218 | |
219 | /* Armada 16x */ |
220 | SCLK_16X_AHB = 0x0 << 28, |
221 | SCLK_16X_PCLK = 0x1 << 28, |
222 | SCLK_16X_AXI = 0x4 << 28, |
223 | SCLK_16X_PLL = 0x8 << 28, |
224 | SCLK_16X_FRAC_DIV_MASK = 0xfff << 16, |
225 | SCLK_16X_INT_DIV_MASK = 0xffff << 0, |
226 | }; |
227 | |
228 | /* For LCD_SPU_DUMB_CTRL */ |
229 | enum { |
230 | DUMB16_RGB565_0 = 0x0 << 28, |
231 | DUMB16_RGB565_1 = 0x1 << 28, |
232 | DUMB18_RGB666_0 = 0x2 << 28, |
233 | DUMB18_RGB666_1 = 0x3 << 28, |
234 | DUMB12_RGB444_0 = 0x4 << 28, |
235 | DUMB12_RGB444_1 = 0x5 << 28, |
236 | DUMB24_RGB888_0 = 0x6 << 28, |
237 | DUMB_BLANK = 0x7 << 28, |
238 | DUMB_MASK = 0xf << 28, |
239 | CFG_BIAS_OUT = 1 << 8, |
240 | CFG_REV_RGB = 1 << 7, |
241 | CFG_INV_CBLANK = 1 << 6, |
242 | CFG_INV_CSYNC = 1 << 5, /* Normally active high */ |
243 | CFG_INV_HENA = 1 << 4, |
244 | CFG_INV_VSYNC = 1 << 3, /* Normally active high */ |
245 | CFG_INV_HSYNC = 1 << 2, /* Normally active high */ |
246 | CFG_INV_PCLK = 1 << 1, |
247 | CFG_DUMB_ENA = 1 << 0, |
248 | }; |
249 | |
250 | /* For LCD_SPU_IOPAD_CONTROL */ |
251 | enum { |
252 | CFG_VSCALE_LN_EN = 3 << 18, |
253 | CFG_GRA_VM_ENA = 1 << 15, |
254 | CFG_DMA_VM_ENA = 1 << 13, |
255 | CFG_CMD_VM_ENA = 1 << 11, |
256 | CFG_CSC_MASK = 3 << 8, |
257 | CFG_CSC_YUV_CCIR709 = 1 << 9, |
258 | CFG_CSC_YUV_CCIR601 = 0 << 9, |
259 | CFG_CSC_RGB_STUDIO = 1 << 8, |
260 | CFG_CSC_RGB_COMPUTER = 0 << 8, |
261 | CFG_IOPAD_MASK = 0xf << 0, |
262 | CFG_IOPAD_DUMB24 = 0x0 << 0, |
263 | CFG_IOPAD_DUMB18SPI = 0x1 << 0, |
264 | CFG_IOPAD_DUMB18GPIO = 0x2 << 0, |
265 | CFG_IOPAD_DUMB16SPI = 0x3 << 0, |
266 | CFG_IOPAD_DUMB16GPIO = 0x4 << 0, |
267 | CFG_IOPAD_DUMB12GPIO = 0x5 << 0, |
268 | CFG_IOPAD_SMART18 = 0x6 << 0, |
269 | CFG_IOPAD_SMART16 = 0x7 << 0, |
270 | CFG_IOPAD_SMART8 = 0x8 << 0, |
271 | }; |
272 | |
273 | #define IOPAD_DUMB24 0x0 |
274 | |
275 | /* For LCD_SPU_IRQ_ENA */ |
276 | enum { |
277 | DMA_FRAME_IRQ0_ENA = 1 << 31, |
278 | DMA_FRAME_IRQ1_ENA = 1 << 30, |
279 | DMA_FRAME_IRQ_ENA = DMA_FRAME_IRQ0_ENA | DMA_FRAME_IRQ1_ENA, |
280 | DMA_FF_UNDERFLOW_ENA = 1 << 29, |
281 | GRA_FRAME_IRQ0_ENA = 1 << 27, |
282 | GRA_FRAME_IRQ1_ENA = 1 << 26, |
283 | GRA_FRAME_IRQ_ENA = GRA_FRAME_IRQ0_ENA | GRA_FRAME_IRQ1_ENA, |
284 | GRA_FF_UNDERFLOW_ENA = 1 << 25, |
285 | VSYNC_IRQ_ENA = 1 << 23, |
286 | DUMB_FRAMEDONE_ENA = 1 << 22, |
287 | TWC_FRAMEDONE_ENA = 1 << 21, |
288 | HWC_FRAMEDONE_ENA = 1 << 20, |
289 | SLV_IRQ_ENA = 1 << 19, |
290 | SPI_IRQ_ENA = 1 << 18, |
291 | PWRDN_IRQ_ENA = 1 << 17, |
292 | ERR_IRQ_ENA = 1 << 16, |
293 | CLEAN_SPU_IRQ_ISR = 0xffff, |
294 | }; |
295 | |
296 | /* For LCD_SPU_IRQ_ISR */ |
297 | enum { |
298 | DMA_FRAME_IRQ0 = 1 << 31, |
299 | DMA_FRAME_IRQ1 = 1 << 30, |
300 | DMA_FRAME_IRQ = DMA_FRAME_IRQ0 | DMA_FRAME_IRQ1, |
301 | DMA_FF_UNDERFLOW = 1 << 29, |
302 | GRA_FRAME_IRQ0 = 1 << 27, |
303 | GRA_FRAME_IRQ1 = 1 << 26, |
304 | GRA_FRAME_IRQ = GRA_FRAME_IRQ0 | GRA_FRAME_IRQ1, |
305 | GRA_FF_UNDERFLOW = 1 << 25, |
306 | VSYNC_IRQ = 1 << 23, |
307 | DUMB_FRAMEDONE = 1 << 22, |
308 | TWC_FRAMEDONE = 1 << 21, |
309 | HWC_FRAMEDONE = 1 << 20, |
310 | SLV_IRQ = 1 << 19, |
311 | SPI_IRQ = 1 << 18, |
312 | PWRDN_IRQ = 1 << 17, |
313 | ERR_IRQ = 1 << 16, |
314 | DMA_FRAME_IRQ0_LEVEL = 1 << 15, |
315 | DMA_FRAME_IRQ1_LEVEL = 1 << 14, |
316 | DMA_FRAME_CNT_ISR = 3 << 12, |
317 | GRA_FRAME_IRQ0_LEVEL = 1 << 11, |
318 | GRA_FRAME_IRQ1_LEVEL = 1 << 10, |
319 | GRA_FRAME_CNT_ISR = 3 << 8, |
320 | VSYNC_IRQ_LEVEL = 1 << 7, |
321 | DUMB_FRAMEDONE_LEVEL = 1 << 6, |
322 | TWC_FRAMEDONE_LEVEL = 1 << 5, |
323 | HWC_FRAMEDONE_LEVEL = 1 << 4, |
324 | SLV_FF_EMPTY = 1 << 3, |
325 | DMA_FF_ALLEMPTY = 1 << 2, |
326 | GRA_FF_ALLEMPTY = 1 << 1, |
327 | PWRDN_IRQ_LEVEL = 1 << 0, |
328 | }; |
329 | |
330 | #endif |
331 | |