1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright (C) 2014 Traphandler |
4 | * Copyright (C) 2014 Free Electrons |
5 | * Copyright (C) 2014 Atmel |
6 | * |
7 | * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com> |
8 | * Author: Boris BREZILLON <boris.brezillon@free-electrons.com> |
9 | */ |
10 | |
11 | #ifndef DRM_ATMEL_HLCDC_H |
12 | #define DRM_ATMEL_HLCDC_H |
13 | |
14 | #include <linux/regmap.h> |
15 | |
16 | #include <drm/drm_plane.h> |
17 | |
18 | #define ATMEL_HLCDC_LAYER_CHER 0x0 |
19 | #define ATMEL_HLCDC_LAYER_CHDR 0x4 |
20 | #define ATMEL_HLCDC_LAYER_CHSR 0x8 |
21 | #define ATMEL_HLCDC_LAYER_EN BIT(0) |
22 | #define ATMEL_HLCDC_LAYER_UPDATE BIT(1) |
23 | #define ATMEL_HLCDC_LAYER_A2Q BIT(2) |
24 | #define ATMEL_HLCDC_LAYER_RST BIT(8) |
25 | |
26 | #define ATMEL_HLCDC_LAYER_IER 0xc |
27 | #define ATMEL_HLCDC_LAYER_IDR 0x10 |
28 | #define ATMEL_HLCDC_LAYER_IMR 0x14 |
29 | #define ATMEL_HLCDC_LAYER_ISR 0x18 |
30 | #define ATMEL_HLCDC_LAYER_DFETCH BIT(0) |
31 | #define ATMEL_HLCDC_LAYER_LFETCH BIT(1) |
32 | #define ATMEL_HLCDC_LAYER_DMA_IRQ(p) BIT(2 + (8 * (p))) |
33 | #define ATMEL_HLCDC_LAYER_DSCR_IRQ(p) BIT(3 + (8 * (p))) |
34 | #define ATMEL_HLCDC_LAYER_ADD_IRQ(p) BIT(4 + (8 * (p))) |
35 | #define ATMEL_HLCDC_LAYER_DONE_IRQ(p) BIT(5 + (8 * (p))) |
36 | #define ATMEL_HLCDC_LAYER_OVR_IRQ(p) BIT(6 + (8 * (p))) |
37 | |
38 | #define ATMEL_HLCDC_LAYER_PLANE_HEAD(p) (((p) * 0x10) + 0x1c) |
39 | #define ATMEL_HLCDC_LAYER_PLANE_ADDR(p) (((p) * 0x10) + 0x20) |
40 | #define ATMEL_HLCDC_LAYER_PLANE_CTRL(p) (((p) * 0x10) + 0x24) |
41 | #define ATMEL_HLCDC_LAYER_PLANE_NEXT(p) (((p) * 0x10) + 0x28) |
42 | |
43 | #define ATMEL_HLCDC_LAYER_DMA_CFG 0 |
44 | #define ATMEL_HLCDC_LAYER_DMA_SIF BIT(0) |
45 | #define ATMEL_HLCDC_LAYER_DMA_BLEN_MASK GENMASK(5, 4) |
46 | #define ATMEL_HLCDC_LAYER_DMA_BLEN_SINGLE (0 << 4) |
47 | #define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR4 (1 << 4) |
48 | #define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR8 (2 << 4) |
49 | #define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16 (3 << 4) |
50 | #define ATMEL_HLCDC_LAYER_DMA_DLBO BIT(8) |
51 | #define ATMEL_HLCDC_LAYER_DMA_ROTDIS BIT(12) |
52 | #define ATMEL_HLCDC_LAYER_DMA_LOCKDIS BIT(13) |
53 | |
54 | #define ATMEL_HLCDC_LAYER_FORMAT_CFG 1 |
55 | #define ATMEL_HLCDC_LAYER_RGB (0 << 0) |
56 | #define ATMEL_HLCDC_LAYER_CLUT (1 << 0) |
57 | #define ATMEL_HLCDC_LAYER_YUV (2 << 0) |
58 | #define ATMEL_HLCDC_RGB_MODE(m) \ |
59 | (ATMEL_HLCDC_LAYER_RGB | (((m) & 0xf) << 4)) |
60 | #define ATMEL_HLCDC_CLUT_MODE(m) \ |
61 | (ATMEL_HLCDC_LAYER_CLUT | (((m) & 0x3) << 8)) |
62 | #define ATMEL_HLCDC_YUV_MODE(m) \ |
63 | (ATMEL_HLCDC_LAYER_YUV | (((m) & 0xf) << 12)) |
64 | #define ATMEL_HLCDC_YUV422ROT BIT(16) |
65 | #define ATMEL_HLCDC_YUV422SWP BIT(17) |
66 | #define ATMEL_HLCDC_DSCALEOPT BIT(20) |
67 | |
68 | #define ATMEL_HLCDC_C1_MODE ATMEL_HLCDC_CLUT_MODE(0) |
69 | #define ATMEL_HLCDC_C2_MODE ATMEL_HLCDC_CLUT_MODE(1) |
70 | #define ATMEL_HLCDC_C4_MODE ATMEL_HLCDC_CLUT_MODE(2) |
71 | #define ATMEL_HLCDC_C8_MODE ATMEL_HLCDC_CLUT_MODE(3) |
72 | |
73 | #define ATMEL_HLCDC_XRGB4444_MODE ATMEL_HLCDC_RGB_MODE(0) |
74 | #define ATMEL_HLCDC_ARGB4444_MODE ATMEL_HLCDC_RGB_MODE(1) |
75 | #define ATMEL_HLCDC_RGBA4444_MODE ATMEL_HLCDC_RGB_MODE(2) |
76 | #define ATMEL_HLCDC_RGB565_MODE ATMEL_HLCDC_RGB_MODE(3) |
77 | #define ATMEL_HLCDC_ARGB1555_MODE ATMEL_HLCDC_RGB_MODE(4) |
78 | #define ATMEL_HLCDC_XRGB8888_MODE ATMEL_HLCDC_RGB_MODE(9) |
79 | #define ATMEL_HLCDC_RGB888_MODE ATMEL_HLCDC_RGB_MODE(10) |
80 | #define ATMEL_HLCDC_ARGB8888_MODE ATMEL_HLCDC_RGB_MODE(12) |
81 | #define ATMEL_HLCDC_RGBA8888_MODE ATMEL_HLCDC_RGB_MODE(13) |
82 | |
83 | #define ATMEL_HLCDC_AYUV_MODE ATMEL_HLCDC_YUV_MODE(0) |
84 | #define ATMEL_HLCDC_YUYV_MODE ATMEL_HLCDC_YUV_MODE(1) |
85 | #define ATMEL_HLCDC_UYVY_MODE ATMEL_HLCDC_YUV_MODE(2) |
86 | #define ATMEL_HLCDC_YVYU_MODE ATMEL_HLCDC_YUV_MODE(3) |
87 | #define ATMEL_HLCDC_VYUY_MODE ATMEL_HLCDC_YUV_MODE(4) |
88 | #define ATMEL_HLCDC_NV61_MODE ATMEL_HLCDC_YUV_MODE(5) |
89 | #define ATMEL_HLCDC_YUV422_MODE ATMEL_HLCDC_YUV_MODE(6) |
90 | #define ATMEL_HLCDC_NV21_MODE ATMEL_HLCDC_YUV_MODE(7) |
91 | #define ATMEL_HLCDC_YUV420_MODE ATMEL_HLCDC_YUV_MODE(8) |
92 | |
93 | #define ATMEL_HLCDC_LAYER_POS(x, y) ((x) | ((y) << 16)) |
94 | #define ATMEL_HLCDC_LAYER_SIZE(w, h) (((w) - 1) | (((h) - 1) << 16)) |
95 | |
96 | #define ATMEL_HLCDC_LAYER_CRKEY BIT(0) |
97 | #define ATMEL_HLCDC_LAYER_INV BIT(1) |
98 | #define ATMEL_HLCDC_LAYER_ITER2BL BIT(2) |
99 | #define ATMEL_HLCDC_LAYER_ITER BIT(3) |
100 | #define ATMEL_HLCDC_LAYER_REVALPHA BIT(4) |
101 | #define ATMEL_HLCDC_LAYER_GAEN BIT(5) |
102 | #define ATMEL_HLCDC_LAYER_LAEN BIT(6) |
103 | #define ATMEL_HLCDC_LAYER_OVR BIT(7) |
104 | #define ATMEL_HLCDC_LAYER_DMA BIT(8) |
105 | #define ATMEL_HLCDC_LAYER_REP BIT(9) |
106 | #define ATMEL_HLCDC_LAYER_DSTKEY BIT(10) |
107 | #define ATMEL_HLCDC_LAYER_DISCEN BIT(11) |
108 | #define ATMEL_HLCDC_LAYER_GA_SHIFT 16 |
109 | #define ATMEL_HLCDC_LAYER_GA_MASK \ |
110 | GENMASK(23, ATMEL_HLCDC_LAYER_GA_SHIFT) |
111 | #define ATMEL_HLCDC_LAYER_GA(x) \ |
112 | ((x) << ATMEL_HLCDC_LAYER_GA_SHIFT) |
113 | |
114 | #define ATMEL_HLCDC_LAYER_DISC_POS(x, y) ((x) | ((y) << 16)) |
115 | #define ATMEL_HLCDC_LAYER_DISC_SIZE(w, h) (((w) - 1) | (((h) - 1) << 16)) |
116 | |
117 | #define ATMEL_HLCDC_LAYER_SCALER_FACTORS(x, y) ((x) | ((y) << 16)) |
118 | #define ATMEL_HLCDC_LAYER_SCALER_ENABLE BIT(31) |
119 | |
120 | #define ATMEL_HLCDC_LAYER_MAX_PLANES 3 |
121 | |
122 | #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_RESERVED BIT(0) |
123 | #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED BIT(1) |
124 | #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE BIT(2) |
125 | #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_OVERRUN BIT(3) |
126 | |
127 | #define ATMEL_HLCDC_CLUT_SIZE 256 |
128 | |
129 | #define ATMEL_HLCDC_MAX_LAYERS 6 |
130 | |
131 | /** |
132 | * Atmel HLCDC Layer registers layout structure |
133 | * |
134 | * Each HLCDC layer has its own register organization and a given register |
135 | * can be placed differently on 2 different layers depending on its |
136 | * capabilities. |
137 | * This structure stores common registers layout for a given layer and is |
138 | * used by HLCDC layer code to choose the appropriate register to write to |
139 | * or to read from. |
140 | * |
141 | * For all fields, a value of zero means "unsupported". |
142 | * |
143 | * See Atmel's datasheet for a detailled description of these registers. |
144 | * |
145 | * @xstride: xstride registers |
146 | * @pstride: pstride registers |
147 | * @pos: position register |
148 | * @size: displayed size register |
149 | * @memsize: memory size register |
150 | * @default_color: default color register |
151 | * @chroma_key: chroma key register |
152 | * @chroma_key_mask: chroma key mask register |
153 | * @general_config: general layer config register |
154 | * @sacler_config: scaler factors register |
155 | * @phicoeffs: X/Y PHI coefficient registers |
156 | * @disc_pos: discard area position register |
157 | * @disc_size: discard area size register |
158 | * @csc: color space conversion register |
159 | */ |
160 | struct atmel_hlcdc_layer_cfg_layout { |
161 | int xstride[ATMEL_HLCDC_LAYER_MAX_PLANES]; |
162 | int pstride[ATMEL_HLCDC_LAYER_MAX_PLANES]; |
163 | int pos; |
164 | int size; |
165 | int memsize; |
166 | int default_color; |
167 | int chroma_key; |
168 | int chroma_key_mask; |
169 | int general_config; |
170 | int scaler_config; |
171 | struct { |
172 | int x; |
173 | int y; |
174 | } phicoeffs; |
175 | int disc_pos; |
176 | int disc_size; |
177 | int csc; |
178 | }; |
179 | |
180 | /** |
181 | * Atmel HLCDC DMA descriptor structure |
182 | * |
183 | * This structure is used by the HLCDC DMA engine to schedule a DMA transfer. |
184 | * |
185 | * The structure fields must remain in this specific order, because they're |
186 | * used by the HLCDC DMA engine, which expect them in this order. |
187 | * HLCDC DMA descriptors must be aligned on 64 bits. |
188 | * |
189 | * @addr: buffer DMA address |
190 | * @ctrl: DMA transfer options |
191 | * @next: next DMA descriptor to fetch |
192 | * @self: descriptor DMA address |
193 | */ |
194 | struct atmel_hlcdc_dma_channel_dscr { |
195 | dma_addr_t addr; |
196 | u32 ctrl; |
197 | dma_addr_t next; |
198 | dma_addr_t self; |
199 | } __aligned(sizeof(u64)); |
200 | |
201 | /** |
202 | * Atmel HLCDC layer types |
203 | */ |
204 | enum atmel_hlcdc_layer_type { |
205 | ATMEL_HLCDC_NO_LAYER, |
206 | ATMEL_HLCDC_BASE_LAYER, |
207 | ATMEL_HLCDC_OVERLAY_LAYER, |
208 | ATMEL_HLCDC_CURSOR_LAYER, |
209 | ATMEL_HLCDC_PP_LAYER, |
210 | }; |
211 | |
212 | /** |
213 | * Atmel HLCDC Supported formats structure |
214 | * |
215 | * This structure list all the formats supported by a given layer. |
216 | * |
217 | * @nformats: number of supported formats |
218 | * @formats: supported formats |
219 | */ |
220 | struct atmel_hlcdc_formats { |
221 | int nformats; |
222 | u32 *formats; |
223 | }; |
224 | |
225 | /** |
226 | * Atmel HLCDC Layer description structure |
227 | * |
228 | * This structure describes the capabilities provided by a given layer. |
229 | * |
230 | * @name: layer name |
231 | * @type: layer type |
232 | * @id: layer id |
233 | * @regs_offset: offset of the layer registers from the HLCDC registers base |
234 | * @cfgs_offset: CFGX registers offset from the layer registers base |
235 | * @formats: supported formats |
236 | * @layout: config registers layout |
237 | * @max_width: maximum width supported by this layer (0 means unlimited) |
238 | * @max_height: maximum height supported by this layer (0 means unlimited) |
239 | */ |
240 | struct atmel_hlcdc_layer_desc { |
241 | const char *name; |
242 | enum atmel_hlcdc_layer_type type; |
243 | int id; |
244 | int regs_offset; |
245 | int cfgs_offset; |
246 | int clut_offset; |
247 | struct atmel_hlcdc_formats *formats; |
248 | struct atmel_hlcdc_layer_cfg_layout layout; |
249 | int max_width; |
250 | int max_height; |
251 | }; |
252 | |
253 | /** |
254 | * Atmel HLCDC Layer. |
255 | * |
256 | * A layer can be a DRM plane of a post processing layer used to render |
257 | * HLCDC composition into memory. |
258 | * |
259 | * @desc: layer description |
260 | * @regmap: pointer to the HLCDC regmap |
261 | */ |
262 | struct atmel_hlcdc_layer { |
263 | const struct atmel_hlcdc_layer_desc *desc; |
264 | struct regmap *regmap; |
265 | }; |
266 | |
267 | /** |
268 | * Atmel HLCDC Plane. |
269 | * |
270 | * @base: base DRM plane structure |
271 | * @layer: HLCDC layer structure |
272 | * @properties: pointer to the property definitions structure |
273 | */ |
274 | struct atmel_hlcdc_plane { |
275 | struct drm_plane base; |
276 | struct atmel_hlcdc_layer layer; |
277 | }; |
278 | |
279 | static inline struct atmel_hlcdc_plane * |
280 | drm_plane_to_atmel_hlcdc_plane(struct drm_plane *p) |
281 | { |
282 | return container_of(p, struct atmel_hlcdc_plane, base); |
283 | } |
284 | |
285 | static inline struct atmel_hlcdc_plane * |
286 | atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer *layer) |
287 | { |
288 | return container_of(layer, struct atmel_hlcdc_plane, layer); |
289 | } |
290 | |
291 | /** |
292 | * Atmel HLCDC Display Controller description structure. |
293 | * |
294 | * This structure describes the HLCDC IP capabilities and depends on the |
295 | * HLCDC IP version (or Atmel SoC family). |
296 | * |
297 | * @min_width: minimum width supported by the Display Controller |
298 | * @min_height: minimum height supported by the Display Controller |
299 | * @max_width: maximum width supported by the Display Controller |
300 | * @max_height: maximum height supported by the Display Controller |
301 | * @max_spw: maximum vertical/horizontal pulse width |
302 | * @max_vpw: maximum vertical back/front porch width |
303 | * @max_hpw: maximum horizontal back/front porch width |
304 | * @conflicting_output_formats: true if RGBXXX output formats conflict with |
305 | * each other. |
306 | * @fixed_clksrc: true if clock source is fixed |
307 | * @layers: a layer description table describing available layers |
308 | * @nlayers: layer description table size |
309 | */ |
310 | struct atmel_hlcdc_dc_desc { |
311 | int min_width; |
312 | int min_height; |
313 | int max_width; |
314 | int max_height; |
315 | int max_spw; |
316 | int max_vpw; |
317 | int max_hpw; |
318 | bool conflicting_output_formats; |
319 | bool fixed_clksrc; |
320 | const struct atmel_hlcdc_layer_desc *layers; |
321 | int nlayers; |
322 | }; |
323 | |
324 | /** |
325 | * Atmel HLCDC Display Controller. |
326 | * |
327 | * @desc: HLCDC Display Controller description |
328 | * @dscrpool: DMA coherent pool used to allocate DMA descriptors |
329 | * @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device |
330 | * @fbdev: framebuffer device attached to the Display Controller |
331 | * @crtc: CRTC provided by the display controller |
332 | * @planes: instantiated planes |
333 | * @layers: active HLCDC layers |
334 | * @suspend: used to store the HLCDC state when entering suspend |
335 | */ |
336 | struct atmel_hlcdc_dc { |
337 | const struct atmel_hlcdc_dc_desc *desc; |
338 | struct dma_pool *dscrpool; |
339 | struct atmel_hlcdc *hlcdc; |
340 | struct drm_crtc *crtc; |
341 | struct atmel_hlcdc_layer *layers[ATMEL_HLCDC_MAX_LAYERS]; |
342 | struct { |
343 | u32 imr; |
344 | struct drm_atomic_state *state; |
345 | } suspend; |
346 | }; |
347 | |
348 | extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats; |
349 | extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_and_yuv_formats; |
350 | |
351 | static inline void atmel_hlcdc_layer_write_reg(struct atmel_hlcdc_layer *layer, |
352 | unsigned int reg, u32 val) |
353 | { |
354 | regmap_write(map: layer->regmap, reg: layer->desc->regs_offset + reg, val); |
355 | } |
356 | |
357 | static inline u32 atmel_hlcdc_layer_read_reg(struct atmel_hlcdc_layer *layer, |
358 | unsigned int reg) |
359 | { |
360 | u32 val; |
361 | |
362 | regmap_read(map: layer->regmap, reg: layer->desc->regs_offset + reg, val: &val); |
363 | |
364 | return val; |
365 | } |
366 | |
367 | static inline void atmel_hlcdc_layer_write_cfg(struct atmel_hlcdc_layer *layer, |
368 | unsigned int cfgid, u32 val) |
369 | { |
370 | atmel_hlcdc_layer_write_reg(layer, |
371 | reg: layer->desc->cfgs_offset + |
372 | (cfgid * sizeof(u32)), val); |
373 | } |
374 | |
375 | static inline u32 atmel_hlcdc_layer_read_cfg(struct atmel_hlcdc_layer *layer, |
376 | unsigned int cfgid) |
377 | { |
378 | return atmel_hlcdc_layer_read_reg(layer, |
379 | reg: layer->desc->cfgs_offset + |
380 | (cfgid * sizeof(u32))); |
381 | } |
382 | |
383 | static inline void atmel_hlcdc_layer_write_clut(struct atmel_hlcdc_layer *layer, |
384 | unsigned int c, u32 val) |
385 | { |
386 | regmap_write(map: layer->regmap, |
387 | reg: layer->desc->clut_offset + c * sizeof(u32), |
388 | val); |
389 | } |
390 | |
391 | static inline void atmel_hlcdc_layer_init(struct atmel_hlcdc_layer *layer, |
392 | const struct atmel_hlcdc_layer_desc *desc, |
393 | struct regmap *regmap) |
394 | { |
395 | layer->desc = desc; |
396 | layer->regmap = regmap; |
397 | } |
398 | |
399 | enum drm_mode_status |
400 | atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc, |
401 | const struct drm_display_mode *mode); |
402 | |
403 | int atmel_hlcdc_create_planes(struct drm_device *dev); |
404 | void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane); |
405 | |
406 | int atmel_hlcdc_plane_prepare_disc_area(struct drm_crtc_state *c_state); |
407 | int atmel_hlcdc_plane_prepare_ahb_routing(struct drm_crtc_state *c_state); |
408 | |
409 | void atmel_hlcdc_crtc_irq(struct drm_crtc *c); |
410 | |
411 | int atmel_hlcdc_crtc_create(struct drm_device *dev); |
412 | |
413 | int atmel_hlcdc_create_outputs(struct drm_device *dev); |
414 | int atmel_hlcdc_encoder_get_bus_fmt(struct drm_encoder *encoder); |
415 | |
416 | #endif /* DRM_ATMEL_HLCDC_H */ |
417 | |