1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright (c) 2006 Intel Corporation |
4 | * |
5 | * Authors: |
6 | * Eric Anholt <eric@anholt.net> |
7 | */ |
8 | |
9 | #ifndef _INTEL_BIOS_H_ |
10 | #define _INTEL_BIOS_H_ |
11 | |
12 | struct drm_device; |
13 | |
14 | struct { |
15 | u8 [20]; /**< Always starts with 'VBT$' */ |
16 | u16 ; /**< decimal */ |
17 | u16 ; /**< in bytes */ |
18 | u16 ; /**< in bytes */ |
19 | u8 ; |
20 | u8 ; |
21 | u32 ; /**< from beginning of VBT */ |
22 | u32 [4]; /**< from beginning of VBT */ |
23 | } __packed; |
24 | |
25 | |
26 | struct { |
27 | u8 [16]; /**< Always 'BIOS_DATA_BLOCK' */ |
28 | u16 ; /**< decimal */ |
29 | u16 ; /**< in bytes */ |
30 | u16 ; /**< in bytes */ |
31 | }; |
32 | |
33 | /* strictly speaking, this is a "skip" block, but it has interesting info */ |
34 | struct vbios_data { |
35 | u8 type; /* 0 == desktop, 1 == mobile */ |
36 | u8 relstage; |
37 | u8 chipset; |
38 | u8 lvds_present:1; |
39 | u8 tv_present:1; |
40 | u8 rsvd2:6; /* finish byte */ |
41 | u8 rsvd3[4]; |
42 | u8 signon[155]; |
43 | u8 copyright[61]; |
44 | u16 code_segment; |
45 | u8 dos_boot_mode; |
46 | u8 bandwidth_percent; |
47 | u8 rsvd4; /* popup memory size */ |
48 | u8 resize_pci_bios; |
49 | u8 rsvd5; /* is crt already on ddc2 */ |
50 | } __packed; |
51 | |
52 | /* |
53 | * There are several types of BIOS data blocks (BDBs), each block has |
54 | * an ID and size in the first 3 bytes (ID in first, size in next 2). |
55 | * Known types are listed below. |
56 | */ |
57 | #define BDB_GENERAL_FEATURES 1 |
58 | #define BDB_GENERAL_DEFINITIONS 2 |
59 | #define BDB_OLD_TOGGLE_LIST 3 |
60 | #define BDB_MODE_SUPPORT_LIST 4 |
61 | #define BDB_GENERIC_MODE_TABLE 5 |
62 | #define BDB_EXT_MMIO_REGS 6 |
63 | #define BDB_SWF_IO 7 |
64 | #define BDB_SWF_MMIO 8 |
65 | #define BDB_DOT_CLOCK_TABLE 9 |
66 | #define BDB_MODE_REMOVAL_TABLE 10 |
67 | #define BDB_CHILD_DEVICE_TABLE 11 |
68 | #define BDB_DRIVER_FEATURES 12 |
69 | #define BDB_DRIVER_PERSISTENCE 13 |
70 | #define BDB_EXT_TABLE_PTRS 14 |
71 | #define BDB_DOT_CLOCK_OVERRIDE 15 |
72 | #define BDB_DISPLAY_SELECT 16 |
73 | /* 17 rsvd */ |
74 | #define BDB_DRIVER_ROTATION 18 |
75 | #define BDB_DISPLAY_REMOVE 19 |
76 | #define BDB_OEM_CUSTOM 20 |
77 | #define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */ |
78 | #define BDB_SDVO_LVDS_OPTIONS 22 |
79 | #define BDB_SDVO_PANEL_DTDS 23 |
80 | #define BDB_SDVO_LVDS_PNP_IDS 24 |
81 | #define BDB_SDVO_LVDS_POWER_SEQ 25 |
82 | #define BDB_TV_OPTIONS 26 |
83 | #define BDB_EDP 27 |
84 | #define BDB_LVDS_OPTIONS 40 |
85 | #define BDB_LVDS_LFP_DATA_PTRS 41 |
86 | #define BDB_LVDS_LFP_DATA 42 |
87 | #define BDB_LVDS_BACKLIGHT 43 |
88 | #define BDB_LVDS_POWER 44 |
89 | #define BDB_SKIP 254 /* VBIOS private block, ignore */ |
90 | |
91 | struct bdb_general_features { |
92 | /* bits 1 */ |
93 | u8 panel_fitting:2; |
94 | u8 flexaim:1; |
95 | u8 msg_enable:1; |
96 | u8 clear_screen:3; |
97 | u8 color_flip:1; |
98 | |
99 | /* bits 2 */ |
100 | u8 download_ext_vbt:1; |
101 | u8 enable_ssc:1; |
102 | u8 ssc_freq:1; |
103 | u8 enable_lfp_on_override:1; |
104 | u8 disable_ssc_ddt:1; |
105 | u8 rsvd8:3; /* finish byte */ |
106 | |
107 | /* bits 3 */ |
108 | u8 disable_smooth_vision:1; |
109 | u8 single_dvi:1; |
110 | u8 rsvd9:6; /* finish byte */ |
111 | |
112 | /* bits 4 */ |
113 | u8 legacy_monitor_detect; |
114 | |
115 | /* bits 5 */ |
116 | u8 int_crt_support:1; |
117 | u8 int_tv_support:1; |
118 | u8 int_efp_support:1; |
119 | u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */ |
120 | u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ |
121 | u8 rsvd11:3; /* finish byte */ |
122 | } __packed; |
123 | |
124 | /* pre-915 */ |
125 | #define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ |
126 | #define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ |
127 | #define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ |
128 | #define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ |
129 | |
130 | /* Pre 915 */ |
131 | #define DEVICE_TYPE_NONE 0x00 |
132 | #define DEVICE_TYPE_CRT 0x01 |
133 | #define DEVICE_TYPE_TV 0x09 |
134 | #define DEVICE_TYPE_EFP 0x12 |
135 | #define DEVICE_TYPE_LFP 0x22 |
136 | /* On 915+ */ |
137 | #define DEVICE_TYPE_CRT_DPMS 0x6001 |
138 | #define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 |
139 | #define DEVICE_TYPE_TV_COMPOSITE 0x0209 |
140 | #define DEVICE_TYPE_TV_MACROVISION 0x0289 |
141 | #define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c |
142 | #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 |
143 | #define DEVICE_TYPE_TV_SCART 0x0209 |
144 | #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 |
145 | #define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 |
146 | #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 |
147 | #define DEVICE_TYPE_EFP_DVI_I 0x6053 |
148 | #define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 |
149 | #define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 |
150 | #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 |
151 | #define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 |
152 | #define DEVICE_TYPE_LFP_PANELLINK 0x5012 |
153 | #define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 |
154 | #define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 |
155 | #define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 |
156 | #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 |
157 | |
158 | #define DEVICE_CFG_NONE 0x00 |
159 | #define DEVICE_CFG_12BIT_DVOB 0x01 |
160 | #define DEVICE_CFG_12BIT_DVOC 0x02 |
161 | #define DEVICE_CFG_24BIT_DVOBC 0x09 |
162 | #define DEVICE_CFG_24BIT_DVOCB 0x0a |
163 | #define DEVICE_CFG_DUAL_DVOB 0x11 |
164 | #define DEVICE_CFG_DUAL_DVOC 0x12 |
165 | #define DEVICE_CFG_DUAL_DVOBC 0x13 |
166 | #define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 |
167 | #define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a |
168 | |
169 | #define DEVICE_WIRE_NONE 0x00 |
170 | #define DEVICE_WIRE_DVOB 0x01 |
171 | #define DEVICE_WIRE_DVOC 0x02 |
172 | #define DEVICE_WIRE_DVOBC 0x03 |
173 | #define DEVICE_WIRE_DVOBB 0x05 |
174 | #define DEVICE_WIRE_DVOCC 0x06 |
175 | #define DEVICE_WIRE_DVOB_MASTER 0x0d |
176 | #define DEVICE_WIRE_DVOC_MASTER 0x0e |
177 | |
178 | #define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ |
179 | #define DEVICE_PORT_DVOB 0x01 |
180 | #define DEVICE_PORT_DVOC 0x02 |
181 | |
182 | struct child_device_config { |
183 | u16 handle; |
184 | u16 device_type; |
185 | u8 device_id[10]; /* ascii string */ |
186 | u16 addin_offset; |
187 | u8 dvo_port; /* See Device_PORT_* above */ |
188 | u8 i2c_pin; |
189 | u8 slave_addr; |
190 | u8 ddc_pin; |
191 | u16 edid_ptr; |
192 | u8 dvo_cfg; /* See DEVICE_CFG_* above */ |
193 | u8 dvo2_port; |
194 | u8 i2c2_pin; |
195 | u8 slave2_addr; |
196 | u8 ddc2_pin; |
197 | u8 capabilities; |
198 | u8 dvo_wiring;/* See DEVICE_WIRE_* above */ |
199 | u8 dvo2_wiring; |
200 | u16 extended_type; |
201 | u8 dvo_function; |
202 | } __packed; |
203 | |
204 | |
205 | struct bdb_general_definitions { |
206 | /* DDC GPIO */ |
207 | u8 crt_ddc_gmbus_pin; |
208 | |
209 | /* DPMS bits */ |
210 | u8 dpms_acpi:1; |
211 | u8 skip_boot_crt_detect:1; |
212 | u8 dpms_aim:1; |
213 | u8 rsvd1:5; /* finish byte */ |
214 | |
215 | /* boot device bits */ |
216 | u8 boot_display[2]; |
217 | u8 child_dev_size; |
218 | |
219 | /* |
220 | * Device info: |
221 | * If TV is present, it'll be at devices[0]. |
222 | * LVDS will be next, either devices[0] or [1], if present. |
223 | * On some platforms the number of device is 6. But could be as few as |
224 | * 4 if both TV and LVDS are missing. |
225 | * And the device num is related with the size of general definition |
226 | * block. It is obtained by using the following formula: |
227 | * number = (block_size - sizeof(bdb_general_definitions))/ |
228 | * sizeof(child_device_config); |
229 | */ |
230 | struct child_device_config devices[]; |
231 | }; |
232 | |
233 | struct bdb_lvds_options { |
234 | u8 panel_type; |
235 | u8 rsvd1; |
236 | /* LVDS capabilities, stored in a dword */ |
237 | u8 pfit_mode:2; |
238 | u8 pfit_text_mode_enhanced:1; |
239 | u8 pfit_gfx_mode_enhanced:1; |
240 | u8 pfit_ratio_auto:1; |
241 | u8 pixel_dither:1; |
242 | u8 lvds_edid:1; |
243 | u8 rsvd2:1; |
244 | u8 rsvd4; |
245 | } __packed; |
246 | |
247 | struct bdb_lvds_backlight { |
248 | u8 type:2; |
249 | u8 pol:1; |
250 | u8 gpio:3; |
251 | u8 gmbus:2; |
252 | u16 freq; |
253 | u8 minbrightness; |
254 | u8 i2caddr; |
255 | u8 brightnesscmd; |
256 | /*FIXME: more...*/ |
257 | } __packed; |
258 | |
259 | /* LFP pointer table contains entries to the struct below */ |
260 | struct bdb_lvds_lfp_data_ptr { |
261 | u16 fp_timing_offset; /* offsets are from start of bdb */ |
262 | u8 fp_table_size; |
263 | u16 dvo_timing_offset; |
264 | u8 dvo_table_size; |
265 | u16 panel_pnp_id_offset; |
266 | u8 pnp_table_size; |
267 | } __packed; |
268 | |
269 | struct bdb_lvds_lfp_data_ptrs { |
270 | u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */ |
271 | struct bdb_lvds_lfp_data_ptr ptr[16]; |
272 | } __packed; |
273 | |
274 | /* LFP data has 3 blocks per entry */ |
275 | struct lvds_fp_timing { |
276 | u16 x_res; |
277 | u16 y_res; |
278 | u32 lvds_reg; |
279 | u32 lvds_reg_val; |
280 | u32 pp_on_reg; |
281 | u32 pp_on_reg_val; |
282 | u32 pp_off_reg; |
283 | u32 pp_off_reg_val; |
284 | u32 pp_cycle_reg; |
285 | u32 pp_cycle_reg_val; |
286 | u32 pfit_reg; |
287 | u32 pfit_reg_val; |
288 | u16 terminator; |
289 | } __packed; |
290 | |
291 | struct lvds_dvo_timing { |
292 | u16 clock; /**< In 10khz */ |
293 | u8 hactive_lo; |
294 | u8 hblank_lo; |
295 | u8 hblank_hi:4; |
296 | u8 hactive_hi:4; |
297 | u8 vactive_lo; |
298 | u8 vblank_lo; |
299 | u8 vblank_hi:4; |
300 | u8 vactive_hi:4; |
301 | u8 hsync_off_lo; |
302 | u8 hsync_pulse_width; |
303 | u8 vsync_pulse_width:4; |
304 | u8 vsync_off:4; |
305 | u8 rsvd0:6; |
306 | u8 hsync_off_hi:2; |
307 | u8 h_image; |
308 | u8 v_image; |
309 | u8 max_hv; |
310 | u8 h_border; |
311 | u8 v_border; |
312 | u8 rsvd1:3; |
313 | u8 digital:2; |
314 | u8 vsync_positive:1; |
315 | u8 hsync_positive:1; |
316 | u8 rsvd2:1; |
317 | } __packed; |
318 | |
319 | struct lvds_pnp_id { |
320 | u16 mfg_name; |
321 | u16 product_code; |
322 | u32 serial; |
323 | u8 mfg_week; |
324 | u8 mfg_year; |
325 | } __packed; |
326 | |
327 | struct bdb_lvds_lfp_data_entry { |
328 | struct lvds_fp_timing fp_timing; |
329 | struct lvds_dvo_timing dvo_timing; |
330 | struct lvds_pnp_id pnp_id; |
331 | } __packed; |
332 | |
333 | struct bdb_lvds_lfp_data { |
334 | struct bdb_lvds_lfp_data_entry data[16]; |
335 | } __packed; |
336 | |
337 | struct { |
338 | char [16]; |
339 | char [20]; |
340 | u16 ; |
341 | u16 ; |
342 | u16 ; |
343 | } __packed; |
344 | |
345 | struct aimdb_block { |
346 | u8 aimdb_id; |
347 | u16 aimdb_size; |
348 | } __packed; |
349 | |
350 | struct vch_panel_data { |
351 | u16 fp_timing_offset; |
352 | u8 fp_timing_size; |
353 | u16 dvo_timing_offset; |
354 | u8 dvo_timing_size; |
355 | u16 text_fitting_offset; |
356 | u8 text_fitting_size; |
357 | u16 graphics_fitting_offset; |
358 | u8 graphics_fitting_size; |
359 | } __packed; |
360 | |
361 | struct vch_bdb_22 { |
362 | struct aimdb_block aimdb_block; |
363 | struct vch_panel_data panels[16]; |
364 | } __packed; |
365 | |
366 | struct bdb_sdvo_lvds_options { |
367 | u8 panel_backlight; |
368 | u8 h40_set_panel_type; |
369 | u8 panel_type; |
370 | u8 ssc_clk_freq; |
371 | u16 als_low_trip; |
372 | u16 als_high_trip; |
373 | u8 sclalarcoeff_tab_row_num; |
374 | u8 sclalarcoeff_tab_row_size; |
375 | u8 coefficient[8]; |
376 | u8 panel_misc_bits_1; |
377 | u8 panel_misc_bits_2; |
378 | u8 panel_misc_bits_3; |
379 | u8 panel_misc_bits_4; |
380 | } __packed; |
381 | |
382 | #define BDB_DRIVER_FEATURE_NO_LVDS 0 |
383 | #define BDB_DRIVER_FEATURE_INT_LVDS 1 |
384 | #define BDB_DRIVER_FEATURE_SDVO_LVDS 2 |
385 | #define BDB_DRIVER_FEATURE_EDP 3 |
386 | |
387 | struct bdb_driver_features { |
388 | u8 boot_dev_algorithm:1; |
389 | u8 block_display_switch:1; |
390 | u8 allow_display_switch:1; |
391 | u8 hotplug_dvo:1; |
392 | u8 dual_view_zoom:1; |
393 | u8 int15h_hook:1; |
394 | u8 sprite_in_clone:1; |
395 | u8 primary_lfp_id:1; |
396 | |
397 | u16 boot_mode_x; |
398 | u16 boot_mode_y; |
399 | u8 boot_mode_bpp; |
400 | u8 boot_mode_refresh; |
401 | |
402 | u16 enable_lfp_primary:1; |
403 | u16 selective_mode_pruning:1; |
404 | u16 dual_frequency:1; |
405 | u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ |
406 | u16 nt_clone_support:1; |
407 | u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ |
408 | u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ |
409 | u16 cui_aspect_scaling:1; |
410 | u16 preserve_aspect_ratio:1; |
411 | u16 sdvo_device_power_down:1; |
412 | u16 crt_hotplug:1; |
413 | u16 lvds_config:2; |
414 | u16 tv_hotplug:1; |
415 | u16 hdmi_config:2; |
416 | |
417 | u8 static_display:1; |
418 | u8 reserved2:7; |
419 | u16 legacy_crt_max_x; |
420 | u16 legacy_crt_max_y; |
421 | u8 legacy_crt_max_refresh; |
422 | |
423 | u8 hdmi_termination; |
424 | u8 custom_vbt_version; |
425 | } __packed; |
426 | |
427 | #define EDP_18BPP 0 |
428 | #define EDP_24BPP 1 |
429 | #define EDP_30BPP 2 |
430 | #define EDP_RATE_1_62 0 |
431 | #define EDP_RATE_2_7 1 |
432 | #define EDP_LANE_1 0 |
433 | #define EDP_LANE_2 1 |
434 | #define EDP_LANE_4 3 |
435 | #define EDP_PREEMPHASIS_NONE 0 |
436 | #define EDP_PREEMPHASIS_3_5dB 1 |
437 | #define EDP_PREEMPHASIS_6dB 2 |
438 | #define EDP_PREEMPHASIS_9_5dB 3 |
439 | #define EDP_VSWING_0_4V 0 |
440 | #define EDP_VSWING_0_6V 1 |
441 | #define EDP_VSWING_0_8V 2 |
442 | #define EDP_VSWING_1_2V 3 |
443 | |
444 | struct edp_power_seq { |
445 | u16 t1_t3; |
446 | u16 t8; |
447 | u16 t9; |
448 | u16 t10; |
449 | u16 t11_t12; |
450 | } __attribute__ ((packed)); |
451 | |
452 | struct edp_link_params { |
453 | u8 rate:4; |
454 | u8 lanes:4; |
455 | u8 preemphasis:4; |
456 | u8 vswing:4; |
457 | } __attribute__ ((packed)); |
458 | |
459 | struct bdb_edp { |
460 | struct edp_power_seq power_seqs[16]; |
461 | u32 color_depth; |
462 | u32 sdrrs_msa_timing_delay; |
463 | struct edp_link_params link_params[16]; |
464 | } __attribute__ ((packed)); |
465 | |
466 | extern int psb_intel_init_bios(struct drm_device *dev); |
467 | extern void psb_intel_destroy_bios(struct drm_device *dev); |
468 | |
469 | /* |
470 | * Driver<->VBIOS interaction occurs through scratch bits in |
471 | * GR18 & SWF*. |
472 | */ |
473 | |
474 | /* GR18 bits are set on display switch and hotkey events */ |
475 | #define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */ |
476 | #define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */ |
477 | #define GR18_HK_NONE (0x0<<3) |
478 | #define GR18_HK_LFP_STRETCH (0x1<<3) |
479 | #define GR18_HK_TOGGLE_DISP (0x2<<3) |
480 | #define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */ |
481 | #define (0x6<<3) |
482 | #define (0x7<<3) |
483 | #define GR18_HK_PFIT (0x8<<3) |
484 | #define GR18_HK_APM_CHANGE (0xa<<3) |
485 | #define GR18_HK_MULTIPLE (0xc<<3) |
486 | #define GR18_USER_INT_EN (1<<2) |
487 | #define GR18_A0000_FLUSH_EN (1<<1) |
488 | #define GR18_SMM_EN (1<<0) |
489 | |
490 | /* Set by driver, cleared by VBIOS */ |
491 | #define SWF00_YRES_SHIFT 16 |
492 | #define SWF00_XRES_SHIFT 0 |
493 | #define SWF00_RES_MASK 0xffff |
494 | |
495 | /* Set by VBIOS at boot time and driver at runtime */ |
496 | #define SWF01_TV2_FORMAT_SHIFT 8 |
497 | #define SWF01_TV1_FORMAT_SHIFT 0 |
498 | #define SWF01_TV_FORMAT_MASK 0xffff |
499 | |
500 | #define SWF10_VBIOS_BLC_I2C_EN (1<<29) |
501 | #define SWF10_GTT_OVERRIDE_EN (1<<28) |
502 | #define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */ |
503 | #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24) |
504 | #define SWF10_OLD_TOGGLE 0x0 |
505 | #define SWF10_TOGGLE_LIST_1 0x1 |
506 | #define SWF10_TOGGLE_LIST_2 0x2 |
507 | #define SWF10_TOGGLE_LIST_3 0x3 |
508 | #define SWF10_TOGGLE_LIST_4 0x4 |
509 | #define SWF10_PANNING_EN (1<<23) |
510 | #define SWF10_DRIVER_LOADED (1<<22) |
511 | #define SWF10_EXTENDED_DESKTOP (1<<21) |
512 | #define SWF10_EXCLUSIVE_MODE (1<<20) |
513 | #define SWF10_OVERLAY_EN (1<<19) |
514 | #define SWF10_PLANEB_HOLDOFF (1<<18) |
515 | #define SWF10_PLANEA_HOLDOFF (1<<17) |
516 | #define SWF10_VGA_HOLDOFF (1<<16) |
517 | #define SWF10_ACTIVE_DISP_MASK 0xffff |
518 | #define SWF10_PIPEB_LFP2 (1<<15) |
519 | #define SWF10_PIPEB_EFP2 (1<<14) |
520 | #define SWF10_PIPEB_TV2 (1<<13) |
521 | #define SWF10_PIPEB_CRT2 (1<<12) |
522 | #define SWF10_PIPEB_LFP (1<<11) |
523 | #define SWF10_PIPEB_EFP (1<<10) |
524 | #define SWF10_PIPEB_TV (1<<9) |
525 | #define SWF10_PIPEB_CRT (1<<8) |
526 | #define SWF10_PIPEA_LFP2 (1<<7) |
527 | #define SWF10_PIPEA_EFP2 (1<<6) |
528 | #define SWF10_PIPEA_TV2 (1<<5) |
529 | #define SWF10_PIPEA_CRT2 (1<<4) |
530 | #define SWF10_PIPEA_LFP (1<<3) |
531 | #define SWF10_PIPEA_EFP (1<<2) |
532 | #define SWF10_PIPEA_TV (1<<1) |
533 | #define SWF10_PIPEA_CRT (1<<0) |
534 | |
535 | #define SWF11_MEMORY_SIZE_SHIFT 16 |
536 | #define SWF11_SV_TEST_EN (1<<15) |
537 | #define SWF11_IS_AGP (1<<14) |
538 | #define SWF11_DISPLAY_HOLDOFF (1<<13) |
539 | #define SWF11_DPMS_REDUCED (1<<12) |
540 | #define SWF11_IS_VBE_MODE (1<<11) |
541 | #define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */ |
542 | #define SWF11_DPMS_MASK 0x07 |
543 | #define SWF11_DPMS_OFF (1<<2) |
544 | #define SWF11_DPMS_SUSPEND (1<<1) |
545 | #define SWF11_DPMS_STANDBY (1<<0) |
546 | #define SWF11_DPMS_ON 0 |
547 | |
548 | #define SWF14_GFX_PFIT_EN (1<<31) |
549 | #define SWF14_TEXT_PFIT_EN (1<<30) |
550 | #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */ |
551 | #define (1<<28) |
552 | #define SWF14_DISPLAY_HOLDOFF (1<<27) |
553 | #define SWF14_DISP_DETECT_EN (1<<26) |
554 | #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */ |
555 | #define SWF14_DRIVER_STATUS (1<<24) |
556 | #define SWF14_OS_TYPE_WIN9X (1<<23) |
557 | #define SWF14_OS_TYPE_WINNT (1<<22) |
558 | /* 21:19 rsvd */ |
559 | #define SWF14_PM_TYPE_MASK 0x00070000 |
560 | #define SWF14_PM_ACPI_VIDEO (0x4 << 16) |
561 | #define SWF14_PM_ACPI (0x3 << 16) |
562 | #define SWF14_PM_APM_12 (0x2 << 16) |
563 | #define SWF14_PM_APM_11 (0x1 << 16) |
564 | #define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */ |
565 | /* if GR18 indicates a display switch */ |
566 | #define SWF14_DS_PIPEB_LFP2_EN (1<<15) |
567 | #define SWF14_DS_PIPEB_EFP2_EN (1<<14) |
568 | #define SWF14_DS_PIPEB_TV2_EN (1<<13) |
569 | #define SWF14_DS_PIPEB_CRT2_EN (1<<12) |
570 | #define SWF14_DS_PIPEB_LFP_EN (1<<11) |
571 | #define SWF14_DS_PIPEB_EFP_EN (1<<10) |
572 | #define SWF14_DS_PIPEB_TV_EN (1<<9) |
573 | #define SWF14_DS_PIPEB_CRT_EN (1<<8) |
574 | #define SWF14_DS_PIPEA_LFP2_EN (1<<7) |
575 | #define SWF14_DS_PIPEA_EFP2_EN (1<<6) |
576 | #define SWF14_DS_PIPEA_TV2_EN (1<<5) |
577 | #define SWF14_DS_PIPEA_CRT2_EN (1<<4) |
578 | #define SWF14_DS_PIPEA_LFP_EN (1<<3) |
579 | #define SWF14_DS_PIPEA_EFP_EN (1<<2) |
580 | #define SWF14_DS_PIPEA_TV_EN (1<<1) |
581 | #define SWF14_DS_PIPEA_CRT_EN (1<<0) |
582 | /* if GR18 indicates a panel fitting request */ |
583 | #define SWF14_PFIT_EN (1<<0) /* 0 means disable */ |
584 | /* if GR18 indicates an APM change request */ |
585 | #define SWF14_APM_HIBERNATE 0x4 |
586 | #define SWF14_APM_SUSPEND 0x3 |
587 | #define SWF14_APM_STANDBY 0x1 |
588 | #define SWF14_APM_RESTORE 0x0 |
589 | |
590 | /* Add the device class for LFP, TV, HDMI */ |
591 | #define DEVICE_TYPE_INT_LFP 0x1022 |
592 | #define DEVICE_TYPE_INT_TV 0x1009 |
593 | #define DEVICE_TYPE_HDMI 0x60D2 |
594 | #define DEVICE_TYPE_DP 0x68C6 |
595 | #define DEVICE_TYPE_eDP 0x78C6 |
596 | |
597 | /* define the DVO port for HDMI output type */ |
598 | #define DVO_B 1 |
599 | #define DVO_C 2 |
600 | #define DVO_D 3 |
601 | |
602 | /* define the PORT for DP output type */ |
603 | #define PORT_IDPB 7 |
604 | #define PORT_IDPC 8 |
605 | #define PORT_IDPD 9 |
606 | |
607 | #endif /* _INTEL_BIOS_H_ */ |
608 | |