| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /************************************************************************** |
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| 3 | * |
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| 4 | * Copyright (c) (2005-2007) Imagination Technologies Limited. |
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| 5 | * Copyright (c) 2007, Intel Corporation. |
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| 6 | * All Rights Reserved. |
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| 7 | * |
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| 8 | **************************************************************************/ |
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| 9 | |
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| 10 | #ifndef _PSB_REG_H_ |
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| 11 | #define _PSB_REG_H_ |
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| 12 | |
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| 13 | #define PSB_CR_CLKGATECTL 0x0000 |
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| 14 | #define _PSB_C_CLKGATECTL_AUTO_MAN_REG (1 << 24) |
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| 15 | #define _PSB_C_CLKGATECTL_USE_CLKG_SHIFT (20) |
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| 16 | #define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20) |
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| 17 | #define _PSB_C_CLKGATECTL_DPM_CLKG_SHIFT (16) |
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| 18 | #define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16) |
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| 19 | #define _PSB_C_CLKGATECTL_TA_CLKG_SHIFT (12) |
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| 20 | #define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12) |
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| 21 | #define _PSB_C_CLKGATECTL_TSP_CLKG_SHIFT (8) |
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| 22 | #define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8) |
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| 23 | #define _PSB_C_CLKGATECTL_ISP_CLKG_SHIFT (4) |
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| 24 | #define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4) |
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| 25 | #define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0) |
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| 26 | #define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0) |
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| 27 | #define _PSB_C_CLKGATECTL_CLKG_ENABLED (0) |
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| 28 | #define _PSB_C_CLKGATECTL_CLKG_DISABLED (1) |
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| 29 | #define _PSB_C_CLKGATECTL_CLKG_AUTO (2) |
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| 30 | |
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| 31 | #define PSB_CR_CORE_ID 0x0010 |
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| 32 | #define _PSB_CC_ID_ID_SHIFT (16) |
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| 33 | #define _PSB_CC_ID_ID_MASK (0xFFFF << 16) |
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| 34 | #define _PSB_CC_ID_CONFIG_SHIFT (0) |
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| 35 | #define _PSB_CC_ID_CONFIG_MASK (0xFFFF << 0) |
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| 36 | |
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| 37 | #define PSB_CR_CORE_REVISION 0x0014 |
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| 38 | #define _PSB_CC_REVISION_DESIGNER_SHIFT (24) |
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| 39 | #define _PSB_CC_REVISION_DESIGNER_MASK (0xFF << 24) |
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| 40 | #define _PSB_CC_REVISION_MAJOR_SHIFT (16) |
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| 41 | #define _PSB_CC_REVISION_MAJOR_MASK (0xFF << 16) |
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| 42 | #define _PSB_CC_REVISION_MINOR_SHIFT (8) |
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| 43 | #define _PSB_CC_REVISION_MINOR_MASK (0xFF << 8) |
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| 44 | #define _PSB_CC_REVISION_MAINTENANCE_SHIFT (0) |
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| 45 | #define _PSB_CC_REVISION_MAINTENANCE_MASK (0xFF << 0) |
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| 46 | |
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| 47 | #define PSB_CR_DESIGNER_REV_FIELD1 0x0018 |
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| 48 | |
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| 49 | #define PSB_CR_SOFT_RESET 0x0080 |
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| 50 | #define _PSB_CS_RESET_TSP_RESET (1 << 6) |
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| 51 | #define _PSB_CS_RESET_ISP_RESET (1 << 5) |
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| 52 | #define _PSB_CS_RESET_USE_RESET (1 << 4) |
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| 53 | #define _PSB_CS_RESET_TA_RESET (1 << 3) |
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| 54 | #define _PSB_CS_RESET_DPM_RESET (1 << 2) |
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| 55 | #define _PSB_CS_RESET_TWOD_RESET (1 << 1) |
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| 56 | #define _PSB_CS_RESET_BIF_RESET (1 << 0) |
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| 57 | |
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| 58 | #define PSB_CR_DESIGNER_REV_FIELD2 0x001C |
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| 59 | |
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| 60 | #define PSB_CR_EVENT_HOST_ENABLE2 0x0110 |
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| 61 | |
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| 62 | #define PSB_CR_EVENT_STATUS2 0x0118 |
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| 63 | |
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| 64 | #define PSB_CR_EVENT_HOST_CLEAR2 0x0114 |
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| 65 | #define _PSB_CE2_BIF_REQUESTER_FAULT (1 << 4) |
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| 66 | |
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| 67 | #define PSB_CR_EVENT_STATUS 0x012C |
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| 68 | |
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| 69 | #define PSB_CR_EVENT_HOST_ENABLE 0x0130 |
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| 70 | |
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| 71 | #define PSB_CR_EVENT_HOST_CLEAR 0x0134 |
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| 72 | #define _PSB_CE_MASTER_INTERRUPT (1 << 31) |
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| 73 | #define _PSB_CE_TA_DPM_FAULT (1 << 28) |
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| 74 | #define _PSB_CE_TWOD_COMPLETE (1 << 27) |
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| 75 | #define _PSB_CE_DPM_OUT_OF_MEMORY_ZLS (1 << 25) |
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| 76 | #define _PSB_CE_DPM_TA_MEM_FREE (1 << 24) |
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| 77 | #define _PSB_CE_PIXELBE_END_RENDER (1 << 18) |
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| 78 | #define _PSB_CE_SW_EVENT (1 << 14) |
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| 79 | #define _PSB_CE_TA_FINISHED (1 << 13) |
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| 80 | #define _PSB_CE_TA_TERMINATE (1 << 12) |
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| 81 | #define _PSB_CE_DPM_REACHED_MEM_THRESH (1 << 3) |
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| 82 | #define _PSB_CE_DPM_OUT_OF_MEMORY_GBL (1 << 2) |
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| 83 | #define _PSB_CE_DPM_OUT_OF_MEMORY_MT (1 << 1) |
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| 84 | #define _PSB_CE_DPM_3D_MEM_FREE (1 << 0) |
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| 85 | |
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| 86 | |
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| 87 | #define PSB_USE_OFFSET_MASK 0x0007FFFF |
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| 88 | #define PSB_USE_OFFSET_SIZE (PSB_USE_OFFSET_MASK + 1) |
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| 89 | #define PSB_CR_USE_CODE_BASE0 0x0A0C |
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| 90 | #define PSB_CR_USE_CODE_BASE1 0x0A10 |
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| 91 | #define PSB_CR_USE_CODE_BASE2 0x0A14 |
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| 92 | #define PSB_CR_USE_CODE_BASE3 0x0A18 |
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| 93 | #define PSB_CR_USE_CODE_BASE4 0x0A1C |
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| 94 | #define PSB_CR_USE_CODE_BASE5 0x0A20 |
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| 95 | #define PSB_CR_USE_CODE_BASE6 0x0A24 |
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| 96 | #define PSB_CR_USE_CODE_BASE7 0x0A28 |
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| 97 | #define PSB_CR_USE_CODE_BASE8 0x0A2C |
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| 98 | #define PSB_CR_USE_CODE_BASE9 0x0A30 |
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| 99 | #define PSB_CR_USE_CODE_BASE10 0x0A34 |
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| 100 | #define PSB_CR_USE_CODE_BASE11 0x0A38 |
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| 101 | #define PSB_CR_USE_CODE_BASE12 0x0A3C |
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| 102 | #define PSB_CR_USE_CODE_BASE13 0x0A40 |
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| 103 | #define PSB_CR_USE_CODE_BASE14 0x0A44 |
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| 104 | #define PSB_CR_USE_CODE_BASE15 0x0A48 |
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| 105 | #define PSB_CR_USE_CODE_BASE(_i) (0x0A0C + ((_i) << 2)) |
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| 106 | #define _PSB_CUC_BASE_DM_SHIFT (25) |
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| 107 | #define _PSB_CUC_BASE_DM_MASK (0x3 << 25) |
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| 108 | #define _PSB_CUC_BASE_ADDR_SHIFT (0) /* 1024-bit aligned address? */ |
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| 109 | #define _PSB_CUC_BASE_ADDR_ALIGNSHIFT (7) |
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| 110 | #define _PSB_CUC_BASE_ADDR_MASK (0x1FFFFFF << 0) |
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| 111 | #define _PSB_CUC_DM_VERTEX (0) |
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| 112 | #define _PSB_CUC_DM_PIXEL (1) |
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| 113 | #define _PSB_CUC_DM_RESERVED (2) |
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| 114 | #define _PSB_CUC_DM_EDM (3) |
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| 115 | |
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| 116 | #define PSB_CR_PDS_EXEC_BASE 0x0AB8 |
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| 117 | #define _PSB_CR_PDS_EXEC_BASE_ADDR_SHIFT (20) /* 1MB aligned address */ |
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| 118 | #define _PSB_CR_PDS_EXEC_BASE_ADDR_ALIGNSHIFT (20) |
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| 119 | |
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| 120 | #define PSB_CR_EVENT_KICKER 0x0AC4 |
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| 121 | #define _PSB_CE_KICKER_ADDRESS_SHIFT (4) /* 128-bit aligned address */ |
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| 122 | |
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| 123 | #define PSB_CR_EVENT_KICK 0x0AC8 |
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| 124 | #define _PSB_CE_KICK_NOW (1 << 0) |
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| 125 | |
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| 126 | #define PSB_CR_BIF_DIR_LIST_BASE1 0x0C38 |
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| 127 | |
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| 128 | #define PSB_CR_BIF_CTRL 0x0C00 |
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| 129 | #define _PSB_CB_CTRL_CLEAR_FAULT (1 << 4) |
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| 130 | #define _PSB_CB_CTRL_INVALDC (1 << 3) |
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| 131 | #define _PSB_CB_CTRL_FLUSH (1 << 2) |
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| 132 | |
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| 133 | #define PSB_CR_BIF_INT_STAT 0x0C04 |
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| 134 | |
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| 135 | #define PSB_CR_BIF_FAULT 0x0C08 |
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| 136 | #define _PSB_CBI_STAT_PF_N_RW (1 << 14) |
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| 137 | #define _PSB_CBI_STAT_FAULT_SHIFT (0) |
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| 138 | #define _PSB_CBI_STAT_FAULT_MASK (0x3FFF << 0) |
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| 139 | #define _PSB_CBI_STAT_FAULT_CACHE (1 << 1) |
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| 140 | #define _PSB_CBI_STAT_FAULT_TA (1 << 2) |
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| 141 | #define _PSB_CBI_STAT_FAULT_VDM (1 << 3) |
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| 142 | #define _PSB_CBI_STAT_FAULT_2D (1 << 4) |
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| 143 | #define _PSB_CBI_STAT_FAULT_PBE (1 << 5) |
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| 144 | #define _PSB_CBI_STAT_FAULT_TSP (1 << 6) |
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| 145 | #define _PSB_CBI_STAT_FAULT_ISP (1 << 7) |
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| 146 | #define _PSB_CBI_STAT_FAULT_USSEPDS (1 << 8) |
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| 147 | #define _PSB_CBI_STAT_FAULT_HOST (1 << 9) |
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| 148 | |
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| 149 | #define PSB_CR_BIF_BANK0 0x0C78 |
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| 150 | #define PSB_CR_BIF_BANK1 0x0C7C |
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| 151 | #define PSB_CR_BIF_DIR_LIST_BASE0 0x0C84 |
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| 152 | #define PSB_CR_BIF_TWOD_REQ_BASE 0x0C88 |
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| 153 | #define PSB_CR_BIF_3D_REQ_BASE 0x0CAC |
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| 154 | |
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| 155 | #define PSB_CR_2D_SOCIF 0x0E18 |
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| 156 | #define _PSB_C2_SOCIF_FREESPACE_SHIFT (0) |
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| 157 | #define _PSB_C2_SOCIF_FREESPACE_MASK (0xFF << 0) |
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| 158 | #define _PSB_C2_SOCIF_EMPTY (0x80 << 0) |
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| 159 | |
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| 160 | #define PSB_CR_2D_BLIT_STATUS 0x0E04 |
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| 161 | #define _PSB_C2B_STATUS_BUSY (1 << 24) |
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| 162 | #define _PSB_C2B_STATUS_COMPLETE_SHIFT (0) |
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| 163 | #define _PSB_C2B_STATUS_COMPLETE_MASK (0xFFFFFF << 0) |
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| 164 | |
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| 165 | /* |
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| 166 | * 2D defs. |
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| 167 | */ |
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| 168 | |
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| 169 | /* |
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| 170 | * 2D Slave Port Data : Block Header's Object Type |
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| 171 | */ |
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| 172 | |
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| 173 | #define PSB_2D_CLIP_BH (0x00000000) |
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| 174 | #define PSB_2D_PAT_BH (0x10000000) |
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| 175 | #define PSB_2D_CTRL_BH (0x20000000) |
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| 176 | #define PSB_2D_SRC_OFF_BH (0x30000000) |
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| 177 | #define PSB_2D_MASK_OFF_BH (0x40000000) |
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| 178 | #define PSB_2D_RESERVED1_BH (0x50000000) |
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| 179 | #define PSB_2D_RESERVED2_BH (0x60000000) |
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| 180 | #define PSB_2D_FENCE_BH (0x70000000) |
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| 181 | #define PSB_2D_BLIT_BH (0x80000000) |
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| 182 | #define PSB_2D_SRC_SURF_BH (0x90000000) |
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| 183 | #define PSB_2D_DST_SURF_BH (0xA0000000) |
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| 184 | #define PSB_2D_PAT_SURF_BH (0xB0000000) |
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| 185 | #define PSB_2D_SRC_PAL_BH (0xC0000000) |
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| 186 | #define PSB_2D_PAT_PAL_BH (0xD0000000) |
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| 187 | #define PSB_2D_MASK_SURF_BH (0xE0000000) |
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| 188 | #define PSB_2D_FLUSH_BH (0xF0000000) |
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| 189 | |
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| 190 | /* |
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| 191 | * Clip Definition block (PSB_2D_CLIP_BH) |
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| 192 | */ |
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| 193 | #define PSB_2D_CLIPCOUNT_MAX (1) |
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| 194 | #define PSB_2D_CLIPCOUNT_MASK (0x00000000) |
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| 195 | #define PSB_2D_CLIPCOUNT_CLRMASK (0xFFFFFFFF) |
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| 196 | #define PSB_2D_CLIPCOUNT_SHIFT (0) |
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| 197 | /* clip rectangle min & max */ |
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| 198 | #define PSB_2D_CLIP_XMAX_MASK (0x00FFF000) |
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| 199 | #define PSB_2D_CLIP_XMAX_CLRMASK (0xFF000FFF) |
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| 200 | #define PSB_2D_CLIP_XMAX_SHIFT (12) |
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| 201 | #define PSB_2D_CLIP_XMIN_MASK (0x00000FFF) |
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| 202 | #define PSB_2D_CLIP_XMIN_CLRMASK (0x00FFF000) |
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| 203 | #define PSB_2D_CLIP_XMIN_SHIFT (0) |
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| 204 | /* clip rectangle offset */ |
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| 205 | #define PSB_2D_CLIP_YMAX_MASK (0x00FFF000) |
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| 206 | #define PSB_2D_CLIP_YMAX_CLRMASK (0xFF000FFF) |
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| 207 | #define PSB_2D_CLIP_YMAX_SHIFT (12) |
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| 208 | #define PSB_2D_CLIP_YMIN_MASK (0x00000FFF) |
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| 209 | #define PSB_2D_CLIP_YMIN_CLRMASK (0x00FFF000) |
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| 210 | #define PSB_2D_CLIP_YMIN_SHIFT (0) |
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| 211 | |
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| 212 | /* |
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| 213 | * Pattern Control (PSB_2D_PAT_BH) |
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| 214 | */ |
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| 215 | #define PSB_2D_PAT_HEIGHT_MASK (0x0000001F) |
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| 216 | #define PSB_2D_PAT_HEIGHT_SHIFT (0) |
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| 217 | #define PSB_2D_PAT_WIDTH_MASK (0x000003E0) |
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| 218 | #define PSB_2D_PAT_WIDTH_SHIFT (5) |
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| 219 | #define PSB_2D_PAT_YSTART_MASK (0x00007C00) |
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| 220 | #define PSB_2D_PAT_YSTART_SHIFT (10) |
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| 221 | #define PSB_2D_PAT_XSTART_MASK (0x000F8000) |
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| 222 | #define PSB_2D_PAT_XSTART_SHIFT (15) |
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| 223 | |
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| 224 | /* |
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| 225 | * 2D Control block (PSB_2D_CTRL_BH) |
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| 226 | */ |
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| 227 | /* Present Flags */ |
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| 228 | #define PSB_2D_SRCCK_CTRL (0x00000001) |
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| 229 | #define PSB_2D_DSTCK_CTRL (0x00000002) |
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| 230 | #define PSB_2D_ALPHA_CTRL (0x00000004) |
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| 231 | /* Colour Key Colour (SRC/DST)*/ |
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| 232 | #define PSB_2D_CK_COL_MASK (0xFFFFFFFF) |
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| 233 | #define PSB_2D_CK_COL_CLRMASK (0x00000000) |
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| 234 | #define PSB_2D_CK_COL_SHIFT (0) |
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| 235 | /* Colour Key Mask (SRC/DST)*/ |
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| 236 | #define PSB_2D_CK_MASK_MASK (0xFFFFFFFF) |
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| 237 | #define PSB_2D_CK_MASK_CLRMASK (0x00000000) |
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| 238 | #define PSB_2D_CK_MASK_SHIFT (0) |
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| 239 | /* Alpha Control (Alpha/RGB)*/ |
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| 240 | #define PSB_2D_GBLALPHA_MASK (0x000FF000) |
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| 241 | #define PSB_2D_GBLALPHA_CLRMASK (0xFFF00FFF) |
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| 242 | #define PSB_2D_GBLALPHA_SHIFT (12) |
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| 243 | #define PSB_2D_SRCALPHA_OP_MASK (0x00700000) |
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| 244 | #define PSB_2D_SRCALPHA_OP_CLRMASK (0xFF8FFFFF) |
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| 245 | #define PSB_2D_SRCALPHA_OP_SHIFT (20) |
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| 246 | #define PSB_2D_SRCALPHA_OP_ONE (0x00000000) |
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| 247 | #define PSB_2D_SRCALPHA_OP_SRC (0x00100000) |
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| 248 | #define PSB_2D_SRCALPHA_OP_DST (0x00200000) |
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| 249 | #define PSB_2D_SRCALPHA_OP_SG (0x00300000) |
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| 250 | #define PSB_2D_SRCALPHA_OP_DG (0x00400000) |
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| 251 | #define PSB_2D_SRCALPHA_OP_GBL (0x00500000) |
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| 252 | #define PSB_2D_SRCALPHA_OP_ZERO (0x00600000) |
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| 253 | #define PSB_2D_SRCALPHA_INVERT (0x00800000) |
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| 254 | #define PSB_2D_SRCALPHA_INVERT_CLR (0xFF7FFFFF) |
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| 255 | #define PSB_2D_DSTALPHA_OP_MASK (0x07000000) |
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| 256 | #define PSB_2D_DSTALPHA_OP_CLRMASK (0xF8FFFFFF) |
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| 257 | #define PSB_2D_DSTALPHA_OP_SHIFT (24) |
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| 258 | #define PSB_2D_DSTALPHA_OP_ONE (0x00000000) |
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| 259 | #define PSB_2D_DSTALPHA_OP_SRC (0x01000000) |
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| 260 | #define PSB_2D_DSTALPHA_OP_DST (0x02000000) |
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| 261 | #define PSB_2D_DSTALPHA_OP_SG (0x03000000) |
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| 262 | #define PSB_2D_DSTALPHA_OP_DG (0x04000000) |
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| 263 | #define PSB_2D_DSTALPHA_OP_GBL (0x05000000) |
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| 264 | #define PSB_2D_DSTALPHA_OP_ZERO (0x06000000) |
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| 265 | #define PSB_2D_DSTALPHA_INVERT (0x08000000) |
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| 266 | #define PSB_2D_DSTALPHA_INVERT_CLR (0xF7FFFFFF) |
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| 267 | |
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| 268 | #define PSB_2D_PRE_MULTIPLICATION_ENABLE (0x10000000) |
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| 269 | #define PSB_2D_PRE_MULTIPLICATION_CLRMASK (0xEFFFFFFF) |
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| 270 | #define PSB_2D_ZERO_SOURCE_ALPHA_ENABLE (0x20000000) |
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| 271 | #define PSB_2D_ZERO_SOURCE_ALPHA_CLRMASK (0xDFFFFFFF) |
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| 272 | |
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| 273 | /* |
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| 274 | *Source Offset (PSB_2D_SRC_OFF_BH) |
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| 275 | */ |
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| 276 | #define PSB_2D_SRCOFF_XSTART_MASK ((0x00000FFF) << 12) |
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| 277 | #define PSB_2D_SRCOFF_XSTART_SHIFT (12) |
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| 278 | #define PSB_2D_SRCOFF_YSTART_MASK (0x00000FFF) |
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| 279 | #define PSB_2D_SRCOFF_YSTART_SHIFT (0) |
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| 280 | |
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| 281 | /* |
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| 282 | * Mask Offset (PSB_2D_MASK_OFF_BH) |
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| 283 | */ |
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| 284 | #define PSB_2D_MASKOFF_XSTART_MASK ((0x00000FFF) << 12) |
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| 285 | #define PSB_2D_MASKOFF_XSTART_SHIFT (12) |
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| 286 | #define PSB_2D_MASKOFF_YSTART_MASK (0x00000FFF) |
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| 287 | #define PSB_2D_MASKOFF_YSTART_SHIFT (0) |
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| 288 | |
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| 289 | /* |
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| 290 | * 2D Fence (see PSB_2D_FENCE_BH): bits 0:27 are ignored |
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| 291 | */ |
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| 292 | |
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| 293 | /* |
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| 294 | *Blit Rectangle (PSB_2D_BLIT_BH) |
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| 295 | */ |
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| 296 | |
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| 297 | #define PSB_2D_ROT_MASK (3 << 25) |
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| 298 | #define PSB_2D_ROT_CLRMASK (~PSB_2D_ROT_MASK) |
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| 299 | #define PSB_2D_ROT_NONE (0 << 25) |
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| 300 | #define PSB_2D_ROT_90DEGS (1 << 25) |
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| 301 | #define PSB_2D_ROT_180DEGS (2 << 25) |
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| 302 | #define PSB_2D_ROT_270DEGS (3 << 25) |
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| 303 | |
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| 304 | #define PSB_2D_COPYORDER_MASK (3 << 23) |
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| 305 | #define PSB_2D_COPYORDER_CLRMASK (~PSB_2D_COPYORDER_MASK) |
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| 306 | #define PSB_2D_COPYORDER_TL2BR (0 << 23) |
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| 307 | #define PSB_2D_COPYORDER_BR2TL (1 << 23) |
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| 308 | #define PSB_2D_COPYORDER_TR2BL (2 << 23) |
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| 309 | #define PSB_2D_COPYORDER_BL2TR (3 << 23) |
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| 310 | |
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| 311 | #define PSB_2D_DSTCK_CLRMASK (0xFF9FFFFF) |
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| 312 | #define PSB_2D_DSTCK_DISABLE (0x00000000) |
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| 313 | #define PSB_2D_DSTCK_PASS (0x00200000) |
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| 314 | #define PSB_2D_DSTCK_REJECT (0x00400000) |
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| 315 | |
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| 316 | #define PSB_2D_SRCCK_CLRMASK (0xFFE7FFFF) |
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| 317 | #define PSB_2D_SRCCK_DISABLE (0x00000000) |
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| 318 | #define PSB_2D_SRCCK_PASS (0x00080000) |
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| 319 | #define PSB_2D_SRCCK_REJECT (0x00100000) |
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| 320 | |
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| 321 | #define PSB_2D_CLIP_ENABLE (0x00040000) |
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| 322 | |
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| 323 | #define PSB_2D_ALPHA_ENABLE (0x00020000) |
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| 324 | |
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| 325 | #define PSB_2D_PAT_CLRMASK (0xFFFEFFFF) |
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| 326 | #define PSB_2D_PAT_MASK (0x00010000) |
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| 327 | #define PSB_2D_USE_PAT (0x00010000) |
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| 328 | #define PSB_2D_USE_FILL (0x00000000) |
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| 329 | /* |
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| 330 | * Tungsten Graphics note on rop codes: If rop A and rop B are |
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| 331 | * identical, the mask surface will not be read and need not be |
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| 332 | * set up. |
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| 333 | */ |
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| 334 | |
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| 335 | #define PSB_2D_ROP3B_MASK (0x0000FF00) |
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| 336 | #define PSB_2D_ROP3B_CLRMASK (0xFFFF00FF) |
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| 337 | #define PSB_2D_ROP3B_SHIFT (8) |
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| 338 | /* rop code A */ |
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| 339 | #define PSB_2D_ROP3A_MASK (0x000000FF) |
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| 340 | #define PSB_2D_ROP3A_CLRMASK (0xFFFFFF00) |
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| 341 | #define PSB_2D_ROP3A_SHIFT (0) |
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| 342 | |
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| 343 | #define PSB_2D_ROP4_MASK (0x0000FFFF) |
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| 344 | /* |
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| 345 | * DWORD0: (Only pass if Pattern control == Use Fill Colour) |
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| 346 | * Fill Colour RGBA8888 |
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| 347 | */ |
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| 348 | #define PSB_2D_FILLCOLOUR_MASK (0xFFFFFFFF) |
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| 349 | #define PSB_2D_FILLCOLOUR_SHIFT (0) |
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| 350 | /* |
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| 351 | * DWORD1: (Always Present) |
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| 352 | * X Start (Dest) |
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| 353 | * Y Start (Dest) |
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| 354 | */ |
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| 355 | #define PSB_2D_DST_XSTART_MASK (0x00FFF000) |
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| 356 | #define PSB_2D_DST_XSTART_CLRMASK (0xFF000FFF) |
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| 357 | #define PSB_2D_DST_XSTART_SHIFT (12) |
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| 358 | #define PSB_2D_DST_YSTART_MASK (0x00000FFF) |
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| 359 | #define PSB_2D_DST_YSTART_CLRMASK (0xFFFFF000) |
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| 360 | #define PSB_2D_DST_YSTART_SHIFT (0) |
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| 361 | /* |
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| 362 | * DWORD2: (Always Present) |
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| 363 | * X Size (Dest) |
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| 364 | * Y Size (Dest) |
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| 365 | */ |
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| 366 | #define PSB_2D_DST_XSIZE_MASK (0x00FFF000) |
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| 367 | #define PSB_2D_DST_XSIZE_CLRMASK (0xFF000FFF) |
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| 368 | #define PSB_2D_DST_XSIZE_SHIFT (12) |
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| 369 | #define PSB_2D_DST_YSIZE_MASK (0x00000FFF) |
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| 370 | #define PSB_2D_DST_YSIZE_CLRMASK (0xFFFFF000) |
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| 371 | #define PSB_2D_DST_YSIZE_SHIFT (0) |
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| 372 | |
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| 373 | /* |
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| 374 | * Source Surface (PSB_2D_SRC_SURF_BH) |
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| 375 | */ |
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| 376 | /* |
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| 377 | * WORD 0 |
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| 378 | */ |
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| 379 | |
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| 380 | #define PSB_2D_SRC_FORMAT_MASK (0x00078000) |
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| 381 | #define PSB_2D_SRC_1_PAL (0x00000000) |
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| 382 | #define PSB_2D_SRC_2_PAL (0x00008000) |
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| 383 | #define PSB_2D_SRC_4_PAL (0x00010000) |
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| 384 | #define PSB_2D_SRC_8_PAL (0x00018000) |
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| 385 | #define PSB_2D_SRC_8_ALPHA (0x00020000) |
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| 386 | #define PSB_2D_SRC_4_ALPHA (0x00028000) |
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| 387 | #define PSB_2D_SRC_332RGB (0x00030000) |
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| 388 | #define PSB_2D_SRC_4444ARGB (0x00038000) |
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| 389 | #define PSB_2D_SRC_555RGB (0x00040000) |
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| 390 | #define PSB_2D_SRC_1555ARGB (0x00048000) |
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| 391 | #define PSB_2D_SRC_565RGB (0x00050000) |
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| 392 | #define PSB_2D_SRC_0888ARGB (0x00058000) |
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| 393 | #define PSB_2D_SRC_8888ARGB (0x00060000) |
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| 394 | #define PSB_2D_SRC_8888UYVY (0x00068000) |
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| 395 | #define PSB_2D_SRC_RESERVED (0x00070000) |
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| 396 | #define PSB_2D_SRC_1555ARGB_LOOKUP (0x00078000) |
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| 397 | |
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| 398 | |
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| 399 | #define PSB_2D_SRC_STRIDE_MASK (0x00007FFF) |
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| 400 | #define PSB_2D_SRC_STRIDE_CLRMASK (0xFFFF8000) |
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| 401 | #define PSB_2D_SRC_STRIDE_SHIFT (0) |
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| 402 | /* |
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| 403 | * WORD 1 - Base Address |
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| 404 | */ |
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| 405 | #define PSB_2D_SRC_ADDR_MASK (0x0FFFFFFC) |
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| 406 | #define PSB_2D_SRC_ADDR_CLRMASK (0x00000003) |
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| 407 | #define PSB_2D_SRC_ADDR_SHIFT (2) |
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| 408 | #define PSB_2D_SRC_ADDR_ALIGNSHIFT (2) |
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| 409 | |
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| 410 | /* |
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| 411 | * Pattern Surface (PSB_2D_PAT_SURF_BH) |
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| 412 | */ |
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| 413 | /* |
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| 414 | * WORD 0 |
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| 415 | */ |
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| 416 | |
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| 417 | #define PSB_2D_PAT_FORMAT_MASK (0x00078000) |
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| 418 | #define PSB_2D_PAT_1_PAL (0x00000000) |
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| 419 | #define PSB_2D_PAT_2_PAL (0x00008000) |
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| 420 | #define PSB_2D_PAT_4_PAL (0x00010000) |
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| 421 | #define PSB_2D_PAT_8_PAL (0x00018000) |
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| 422 | #define PSB_2D_PAT_8_ALPHA (0x00020000) |
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| 423 | #define PSB_2D_PAT_4_ALPHA (0x00028000) |
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| 424 | #define PSB_2D_PAT_332RGB (0x00030000) |
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| 425 | #define PSB_2D_PAT_4444ARGB (0x00038000) |
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| 426 | #define PSB_2D_PAT_555RGB (0x00040000) |
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| 427 | #define PSB_2D_PAT_1555ARGB (0x00048000) |
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| 428 | #define PSB_2D_PAT_565RGB (0x00050000) |
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| 429 | #define PSB_2D_PAT_0888ARGB (0x00058000) |
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| 430 | #define PSB_2D_PAT_8888ARGB (0x00060000) |
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| 431 | |
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| 432 | #define PSB_2D_PAT_STRIDE_MASK (0x00007FFF) |
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| 433 | #define PSB_2D_PAT_STRIDE_CLRMASK (0xFFFF8000) |
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| 434 | #define PSB_2D_PAT_STRIDE_SHIFT (0) |
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| 435 | /* |
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| 436 | * WORD 1 - Base Address |
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| 437 | */ |
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| 438 | #define PSB_2D_PAT_ADDR_MASK (0x0FFFFFFC) |
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| 439 | #define PSB_2D_PAT_ADDR_CLRMASK (0x00000003) |
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| 440 | #define PSB_2D_PAT_ADDR_SHIFT (2) |
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| 441 | #define PSB_2D_PAT_ADDR_ALIGNSHIFT (2) |
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| 442 | |
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| 443 | /* |
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| 444 | * Destination Surface (PSB_2D_DST_SURF_BH) |
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| 445 | */ |
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| 446 | /* |
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| 447 | * WORD 0 |
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| 448 | */ |
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| 449 | |
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| 450 | #define PSB_2D_DST_FORMAT_MASK (0x00078000) |
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| 451 | #define PSB_2D_DST_332RGB (0x00030000) |
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| 452 | #define PSB_2D_DST_4444ARGB (0x00038000) |
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| 453 | #define PSB_2D_DST_555RGB (0x00040000) |
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| 454 | #define PSB_2D_DST_1555ARGB (0x00048000) |
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| 455 | #define PSB_2D_DST_565RGB (0x00050000) |
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| 456 | #define PSB_2D_DST_0888ARGB (0x00058000) |
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| 457 | #define PSB_2D_DST_8888ARGB (0x00060000) |
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| 458 | #define PSB_2D_DST_8888AYUV (0x00070000) |
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| 459 | |
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| 460 | #define PSB_2D_DST_STRIDE_MASK (0x00007FFF) |
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| 461 | #define PSB_2D_DST_STRIDE_CLRMASK (0xFFFF8000) |
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| 462 | #define PSB_2D_DST_STRIDE_SHIFT (0) |
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| 463 | /* |
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| 464 | * WORD 1 - Base Address |
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| 465 | */ |
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| 466 | #define PSB_2D_DST_ADDR_MASK (0x0FFFFFFC) |
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| 467 | #define PSB_2D_DST_ADDR_CLRMASK (0x00000003) |
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| 468 | #define PSB_2D_DST_ADDR_SHIFT (2) |
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| 469 | #define PSB_2D_DST_ADDR_ALIGNSHIFT (2) |
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| 470 | |
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| 471 | /* |
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| 472 | * Mask Surface (PSB_2D_MASK_SURF_BH) |
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| 473 | */ |
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| 474 | /* |
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| 475 | * WORD 0 |
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| 476 | */ |
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| 477 | #define PSB_2D_MASK_STRIDE_MASK (0x00007FFF) |
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| 478 | #define PSB_2D_MASK_STRIDE_CLRMASK (0xFFFF8000) |
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| 479 | #define PSB_2D_MASK_STRIDE_SHIFT (0) |
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| 480 | /* |
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| 481 | * WORD 1 - Base Address |
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| 482 | */ |
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| 483 | #define PSB_2D_MASK_ADDR_MASK (0x0FFFFFFC) |
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| 484 | #define PSB_2D_MASK_ADDR_CLRMASK (0x00000003) |
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| 485 | #define PSB_2D_MASK_ADDR_SHIFT (2) |
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| 486 | #define PSB_2D_MASK_ADDR_ALIGNSHIFT (2) |
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| 487 | |
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| 488 | /* |
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| 489 | * Source Palette (PSB_2D_SRC_PAL_BH) |
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| 490 | */ |
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| 491 | |
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| 492 | #define PSB_2D_SRCPAL_ADDR_SHIFT (0) |
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| 493 | #define PSB_2D_SRCPAL_ADDR_CLRMASK (0xF0000007) |
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| 494 | #define PSB_2D_SRCPAL_ADDR_MASK (0x0FFFFFF8) |
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| 495 | #define PSB_2D_SRCPAL_BYTEALIGN (1024) |
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| 496 | |
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| 497 | /* |
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| 498 | * Pattern Palette (PSB_2D_PAT_PAL_BH) |
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| 499 | */ |
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| 500 | |
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| 501 | #define PSB_2D_PATPAL_ADDR_SHIFT (0) |
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| 502 | #define PSB_2D_PATPAL_ADDR_CLRMASK (0xF0000007) |
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| 503 | #define PSB_2D_PATPAL_ADDR_MASK (0x0FFFFFF8) |
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| 504 | #define PSB_2D_PATPAL_BYTEALIGN (1024) |
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| 505 | |
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| 506 | /* |
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| 507 | * Rop3 Codes (2 LS bytes) |
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| 508 | */ |
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| 509 | |
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| 510 | #define PSB_2D_ROP3_SRCCOPY (0xCCCC) |
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| 511 | #define PSB_2D_ROP3_PATCOPY (0xF0F0) |
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| 512 | #define PSB_2D_ROP3_WHITENESS (0xFFFF) |
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| 513 | #define PSB_2D_ROP3_BLACKNESS (0x0000) |
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| 514 | #define PSB_2D_ROP3_SRC (0xCC) |
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| 515 | #define PSB_2D_ROP3_PAT (0xF0) |
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| 516 | #define PSB_2D_ROP3_DST (0xAA) |
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| 517 | |
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| 518 | /* |
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| 519 | * Sizes. |
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| 520 | */ |
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| 521 | |
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| 522 | #define PSB_SCENE_HW_COOKIE_SIZE 16 |
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| 523 | #define PSB_TA_MEM_HW_COOKIE_SIZE 16 |
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| 524 | |
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| 525 | /* |
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| 526 | * Scene stuff. |
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| 527 | */ |
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| 528 | |
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| 529 | #define PSB_NUM_HW_SCENES 2 |
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| 530 | |
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| 531 | /* |
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| 532 | * Scheduler completion actions. |
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| 533 | */ |
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| 534 | |
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| 535 | #define PSB_RASTER_BLOCK 0 |
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| 536 | #define PSB_RASTER 1 |
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| 537 | #define PSB_RETURN 2 |
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| 538 | #define PSB_TA 3 |
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| 539 | |
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| 540 | /* Power management */ |
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| 541 | #define PSB_PUNIT_PORT 0x04 |
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| 542 | #define PSB_OSPMBA 0x78 |
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| 543 | #define PSB_APMBA 0x7a |
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| 544 | #define PSB_APM_CMD 0x0 |
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| 545 | #define PSB_APM_STS 0x04 |
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| 546 | #define PSB_PWRGT_VID_ENC_MASK 0x30 |
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| 547 | #define PSB_PWRGT_VID_DEC_MASK 0xc |
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| 548 | #define PSB_PWRGT_GL3_MASK 0xc0 |
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| 549 | |
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| 550 | #define PSB_PM_SSC 0x20 |
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| 551 | #define PSB_PM_SSS 0x30 |
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| 552 | #define PSB_PWRGT_DISPLAY_MASK 0xc /*on a different BA than video/gfx*/ |
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| 553 | /* Display SSS register bits are different in A0 vs. B0 */ |
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| 554 | #define PSB_PWRGT_GFX_MASK 0x3 |
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| 555 | #define PSB_PWRGT_GFX_MASK_B0 0xc3 |
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| 556 | #endif |
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| 557 | |
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