1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2019 Intel Corporation
4 */
5
6#ifndef __INTEL_CONTEXT_TYPES__
7#define __INTEL_CONTEXT_TYPES__
8
9#include <linux/average.h>
10#include <linux/kref.h>
11#include <linux/list.h>
12#include <linux/mutex.h>
13#include <linux/types.h>
14
15#include "i915_active_types.h"
16#include "i915_sw_fence.h"
17#include "i915_utils.h"
18#include "intel_engine_types.h"
19#include "intel_sseu.h"
20#include "intel_wakeref.h"
21
22#include "uc/intel_guc_fwif.h"
23
24#define CONTEXT_REDZONE POISON_INUSE
25DECLARE_EWMA(runtime, 3, 8);
26
27struct i915_gem_context;
28struct i915_gem_ww_ctx;
29struct i915_vma;
30struct intel_breadcrumbs;
31struct intel_context;
32struct intel_ring;
33
34struct intel_context_ops {
35 unsigned long flags;
36#define COPS_HAS_INFLIGHT_BIT 0
37#define COPS_HAS_INFLIGHT BIT(COPS_HAS_INFLIGHT_BIT)
38
39#define COPS_RUNTIME_CYCLES_BIT 1
40#define COPS_RUNTIME_CYCLES BIT(COPS_RUNTIME_CYCLES_BIT)
41
42 int (*alloc)(struct intel_context *ce);
43
44 void (*revoke)(struct intel_context *ce, struct i915_request *rq,
45 unsigned int preempt_timeout_ms);
46
47 void (*close)(struct intel_context *ce);
48
49 int (*pre_pin)(struct intel_context *ce, struct i915_gem_ww_ctx *ww, void **vaddr);
50 int (*pin)(struct intel_context *ce, void *vaddr);
51 void (*unpin)(struct intel_context *ce);
52 void (*post_unpin)(struct intel_context *ce);
53
54 void (*cancel_request)(struct intel_context *ce,
55 struct i915_request *rq);
56
57 void (*enter)(struct intel_context *ce);
58 void (*exit)(struct intel_context *ce);
59
60 void (*sched_disable)(struct intel_context *ce);
61
62 void (*update_stats)(struct intel_context *ce);
63
64 void (*reset)(struct intel_context *ce);
65 void (*destroy)(struct kref *kref);
66
67 /* virtual/parallel engine/context interface */
68 struct intel_context *(*create_virtual)(struct intel_engine_cs **engine,
69 unsigned int count,
70 unsigned long flags);
71 struct intel_context *(*create_parallel)(struct intel_engine_cs **engines,
72 unsigned int num_siblings,
73 unsigned int width);
74 struct intel_engine_cs *(*get_sibling)(struct intel_engine_cs *engine,
75 unsigned int sibling);
76};
77
78struct intel_context {
79 /*
80 * Note: Some fields may be accessed under RCU.
81 *
82 * Unless otherwise noted a field can safely be assumed to be protected
83 * by strong reference counting.
84 */
85 union {
86 struct kref ref; /* no kref_get_unless_zero()! */
87 struct rcu_head rcu;
88 };
89
90 struct intel_engine_cs *engine;
91 struct intel_engine_cs *inflight;
92#define __intel_context_inflight(engine) ptr_mask_bits(engine, 3)
93#define __intel_context_inflight_count(engine) ptr_unmask_bits(engine, 3)
94#define intel_context_inflight(ce) \
95 __intel_context_inflight(READ_ONCE((ce)->inflight))
96#define intel_context_inflight_count(ce) \
97 __intel_context_inflight_count(READ_ONCE((ce)->inflight))
98
99 struct i915_address_space *vm;
100 struct i915_gem_context __rcu *gem_context;
101
102 /*
103 * @signal_lock protects the list of requests that need signaling,
104 * @signals. While there are any requests that need signaling,
105 * we add the context to the breadcrumbs worker, and remove it
106 * upon completion/cancellation of the last request.
107 */
108 struct list_head signal_link; /* Accessed under RCU */
109 struct list_head signals; /* Guarded by signal_lock */
110 spinlock_t signal_lock; /* protects signals, the list of requests */
111
112 struct i915_vma *state;
113 u32 ring_size;
114 struct intel_ring *ring;
115 struct intel_timeline *timeline;
116 intel_wakeref_t wakeref;
117
118 unsigned long flags;
119#define CONTEXT_BARRIER_BIT 0
120#define CONTEXT_ALLOC_BIT 1
121#define CONTEXT_INIT_BIT 2
122#define CONTEXT_VALID_BIT 3
123#define CONTEXT_CLOSED_BIT 4
124#define CONTEXT_USE_SEMAPHORES 5
125#define CONTEXT_BANNED 6
126#define CONTEXT_FORCE_SINGLE_SUBMISSION 7
127#define CONTEXT_NOPREEMPT 8
128#define CONTEXT_LRCA_DIRTY 9
129#define CONTEXT_GUC_INIT 10
130#define CONTEXT_PERMA_PIN 11
131#define CONTEXT_IS_PARKING 12
132#define CONTEXT_EXITING 13
133
134 struct {
135 u64 timeout_us;
136 } watchdog;
137
138 u32 *lrc_reg_state;
139 union {
140 struct {
141 u32 lrca;
142 u32 ccid;
143 };
144 u64 desc;
145 } lrc;
146 u32 tag; /* cookie passed to HW to track this context on submission */
147
148 /** stats: Context GPU engine busyness tracking. */
149 struct intel_context_stats {
150 u64 active;
151
152 /* Time on GPU as tracked by the hw. */
153 struct {
154 struct ewma_runtime avg;
155 u64 total;
156 u32 last;
157 I915_SELFTEST_DECLARE(u32 num_underflow);
158 I915_SELFTEST_DECLARE(u32 max_underflow);
159 } runtime;
160 } stats;
161
162 unsigned int active_count; /* protected by timeline->mutex */
163
164 atomic_t pin_count;
165 struct mutex pin_mutex; /* guards pinning and associated on-gpuing */
166
167 /**
168 * active: Active tracker for the rq activity (inc. external) on this
169 * intel_context object.
170 */
171 struct i915_active active;
172
173 const struct intel_context_ops *ops;
174
175 /** sseu: Control eu/slice partitioning */
176 struct intel_sseu sseu;
177
178 /**
179 * pinned_contexts_link: List link for the engine's pinned contexts.
180 * This is only used if this is a perma-pinned kernel context and
181 * the list is assumed to only be manipulated during driver load
182 * or unload time so no mutex protection currently.
183 */
184 struct list_head pinned_contexts_link;
185
186 u8 wa_bb_page; /* if set, page num reserved for context workarounds */
187
188 struct {
189 /** @lock: protects everything in guc_state */
190 spinlock_t lock;
191 /**
192 * @sched_state: scheduling state of this context using GuC
193 * submission
194 */
195 u32 sched_state;
196 /*
197 * @fences: maintains a list of requests that are currently
198 * being fenced until a GuC operation completes
199 */
200 struct list_head fences;
201 /**
202 * @blocked: fence used to signal when the blocking of a
203 * context's submissions is complete.
204 */
205 struct i915_sw_fence blocked;
206 /** @requests: list of active requests on this context */
207 struct list_head requests;
208 /** @prio: the context's current guc priority */
209 u8 prio;
210 /**
211 * @prio_count: a counter of the number requests in flight in
212 * each priority bucket
213 */
214 u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
215 /**
216 * @sched_disable_delay_work: worker to disable scheduling on this
217 * context
218 */
219 struct delayed_work sched_disable_delay_work;
220 } guc_state;
221
222 struct {
223 /**
224 * @id: handle which is used to uniquely identify this context
225 * with the GuC, protected by guc->submission_state.lock
226 */
227 u16 id;
228 /**
229 * @ref: the number of references to the guc_id, when
230 * transitioning in and out of zero protected by
231 * guc->submission_state.lock
232 */
233 atomic_t ref;
234 /**
235 * @link: in guc->guc_id_list when the guc_id has no refs but is
236 * still valid, protected by guc->submission_state.lock
237 */
238 struct list_head link;
239 } guc_id;
240
241 /**
242 * @destroyed_link: link in guc->submission_state.destroyed_contexts, in
243 * list when context is pending to be destroyed (deregistered with the
244 * GuC), protected by guc->submission_state.lock
245 */
246 struct list_head destroyed_link;
247
248 /** @parallel: sub-structure for parallel submission members */
249 struct {
250 union {
251 /**
252 * @child_list: parent's list of children
253 * contexts, no protection as immutable after context
254 * creation
255 */
256 struct list_head child_list;
257 /**
258 * @child_link: child's link into parent's list of
259 * children
260 */
261 struct list_head child_link;
262 };
263 /** @parent: pointer to parent if child */
264 struct intel_context *parent;
265 /**
266 * @last_rq: last request submitted on a parallel context, used
267 * to insert submit fences between requests in the parallel
268 * context
269 */
270 struct i915_request *last_rq;
271 /**
272 * @fence_context: fence context composite fence when doing
273 * parallel submission
274 */
275 u64 fence_context;
276 /**
277 * @seqno: seqno for composite fence when doing parallel
278 * submission
279 */
280 u32 seqno;
281 /** @number_children: number of children if parent */
282 u8 number_children;
283 /** @child_index: index into child_list if child */
284 u8 child_index;
285 /** @guc: GuC specific members for parallel submission */
286 struct {
287 /** @wqi_head: cached head pointer in work queue */
288 u16 wqi_head;
289 /** @wqi_tail: cached tail pointer in work queue */
290 u16 wqi_tail;
291 /** @wq_head: pointer to the actual head in work queue */
292 u32 *wq_head;
293 /** @wq_tail: pointer to the actual head in work queue */
294 u32 *wq_tail;
295 /** @wq_status: pointer to the status in work queue */
296 u32 *wq_status;
297
298 /**
299 * @parent_page: page in context state (ce->state) used
300 * by parent for work queue, process descriptor
301 */
302 u8 parent_page;
303 } guc;
304 } parallel;
305
306#ifdef CONFIG_DRM_I915_SELFTEST
307 /**
308 * @drop_schedule_enable: Force drop of schedule enable G2H for selftest
309 */
310 bool drop_schedule_enable;
311
312 /**
313 * @drop_schedule_disable: Force drop of schedule disable G2H for
314 * selftest
315 */
316 bool drop_schedule_disable;
317
318 /**
319 * @drop_deregister: Force drop of deregister G2H for selftest
320 */
321 bool drop_deregister;
322#endif
323};
324
325#endif /* __INTEL_CONTEXT_TYPES__ */
326

source code of linux/drivers/gpu/drm/i915/gt/intel_context_types.h