1 | /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
2 | * All Rights Reserved. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the |
6 | * "Software"), to deal in the Software without restriction, including |
7 | * without limitation the rights to use, copy, modify, merge, publish, |
8 | * distribute, sub license, and/or sell copies of the Software, and to |
9 | * permit persons to whom the Software is furnished to do so, subject to |
10 | * the following conditions: |
11 | * |
12 | * The above copyright notice and this permission notice (including the |
13 | * next paragraph) shall be included in all copies or substantial portions |
14 | * of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
19 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
20 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
21 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
22 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
23 | */ |
24 | |
25 | #ifndef _I915_REG_H_ |
26 | #define _I915_REG_H_ |
27 | |
28 | #include "i915_reg_defs.h" |
29 | #include "display/intel_display_reg_defs.h" |
30 | |
31 | /** |
32 | * DOC: The i915 register macro definition style guide |
33 | * |
34 | * Follow the style described here for new macros, and while changing existing |
35 | * macros. Do **not** mass change existing definitions just to update the style. |
36 | * |
37 | * File Layout |
38 | * ~~~~~~~~~~~ |
39 | * |
40 | * Keep helper macros near the top. For example, _PIPE() and friends. |
41 | * |
42 | * Prefix macros that generally should not be used outside of this file with |
43 | * underscore '_'. For example, _PIPE() and friends, single instances of |
44 | * registers that are defined solely for the use by function-like macros. |
45 | * |
46 | * Avoid using the underscore prefixed macros outside of this file. There are |
47 | * exceptions, but keep them to a minimum. |
48 | * |
49 | * There are two basic types of register definitions: Single registers and |
50 | * register groups. Register groups are registers which have two or more |
51 | * instances, for example one per pipe, port, transcoder, etc. Register groups |
52 | * should be defined using function-like macros. |
53 | * |
54 | * For single registers, define the register offset first, followed by register |
55 | * contents. |
56 | * |
57 | * For register groups, define the register instance offsets first, prefixed |
58 | * with underscore, followed by a function-like macro choosing the right |
59 | * instance based on the parameter, followed by register contents. |
60 | * |
61 | * Define the register contents (i.e. bit and bit field macros) from most |
62 | * significant to least significant bit. Indent the register content macros |
63 | * using two extra spaces between ``#define`` and the macro name. |
64 | * |
65 | * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents |
66 | * using ``REG_FIELD_PREP(mask, value)``. This will define the values already |
67 | * shifted in place, so they can be directly OR'd together. For convenience, |
68 | * function-like macros may be used to define bit fields, but do note that the |
69 | * macros may be needed to read as well as write the register contents. |
70 | * |
71 | * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name. |
72 | * |
73 | * Group the register and its contents together without blank lines, separate |
74 | * from other registers and their contents with one blank line. |
75 | * |
76 | * Indent macro values from macro names using TABs. Align values vertically. Use |
77 | * braces in macro values as needed to avoid unintended precedence after macro |
78 | * substitution. Use spaces in macro values according to kernel coding |
79 | * style. Use lower case in hexadecimal values. |
80 | * |
81 | * Naming |
82 | * ~~~~~~ |
83 | * |
84 | * Try to name registers according to the specs. If the register name changes in |
85 | * the specs from platform to another, stick to the original name. |
86 | * |
87 | * Try to re-use existing register macro definitions. Only add new macros for |
88 | * new register offsets, or when the register contents have changed enough to |
89 | * warrant a full redefinition. |
90 | * |
91 | * When a register macro changes for a new platform, prefix the new macro using |
92 | * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The |
93 | * prefix signifies the start platform/generation using the register. |
94 | * |
95 | * When a bit (field) macro changes or gets added for a new platform, while |
96 | * retaining the existing register macro, add a platform acronym or generation |
97 | * suffix to the name. For example, ``_SKL`` or ``_GEN8``. |
98 | * |
99 | * Examples |
100 | * ~~~~~~~~ |
101 | * |
102 | * (Note that the values in the example are indented using spaces instead of |
103 | * TABs to avoid misalignment in generated documentation. Use TABs in the |
104 | * definitions.):: |
105 | * |
106 | * #define _FOO_A 0xf000 |
107 | * #define _FOO_B 0xf001 |
108 | * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) |
109 | * #define FOO_ENABLE REG_BIT(31) |
110 | * #define FOO_MODE_MASK REG_GENMASK(19, 16) |
111 | * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) |
112 | * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1) |
113 | * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2) |
114 | * |
115 | * #define BAR _MMIO(0xb000) |
116 | * #define GEN8_BAR _MMIO(0xb888) |
117 | */ |
118 | |
119 | #define GU_CNTL_PROTECTED _MMIO(0x10100C) |
120 | #define DEPRESENT REG_BIT(9) |
121 | |
122 | #define GU_CNTL _MMIO(0x101010) |
123 | #define LMEM_INIT REG_BIT(7) |
124 | #define DRIVERFLR REG_BIT(31) |
125 | #define GU_DEBUG _MMIO(0x101018) |
126 | #define DRIVERFLR_STATUS REG_BIT(31) |
127 | |
128 | #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0) |
129 | #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20) |
130 | #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18) |
131 | #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4) |
132 | #define GEN6_STOLEN_RESERVED_1M (0 << 4) |
133 | #define GEN6_STOLEN_RESERVED_512K (1 << 4) |
134 | #define GEN6_STOLEN_RESERVED_256K (2 << 4) |
135 | #define GEN6_STOLEN_RESERVED_128K (3 << 4) |
136 | #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5) |
137 | #define GEN7_STOLEN_RESERVED_1M (0 << 5) |
138 | #define GEN7_STOLEN_RESERVED_256K (1 << 5) |
139 | #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7) |
140 | #define GEN8_STOLEN_RESERVED_1M (0 << 7) |
141 | #define GEN8_STOLEN_RESERVED_2M (1 << 7) |
142 | #define GEN8_STOLEN_RESERVED_4M (2 << 7) |
143 | #define GEN8_STOLEN_RESERVED_8M (3 << 7) |
144 | #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0) |
145 | #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20) |
146 | |
147 | #define _VGA_MSR_WRITE _MMIO(0x3c2) |
148 | |
149 | #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 |
150 | #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 |
151 | #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) |
152 | |
153 | /* |
154 | * Reset registers |
155 | */ |
156 | #define DEBUG_RESET_I830 _MMIO(0x6070) |
157 | #define DEBUG_RESET_FULL (1 << 7) |
158 | #define DEBUG_RESET_RENDER (1 << 8) |
159 | #define DEBUG_RESET_DISPLAY (1 << 9) |
160 | |
161 | /* |
162 | * IOSF sideband |
163 | */ |
164 | #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) |
165 | #define IOSF_DEVFN_SHIFT 24 |
166 | #define IOSF_OPCODE_SHIFT 16 |
167 | #define IOSF_PORT_SHIFT 8 |
168 | #define IOSF_BYTE_ENABLES_SHIFT 4 |
169 | #define IOSF_BAR_SHIFT 1 |
170 | #define IOSF_SB_BUSY (1 << 0) |
171 | #define IOSF_PORT_BUNIT 0x03 |
172 | #define IOSF_PORT_PUNIT 0x04 |
173 | #define IOSF_PORT_NC 0x11 |
174 | #define IOSF_PORT_DPIO 0x12 |
175 | #define IOSF_PORT_GPIO_NC 0x13 |
176 | #define IOSF_PORT_CCK 0x14 |
177 | #define IOSF_PORT_DPIO_2 0x1a |
178 | #define IOSF_PORT_FLISDSI 0x1b |
179 | #define IOSF_PORT_GPIO_SC 0x48 |
180 | #define IOSF_PORT_GPIO_SUS 0xa8 |
181 | #define IOSF_PORT_CCU 0xa9 |
182 | #define CHV_IOSF_PORT_GPIO_N 0x13 |
183 | #define CHV_IOSF_PORT_GPIO_SE 0x48 |
184 | #define CHV_IOSF_PORT_GPIO_E 0xa8 |
185 | #define CHV_IOSF_PORT_GPIO_SW 0xb2 |
186 | #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) |
187 | #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) |
188 | |
189 | /* DPIO registers */ |
190 | #define DPIO_DEVFN 0 |
191 | |
192 | #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) |
193 | #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */ |
194 | #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */ |
195 | #define DPIO_SFR_BYPASS (1 << 1) |
196 | #define DPIO_CMNRST (1 << 0) |
197 | |
198 | #define DPIO_PHY(pipe) ((pipe) >> 1) |
199 | |
200 | /* |
201 | * Per pipe/PLL DPIO regs |
202 | */ |
203 | #define _VLV_PLL_DW3_CH0 0x800c |
204 | #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ |
205 | #define DPIO_POST_DIV_DAC 0 |
206 | #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ |
207 | #define DPIO_POST_DIV_LVDS1 2 |
208 | #define DPIO_POST_DIV_LVDS2 3 |
209 | #define DPIO_K_SHIFT (24) /* 4 bits */ |
210 | #define DPIO_P1_SHIFT (21) /* 3 bits */ |
211 | #define DPIO_P2_SHIFT (16) /* 5 bits */ |
212 | #define DPIO_N_SHIFT (12) /* 4 bits */ |
213 | #define DPIO_ENABLE_CALIBRATION (1 << 11) |
214 | #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ |
215 | #define DPIO_M2DIV_MASK 0xff |
216 | #define _VLV_PLL_DW3_CH1 0x802c |
217 | #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) |
218 | |
219 | #define _VLV_PLL_DW5_CH0 0x8014 |
220 | #define DPIO_REFSEL_OVERRIDE 27 |
221 | #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ |
222 | #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ |
223 | #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ |
224 | #define DPIO_PLL_REFCLK_SEL_MASK 3 |
225 | #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ |
226 | #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ |
227 | #define _VLV_PLL_DW5_CH1 0x8034 |
228 | #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) |
229 | |
230 | #define _VLV_PLL_DW7_CH0 0x801c |
231 | #define _VLV_PLL_DW7_CH1 0x803c |
232 | #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) |
233 | |
234 | #define _VLV_PLL_DW8_CH0 0x8040 |
235 | #define _VLV_PLL_DW8_CH1 0x8060 |
236 | #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) |
237 | |
238 | #define VLV_PLL_DW9_BCAST 0xc044 |
239 | #define _VLV_PLL_DW9_CH0 0x8044 |
240 | #define _VLV_PLL_DW9_CH1 0x8064 |
241 | #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) |
242 | |
243 | #define _VLV_PLL_DW10_CH0 0x8048 |
244 | #define _VLV_PLL_DW10_CH1 0x8068 |
245 | #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) |
246 | |
247 | #define _VLV_PLL_DW11_CH0 0x804c |
248 | #define _VLV_PLL_DW11_CH1 0x806c |
249 | #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) |
250 | |
251 | /* Spec for ref block start counts at DW10 */ |
252 | #define VLV_REF_DW13 0x80ac |
253 | |
254 | #define VLV_CMN_DW0 0x8100 |
255 | |
256 | /* |
257 | * Per DDI channel DPIO regs |
258 | */ |
259 | |
260 | #define _VLV_PCS_DW0_CH0 0x8200 |
261 | #define _VLV_PCS_DW0_CH1 0x8400 |
262 | #define DPIO_PCS_TX_LANE2_RESET (1 << 16) |
263 | #define DPIO_PCS_TX_LANE1_RESET (1 << 7) |
264 | #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4) |
265 | #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3) |
266 | #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) |
267 | |
268 | #define _VLV_PCS01_DW0_CH0 0x200 |
269 | #define _VLV_PCS23_DW0_CH0 0x400 |
270 | #define _VLV_PCS01_DW0_CH1 0x2600 |
271 | #define _VLV_PCS23_DW0_CH1 0x2800 |
272 | #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) |
273 | #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) |
274 | |
275 | #define _VLV_PCS_DW1_CH0 0x8204 |
276 | #define _VLV_PCS_DW1_CH1 0x8404 |
277 | #define CHV_PCS_REQ_SOFTRESET_EN (1 << 23) |
278 | #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22) |
279 | #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21) |
280 | #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) |
281 | #define DPIO_PCS_CLK_SOFT_RESET (1 << 5) |
282 | #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) |
283 | |
284 | #define _VLV_PCS01_DW1_CH0 0x204 |
285 | #define _VLV_PCS23_DW1_CH0 0x404 |
286 | #define _VLV_PCS01_DW1_CH1 0x2604 |
287 | #define _VLV_PCS23_DW1_CH1 0x2804 |
288 | #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) |
289 | #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) |
290 | |
291 | #define _VLV_PCS_DW8_CH0 0x8220 |
292 | #define _VLV_PCS_DW8_CH1 0x8420 |
293 | #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) |
294 | #define CHV_PCS_USEDCLKCHANNEL (1 << 21) |
295 | #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) |
296 | |
297 | #define _VLV_PCS01_DW8_CH0 0x0220 |
298 | #define _VLV_PCS23_DW8_CH0 0x0420 |
299 | #define _VLV_PCS01_DW8_CH1 0x2620 |
300 | #define _VLV_PCS23_DW8_CH1 0x2820 |
301 | #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) |
302 | #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) |
303 | |
304 | #define _VLV_PCS_DW9_CH0 0x8224 |
305 | #define _VLV_PCS_DW9_CH1 0x8424 |
306 | #define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13) |
307 | #define DPIO_PCS_TX2MARGIN_000 (0 << 13) |
308 | #define DPIO_PCS_TX2MARGIN_101 (1 << 13) |
309 | #define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10) |
310 | #define DPIO_PCS_TX1MARGIN_000 (0 << 10) |
311 | #define DPIO_PCS_TX1MARGIN_101 (1 << 10) |
312 | #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) |
313 | |
314 | #define _VLV_PCS01_DW9_CH0 0x224 |
315 | #define _VLV_PCS23_DW9_CH0 0x424 |
316 | #define _VLV_PCS01_DW9_CH1 0x2624 |
317 | #define _VLV_PCS23_DW9_CH1 0x2824 |
318 | #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) |
319 | #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) |
320 | |
321 | #define _CHV_PCS_DW10_CH0 0x8228 |
322 | #define _CHV_PCS_DW10_CH1 0x8428 |
323 | #define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30) |
324 | #define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31) |
325 | #define DPIO_PCS_TX2DEEMP_MASK (0xf << 24) |
326 | #define DPIO_PCS_TX2DEEMP_9P5 (0 << 24) |
327 | #define DPIO_PCS_TX2DEEMP_6P0 (2 << 24) |
328 | #define DPIO_PCS_TX1DEEMP_MASK (0xf << 16) |
329 | #define DPIO_PCS_TX1DEEMP_9P5 (0 << 16) |
330 | #define DPIO_PCS_TX1DEEMP_6P0 (2 << 16) |
331 | #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) |
332 | |
333 | #define _VLV_PCS01_DW10_CH0 0x0228 |
334 | #define _VLV_PCS23_DW10_CH0 0x0428 |
335 | #define _VLV_PCS01_DW10_CH1 0x2628 |
336 | #define _VLV_PCS23_DW10_CH1 0x2828 |
337 | #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) |
338 | #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) |
339 | |
340 | #define _VLV_PCS_DW11_CH0 0x822c |
341 | #define _VLV_PCS_DW11_CH1 0x842c |
342 | #define DPIO_TX2_STAGGER_MASK(x) ((x) << 24) |
343 | #define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3) |
344 | #define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1) |
345 | #define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0) |
346 | #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) |
347 | |
348 | #define _VLV_PCS01_DW11_CH0 0x022c |
349 | #define _VLV_PCS23_DW11_CH0 0x042c |
350 | #define _VLV_PCS01_DW11_CH1 0x262c |
351 | #define _VLV_PCS23_DW11_CH1 0x282c |
352 | #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) |
353 | #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) |
354 | |
355 | #define _VLV_PCS01_DW12_CH0 0x0230 |
356 | #define _VLV_PCS23_DW12_CH0 0x0430 |
357 | #define _VLV_PCS01_DW12_CH1 0x2630 |
358 | #define _VLV_PCS23_DW12_CH1 0x2830 |
359 | #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1) |
360 | #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1) |
361 | |
362 | #define _VLV_PCS_DW12_CH0 0x8230 |
363 | #define _VLV_PCS_DW12_CH1 0x8430 |
364 | #define DPIO_TX2_STAGGER_MULT(x) ((x) << 20) |
365 | #define DPIO_TX1_STAGGER_MULT(x) ((x) << 16) |
366 | #define DPIO_TX1_STAGGER_MASK(x) ((x) << 8) |
367 | #define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6) |
368 | #define DPIO_LANESTAGGER_STRAP(x) ((x) << 0) |
369 | #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) |
370 | |
371 | #define _VLV_PCS_DW14_CH0 0x8238 |
372 | #define _VLV_PCS_DW14_CH1 0x8438 |
373 | #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) |
374 | |
375 | #define _VLV_PCS_DW23_CH0 0x825c |
376 | #define _VLV_PCS_DW23_CH1 0x845c |
377 | #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) |
378 | |
379 | #define _VLV_TX_DW2_CH0 0x8288 |
380 | #define _VLV_TX_DW2_CH1 0x8488 |
381 | #define DPIO_SWING_MARGIN000_SHIFT 16 |
382 | #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) |
383 | #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 |
384 | #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) |
385 | |
386 | #define _VLV_TX_DW3_CH0 0x828c |
387 | #define _VLV_TX_DW3_CH1 0x848c |
388 | /* The following bit for CHV phy */ |
389 | #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27) |
390 | #define DPIO_SWING_MARGIN101_SHIFT 16 |
391 | #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) |
392 | #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) |
393 | |
394 | #define _VLV_TX_DW4_CH0 0x8290 |
395 | #define _VLV_TX_DW4_CH1 0x8490 |
396 | #define DPIO_SWING_DEEMPH9P5_SHIFT 24 |
397 | #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) |
398 | #define DPIO_SWING_DEEMPH6P0_SHIFT 16 |
399 | #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) |
400 | #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) |
401 | |
402 | #define _VLV_TX3_DW4_CH0 0x690 |
403 | #define _VLV_TX3_DW4_CH1 0x2a90 |
404 | #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) |
405 | |
406 | #define _VLV_TX_DW5_CH0 0x8294 |
407 | #define _VLV_TX_DW5_CH1 0x8494 |
408 | #define DPIO_TX_OCALINIT_EN (1 << 31) |
409 | #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) |
410 | |
411 | #define _VLV_TX_DW11_CH0 0x82ac |
412 | #define _VLV_TX_DW11_CH1 0x84ac |
413 | #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) |
414 | |
415 | #define _VLV_TX_DW14_CH0 0x82b8 |
416 | #define _VLV_TX_DW14_CH1 0x84b8 |
417 | #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) |
418 | |
419 | /* CHV dpPhy registers */ |
420 | #define _CHV_PLL_DW0_CH0 0x8000 |
421 | #define _CHV_PLL_DW0_CH1 0x8180 |
422 | #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) |
423 | |
424 | #define _CHV_PLL_DW1_CH0 0x8004 |
425 | #define _CHV_PLL_DW1_CH1 0x8184 |
426 | #define DPIO_CHV_N_DIV_SHIFT 8 |
427 | #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) |
428 | #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) |
429 | |
430 | #define _CHV_PLL_DW2_CH0 0x8008 |
431 | #define _CHV_PLL_DW2_CH1 0x8188 |
432 | #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) |
433 | |
434 | #define _CHV_PLL_DW3_CH0 0x800c |
435 | #define _CHV_PLL_DW3_CH1 0x818c |
436 | #define DPIO_CHV_FRAC_DIV_EN (1 << 16) |
437 | #define DPIO_CHV_FIRST_MOD (0 << 8) |
438 | #define DPIO_CHV_SECOND_MOD (1 << 8) |
439 | #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 |
440 | #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0) |
441 | #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) |
442 | |
443 | #define _CHV_PLL_DW6_CH0 0x8018 |
444 | #define _CHV_PLL_DW6_CH1 0x8198 |
445 | #define DPIO_CHV_GAIN_CTRL_SHIFT 16 |
446 | #define DPIO_CHV_INT_COEFF_SHIFT 8 |
447 | #define DPIO_CHV_PROP_COEFF_SHIFT 0 |
448 | #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) |
449 | |
450 | #define _CHV_PLL_DW8_CH0 0x8020 |
451 | #define _CHV_PLL_DW8_CH1 0x81A0 |
452 | #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0 |
453 | #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0) |
454 | #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1) |
455 | |
456 | #define _CHV_PLL_DW9_CH0 0x8024 |
457 | #define _CHV_PLL_DW9_CH1 0x81A4 |
458 | #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */ |
459 | #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1) |
460 | #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */ |
461 | #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1) |
462 | |
463 | #define _CHV_CMN_DW0_CH0 0x8100 |
464 | #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19 |
465 | #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18 |
466 | #define DPIO_ALLDL_POWERDOWN (1 << 1) |
467 | #define DPIO_ANYDL_POWERDOWN (1 << 0) |
468 | |
469 | #define _CHV_CMN_DW5_CH0 0x8114 |
470 | #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) |
471 | #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) |
472 | #define CHV_BUFRIGHTENA1_FORCE (3 << 20) |
473 | #define CHV_BUFRIGHTENA1_MASK (3 << 20) |
474 | #define CHV_BUFLEFTENA1_DISABLE (0 << 22) |
475 | #define CHV_BUFLEFTENA1_NORMAL (1 << 22) |
476 | #define CHV_BUFLEFTENA1_FORCE (3 << 22) |
477 | #define CHV_BUFLEFTENA1_MASK (3 << 22) |
478 | |
479 | #define _CHV_CMN_DW13_CH0 0x8134 |
480 | #define _CHV_CMN_DW0_CH1 0x8080 |
481 | #define DPIO_CHV_S1_DIV_SHIFT 21 |
482 | #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ |
483 | #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ |
484 | #define DPIO_CHV_K_DIV_SHIFT 4 |
485 | #define DPIO_PLL_FREQLOCK (1 << 1) |
486 | #define DPIO_PLL_LOCK (1 << 0) |
487 | #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) |
488 | |
489 | #define _CHV_CMN_DW14_CH0 0x8138 |
490 | #define _CHV_CMN_DW1_CH1 0x8084 |
491 | #define DPIO_AFC_RECAL (1 << 14) |
492 | #define DPIO_DCLKP_EN (1 << 13) |
493 | #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ |
494 | #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ |
495 | #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ |
496 | #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ |
497 | #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ |
498 | #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ |
499 | #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ |
500 | #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ |
501 | #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) |
502 | |
503 | #define _CHV_CMN_DW19_CH0 0x814c |
504 | #define _CHV_CMN_DW6_CH1 0x8098 |
505 | #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */ |
506 | #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */ |
507 | #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */ |
508 | #define CHV_CMN_USEDCLKCHANNEL (1 << 13) |
509 | |
510 | #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) |
511 | |
512 | #define CHV_CMN_DW28 0x8170 |
513 | #define DPIO_CL1POWERDOWNEN (1 << 23) |
514 | #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22) |
515 | #define DPIO_SUS_CLK_CONFIG_ON (0 << 0) |
516 | #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0) |
517 | #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0) |
518 | #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0) |
519 | |
520 | #define CHV_CMN_DW30 0x8178 |
521 | #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6) |
522 | #define DPIO_LRC_BYPASS (1 << 3) |
523 | |
524 | #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ |
525 | (lane) * 0x200 + (offset)) |
526 | |
527 | #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) |
528 | #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) |
529 | #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) |
530 | #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) |
531 | #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) |
532 | #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) |
533 | #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) |
534 | #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) |
535 | #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) |
536 | #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) |
537 | #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) |
538 | #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) |
539 | #define DPIO_FRC_LATENCY_SHFIT 8 |
540 | #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) |
541 | #define DPIO_UPAR_SHIFT 30 |
542 | |
543 | /* BXT PHY registers */ |
544 | #define _BXT_PHY0_BASE 0x6C000 |
545 | #define _BXT_PHY1_BASE 0x162000 |
546 | #define _BXT_PHY2_BASE 0x163000 |
547 | #define BXT_PHY_BASE(phy) \ |
548 | _PICK_EVEN_2RANGES(phy, 1, \ |
549 | _BXT_PHY0_BASE, _BXT_PHY0_BASE, \ |
550 | _BXT_PHY1_BASE, _BXT_PHY2_BASE) |
551 | |
552 | #define _BXT_PHY(phy, reg) \ |
553 | _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg)) |
554 | |
555 | #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ |
556 | (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \ |
557 | (reg_ch1) - _BXT_PHY0_BASE)) |
558 | #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ |
559 | _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)) |
560 | |
561 | #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) |
562 | #define MIPIO_RST_CTRL (1 << 2) |
563 | |
564 | #define _BXT_PHY_CTL_DDI_A 0x64C00 |
565 | #define _BXT_PHY_CTL_DDI_B 0x64C10 |
566 | #define _BXT_PHY_CTL_DDI_C 0x64C20 |
567 | #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10) |
568 | #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9) |
569 | #define BXT_PHY_LANE_ENABLED (1 << 8) |
570 | #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \ |
571 | _BXT_PHY_CTL_DDI_B) |
572 | |
573 | #define _PHY_CTL_FAMILY_DDI 0x64C90 |
574 | #define _PHY_CTL_FAMILY_EDP 0x64C80 |
575 | #define _PHY_CTL_FAMILY_DDI_C 0x64CA0 |
576 | #define COMMON_RESET_DIS (1 << 31) |
577 | #define BXT_PHY_CTL_FAMILY(phy) \ |
578 | _MMIO(_PICK_EVEN_2RANGES(phy, 1, \ |
579 | _PHY_CTL_FAMILY_DDI, _PHY_CTL_FAMILY_DDI, \ |
580 | _PHY_CTL_FAMILY_EDP, _PHY_CTL_FAMILY_DDI_C)) |
581 | |
582 | /* BXT PHY PLL registers */ |
583 | #define _PORT_PLL_A 0x46074 |
584 | #define _PORT_PLL_B 0x46078 |
585 | #define _PORT_PLL_C 0x4607c |
586 | #define PORT_PLL_ENABLE REG_BIT(31) |
587 | #define PORT_PLL_LOCK REG_BIT(30) |
588 | #define PORT_PLL_REF_SEL REG_BIT(27) |
589 | #define PORT_PLL_POWER_ENABLE REG_BIT(26) |
590 | #define PORT_PLL_POWER_STATE REG_BIT(25) |
591 | #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B) |
592 | |
593 | #define _PORT_PLL_EBB_0_A 0x162034 |
594 | #define _PORT_PLL_EBB_0_B 0x6C034 |
595 | #define _PORT_PLL_EBB_0_C 0x6C340 |
596 | #define PORT_PLL_P1_MASK REG_GENMASK(15, 13) |
597 | #define PORT_PLL_P1(p1) REG_FIELD_PREP(PORT_PLL_P1_MASK, (p1)) |
598 | #define PORT_PLL_P2_MASK REG_GENMASK(12, 8) |
599 | #define PORT_PLL_P2(p2) REG_FIELD_PREP(PORT_PLL_P2_MASK, (p2)) |
600 | #define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
601 | _PORT_PLL_EBB_0_B, \ |
602 | _PORT_PLL_EBB_0_C) |
603 | |
604 | #define _PORT_PLL_EBB_4_A 0x162038 |
605 | #define _PORT_PLL_EBB_4_B 0x6C038 |
606 | #define _PORT_PLL_EBB_4_C 0x6C344 |
607 | #define PORT_PLL_RECALIBRATE REG_BIT(14) |
608 | #define PORT_PLL_10BIT_CLK_ENABLE REG_BIT(13) |
609 | #define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
610 | _PORT_PLL_EBB_4_B, \ |
611 | _PORT_PLL_EBB_4_C) |
612 | |
613 | #define _PORT_PLL_0_A 0x162100 |
614 | #define _PORT_PLL_0_B 0x6C100 |
615 | #define _PORT_PLL_0_C 0x6C380 |
616 | /* PORT_PLL_0_A */ |
617 | #define PORT_PLL_M2_INT_MASK REG_GENMASK(7, 0) |
618 | #define PORT_PLL_M2_INT(m2_int) REG_FIELD_PREP(PORT_PLL_M2_INT_MASK, (m2_int)) |
619 | /* PORT_PLL_1_A */ |
620 | #define PORT_PLL_N_MASK REG_GENMASK(11, 8) |
621 | #define PORT_PLL_N(n) REG_FIELD_PREP(PORT_PLL_N_MASK, (n)) |
622 | /* PORT_PLL_2_A */ |
623 | #define PORT_PLL_M2_FRAC_MASK REG_GENMASK(21, 0) |
624 | #define PORT_PLL_M2_FRAC(m2_frac) REG_FIELD_PREP(PORT_PLL_M2_FRAC_MASK, (m2_frac)) |
625 | /* PORT_PLL_3_A */ |
626 | #define PORT_PLL_M2_FRAC_ENABLE REG_BIT(16) |
627 | /* PORT_PLL_6_A */ |
628 | #define PORT_PLL_GAIN_CTL_MASK REG_GENMASK(18, 16) |
629 | #define PORT_PLL_GAIN_CTL(x) REG_FIELD_PREP(PORT_PLL_GAIN_CTL_MASK, (x)) |
630 | #define PORT_PLL_INT_COEFF_MASK REG_GENMASK(12, 8) |
631 | #define PORT_PLL_INT_COEFF(x) REG_FIELD_PREP(PORT_PLL_INT_COEFF_MASK, (x)) |
632 | #define PORT_PLL_PROP_COEFF_MASK REG_GENMASK(3, 0) |
633 | #define PORT_PLL_PROP_COEFF(x) REG_FIELD_PREP(PORT_PLL_PROP_COEFF_MASK, (x)) |
634 | /* PORT_PLL_8_A */ |
635 | #define PORT_PLL_TARGET_CNT_MASK REG_GENMASK(9, 0) |
636 | #define PORT_PLL_TARGET_CNT(x) REG_FIELD_PREP(PORT_PLL_TARGET_CNT_MASK, (x)) |
637 | /* PORT_PLL_9_A */ |
638 | #define PORT_PLL_LOCK_THRESHOLD_MASK REG_GENMASK(3, 1) |
639 | #define PORT_PLL_LOCK_THRESHOLD(x) REG_FIELD_PREP(PORT_PLL_LOCK_THRESHOLD_MASK, (x)) |
640 | /* PORT_PLL_10_A */ |
641 | #define PORT_PLL_DCO_AMP_OVR_EN_H REG_BIT(27) |
642 | #define PORT_PLL_DCO_AMP_MASK REG_GENMASK(13, 10) |
643 | #define PORT_PLL_DCO_AMP(x) REG_FIELD_PREP(PORT_PLL_DCO_AMP_MASK, (x)) |
644 | #define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \ |
645 | _PORT_PLL_0_B, \ |
646 | _PORT_PLL_0_C) |
647 | #define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \ |
648 | (idx) * 4) |
649 | |
650 | /* BXT PHY common lane registers */ |
651 | #define _PORT_CL1CM_DW0_A 0x162000 |
652 | #define _PORT_CL1CM_DW0_BC 0x6C000 |
653 | #define PHY_POWER_GOOD (1 << 16) |
654 | #define PHY_RESERVED (1 << 7) |
655 | #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC) |
656 | |
657 | #define _PORT_CL1CM_DW9_A 0x162024 |
658 | #define _PORT_CL1CM_DW9_BC 0x6C024 |
659 | #define IREF0RC_OFFSET_SHIFT 8 |
660 | #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT) |
661 | #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC) |
662 | |
663 | #define _PORT_CL1CM_DW10_A 0x162028 |
664 | #define _PORT_CL1CM_DW10_BC 0x6C028 |
665 | #define IREF1RC_OFFSET_SHIFT 8 |
666 | #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT) |
667 | #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC) |
668 | |
669 | #define _PORT_CL1CM_DW28_A 0x162070 |
670 | #define _PORT_CL1CM_DW28_BC 0x6C070 |
671 | #define OCL1_POWER_DOWN_EN (1 << 23) |
672 | #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22) |
673 | #define SUS_CLK_CONFIG 0x3 |
674 | #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC) |
675 | |
676 | #define _PORT_CL1CM_DW30_A 0x162078 |
677 | #define _PORT_CL1CM_DW30_BC 0x6C078 |
678 | #define OCL2_LDOFUSE_PWR_DIS (1 << 6) |
679 | #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC) |
680 | |
681 | /* The spec defines this only for BXT PHY0, but lets assume that this |
682 | * would exist for PHY1 too if it had a second channel. |
683 | */ |
684 | #define _PORT_CL2CM_DW6_A 0x162358 |
685 | #define _PORT_CL2CM_DW6_BC 0x6C358 |
686 | #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC) |
687 | #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28) |
688 | |
689 | /* BXT PHY Ref registers */ |
690 | #define _PORT_REF_DW3_A 0x16218C |
691 | #define _PORT_REF_DW3_BC 0x6C18C |
692 | #define GRC_DONE (1 << 22) |
693 | #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC) |
694 | |
695 | #define _PORT_REF_DW6_A 0x162198 |
696 | #define _PORT_REF_DW6_BC 0x6C198 |
697 | #define GRC_CODE_SHIFT 24 |
698 | #define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT) |
699 | #define GRC_CODE_FAST_SHIFT 16 |
700 | #define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT) |
701 | #define GRC_CODE_SLOW_SHIFT 8 |
702 | #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT) |
703 | #define GRC_CODE_NOM_MASK 0xFF |
704 | #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC) |
705 | |
706 | #define _PORT_REF_DW8_A 0x1621A0 |
707 | #define _PORT_REF_DW8_BC 0x6C1A0 |
708 | #define GRC_DIS (1 << 15) |
709 | #define GRC_RDY_OVRD (1 << 1) |
710 | #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC) |
711 | |
712 | /* BXT PHY PCS registers */ |
713 | #define _PORT_PCS_DW10_LN01_A 0x162428 |
714 | #define _PORT_PCS_DW10_LN01_B 0x6C428 |
715 | #define _PORT_PCS_DW10_LN01_C 0x6C828 |
716 | #define _PORT_PCS_DW10_GRP_A 0x162C28 |
717 | #define _PORT_PCS_DW10_GRP_B 0x6CC28 |
718 | #define _PORT_PCS_DW10_GRP_C 0x6CE28 |
719 | #define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
720 | _PORT_PCS_DW10_LN01_B, \ |
721 | _PORT_PCS_DW10_LN01_C) |
722 | #define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
723 | _PORT_PCS_DW10_GRP_B, \ |
724 | _PORT_PCS_DW10_GRP_C) |
725 | |
726 | #define TX2_SWING_CALC_INIT (1 << 31) |
727 | #define TX1_SWING_CALC_INIT (1 << 30) |
728 | |
729 | #define _PORT_PCS_DW12_LN01_A 0x162430 |
730 | #define _PORT_PCS_DW12_LN01_B 0x6C430 |
731 | #define _PORT_PCS_DW12_LN01_C 0x6C830 |
732 | #define _PORT_PCS_DW12_LN23_A 0x162630 |
733 | #define _PORT_PCS_DW12_LN23_B 0x6C630 |
734 | #define _PORT_PCS_DW12_LN23_C 0x6CA30 |
735 | #define _PORT_PCS_DW12_GRP_A 0x162c30 |
736 | #define _PORT_PCS_DW12_GRP_B 0x6CC30 |
737 | #define _PORT_PCS_DW12_GRP_C 0x6CE30 |
738 | #define LANESTAGGER_STRAP_OVRD (1 << 6) |
739 | #define LANE_STAGGER_MASK 0x1F |
740 | #define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
741 | _PORT_PCS_DW12_LN01_B, \ |
742 | _PORT_PCS_DW12_LN01_C) |
743 | #define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
744 | _PORT_PCS_DW12_LN23_B, \ |
745 | _PORT_PCS_DW12_LN23_C) |
746 | #define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
747 | _PORT_PCS_DW12_GRP_B, \ |
748 | _PORT_PCS_DW12_GRP_C) |
749 | |
750 | /* BXT PHY TX registers */ |
751 | #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ |
752 | ((lane) & 1) * 0x80) |
753 | |
754 | #define _PORT_TX_DW2_LN0_A 0x162508 |
755 | #define _PORT_TX_DW2_LN0_B 0x6C508 |
756 | #define _PORT_TX_DW2_LN0_C 0x6C908 |
757 | #define _PORT_TX_DW2_GRP_A 0x162D08 |
758 | #define _PORT_TX_DW2_GRP_B 0x6CD08 |
759 | #define _PORT_TX_DW2_GRP_C 0x6CF08 |
760 | #define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
761 | _PORT_TX_DW2_LN0_B, \ |
762 | _PORT_TX_DW2_LN0_C) |
763 | #define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
764 | _PORT_TX_DW2_GRP_B, \ |
765 | _PORT_TX_DW2_GRP_C) |
766 | #define MARGIN_000_SHIFT 16 |
767 | #define MARGIN_000 (0xFF << MARGIN_000_SHIFT) |
768 | #define UNIQ_TRANS_SCALE_SHIFT 8 |
769 | #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT) |
770 | |
771 | #define _PORT_TX_DW3_LN0_A 0x16250C |
772 | #define _PORT_TX_DW3_LN0_B 0x6C50C |
773 | #define _PORT_TX_DW3_LN0_C 0x6C90C |
774 | #define _PORT_TX_DW3_GRP_A 0x162D0C |
775 | #define _PORT_TX_DW3_GRP_B 0x6CD0C |
776 | #define _PORT_TX_DW3_GRP_C 0x6CF0C |
777 | #define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
778 | _PORT_TX_DW3_LN0_B, \ |
779 | _PORT_TX_DW3_LN0_C) |
780 | #define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
781 | _PORT_TX_DW3_GRP_B, \ |
782 | _PORT_TX_DW3_GRP_C) |
783 | #define SCALE_DCOMP_METHOD (1 << 26) |
784 | #define UNIQUE_TRANGE_EN_METHOD (1 << 27) |
785 | |
786 | #define _PORT_TX_DW4_LN0_A 0x162510 |
787 | #define _PORT_TX_DW4_LN0_B 0x6C510 |
788 | #define _PORT_TX_DW4_LN0_C 0x6C910 |
789 | #define _PORT_TX_DW4_GRP_A 0x162D10 |
790 | #define _PORT_TX_DW4_GRP_B 0x6CD10 |
791 | #define _PORT_TX_DW4_GRP_C 0x6CF10 |
792 | #define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
793 | _PORT_TX_DW4_LN0_B, \ |
794 | _PORT_TX_DW4_LN0_C) |
795 | #define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
796 | _PORT_TX_DW4_GRP_B, \ |
797 | _PORT_TX_DW4_GRP_C) |
798 | #define DEEMPH_SHIFT 24 |
799 | #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT) |
800 | |
801 | #define _PORT_TX_DW5_LN0_A 0x162514 |
802 | #define _PORT_TX_DW5_LN0_B 0x6C514 |
803 | #define _PORT_TX_DW5_LN0_C 0x6C914 |
804 | #define _PORT_TX_DW5_GRP_A 0x162D14 |
805 | #define _PORT_TX_DW5_GRP_B 0x6CD14 |
806 | #define _PORT_TX_DW5_GRP_C 0x6CF14 |
807 | #define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
808 | _PORT_TX_DW5_LN0_B, \ |
809 | _PORT_TX_DW5_LN0_C) |
810 | #define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
811 | _PORT_TX_DW5_GRP_B, \ |
812 | _PORT_TX_DW5_GRP_C) |
813 | #define DCC_DELAY_RANGE_1 (1 << 9) |
814 | #define DCC_DELAY_RANGE_2 (1 << 8) |
815 | |
816 | #define _PORT_TX_DW14_LN0_A 0x162538 |
817 | #define _PORT_TX_DW14_LN0_B 0x6C538 |
818 | #define _PORT_TX_DW14_LN0_C 0x6C938 |
819 | #define LATENCY_OPTIM_SHIFT 30 |
820 | #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT) |
821 | #define BXT_PORT_TX_DW14_LN(phy, ch, lane) \ |
822 | _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \ |
823 | _PORT_TX_DW14_LN0_C) + \ |
824 | _BXT_LANE_OFFSET(lane)) |
825 | |
826 | /* UAIMI scratch pad register 1 */ |
827 | #define UAIMI_SPR1 _MMIO(0x4F074) |
828 | /* SKL VccIO mask */ |
829 | #define SKL_VCCIO_MASK 0x1 |
830 | /* SKL balance leg register */ |
831 | #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C) |
832 | /* I_boost values */ |
833 | #define BALANCE_LEG_SHIFT(port) (8 + 3 * (port)) |
834 | #define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port))) |
835 | /* Balance leg disable bits */ |
836 | #define BALANCE_LEG_DISABLE_SHIFT 23 |
837 | #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port))) |
838 | |
839 | /* |
840 | * Fence registers |
841 | * [0-7] @ 0x2000 gen2,gen3 |
842 | * [8-15] @ 0x3000 945,g33,pnv |
843 | * |
844 | * [0-15] @ 0x3000 gen4,gen5 |
845 | * |
846 | * [0-15] @ 0x100000 gen6,vlv,chv |
847 | * [0-31] @ 0x100000 gen7+ |
848 | */ |
849 | #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) |
850 | #define I830_FENCE_START_MASK 0x07f80000 |
851 | #define I830_FENCE_TILING_Y_SHIFT 12 |
852 | #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) |
853 | #define I830_FENCE_PITCH_SHIFT 4 |
854 | #define I830_FENCE_REG_VALID (1 << 0) |
855 | #define I915_FENCE_MAX_PITCH_VAL 4 |
856 | #define I830_FENCE_MAX_PITCH_VAL 6 |
857 | #define I830_FENCE_MAX_SIZE_VAL (1 << 8) |
858 | |
859 | #define I915_FENCE_START_MASK 0x0ff00000 |
860 | #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) |
861 | |
862 | #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8) |
863 | #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4) |
864 | #define I965_FENCE_PITCH_SHIFT 2 |
865 | #define I965_FENCE_TILING_Y_SHIFT 1 |
866 | #define I965_FENCE_REG_VALID (1 << 0) |
867 | #define I965_FENCE_MAX_PITCH_VAL 0x0400 |
868 | |
869 | #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8) |
870 | #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4) |
871 | #define GEN6_FENCE_PITCH_SHIFT 32 |
872 | #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 |
873 | |
874 | |
875 | /* control register for cpu gtt access */ |
876 | #define TILECTL _MMIO(0x101000) |
877 | #define TILECTL_SWZCTL (1 << 0) |
878 | #define TILECTL_TLBPF (1 << 1) |
879 | #define TILECTL_TLB_PREFETCH_DIS (1 << 2) |
880 | #define TILECTL_BACKSNOOP_DIS (1 << 3) |
881 | |
882 | /* |
883 | * Instruction and interrupt control regs |
884 | */ |
885 | #define PGTBL_CTL _MMIO(0x02020) |
886 | #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ |
887 | #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ |
888 | #define PGTBL_ER _MMIO(0x02024) |
889 | #define PRB0_BASE (0x2030 - 0x30) |
890 | #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */ |
891 | #define PRB2_BASE (0x2050 - 0x30) /* gen3 */ |
892 | #define SRB0_BASE (0x2100 - 0x30) /* gen2 */ |
893 | #define SRB1_BASE (0x2110 - 0x30) /* gen2 */ |
894 | #define SRB2_BASE (0x2120 - 0x30) /* 830 */ |
895 | #define SRB3_BASE (0x2130 - 0x30) /* 830 */ |
896 | #define RENDER_RING_BASE 0x02000 |
897 | #define BSD_RING_BASE 0x04000 |
898 | #define GEN6_BSD_RING_BASE 0x12000 |
899 | #define GEN8_BSD2_RING_BASE 0x1c000 |
900 | #define GEN11_BSD_RING_BASE 0x1c0000 |
901 | #define GEN11_BSD2_RING_BASE 0x1c4000 |
902 | #define GEN11_BSD3_RING_BASE 0x1d0000 |
903 | #define GEN11_BSD4_RING_BASE 0x1d4000 |
904 | #define XEHP_BSD5_RING_BASE 0x1e0000 |
905 | #define XEHP_BSD6_RING_BASE 0x1e4000 |
906 | #define XEHP_BSD7_RING_BASE 0x1f0000 |
907 | #define XEHP_BSD8_RING_BASE 0x1f4000 |
908 | #define VEBOX_RING_BASE 0x1a000 |
909 | #define GEN11_VEBOX_RING_BASE 0x1c8000 |
910 | #define GEN11_VEBOX2_RING_BASE 0x1d8000 |
911 | #define XEHP_VEBOX3_RING_BASE 0x1e8000 |
912 | #define XEHP_VEBOX4_RING_BASE 0x1f8000 |
913 | #define MTL_GSC_RING_BASE 0x11a000 |
914 | #define GEN12_COMPUTE0_RING_BASE 0x1a000 |
915 | #define GEN12_COMPUTE1_RING_BASE 0x1c000 |
916 | #define GEN12_COMPUTE2_RING_BASE 0x1e000 |
917 | #define GEN12_COMPUTE3_RING_BASE 0x26000 |
918 | #define BLT_RING_BASE 0x22000 |
919 | #define XEHPC_BCS1_RING_BASE 0x3e0000 |
920 | #define XEHPC_BCS2_RING_BASE 0x3e2000 |
921 | #define XEHPC_BCS3_RING_BASE 0x3e4000 |
922 | #define XEHPC_BCS4_RING_BASE 0x3e6000 |
923 | #define XEHPC_BCS5_RING_BASE 0x3e8000 |
924 | #define XEHPC_BCS6_RING_BASE 0x3ea000 |
925 | #define XEHPC_BCS7_RING_BASE 0x3ec000 |
926 | #define XEHPC_BCS8_RING_BASE 0x3ee000 |
927 | #define DG1_GSC_HECI1_BASE 0x00258000 |
928 | #define DG1_GSC_HECI2_BASE 0x00259000 |
929 | #define DG2_GSC_HECI1_BASE 0x00373000 |
930 | #define DG2_GSC_HECI2_BASE 0x00374000 |
931 | #define MTL_GSC_HECI1_BASE 0x00116000 |
932 | #define MTL_GSC_HECI2_BASE 0x00117000 |
933 | |
934 | #define HECI_H_CSR(base) _MMIO((base) + 0x4) |
935 | #define HECI_H_CSR_IE REG_BIT(0) |
936 | #define HECI_H_CSR_IS REG_BIT(1) |
937 | #define HECI_H_CSR_IG REG_BIT(2) |
938 | #define HECI_H_CSR_RDY REG_BIT(3) |
939 | #define HECI_H_CSR_RST REG_BIT(4) |
940 | |
941 | #define HECI_H_GS1(base) _MMIO((base) + 0xc4c) |
942 | #define HECI_H_GS1_ER_PREP REG_BIT(0) |
943 | |
944 | /* |
945 | * The FWSTS register values are FW defined and can be different between |
946 | * HECI1 and HECI2 |
947 | */ |
948 | #define HECI_FWSTS1 0xc40 |
949 | #define HECI1_FWSTS1_CURRENT_STATE REG_GENMASK(3, 0) |
950 | #define HECI1_FWSTS1_CURRENT_STATE_RESET 0 |
951 | #define HECI1_FWSTS1_PROXY_STATE_NORMAL 5 |
952 | #define HECI1_FWSTS1_INIT_COMPLETE REG_BIT(9) |
953 | #define HECI_FWSTS2 0xc48 |
954 | #define HECI_FWSTS3 0xc60 |
955 | #define HECI_FWSTS4 0xc64 |
956 | #define HECI_FWSTS5 0xc68 |
957 | #define HECI1_FWSTS5_HUC_AUTH_DONE (1 << 19) |
958 | #define HECI_FWSTS6 0xc6c |
959 | |
960 | /* the FWSTS regs are 1-based, so we use -base for index 0 to get an invalid reg */ |
961 | #define HECI_FWSTS(base, x) _MMIO((base) + _PICK(x, -(base), \ |
962 | HECI_FWSTS1, \ |
963 | HECI_FWSTS2, \ |
964 | HECI_FWSTS3, \ |
965 | HECI_FWSTS4, \ |
966 | HECI_FWSTS5, \ |
967 | HECI_FWSTS6)) |
968 | |
969 | #define HSW_GTT_CACHE_EN _MMIO(0x4024) |
970 | #define GTT_CACHE_EN_ALL 0xF0007FFF |
971 | #define GEN7_WR_WATERMARK _MMIO(0x4028) |
972 | #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) |
973 | #define ARB_MODE _MMIO(0x4030) |
974 | #define ARB_MODE_SWIZZLE_SNB (1 << 4) |
975 | #define ARB_MODE_SWIZZLE_IVB (1 << 5) |
976 | #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034) |
977 | #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038) |
978 | /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ |
979 | #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4) |
980 | #define GEN7_LRA_LIMITS_REG_NUM 13 |
981 | #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) |
982 | #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) |
983 | |
984 | #define GEN7_ERR_INT _MMIO(0x44040) |
985 | #define ERR_INT_POISON (1 << 31) |
986 | #define ERR_INT_MMIO_UNCLAIMED (1 << 13) |
987 | #define ERR_INT_PIPE_CRC_DONE_C (1 << 8) |
988 | #define ERR_INT_FIFO_UNDERRUN_C (1 << 6) |
989 | #define ERR_INT_PIPE_CRC_DONE_B (1 << 5) |
990 | #define ERR_INT_FIFO_UNDERRUN_B (1 << 3) |
991 | #define ERR_INT_PIPE_CRC_DONE_A (1 << 2) |
992 | #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3)) |
993 | #define ERR_INT_FIFO_UNDERRUN_A (1 << 0) |
994 | #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) |
995 | |
996 | #define FPGA_DBG _MMIO(0x42300) |
997 | #define FPGA_DBG_RM_NOCLAIM REG_BIT(31) |
998 | |
999 | #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) |
1000 | #define CLAIM_ER_CLR REG_BIT(31) |
1001 | #define CLAIM_ER_OVERFLOW REG_BIT(16) |
1002 | #define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0) |
1003 | |
1004 | #define DERRMR _MMIO(0x44050) |
1005 | /* Note that HBLANK events are reserved on bdw+ */ |
1006 | #define DERRMR_PIPEA_SCANLINE (1 << 0) |
1007 | #define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1) |
1008 | #define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2) |
1009 | #define DERRMR_PIPEA_VBLANK (1 << 3) |
1010 | #define DERRMR_PIPEA_HBLANK (1 << 5) |
1011 | #define DERRMR_PIPEB_SCANLINE (1 << 8) |
1012 | #define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9) |
1013 | #define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10) |
1014 | #define DERRMR_PIPEB_VBLANK (1 << 11) |
1015 | #define DERRMR_PIPEB_HBLANK (1 << 13) |
1016 | /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ |
1017 | #define DERRMR_PIPEC_SCANLINE (1 << 14) |
1018 | #define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15) |
1019 | #define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20) |
1020 | #define DERRMR_PIPEC_VBLANK (1 << 21) |
1021 | #define DERRMR_PIPEC_HBLANK (1 << 22) |
1022 | |
1023 | #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) |
1024 | #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) |
1025 | #define SCPD0 _MMIO(0x209c) /* 915+ only */ |
1026 | #define SCPD_FBC_IGNORE_3D (1 << 6) |
1027 | #define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5) |
1028 | #define GEN2_IER _MMIO(0x20a0) |
1029 | #define GEN2_IIR _MMIO(0x20a4) |
1030 | #define GEN2_IMR _MMIO(0x20a8) |
1031 | #define GEN2_ISR _MMIO(0x20ac) |
1032 | #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060) |
1033 | #define GINT_DIS (1 << 22) |
1034 | #define GCFG_DIS (1 << 8) |
1035 | #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) |
1036 | #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) |
1037 | #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) |
1038 | #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) |
1039 | #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) |
1040 | #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) |
1041 | #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) |
1042 | #define VLV_PCBR_ADDR_SHIFT 12 |
1043 | |
1044 | #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */ |
1045 | #define EIR _MMIO(0x20b0) |
1046 | #define EMR _MMIO(0x20b4) |
1047 | #define ESR _MMIO(0x20b8) |
1048 | #define GM45_ERROR_PAGE_TABLE (1 << 5) |
1049 | #define GM45_ERROR_MEM_PRIV (1 << 4) |
1050 | #define I915_ERROR_PAGE_TABLE (1 << 4) |
1051 | #define GM45_ERROR_CP_PRIV (1 << 3) |
1052 | #define I915_ERROR_MEMORY_REFRESH (1 << 1) |
1053 | #define I915_ERROR_INSTRUCTION (1 << 0) |
1054 | #define INSTPM _MMIO(0x20c0) |
1055 | #define INSTPM_SELF_EN (1 << 12) /* 915GM only */ |
1056 | #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts |
1057 | will not assert AGPBUSY# and will only |
1058 | be delivered when out of C3. */ |
1059 | #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */ |
1060 | #define INSTPM_TLB_INVALIDATE (1 << 9) |
1061 | #define INSTPM_SYNC_FLUSH (1 << 5) |
1062 | #define MEM_MODE _MMIO(0x20cc) |
1063 | #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */ |
1064 | #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */ |
1065 | #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */ |
1066 | #define FW_BLC _MMIO(0x20d8) |
1067 | #define FW_BLC2 _MMIO(0x20dc) |
1068 | #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ |
1069 | #define FW_BLC_SELF_EN_MASK (1 << 31) |
1070 | #define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */ |
1071 | #define FW_BLC_SELF_EN (1 << 15) /* 945 only */ |
1072 | #define MM_BURST_LENGTH 0x00700000 |
1073 | #define MM_FIFO_WATERMARK 0x0001F000 |
1074 | #define LM_BURST_LENGTH 0x00000700 |
1075 | #define LM_FIFO_WATERMARK 0x0000001F |
1076 | #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ |
1077 | |
1078 | #define _MBUS_ABOX0_CTL 0x45038 |
1079 | #define _MBUS_ABOX1_CTL 0x45048 |
1080 | #define _MBUS_ABOX2_CTL 0x4504C |
1081 | #define MBUS_ABOX_CTL(x) \ |
1082 | _MMIO(_PICK_EVEN_2RANGES(x, 2, \ |
1083 | _MBUS_ABOX0_CTL, _MBUS_ABOX1_CTL, \ |
1084 | _MBUS_ABOX2_CTL, _MBUS_ABOX2_CTL)) |
1085 | |
1086 | #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) |
1087 | #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) |
1088 | #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) |
1089 | #define MBUS_ABOX_B_CREDIT(x) ((x) << 16) |
1090 | #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8) |
1091 | #define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8) |
1092 | #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0) |
1093 | #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0) |
1094 | |
1095 | /* Make render/texture TLB fetches lower priorty than associated data |
1096 | * fetches. This is not turned on by default |
1097 | */ |
1098 | #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) |
1099 | |
1100 | /* Isoch request wait on GTT enable (Display A/B/C streams). |
1101 | * Make isoch requests stall on the TLB update. May cause |
1102 | * display underruns (test mode only) |
1103 | */ |
1104 | #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) |
1105 | |
1106 | /* Block grant count for isoch requests when block count is |
1107 | * set to a finite value. |
1108 | */ |
1109 | #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) |
1110 | #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ |
1111 | #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ |
1112 | #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ |
1113 | #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ |
1114 | |
1115 | /* Enable render writes to complete in C2/C3/C4 power states. |
1116 | * If this isn't enabled, render writes are prevented in low |
1117 | * power states. That seems bad to me. |
1118 | */ |
1119 | #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) |
1120 | |
1121 | /* This acknowledges an async flip immediately instead |
1122 | * of waiting for 2TLB fetches. |
1123 | */ |
1124 | #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) |
1125 | |
1126 | /* Enables non-sequential data reads through arbiter |
1127 | */ |
1128 | #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) |
1129 | |
1130 | /* Disable FSB snooping of cacheable write cycles from binner/render |
1131 | * command stream |
1132 | */ |
1133 | #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) |
1134 | |
1135 | /* Arbiter time slice for non-isoch streams */ |
1136 | #define MI_ARB_TIME_SLICE_MASK (7 << 5) |
1137 | #define MI_ARB_TIME_SLICE_1 (0 << 5) |
1138 | #define MI_ARB_TIME_SLICE_2 (1 << 5) |
1139 | #define MI_ARB_TIME_SLICE_4 (2 << 5) |
1140 | #define MI_ARB_TIME_SLICE_6 (3 << 5) |
1141 | #define MI_ARB_TIME_SLICE_8 (4 << 5) |
1142 | #define MI_ARB_TIME_SLICE_10 (5 << 5) |
1143 | #define MI_ARB_TIME_SLICE_14 (6 << 5) |
1144 | #define MI_ARB_TIME_SLICE_16 (7 << 5) |
1145 | |
1146 | /* Low priority grace period page size */ |
1147 | #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ |
1148 | #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) |
1149 | |
1150 | /* Disable display A/B trickle feed */ |
1151 | #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) |
1152 | |
1153 | /* Set display plane priority */ |
1154 | #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ |
1155 | #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ |
1156 | |
1157 | #define MI_STATE _MMIO(0x20e4) /* gen2 only */ |
1158 | #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ |
1159 | #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ |
1160 | |
1161 | /* On modern GEN architectures interrupt control consists of two sets |
1162 | * of registers. The first set pertains to the ring generating the |
1163 | * interrupt. The second control is for the functional block generating the |
1164 | * interrupt. These are PM, GT, DE, etc. |
1165 | * |
1166 | * Luckily *knocks on wood* all the ring interrupt bits match up with the |
1167 | * GT interrupt bits, so we don't need to duplicate the defines. |
1168 | * |
1169 | * These defines should cover us well from SNB->HSW with minor exceptions |
1170 | * it can also work on ILK. |
1171 | */ |
1172 | #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) |
1173 | #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) |
1174 | #define GT_BLT_USER_INTERRUPT (1 << 22) |
1175 | #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) |
1176 | #define GT_BSD_USER_INTERRUPT (1 << 12) |
1177 | #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ |
1178 | #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */ |
1179 | #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) |
1180 | #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ |
1181 | #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) |
1182 | #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) |
1183 | #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) |
1184 | #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) |
1185 | #define GT_RENDER_USER_INTERRUPT (1 << 0) |
1186 | |
1187 | #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ |
1188 | #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ |
1189 | |
1190 | #define GT_PARITY_ERROR(dev_priv) \ |
1191 | (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ |
1192 | (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) |
1193 | |
1194 | /* These are all the "old" interrupts */ |
1195 | #define ILK_BSD_USER_INTERRUPT (1 << 5) |
1196 | |
1197 | #define I915_PM_INTERRUPT (1 << 31) |
1198 | #define I915_ISP_INTERRUPT (1 << 22) |
1199 | #define I915_LPE_PIPE_B_INTERRUPT (1 << 21) |
1200 | #define I915_LPE_PIPE_A_INTERRUPT (1 << 20) |
1201 | #define I915_MIPIC_INTERRUPT (1 << 19) |
1202 | #define I915_MIPIA_INTERRUPT (1 << 18) |
1203 | #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18) |
1204 | #define I915_DISPLAY_PORT_INTERRUPT (1 << 17) |
1205 | #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16) |
1206 | #define I915_MASTER_ERROR_INTERRUPT (1 << 15) |
1207 | #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14) |
1208 | #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */ |
1209 | #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13) |
1210 | #define I915_HWB_OOM_INTERRUPT (1 << 13) |
1211 | #define I915_LPE_PIPE_C_INTERRUPT (1 << 12) |
1212 | #define I915_SYNC_STATUS_INTERRUPT (1 << 12) |
1213 | #define I915_MISC_INTERRUPT (1 << 11) |
1214 | #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11) |
1215 | #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10) |
1216 | #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10) |
1217 | #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9) |
1218 | #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9) |
1219 | #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8) |
1220 | #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8) |
1221 | #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7) |
1222 | #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6) |
1223 | #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5) |
1224 | #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4) |
1225 | #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3) |
1226 | #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2) |
1227 | #define I915_DEBUG_INTERRUPT (1 << 2) |
1228 | #define I915_WINVALID_INTERRUPT (1 << 1) |
1229 | #define I915_USER_INTERRUPT (1 << 1) |
1230 | #define I915_ASLE_INTERRUPT (1 << 0) |
1231 | #define I915_BSD_USER_INTERRUPT (1 << 25) |
1232 | |
1233 | #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000) |
1234 | #define I915_HDMI_LPE_AUDIO_SIZE 0x1000 |
1235 | |
1236 | /* DisplayPort Audio w/ LPE */ |
1237 | #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38) |
1238 | #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0) |
1239 | |
1240 | #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20) |
1241 | #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30) |
1242 | #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34) |
1243 | #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \ |
1244 | _VLV_AUD_PORT_EN_B_DBG, \ |
1245 | _VLV_AUD_PORT_EN_C_DBG, \ |
1246 | _VLV_AUD_PORT_EN_D_DBG) |
1247 | #define VLV_AMP_MUTE (1 << 1) |
1248 | |
1249 | #define GEN6_BSD_RNCID _MMIO(0x12198) |
1250 | |
1251 | #define GEN7_FF_THREAD_MODE _MMIO(0x20a0) |
1252 | #define GEN7_FF_SCHED_MASK 0x0077070 |
1253 | #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) |
1254 | #define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19) |
1255 | #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16) |
1256 | #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16) |
1257 | #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16) |
1258 | #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */ |
1259 | #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) |
1260 | #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12) |
1261 | #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12) |
1262 | #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */ |
1263 | #define GEN7_FF_VS_SCHED_HW (0x0 << 12) |
1264 | #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4) |
1265 | #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4) |
1266 | #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */ |
1267 | #define GEN7_FF_DS_SCHED_HW (0x0 << 4) |
1268 | |
1269 | /* |
1270 | * Framebuffer compression (915+ only) |
1271 | */ |
1272 | |
1273 | #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ |
1274 | #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ |
1275 | #define FBC_CONTROL _MMIO(0x3208) |
1276 | #define FBC_CTL_EN REG_BIT(31) |
1277 | #define FBC_CTL_PERIODIC REG_BIT(30) |
1278 | #define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16) |
1279 | #define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x)) |
1280 | #define FBC_CTL_STOP_ON_MOD REG_BIT(15) |
1281 | #define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */ |
1282 | #define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */ |
1283 | #define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5) |
1284 | #define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x)) |
1285 | #define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0) |
1286 | #define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x)) |
1287 | #define FBC_COMMAND _MMIO(0x320c) |
1288 | #define FBC_CMD_COMPRESS REG_BIT(0) |
1289 | #define FBC_STATUS _MMIO(0x3210) |
1290 | #define FBC_STAT_COMPRESSING REG_BIT(31) |
1291 | #define FBC_STAT_COMPRESSED REG_BIT(30) |
1292 | #define FBC_STAT_MODIFIED REG_BIT(29) |
1293 | #define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0) |
1294 | #define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */ |
1295 | #define FBC_CTL_FENCE_DBL REG_BIT(4) |
1296 | #define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2) |
1297 | #define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0) |
1298 | #define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1) |
1299 | #define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2) |
1300 | #define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3) |
1301 | #define FBC_CTL_CPU_FENCE_EN REG_BIT(1) |
1302 | #define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0) |
1303 | #define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane)) |
1304 | #define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */ |
1305 | #define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */ |
1306 | #define FBC_MOD_NUM_MASK REG_GENMASK(31, 1) |
1307 | #define FBC_MOD_NUM_VALID REG_BIT(0) |
1308 | #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */ |
1309 | #define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */ |
1310 | #define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0) |
1311 | #define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1) |
1312 | #define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2) |
1313 | #define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3) |
1314 | |
1315 | #define FBC_LL_SIZE (1536) |
1316 | |
1317 | /* Framebuffer compression for GM45+ */ |
1318 | #define DPFC_CB_BASE _MMIO(0x3200) |
1319 | #define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240) |
1320 | #define DPFC_CONTROL _MMIO(0x3208) |
1321 | #define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248) |
1322 | #define DPFC_CTL_EN REG_BIT(31) |
1323 | #define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */ |
1324 | #define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane)) |
1325 | #define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */ |
1326 | #define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */ |
1327 | #define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane)) |
1328 | #define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */ |
1329 | #define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */ |
1330 | #define DPFC_CTL_PLANE_BINDING_MASK REG_GENMASK(12, 11) /* lnl+ */ |
1331 | #define DPFC_CTL_PLANE_BINDING(plane_id) REG_FIELD_PREP(DPFC_CTL_PLANE_BINDING_MASK, (plane_id)) |
1332 | #define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */ |
1333 | #define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */ |
1334 | #define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */ |
1335 | #define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6) |
1336 | #define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0) |
1337 | #define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1) |
1338 | #define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2) |
1339 | #define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0) |
1340 | #define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence)) |
1341 | #define DPFC_RECOMP_CTL _MMIO(0x320c) |
1342 | #define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c) |
1343 | #define DPFC_RECOMP_STALL_EN REG_BIT(27) |
1344 | #define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16) |
1345 | #define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0) |
1346 | #define DPFC_STATUS _MMIO(0x3210) |
1347 | #define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250) |
1348 | #define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16) |
1349 | #define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0) |
1350 | #define DPFC_STATUS2 _MMIO(0x3214) |
1351 | #define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254) |
1352 | #define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0) |
1353 | #define DPFC_FENCE_YOFF _MMIO(0x3218) |
1354 | #define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258) |
1355 | #define DPFC_CHICKEN _MMIO(0x3224) |
1356 | #define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264) |
1357 | #define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */ |
1358 | #define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */ |
1359 | #define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */ |
1360 | #define DPFC_CHICKEN_FORCE_SLB_INVALIDATION REG_BIT(13) /* icl+ */ |
1361 | #define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */ |
1362 | |
1363 | #define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268) |
1364 | #define FBC_STRIDE_OVERRIDE REG_BIT(15) |
1365 | #define FBC_STRIDE_MASK REG_GENMASK(14, 0) |
1366 | #define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x)) |
1367 | |
1368 | #define ILK_FBC_RT_BASE _MMIO(0x2128) |
1369 | #define ILK_FBC_RT_VALID REG_BIT(0) |
1370 | #define SNB_FBC_FRONT_BUFFER REG_BIT(1) |
1371 | |
1372 | #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) |
1373 | #define ILK_FBCQ_DIS REG_BIT(22) |
1374 | #define ILK_PABSTRETCH_DIS REG_BIT(21) |
1375 | #define ILK_SABSTRETCH_DIS REG_BIT(20) |
1376 | #define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20) |
1377 | #define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0) |
1378 | #define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1) |
1379 | #define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2) |
1380 | #define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3) |
1381 | #define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18) |
1382 | #define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0) |
1383 | #define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1) |
1384 | #define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2) |
1385 | #define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3) |
1386 | |
1387 | |
1388 | /* |
1389 | * Framebuffer compression for Sandybridge |
1390 | * |
1391 | * The following two registers are of type GTTMMADR |
1392 | */ |
1393 | #define SNB_DPFC_CTL_SA _MMIO(0x100100) |
1394 | #define SNB_DPFC_FENCE_EN REG_BIT(29) |
1395 | #define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0) |
1396 | #define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence)) |
1397 | #define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104) |
1398 | |
1399 | /* Framebuffer compression for Ivybridge */ |
1400 | #define IVB_FBC_RT_BASE _MMIO(0x7020) |
1401 | #define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024) |
1402 | |
1403 | #define IPS_CTL _MMIO(0x43408) |
1404 | #define IPS_ENABLE REG_BIT(31) |
1405 | #define IPS_FALSE_COLOR REG_BIT(4) |
1406 | |
1407 | #define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384) |
1408 | #define FBC_REND_NUKE REG_BIT(2) |
1409 | #define FBC_REND_CACHE_CLEAN REG_BIT(1) |
1410 | |
1411 | /* |
1412 | * Clock control & power management |
1413 | */ |
1414 | #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014) |
1415 | #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018) |
1416 | #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030) |
1417 | #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) |
1418 | |
1419 | #define VGA0 _MMIO(0x6000) |
1420 | #define VGA1 _MMIO(0x6004) |
1421 | #define VGA_PD _MMIO(0x6010) |
1422 | #define VGA0_PD_P2_DIV_4 (1 << 7) |
1423 | #define VGA0_PD_P1_DIV_2 (1 << 5) |
1424 | #define VGA0_PD_P1_SHIFT 0 |
1425 | #define VGA0_PD_P1_MASK (0x1f << 0) |
1426 | #define VGA1_PD_P2_DIV_4 (1 << 15) |
1427 | #define VGA1_PD_P1_DIV_2 (1 << 13) |
1428 | #define VGA1_PD_P1_SHIFT 8 |
1429 | #define VGA1_PD_P1_MASK (0x1f << 8) |
1430 | #define DPLL_VCO_ENABLE (1 << 31) |
1431 | #define DPLL_SDVO_HIGH_SPEED (1 << 30) |
1432 | #define DPLL_DVO_2X_MODE (1 << 30) |
1433 | #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) |
1434 | #define DPLL_SYNCLOCK_ENABLE (1 << 29) |
1435 | #define DPLL_REF_CLK_ENABLE_VLV (1 << 29) |
1436 | #define DPLL_VGA_MODE_DIS (1 << 28) |
1437 | #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ |
1438 | #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ |
1439 | #define DPLL_MODE_MASK (3 << 26) |
1440 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ |
1441 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ |
1442 | #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ |
1443 | #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ |
1444 | #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ |
1445 | #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ |
1446 | #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ |
1447 | #define DPLL_LOCK_VLV (1 << 15) |
1448 | #define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14) |
1449 | #define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13) |
1450 | #define DPLL_SSC_REF_CLK_CHV (1 << 13) |
1451 | #define DPLL_PORTC_READY_MASK (0xf << 4) |
1452 | #define DPLL_PORTB_READY_MASK (0xf) |
1453 | |
1454 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 |
1455 | |
1456 | /* Additional CHV pll/phy registers */ |
1457 | #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240) |
1458 | #define DPLL_PORTD_READY_MASK (0xf) |
1459 | #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100) |
1460 | #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27)) |
1461 | #define PHY_LDO_DELAY_0NS 0x0 |
1462 | #define PHY_LDO_DELAY_200NS 0x1 |
1463 | #define PHY_LDO_DELAY_600NS 0x2 |
1464 | #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23)) |
1465 | #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11)) |
1466 | #define PHY_CH_SU_PSR 0x1 |
1467 | #define PHY_CH_DEEP_PSR 0x7 |
1468 | #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2)) |
1469 | #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) |
1470 | #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104) |
1471 | #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30)) |
1472 | #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch)))) |
1473 | #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline)))) |
1474 | |
1475 | /* |
1476 | * The i830 generation, in LVDS mode, defines P1 as the bit number set within |
1477 | * this field (only one bit may be set). |
1478 | */ |
1479 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 |
1480 | #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 |
1481 | #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 |
1482 | /* i830, required in DVO non-gang */ |
1483 | #define PLL_P2_DIVIDE_BY_4 (1 << 23) |
1484 | #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ |
1485 | #define PLL_REF_INPUT_DREFCLK (0 << 13) |
1486 | #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ |
1487 | #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ |
1488 | #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) |
1489 | #define PLL_REF_INPUT_MASK (3 << 13) |
1490 | #define PLL_LOAD_PULSE_PHASE_SHIFT 9 |
1491 | /* Ironlake */ |
1492 | # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 |
1493 | # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) |
1494 | # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9) |
1495 | # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 |
1496 | # define DPLL_FPA1_P1_POST_DIV_MASK 0xff |
1497 | |
1498 | /* |
1499 | * Parallel to Serial Load Pulse phase selection. |
1500 | * Selects the phase for the 10X DPLL clock for the PCIe |
1501 | * digital display port. The range is 4 to 13; 10 or more |
1502 | * is just a flip delay. The default is 6 |
1503 | */ |
1504 | #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) |
1505 | #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) |
1506 | /* |
1507 | * SDVO multiplier for 945G/GM. Not used on 965. |
1508 | */ |
1509 | #define SDVO_MULTIPLIER_MASK 0x000000ff |
1510 | #define SDVO_MULTIPLIER_SHIFT_HIRES 4 |
1511 | #define SDVO_MULTIPLIER_SHIFT_VGA 0 |
1512 | |
1513 | #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c) |
1514 | #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020) |
1515 | #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c) |
1516 | #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) |
1517 | |
1518 | /* |
1519 | * UDI pixel divider, controlling how many pixels are stuffed into a packet. |
1520 | * |
1521 | * Value is pixels minus 1. Must be set to 1 pixel for SDVO. |
1522 | */ |
1523 | #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 |
1524 | #define DPLL_MD_UDI_DIVIDER_SHIFT 24 |
1525 | /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ |
1526 | #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 |
1527 | #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 |
1528 | /* |
1529 | * SDVO/UDI pixel multiplier. |
1530 | * |
1531 | * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus |
1532 | * clock rate is 10 times the DPLL clock. At low resolution/refresh rate |
1533 | * modes, the bus rate would be below the limits, so SDVO allows for stuffing |
1534 | * dummy bytes in the datastream at an increased clock rate, with both sides of |
1535 | * the link knowing how many bytes are fill. |
1536 | * |
1537 | * So, for a mode with a dotclock of 65Mhz, we would want to double the clock |
1538 | * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be |
1539 | * set to 130Mhz, and the SDVO multiplier set to 2x in this register and |
1540 | * through an SDVO command. |
1541 | * |
1542 | * This register field has values of multiplication factor minus 1, with |
1543 | * a maximum multiplier of 5 for SDVO. |
1544 | */ |
1545 | #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 |
1546 | #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 |
1547 | /* |
1548 | * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. |
1549 | * This best be set to the default value (3) or the CRT won't work. No, |
1550 | * I don't entirely understand what this does... |
1551 | */ |
1552 | #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f |
1553 | #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 |
1554 | |
1555 | #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024) |
1556 | |
1557 | #define _FPA0 0x6040 |
1558 | #define _FPA1 0x6044 |
1559 | #define _FPB0 0x6048 |
1560 | #define _FPB1 0x604c |
1561 | #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0) |
1562 | #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1) |
1563 | #define FP_N_DIV_MASK 0x003f0000 |
1564 | #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 |
1565 | #define FP_N_DIV_SHIFT 16 |
1566 | #define FP_M1_DIV_MASK 0x00003f00 |
1567 | #define FP_M1_DIV_SHIFT 8 |
1568 | #define FP_M2_DIV_MASK 0x0000003f |
1569 | #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff |
1570 | #define FP_M2_DIV_SHIFT 0 |
1571 | #define DPLL_TEST _MMIO(0x606c) |
1572 | #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) |
1573 | #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) |
1574 | #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) |
1575 | #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) |
1576 | #define DPLLB_TEST_N_BYPASS (1 << 19) |
1577 | #define DPLLB_TEST_M_BYPASS (1 << 18) |
1578 | #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) |
1579 | #define DPLLA_TEST_N_BYPASS (1 << 3) |
1580 | #define DPLLA_TEST_M_BYPASS (1 << 2) |
1581 | #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) |
1582 | #define D_STATE _MMIO(0x6104) |
1583 | #define DSTATE_GFX_RESET_I830 (1 << 6) |
1584 | #define DSTATE_PLL_D3_OFF (1 << 3) |
1585 | #define DSTATE_GFX_CLOCK_GATING (1 << 1) |
1586 | #define DSTATE_DOT_CLOCK_GATING (1 << 0) |
1587 | #define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200) |
1588 | # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ |
1589 | # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ |
1590 | # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ |
1591 | # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ |
1592 | # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ |
1593 | # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ |
1594 | # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ |
1595 | # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */ |
1596 | # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ |
1597 | # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ |
1598 | # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ |
1599 | # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ |
1600 | # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ |
1601 | # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ |
1602 | # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ |
1603 | # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ |
1604 | # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ |
1605 | # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ |
1606 | # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ |
1607 | # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ |
1608 | # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) |
1609 | # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) |
1610 | # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) |
1611 | # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) |
1612 | # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ |
1613 | # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ |
1614 | # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ |
1615 | # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) |
1616 | # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) |
1617 | /* |
1618 | * This bit must be set on the 830 to prevent hangs when turning off the |
1619 | * overlay scaler. |
1620 | */ |
1621 | # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) |
1622 | # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) |
1623 | # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) |
1624 | # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ |
1625 | # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ |
1626 | |
1627 | #define RENCLK_GATE_D1 _MMIO(0x6204) |
1628 | # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ |
1629 | # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ |
1630 | # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) |
1631 | # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) |
1632 | # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) |
1633 | # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) |
1634 | # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) |
1635 | # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) |
1636 | # define MAG_CLOCK_GATE_DISABLE (1 << 5) |
1637 | /* This bit must be unset on 855,865 */ |
1638 | # define MECI_CLOCK_GATE_DISABLE (1 << 4) |
1639 | # define DCMP_CLOCK_GATE_DISABLE (1 << 3) |
1640 | # define MEC_CLOCK_GATE_DISABLE (1 << 2) |
1641 | # define MECO_CLOCK_GATE_DISABLE (1 << 1) |
1642 | /* This bit must be set on 855,865. */ |
1643 | # define SV_CLOCK_GATE_DISABLE (1 << 0) |
1644 | # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) |
1645 | # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) |
1646 | # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) |
1647 | # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) |
1648 | # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) |
1649 | # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) |
1650 | # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) |
1651 | # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) |
1652 | # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) |
1653 | # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) |
1654 | # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) |
1655 | # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) |
1656 | # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) |
1657 | # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) |
1658 | # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) |
1659 | # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) |
1660 | # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) |
1661 | |
1662 | # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) |
1663 | /* This bit must always be set on 965G/965GM */ |
1664 | # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) |
1665 | # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) |
1666 | # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) |
1667 | # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) |
1668 | # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) |
1669 | # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) |
1670 | /* This bit must always be set on 965G */ |
1671 | # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) |
1672 | # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) |
1673 | # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) |
1674 | # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) |
1675 | # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) |
1676 | # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) |
1677 | # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) |
1678 | # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) |
1679 | # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) |
1680 | # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) |
1681 | # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) |
1682 | # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) |
1683 | # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) |
1684 | # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) |
1685 | # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) |
1686 | # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) |
1687 | # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) |
1688 | # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) |
1689 | # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) |
1690 | |
1691 | #define RENCLK_GATE_D2 _MMIO(0x6208) |
1692 | #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) |
1693 | #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) |
1694 | #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) |
1695 | |
1696 | #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */ |
1697 | #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) |
1698 | |
1699 | #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */ |
1700 | #define DEUC _MMIO(0x6214) /* CRL only */ |
1701 | |
1702 | #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500) |
1703 | #define FW_CSPWRDWNEN (1 << 15) |
1704 | |
1705 | #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) |
1706 | |
1707 | #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) |
1708 | #define CDCLK_FREQ_SHIFT 4 |
1709 | #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) |
1710 | #define CZCLK_FREQ_MASK 0xf |
1711 | |
1712 | #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C) |
1713 | #define PFI_CREDIT_63 (9 << 28) /* chv only */ |
1714 | #define PFI_CREDIT_31 (8 << 28) /* chv only */ |
1715 | #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */ |
1716 | #define PFI_CREDIT_RESEND (1 << 27) |
1717 | #define VGA_FAST_MODE_DISABLE (1 << 14) |
1718 | |
1719 | #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) |
1720 | |
1721 | /* |
1722 | * Palette regs |
1723 | */ |
1724 | #define _PALETTE_A 0xa000 |
1725 | #define _PALETTE_B 0xa800 |
1726 | #define _CHV_PALETTE_C 0xc000 |
1727 | /* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */ |
1728 | #define PALETTE_RED_MASK REG_GENMASK(23, 16) |
1729 | #define PALETTE_GREEN_MASK REG_GENMASK(15, 8) |
1730 | #define PALETTE_BLUE_MASK REG_GENMASK(7, 0) |
1731 | /* pre-i965 10bit interpolated mode ldw */ |
1732 | #define PALETTE_10BIT_RED_LDW_MASK REG_GENMASK(23, 16) |
1733 | #define PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8) |
1734 | #define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0) |
1735 | /* pre-i965 10bit interpolated mode udw */ |
1736 | #define PALETTE_10BIT_RED_EXP_MASK REG_GENMASK(23, 22) |
1737 | #define PALETTE_10BIT_RED_MANT_MASK REG_GENMASK(21, 18) |
1738 | #define PALETTE_10BIT_RED_UDW_MASK REG_GENMASK(17, 16) |
1739 | #define PALETTE_10BIT_GREEN_EXP_MASK REG_GENMASK(15, 14) |
1740 | #define PALETTE_10BIT_GREEN_MANT_MASK REG_GENMASK(13, 10) |
1741 | #define PALETTE_10BIT_GREEN_UDW_MASK REG_GENMASK(9, 8) |
1742 | #define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6) |
1743 | #define PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2) |
1744 | #define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0) |
1745 | #define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ |
1746 | _PICK_EVEN_2RANGES(pipe, 2, \ |
1747 | _PALETTE_A, _PALETTE_B, \ |
1748 | _CHV_PALETTE_C, _CHV_PALETTE_C) + \ |
1749 | (i) * 4) |
1750 | |
1751 | #define PEG_BAND_GAP_DATA _MMIO(0x14d68) |
1752 | |
1753 | #define BXT_RP_STATE_CAP _MMIO(0x138170) |
1754 | #define GEN9_RP_STATE_LIMITS _MMIO(0x138148) |
1755 | #define XEHPSDV_RP_STATE_CAP _MMIO(0x250014) |
1756 | #define PVC_RP_STATE_CAP _MMIO(0x281014) |
1757 | |
1758 | #define MTL_RP_STATE_CAP _MMIO(0x138000) |
1759 | #define MTL_MEDIAP_STATE_CAP _MMIO(0x138020) |
1760 | #define MTL_RP0_CAP_MASK REG_GENMASK(8, 0) |
1761 | #define MTL_RPN_CAP_MASK REG_GENMASK(24, 16) |
1762 | |
1763 | #define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c) |
1764 | #define MTL_MPE_FREQUENCY _MMIO(0x13802c) |
1765 | #define MTL_RPE_MASK REG_GENMASK(8, 0) |
1766 | |
1767 | #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8) |
1768 | #define GT0_PERF_LIMIT_REASONS_MASK 0xde3 |
1769 | #define PROCHOT_MASK REG_BIT(0) |
1770 | #define THERMAL_LIMIT_MASK REG_BIT(1) |
1771 | #define RATL_MASK REG_BIT(5) |
1772 | #define VR_THERMALERT_MASK REG_BIT(6) |
1773 | #define VR_TDC_MASK REG_BIT(7) |
1774 | #define POWER_LIMIT_4_MASK REG_BIT(8) |
1775 | #define POWER_LIMIT_1_MASK REG_BIT(10) |
1776 | #define POWER_LIMIT_2_MASK REG_BIT(11) |
1777 | #define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16) |
1778 | #define MTL_MEDIA_PERF_LIMIT_REASONS _MMIO(0x138030) |
1779 | |
1780 | #define CHV_CLK_CTL1 _MMIO(0x101100) |
1781 | #define VLV_CLK_CTL2 _MMIO(0x101104) |
1782 | #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 |
1783 | |
1784 | /* |
1785 | * Overlay regs |
1786 | */ |
1787 | |
1788 | #define OVADD _MMIO(0x30000) |
1789 | #define DOVSTA _MMIO(0x30008) |
1790 | #define OC_BUF (0x3 << 20) |
1791 | #define OGAMC5 _MMIO(0x30010) |
1792 | #define OGAMC4 _MMIO(0x30014) |
1793 | #define OGAMC3 _MMIO(0x30018) |
1794 | #define OGAMC2 _MMIO(0x3001c) |
1795 | #define OGAMC1 _MMIO(0x30020) |
1796 | #define OGAMC0 _MMIO(0x30024) |
1797 | |
1798 | /* |
1799 | * GEN9 clock gating regs |
1800 | */ |
1801 | #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) |
1802 | #define DARBF_GATING_DIS REG_BIT(27) |
1803 | #define MTL_PIPEDMC_GATING_DIS_A REG_BIT(15) |
1804 | #define MTL_PIPEDMC_GATING_DIS_B REG_BIT(14) |
1805 | #define PWM2_GATING_DIS REG_BIT(14) |
1806 | #define PWM1_GATING_DIS REG_BIT(13) |
1807 | |
1808 | #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538) |
1809 | #define TGL_VRH_GATING_DIS REG_BIT(31) |
1810 | #define DPT_GATING_DIS REG_BIT(22) |
1811 | |
1812 | #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) |
1813 | #define BXT_GMBUS_GATING_DIS (1 << 14) |
1814 | |
1815 | #define GEN9_CLKGATE_DIS_5 _MMIO(0x46540) |
1816 | #define DPCE_GATING_DIS REG_BIT(17) |
1817 | |
1818 | #define _CLKGATE_DIS_PSL_A 0x46520 |
1819 | #define _CLKGATE_DIS_PSL_B 0x46524 |
1820 | #define _CLKGATE_DIS_PSL_C 0x46528 |
1821 | #define DUPS1_GATING_DIS (1 << 15) |
1822 | #define DUPS2_GATING_DIS (1 << 19) |
1823 | #define DUPS3_GATING_DIS (1 << 23) |
1824 | #define CURSOR_GATING_DIS REG_BIT(28) |
1825 | #define DPF_GATING_DIS (1 << 10) |
1826 | #define DPF_RAM_GATING_DIS (1 << 9) |
1827 | #define DPFR_GATING_DIS (1 << 8) |
1828 | |
1829 | #define CLKGATE_DIS_PSL(pipe) \ |
1830 | _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B) |
1831 | |
1832 | #define _CLKGATE_DIS_PSL_EXT_A 0x4654C |
1833 | #define _CLKGATE_DIS_PSL_EXT_B 0x46550 |
1834 | #define PIPEDMC_GATING_DIS REG_BIT(12) |
1835 | |
1836 | #define CLKGATE_DIS_PSL_EXT(pipe) \ |
1837 | _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B) |
1838 | |
1839 | /* DDI Buffer Control */ |
1840 | #define _DDI_CLK_VALFREQ_A 0x64030 |
1841 | #define _DDI_CLK_VALFREQ_B 0x64130 |
1842 | #define DDI_CLK_VALFREQ(port) _MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B) |
1843 | |
1844 | /* |
1845 | * Display engine regs |
1846 | */ |
1847 | |
1848 | /* Pipe A CRC regs */ |
1849 | #define _PIPE_CRC_CTL_A 0x60050 |
1850 | #define PIPE_CRC_ENABLE REG_BIT(31) |
1851 | /* skl+ source selection */ |
1852 | #define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28) |
1853 | #define PIPE_CRC_SOURCE_PLANE_1_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0) |
1854 | #define PIPE_CRC_SOURCE_PLANE_2_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2) |
1855 | #define PIPE_CRC_SOURCE_DMUX_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4) |
1856 | #define PIPE_CRC_SOURCE_PLANE_3_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6) |
1857 | #define PIPE_CRC_SOURCE_PLANE_4_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7) |
1858 | #define PIPE_CRC_SOURCE_PLANE_5_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5) |
1859 | #define PIPE_CRC_SOURCE_PLANE_6_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3) |
1860 | #define PIPE_CRC_SOURCE_PLANE_7_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1) |
1861 | /* ivb+ source selection */ |
1862 | #define PIPE_CRC_SOURCE_MASK_IVB REG_GENMASK(30, 29) |
1863 | #define PIPE_CRC_SOURCE_PRIMARY_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0) |
1864 | #define PIPE_CRC_SOURCE_SPRITE_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1) |
1865 | #define PIPE_CRC_SOURCE_PF_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2) |
1866 | /* ilk+ source selection */ |
1867 | #define PIPE_CRC_SOURCE_MASK_ILK REG_GENMASK(30, 28) |
1868 | #define PIPE_CRC_SOURCE_PRIMARY_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0) |
1869 | #define PIPE_CRC_SOURCE_SPRITE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1) |
1870 | #define PIPE_CRC_SOURCE_PIPE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2) |
1871 | /* embedded DP port on the north display block */ |
1872 | #define PIPE_CRC_SOURCE_PORT_A_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4) |
1873 | #define PIPE_CRC_SOURCE_FDI_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5) |
1874 | /* vlv source selection */ |
1875 | #define PIPE_CRC_SOURCE_MASK_VLV REG_GENMASK(30, 27) |
1876 | #define PIPE_CRC_SOURCE_PIPE_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0) |
1877 | #define PIPE_CRC_SOURCE_HDMIB_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1) |
1878 | #define PIPE_CRC_SOURCE_HDMIC_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2) |
1879 | /* with DP port the pipe source is invalid */ |
1880 | #define PIPE_CRC_SOURCE_DP_D_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3) |
1881 | #define PIPE_CRC_SOURCE_DP_B_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6) |
1882 | #define PIPE_CRC_SOURCE_DP_C_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7) |
1883 | /* gen3+ source selection */ |
1884 | #define PIPE_CRC_SOURCE_MASK_I9XX REG_GENMASK(30, 28) |
1885 | #define PIPE_CRC_SOURCE_PIPE_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0) |
1886 | #define PIPE_CRC_SOURCE_SDVOB_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1) |
1887 | #define PIPE_CRC_SOURCE_SDVOC_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2) |
1888 | /* with DP/TV port the pipe source is invalid */ |
1889 | #define PIPE_CRC_SOURCE_DP_D_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3) |
1890 | #define PIPE_CRC_SOURCE_TV_PRE REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4) |
1891 | #define PIPE_CRC_SOURCE_TV_POST REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5) |
1892 | #define PIPE_CRC_SOURCE_DP_B_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6) |
1893 | #define PIPE_CRC_SOURCE_DP_C_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7) |
1894 | /* gen2 doesn't have source selection bits */ |
1895 | #define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30) |
1896 | |
1897 | #define _PIPE_CRC_RES_1_A_IVB 0x60064 |
1898 | #define _PIPE_CRC_RES_2_A_IVB 0x60068 |
1899 | #define _PIPE_CRC_RES_3_A_IVB 0x6006c |
1900 | #define _PIPE_CRC_RES_4_A_IVB 0x60070 |
1901 | #define _PIPE_CRC_RES_5_A_IVB 0x60074 |
1902 | |
1903 | #define _PIPE_CRC_RES_RED_A 0x60060 |
1904 | #define _PIPE_CRC_RES_GREEN_A 0x60064 |
1905 | #define _PIPE_CRC_RES_BLUE_A 0x60068 |
1906 | #define _PIPE_CRC_RES_RES1_A_I915 0x6006c |
1907 | #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 |
1908 | |
1909 | /* Pipe B CRC regs */ |
1910 | #define _PIPE_CRC_RES_1_B_IVB 0x61064 |
1911 | #define _PIPE_CRC_RES_2_B_IVB 0x61068 |
1912 | #define _PIPE_CRC_RES_3_B_IVB 0x6106c |
1913 | #define _PIPE_CRC_RES_4_B_IVB 0x61070 |
1914 | #define _PIPE_CRC_RES_5_B_IVB 0x61074 |
1915 | |
1916 | #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A) |
1917 | #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB) |
1918 | #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB) |
1919 | #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB) |
1920 | #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB) |
1921 | #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB) |
1922 | |
1923 | #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A) |
1924 | #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A) |
1925 | #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A) |
1926 | #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915) |
1927 | #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X) |
1928 | |
1929 | /* Pipe/transcoder A timing regs */ |
1930 | #define _TRANS_HTOTAL_A 0x60000 |
1931 | #define HTOTAL_MASK REG_GENMASK(31, 16) |
1932 | #define HTOTAL(htotal) REG_FIELD_PREP(HTOTAL_MASK, (htotal)) |
1933 | #define HACTIVE_MASK REG_GENMASK(15, 0) |
1934 | #define HACTIVE(hdisplay) REG_FIELD_PREP(HACTIVE_MASK, (hdisplay)) |
1935 | #define _TRANS_HBLANK_A 0x60004 |
1936 | #define HBLANK_END_MASK REG_GENMASK(31, 16) |
1937 | #define HBLANK_END(hblank_end) REG_FIELD_PREP(HBLANK_END_MASK, (hblank_end)) |
1938 | #define HBLANK_START_MASK REG_GENMASK(15, 0) |
1939 | #define HBLANK_START(hblank_start) REG_FIELD_PREP(HBLANK_START_MASK, (hblank_start)) |
1940 | #define _TRANS_HSYNC_A 0x60008 |
1941 | #define HSYNC_END_MASK REG_GENMASK(31, 16) |
1942 | #define HSYNC_END(hsync_end) REG_FIELD_PREP(HSYNC_END_MASK, (hsync_end)) |
1943 | #define HSYNC_START_MASK REG_GENMASK(15, 0) |
1944 | #define HSYNC_START(hsync_start) REG_FIELD_PREP(HSYNC_START_MASK, (hsync_start)) |
1945 | #define _TRANS_VTOTAL_A 0x6000c |
1946 | #define VTOTAL_MASK REG_GENMASK(31, 16) |
1947 | #define VTOTAL(vtotal) REG_FIELD_PREP(VTOTAL_MASK, (vtotal)) |
1948 | #define VACTIVE_MASK REG_GENMASK(15, 0) |
1949 | #define VACTIVE(vdisplay) REG_FIELD_PREP(VACTIVE_MASK, (vdisplay)) |
1950 | #define _TRANS_VBLANK_A 0x60010 |
1951 | #define VBLANK_END_MASK REG_GENMASK(31, 16) |
1952 | #define VBLANK_END(vblank_end) REG_FIELD_PREP(VBLANK_END_MASK, (vblank_end)) |
1953 | #define VBLANK_START_MASK REG_GENMASK(15, 0) |
1954 | #define VBLANK_START(vblank_start) REG_FIELD_PREP(VBLANK_START_MASK, (vblank_start)) |
1955 | #define _TRANS_VSYNC_A 0x60014 |
1956 | #define VSYNC_END_MASK REG_GENMASK(31, 16) |
1957 | #define VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end)) |
1958 | #define VSYNC_START_MASK REG_GENMASK(15, 0) |
1959 | #define VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start)) |
1960 | #define _TRANS_EXITLINE_A 0x60018 |
1961 | #define _PIPEASRC 0x6001c |
1962 | #define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16) |
1963 | #define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w)) |
1964 | #define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0) |
1965 | #define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h)) |
1966 | #define _BCLRPAT_A 0x60020 |
1967 | #define _TRANS_VSYNCSHIFT_A 0x60028 |
1968 | #define _TRANS_MULT_A 0x6002c |
1969 | |
1970 | /* Pipe/transcoder B timing regs */ |
1971 | #define _TRANS_HTOTAL_B 0x61000 |
1972 | #define _TRANS_HBLANK_B 0x61004 |
1973 | #define _TRANS_HSYNC_B 0x61008 |
1974 | #define _TRANS_VTOTAL_B 0x6100c |
1975 | #define _TRANS_VBLANK_B 0x61010 |
1976 | #define _TRANS_VSYNC_B 0x61014 |
1977 | #define _PIPEBSRC 0x6101c |
1978 | #define _BCLRPAT_B 0x61020 |
1979 | #define _TRANS_VSYNCSHIFT_B 0x61028 |
1980 | #define _TRANS_MULT_B 0x6102c |
1981 | |
1982 | /* DSI 0 timing regs */ |
1983 | #define _TRANS_HTOTAL_DSI0 0x6b000 |
1984 | #define _TRANS_HSYNC_DSI0 0x6b008 |
1985 | #define _TRANS_VTOTAL_DSI0 0x6b00c |
1986 | #define _TRANS_VSYNC_DSI0 0x6b014 |
1987 | #define _TRANS_VSYNCSHIFT_DSI0 0x6b028 |
1988 | |
1989 | /* DSI 1 timing regs */ |
1990 | #define _TRANS_HTOTAL_DSI1 0x6b800 |
1991 | #define _TRANS_HSYNC_DSI1 0x6b808 |
1992 | #define _TRANS_VTOTAL_DSI1 0x6b80c |
1993 | #define _TRANS_VSYNC_DSI1 0x6b814 |
1994 | #define _TRANS_VSYNCSHIFT_DSI1 0x6b828 |
1995 | |
1996 | #define TRANS_HTOTAL(trans) _MMIO_TRANS2((trans), _TRANS_HTOTAL_A) |
1997 | #define TRANS_HBLANK(trans) _MMIO_TRANS2((trans), _TRANS_HBLANK_A) |
1998 | #define TRANS_HSYNC(trans) _MMIO_TRANS2((trans), _TRANS_HSYNC_A) |
1999 | #define TRANS_VTOTAL(trans) _MMIO_TRANS2((trans), _TRANS_VTOTAL_A) |
2000 | #define TRANS_VBLANK(trans) _MMIO_TRANS2((trans), _TRANS_VBLANK_A) |
2001 | #define TRANS_VSYNC(trans) _MMIO_TRANS2((trans), _TRANS_VSYNC_A) |
2002 | #define BCLRPAT(trans) _MMIO_TRANS2((trans), _BCLRPAT_A) |
2003 | #define TRANS_VSYNCSHIFT(trans) _MMIO_TRANS2((trans), _TRANS_VSYNCSHIFT_A) |
2004 | #define PIPESRC(pipe) _MMIO_TRANS2((pipe), _PIPEASRC) |
2005 | #define TRANS_MULT(trans) _MMIO_TRANS2((trans), _TRANS_MULT_A) |
2006 | |
2007 | /* VRR registers */ |
2008 | #define _TRANS_VRR_CTL_A 0x60420 |
2009 | #define _TRANS_VRR_CTL_B 0x61420 |
2010 | #define _TRANS_VRR_CTL_C 0x62420 |
2011 | #define _TRANS_VRR_CTL_D 0x63420 |
2012 | #define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A) |
2013 | #define VRR_CTL_VRR_ENABLE REG_BIT(31) |
2014 | #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) |
2015 | #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) |
2016 | #define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3) |
2017 | #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) |
2018 | #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) |
2019 | #define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) |
2020 | #define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x)) |
2021 | |
2022 | #define _TRANS_VRR_VMAX_A 0x60424 |
2023 | #define _TRANS_VRR_VMAX_B 0x61424 |
2024 | #define _TRANS_VRR_VMAX_C 0x62424 |
2025 | #define _TRANS_VRR_VMAX_D 0x63424 |
2026 | #define TRANS_VRR_VMAX(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMAX_A) |
2027 | #define VRR_VMAX_MASK REG_GENMASK(19, 0) |
2028 | |
2029 | #define _TRANS_VRR_VMIN_A 0x60434 |
2030 | #define _TRANS_VRR_VMIN_B 0x61434 |
2031 | #define _TRANS_VRR_VMIN_C 0x62434 |
2032 | #define _TRANS_VRR_VMIN_D 0x63434 |
2033 | #define TRANS_VRR_VMIN(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMIN_A) |
2034 | #define VRR_VMIN_MASK REG_GENMASK(15, 0) |
2035 | |
2036 | #define _TRANS_VRR_VMAXSHIFT_A 0x60428 |
2037 | #define _TRANS_VRR_VMAXSHIFT_B 0x61428 |
2038 | #define _TRANS_VRR_VMAXSHIFT_C 0x62428 |
2039 | #define _TRANS_VRR_VMAXSHIFT_D 0x63428 |
2040 | #define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(trans, \ |
2041 | _TRANS_VRR_VMAXSHIFT_A) |
2042 | #define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16) |
2043 | #define VRR_VMAXSHIFT_DEC REG_BIT(16) |
2044 | #define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0) |
2045 | |
2046 | #define _TRANS_VRR_STATUS_A 0x6042C |
2047 | #define _TRANS_VRR_STATUS_B 0x6142C |
2048 | #define _TRANS_VRR_STATUS_C 0x6242C |
2049 | #define _TRANS_VRR_STATUS_D 0x6342C |
2050 | #define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS_A) |
2051 | #define VRR_STATUS_VMAX_REACHED REG_BIT(31) |
2052 | #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) |
2053 | #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) |
2054 | #define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28) |
2055 | #define VRR_STATUS_VRR_EN_LIVE REG_BIT(27) |
2056 | #define VRR_STATUS_FLIPS_SERVICED REG_BIT(26) |
2057 | #define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20) |
2058 | #define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0) |
2059 | #define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1) |
2060 | #define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2) |
2061 | #define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3) |
2062 | #define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4) |
2063 | #define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5) |
2064 | #define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6) |
2065 | |
2066 | #define _TRANS_VRR_VTOTAL_PREV_A 0x60480 |
2067 | #define _TRANS_VRR_VTOTAL_PREV_B 0x61480 |
2068 | #define _TRANS_VRR_VTOTAL_PREV_C 0x62480 |
2069 | #define _TRANS_VRR_VTOTAL_PREV_D 0x63480 |
2070 | #define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(trans, \ |
2071 | _TRANS_VRR_VTOTAL_PREV_A) |
2072 | #define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31) |
2073 | #define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30) |
2074 | #define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29) |
2075 | #define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0) |
2076 | |
2077 | #define _TRANS_VRR_FLIPLINE_A 0x60438 |
2078 | #define _TRANS_VRR_FLIPLINE_B 0x61438 |
2079 | #define _TRANS_VRR_FLIPLINE_C 0x62438 |
2080 | #define _TRANS_VRR_FLIPLINE_D 0x63438 |
2081 | #define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(trans, \ |
2082 | _TRANS_VRR_FLIPLINE_A) |
2083 | #define VRR_FLIPLINE_MASK REG_GENMASK(19, 0) |
2084 | |
2085 | #define _TRANS_VRR_STATUS2_A 0x6043C |
2086 | #define _TRANS_VRR_STATUS2_B 0x6143C |
2087 | #define _TRANS_VRR_STATUS2_C 0x6243C |
2088 | #define _TRANS_VRR_STATUS2_D 0x6343C |
2089 | #define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A) |
2090 | #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) |
2091 | |
2092 | #define _TRANS_PUSH_A 0x60A70 |
2093 | #define _TRANS_PUSH_B 0x61A70 |
2094 | #define _TRANS_PUSH_C 0x62A70 |
2095 | #define _TRANS_PUSH_D 0x63A70 |
2096 | #define TRANS_PUSH(trans) _MMIO_TRANS2(trans, _TRANS_PUSH_A) |
2097 | #define TRANS_PUSH_EN REG_BIT(31) |
2098 | #define TRANS_PUSH_SEND REG_BIT(30) |
2099 | |
2100 | /* VGA port control */ |
2101 | #define ADPA _MMIO(0x61100) |
2102 | #define PCH_ADPA _MMIO(0xe1100) |
2103 | #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) |
2104 | |
2105 | #define ADPA_DAC_ENABLE (1 << 31) |
2106 | #define ADPA_DAC_DISABLE 0 |
2107 | #define ADPA_PIPE_SEL_SHIFT 30 |
2108 | #define ADPA_PIPE_SEL_MASK (1 << 30) |
2109 | #define ADPA_PIPE_SEL(pipe) ((pipe) << 30) |
2110 | #define ADPA_PIPE_SEL_SHIFT_CPT 29 |
2111 | #define ADPA_PIPE_SEL_MASK_CPT (3 << 29) |
2112 | #define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29) |
2113 | #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ |
2114 | #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24) |
2115 | #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24) |
2116 | #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24) |
2117 | #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24) |
2118 | #define ADPA_CRT_HOTPLUG_ENABLE (1 << 23) |
2119 | #define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22) |
2120 | #define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22) |
2121 | #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21) |
2122 | #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21) |
2123 | #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20) |
2124 | #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20) |
2125 | #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18) |
2126 | #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18) |
2127 | #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18) |
2128 | #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18) |
2129 | #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17) |
2130 | #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17) |
2131 | #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16) |
2132 | #define ADPA_USE_VGA_HVPOLARITY (1 << 15) |
2133 | #define ADPA_SETS_HVPOLARITY 0 |
2134 | #define ADPA_VSYNC_CNTL_DISABLE (1 << 10) |
2135 | #define ADPA_VSYNC_CNTL_ENABLE 0 |
2136 | #define ADPA_HSYNC_CNTL_DISABLE (1 << 11) |
2137 | #define ADPA_HSYNC_CNTL_ENABLE 0 |
2138 | #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4) |
2139 | #define ADPA_VSYNC_ACTIVE_LOW 0 |
2140 | #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3) |
2141 | #define ADPA_HSYNC_ACTIVE_LOW 0 |
2142 | #define ADPA_DPMS_MASK (~(3 << 10)) |
2143 | #define ADPA_DPMS_ON (0 << 10) |
2144 | #define ADPA_DPMS_SUSPEND (1 << 10) |
2145 | #define ADPA_DPMS_STANDBY (2 << 10) |
2146 | #define ADPA_DPMS_OFF (3 << 10) |
2147 | |
2148 | |
2149 | /* Hotplug control (945+ only) */ |
2150 | #define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110) |
2151 | #define PORTB_HOTPLUG_INT_EN (1 << 29) |
2152 | #define PORTC_HOTPLUG_INT_EN (1 << 28) |
2153 | #define PORTD_HOTPLUG_INT_EN (1 << 27) |
2154 | #define SDVOB_HOTPLUG_INT_EN (1 << 26) |
2155 | #define SDVOC_HOTPLUG_INT_EN (1 << 25) |
2156 | #define TV_HOTPLUG_INT_EN (1 << 18) |
2157 | #define CRT_HOTPLUG_INT_EN (1 << 9) |
2158 | #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ |
2159 | PORTC_HOTPLUG_INT_EN | \ |
2160 | PORTD_HOTPLUG_INT_EN | \ |
2161 | SDVOC_HOTPLUG_INT_EN | \ |
2162 | SDVOB_HOTPLUG_INT_EN | \ |
2163 | CRT_HOTPLUG_INT_EN) |
2164 | #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) |
2165 | #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) |
2166 | /* must use period 64 on GM45 according to docs */ |
2167 | #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) |
2168 | #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) |
2169 | #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) |
2170 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) |
2171 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) |
2172 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) |
2173 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) |
2174 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) |
2175 | #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) |
2176 | #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) |
2177 | #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) |
2178 | #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) |
2179 | |
2180 | #define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114) |
2181 | /* HDMI/DP bits are g4x+ */ |
2182 | #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) |
2183 | #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) |
2184 | #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29) |
2185 | #define PORTD_HOTPLUG_INT_STATUS (3 << 21) |
2186 | #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) |
2187 | #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) |
2188 | #define PORTC_HOTPLUG_INT_STATUS (3 << 19) |
2189 | #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) |
2190 | #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) |
2191 | #define PORTB_HOTPLUG_INT_STATUS (3 << 17) |
2192 | #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) |
2193 | #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) |
2194 | /* CRT/TV common between gen3+ */ |
2195 | #define CRT_HOTPLUG_INT_STATUS (1 << 11) |
2196 | #define TV_HOTPLUG_INT_STATUS (1 << 10) |
2197 | #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) |
2198 | #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) |
2199 | #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) |
2200 | #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) |
2201 | #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) |
2202 | #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) |
2203 | #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) |
2204 | #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) |
2205 | |
2206 | /* SDVO is different across gen3/4 */ |
2207 | #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) |
2208 | #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) |
2209 | /* |
2210 | * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, |
2211 | * since reality corrobates that they're the same as on gen3. But keep these |
2212 | * bits here (and the comment!) to help any other lost wanderers back onto the |
2213 | * right tracks. |
2214 | */ |
2215 | #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) |
2216 | #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) |
2217 | #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) |
2218 | #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) |
2219 | #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ |
2220 | SDVOB_HOTPLUG_INT_STATUS_G4X | \ |
2221 | SDVOC_HOTPLUG_INT_STATUS_G4X | \ |
2222 | PORTB_HOTPLUG_INT_STATUS | \ |
2223 | PORTC_HOTPLUG_INT_STATUS | \ |
2224 | PORTD_HOTPLUG_INT_STATUS) |
2225 | |
2226 | #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ |
2227 | SDVOB_HOTPLUG_INT_STATUS_I915 | \ |
2228 | SDVOC_HOTPLUG_INT_STATUS_I915 | \ |
2229 | PORTB_HOTPLUG_INT_STATUS | \ |
2230 | PORTC_HOTPLUG_INT_STATUS | \ |
2231 | PORTD_HOTPLUG_INT_STATUS) |
2232 | |
2233 | /* SDVO and HDMI port control. |
2234 | * The same register may be used for SDVO or HDMI */ |
2235 | #define _GEN3_SDVOB 0x61140 |
2236 | #define _GEN3_SDVOC 0x61160 |
2237 | #define GEN3_SDVOB _MMIO(_GEN3_SDVOB) |
2238 | #define GEN3_SDVOC _MMIO(_GEN3_SDVOC) |
2239 | #define GEN4_HDMIB GEN3_SDVOB |
2240 | #define GEN4_HDMIC GEN3_SDVOC |
2241 | #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140) |
2242 | #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160) |
2243 | #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C) |
2244 | #define PCH_SDVOB _MMIO(0xe1140) |
2245 | #define PCH_HDMIB PCH_SDVOB |
2246 | #define PCH_HDMIC _MMIO(0xe1150) |
2247 | #define PCH_HDMID _MMIO(0xe1160) |
2248 | |
2249 | #define PORT_DFT_I9XX _MMIO(0x61150) |
2250 | #define DC_BALANCE_RESET (1 << 25) |
2251 | #define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154) |
2252 | #define DC_BALANCE_RESET_VLV (1 << 31) |
2253 | #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) |
2254 | #define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */ |
2255 | #define PIPE_B_SCRAMBLE_RESET REG_BIT(1) |
2256 | #define PIPE_A_SCRAMBLE_RESET REG_BIT(0) |
2257 | |
2258 | /* Gen 3 SDVO bits: */ |
2259 | #define SDVO_ENABLE (1 << 31) |
2260 | #define SDVO_PIPE_SEL_SHIFT 30 |
2261 | #define SDVO_PIPE_SEL_MASK (1 << 30) |
2262 | #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) |
2263 | #define SDVO_STALL_SELECT (1 << 29) |
2264 | #define SDVO_INTERRUPT_ENABLE (1 << 26) |
2265 | /* |
2266 | * 915G/GM SDVO pixel multiplier. |
2267 | * Programmed value is multiplier - 1, up to 5x. |
2268 | * \sa DPLL_MD_UDI_MULTIPLIER_MASK |
2269 | */ |
2270 | #define SDVO_PORT_MULTIPLY_MASK (7 << 23) |
2271 | #define SDVO_PORT_MULTIPLY_SHIFT 23 |
2272 | #define SDVO_PHASE_SELECT_MASK (15 << 19) |
2273 | #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) |
2274 | #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) |
2275 | #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ |
2276 | #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ |
2277 | #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ |
2278 | #define SDVO_DETECTED (1 << 2) |
2279 | /* Bits to be preserved when writing */ |
2280 | #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ |
2281 | SDVO_INTERRUPT_ENABLE) |
2282 | #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) |
2283 | |
2284 | /* Gen 4 SDVO/HDMI bits: */ |
2285 | #define SDVO_COLOR_FORMAT_8bpc (0 << 26) |
2286 | #define SDVO_COLOR_FORMAT_MASK (7 << 26) |
2287 | #define SDVO_ENCODING_SDVO (0 << 10) |
2288 | #define SDVO_ENCODING_HDMI (2 << 10) |
2289 | #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ |
2290 | #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ |
2291 | #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ |
2292 | #define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */ |
2293 | /* VSYNC/HSYNC bits new with 965, default is to be set */ |
2294 | #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) |
2295 | #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) |
2296 | |
2297 | /* Gen 5 (IBX) SDVO/HDMI bits: */ |
2298 | #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ |
2299 | #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ |
2300 | |
2301 | /* Gen 6 (CPT) SDVO/HDMI bits: */ |
2302 | #define SDVO_PIPE_SEL_SHIFT_CPT 29 |
2303 | #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) |
2304 | #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) |
2305 | |
2306 | /* CHV SDVO/HDMI bits: */ |
2307 | #define SDVO_PIPE_SEL_SHIFT_CHV 24 |
2308 | #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) |
2309 | #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) |
2310 | |
2311 | /* Video Data Island Packet control */ |
2312 | #define VIDEO_DIP_DATA _MMIO(0x61178) |
2313 | /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC |
2314 | * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte |
2315 | * of the infoframe structure specified by CEA-861. */ |
2316 | #define VIDEO_DIP_DATA_SIZE 32 |
2317 | #define VIDEO_DIP_GMP_DATA_SIZE 36 |
2318 | #define VIDEO_DIP_VSC_DATA_SIZE 36 |
2319 | #define VIDEO_DIP_PPS_DATA_SIZE 132 |
2320 | #define VIDEO_DIP_CTL _MMIO(0x61170) |
2321 | /* Pre HSW: */ |
2322 | #define VIDEO_DIP_ENABLE (1 << 31) |
2323 | #define VIDEO_DIP_PORT(port) ((port) << 29) |
2324 | #define VIDEO_DIP_PORT_MASK (3 << 29) |
2325 | #define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */ |
2326 | #define VIDEO_DIP_ENABLE_AVI (1 << 21) |
2327 | #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) |
2328 | #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */ |
2329 | #define VIDEO_DIP_ENABLE_SPD (8 << 21) |
2330 | #define VIDEO_DIP_SELECT_AVI (0 << 19) |
2331 | #define VIDEO_DIP_SELECT_VENDOR (1 << 19) |
2332 | #define VIDEO_DIP_SELECT_GAMUT (2 << 19) |
2333 | #define VIDEO_DIP_SELECT_SPD (3 << 19) |
2334 | #define VIDEO_DIP_SELECT_MASK (3 << 19) |
2335 | #define VIDEO_DIP_FREQ_ONCE (0 << 16) |
2336 | #define VIDEO_DIP_FREQ_VSYNC (1 << 16) |
2337 | #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) |
2338 | #define VIDEO_DIP_FREQ_MASK (3 << 16) |
2339 | /* HSW and later: */ |
2340 | #define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28) |
2341 | #define PSR_VSC_BIT_7_SET (1 << 27) |
2342 | #define VSC_SELECT_MASK (0x3 << 25) |
2343 | #define VSC_SELECT_SHIFT 25 |
2344 | #define VSC_DIP_HW_HEA_DATA (0 << 25) |
2345 | #define VSC_DIP_HW_HEA_SW_DATA (1 << 25) |
2346 | #define VSC_DIP_HW_DATA_SW_HEA (2 << 25) |
2347 | #define VSC_DIP_SW_HEA_DATA (3 << 25) |
2348 | #define VDIP_ENABLE_PPS (1 << 24) |
2349 | #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) |
2350 | #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) |
2351 | #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) |
2352 | #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) |
2353 | #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) |
2354 | #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) |
2355 | |
2356 | /* Panel fitting */ |
2357 | #define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) |
2358 | #define PFIT_ENABLE REG_BIT(31) |
2359 | #define PFIT_PIPE_MASK REG_GENMASK(30, 29) /* 965+ */ |
2360 | #define PFIT_PIPE(pipe) REG_FIELD_PREP(PFIT_PIPE_MASK, (pipe)) |
2361 | #define PFIT_SCALING_MASK REG_GENMASK(28, 26) /* 965+ */ |
2362 | #define PFIT_SCALING_AUTO REG_FIELD_PREP(PFIT_SCALING_MASK, 0) |
2363 | #define PFIT_SCALING_PROGRAMMED REG_FIELD_PREP(PFIT_SCALING_MASK, 1) |
2364 | #define PFIT_SCALING_PILLAR REG_FIELD_PREP(PFIT_SCALING_MASK, 2) |
2365 | #define PFIT_SCALING_LETTER REG_FIELD_PREP(PFIT_SCALING_MASK, 3) |
2366 | #define PFIT_FILTER_MASK REG_GENMASK(25, 24) /* 965+ */ |
2367 | #define PFIT_FILTER_FUZZY REG_FIELD_PREP(PFIT_FILTER_MASK, 0) |
2368 | #define PFIT_FILTER_CRISP REG_FIELD_PREP(PFIT_FILTER_MASK, 1) |
2369 | #define PFIT_FILTER_MEDIAN REG_FIELD_PREP(PFIT_FILTER_MASK, 2) |
2370 | #define PFIT_VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */ |
2371 | #define PFIT_VERT_INTERP_BILINEAR REG_FIELD_PREP(PFIT_VERT_INTERP_MASK, 1) |
2372 | #define PFIT_VERT_AUTO_SCALE REG_BIT(9) /* pre-965 */ |
2373 | #define PFIT_HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */ |
2374 | #define PFIT_HORIZ_INTERP_BILINEAR REG_FIELD_PREP(PFIT_HORIZ_INTERP_MASK, 1) |
2375 | #define PFIT_HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */ |
2376 | #define PFIT_PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */ |
2377 | |
2378 | #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) |
2379 | #define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */ |
2380 | #define PFIT_VERT_SCALE(x) REG_FIELD_PREP(PFIT_VERT_SCALE_MASK, (x)) |
2381 | #define PFIT_HORIZ_SCALE_MASK REG_GENMASK(15, 4) /* pre-965 */ |
2382 | #define PFIT_HORIZ_SCALE(x) REG_FIELD_PREP(PFIT_HORIZ_SCALE_MASK, (x)) |
2383 | #define PFIT_VERT_SCALE_MASK_965 REG_GENMASK(28, 16) /* 965+ */ |
2384 | #define PFIT_HORIZ_SCALE_MASK_965 REG_GENMASK(12, 0) /* 965+ */ |
2385 | |
2386 | #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) |
2387 | |
2388 | #define PCH_GTC_CTL _MMIO(0xe7000) |
2389 | #define PCH_GTC_ENABLE (1 << 31) |
2390 | |
2391 | /* Display Port */ |
2392 | #define DP_A _MMIO(0x64000) /* eDP */ |
2393 | #define DP_B _MMIO(0x64100) |
2394 | #define DP_C _MMIO(0x64200) |
2395 | #define DP_D _MMIO(0x64300) |
2396 | |
2397 | #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100) |
2398 | #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200) |
2399 | #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300) |
2400 | |
2401 | #define DP_PORT_EN (1 << 31) |
2402 | #define DP_PIPE_SEL_SHIFT 30 |
2403 | #define DP_PIPE_SEL_MASK (1 << 30) |
2404 | #define DP_PIPE_SEL(pipe) ((pipe) << 30) |
2405 | #define DP_PIPE_SEL_SHIFT_IVB 29 |
2406 | #define DP_PIPE_SEL_MASK_IVB (3 << 29) |
2407 | #define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29) |
2408 | #define DP_PIPE_SEL_SHIFT_CHV 16 |
2409 | #define DP_PIPE_SEL_MASK_CHV (3 << 16) |
2410 | #define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16) |
2411 | |
2412 | /* Link training mode - select a suitable mode for each stage */ |
2413 | #define DP_LINK_TRAIN_PAT_1 (0 << 28) |
2414 | #define DP_LINK_TRAIN_PAT_2 (1 << 28) |
2415 | #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) |
2416 | #define DP_LINK_TRAIN_OFF (3 << 28) |
2417 | #define DP_LINK_TRAIN_MASK (3 << 28) |
2418 | #define DP_LINK_TRAIN_SHIFT 28 |
2419 | |
2420 | /* CPT Link training mode */ |
2421 | #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) |
2422 | #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) |
2423 | #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) |
2424 | #define DP_LINK_TRAIN_OFF_CPT (3 << 8) |
2425 | #define DP_LINK_TRAIN_MASK_CPT (7 << 8) |
2426 | #define DP_LINK_TRAIN_SHIFT_CPT 8 |
2427 | |
2428 | /* Signal voltages. These are mostly controlled by the other end */ |
2429 | #define DP_VOLTAGE_0_4 (0 << 25) |
2430 | #define DP_VOLTAGE_0_6 (1 << 25) |
2431 | #define DP_VOLTAGE_0_8 (2 << 25) |
2432 | #define DP_VOLTAGE_1_2 (3 << 25) |
2433 | #define DP_VOLTAGE_MASK (7 << 25) |
2434 | #define DP_VOLTAGE_SHIFT 25 |
2435 | |
2436 | /* Signal pre-emphasis levels, like voltages, the other end tells us what |
2437 | * they want |
2438 | */ |
2439 | #define DP_PRE_EMPHASIS_0 (0 << 22) |
2440 | #define DP_PRE_EMPHASIS_3_5 (1 << 22) |
2441 | #define DP_PRE_EMPHASIS_6 (2 << 22) |
2442 | #define DP_PRE_EMPHASIS_9_5 (3 << 22) |
2443 | #define DP_PRE_EMPHASIS_MASK (7 << 22) |
2444 | #define DP_PRE_EMPHASIS_SHIFT 22 |
2445 | |
2446 | /* How many wires to use. I guess 3 was too hard */ |
2447 | #define DP_PORT_WIDTH(width) (((width) - 1) << 19) |
2448 | #define DP_PORT_WIDTH_MASK (7 << 19) |
2449 | #define DP_PORT_WIDTH_SHIFT 19 |
2450 | |
2451 | /* Mystic DPCD version 1.1 special mode */ |
2452 | #define DP_ENHANCED_FRAMING (1 << 18) |
2453 | |
2454 | /* eDP */ |
2455 | #define DP_PLL_FREQ_270MHZ (0 << 16) |
2456 | #define DP_PLL_FREQ_162MHZ (1 << 16) |
2457 | #define DP_PLL_FREQ_MASK (3 << 16) |
2458 | |
2459 | /* locked once port is enabled */ |
2460 | #define DP_PORT_REVERSAL (1 << 15) |
2461 | |
2462 | /* eDP */ |
2463 | #define DP_PLL_ENABLE (1 << 14) |
2464 | |
2465 | /* sends the clock on lane 15 of the PEG for debug */ |
2466 | #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) |
2467 | |
2468 | #define DP_SCRAMBLING_DISABLE (1 << 12) |
2469 | #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) |
2470 | |
2471 | /* limit RGB values to avoid confusing TVs */ |
2472 | #define DP_COLOR_RANGE_16_235 (1 << 8) |
2473 | |
2474 | /* Turn on the audio link */ |
2475 | #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) |
2476 | |
2477 | /* vs and hs sync polarity */ |
2478 | #define DP_SYNC_VS_HIGH (1 << 4) |
2479 | #define DP_SYNC_HS_HIGH (1 << 3) |
2480 | |
2481 | /* A fantasy */ |
2482 | #define DP_DETECTED (1 << 2) |
2483 | |
2484 | /* |
2485 | * Computing GMCH M and N values for the Display Port link |
2486 | * |
2487 | * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes |
2488 | * |
2489 | * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) |
2490 | * |
2491 | * The GMCH value is used internally |
2492 | * |
2493 | * bytes_per_pixel is the number of bytes coming out of the plane, |
2494 | * which is after the LUTs, so we want the bytes for our color format. |
2495 | * For our current usage, this is always 3, one byte for R, G and B. |
2496 | */ |
2497 | #define _PIPEA_DATA_M_G4X 0x70050 |
2498 | #define _PIPEB_DATA_M_G4X 0x71050 |
2499 | |
2500 | /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ |
2501 | #define TU_SIZE_MASK REG_GENMASK(30, 25) |
2502 | #define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */ |
2503 | |
2504 | #define DATA_LINK_M_N_MASK REG_GENMASK(23, 0) |
2505 | #define DATA_LINK_N_MAX (0x800000) |
2506 | |
2507 | #define _PIPEA_DATA_N_G4X 0x70054 |
2508 | #define _PIPEB_DATA_N_G4X 0x71054 |
2509 | |
2510 | /* |
2511 | * Computing Link M and N values for the Display Port link |
2512 | * |
2513 | * Link M / N = pixel_clock / ls_clk |
2514 | * |
2515 | * (the DP spec calls pixel_clock the 'strm_clk') |
2516 | * |
2517 | * The Link value is transmitted in the Main Stream |
2518 | * Attributes and VB-ID. |
2519 | */ |
2520 | |
2521 | #define _PIPEA_LINK_M_G4X 0x70060 |
2522 | #define _PIPEB_LINK_M_G4X 0x71060 |
2523 | #define _PIPEA_LINK_N_G4X 0x70064 |
2524 | #define _PIPEB_LINK_N_G4X 0x71064 |
2525 | |
2526 | #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) |
2527 | #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) |
2528 | #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) |
2529 | #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) |
2530 | |
2531 | /* Display & cursor control */ |
2532 | |
2533 | /* Pipe A */ |
2534 | #define _PIPEADSL 0x70000 |
2535 | #define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */ |
2536 | #define PIPEDSL_LINE_MASK REG_GENMASK(19, 0) |
2537 | #define _TRANSACONF 0x70008 |
2538 | #define TRANSCONF_ENABLE REG_BIT(31) |
2539 | #define TRANSCONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */ |
2540 | #define TRANSCONF_STATE_ENABLE REG_BIT(30) /* i965+ */ |
2541 | #define TRANSCONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */ |
2542 | #define TRANSCONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */ |
2543 | #define TRANSCONF_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */ |
2544 | #define TRANSCONF_PIPE_LOCKED REG_BIT(25) |
2545 | #define TRANSCONF_FORCE_BORDER REG_BIT(25) |
2546 | #define TRANSCONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */ |
2547 | #define TRANSCONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */ |
2548 | #define TRANSCONF_GAMMA_MODE_8BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 0) |
2549 | #define TRANSCONF_GAMMA_MODE_10BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 1) |
2550 | #define TRANSCONF_GAMMA_MODE_12BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */ |
2551 | #define TRANSCONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */ |
2552 | #define TRANSCONF_GAMMA_MODE(x) REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */ |
2553 | #define TRANSCONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */ |
2554 | #define TRANSCONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 0) |
2555 | #define TRANSCONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 4) /* gen4 only */ |
2556 | #define TRANSCONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 5) /* gen4 only */ |
2557 | #define TRANSCONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 6) |
2558 | #define TRANSCONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 7) /* gen3 only */ |
2559 | /* |
2560 | * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display, |
2561 | * DBL=power saving pixel doubling, PF-ID* requires panel fitter |
2562 | */ |
2563 | #define TRANSCONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */ |
2564 | #define TRANSCONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */ |
2565 | #define TRANSCONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 0) |
2566 | #define TRANSCONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 1) |
2567 | #define TRANSCONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 3) |
2568 | #define TRANSCONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */ |
2569 | #define TRANSCONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */ |
2570 | #define TRANSCONF_REFRESH_RATE_ALT_ILK REG_BIT(20) |
2571 | #define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */ |
2572 | #define TRANSCONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x)) |
2573 | #define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16) |
2574 | #define TRANSCONF_WGC_ENABLE REG_BIT(15) /* vlv/chv only */ |
2575 | #define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14) |
2576 | #define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13) |
2577 | #define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */ |
2578 | #define TRANSCONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */ |
2579 | #define TRANSCONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */ |
2580 | #define TRANSCONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */ |
2581 | #define TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */ |
2582 | #define TRANSCONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */ |
2583 | #define TRANSCONF_BPC_8 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 0) |
2584 | #define TRANSCONF_BPC_10 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 1) |
2585 | #define TRANSCONF_BPC_6 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 2) |
2586 | #define TRANSCONF_BPC_12 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 3) |
2587 | #define TRANSCONF_DITHER_EN REG_BIT(4) |
2588 | #define TRANSCONF_DITHER_TYPE_MASK REG_GENMASK(3, 2) |
2589 | #define TRANSCONF_DITHER_TYPE_SP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 0) |
2590 | #define TRANSCONF_DITHER_TYPE_ST1 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 1) |
2591 | #define TRANSCONF_DITHER_TYPE_ST2 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 2) |
2592 | #define TRANSCONF_DITHER_TYPE_TEMP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3) |
2593 | #define _PIPEASTAT 0x70024 |
2594 | #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31) |
2595 | #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30) |
2596 | #define PIPE_CRC_ERROR_ENABLE (1UL << 29) |
2597 | #define PIPE_CRC_DONE_ENABLE (1UL << 28) |
2598 | #define PERF_COUNTER2_INTERRUPT_EN (1UL << 27) |
2599 | #define PIPE_GMBUS_EVENT_ENABLE (1UL << 27) |
2600 | #define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26) |
2601 | #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) |
2602 | #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) |
2603 | #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) |
2604 | #define PIPE_DPST_EVENT_ENABLE (1UL << 23) |
2605 | #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) |
2606 | #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) |
2607 | #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) |
2608 | #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20) |
2609 | #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19) |
2610 | #define PERF_COUNTER_INTERRUPT_EN (1UL << 19) |
2611 | #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */ |
2612 | #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */ |
2613 | #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17) |
2614 | #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17) |
2615 | #define PIPEA_HBLANK_INT_EN_VLV (1UL << 16) |
2616 | #define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16) |
2617 | #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15) |
2618 | #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14) |
2619 | #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13) |
2620 | #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12) |
2621 | #define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11) |
2622 | #define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11) |
2623 | #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10) |
2624 | #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) |
2625 | #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) |
2626 | #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) |
2627 | #define PIPE_DPST_EVENT_STATUS (1UL << 7) |
2628 | #define PIPE_A_PSR_STATUS_VLV (1UL << 6) |
2629 | #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) |
2630 | #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) |
2631 | #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4) |
2632 | #define PIPE_B_PSR_STATUS_VLV (1UL << 3) |
2633 | #define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3) |
2634 | #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */ |
2635 | #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */ |
2636 | #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1) |
2637 | #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1) |
2638 | #define PIPE_HBLANK_INT_STATUS (1UL << 0) |
2639 | #define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0) |
2640 | |
2641 | #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 |
2642 | #define PIPESTAT_INT_STATUS_MASK 0x0000ffff |
2643 | |
2644 | #define TRANSCONF(trans) _MMIO_PIPE2((trans), _TRANSACONF) |
2645 | #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL) |
2646 | #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH) |
2647 | #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL) |
2648 | #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT) |
2649 | |
2650 | #define _PIPEAGCMAX 0x70010 |
2651 | #define _PIPEBGCMAX 0x71010 |
2652 | #define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */ |
2653 | |
2654 | #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */ |
2655 | #define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(pipe, _PIPE_ARB_CTL_A) |
2656 | #define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13) |
2657 | |
2658 | #define _PIPE_MISC_A 0x70030 |
2659 | #define _PIPE_MISC_B 0x71030 |
2660 | #define PIPE_MISC_YUV420_ENABLE REG_BIT(27) /* glk+ */ |
2661 | #define PIPE_MISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */ |
2662 | #define PIPE_MISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */ |
2663 | #define PIPE_MISC_PSR_MASK_PRIMARY_FLIP REG_BIT(23) /* bdw */ |
2664 | #define PIPE_MISC_PSR_MASK_SPRITE_ENABLE REG_BIT(22) /* bdw */ |
2665 | #define PIPE_MISC_PSR_MASK_PIPE_REG_WRITE REG_BIT(21) /* skl+ */ |
2666 | #define PIPE_MISC_PSR_MASK_CURSOR_MOVE REG_BIT(21) /* bdw */ |
2667 | #define PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT REG_BIT(20) |
2668 | #define PIPE_MISC_OUTPUT_COLORSPACE_YUV REG_BIT(11) |
2669 | #define PIPE_MISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */ |
2670 | /* |
2671 | * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with |
2672 | * valid values of: 6, 8, 10 BPC. |
2673 | * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of: |
2674 | * 6, 8, 10, 12 BPC. |
2675 | */ |
2676 | #define PIPE_MISC_BPC_MASK REG_GENMASK(7, 5) |
2677 | #define PIPE_MISC_BPC_8 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 0) |
2678 | #define PIPE_MISC_BPC_10 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 1) |
2679 | #define PIPE_MISC_BPC_6 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 2) |
2680 | #define PIPE_MISC_BPC_12_ADLP REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 4) /* adlp+ */ |
2681 | #define PIPE_MISC_DITHER_ENABLE REG_BIT(4) |
2682 | #define PIPE_MISC_DITHER_TYPE_MASK REG_GENMASK(3, 2) |
2683 | #define PIPE_MISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 0) |
2684 | #define PIPE_MISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 1) |
2685 | #define PIPE_MISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 2) |
2686 | #define PIPE_MISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 3) |
2687 | #define PIPE_MISC(pipe) _MMIO_PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B) |
2688 | |
2689 | #define _PIPE_MISC2_A 0x7002C |
2690 | #define _PIPE_MISC2_B 0x7102C |
2691 | #define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24) |
2692 | #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80) |
2693 | #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20) |
2694 | #define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */ |
2695 | #define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id)) |
2696 | #define PIPE_MISC2(pipe) _MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B) |
2697 | |
2698 | #define _ICL_PIPE_A_STATUS 0x70058 |
2699 | #define ICL_PIPESTATUS(pipe) _MMIO_PIPE2(pipe, _ICL_PIPE_A_STATUS) |
2700 | #define PIPE_STATUS_UNDERRUN REG_BIT(31) |
2701 | #define PIPE_STATUS_SOFT_UNDERRUN_XELPD REG_BIT(28) |
2702 | #define PIPE_STATUS_HARD_UNDERRUN_XELPD REG_BIT(27) |
2703 | #define PIPE_STATUS_PORT_UNDERRUN_XELPD REG_BIT(26) |
2704 | |
2705 | #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) |
2706 | #define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29) |
2707 | #define PIPEB_HLINE_INT_EN REG_BIT(28) |
2708 | #define PIPEB_VBLANK_INT_EN REG_BIT(27) |
2709 | #define SPRITED_FLIP_DONE_INT_EN REG_BIT(26) |
2710 | #define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25) |
2711 | #define PLANEB_FLIP_DONE_INT_EN REG_BIT(24) |
2712 | #define PIPE_PSR_INT_EN REG_BIT(22) |
2713 | #define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21) |
2714 | #define PIPEA_HLINE_INT_EN REG_BIT(20) |
2715 | #define PIPEA_VBLANK_INT_EN REG_BIT(19) |
2716 | #define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18) |
2717 | #define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17) |
2718 | #define PLANEA_FLIPDONE_INT_EN REG_BIT(16) |
2719 | #define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13) |
2720 | #define PIPEC_HLINE_INT_EN REG_BIT(12) |
2721 | #define PIPEC_VBLANK_INT_EN REG_BIT(11) |
2722 | #define SPRITEF_FLIPDONE_INT_EN REG_BIT(10) |
2723 | #define SPRITEE_FLIPDONE_INT_EN REG_BIT(9) |
2724 | #define PLANEC_FLIPDONE_INT_EN REG_BIT(8) |
2725 | |
2726 | #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ |
2727 | #define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16) |
2728 | #define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16) |
2729 | #define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27) |
2730 | #define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26) |
2731 | #define PLANEC_INVALID_GTT_INT_EN REG_BIT(25) |
2732 | #define CURSORC_INVALID_GTT_INT_EN REG_BIT(24) |
2733 | #define CURSORB_INVALID_GTT_INT_EN REG_BIT(23) |
2734 | #define CURSORA_INVALID_GTT_INT_EN REG_BIT(22) |
2735 | #define SPRITED_INVALID_GTT_INT_EN REG_BIT(21) |
2736 | #define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20) |
2737 | #define PLANEB_INVALID_GTT_INT_EN REG_BIT(19) |
2738 | #define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18) |
2739 | #define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17) |
2740 | #define PLANEA_INVALID_GTT_INT_EN REG_BIT(16) |
2741 | #define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0) |
2742 | #define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0) |
2743 | #define SPRITEF_INVALID_GTT_STATUS REG_BIT(11) |
2744 | #define SPRITEE_INVALID_GTT_STATUS REG_BIT(10) |
2745 | #define PLANEC_INVALID_GTT_STATUS REG_BIT(9) |
2746 | #define CURSORC_INVALID_GTT_STATUS REG_BIT(8) |
2747 | #define CURSORB_INVALID_GTT_STATUS REG_BIT(7) |
2748 | #define CURSORA_INVALID_GTT_STATUS REG_BIT(6) |
2749 | #define SPRITED_INVALID_GTT_STATUS REG_BIT(5) |
2750 | #define SPRITEC_INVALID_GTT_STATUS REG_BIT(4) |
2751 | #define PLANEB_INVALID_GTT_STATUS REG_BIT(3) |
2752 | #define SPRITEB_INVALID_GTT_STATUS REG_BIT(2) |
2753 | #define SPRITEA_INVALID_GTT_STATUS REG_BIT(1) |
2754 | #define PLANEA_INVALID_GTT_STATUS REG_BIT(0) |
2755 | |
2756 | #define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030) |
2757 | #define DSPARB_CSTART_MASK (0x7f << 7) |
2758 | #define DSPARB_CSTART_SHIFT 7 |
2759 | #define DSPARB_BSTART_MASK (0x7f) |
2760 | #define DSPARB_BSTART_SHIFT 0 |
2761 | #define DSPARB_BEND_SHIFT 9 /* on 855 */ |
2762 | #define DSPARB_AEND_SHIFT 0 |
2763 | #define DSPARB_SPRITEA_SHIFT_VLV 0 |
2764 | #define DSPARB_SPRITEA_MASK_VLV (0xff << 0) |
2765 | #define DSPARB_SPRITEB_SHIFT_VLV 8 |
2766 | #define DSPARB_SPRITEB_MASK_VLV (0xff << 8) |
2767 | #define DSPARB_SPRITEC_SHIFT_VLV 16 |
2768 | #define DSPARB_SPRITEC_MASK_VLV (0xff << 16) |
2769 | #define DSPARB_SPRITED_SHIFT_VLV 24 |
2770 | #define DSPARB_SPRITED_MASK_VLV (0xff << 24) |
2771 | #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */ |
2772 | #define DSPARB_SPRITEA_HI_SHIFT_VLV 0 |
2773 | #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0) |
2774 | #define DSPARB_SPRITEB_HI_SHIFT_VLV 4 |
2775 | #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4) |
2776 | #define DSPARB_SPRITEC_HI_SHIFT_VLV 8 |
2777 | #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8) |
2778 | #define DSPARB_SPRITED_HI_SHIFT_VLV 12 |
2779 | #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12) |
2780 | #define DSPARB_SPRITEE_HI_SHIFT_VLV 16 |
2781 | #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16) |
2782 | #define DSPARB_SPRITEF_HI_SHIFT_VLV 20 |
2783 | #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20) |
2784 | #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */ |
2785 | #define DSPARB_SPRITEE_SHIFT_VLV 0 |
2786 | #define DSPARB_SPRITEE_MASK_VLV (0xff << 0) |
2787 | #define DSPARB_SPRITEF_SHIFT_VLV 8 |
2788 | #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) |
2789 | |
2790 | /* pnv/gen4/g4x/vlv/chv */ |
2791 | #define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034) |
2792 | #define DSPFW_SR_SHIFT 23 |
2793 | #define DSPFW_SR_MASK (0x1ff << 23) |
2794 | #define DSPFW_CURSORB_SHIFT 16 |
2795 | #define DSPFW_CURSORB_MASK (0x3f << 16) |
2796 | #define DSPFW_PLANEB_SHIFT 8 |
2797 | #define DSPFW_PLANEB_MASK (0x7f << 8) |
2798 | #define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */ |
2799 | #define DSPFW_PLANEA_SHIFT 0 |
2800 | #define DSPFW_PLANEA_MASK (0x7f << 0) |
2801 | #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */ |
2802 | #define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038) |
2803 | #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */ |
2804 | #define DSPFW_FBC_SR_SHIFT 28 |
2805 | #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */ |
2806 | #define DSPFW_FBC_HPLL_SR_SHIFT 24 |
2807 | #define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */ |
2808 | #define DSPFW_SPRITEB_SHIFT (16) |
2809 | #define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */ |
2810 | #define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */ |
2811 | #define DSPFW_CURSORA_SHIFT 8 |
2812 | #define DSPFW_CURSORA_MASK (0x3f << 8) |
2813 | #define DSPFW_PLANEC_OLD_SHIFT 0 |
2814 | #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */ |
2815 | #define DSPFW_SPRITEA_SHIFT 0 |
2816 | #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */ |
2817 | #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */ |
2818 | #define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c) |
2819 | #define DSPFW_HPLL_SR_EN (1 << 31) |
2820 | #define PINEVIEW_SELF_REFRESH_EN (1 << 30) |
2821 | #define DSPFW_CURSOR_SR_SHIFT 24 |
2822 | #define DSPFW_CURSOR_SR_MASK (0x3f << 24) |
2823 | #define DSPFW_HPLL_CURSOR_SHIFT 16 |
2824 | #define DSPFW_HPLL_CURSOR_MASK (0x3f << 16) |
2825 | #define DSPFW_HPLL_SR_SHIFT 0 |
2826 | #define DSPFW_HPLL_SR_MASK (0x1ff << 0) |
2827 | |
2828 | /* vlv/chv */ |
2829 | #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070) |
2830 | #define DSPFW_SPRITEB_WM1_SHIFT 16 |
2831 | #define DSPFW_SPRITEB_WM1_MASK (0xff << 16) |
2832 | #define DSPFW_CURSORA_WM1_SHIFT 8 |
2833 | #define DSPFW_CURSORA_WM1_MASK (0x3f << 8) |
2834 | #define DSPFW_SPRITEA_WM1_SHIFT 0 |
2835 | #define DSPFW_SPRITEA_WM1_MASK (0xff << 0) |
2836 | #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074) |
2837 | #define DSPFW_PLANEB_WM1_SHIFT 24 |
2838 | #define DSPFW_PLANEB_WM1_MASK (0xff << 24) |
2839 | #define DSPFW_PLANEA_WM1_SHIFT 16 |
2840 | #define DSPFW_PLANEA_WM1_MASK (0xff << 16) |
2841 | #define DSPFW_CURSORB_WM1_SHIFT 8 |
2842 | #define DSPFW_CURSORB_WM1_MASK (0x3f << 8) |
2843 | #define DSPFW_CURSOR_SR_WM1_SHIFT 0 |
2844 | #define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0) |
2845 | #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078) |
2846 | #define DSPFW_SR_WM1_SHIFT 0 |
2847 | #define DSPFW_SR_WM1_MASK (0x1ff << 0) |
2848 | #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c) |
2849 | #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ |
2850 | #define DSPFW_SPRITED_WM1_SHIFT 24 |
2851 | #define DSPFW_SPRITED_WM1_MASK (0xff << 24) |
2852 | #define DSPFW_SPRITED_SHIFT 16 |
2853 | #define DSPFW_SPRITED_MASK_VLV (0xff << 16) |
2854 | #define DSPFW_SPRITEC_WM1_SHIFT 8 |
2855 | #define DSPFW_SPRITEC_WM1_MASK (0xff << 8) |
2856 | #define DSPFW_SPRITEC_SHIFT 0 |
2857 | #define DSPFW_SPRITEC_MASK_VLV (0xff << 0) |
2858 | #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8) |
2859 | #define DSPFW_SPRITEF_WM1_SHIFT 24 |
2860 | #define DSPFW_SPRITEF_WM1_MASK (0xff << 24) |
2861 | #define DSPFW_SPRITEF_SHIFT 16 |
2862 | #define DSPFW_SPRITEF_MASK_VLV (0xff << 16) |
2863 | #define DSPFW_SPRITEE_WM1_SHIFT 8 |
2864 | #define DSPFW_SPRITEE_WM1_MASK (0xff << 8) |
2865 | #define DSPFW_SPRITEE_SHIFT 0 |
2866 | #define DSPFW_SPRITEE_MASK_VLV (0xff << 0) |
2867 | #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ |
2868 | #define DSPFW_PLANEC_WM1_SHIFT 24 |
2869 | #define DSPFW_PLANEC_WM1_MASK (0xff << 24) |
2870 | #define DSPFW_PLANEC_SHIFT 16 |
2871 | #define DSPFW_PLANEC_MASK_VLV (0xff << 16) |
2872 | #define DSPFW_CURSORC_WM1_SHIFT 8 |
2873 | #define DSPFW_CURSORC_WM1_MASK (0x3f << 16) |
2874 | #define DSPFW_CURSORC_SHIFT 0 |
2875 | #define DSPFW_CURSORC_MASK (0x3f << 0) |
2876 | |
2877 | /* vlv/chv high order bits */ |
2878 | #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064) |
2879 | #define DSPFW_SR_HI_SHIFT 24 |
2880 | #define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ |
2881 | #define DSPFW_SPRITEF_HI_SHIFT 23 |
2882 | #define DSPFW_SPRITEF_HI_MASK (1 << 23) |
2883 | #define DSPFW_SPRITEE_HI_SHIFT 22 |
2884 | #define DSPFW_SPRITEE_HI_MASK (1 << 22) |
2885 | #define DSPFW_PLANEC_HI_SHIFT 21 |
2886 | #define DSPFW_PLANEC_HI_MASK (1 << 21) |
2887 | #define DSPFW_SPRITED_HI_SHIFT 20 |
2888 | #define DSPFW_SPRITED_HI_MASK (1 << 20) |
2889 | #define DSPFW_SPRITEC_HI_SHIFT 16 |
2890 | #define DSPFW_SPRITEC_HI_MASK (1 << 16) |
2891 | #define DSPFW_PLANEB_HI_SHIFT 12 |
2892 | #define DSPFW_PLANEB_HI_MASK (1 << 12) |
2893 | #define DSPFW_SPRITEB_HI_SHIFT 8 |
2894 | #define DSPFW_SPRITEB_HI_MASK (1 << 8) |
2895 | #define DSPFW_SPRITEA_HI_SHIFT 4 |
2896 | #define DSPFW_SPRITEA_HI_MASK (1 << 4) |
2897 | #define DSPFW_PLANEA_HI_SHIFT 0 |
2898 | #define DSPFW_PLANEA_HI_MASK (1 << 0) |
2899 | #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068) |
2900 | #define DSPFW_SR_WM1_HI_SHIFT 24 |
2901 | #define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ |
2902 | #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 |
2903 | #define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23) |
2904 | #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 |
2905 | #define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22) |
2906 | #define DSPFW_PLANEC_WM1_HI_SHIFT 21 |
2907 | #define DSPFW_PLANEC_WM1_HI_MASK (1 << 21) |
2908 | #define DSPFW_SPRITED_WM1_HI_SHIFT 20 |
2909 | #define DSPFW_SPRITED_WM1_HI_MASK (1 << 20) |
2910 | #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 |
2911 | #define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16) |
2912 | #define DSPFW_PLANEB_WM1_HI_SHIFT 12 |
2913 | #define DSPFW_PLANEB_WM1_HI_MASK (1 << 12) |
2914 | #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 |
2915 | #define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8) |
2916 | #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 |
2917 | #define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4) |
2918 | #define DSPFW_PLANEA_WM1_HI_SHIFT 0 |
2919 | #define DSPFW_PLANEA_WM1_HI_MASK (1 << 0) |
2920 | |
2921 | /* drain latency register values*/ |
2922 | #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) |
2923 | #define DDL_CURSOR_SHIFT 24 |
2924 | #define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite)) |
2925 | #define DDL_PLANE_SHIFT 0 |
2926 | #define DDL_PRECISION_HIGH (1 << 7) |
2927 | #define DDL_PRECISION_LOW (0 << 7) |
2928 | #define DRAIN_LATENCY_MASK 0x7f |
2929 | |
2930 | #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400) |
2931 | #define CBR_PND_DEADLINE_DISABLE (1 << 31) |
2932 | #define CBR_PWM_CLOCK_MUX_SELECT (1 << 30) |
2933 | |
2934 | #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450) |
2935 | #define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */ |
2936 | |
2937 | /* FIFO watermark sizes etc */ |
2938 | #define G4X_FIFO_LINE_SIZE 64 |
2939 | #define I915_FIFO_LINE_SIZE 64 |
2940 | #define I830_FIFO_LINE_SIZE 32 |
2941 | |
2942 | #define VALLEYVIEW_FIFO_SIZE 255 |
2943 | #define G4X_FIFO_SIZE 127 |
2944 | #define I965_FIFO_SIZE 512 |
2945 | #define I945_FIFO_SIZE 127 |
2946 | #define I915_FIFO_SIZE 95 |
2947 | #define I855GM_FIFO_SIZE 127 /* In cachelines */ |
2948 | #define I830_FIFO_SIZE 95 |
2949 | |
2950 | #define VALLEYVIEW_MAX_WM 0xff |
2951 | #define G4X_MAX_WM 0x3f |
2952 | #define I915_MAX_WM 0x3f |
2953 | |
2954 | #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ |
2955 | #define PINEVIEW_FIFO_LINE_SIZE 64 |
2956 | #define PINEVIEW_MAX_WM 0x1ff |
2957 | #define PINEVIEW_DFT_WM 0x3f |
2958 | #define PINEVIEW_DFT_HPLLOFF_WM 0 |
2959 | #define PINEVIEW_GUARD_WM 10 |
2960 | #define PINEVIEW_CURSOR_FIFO 64 |
2961 | #define PINEVIEW_CURSOR_MAX_WM 0x3f |
2962 | #define PINEVIEW_CURSOR_DFT_WM 0 |
2963 | #define PINEVIEW_CURSOR_GUARD_WM 5 |
2964 | |
2965 | #define VALLEYVIEW_CURSOR_MAX_WM 64 |
2966 | #define I965_CURSOR_FIFO 64 |
2967 | #define I965_CURSOR_MAX_WM 32 |
2968 | #define I965_CURSOR_DFT_WM 8 |
2969 | |
2970 | /* define the Watermark register on Ironlake */ |
2971 | #define _WM0_PIPEA_ILK 0x45100 |
2972 | #define _WM0_PIPEB_ILK 0x45104 |
2973 | #define _WM0_PIPEC_IVB 0x45200 |
2974 | #define WM0_PIPE_ILK(pipe) _MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \ |
2975 | _WM0_PIPEB_ILK, _WM0_PIPEC_IVB) |
2976 | #define WM0_PIPE_PRIMARY_MASK REG_GENMASK(31, 16) |
2977 | #define WM0_PIPE_SPRITE_MASK REG_GENMASK(15, 8) |
2978 | #define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0) |
2979 | #define WM0_PIPE_PRIMARY(x) REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x)) |
2980 | #define WM0_PIPE_SPRITE(x) REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x)) |
2981 | #define WM0_PIPE_CURSOR(x) REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x)) |
2982 | #define WM1_LP_ILK _MMIO(0x45108) |
2983 | #define WM2_LP_ILK _MMIO(0x4510c) |
2984 | #define WM3_LP_ILK _MMIO(0x45110) |
2985 | #define WM_LP_ENABLE REG_BIT(31) |
2986 | #define WM_LP_LATENCY_MASK REG_GENMASK(30, 24) |
2987 | #define WM_LP_FBC_MASK_BDW REG_GENMASK(23, 19) |
2988 | #define WM_LP_FBC_MASK_ILK REG_GENMASK(23, 20) |
2989 | #define WM_LP_PRIMARY_MASK REG_GENMASK(18, 8) |
2990 | #define WM_LP_CURSOR_MASK REG_GENMASK(7, 0) |
2991 | #define WM_LP_LATENCY(x) REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x)) |
2992 | #define WM_LP_FBC_BDW(x) REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x)) |
2993 | #define WM_LP_FBC_ILK(x) REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x)) |
2994 | #define WM_LP_PRIMARY(x) REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x)) |
2995 | #define WM_LP_CURSOR(x) REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x)) |
2996 | #define WM1S_LP_ILK _MMIO(0x45120) |
2997 | #define WM2S_LP_IVB _MMIO(0x45124) |
2998 | #define WM3S_LP_IVB _MMIO(0x45128) |
2999 | #define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1S only */ |
3000 | #define WM_LP_SPRITE_MASK REG_GENMASK(10, 0) |
3001 | #define WM_LP_SPRITE(x) REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x)) |
3002 | |
3003 | /* |
3004 | * The two pipe frame counter registers are not synchronized, so |
3005 | * reading a stable value is somewhat tricky. The following code |
3006 | * should work: |
3007 | * |
3008 | * do { |
3009 | * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> |
3010 | * PIPE_FRAME_HIGH_SHIFT; |
3011 | * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> |
3012 | * PIPE_FRAME_LOW_SHIFT); |
3013 | * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> |
3014 | * PIPE_FRAME_HIGH_SHIFT); |
3015 | * } while (high1 != high2); |
3016 | * frame = (high1 << 8) | low1; |
3017 | */ |
3018 | #define _PIPEAFRAMEHIGH 0x70040 |
3019 | #define PIPE_FRAME_HIGH_MASK 0x0000ffff |
3020 | #define PIPE_FRAME_HIGH_SHIFT 0 |
3021 | #define _PIPEAFRAMEPIXEL 0x70044 |
3022 | #define PIPE_FRAME_LOW_MASK 0xff000000 |
3023 | #define PIPE_FRAME_LOW_SHIFT 24 |
3024 | #define PIPE_PIXEL_MASK 0x00ffffff |
3025 | #define PIPE_PIXEL_SHIFT 0 |
3026 | /* GM45+ just has to be different */ |
3027 | #define _PIPEA_FRMCOUNT_G4X 0x70040 |
3028 | #define _PIPEA_FLIPCOUNT_G4X 0x70044 |
3029 | #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X) |
3030 | #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X) |
3031 | |
3032 | /* Cursor A & B regs */ |
3033 | #define _CURACNTR 0x70080 |
3034 | /* Old style CUR*CNTR flags (desktop 8xx) */ |
3035 | #define CURSOR_ENABLE REG_BIT(31) |
3036 | #define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30) |
3037 | #define CURSOR_STRIDE_MASK REG_GENMASK(29, 28) |
3038 | #define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */ |
3039 | #define CURSOR_FORMAT_MASK REG_GENMASK(26, 24) |
3040 | #define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0) |
3041 | #define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1) |
3042 | #define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2) |
3043 | #define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4) |
3044 | #define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5) |
3045 | /* New style CUR*CNTR flags */ |
3046 | #define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ |
3047 | #define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */ |
3048 | #define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28) |
3049 | #define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe)) |
3050 | #define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26) |
3051 | #define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ |
3052 | #define MCURSOR_ROTATE_180 REG_BIT(15) |
3053 | #define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14) |
3054 | #define MCURSOR_MODE_MASK 0x27 |
3055 | #define MCURSOR_MODE_DISABLE 0x00 |
3056 | #define MCURSOR_MODE_128_32B_AX 0x02 |
3057 | #define MCURSOR_MODE_256_32B_AX 0x03 |
3058 | #define MCURSOR_MODE_64_32B_AX 0x07 |
3059 | #define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX) |
3060 | #define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX) |
3061 | #define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX) |
3062 | #define _CURABASE 0x70084 |
3063 | #define _CURAPOS 0x70088 |
3064 | #define CURSOR_POS_Y_SIGN REG_BIT(31) |
3065 | #define CURSOR_POS_Y_MASK REG_GENMASK(30, 16) |
3066 | #define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y)) |
3067 | #define CURSOR_POS_X_SIGN REG_BIT(15) |
3068 | #define CURSOR_POS_X_MASK REG_GENMASK(14, 0) |
3069 | #define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x)) |
3070 | #define _CURASIZE 0x700a0 /* 845/865 */ |
3071 | #define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12) |
3072 | #define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h)) |
3073 | #define CURSOR_WIDTH_MASK REG_GENMASK(9, 0) |
3074 | #define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w)) |
3075 | #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ |
3076 | #define CUR_FBC_EN REG_BIT(31) |
3077 | #define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0) |
3078 | #define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h)) |
3079 | #define _CUR_CHICKEN_A 0x700a4 /* mtl+ */ |
3080 | #define _CURASURFLIVE 0x700ac /* g4x+ */ |
3081 | #define _CURBCNTR 0x700c0 |
3082 | #define _CURBBASE 0x700c4 |
3083 | #define _CURBPOS 0x700c8 |
3084 | |
3085 | #define _CURBCNTR_IVB 0x71080 |
3086 | #define _CURBBASE_IVB 0x71084 |
3087 | #define _CURBPOS_IVB 0x71088 |
3088 | |
3089 | #define CURCNTR(pipe) _MMIO_CURSOR2(pipe, _CURACNTR) |
3090 | #define CURBASE(pipe) _MMIO_CURSOR2(pipe, _CURABASE) |
3091 | #define CURPOS(pipe) _MMIO_CURSOR2(pipe, _CURAPOS) |
3092 | #define CURSIZE(pipe) _MMIO_CURSOR2(pipe, _CURASIZE) |
3093 | #define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(pipe, _CUR_FBC_CTL_A) |
3094 | #define CUR_CHICKEN(pipe) _MMIO_CURSOR2(pipe, _CUR_CHICKEN_A) |
3095 | #define CURSURFLIVE(pipe) _MMIO_CURSOR2(pipe, _CURASURFLIVE) |
3096 | |
3097 | /* Display A control */ |
3098 | #define _DSPAADDR_VLV 0x7017C /* vlv/chv */ |
3099 | #define _DSPACNTR 0x70180 |
3100 | #define DISP_ENABLE REG_BIT(31) |
3101 | #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30) |
3102 | #define DISP_FORMAT_MASK REG_GENMASK(29, 26) |
3103 | #define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2) |
3104 | #define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3) |
3105 | #define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4) |
3106 | #define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5) |
3107 | #define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6) |
3108 | #define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7) |
3109 | #define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8) |
3110 | #define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9) |
3111 | #define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10) |
3112 | #define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11) |
3113 | #define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12) |
3114 | #define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14) |
3115 | #define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15) |
3116 | #define DISP_STEREO_ENABLE REG_BIT(25) |
3117 | #define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ |
3118 | #define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24) |
3119 | #define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe)) |
3120 | #define DISP_SRC_KEY_ENABLE REG_BIT(22) |
3121 | #define DISP_LINE_DOUBLE REG_BIT(20) |
3122 | #define DISP_STEREO_POLARITY_SECOND REG_BIT(18) |
3123 | #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */ |
3124 | #define DISP_ROTATE_180 REG_BIT(15) |
3125 | #define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */ |
3126 | #define DISP_TILED REG_BIT(10) |
3127 | #define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */ |
3128 | #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */ |
3129 | #define _DSPAADDR 0x70184 |
3130 | #define _DSPASTRIDE 0x70188 |
3131 | #define _DSPAPOS 0x7018C /* reserved */ |
3132 | #define DISP_POS_Y_MASK REG_GENMASK(31, 16) |
3133 | #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y)) |
3134 | #define DISP_POS_X_MASK REG_GENMASK(15, 0) |
3135 | #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x)) |
3136 | #define _DSPASIZE 0x70190 |
3137 | #define DISP_HEIGHT_MASK REG_GENMASK(31, 16) |
3138 | #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) |
3139 | #define DISP_WIDTH_MASK REG_GENMASK(15, 0) |
3140 | #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w)) |
3141 | #define _DSPASURF 0x7019C /* 965+ only */ |
3142 | #define DISP_ADDR_MASK REG_GENMASK(31, 12) |
3143 | #define _DSPATILEOFF 0x701A4 /* 965+ only */ |
3144 | #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16) |
3145 | #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y)) |
3146 | #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0) |
3147 | #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x)) |
3148 | #define _DSPAOFFSET 0x701A4 /* HSW */ |
3149 | #define _DSPASURFLIVE 0x701AC |
3150 | #define _DSPAGAMC 0x701E0 |
3151 | |
3152 | #define DSPADDR_VLV(plane) _MMIO_PIPE2(plane, _DSPAADDR_VLV) |
3153 | #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) |
3154 | #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR) |
3155 | #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE) |
3156 | #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS) |
3157 | #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE) |
3158 | #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF) |
3159 | #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF) |
3160 | #define DSPLINOFF(plane) DSPADDR(plane) |
3161 | #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET) |
3162 | #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE) |
3163 | #define DSPGAMC(plane, i) _MMIO_PIPE2(plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ |
3164 | |
3165 | /* CHV pipe B blender and primary plane */ |
3166 | #define _CHV_BLEND_A 0x60a00 |
3167 | #define CHV_BLEND_MASK REG_GENMASK(31, 30) |
3168 | #define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0) |
3169 | #define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1) |
3170 | #define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2) |
3171 | #define _CHV_CANVAS_A 0x60a04 |
3172 | #define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20) |
3173 | #define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10) |
3174 | #define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0) |
3175 | #define _PRIMPOS_A 0x60a08 |
3176 | #define PRIM_POS_Y_MASK REG_GENMASK(31, 16) |
3177 | #define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y)) |
3178 | #define PRIM_POS_X_MASK REG_GENMASK(15, 0) |
3179 | #define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x)) |
3180 | #define _PRIMSIZE_A 0x60a0c |
3181 | #define PRIM_HEIGHT_MASK REG_GENMASK(31, 16) |
3182 | #define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h)) |
3183 | #define PRIM_WIDTH_MASK REG_GENMASK(15, 0) |
3184 | #define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w)) |
3185 | #define _PRIMCNSTALPHA_A 0x60a10 |
3186 | #define PRIM_CONST_ALPHA_ENABLE REG_BIT(31) |
3187 | #define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0) |
3188 | #define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha)) |
3189 | |
3190 | #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A) |
3191 | #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A) |
3192 | #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A) |
3193 | #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A) |
3194 | #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A) |
3195 | |
3196 | /* Display/Sprite base address macros */ |
3197 | #define DISP_BASEADDR_MASK (0xfffff000) |
3198 | #define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK) |
3199 | #define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK) |
3200 | |
3201 | /* |
3202 | * VBIOS flags |
3203 | * gen2: |
3204 | * [00:06] alm,mgm |
3205 | * [10:16] all |
3206 | * [30:32] alm,mgm |
3207 | * gen3+: |
3208 | * [00:0f] all |
3209 | * [10:1f] all |
3210 | * [30:32] all |
3211 | */ |
3212 | #define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) |
3213 | #define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) |
3214 | #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) |
3215 | #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) |
3216 | |
3217 | /* Pipe B */ |
3218 | #define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000) |
3219 | #define _TRANSBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008) |
3220 | #define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024) |
3221 | #define _PIPEBFRAMEHIGH 0x71040 |
3222 | #define _PIPEBFRAMEPIXEL 0x71044 |
3223 | #define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040) |
3224 | #define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044) |
3225 | |
3226 | |
3227 | /* Display B control */ |
3228 | #define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180) |
3229 | #define DISP_ALPHA_TRANS_ENABLE REG_BIT(15) |
3230 | #define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0) |
3231 | #define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184) |
3232 | #define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188) |
3233 | #define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C) |
3234 | #define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190) |
3235 | #define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C) |
3236 | #define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) |
3237 | #define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) |
3238 | #define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC) |
3239 | |
3240 | /* ICL DSI 0 and 1 */ |
3241 | #define _PIPEDSI0CONF 0x7b008 |
3242 | #define _PIPEDSI1CONF 0x7b808 |
3243 | |
3244 | /* Sprite A control */ |
3245 | #define _DVSACNTR 0x72180 |
3246 | #define DVS_ENABLE REG_BIT(31) |
3247 | #define DVS_PIPE_GAMMA_ENABLE REG_BIT(30) |
3248 | #define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27) |
3249 | #define DVS_FORMAT_MASK REG_GENMASK(26, 25) |
3250 | #define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0) |
3251 | #define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1) |
3252 | #define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2) |
3253 | #define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3) |
3254 | #define DVS_PIPE_CSC_ENABLE REG_BIT(24) |
3255 | #define DVS_SOURCE_KEY REG_BIT(22) |
3256 | #define DVS_RGB_ORDER_XBGR REG_BIT(20) |
3257 | #define DVS_YUV_FORMAT_BT709 REG_BIT(18) |
3258 | #define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16) |
3259 | #define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0) |
3260 | #define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1) |
3261 | #define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2) |
3262 | #define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3) |
3263 | #define DVS_ROTATE_180 REG_BIT(15) |
3264 | #define DVS_TRICKLE_FEED_DISABLE REG_BIT(14) |
3265 | #define DVS_TILED REG_BIT(10) |
3266 | #define DVS_DEST_KEY REG_BIT(2) |
3267 | #define _DVSALINOFF 0x72184 |
3268 | #define _DVSASTRIDE 0x72188 |
3269 | #define _DVSAPOS 0x7218c |
3270 | #define DVS_POS_Y_MASK REG_GENMASK(31, 16) |
3271 | #define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y)) |
3272 | #define DVS_POS_X_MASK REG_GENMASK(15, 0) |
3273 | #define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x)) |
3274 | #define _DVSASIZE 0x72190 |
3275 | #define DVS_HEIGHT_MASK REG_GENMASK(31, 16) |
3276 | #define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h)) |
3277 | #define DVS_WIDTH_MASK REG_GENMASK(15, 0) |
3278 | #define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w)) |
3279 | #define _DVSAKEYVAL 0x72194 |
3280 | #define _DVSAKEYMSK 0x72198 |
3281 | #define _DVSASURF 0x7219c |
3282 | #define DVS_ADDR_MASK REG_GENMASK(31, 12) |
3283 | #define _DVSAKEYMAXVAL 0x721a0 |
3284 | #define _DVSATILEOFF 0x721a4 |
3285 | #define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16) |
3286 | #define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y)) |
3287 | #define DVS_OFFSET_X_MASK REG_GENMASK(15, 0) |
3288 | #define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x)) |
3289 | #define _DVSASURFLIVE 0x721ac |
3290 | #define _DVSAGAMC_G4X 0x721e0 /* g4x */ |
3291 | #define _DVSASCALE 0x72204 |
3292 | #define DVS_SCALE_ENABLE REG_BIT(31) |
3293 | #define DVS_FILTER_MASK REG_GENMASK(30, 29) |
3294 | #define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0) |
3295 | #define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1) |
3296 | #define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2) |
3297 | #define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */ |
3298 | #define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27) |
3299 | #define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16) |
3300 | #define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w)) |
3301 | #define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0) |
3302 | #define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h)) |
3303 | #define _DVSAGAMC_ILK 0x72300 /* ilk/snb */ |
3304 | #define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */ |
3305 | |
3306 | #define _DVSBCNTR 0x73180 |
3307 | #define _DVSBLINOFF 0x73184 |
3308 | #define _DVSBSTRIDE 0x73188 |
3309 | #define _DVSBPOS 0x7318c |
3310 | #define _DVSBSIZE 0x73190 |
3311 | #define _DVSBKEYVAL 0x73194 |
3312 | #define _DVSBKEYMSK 0x73198 |
3313 | #define _DVSBSURF 0x7319c |
3314 | #define _DVSBKEYMAXVAL 0x731a0 |
3315 | #define _DVSBTILEOFF 0x731a4 |
3316 | #define _DVSBSURFLIVE 0x731ac |
3317 | #define _DVSBGAMC_G4X 0x731e0 /* g4x */ |
3318 | #define _DVSBSCALE 0x73204 |
3319 | #define _DVSBGAMC_ILK 0x73300 /* ilk/snb */ |
3320 | #define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */ |
3321 | |
3322 | #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) |
3323 | #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) |
3324 | #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) |
3325 | #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) |
3326 | #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) |
3327 | #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) |
3328 | #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) |
3329 | #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) |
3330 | #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) |
3331 | #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) |
3332 | #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) |
3333 | #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) |
3334 | #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */ |
3335 | #define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */ |
3336 | #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */ |
3337 | |
3338 | #define _SPRA_CTL 0x70280 |
3339 | #define SPRITE_ENABLE REG_BIT(31) |
3340 | #define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30) |
3341 | #define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) |
3342 | #define SPRITE_FORMAT_MASK REG_GENMASK(27, 25) |
3343 | #define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0) |
3344 | #define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1) |
3345 | #define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2) |
3346 | #define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3) |
3347 | #define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4) |
3348 | #define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */ |
3349 | #define SPRITE_PIPE_CSC_ENABLE REG_BIT(24) |
3350 | #define SPRITE_SOURCE_KEY REG_BIT(22) |
3351 | #define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */ |
3352 | #define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19) |
3353 | #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */ |
3354 | #define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16) |
3355 | #define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0) |
3356 | #define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1) |
3357 | #define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2) |
3358 | #define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3) |
3359 | #define SPRITE_ROTATE_180 REG_BIT(15) |
3360 | #define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14) |
3361 | #define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13) |
3362 | #define SPRITE_TILED REG_BIT(10) |
3363 | #define SPRITE_DEST_KEY REG_BIT(2) |
3364 | #define _SPRA_LINOFF 0x70284 |
3365 | #define _SPRA_STRIDE 0x70288 |
3366 | #define _SPRA_POS 0x7028c |
3367 | #define SPRITE_POS_Y_MASK REG_GENMASK(31, 16) |
3368 | #define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y)) |
3369 | #define SPRITE_POS_X_MASK REG_GENMASK(15, 0) |
3370 | #define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x)) |
3371 | #define _SPRA_SIZE 0x70290 |
3372 | #define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16) |
3373 | #define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h)) |
3374 | #define SPRITE_WIDTH_MASK REG_GENMASK(15, 0) |
3375 | #define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w)) |
3376 | #define _SPRA_KEYVAL 0x70294 |
3377 | #define _SPRA_KEYMSK 0x70298 |
3378 | #define _SPRA_SURF 0x7029c |
3379 | #define SPRITE_ADDR_MASK REG_GENMASK(31, 12) |
3380 | #define _SPRA_KEYMAX 0x702a0 |
3381 | #define _SPRA_TILEOFF 0x702a4 |
3382 | #define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16) |
3383 | #define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y)) |
3384 | #define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0) |
3385 | #define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x)) |
3386 | #define _SPRA_OFFSET 0x702a4 |
3387 | #define _SPRA_SURFLIVE 0x702ac |
3388 | #define _SPRA_SCALE 0x70304 |
3389 | #define SPRITE_SCALE_ENABLE REG_BIT(31) |
3390 | #define SPRITE_FILTER_MASK REG_GENMASK(30, 29) |
3391 | #define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0) |
3392 | #define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1) |
3393 | #define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2) |
3394 | #define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */ |
3395 | #define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27) |
3396 | #define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16) |
3397 | #define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w)) |
3398 | #define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0) |
3399 | #define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h)) |
3400 | #define _SPRA_GAMC 0x70400 |
3401 | #define _SPRA_GAMC16 0x70440 |
3402 | #define _SPRA_GAMC17 0x7044c |
3403 | |
3404 | #define _SPRB_CTL 0x71280 |
3405 | #define _SPRB_LINOFF 0x71284 |
3406 | #define _SPRB_STRIDE 0x71288 |
3407 | #define _SPRB_POS 0x7128c |
3408 | #define _SPRB_SIZE 0x71290 |
3409 | #define _SPRB_KEYVAL 0x71294 |
3410 | #define _SPRB_KEYMSK 0x71298 |
3411 | #define _SPRB_SURF 0x7129c |
3412 | #define _SPRB_KEYMAX 0x712a0 |
3413 | #define _SPRB_TILEOFF 0x712a4 |
3414 | #define _SPRB_OFFSET 0x712a4 |
3415 | #define _SPRB_SURFLIVE 0x712ac |
3416 | #define _SPRB_SCALE 0x71304 |
3417 | #define _SPRB_GAMC 0x71400 |
3418 | #define _SPRB_GAMC16 0x71440 |
3419 | #define _SPRB_GAMC17 0x7144c |
3420 | |
3421 | #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) |
3422 | #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) |
3423 | #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) |
3424 | #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS) |
3425 | #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) |
3426 | #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) |
3427 | #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) |
3428 | #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF) |
3429 | #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) |
3430 | #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) |
3431 | #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) |
3432 | #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) |
3433 | #define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */ |
3434 | #define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */ |
3435 | #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */ |
3436 | #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) |
3437 | |
3438 | #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) |
3439 | #define SP_ENABLE REG_BIT(31) |
3440 | #define SP_PIPE_GAMMA_ENABLE REG_BIT(30) |
3441 | #define SP_FORMAT_MASK REG_GENMASK(29, 26) |
3442 | #define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0) |
3443 | #define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2) |
3444 | #define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5) |
3445 | #define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6) |
3446 | #define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7) |
3447 | #define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8) |
3448 | #define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9) |
3449 | #define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */ |
3450 | #define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */ |
3451 | #define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14) |
3452 | #define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15) |
3453 | #define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */ |
3454 | #define SP_SOURCE_KEY REG_BIT(22) |
3455 | #define SP_YUV_FORMAT_BT709 REG_BIT(18) |
3456 | #define SP_YUV_ORDER_MASK REG_GENMASK(17, 16) |
3457 | #define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0) |
3458 | #define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1) |
3459 | #define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2) |
3460 | #define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3) |
3461 | #define SP_ROTATE_180 REG_BIT(15) |
3462 | #define SP_TILED REG_BIT(10) |
3463 | #define SP_MIRROR REG_BIT(8) /* CHV pipe B */ |
3464 | #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) |
3465 | #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) |
3466 | #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) |
3467 | #define SP_POS_Y_MASK REG_GENMASK(31, 16) |
3468 | #define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y)) |
3469 | #define SP_POS_X_MASK REG_GENMASK(15, 0) |
3470 | #define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x)) |
3471 | #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) |
3472 | #define SP_HEIGHT_MASK REG_GENMASK(31, 16) |
3473 | #define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h)) |
3474 | #define SP_WIDTH_MASK REG_GENMASK(15, 0) |
3475 | #define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w)) |
3476 | #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) |
3477 | #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) |
3478 | #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) |
3479 | #define SP_ADDR_MASK REG_GENMASK(31, 12) |
3480 | #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) |
3481 | #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) |
3482 | #define SP_OFFSET_Y_MASK REG_GENMASK(31, 16) |
3483 | #define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y)) |
3484 | #define SP_OFFSET_X_MASK REG_GENMASK(15, 0) |
3485 | #define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x)) |
3486 | #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) |
3487 | #define SP_CONST_ALPHA_ENABLE REG_BIT(31) |
3488 | #define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0) |
3489 | #define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha)) |
3490 | #define _SPASURFLIVE (VLV_DISPLAY_BASE + 0x721ac) |
3491 | #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0) |
3492 | #define SP_CONTRAST_MASK REG_GENMASK(26, 18) |
3493 | #define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */ |
3494 | #define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0) |
3495 | #define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */ |
3496 | #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4) |
3497 | #define SP_SH_SIN_MASK REG_GENMASK(26, 16) |
3498 | #define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */ |
3499 | #define SP_SH_COS_MASK REG_GENMASK(9, 0) |
3500 | #define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */ |
3501 | #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0) |
3502 | |
3503 | #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) |
3504 | #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) |
3505 | #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) |
3506 | #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) |
3507 | #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) |
3508 | #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) |
3509 | #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) |
3510 | #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) |
3511 | #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) |
3512 | #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) |
3513 | #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) |
3514 | #define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac) |
3515 | #define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0) |
3516 | #define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4) |
3517 | #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0) |
3518 | |
3519 | #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \ |
3520 | _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b)) |
3521 | #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ |
3522 | _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b))) |
3523 | |
3524 | #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR) |
3525 | #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF) |
3526 | #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE) |
3527 | #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS) |
3528 | #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE) |
3529 | #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL) |
3530 | #define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK) |
3531 | #define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF) |
3532 | #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL) |
3533 | #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF) |
3534 | #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA) |
3535 | #define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE) |
3536 | #define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0) |
3537 | #define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1) |
3538 | #define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */ |
3539 | |
3540 | /* |
3541 | * CHV pipe B sprite CSC |
3542 | * |
3543 | * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| |
3544 | * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| |
3545 | * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| |
3546 | */ |
3547 | #define _MMIO_CHV_SPCSC(plane_id, reg) \ |
3548 | _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg)) |
3549 | |
3550 | #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900) |
3551 | #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904) |
3552 | #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908) |
3553 | #define SPCSC_OOFF_MASK REG_GENMASK(26, 16) |
3554 | #define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */ |
3555 | #define SPCSC_IOFF_MASK REG_GENMASK(10, 0) |
3556 | #define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */ |
3557 | |
3558 | #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c) |
3559 | #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910) |
3560 | #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914) |
3561 | #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918) |
3562 | #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c) |
3563 | #define SPCSC_C1_MASK REG_GENMASK(30, 16) |
3564 | #define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */ |
3565 | #define SPCSC_C0_MASK REG_GENMASK(14, 0) |
3566 | #define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */ |
3567 | |
3568 | #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920) |
3569 | #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924) |
3570 | #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928) |
3571 | #define SPCSC_IMAX_MASK REG_GENMASK(26, 16) |
3572 | #define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */ |
3573 | #define SPCSC_IMIN_MASK REG_GENMASK(10, 0) |
3574 | #define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */ |
3575 | |
3576 | #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c) |
3577 | #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930) |
3578 | #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934) |
3579 | #define SPCSC_OMAX_MASK REG_GENMASK(25, 16) |
3580 | #define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */ |
3581 | #define SPCSC_OMIN_MASK REG_GENMASK(9, 0) |
3582 | #define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */ |
3583 | |
3584 | /* Skylake plane registers */ |
3585 | |
3586 | #define _PLANE_CTL_1_A 0x70180 |
3587 | #define _PLANE_CTL_2_A 0x70280 |
3588 | #define _PLANE_CTL_3_A 0x70380 |
3589 | #define PLANE_CTL_ENABLE REG_BIT(31) |
3590 | #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ |
3591 | #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ |
3592 | #define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */ |
3593 | #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) |
3594 | /* |
3595 | * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition |
3596 | * expanded to include bit 23 as well. However, the shift-24 based values |
3597 | * correctly map to the same formats in ICL, as long as bit 23 is set to 0 |
3598 | */ |
3599 | #define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */ |
3600 | #define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */ |
3601 | #define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0) |
3602 | #define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1) |
3603 | #define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2) |
3604 | #define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3) |
3605 | #define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4) |
3606 | #define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5) |
3607 | #define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6) |
3608 | #define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7) |
3609 | #define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8) |
3610 | #define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12) |
3611 | #define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14) |
3612 | #define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1) |
3613 | #define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3) |
3614 | #define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5) |
3615 | #define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7) |
3616 | #define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9) |
3617 | #define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11) |
3618 | #define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */ |
3619 | #define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21) |
3620 | #define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1) |
3621 | #define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2) |
3622 | #define PLANE_CTL_ORDER_RGBX REG_BIT(20) |
3623 | #define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19) |
3624 | #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) |
3625 | #define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16) |
3626 | #define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0) |
3627 | #define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1) |
3628 | #define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2) |
3629 | #define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3) |
3630 | #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15) |
3631 | #define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14) |
3632 | #define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */ |
3633 | #define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */ |
3634 | #define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10) |
3635 | #define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0) |
3636 | #define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1) |
3637 | #define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4) |
3638 | #define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) |
3639 | #define PLANE_CTL_TILED_4 REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) |
3640 | #define PLANE_CTL_ASYNC_FLIP REG_BIT(9) |
3641 | #define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8) |
3642 | #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */ |
3643 | #define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */ |
3644 | #define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0) |
3645 | #define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2) |
3646 | #define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3) |
3647 | #define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0) |
3648 | #define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0) |
3649 | #define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1) |
3650 | #define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2) |
3651 | #define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3) |
3652 | #define _PLANE_STRIDE_1_A 0x70188 |
3653 | #define _PLANE_STRIDE_2_A 0x70288 |
3654 | #define _PLANE_STRIDE_3_A 0x70388 |
3655 | #define PLANE_STRIDE__MASK REG_GENMASK(11, 0) |
3656 | #define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride)) |
3657 | #define _PLANE_POS_1_A 0x7018c |
3658 | #define _PLANE_POS_2_A 0x7028c |
3659 | #define _PLANE_POS_3_A 0x7038c |
3660 | #define PLANE_POS_Y_MASK REG_GENMASK(31, 16) |
3661 | #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y)) |
3662 | #define PLANE_POS_X_MASK REG_GENMASK(15, 0) |
3663 | #define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x)) |
3664 | #define _PLANE_SIZE_1_A 0x70190 |
3665 | #define _PLANE_SIZE_2_A 0x70290 |
3666 | #define _PLANE_SIZE_3_A 0x70390 |
3667 | #define PLANE_HEIGHT_MASK REG_GENMASK(31, 16) |
3668 | #define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h)) |
3669 | #define PLANE_WIDTH_MASK REG_GENMASK(15, 0) |
3670 | #define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w)) |
3671 | #define _PLANE_SURF_1_A 0x7019c |
3672 | #define _PLANE_SURF_2_A 0x7029c |
3673 | #define _PLANE_SURF_3_A 0x7039c |
3674 | #define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12) |
3675 | #define PLANE_SURF_DECRYPT REG_BIT(2) |
3676 | #define _PLANE_OFFSET_1_A 0x701a4 |
3677 | #define _PLANE_OFFSET_2_A 0x702a4 |
3678 | #define _PLANE_OFFSET_3_A 0x703a4 |
3679 | #define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16) |
3680 | #define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y)) |
3681 | #define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0) |
3682 | #define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x)) |
3683 | #define _PLANE_KEYVAL_1_A 0x70194 |
3684 | #define _PLANE_KEYVAL_2_A 0x70294 |
3685 | #define _PLANE_KEYMSK_1_A 0x70198 |
3686 | #define _PLANE_KEYMSK_2_A 0x70298 |
3687 | #define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31) |
3688 | #define _PLANE_KEYMAX_1_A 0x701a0 |
3689 | #define _PLANE_KEYMAX_2_A 0x702a0 |
3690 | #define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24) |
3691 | #define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a)) |
3692 | #define _PLANE_SURFLIVE_1_A 0x701ac |
3693 | #define _PLANE_SURFLIVE_2_A 0x702ac |
3694 | #define _PLANE_CC_VAL_1_A 0x701b4 |
3695 | #define _PLANE_CC_VAL_2_A 0x702b4 |
3696 | #define _PLANE_AUX_DIST_1_A 0x701c0 |
3697 | #define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12) |
3698 | #define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0) |
3699 | #define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride)) |
3700 | #define _PLANE_AUX_DIST_2_A 0x702c0 |
3701 | #define _PLANE_AUX_OFFSET_1_A 0x701c4 |
3702 | #define _PLANE_AUX_OFFSET_2_A 0x702c4 |
3703 | #define _PLANE_CUS_CTL_1_A 0x701c8 |
3704 | #define _PLANE_CUS_CTL_2_A 0x702c8 |
3705 | #define PLANE_CUS_ENABLE REG_BIT(31) |
3706 | #define PLANE_CUS_Y_PLANE_MASK REG_BIT(30) |
3707 | #define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) |
3708 | #define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) |
3709 | #define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) |
3710 | #define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) |
3711 | #define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19) |
3712 | #define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16) |
3713 | #define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0) |
3714 | #define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1) |
3715 | #define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2) |
3716 | #define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15) |
3717 | #define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12) |
3718 | #define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0) |
3719 | #define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1) |
3720 | #define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2) |
3721 | #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ |
3722 | #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ |
3723 | #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ |
3724 | #define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */ |
3725 | #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) |
3726 | #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */ |
3727 | #define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */ |
3728 | #define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */ |
3729 | #define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17) |
3730 | #define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0) |
3731 | #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1) |
3732 | #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2) |
3733 | #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3) |
3734 | #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4) |
3735 | #define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13) |
3736 | #define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4) |
3737 | #define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0) |
3738 | #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2) |
3739 | #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3) |
3740 | #define _PLANE_CHICKEN_1_A 0x7026C /* tgl+ */ |
3741 | #define _PLANE_CHICKEN_2_A 0x7036C /* tgl+ */ |
3742 | #define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */ |
3743 | #define _PLANE_BUF_CFG_1_A 0x7027c |
3744 | #define _PLANE_BUF_CFG_2_A 0x7037c |
3745 | /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */ |
3746 | #define PLANE_BUF_END_MASK REG_GENMASK(27, 16) |
3747 | #define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end)) |
3748 | #define PLANE_BUF_START_MASK REG_GENMASK(11, 0) |
3749 | #define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start)) |
3750 | #define _PLANE_NV12_BUF_CFG_1_A 0x70278 |
3751 | #define _PLANE_NV12_BUF_CFG_2_A 0x70378 |
3752 | |
3753 | #define _PLANE_CC_VAL_1_B 0x711b4 |
3754 | #define _PLANE_CC_VAL_2_B 0x712b4 |
3755 | #define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4) |
3756 | #define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4) |
3757 | #define PLANE_CC_VAL(pipe, plane, dw) \ |
3758 | _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw))) |
3759 | |
3760 | /* Input CSC Register Definitions */ |
3761 | #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0 |
3762 | #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0 |
3763 | |
3764 | #define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0 |
3765 | #define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0 |
3766 | |
3767 | #define _PLANE_INPUT_CSC_RY_GY_1(pipe) \ |
3768 | _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \ |
3769 | _PLANE_INPUT_CSC_RY_GY_1_B) |
3770 | #define _PLANE_INPUT_CSC_RY_GY_2(pipe) \ |
3771 | _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ |
3772 | _PLANE_INPUT_CSC_RY_GY_2_B) |
3773 | |
3774 | #define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \ |
3775 | _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \ |
3776 | _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) |
3777 | |
3778 | #define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8 |
3779 | #define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8 |
3780 | |
3781 | #define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8 |
3782 | #define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8 |
3783 | |
3784 | #define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \ |
3785 | _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \ |
3786 | _PLANE_INPUT_CSC_PREOFF_HI_1_B) |
3787 | #define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \ |
3788 | _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \ |
3789 | _PLANE_INPUT_CSC_PREOFF_HI_2_B) |
3790 | #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \ |
3791 | _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \ |
3792 | _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) |
3793 | |
3794 | #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204 |
3795 | #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304 |
3796 | |
3797 | #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204 |
3798 | #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304 |
3799 | |
3800 | #define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \ |
3801 | _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \ |
3802 | _PLANE_INPUT_CSC_POSTOFF_HI_1_B) |
3803 | #define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \ |
3804 | _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \ |
3805 | _PLANE_INPUT_CSC_POSTOFF_HI_2_B) |
3806 | #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \ |
3807 | _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \ |
3808 | _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) |
3809 | |
3810 | #define _PLANE_CTL_1_B 0x71180 |
3811 | #define _PLANE_CTL_2_B 0x71280 |
3812 | #define _PLANE_CTL_3_B 0x71380 |
3813 | #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) |
3814 | #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) |
3815 | #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) |
3816 | #define PLANE_CTL(pipe, plane) \ |
3817 | _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) |
3818 | |
3819 | #define _PLANE_STRIDE_1_B 0x71188 |
3820 | #define _PLANE_STRIDE_2_B 0x71288 |
3821 | #define _PLANE_STRIDE_3_B 0x71388 |
3822 | #define _PLANE_STRIDE_1(pipe) \ |
3823 | _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) |
3824 | #define _PLANE_STRIDE_2(pipe) \ |
3825 | _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) |
3826 | #define _PLANE_STRIDE_3(pipe) \ |
3827 | _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) |
3828 | #define PLANE_STRIDE(pipe, plane) \ |
3829 | _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) |
3830 | |
3831 | #define _PLANE_POS_1_B 0x7118c |
3832 | #define _PLANE_POS_2_B 0x7128c |
3833 | #define _PLANE_POS_3_B 0x7138c |
3834 | #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) |
3835 | #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) |
3836 | #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) |
3837 | #define PLANE_POS(pipe, plane) \ |
3838 | _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) |
3839 | |
3840 | #define _PLANE_SIZE_1_B 0x71190 |
3841 | #define _PLANE_SIZE_2_B 0x71290 |
3842 | #define _PLANE_SIZE_3_B 0x71390 |
3843 | #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) |
3844 | #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) |
3845 | #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) |
3846 | #define PLANE_SIZE(pipe, plane) \ |
3847 | _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) |
3848 | |
3849 | #define _PLANE_SURF_1_B 0x7119c |
3850 | #define _PLANE_SURF_2_B 0x7129c |
3851 | #define _PLANE_SURF_3_B 0x7139c |
3852 | #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) |
3853 | #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) |
3854 | #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) |
3855 | #define PLANE_SURF(pipe, plane) \ |
3856 | _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) |
3857 | |
3858 | #define _PLANE_OFFSET_1_B 0x711a4 |
3859 | #define _PLANE_OFFSET_2_B 0x712a4 |
3860 | #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) |
3861 | #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) |
3862 | #define PLANE_OFFSET(pipe, plane) \ |
3863 | _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) |
3864 | |
3865 | #define _PLANE_KEYVAL_1_B 0x71194 |
3866 | #define _PLANE_KEYVAL_2_B 0x71294 |
3867 | #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) |
3868 | #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) |
3869 | #define PLANE_KEYVAL(pipe, plane) \ |
3870 | _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) |
3871 | |
3872 | #define _PLANE_KEYMSK_1_B 0x71198 |
3873 | #define _PLANE_KEYMSK_2_B 0x71298 |
3874 | #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) |
3875 | #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) |
3876 | #define PLANE_KEYMSK(pipe, plane) \ |
3877 | _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) |
3878 | |
3879 | #define _PLANE_KEYMAX_1_B 0x711a0 |
3880 | #define _PLANE_KEYMAX_2_B 0x712a0 |
3881 | #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) |
3882 | #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) |
3883 | #define PLANE_KEYMAX(pipe, plane) \ |
3884 | _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) |
3885 | |
3886 | #define _PLANE_SURFLIVE_1_B 0x711ac |
3887 | #define _PLANE_SURFLIVE_2_B 0x712ac |
3888 | #define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B) |
3889 | #define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B) |
3890 | #define PLANE_SURFLIVE(pipe, plane) \ |
3891 | _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe)) |
3892 | |
3893 | #define _PLANE_CHICKEN_1_B 0x7126c |
3894 | #define _PLANE_CHICKEN_2_B 0x7136c |
3895 | #define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B) |
3896 | #define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B) |
3897 | #define PLANE_CHICKEN(pipe, plane) \ |
3898 | _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe)) |
3899 | |
3900 | #define _PLANE_AUX_DIST_1_B 0x711c0 |
3901 | #define _PLANE_AUX_DIST_2_B 0x712c0 |
3902 | #define _PLANE_AUX_DIST_1(pipe) \ |
3903 | _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B) |
3904 | #define _PLANE_AUX_DIST_2(pipe) \ |
3905 | _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) |
3906 | #define PLANE_AUX_DIST(pipe, plane) \ |
3907 | _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe)) |
3908 | |
3909 | #define _PLANE_AUX_OFFSET_1_B 0x711c4 |
3910 | #define _PLANE_AUX_OFFSET_2_B 0x712c4 |
3911 | #define _PLANE_AUX_OFFSET_1(pipe) \ |
3912 | _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B) |
3913 | #define _PLANE_AUX_OFFSET_2(pipe) \ |
3914 | _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) |
3915 | #define PLANE_AUX_OFFSET(pipe, plane) \ |
3916 | _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) |
3917 | |
3918 | #define _PLANE_CUS_CTL_1_B 0x711c8 |
3919 | #define _PLANE_CUS_CTL_2_B 0x712c8 |
3920 | #define _PLANE_CUS_CTL_1(pipe) \ |
3921 | _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B) |
3922 | #define _PLANE_CUS_CTL_2(pipe) \ |
3923 | _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) |
3924 | #define PLANE_CUS_CTL(pipe, plane) \ |
3925 | _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe)) |
3926 | |
3927 | #define _PLANE_COLOR_CTL_1_B 0x711CC |
3928 | #define _PLANE_COLOR_CTL_2_B 0x712CC |
3929 | #define _PLANE_COLOR_CTL_3_B 0x713CC |
3930 | #define _PLANE_COLOR_CTL_1(pipe) \ |
3931 | _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B) |
3932 | #define _PLANE_COLOR_CTL_2(pipe) \ |
3933 | _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B) |
3934 | #define PLANE_COLOR_CTL(pipe, plane) \ |
3935 | _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) |
3936 | |
3937 | /* VBIOS regs */ |
3938 | #define VGACNTRL _MMIO(0x71400) |
3939 | # define VGA_DISP_DISABLE (1 << 31) |
3940 | # define VGA_2X_MODE (1 << 30) |
3941 | # define VGA_PIPE_B_SELECT (1 << 29) |
3942 | |
3943 | #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) |
3944 | |
3945 | /* Ironlake */ |
3946 | |
3947 | #define CPU_VGACNTRL _MMIO(0x41000) |
3948 | |
3949 | #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) |
3950 | #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) |
3951 | #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ |
3952 | #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */ |
3953 | #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */ |
3954 | #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */ |
3955 | #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */ |
3956 | #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0) |
3957 | #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0) |
3958 | #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0) |
3959 | #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0) |
3960 | |
3961 | /* refresh rate hardware control */ |
3962 | #define RR_HW_CTL _MMIO(0x45300) |
3963 | #define RR_HW_LOW_POWER_FRAMES_MASK 0xff |
3964 | #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 |
3965 | |
3966 | #define PCH_3DCGDIS0 _MMIO(0x46020) |
3967 | # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) |
3968 | # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) |
3969 | |
3970 | #define PCH_3DCGDIS1 _MMIO(0x46024) |
3971 | # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) |
3972 | |
3973 | #define _PIPEA_DATA_M1 0x60030 |
3974 | #define _PIPEA_DATA_N1 0x60034 |
3975 | #define _PIPEA_DATA_M2 0x60038 |
3976 | #define _PIPEA_DATA_N2 0x6003c |
3977 | #define _PIPEA_LINK_M1 0x60040 |
3978 | #define _PIPEA_LINK_N1 0x60044 |
3979 | #define _PIPEA_LINK_M2 0x60048 |
3980 | #define _PIPEA_LINK_N2 0x6004c |
3981 | |
3982 | /* PIPEB timing regs are same start from 0x61000 */ |
3983 | |
3984 | #define _PIPEB_DATA_M1 0x61030 |
3985 | #define _PIPEB_DATA_N1 0x61034 |
3986 | #define _PIPEB_DATA_M2 0x61038 |
3987 | #define _PIPEB_DATA_N2 0x6103c |
3988 | #define _PIPEB_LINK_M1 0x61040 |
3989 | #define _PIPEB_LINK_N1 0x61044 |
3990 | #define _PIPEB_LINK_M2 0x61048 |
3991 | #define _PIPEB_LINK_N2 0x6104c |
3992 | |
3993 | #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1) |
3994 | #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1) |
3995 | #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2) |
3996 | #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2) |
3997 | #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1) |
3998 | #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1) |
3999 | #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2) |
4000 | #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2) |
4001 | |
4002 | /* CPU panel fitter */ |
4003 | /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ |
4004 | #define _PFA_CTL_1 0x68080 |
4005 | #define _PFB_CTL_1 0x68880 |
4006 | #define PF_ENABLE REG_BIT(31) |
4007 | #define PF_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29) /* ivb/hsw */ |
4008 | #define PF_PIPE_SEL_IVB(pipe) REG_FIELD_PREP(PF_PIPE_SEL_MASK_IVB, (pipe)) |
4009 | #define PF_FILTER_MASK REG_GENMASK(24, 23) |
4010 | #define PF_FILTER_PROGRAMMED REG_FIELD_PREP(PF_FILTER_MASK, 0) |
4011 | #define PF_FILTER_MED_3x3 REG_FIELD_PREP(PF_FILTER_MASK, 1) |
4012 | #define PF_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 2) |
4013 | #define PF_FILTER_EDGE_SOFTEN REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3) |
4014 | #define _PFA_WIN_SZ 0x68074 |
4015 | #define _PFB_WIN_SZ 0x68874 |
4016 | #define PF_WIN_XSIZE_MASK REG_GENMASK(31, 16) |
4017 | #define PF_WIN_XSIZE(w) REG_FIELD_PREP(PF_WIN_XSIZE_MASK, (w)) |
4018 | #define PF_WIN_YSIZE_MASK REG_GENMASK(15, 0) |
4019 | #define PF_WIN_YSIZE(h) REG_FIELD_PREP(PF_WIN_YSIZE_MASK, (h)) |
4020 | #define _PFA_WIN_POS 0x68070 |
4021 | #define _PFB_WIN_POS 0x68870 |
4022 | #define PF_WIN_XPOS_MASK REG_GENMASK(31, 16) |
4023 | #define PF_WIN_XPOS(x) REG_FIELD_PREP(PF_WIN_XPOS_MASK, (x)) |
4024 | #define PF_WIN_YPOS_MASK REG_GENMASK(15, 0) |
4025 | #define PF_WIN_YPOS(y) REG_FIELD_PREP(PF_WIN_YPOS_MASK, (y)) |
4026 | #define _PFA_VSCALE 0x68084 |
4027 | #define _PFB_VSCALE 0x68884 |
4028 | #define _PFA_HSCALE 0x68090 |
4029 | #define _PFB_HSCALE 0x68890 |
4030 | |
4031 | #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) |
4032 | #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) |
4033 | #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) |
4034 | #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) |
4035 | #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) |
4036 | |
4037 | /* |
4038 | * Skylake scalers |
4039 | */ |
4040 | #define _PS_1A_CTRL 0x68180 |
4041 | #define _PS_2A_CTRL 0x68280 |
4042 | #define _PS_1B_CTRL 0x68980 |
4043 | #define _PS_2B_CTRL 0x68A80 |
4044 | #define _PS_1C_CTRL 0x69180 |
4045 | #define PS_SCALER_EN REG_BIT(31) |
4046 | #define PS_SCALER_TYPE_MASK REG_BIT(30) /* icl+ */ |
4047 | #define PS_SCALER_TYPE_NON_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0) |
4048 | #define PS_SCALER_TYPE_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 1) |
4049 | #define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29, 28) /* skl/bxt */ |
4050 | #define SKL_PS_SCALER_MODE_DYN REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0) |
4051 | #define SKL_PS_SCALER_MODE_HQ REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1) |
4052 | #define SKL_PS_SCALER_MODE_NV12 REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 2) |
4053 | #define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */ |
4054 | #define PS_SCALER_MODE_NORMAL REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0) |
4055 | #define PS_SCALER_MODE_PLANAR REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1) |
4056 | #define PS_ADAPTIVE_FILTERING_EN REG_BIT(28) /* icl+ */ |
4057 | #define PS_BINDING_MASK REG_GENMASK(27, 25) |
4058 | #define PS_BINDING_PIPE REG_FIELD_PREP(PS_BINDING_MASK, 0) |
4059 | #define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1) |
4060 | #define PS_FILTER_MASK REG_GENMASK(24, 23) |
4061 | #define PS_FILTER_MEDIUM REG_FIELD_PREP(PS_FILTER_MASK, 0) |
4062 | #define PS_FILTER_PROGRAMMED REG_FIELD_PREP(PS_FILTER_MASK, 1) |
4063 | #define PS_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_FILTER_MASK, 2) |
4064 | #define PS_FILTER_BILINEAR REG_FIELD_PREP(PS_FILTER_MASK, 3) |
4065 | #define PS_ADAPTIVE_FILTER_MASK REG_BIT(22) /* icl+ */ |
4066 | #define PS_ADAPTIVE_FILTER_MEDIUM REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0) |
4067 | #define PS_ADAPTIVE_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 1) |
4068 | #define PS_PIPE_SCALER_LOC_MASK REG_BIT(21) /* icl+ */ |
4069 | #define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */ |
4070 | #define PS_PIPE_SCALER_LOC_AFTER_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */ |
4071 | #define PS_VERT3TAP REG_BIT(21) /* skl/bxt */ |
4072 | #define PS_VERT_INT_INVERT_FIELD REG_BIT(20) |
4073 | #define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */ |
4074 | #define PS_PWRUP_PROGRESS REG_BIT(17) |
4075 | #define PS_V_FILTER_BYPASS REG_BIT(8) |
4076 | #define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */ |
4077 | #define PS_VADAPT_MODE_MASK REG_GENMASK(6, 5) /* skl/bxt */ |
4078 | #define PS_VADAPT_MODE_LEAST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 0) |
4079 | #define PS_VADAPT_MODE_MOD_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 1) |
4080 | #define PS_VADAPT_MODE_MOST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 3) |
4081 | #define PS_BINDING_Y_MASK REG_GENMASK(7, 5) /* icl-tgl */ |
4082 | #define PS_BINDING_Y_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_Y_MASK, (plane_id) + 1) |
4083 | #define PS_Y_VERT_FILTER_SELECT_MASK REG_BIT(4) /* glk+ */ |
4084 | #define PS_Y_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_VERT_FILTER_SELECT_MASK, (set)) |
4085 | #define PS_Y_HORZ_FILTER_SELECT_MASK REG_BIT(3) /* glk+ */ |
4086 | #define PS_Y_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_HORZ_FILTER_SELECT_MASK, (set)) |
4087 | #define PS_UV_VERT_FILTER_SELECT_MASK REG_BIT(2) /* glk+ */ |
4088 | #define PS_UV_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_VERT_FILTER_SELECT_MASK, (set)) |
4089 | #define PS_UV_HORZ_FILTER_SELECT_MASK REG_BIT(1) /* glk+ */ |
4090 | #define PS_UV_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_HORZ_FILTER_SELECT_MASK, (set)) |
4091 | |
4092 | #define _PS_PWR_GATE_1A 0x68160 |
4093 | #define _PS_PWR_GATE_2A 0x68260 |
4094 | #define _PS_PWR_GATE_1B 0x68960 |
4095 | #define _PS_PWR_GATE_2B 0x68A60 |
4096 | #define _PS_PWR_GATE_1C 0x69160 |
4097 | #define PS_PWR_GATE_DIS_OVERRIDE REG_BIT(31) |
4098 | #define PS_PWR_GATE_SETTLING_TIME_MASK REG_GENMASK(4, 3) |
4099 | #define PS_PWR_GATE_SETTLING_TIME_32 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 0) |
4100 | #define PS_PWR_GATE_SETTLING_TIME_64 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 1) |
4101 | #define PS_PWR_GATE_SETTLING_TIME_96 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 2) |
4102 | #define PS_PWR_GATE_SETTLING_TIME_128 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 3) |
4103 | #define PS_PWR_GATE_SLPEN_MASK REG_GENMASK(1, 0) |
4104 | #define PS_PWR_GATE_SLPEN_8 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 0) |
4105 | #define PS_PWR_GATE_SLPEN_16 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 1) |
4106 | #define PS_PWR_GATE_SLPEN_24 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 2) |
4107 | #define PS_PWR_GATE_SLPEN_32 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 3) |
4108 | |
4109 | #define _PS_WIN_POS_1A 0x68170 |
4110 | #define _PS_WIN_POS_2A 0x68270 |
4111 | #define _PS_WIN_POS_1B 0x68970 |
4112 | #define _PS_WIN_POS_2B 0x68A70 |
4113 | #define _PS_WIN_POS_1C 0x69170 |
4114 | #define PS_WIN_XPOS_MASK REG_GENMASK(31, 16) |
4115 | #define PS_WIN_XPOS(x) REG_FIELD_PREP(PS_WIN_XPOS_MASK, (x)) |
4116 | #define PS_WIN_YPOS_MASK REG_GENMASK(15, 0) |
4117 | #define PS_WIN_YPOS(y) REG_FIELD_PREP(PS_WIN_YPOS_MASK, (y)) |
4118 | |
4119 | #define _PS_WIN_SZ_1A 0x68174 |
4120 | #define _PS_WIN_SZ_2A 0x68274 |
4121 | #define _PS_WIN_SZ_1B 0x68974 |
4122 | #define _PS_WIN_SZ_2B 0x68A74 |
4123 | #define _PS_WIN_SZ_1C 0x69174 |
4124 | #define PS_WIN_XSIZE_MASK REG_GENMASK(31, 16) |
4125 | #define PS_WIN_XSIZE(w) REG_FIELD_PREP(PS_WIN_XSIZE_MASK, (w)) |
4126 | #define PS_WIN_YSIZE_MASK REG_GENMASK(15, 0) |
4127 | #define PS_WIN_YSIZE(h) REG_FIELD_PREP(PS_WIN_YSIZE_MASK, (h)) |
4128 | |
4129 | #define _PS_VSCALE_1A 0x68184 |
4130 | #define _PS_VSCALE_2A 0x68284 |
4131 | #define _PS_VSCALE_1B 0x68984 |
4132 | #define _PS_VSCALE_2B 0x68A84 |
4133 | #define _PS_VSCALE_1C 0x69184 |
4134 | |
4135 | #define _PS_HSCALE_1A 0x68190 |
4136 | #define _PS_HSCALE_2A 0x68290 |
4137 | #define _PS_HSCALE_1B 0x68990 |
4138 | #define _PS_HSCALE_2B 0x68A90 |
4139 | #define _PS_HSCALE_1C 0x69190 |
4140 | |
4141 | #define _PS_VPHASE_1A 0x68188 |
4142 | #define _PS_VPHASE_2A 0x68288 |
4143 | #define _PS_VPHASE_1B 0x68988 |
4144 | #define _PS_VPHASE_2B 0x68A88 |
4145 | #define _PS_VPHASE_1C 0x69188 |
4146 | #define PS_Y_PHASE_MASK REG_GENMASK(31, 16) |
4147 | #define PS_Y_PHASE(x) REG_FIELD_PREP(PS_Y_PHASE_MASK, (x)) |
4148 | #define PS_UV_RGB_PHASE_MASK REG_GENMASK(15, 0) |
4149 | #define PS_UV_RGB_PHASE(x) REG_FIELD_PREP(PS_UV_RGB_PHASE_MASK, (x)) |
4150 | #define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */ |
4151 | #define PS_PHASE_TRIP (1 << 0) |
4152 | |
4153 | #define _PS_HPHASE_1A 0x68194 |
4154 | #define _PS_HPHASE_2A 0x68294 |
4155 | #define _PS_HPHASE_1B 0x68994 |
4156 | #define _PS_HPHASE_2B 0x68A94 |
4157 | #define _PS_HPHASE_1C 0x69194 |
4158 | |
4159 | #define _PS_ECC_STAT_1A 0x681D0 |
4160 | #define _PS_ECC_STAT_2A 0x682D0 |
4161 | #define _PS_ECC_STAT_1B 0x689D0 |
4162 | #define _PS_ECC_STAT_2B 0x68AD0 |
4163 | #define _PS_ECC_STAT_1C 0x691D0 |
4164 | |
4165 | #define _PS_COEF_SET0_INDEX_1A 0x68198 |
4166 | #define _PS_COEF_SET0_INDEX_2A 0x68298 |
4167 | #define _PS_COEF_SET0_INDEX_1B 0x68998 |
4168 | #define _PS_COEF_SET0_INDEX_2B 0x68A98 |
4169 | #define PS_COEF_INDEX_AUTO_INC REG_BIT(10) |
4170 | |
4171 | #define _PS_COEF_SET0_DATA_1A 0x6819C |
4172 | #define _PS_COEF_SET0_DATA_2A 0x6829C |
4173 | #define _PS_COEF_SET0_DATA_1B 0x6899C |
4174 | #define _PS_COEF_SET0_DATA_2B 0x68A9C |
4175 | |
4176 | #define _ID(id, a, b) _PICK_EVEN(id, a, b) |
4177 | #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \ |
4178 | _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ |
4179 | _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) |
4180 | #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \ |
4181 | _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ |
4182 | _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) |
4183 | #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \ |
4184 | _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ |
4185 | _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) |
4186 | #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \ |
4187 | _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ |
4188 | _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) |
4189 | #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \ |
4190 | _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ |
4191 | _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) |
4192 | #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \ |
4193 | _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ |
4194 | _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) |
4195 | #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \ |
4196 | _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ |
4197 | _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) |
4198 | #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \ |
4199 | _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ |
4200 | _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) |
4201 | #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \ |
4202 | _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ |
4203 | _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)) |
4204 | #define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \ |
4205 | _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \ |
4206 | _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8) |
4207 | |
4208 | #define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \ |
4209 | _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \ |
4210 | _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8) |
4211 | |
4212 | /* Display Internal Timeout Register */ |
4213 | #define RM_TIMEOUT _MMIO(0x42060) |
4214 | #define MMIO_TIMEOUT_US(us) ((us) << 0) |
4215 | |
4216 | /* interrupts */ |
4217 | #define DE_MASTER_IRQ_CONTROL (1 << 31) |
4218 | #define DE_SPRITEB_FLIP_DONE (1 << 29) |
4219 | #define DE_SPRITEA_FLIP_DONE (1 << 28) |
4220 | #define DE_PLANEB_FLIP_DONE (1 << 27) |
4221 | #define DE_PLANEA_FLIP_DONE (1 << 26) |
4222 | #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) |
4223 | #define DE_PCU_EVENT (1 << 25) |
4224 | #define DE_GTT_FAULT (1 << 24) |
4225 | #define DE_POISON (1 << 23) |
4226 | #define DE_PERFORM_COUNTER (1 << 22) |
4227 | #define DE_PCH_EVENT (1 << 21) |
4228 | #define DE_AUX_CHANNEL_A (1 << 20) |
4229 | #define DE_DP_A_HOTPLUG (1 << 19) |
4230 | #define DE_GSE (1 << 18) |
4231 | #define DE_PIPEB_VBLANK (1 << 15) |
4232 | #define DE_PIPEB_EVEN_FIELD (1 << 14) |
4233 | #define DE_PIPEB_ODD_FIELD (1 << 13) |
4234 | #define DE_PIPEB_LINE_COMPARE (1 << 12) |
4235 | #define DE_PIPEB_VSYNC (1 << 11) |
4236 | #define DE_PIPEB_CRC_DONE (1 << 10) |
4237 | #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) |
4238 | #define DE_PIPEA_VBLANK (1 << 7) |
4239 | #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe))) |
4240 | #define DE_PIPEA_EVEN_FIELD (1 << 6) |
4241 | #define DE_PIPEA_ODD_FIELD (1 << 5) |
4242 | #define DE_PIPEA_LINE_COMPARE (1 << 4) |
4243 | #define DE_PIPEA_VSYNC (1 << 3) |
4244 | #define DE_PIPEA_CRC_DONE (1 << 2) |
4245 | #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe))) |
4246 | #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) |
4247 | #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe))) |
4248 | |
4249 | /* More Ivybridge lolz */ |
4250 | #define DE_ERR_INT_IVB (1 << 30) |
4251 | #define DE_GSE_IVB (1 << 29) |
4252 | #define DE_PCH_EVENT_IVB (1 << 28) |
4253 | #define DE_DP_A_HOTPLUG_IVB (1 << 27) |
4254 | #define DE_AUX_CHANNEL_A_IVB (1 << 26) |
4255 | #define DE_EDP_PSR_INT_HSW (1 << 19) |
4256 | #define DE_SPRITEC_FLIP_DONE_IVB (1 << 14) |
4257 | #define DE_PLANEC_FLIP_DONE_IVB (1 << 13) |
4258 | #define DE_PIPEC_VBLANK_IVB (1 << 10) |
4259 | #define DE_SPRITEB_FLIP_DONE_IVB (1 << 9) |
4260 | #define DE_PLANEB_FLIP_DONE_IVB (1 << 8) |
4261 | #define DE_PIPEB_VBLANK_IVB (1 << 5) |
4262 | #define DE_SPRITEA_FLIP_DONE_IVB (1 << 4) |
4263 | #define DE_PLANEA_FLIP_DONE_IVB (1 << 3) |
4264 | #define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane))) |
4265 | #define DE_PIPEA_VBLANK_IVB (1 << 0) |
4266 | #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5)) |
4267 | |
4268 | #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ |
4269 | #define MASTER_INTERRUPT_ENABLE (1 << 31) |
4270 | |
4271 | #define DEISR _MMIO(0x44000) |
4272 | #define DEIMR _MMIO(0x44004) |
4273 | #define DEIIR _MMIO(0x44008) |
4274 | #define DEIER _MMIO(0x4400c) |
4275 | |
4276 | #define GTISR _MMIO(0x44010) |
4277 | #define GTIMR _MMIO(0x44014) |
4278 | #define GTIIR _MMIO(0x44018) |
4279 | #define GTIER _MMIO(0x4401c) |
4280 | |
4281 | #define GEN8_MASTER_IRQ _MMIO(0x44200) |
4282 | #define GEN8_MASTER_IRQ_CONTROL (1 << 31) |
4283 | #define GEN8_PCU_IRQ (1 << 30) |
4284 | #define GEN8_DE_PCH_IRQ (1 << 23) |
4285 | #define GEN8_DE_MISC_IRQ (1 << 22) |
4286 | #define GEN8_DE_PORT_IRQ (1 << 20) |
4287 | #define GEN8_DE_PIPE_C_IRQ (1 << 18) |
4288 | #define GEN8_DE_PIPE_B_IRQ (1 << 17) |
4289 | #define GEN8_DE_PIPE_A_IRQ (1 << 16) |
4290 | #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe))) |
4291 | #define GEN8_GT_VECS_IRQ (1 << 6) |
4292 | #define GEN8_GT_GUC_IRQ (1 << 5) |
4293 | #define GEN8_GT_PM_IRQ (1 << 4) |
4294 | #define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */ |
4295 | #define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */ |
4296 | #define GEN8_GT_BCS_IRQ (1 << 1) |
4297 | #define GEN8_GT_RCS_IRQ (1 << 0) |
4298 | |
4299 | #define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c) |
4300 | |
4301 | #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) |
4302 | #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) |
4303 | #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) |
4304 | #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which))) |
4305 | |
4306 | #define GEN8_RCS_IRQ_SHIFT 0 |
4307 | #define GEN8_BCS_IRQ_SHIFT 16 |
4308 | #define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */ |
4309 | #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */ |
4310 | #define GEN8_VECS_IRQ_SHIFT 0 |
4311 | #define GEN8_WD_IRQ_SHIFT 16 |
4312 | |
4313 | #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe))) |
4314 | #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) |
4315 | #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) |
4316 | #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) |
4317 | #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) |
4318 | #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) |
4319 | #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) |
4320 | #define XELPD_PIPE_SOFT_UNDERRUN (1 << 22) |
4321 | #define XELPD_PIPE_HARD_UNDERRUN (1 << 21) |
4322 | #define GEN12_PIPE_VBLANK_UNMOD (1 << 19) |
4323 | #define GEN8_PIPE_CURSOR_FAULT (1 << 10) |
4324 | #define GEN8_PIPE_SPRITE_FAULT (1 << 9) |
4325 | #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) |
4326 | #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) |
4327 | #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) |
4328 | #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) |
4329 | #define GEN8_PIPE_VSYNC (1 << 1) |
4330 | #define GEN8_PIPE_VBLANK (1 << 0) |
4331 | #define GEN9_PIPE_CURSOR_FAULT (1 << 11) |
4332 | #define GEN11_PIPE_PLANE7_FAULT (1 << 22) |
4333 | #define GEN11_PIPE_PLANE6_FAULT (1 << 21) |
4334 | #define GEN11_PIPE_PLANE5_FAULT (1 << 20) |
4335 | #define GEN9_PIPE_PLANE4_FAULT (1 << 10) |
4336 | #define GEN9_PIPE_PLANE3_FAULT (1 << 9) |
4337 | #define GEN9_PIPE_PLANE2_FAULT (1 << 8) |
4338 | #define GEN9_PIPE_PLANE1_FAULT (1 << 7) |
4339 | #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6) |
4340 | #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) |
4341 | #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) |
4342 | #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) |
4343 | #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p))) |
4344 | #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ |
4345 | (GEN8_PIPE_CURSOR_FAULT | \ |
4346 | GEN8_PIPE_SPRITE_FAULT | \ |
4347 | GEN8_PIPE_PRIMARY_FAULT) |
4348 | #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ |
4349 | (GEN9_PIPE_CURSOR_FAULT | \ |
4350 | GEN9_PIPE_PLANE4_FAULT | \ |
4351 | GEN9_PIPE_PLANE3_FAULT | \ |
4352 | GEN9_PIPE_PLANE2_FAULT | \ |
4353 | GEN9_PIPE_PLANE1_FAULT) |
4354 | #define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \ |
4355 | (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ |
4356 | GEN11_PIPE_PLANE7_FAULT | \ |
4357 | GEN11_PIPE_PLANE6_FAULT | \ |
4358 | GEN11_PIPE_PLANE5_FAULT) |
4359 | #define RKL_DE_PIPE_IRQ_FAULT_ERRORS \ |
4360 | (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ |
4361 | GEN11_PIPE_PLANE5_FAULT) |
4362 | |
4363 | #define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A) |
4364 | #define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1) |
4365 | |
4366 | #define GEN8_DE_PORT_ISR _MMIO(0x44440) |
4367 | #define GEN8_DE_PORT_IMR _MMIO(0x44444) |
4368 | #define GEN8_DE_PORT_IIR _MMIO(0x44448) |
4369 | #define GEN8_DE_PORT_IER _MMIO(0x4444c) |
4370 | #define DSI1_NON_TE (1 << 31) |
4371 | #define DSI0_NON_TE (1 << 30) |
4372 | #define ICL_AUX_CHANNEL_E (1 << 29) |
4373 | #define ICL_AUX_CHANNEL_F (1 << 28) |
4374 | #define GEN9_AUX_CHANNEL_D (1 << 27) |
4375 | #define GEN9_AUX_CHANNEL_C (1 << 26) |
4376 | #define GEN9_AUX_CHANNEL_B (1 << 25) |
4377 | #define DSI1_TE (1 << 24) |
4378 | #define DSI0_TE (1 << 23) |
4379 | #define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin)) |
4380 | #define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \ |
4381 | GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \ |
4382 | GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) |
4383 | #define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) |
4384 | #define BXT_DE_PORT_GMBUS (1 << 1) |
4385 | #define GEN8_AUX_CHANNEL_A (1 << 0) |
4386 | #define TGL_DE_PORT_AUX_USBC6 REG_BIT(13) |
4387 | #define XELPD_DE_PORT_AUX_DDIE REG_BIT(13) |
4388 | #define TGL_DE_PORT_AUX_USBC5 REG_BIT(12) |
4389 | #define XELPD_DE_PORT_AUX_DDID REG_BIT(12) |
4390 | #define TGL_DE_PORT_AUX_USBC4 REG_BIT(11) |
4391 | #define TGL_DE_PORT_AUX_USBC3 REG_BIT(10) |
4392 | #define TGL_DE_PORT_AUX_USBC2 REG_BIT(9) |
4393 | #define TGL_DE_PORT_AUX_USBC1 REG_BIT(8) |
4394 | #define TGL_DE_PORT_AUX_DDIC REG_BIT(2) |
4395 | #define TGL_DE_PORT_AUX_DDIB REG_BIT(1) |
4396 | #define TGL_DE_PORT_AUX_DDIA REG_BIT(0) |
4397 | |
4398 | #define GEN8_DE_MISC_ISR _MMIO(0x44460) |
4399 | #define GEN8_DE_MISC_IMR _MMIO(0x44464) |
4400 | #define GEN8_DE_MISC_IIR _MMIO(0x44468) |
4401 | #define GEN8_DE_MISC_IER _MMIO(0x4446c) |
4402 | #define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27) |
4403 | #define GEN8_DE_MISC_GSE REG_BIT(27) |
4404 | #define GEN8_DE_EDP_PSR REG_BIT(19) |
4405 | #define XELPDP_PMDEMAND_RSP REG_BIT(3) |
4406 | |
4407 | #define GEN8_PCU_ISR _MMIO(0x444e0) |
4408 | #define GEN8_PCU_IMR _MMIO(0x444e4) |
4409 | #define GEN8_PCU_IIR _MMIO(0x444e8) |
4410 | #define GEN8_PCU_IER _MMIO(0x444ec) |
4411 | |
4412 | #define GEN11_GU_MISC_ISR _MMIO(0x444f0) |
4413 | #define GEN11_GU_MISC_IMR _MMIO(0x444f4) |
4414 | #define GEN11_GU_MISC_IIR _MMIO(0x444f8) |
4415 | #define GEN11_GU_MISC_IER _MMIO(0x444fc) |
4416 | #define GEN11_GU_MISC_GSE (1 << 27) |
4417 | |
4418 | #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010) |
4419 | #define GEN11_MASTER_IRQ (1 << 31) |
4420 | #define GEN11_PCU_IRQ (1 << 30) |
4421 | #define GEN11_GU_MISC_IRQ (1 << 29) |
4422 | #define GEN11_DISPLAY_IRQ (1 << 16) |
4423 | #define GEN11_GT_DW_IRQ(x) (1 << (x)) |
4424 | #define GEN11_GT_DW1_IRQ (1 << 1) |
4425 | #define GEN11_GT_DW0_IRQ (1 << 0) |
4426 | |
4427 | #define DG1_MSTR_TILE_INTR _MMIO(0x190008) |
4428 | #define DG1_MSTR_IRQ REG_BIT(31) |
4429 | #define DG1_MSTR_TILE(t) REG_BIT(t) |
4430 | |
4431 | #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200) |
4432 | #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31) |
4433 | #define GEN11_AUDIO_CODEC_IRQ (1 << 24) |
4434 | #define GEN11_DE_PCH_IRQ (1 << 23) |
4435 | #define GEN11_DE_MISC_IRQ (1 << 22) |
4436 | #define GEN11_DE_HPD_IRQ (1 << 21) |
4437 | #define GEN11_DE_PORT_IRQ (1 << 20) |
4438 | #define GEN11_DE_PIPE_C (1 << 18) |
4439 | #define GEN11_DE_PIPE_B (1 << 17) |
4440 | #define GEN11_DE_PIPE_A (1 << 16) |
4441 | |
4442 | #define GEN11_DE_HPD_ISR _MMIO(0x44470) |
4443 | #define GEN11_DE_HPD_IMR _MMIO(0x44474) |
4444 | #define GEN11_DE_HPD_IIR _MMIO(0x44478) |
4445 | #define GEN11_DE_HPD_IER _MMIO(0x4447c) |
4446 | #define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin)) |
4447 | #define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \ |
4448 | GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \ |
4449 | GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \ |
4450 | GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \ |
4451 | GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \ |
4452 | GEN11_TC_HOTPLUG(HPD_PORT_TC1)) |
4453 | #define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin)) |
4454 | #define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \ |
4455 | GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \ |
4456 | GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \ |
4457 | GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \ |
4458 | GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \ |
4459 | GEN11_TBT_HOTPLUG(HPD_PORT_TC1)) |
4460 | |
4461 | #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) |
4462 | #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) |
4463 | #define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) |
4464 | #define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) |
4465 | #define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) |
4466 | #define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4)) |
4467 | |
4468 | #define PICAINTERRUPT_ISR _MMIO(0x16FE50) |
4469 | #define PICAINTERRUPT_IMR _MMIO(0x16FE54) |
4470 | #define PICAINTERRUPT_IIR _MMIO(0x16FE58) |
4471 | #define PICAINTERRUPT_IER _MMIO(0x16FE5C) |
4472 | #define XELPDP_DP_ALT_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin)) |
4473 | #define XELPDP_DP_ALT_HOTPLUG_MASK REG_GENMASK(19, 16) |
4474 | #define XELPDP_AUX_TC(hpd_pin) REG_BIT(8 + _HPD_PIN_TC(hpd_pin)) |
4475 | #define XELPDP_AUX_TC_MASK REG_GENMASK(11, 8) |
4476 | #define XE2LPD_AUX_DDI(hpd_pin) REG_BIT(6 + _HPD_PIN_DDI(hpd_pin)) |
4477 | #define XE2LPD_AUX_DDI_MASK REG_GENMASK(7, 6) |
4478 | #define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin)) |
4479 | #define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0) |
4480 | |
4481 | #define XELPDP_PORT_HOTPLUG_CTL(hpd_pin) _MMIO(0x16F270 + (_HPD_PIN_TC(hpd_pin) * 0x200)) |
4482 | #define XELPDP_TBT_HOTPLUG_ENABLE REG_BIT(6) |
4483 | #define XELPDP_TBT_HPD_LONG_DETECT REG_BIT(5) |
4484 | #define XELPDP_TBT_HPD_SHORT_DETECT REG_BIT(4) |
4485 | #define XELPDP_DP_ALT_HOTPLUG_ENABLE REG_BIT(2) |
4486 | #define XELPDP_DP_ALT_HPD_LONG_DETECT REG_BIT(1) |
4487 | #define XELPDP_DP_ALT_HPD_SHORT_DETECT REG_BIT(0) |
4488 | |
4489 | #define XELPDP_INITIATE_PMDEMAND_REQUEST(dword) _MMIO(0x45230 + 4 * (dword)) |
4490 | #define XELPDP_PMDEMAND_QCLK_GV_BW_MASK REG_GENMASK(31, 16) |
4491 | #define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK REG_GENMASK(14, 12) |
4492 | #define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK REG_GENMASK(11, 8) |
4493 | #define XELPDP_PMDEMAND_PIPES_MASK REG_GENMASK(7, 6) |
4494 | #define XELPDP_PMDEMAND_DBUFS_MASK REG_GENMASK(5, 4) |
4495 | #define XELPDP_PMDEMAND_PHYS_MASK REG_GENMASK(2, 0) |
4496 | |
4497 | #define XELPDP_PMDEMAND_REQ_ENABLE REG_BIT(31) |
4498 | #define XELPDP_PMDEMAND_CDCLK_FREQ_MASK REG_GENMASK(30, 20) |
4499 | #define XELPDP_PMDEMAND_DDICLK_FREQ_MASK REG_GENMASK(18, 8) |
4500 | #define XELPDP_PMDEMAND_SCALERS_MASK REG_GENMASK(6, 4) |
4501 | #define XELPDP_PMDEMAND_PLLS_MASK REG_GENMASK(2, 0) |
4502 | |
4503 | #define GEN12_DCPR_STATUS_1 _MMIO(0x46440) |
4504 | #define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26) |
4505 | |
4506 | #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) |
4507 | /* Required on all Ironlake and Sandybridge according to the B-Spec. */ |
4508 | #define ILK_ELPIN_409_SELECT REG_BIT(25) |
4509 | #define ILK_DPARB_GATE REG_BIT(22) |
4510 | #define ILK_VSDPFD_FULL REG_BIT(21) |
4511 | |
4512 | #define FUSE_STRAP _MMIO(0x42014) |
4513 | #define ILK_INTERNAL_GRAPHICS_DISABLE REG_BIT(31) |
4514 | #define ILK_INTERNAL_DISPLAY_DISABLE REG_BIT(30) |
4515 | #define ILK_DISPLAY_DEBUG_DISABLE REG_BIT(29) |
4516 | #define IVB_PIPE_C_DISABLE REG_BIT(28) |
4517 | #define ILK_HDCP_DISABLE REG_BIT(25) |
4518 | #define ILK_eDP_A_DISABLE REG_BIT(24) |
4519 | #define HSW_CDCLK_LIMIT REG_BIT(24) |
4520 | #define ILK_DESKTOP REG_BIT(23) |
4521 | #define HSW_CPU_SSC_ENABLE REG_BIT(21) |
4522 | |
4523 | #define FUSE_STRAP3 _MMIO(0x42020) |
4524 | #define HSW_REF_CLK_SELECT REG_BIT(1) |
4525 | |
4526 | #define ILK_DSPCLK_GATE_D _MMIO(0x42020) |
4527 | #define ILK_VRHUNIT_CLOCK_GATE_DISABLE REG_BIT(28) |
4528 | #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE REG_BIT(9) |
4529 | #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE REG_BIT(8) |
4530 | #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE REG_BIT(7) |
4531 | #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE REG_BIT(5) |
4532 | |
4533 | #define IVB_CHICKEN3 _MMIO(0x4200c) |
4534 | #define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE REG_BIT(5) |
4535 | #define CHICKEN3_DGMG_DONE_FIX_DISABLE REG_BIT(2) |
4536 | |
4537 | #define CHICKEN_PAR1_1 _MMIO(0x42080) |
4538 | #define IGNORE_KVMR_PIPE_A REG_BIT(23) |
4539 | #define KBL_ARB_FILL_SPARE_22 REG_BIT(22) |
4540 | #define DIS_RAM_BYPASS_PSR2_MAN_TRACK REG_BIT(16) |
4541 | #define SKL_DE_COMPRESSED_HASH_MODE REG_BIT(15) |
4542 | #define HSW_MASK_VBL_TO_PIPE_IN_SRD REG_BIT(15) /* hsw/bdw */ |
4543 | #define FORCE_ARB_IDLE_PLANES REG_BIT(14) |
4544 | #define SKL_EDP_PSR_FIX_RDWRAP REG_BIT(3) |
4545 | #define IGNORE_PSR2_HW_TRACKING REG_BIT(1) |
4546 | |
4547 | #define CHICKEN_PAR2_1 _MMIO(0x42090) |
4548 | #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14) |
4549 | |
4550 | #define CHICKEN_MISC_2 _MMIO(0x42084) |
4551 | #define CHICKEN_MISC_DISABLE_DPT REG_BIT(30) /* adl,dg2 */ |
4552 | #define KBL_ARB_FILL_SPARE_14 REG_BIT(14) |
4553 | #define KBL_ARB_FILL_SPARE_13 REG_BIT(13) |
4554 | #define GLK_CL2_PWR_DOWN REG_BIT(12) |
4555 | #define GLK_CL1_PWR_DOWN REG_BIT(11) |
4556 | #define GLK_CL0_PWR_DOWN REG_BIT(10) |
4557 | |
4558 | #define CHICKEN_MISC_4 _MMIO(0x4208c) |
4559 | #define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13) |
4560 | #define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0) |
4561 | #define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x)) |
4562 | |
4563 | #define _CHICKEN_PIPESL_1_A 0x420b0 |
4564 | #define _CHICKEN_PIPESL_1_B 0x420b4 |
4565 | #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) |
4566 | #define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27) |
4567 | #define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0) |
4568 | #define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1) |
4569 | #define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2) |
4570 | #define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3) |
4571 | #define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25) |
4572 | #define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0) |
4573 | #define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1) |
4574 | #define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2) |
4575 | #define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3) |
4576 | #define HSW_FBCQ_DIS REG_BIT(22) |
4577 | #define HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */ |
4578 | #define SKL_PSR_MASK_PLANE_FLIP REG_BIT(11) /* skl+ */ |
4579 | #define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0) |
4580 | #define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0) |
4581 | #define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1) |
4582 | #define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2) |
4583 | #define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3) |
4584 | #define BDW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(0) /* bdw */ |
4585 | |
4586 | #define _CHICKEN_TRANS_A 0x420c0 |
4587 | #define _CHICKEN_TRANS_B 0x420c4 |
4588 | #define _CHICKEN_TRANS_C 0x420c8 |
4589 | #define _CHICKEN_TRANS_EDP 0x420cc |
4590 | #define _CHICKEN_TRANS_D 0x420d8 |
4591 | #define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \ |
4592 | [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \ |
4593 | [TRANSCODER_A] = _CHICKEN_TRANS_A, \ |
4594 | [TRANSCODER_B] = _CHICKEN_TRANS_B, \ |
4595 | [TRANSCODER_C] = _CHICKEN_TRANS_C, \ |
4596 | [TRANSCODER_D] = _CHICKEN_TRANS_D)) |
4597 | #define _MTL_CHICKEN_TRANS_A 0x604e0 |
4598 | #define _MTL_CHICKEN_TRANS_B 0x614e0 |
4599 | #define MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \ |
4600 | _MTL_CHICKEN_TRANS_A, \ |
4601 | _MTL_CHICKEN_TRANS_B) |
4602 | #define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* ADL/DG2 */ |
4603 | #define SKL_UNMASK_VBL_TO_PIPE_IN_SRD REG_BIT(30) /* skl+ */ |
4604 | #define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) |
4605 | #define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x) |
4606 | #define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */ |
4607 | #define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23) |
4608 | #define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19) |
4609 | #define ADLP_1_BASED_X_GRANULARITY REG_BIT(18) |
4610 | #define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18) |
4611 | #define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */ |
4612 | #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */ |
4613 | #define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15) |
4614 | #define REG_BIT(12) |
4615 | |
4616 | #define DISP_ARB_CTL _MMIO(0x45000) |
4617 | #define DISP_FBC_MEMORY_WAKE REG_BIT(31) |
4618 | #define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13) |
4619 | #define DISP_FBC_WM_DIS REG_BIT(15) |
4620 | |
4621 | #define DISP_ARB_CTL2 _MMIO(0x45004) |
4622 | #define DISP_DATA_PARTITION_5_6 REG_BIT(6) |
4623 | #define DISP_IPC_ENABLE REG_BIT(3) |
4624 | |
4625 | #define GEN7_MSG_CTL _MMIO(0x45010) |
4626 | #define WAIT_FOR_PCH_RESET_ACK (1 << 1) |
4627 | #define WAIT_FOR_PCH_FLR_ACK (1 << 0) |
4628 | |
4629 | #define _BW_BUDDY0_CTL 0x45130 |
4630 | #define _BW_BUDDY1_CTL 0x45140 |
4631 | #define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \ |
4632 | _BW_BUDDY0_CTL, \ |
4633 | _BW_BUDDY1_CTL)) |
4634 | #define BW_BUDDY_DISABLE REG_BIT(31) |
4635 | #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) |
4636 | #define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x) |
4637 | |
4638 | #define _BW_BUDDY0_PAGE_MASK 0x45134 |
4639 | #define _BW_BUDDY1_PAGE_MASK 0x45144 |
4640 | #define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \ |
4641 | _BW_BUDDY0_PAGE_MASK, \ |
4642 | _BW_BUDDY1_PAGE_MASK)) |
4643 | |
4644 | #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) |
4645 | #define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6) |
4646 | #define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4) |
4647 | |
4648 | #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) |
4649 | #define LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31) |
4650 | #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30) |
4651 | #define LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25) |
4652 | #define LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24) |
4653 | #define LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23) |
4654 | #define ICL_DELAY_PMRSP REG_BIT(22) |
4655 | #define DISABLE_FLR_SRC REG_BIT(15) |
4656 | #define MASK_WAKEMEM REG_BIT(13) |
4657 | #define DDI_CLOCK_REG_ACCESS REG_BIT(7) |
4658 | |
4659 | #define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434) |
4660 | #define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27) |
4661 | #define DCPR_MASK_LPMODE REG_BIT(26) |
4662 | #define DCPR_SEND_RESP_IMM REG_BIT(25) |
4663 | #define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24) |
4664 | |
4665 | #define XELPD_CHICKEN_DCPR_3 _MMIO(0x46438) |
4666 | #define DMD_RSP_TIMEOUT_DISABLE REG_BIT(19) |
4667 | |
4668 | #define SKL_DFSM _MMIO(0x51000) |
4669 | #define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27) |
4670 | #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25) |
4671 | #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) |
4672 | #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) |
4673 | #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) |
4674 | #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) |
4675 | #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) |
4676 | #define ICL_DFSM_DMC_DISABLE (1 << 23) |
4677 | #define SKL_DFSM_PIPE_A_DISABLE (1 << 30) |
4678 | #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) |
4679 | #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) |
4680 | #define TGL_DFSM_PIPE_D_DISABLE (1 << 22) |
4681 | #define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7) |
4682 | |
4683 | #define XE2LPD_DE_CAP _MMIO(0x41100) |
4684 | #define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30) |
4685 | #define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28) |
4686 | #define XE2LPD_DE_CAP_DSC_REMOVED 1 |
4687 | #define XE2LPD_DE_CAP_SCALER_MASK REG_GENMASK(27, 26) |
4688 | #define XE2LPD_DE_CAP_SCALER_SINGLE 1 |
4689 | |
4690 | #define SKL_DSSM _MMIO(0x51004) |
4691 | #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) |
4692 | #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) |
4693 | #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) |
4694 | #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29) |
4695 | |
4696 | #define GMD_ID_DISPLAY _MMIO(0x510a0) |
4697 | #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22) |
4698 | #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14) |
4699 | #define GMD_ID_STEP REG_GENMASK(5, 0) |
4700 | |
4701 | /*GEN11 chicken */ |
4702 | #define _PIPEA_CHICKEN 0x70038 |
4703 | #define _PIPEB_CHICKEN 0x71038 |
4704 | #define _PIPEC_CHICKEN 0x72038 |
4705 | #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ |
4706 | _PIPEB_CHICKEN) |
4707 | #define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30) |
4708 | #define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30) |
4709 | #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15) |
4710 | #define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12) |
4711 | #define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7) |
4712 | |
4713 | /* PCH */ |
4714 | |
4715 | #define PCH_DISPLAY_BASE 0xc0000u |
4716 | |
4717 | /* south display engine interrupt: IBX */ |
4718 | #define SDE_AUDIO_POWER_D (1 << 27) |
4719 | #define SDE_AUDIO_POWER_C (1 << 26) |
4720 | #define SDE_AUDIO_POWER_B (1 << 25) |
4721 | #define SDE_AUDIO_POWER_SHIFT (25) |
4722 | #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) |
4723 | #define SDE_GMBUS (1 << 24) |
4724 | #define SDE_AUDIO_HDCP_TRANSB (1 << 23) |
4725 | #define SDE_AUDIO_HDCP_TRANSA (1 << 22) |
4726 | #define SDE_AUDIO_HDCP_MASK (3 << 22) |
4727 | #define SDE_AUDIO_TRANSB (1 << 21) |
4728 | #define SDE_AUDIO_TRANSA (1 << 20) |
4729 | #define SDE_AUDIO_TRANS_MASK (3 << 20) |
4730 | #define SDE_POISON (1 << 19) |
4731 | /* 18 reserved */ |
4732 | #define SDE_FDI_RXB (1 << 17) |
4733 | #define SDE_FDI_RXA (1 << 16) |
4734 | #define SDE_FDI_MASK (3 << 16) |
4735 | #define SDE_AUXD (1 << 15) |
4736 | #define SDE_AUXC (1 << 14) |
4737 | #define SDE_AUXB (1 << 13) |
4738 | #define SDE_AUX_MASK (7 << 13) |
4739 | /* 12 reserved */ |
4740 | #define SDE_CRT_HOTPLUG (1 << 11) |
4741 | #define SDE_PORTD_HOTPLUG (1 << 10) |
4742 | #define SDE_PORTC_HOTPLUG (1 << 9) |
4743 | #define SDE_PORTB_HOTPLUG (1 << 8) |
4744 | #define SDE_SDVOB_HOTPLUG (1 << 6) |
4745 | #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ |
4746 | SDE_SDVOB_HOTPLUG | \ |
4747 | SDE_PORTB_HOTPLUG | \ |
4748 | SDE_PORTC_HOTPLUG | \ |
4749 | SDE_PORTD_HOTPLUG) |
4750 | #define SDE_TRANSB_CRC_DONE (1 << 5) |
4751 | #define SDE_TRANSB_CRC_ERR (1 << 4) |
4752 | #define SDE_TRANSB_FIFO_UNDER (1 << 3) |
4753 | #define SDE_TRANSA_CRC_DONE (1 << 2) |
4754 | #define SDE_TRANSA_CRC_ERR (1 << 1) |
4755 | #define SDE_TRANSA_FIFO_UNDER (1 << 0) |
4756 | #define SDE_TRANS_MASK (0x3f) |
4757 | |
4758 | /* south display engine interrupt: CPT - CNP */ |
4759 | #define SDE_AUDIO_POWER_D_CPT (1 << 31) |
4760 | #define SDE_AUDIO_POWER_C_CPT (1 << 30) |
4761 | #define SDE_AUDIO_POWER_B_CPT (1 << 29) |
4762 | #define SDE_AUDIO_POWER_SHIFT_CPT 29 |
4763 | #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) |
4764 | #define SDE_AUXD_CPT (1 << 27) |
4765 | #define SDE_AUXC_CPT (1 << 26) |
4766 | #define SDE_AUXB_CPT (1 << 25) |
4767 | #define SDE_AUX_MASK_CPT (7 << 25) |
4768 | #define SDE_PORTE_HOTPLUG_SPT (1 << 25) |
4769 | #define SDE_PORTA_HOTPLUG_SPT (1 << 24) |
4770 | #define SDE_PORTD_HOTPLUG_CPT (1 << 23) |
4771 | #define SDE_PORTC_HOTPLUG_CPT (1 << 22) |
4772 | #define SDE_PORTB_HOTPLUG_CPT (1 << 21) |
4773 | #define SDE_CRT_HOTPLUG_CPT (1 << 19) |
4774 | #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) |
4775 | #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ |
4776 | SDE_SDVOB_HOTPLUG_CPT | \ |
4777 | SDE_PORTD_HOTPLUG_CPT | \ |
4778 | SDE_PORTC_HOTPLUG_CPT | \ |
4779 | SDE_PORTB_HOTPLUG_CPT) |
4780 | #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \ |
4781 | SDE_PORTD_HOTPLUG_CPT | \ |
4782 | SDE_PORTC_HOTPLUG_CPT | \ |
4783 | SDE_PORTB_HOTPLUG_CPT | \ |
4784 | SDE_PORTA_HOTPLUG_SPT) |
4785 | #define SDE_GMBUS_CPT (1 << 17) |
4786 | #define SDE_ERROR_CPT (1 << 16) |
4787 | #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) |
4788 | #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) |
4789 | #define SDE_FDI_RXC_CPT (1 << 8) |
4790 | #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) |
4791 | #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) |
4792 | #define SDE_FDI_RXB_CPT (1 << 4) |
4793 | #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) |
4794 | #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) |
4795 | #define SDE_FDI_RXA_CPT (1 << 0) |
4796 | #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ |
4797 | SDE_AUDIO_CP_REQ_B_CPT | \ |
4798 | SDE_AUDIO_CP_REQ_A_CPT) |
4799 | #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ |
4800 | SDE_AUDIO_CP_CHG_B_CPT | \ |
4801 | SDE_AUDIO_CP_CHG_A_CPT) |
4802 | #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ |
4803 | SDE_FDI_RXB_CPT | \ |
4804 | SDE_FDI_RXA_CPT) |
4805 | |
4806 | /* south display engine interrupt: ICP/TGP/MTP */ |
4807 | #define SDE_PICAINTERRUPT REG_BIT(31) |
4808 | #define SDE_GMBUS_ICP (1 << 23) |
4809 | #define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin)) |
4810 | #define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */ |
4811 | #define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin)) |
4812 | #define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \ |
4813 | SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \ |
4814 | SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \ |
4815 | SDE_DDI_HOTPLUG_ICP(HPD_PORT_A)) |
4816 | #define SDE_TC_HOTPLUG_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \ |
4817 | SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \ |
4818 | SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \ |
4819 | SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \ |
4820 | SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \ |
4821 | SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1)) |
4822 | |
4823 | #define SDEISR _MMIO(0xc4000) |
4824 | #define SDEIMR _MMIO(0xc4004) |
4825 | #define SDEIIR _MMIO(0xc4008) |
4826 | #define SDEIER _MMIO(0xc400c) |
4827 | |
4828 | #define SERR_INT _MMIO(0xc4040) |
4829 | #define SERR_INT_POISON (1 << 31) |
4830 | #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) |
4831 | |
4832 | /* digital port hotplug */ |
4833 | #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */ |
4834 | #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */ |
4835 | #define BXT_DDIA_HPD_INVERT (1 << 27) |
4836 | #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */ |
4837 | #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */ |
4838 | #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */ |
4839 | #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */ |
4840 | #define PORTD_HOTPLUG_ENABLE (1 << 20) |
4841 | #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */ |
4842 | #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */ |
4843 | #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */ |
4844 | #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */ |
4845 | #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */ |
4846 | #define PORTD_HOTPLUG_STATUS_MASK (3 << 16) |
4847 | #define PORTD_HOTPLUG_NO_DETECT (0 << 16) |
4848 | #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) |
4849 | #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) |
4850 | #define PORTC_HOTPLUG_ENABLE (1 << 12) |
4851 | #define BXT_DDIC_HPD_INVERT (1 << 11) |
4852 | #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */ |
4853 | #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */ |
4854 | #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */ |
4855 | #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */ |
4856 | #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */ |
4857 | #define PORTC_HOTPLUG_STATUS_MASK (3 << 8) |
4858 | #define PORTC_HOTPLUG_NO_DETECT (0 << 8) |
4859 | #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) |
4860 | #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) |
4861 | #define PORTB_HOTPLUG_ENABLE (1 << 4) |
4862 | #define BXT_DDIB_HPD_INVERT (1 << 3) |
4863 | #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */ |
4864 | #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */ |
4865 | #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */ |
4866 | #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */ |
4867 | #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */ |
4868 | #define PORTB_HOTPLUG_STATUS_MASK (3 << 0) |
4869 | #define PORTB_HOTPLUG_NO_DETECT (0 << 0) |
4870 | #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) |
4871 | #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) |
4872 | #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \ |
4873 | BXT_DDIB_HPD_INVERT | \ |
4874 | BXT_DDIC_HPD_INVERT) |
4875 | |
4876 | #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */ |
4877 | #define PORTE_HOTPLUG_ENABLE (1 << 4) |
4878 | #define PORTE_HOTPLUG_STATUS_MASK (3 << 0) |
4879 | #define PORTE_HOTPLUG_NO_DETECT (0 << 0) |
4880 | #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0) |
4881 | #define PORTE_HOTPLUG_LONG_DETECT (2 << 0) |
4882 | |
4883 | /* This register is a reuse of PCH_PORT_HOTPLUG register. The |
4884 | * functionality covered in PCH_PORT_HOTPLUG is split into |
4885 | * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC. |
4886 | */ |
4887 | |
4888 | #define SHOTPLUG_CTL_DDI _MMIO(0xc4030) |
4889 | #define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4)) |
4890 | #define SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(hpd_pin) (0x4 << (_HPD_PIN_DDI(hpd_pin) * 4)) |
4891 | #define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) |
4892 | #define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4)) |
4893 | #define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4)) |
4894 | #define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4)) |
4895 | #define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) |
4896 | |
4897 | #define SHOTPLUG_CTL_TC _MMIO(0xc4034) |
4898 | #define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) |
4899 | #define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) |
4900 | #define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) |
4901 | |
4902 | #define SHPD_FILTER_CNT _MMIO(0xc4038) |
4903 | #define SHPD_FILTER_CNT_500_ADJ 0x001D9 |
4904 | #define SHPD_FILTER_CNT_250 0x000F8 |
4905 | |
4906 | #define _PCH_DPLL_A 0xc6014 |
4907 | #define _PCH_DPLL_B 0xc6018 |
4908 | #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) |
4909 | |
4910 | #define _PCH_FPA0 0xc6040 |
4911 | #define FP_CB_TUNE (0x3 << 22) |
4912 | #define _PCH_FPA1 0xc6044 |
4913 | #define _PCH_FPB0 0xc6048 |
4914 | #define _PCH_FPB1 0xc604c |
4915 | #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0) |
4916 | #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1) |
4917 | |
4918 | #define PCH_DPLL_TEST _MMIO(0xc606c) |
4919 | |
4920 | #define PCH_DREF_CONTROL _MMIO(0xC6200) |
4921 | #define DREF_CONTROL_MASK 0x7fc3 |
4922 | #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) |
4923 | #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) |
4924 | #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) |
4925 | #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) |
4926 | #define DREF_SSC_SOURCE_DISABLE (0 << 11) |
4927 | #define DREF_SSC_SOURCE_ENABLE (2 << 11) |
4928 | #define DREF_SSC_SOURCE_MASK (3 << 11) |
4929 | #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) |
4930 | #define DREF_NONSPREAD_CK505_ENABLE (1 << 9) |
4931 | #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) |
4932 | #define DREF_NONSPREAD_SOURCE_MASK (3 << 9) |
4933 | #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) |
4934 | #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) |
4935 | #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) |
4936 | #define DREF_SSC4_DOWNSPREAD (0 << 6) |
4937 | #define DREF_SSC4_CENTERSPREAD (1 << 6) |
4938 | #define DREF_SSC1_DISABLE (0 << 1) |
4939 | #define DREF_SSC1_ENABLE (1 << 1) |
4940 | #define DREF_SSC4_DISABLE (0) |
4941 | #define DREF_SSC4_ENABLE (1) |
4942 | |
4943 | #define PCH_RAWCLK_FREQ _MMIO(0xc6204) |
4944 | #define FDL_TP1_TIMER_SHIFT 12 |
4945 | #define FDL_TP1_TIMER_MASK (3 << 12) |
4946 | #define FDL_TP2_TIMER_SHIFT 10 |
4947 | #define FDL_TP2_TIMER_MASK (3 << 10) |
4948 | #define RAWCLK_FREQ_MASK 0x3ff |
4949 | #define CNP_RAWCLK_DIV_MASK (0x3ff << 16) |
4950 | #define CNP_RAWCLK_DIV(div) ((div) << 16) |
4951 | #define CNP_RAWCLK_FRAC_MASK (0xf << 26) |
4952 | #define CNP_RAWCLK_DEN(den) ((den) << 26) |
4953 | #define ICP_RAWCLK_NUM(num) ((num) << 11) |
4954 | |
4955 | #define PCH_DPLL_TMR_CFG _MMIO(0xc6208) |
4956 | |
4957 | #define PCH_SSC4_PARMS _MMIO(0xc6210) |
4958 | #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214) |
4959 | |
4960 | #define PCH_DPLL_SEL _MMIO(0xc7000) |
4961 | #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4)) |
4962 | #define TRANS_DPLLA_SEL(pipe) 0 |
4963 | #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3)) |
4964 | |
4965 | /* transcoder */ |
4966 | |
4967 | #define _PCH_TRANS_HTOTAL_A 0xe0000 |
4968 | #define TRANS_HTOTAL_SHIFT 16 |
4969 | #define TRANS_HACTIVE_SHIFT 0 |
4970 | #define _PCH_TRANS_HBLANK_A 0xe0004 |
4971 | #define TRANS_HBLANK_END_SHIFT 16 |
4972 | #define TRANS_HBLANK_START_SHIFT 0 |
4973 | #define _PCH_TRANS_HSYNC_A 0xe0008 |
4974 | #define TRANS_HSYNC_END_SHIFT 16 |
4975 | #define TRANS_HSYNC_START_SHIFT 0 |
4976 | #define _PCH_TRANS_VTOTAL_A 0xe000c |
4977 | #define TRANS_VTOTAL_SHIFT 16 |
4978 | #define TRANS_VACTIVE_SHIFT 0 |
4979 | #define _PCH_TRANS_VBLANK_A 0xe0010 |
4980 | #define TRANS_VBLANK_END_SHIFT 16 |
4981 | #define TRANS_VBLANK_START_SHIFT 0 |
4982 | #define _PCH_TRANS_VSYNC_A 0xe0014 |
4983 | #define TRANS_VSYNC_END_SHIFT 16 |
4984 | #define TRANS_VSYNC_START_SHIFT 0 |
4985 | #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 |
4986 | |
4987 | #define _PCH_TRANSA_DATA_M1 0xe0030 |
4988 | #define _PCH_TRANSA_DATA_N1 0xe0034 |
4989 | #define _PCH_TRANSA_DATA_M2 0xe0038 |
4990 | #define _PCH_TRANSA_DATA_N2 0xe003c |
4991 | #define _PCH_TRANSA_LINK_M1 0xe0040 |
4992 | #define _PCH_TRANSA_LINK_N1 0xe0044 |
4993 | #define _PCH_TRANSA_LINK_M2 0xe0048 |
4994 | #define _PCH_TRANSA_LINK_N2 0xe004c |
4995 | |
4996 | /* Per-transcoder DIP controls (PCH) */ |
4997 | #define _VIDEO_DIP_CTL_A 0xe0200 |
4998 | #define _VIDEO_DIP_DATA_A 0xe0208 |
4999 | #define _VIDEO_DIP_GCP_A 0xe0210 |
5000 | #define GCP_COLOR_INDICATION (1 << 2) |
5001 | #define GCP_DEFAULT_PHASE_ENABLE (1 << 1) |
5002 | #define GCP_AV_MUTE (1 << 0) |
5003 | |
5004 | #define _VIDEO_DIP_CTL_B 0xe1200 |
5005 | #define _VIDEO_DIP_DATA_B 0xe1208 |
5006 | #define _VIDEO_DIP_GCP_B 0xe1210 |
5007 | |
5008 | #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) |
5009 | #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) |
5010 | #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) |
5011 | |
5012 | /* Per-transcoder DIP controls (VLV) */ |
5013 | #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) |
5014 | #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) |
5015 | #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) |
5016 | |
5017 | #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) |
5018 | #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) |
5019 | #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) |
5020 | |
5021 | #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) |
5022 | #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) |
5023 | #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) |
5024 | |
5025 | #define VLV_TVIDEO_DIP_CTL(pipe) \ |
5026 | _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \ |
5027 | _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C) |
5028 | #define VLV_TVIDEO_DIP_DATA(pipe) \ |
5029 | _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \ |
5030 | _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C) |
5031 | #define VLV_TVIDEO_DIP_GCP(pipe) \ |
5032 | _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ |
5033 | _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C) |
5034 | |
5035 | /* Haswell DIP controls */ |
5036 | |
5037 | #define _HSW_VIDEO_DIP_CTL_A 0x60200 |
5038 | #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220 |
5039 | #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260 |
5040 | #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 |
5041 | #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 |
5042 | #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 |
5043 | #define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440 |
5044 | #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 |
5045 | #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 |
5046 | #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 |
5047 | #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300 |
5048 | #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344 |
5049 | #define _HSW_VIDEO_DIP_GCP_A 0x60210 |
5050 | |
5051 | #define _HSW_VIDEO_DIP_CTL_B 0x61200 |
5052 | #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220 |
5053 | #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260 |
5054 | #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 |
5055 | #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 |
5056 | #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 |
5057 | #define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440 |
5058 | #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 |
5059 | #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 |
5060 | #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 |
5061 | #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300 |
5062 | #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344 |
5063 | #define _HSW_VIDEO_DIP_GCP_B 0x61210 |
5064 | |
5065 | /* Icelake PPS_DATA and _ECC DIP Registers. |
5066 | * These are available for transcoders B,C and eDP. |
5067 | * Adding the _A so as to reuse the _MMIO_TRANS2 |
5068 | * definition, with which it offsets to the right location. |
5069 | */ |
5070 | |
5071 | #define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350 |
5072 | #define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350 |
5073 | #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4 |
5074 | #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4 |
5075 | |
5076 | #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A) |
5077 | #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A) |
5078 | #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) |
5079 | #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) |
5080 | #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) |
5081 | #define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) |
5082 | #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) |
5083 | #define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) |
5084 | #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) |
5085 | #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) |
5086 | |
5087 | #define _HSW_STEREO_3D_CTL_A 0x70020 |
5088 | #define S3D_ENABLE (1 << 31) |
5089 | #define _HSW_STEREO_3D_CTL_B 0x71020 |
5090 | |
5091 | #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A) |
5092 | |
5093 | #define _PCH_TRANS_HTOTAL_B 0xe1000 |
5094 | #define _PCH_TRANS_HBLANK_B 0xe1004 |
5095 | #define _PCH_TRANS_HSYNC_B 0xe1008 |
5096 | #define _PCH_TRANS_VTOTAL_B 0xe100c |
5097 | #define _PCH_TRANS_VBLANK_B 0xe1010 |
5098 | #define _PCH_TRANS_VSYNC_B 0xe1014 |
5099 | #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 |
5100 | |
5101 | #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) |
5102 | #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) |
5103 | #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) |
5104 | #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) |
5105 | #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) |
5106 | #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) |
5107 | #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B) |
5108 | |
5109 | #define _PCH_TRANSB_DATA_M1 0xe1030 |
5110 | #define _PCH_TRANSB_DATA_N1 0xe1034 |
5111 | #define _PCH_TRANSB_DATA_M2 0xe1038 |
5112 | #define _PCH_TRANSB_DATA_N2 0xe103c |
5113 | #define _PCH_TRANSB_LINK_M1 0xe1040 |
5114 | #define _PCH_TRANSB_LINK_N1 0xe1044 |
5115 | #define _PCH_TRANSB_LINK_M2 0xe1048 |
5116 | #define _PCH_TRANSB_LINK_N2 0xe104c |
5117 | |
5118 | #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) |
5119 | #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) |
5120 | #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) |
5121 | #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) |
5122 | #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) |
5123 | #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) |
5124 | #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) |
5125 | #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) |
5126 | |
5127 | #define _PCH_TRANSACONF 0xf0008 |
5128 | #define _PCH_TRANSBCONF 0xf1008 |
5129 | #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) |
5130 | #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */ |
5131 | #define TRANS_ENABLE REG_BIT(31) |
5132 | #define TRANS_STATE_ENABLE REG_BIT(30) |
5133 | #define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */ |
5134 | #define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */ |
5135 | #define TRANS_INTERLACE_MASK REG_GENMASK(23, 21) |
5136 | #define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0) |
5137 | #define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */ |
5138 | #define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3) |
5139 | #define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */ |
5140 | #define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0) |
5141 | #define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1) |
5142 | #define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2) |
5143 | #define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3) |
5144 | |
5145 | #define _TRANSA_CHICKEN1 0xf0060 |
5146 | #define _TRANSB_CHICKEN1 0xf1060 |
5147 | #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) |
5148 | #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10) |
5149 | #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4) |
5150 | |
5151 | #define _TRANSA_CHICKEN2 0xf0064 |
5152 | #define _TRANSB_CHICKEN2 0xf1064 |
5153 | #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) |
5154 | #define TRANS_CHICKEN2_TIMING_OVERRIDE REG_BIT(31) |
5155 | #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED REG_BIT(29) |
5156 | #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) |
5157 | #define TRANS_CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */ |
5158 | #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER REG_BIT(26) |
5159 | #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH REG_BIT(25) |
5160 | |
5161 | #define SOUTH_CHICKEN1 _MMIO(0xc2000) |
5162 | #define FDIA_PHASE_SYNC_SHIFT_OVR 19 |
5163 | #define FDIA_PHASE_SYNC_SHIFT_EN 18 |
5164 | #define INVERT_DDIE_HPD REG_BIT(28) |
5165 | #define INVERT_DDID_HPD_MTP REG_BIT(27) |
5166 | #define INVERT_TC4_HPD REG_BIT(26) |
5167 | #define INVERT_TC3_HPD REG_BIT(25) |
5168 | #define INVERT_TC2_HPD REG_BIT(24) |
5169 | #define INVERT_TC1_HPD REG_BIT(23) |
5170 | #define INVERT_DDID_HPD (1 << 18) |
5171 | #define INVERT_DDIC_HPD (1 << 17) |
5172 | #define INVERT_DDIB_HPD (1 << 16) |
5173 | #define INVERT_DDIA_HPD (1 << 15) |
5174 | #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) |
5175 | #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) |
5176 | #define FDI_BC_BIFURCATION_SELECT (1 << 12) |
5177 | #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8) |
5178 | #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8) |
5179 | #define SBCLK_RUN_REFCLK_DIS (1 << 7) |
5180 | #define ICP_SECOND_PPS_IO_SELECT REG_BIT(2) |
5181 | #define SPT_PWM_GRANULARITY (1 << 0) |
5182 | #define SOUTH_CHICKEN2 _MMIO(0xc2004) |
5183 | #define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13) |
5184 | #define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12) |
5185 | #define LPT_PWM_GRANULARITY (1 << 5) |
5186 | #define DPLS_EDP_PPS_FIX_DIS (1 << 0) |
5187 | |
5188 | #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) |
5189 | #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31) |
5190 | #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30) |
5191 | #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29) |
5192 | #define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15) |
5193 | #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14) |
5194 | #define CNP_PWM_CGE_GATING_DISABLE (1 << 13) |
5195 | #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12) |
5196 | |
5197 | #define _PCH_DP_B 0xe4100 |
5198 | #define PCH_DP_B _MMIO(_PCH_DP_B) |
5199 | #define _PCH_DPB_AUX_CH_CTL 0xe4110 |
5200 | #define _PCH_DPB_AUX_CH_DATA1 0xe4114 |
5201 | #define _PCH_DPB_AUX_CH_DATA2 0xe4118 |
5202 | #define _PCH_DPB_AUX_CH_DATA3 0xe411c |
5203 | #define _PCH_DPB_AUX_CH_DATA4 0xe4120 |
5204 | #define _PCH_DPB_AUX_CH_DATA5 0xe4124 |
5205 | |
5206 | #define _PCH_DP_C 0xe4200 |
5207 | #define PCH_DP_C _MMIO(_PCH_DP_C) |
5208 | #define _PCH_DPC_AUX_CH_CTL 0xe4210 |
5209 | #define _PCH_DPC_AUX_CH_DATA1 0xe4214 |
5210 | #define _PCH_DPC_AUX_CH_DATA2 0xe4218 |
5211 | #define _PCH_DPC_AUX_CH_DATA3 0xe421c |
5212 | #define _PCH_DPC_AUX_CH_DATA4 0xe4220 |
5213 | #define _PCH_DPC_AUX_CH_DATA5 0xe4224 |
5214 | |
5215 | #define _PCH_DP_D 0xe4300 |
5216 | #define PCH_DP_D _MMIO(_PCH_DP_D) |
5217 | #define _PCH_DPD_AUX_CH_CTL 0xe4310 |
5218 | #define _PCH_DPD_AUX_CH_DATA1 0xe4314 |
5219 | #define _PCH_DPD_AUX_CH_DATA2 0xe4318 |
5220 | #define _PCH_DPD_AUX_CH_DATA3 0xe431c |
5221 | #define _PCH_DPD_AUX_CH_DATA4 0xe4320 |
5222 | #define _PCH_DPD_AUX_CH_DATA5 0xe4324 |
5223 | |
5224 | #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) |
5225 | #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ |
5226 | |
5227 | /* CPT */ |
5228 | #define _TRANS_DP_CTL_A 0xe0300 |
5229 | #define _TRANS_DP_CTL_B 0xe1300 |
5230 | #define _TRANS_DP_CTL_C 0xe2300 |
5231 | #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B) |
5232 | #define TRANS_DP_OUTPUT_ENABLE REG_BIT(31) |
5233 | #define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29) |
5234 | #define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3) |
5235 | #define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B) |
5236 | #define TRANS_DP_AUDIO_ONLY REG_BIT(26) |
5237 | #define TRANS_DP_ENH_FRAMING REG_BIT(18) |
5238 | #define TRANS_DP_BPC_MASK REG_GENMASK(10, 9) |
5239 | #define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0) |
5240 | #define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1) |
5241 | #define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2) |
5242 | #define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3) |
5243 | #define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4) |
5244 | #define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3) |
5245 | |
5246 | #define _TRANS_DP2_CTL_A 0x600a0 |
5247 | #define _TRANS_DP2_CTL_B 0x610a0 |
5248 | #define _TRANS_DP2_CTL_C 0x620a0 |
5249 | #define _TRANS_DP2_CTL_D 0x630a0 |
5250 | #define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B) |
5251 | #define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31) |
5252 | #define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30) |
5253 | #define TRANS_DP2_DEBUG_ENABLE REG_BIT(23) |
5254 | |
5255 | #define _TRANS_DP2_VFREQHIGH_A 0x600a4 |
5256 | #define _TRANS_DP2_VFREQHIGH_B 0x610a4 |
5257 | #define _TRANS_DP2_VFREQHIGH_C 0x620a4 |
5258 | #define _TRANS_DP2_VFREQHIGH_D 0x630a4 |
5259 | #define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B) |
5260 | #define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8) |
5261 | #define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz)) |
5262 | |
5263 | #define _TRANS_DP2_VFREQLOW_A 0x600a8 |
5264 | #define _TRANS_DP2_VFREQLOW_B 0x610a8 |
5265 | #define _TRANS_DP2_VFREQLOW_C 0x620a8 |
5266 | #define _TRANS_DP2_VFREQLOW_D 0x630a8 |
5267 | #define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B) |
5268 | |
5269 | /* SNB eDP training params */ |
5270 | /* SNB A-stepping */ |
5271 | #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) |
5272 | #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) |
5273 | #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) |
5274 | #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) |
5275 | /* SNB B-stepping */ |
5276 | #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22) |
5277 | #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22) |
5278 | #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22) |
5279 | #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22) |
5280 | #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22) |
5281 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22) |
5282 | |
5283 | /* IVB */ |
5284 | #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22) |
5285 | #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22) |
5286 | #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22) |
5287 | #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22) |
5288 | #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22) |
5289 | #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22) |
5290 | #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22) |
5291 | |
5292 | /* legacy values */ |
5293 | #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22) |
5294 | #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22) |
5295 | #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22) |
5296 | #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22) |
5297 | #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22) |
5298 | |
5299 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22) |
5300 | |
5301 | #define VLV_PMWGICZ _MMIO(0x1300a4) |
5302 | |
5303 | #define HSW_EDRAM_CAP _MMIO(0x120010) |
5304 | #define EDRAM_ENABLED 0x1 |
5305 | #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf) |
5306 | #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7) |
5307 | #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3) |
5308 | |
5309 | #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C) |
5310 | #define PIXEL_OVERLAP_CNT_MASK (3 << 30) |
5311 | #define PIXEL_OVERLAP_CNT_SHIFT 30 |
5312 | |
5313 | #define GEN6_PCODE_MAILBOX _MMIO(0x138124) |
5314 | #define GEN6_PCODE_READY (1 << 31) |
5315 | #define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16) |
5316 | #define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8) |
5317 | #define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0) |
5318 | #define GEN6_PCODE_ERROR_MASK 0xFF |
5319 | #define GEN6_PCODE_SUCCESS 0x0 |
5320 | #define GEN6_PCODE_ILLEGAL_CMD 0x1 |
5321 | #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2 |
5322 | #define GEN6_PCODE_TIMEOUT 0x3 |
5323 | #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF |
5324 | #define GEN7_PCODE_TIMEOUT 0x2 |
5325 | #define GEN7_PCODE_ILLEGAL_DATA 0x3 |
5326 | #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4 |
5327 | #define GEN11_PCODE_LOCKED 0x6 |
5328 | #define GEN11_PCODE_REJECTED 0x11 |
5329 | #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10 |
5330 | #define GEN6_PCODE_WRITE_RC6VIDS 0x4 |
5331 | #define GEN6_PCODE_READ_RC6VIDS 0x5 |
5332 | #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) |
5333 | #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) |
5334 | #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 |
5335 | #define GEN9_PCODE_READ_MEM_LATENCY 0x6 |
5336 | #define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24) |
5337 | #define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16) |
5338 | #define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8) |
5339 | #define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0) |
5340 | #define SKL_PCODE_LOAD_HDCP_KEYS 0x5 |
5341 | #define SKL_PCODE_CDCLK_CONTROL 0x7 |
5342 | #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 |
5343 | #define SKL_CDCLK_READY_FOR_CHANGE 0x1 |
5344 | #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 |
5345 | #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 |
5346 | #define GEN6_READ_OC_PARAMS 0xc |
5347 | #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd |
5348 | #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8) |
5349 | #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8)) |
5350 | #define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8)) |
5351 | #define DISPLAY_TO_PCODE_CDCLK_MAX 0x28D |
5352 | #define DISPLAY_TO_PCODE_VOLTAGE_MASK REG_GENMASK(1, 0) |
5353 | #define DISPLAY_TO_PCODE_VOLTAGE_MAX DISPLAY_TO_PCODE_VOLTAGE_MASK |
5354 | #define DISPLAY_TO_PCODE_CDCLK_VALID REG_BIT(27) |
5355 | #define DISPLAY_TO_PCODE_PIPE_COUNT_VALID REG_BIT(31) |
5356 | #define DISPLAY_TO_PCODE_CDCLK_MASK REG_GENMASK(25, 16) |
5357 | #define DISPLAY_TO_PCODE_PIPE_COUNT_MASK REG_GENMASK(30, 28) |
5358 | #define DISPLAY_TO_PCODE_CDCLK(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x)) |
5359 | #define DISPLAY_TO_PCODE_PIPE_COUNT(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x)) |
5360 | #define DISPLAY_TO_PCODE_VOLTAGE(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x)) |
5361 | #define DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \ |
5362 | ((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \ |
5363 | (DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \ |
5364 | (DISPLAY_TO_PCODE_VOLTAGE(voltage_level))) |
5365 | #define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe |
5366 | #define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0) |
5367 | #define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0) |
5368 | #define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1) |
5369 | #define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2) |
5370 | #define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2) |
5371 | #define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0) |
5372 | #define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1) |
5373 | #define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2) |
5374 | #define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0) |
5375 | #define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x)) |
5376 | #define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8) |
5377 | #define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x)) |
5378 | #define GEN6_PCODE_READ_D_COMP 0x10 |
5379 | #define GEN6_PCODE_WRITE_D_COMP 0x11 |
5380 | #define ICL_PCODE_EXIT_TCCOLD 0x12 |
5381 | #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 |
5382 | #define DISPLAY_IPS_CONTROL 0x19 |
5383 | #define TGL_PCODE_TCCOLD 0x26 |
5384 | #define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0) |
5385 | #define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0 |
5386 | #define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0) |
5387 | /* See also IPS_CTL */ |
5388 | #define IPS_PCODE_CONTROL (1 << 30) |
5389 | #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A |
5390 | #define GEN9_PCODE_SAGV_CONTROL 0x21 |
5391 | #define GEN9_SAGV_DISABLE 0x0 |
5392 | #define GEN9_SAGV_IS_DISABLED 0x1 |
5393 | #define GEN9_SAGV_ENABLE 0x3 |
5394 | #define DG1_PCODE_STATUS 0x7E |
5395 | #define DG1_UNCORE_GET_INIT_STATUS 0x0 |
5396 | #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1 |
5397 | #define PCODE_POWER_SETUP 0x7C |
5398 | #define POWER_SETUP_SUBCOMMAND_READ_I1 0x4 |
5399 | #define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5 |
5400 | #define POWER_SETUP_I1_WATTS REG_BIT(31) |
5401 | #define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */ |
5402 | #define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0) |
5403 | #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23 |
5404 | #define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* xehpsdv, pvc */ |
5405 | /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */ |
5406 | #define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0 |
5407 | #define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1 |
5408 | /* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */ |
5409 | /* XEHP_PCODE_FREQUENCY_CONFIG param2 */ |
5410 | #define PCODE_MBOX_DOMAIN_NONE 0x0 |
5411 | #define PCODE_MBOX_DOMAIN_MEDIAFF 0x3 |
5412 | #define GEN6_PCODE_DATA _MMIO(0x138128) |
5413 | #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 |
5414 | #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 |
5415 | #define GEN6_PCODE_DATA1 _MMIO(0x13812C) |
5416 | |
5417 | /* IVYBRIDGE DPF */ |
5418 | #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ |
5419 | #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14) |
5420 | #define GEN7_PARITY_ERROR_VALID (1 << 13) |
5421 | #define GEN7_L3CDERRST1_BANK_MASK (3 << 11) |
5422 | #define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8) |
5423 | #define GEN7_PARITY_ERROR_ROW(reg) \ |
5424 | (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14) |
5425 | #define GEN7_PARITY_ERROR_BANK(reg) \ |
5426 | (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11) |
5427 | #define GEN7_PARITY_ERROR_SUBBANK(reg) \ |
5428 | (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) |
5429 | #define GEN7_L3CDERRST1_ENABLE (1 << 7) |
5430 | |
5431 | /* These are the 4 32-bit write offset registers for each stream |
5432 | * output buffer. It determines the offset from the |
5433 | * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. |
5434 | */ |
5435 | #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) |
5436 | |
5437 | /* |
5438 | * HSW - ICL power wells |
5439 | * |
5440 | * Platforms have up to 3 power well control register sets, each set |
5441 | * controlling up to 16 power wells via a request/status HW flag tuple: |
5442 | * - main (HSW_PWR_WELL_CTL[1-4]) |
5443 | * - AUX (ICL_PWR_WELL_CTL_AUX[1-4]) |
5444 | * - DDI (ICL_PWR_WELL_CTL_DDI[1-4]) |
5445 | * Each control register set consists of up to 4 registers used by different |
5446 | * sources that can request a power well to be enabled: |
5447 | * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1) |
5448 | * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2) |
5449 | * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set) |
5450 | * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4) |
5451 | */ |
5452 | #define HSW_PWR_WELL_CTL1 _MMIO(0x45400) |
5453 | #define HSW_PWR_WELL_CTL2 _MMIO(0x45404) |
5454 | #define HSW_PWR_WELL_CTL3 _MMIO(0x45408) |
5455 | #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C) |
5456 | #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2)) |
5457 | #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2)) |
5458 | |
5459 | /* HSW/BDW power well */ |
5460 | #define HSW_PW_CTL_IDX_GLOBAL 15 |
5461 | |
5462 | /* SKL/BXT/GLK power wells */ |
5463 | #define SKL_PW_CTL_IDX_PW_2 15 |
5464 | #define SKL_PW_CTL_IDX_PW_1 14 |
5465 | #define GLK_PW_CTL_IDX_AUX_C 10 |
5466 | #define GLK_PW_CTL_IDX_AUX_B 9 |
5467 | #define GLK_PW_CTL_IDX_AUX_A 8 |
5468 | #define SKL_PW_CTL_IDX_DDI_D 4 |
5469 | #define SKL_PW_CTL_IDX_DDI_C 3 |
5470 | #define SKL_PW_CTL_IDX_DDI_B 2 |
5471 | #define SKL_PW_CTL_IDX_DDI_A_E 1 |
5472 | #define GLK_PW_CTL_IDX_DDI_A 1 |
5473 | #define SKL_PW_CTL_IDX_MISC_IO 0 |
5474 | |
5475 | /* ICL/TGL - power wells */ |
5476 | #define TGL_PW_CTL_IDX_PW_5 4 |
5477 | #define ICL_PW_CTL_IDX_PW_4 3 |
5478 | #define ICL_PW_CTL_IDX_PW_3 2 |
5479 | #define ICL_PW_CTL_IDX_PW_2 1 |
5480 | #define ICL_PW_CTL_IDX_PW_1 0 |
5481 | |
5482 | /* XE_LPD - power wells */ |
5483 | #define XELPD_PW_CTL_IDX_PW_D 8 |
5484 | #define XELPD_PW_CTL_IDX_PW_C 7 |
5485 | #define XELPD_PW_CTL_IDX_PW_B 6 |
5486 | #define XELPD_PW_CTL_IDX_PW_A 5 |
5487 | |
5488 | #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440) |
5489 | #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444) |
5490 | #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C) |
5491 | #define TGL_PW_CTL_IDX_AUX_TBT6 14 |
5492 | #define TGL_PW_CTL_IDX_AUX_TBT5 13 |
5493 | #define TGL_PW_CTL_IDX_AUX_TBT4 12 |
5494 | #define ICL_PW_CTL_IDX_AUX_TBT4 11 |
5495 | #define TGL_PW_CTL_IDX_AUX_TBT3 11 |
5496 | #define ICL_PW_CTL_IDX_AUX_TBT3 10 |
5497 | #define TGL_PW_CTL_IDX_AUX_TBT2 10 |
5498 | #define ICL_PW_CTL_IDX_AUX_TBT2 9 |
5499 | #define TGL_PW_CTL_IDX_AUX_TBT1 9 |
5500 | #define ICL_PW_CTL_IDX_AUX_TBT1 8 |
5501 | #define TGL_PW_CTL_IDX_AUX_TC6 8 |
5502 | #define XELPD_PW_CTL_IDX_AUX_E 8 |
5503 | #define TGL_PW_CTL_IDX_AUX_TC5 7 |
5504 | #define XELPD_PW_CTL_IDX_AUX_D 7 |
5505 | #define TGL_PW_CTL_IDX_AUX_TC4 6 |
5506 | #define ICL_PW_CTL_IDX_AUX_F 5 |
5507 | #define TGL_PW_CTL_IDX_AUX_TC3 5 |
5508 | #define ICL_PW_CTL_IDX_AUX_E 4 |
5509 | #define TGL_PW_CTL_IDX_AUX_TC2 4 |
5510 | #define ICL_PW_CTL_IDX_AUX_D 3 |
5511 | #define TGL_PW_CTL_IDX_AUX_TC1 3 |
5512 | #define ICL_PW_CTL_IDX_AUX_C 2 |
5513 | #define ICL_PW_CTL_IDX_AUX_B 1 |
5514 | #define ICL_PW_CTL_IDX_AUX_A 0 |
5515 | |
5516 | #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450) |
5517 | #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454) |
5518 | #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C) |
5519 | #define XELPD_PW_CTL_IDX_DDI_E 8 |
5520 | #define TGL_PW_CTL_IDX_DDI_TC6 8 |
5521 | #define XELPD_PW_CTL_IDX_DDI_D 7 |
5522 | #define TGL_PW_CTL_IDX_DDI_TC5 7 |
5523 | #define TGL_PW_CTL_IDX_DDI_TC4 6 |
5524 | #define ICL_PW_CTL_IDX_DDI_F 5 |
5525 | #define TGL_PW_CTL_IDX_DDI_TC3 5 |
5526 | #define ICL_PW_CTL_IDX_DDI_E 4 |
5527 | #define TGL_PW_CTL_IDX_DDI_TC2 4 |
5528 | #define ICL_PW_CTL_IDX_DDI_D 3 |
5529 | #define TGL_PW_CTL_IDX_DDI_TC1 3 |
5530 | #define ICL_PW_CTL_IDX_DDI_C 2 |
5531 | #define ICL_PW_CTL_IDX_DDI_B 1 |
5532 | #define ICL_PW_CTL_IDX_DDI_A 0 |
5533 | |
5534 | /* HSW - power well misc debug registers */ |
5535 | #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) |
5536 | #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31) |
5537 | #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20) |
5538 | #define HSW_PWR_WELL_FORCE_ON (1 << 19) |
5539 | #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) |
5540 | |
5541 | /* SKL Fuse Status */ |
5542 | enum skl_power_gate { |
5543 | SKL_PG0, |
5544 | SKL_PG1, |
5545 | SKL_PG2, |
5546 | ICL_PG3, |
5547 | ICL_PG4, |
5548 | }; |
5549 | |
5550 | #define SKL_FUSE_STATUS _MMIO(0x42000) |
5551 | #define SKL_FUSE_DOWNLOAD_STATUS (1 << 31) |
5552 | /* |
5553 | * PG0 is HW controlled, so doesn't have a corresponding power well control knob |
5554 | * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2 |
5555 | */ |
5556 | #define SKL_PW_CTL_IDX_TO_PG(pw_idx) \ |
5557 | ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1) |
5558 | /* |
5559 | * PG0 is HW controlled, so doesn't have a corresponding power well control knob |
5560 | * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4 |
5561 | */ |
5562 | #define ICL_PW_CTL_IDX_TO_PG(pw_idx) \ |
5563 | ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1) |
5564 | #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) |
5565 | |
5566 | #define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A) |
5567 | #define _ICL_AUX_ANAOVRD1_A 0x162398 |
5568 | #define _ICL_AUX_ANAOVRD1_B 0x6C398 |
5569 | #define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \ |
5570 | _ICL_AUX_ANAOVRD1_A, \ |
5571 | _ICL_AUX_ANAOVRD1_B)) |
5572 | #define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7) |
5573 | #define ICL_AUX_ANAOVRD1_ENABLE (1 << 0) |
5574 | |
5575 | /* Per-pipe DDI Function Control */ |
5576 | #define _TRANS_DDI_FUNC_CTL_A 0x60400 |
5577 | #define _TRANS_DDI_FUNC_CTL_B 0x61400 |
5578 | #define _TRANS_DDI_FUNC_CTL_C 0x62400 |
5579 | #define _TRANS_DDI_FUNC_CTL_D 0x63400 |
5580 | #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 |
5581 | #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400 |
5582 | #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00 |
5583 | #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A) |
5584 | |
5585 | #define TRANS_DDI_FUNC_ENABLE (1 << 31) |
5586 | /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ |
5587 | #define TRANS_DDI_PORT_SHIFT 28 |
5588 | #define TGL_TRANS_DDI_PORT_SHIFT 27 |
5589 | #define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT) |
5590 | #define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT) |
5591 | #define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT) |
5592 | #define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT) |
5593 | #define TRANS_DDI_MODE_SELECT_MASK (7 << 24) |
5594 | #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24) |
5595 | #define TRANS_DDI_MODE_SELECT_DVI (1 << 24) |
5596 | #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) |
5597 | #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) |
5598 | #define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24) |
5599 | #define TRANS_DDI_BPC_MASK (7 << 20) |
5600 | #define TRANS_DDI_BPC_8 (0 << 20) |
5601 | #define TRANS_DDI_BPC_10 (1 << 20) |
5602 | #define TRANS_DDI_BPC_6 (2 << 20) |
5603 | #define TRANS_DDI_BPC_12 (3 << 20) |
5604 | #define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18) |
5605 | #define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x)) |
5606 | #define TRANS_DDI_PVSYNC (1 << 17) |
5607 | #define TRANS_DDI_PHSYNC (1 << 16) |
5608 | #define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15) |
5609 | #define TRANS_DDI_EDP_INPUT_MASK (7 << 12) |
5610 | #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12) |
5611 | #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12) |
5612 | #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) |
5613 | #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) |
5614 | #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12) |
5615 | #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10) |
5616 | #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \ |
5617 | REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans) |
5618 | #define TRANS_DDI_HDCP_SIGNALLING (1 << 9) |
5619 | #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8) |
5620 | #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7) |
5621 | #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6) |
5622 | #define TRANS_DDI_HDCP_SELECT REG_BIT(5) |
5623 | #define TRANS_DDI_BFI_ENABLE (1 << 4) |
5624 | #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4) |
5625 | #define TRANS_DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1) |
5626 | #define TRANS_DDI_PORT_WIDTH(width) REG_FIELD_PREP(TRANS_DDI_PORT_WIDTH_MASK, (width) - 1) |
5627 | #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0) |
5628 | #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \ |
5629 | | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \ |
5630 | | TRANS_DDI_HDMI_SCRAMBLING) |
5631 | |
5632 | #define _TRANS_DDI_FUNC_CTL2_A 0x60404 |
5633 | #define _TRANS_DDI_FUNC_CTL2_B 0x61404 |
5634 | #define _TRANS_DDI_FUNC_CTL2_C 0x62404 |
5635 | #define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404 |
5636 | #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404 |
5637 | #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04 |
5638 | #define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL2_A) |
5639 | #define PORT_SYNC_MODE_ENABLE REG_BIT(4) |
5640 | #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0) |
5641 | #define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x)) |
5642 | |
5643 | #define TRANS_CMTG_CHICKEN _MMIO(0x6fa90) |
5644 | #define DISABLE_DPT_CLK_GATING REG_BIT(1) |
5645 | |
5646 | /* DisplayPort Transport Control */ |
5647 | #define _DP_TP_CTL_A 0x64040 |
5648 | #define _DP_TP_CTL_B 0x64140 |
5649 | #define _TGL_DP_TP_CTL_A 0x60540 |
5650 | #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) |
5651 | #define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A) |
5652 | #define DP_TP_CTL_ENABLE (1 << 31) |
5653 | #define DP_TP_CTL_FEC_ENABLE (1 << 30) |
5654 | #define DP_TP_CTL_MODE_SST (0 << 27) |
5655 | #define DP_TP_CTL_MODE_MST (1 << 27) |
5656 | #define DP_TP_CTL_FORCE_ACT (1 << 25) |
5657 | #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) |
5658 | #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) |
5659 | #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) |
5660 | #define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8) |
5661 | #define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8) |
5662 | #define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8) |
5663 | #define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8) |
5664 | #define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8) |
5665 | #define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8) |
5666 | #define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7) |
5667 | |
5668 | /* DisplayPort Transport Status */ |
5669 | #define _DP_TP_STATUS_A 0x64044 |
5670 | #define _DP_TP_STATUS_B 0x64144 |
5671 | #define _TGL_DP_TP_STATUS_A 0x60544 |
5672 | #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) |
5673 | #define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A) |
5674 | #define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28) |
5675 | #define DP_TP_STATUS_IDLE_DONE (1 << 25) |
5676 | #define DP_TP_STATUS_ACT_SENT (1 << 24) |
5677 | #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23) |
5678 | #define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12) |
5679 | #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) |
5680 | #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) |
5681 | #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) |
5682 | |
5683 | /* DDI Buffer Control */ |
5684 | #define _DDI_BUF_CTL_A 0x64000 |
5685 | #define _DDI_BUF_CTL_B 0x64100 |
5686 | /* Known as DDI_CTL_DE in MTL+ */ |
5687 | #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) |
5688 | #define DDI_BUF_CTL_ENABLE (1 << 31) |
5689 | #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) |
5690 | #define DDI_BUF_EMP_MASK (0xf << 24) |
5691 | #define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20) |
5692 | #define DDI_BUF_PORT_DATA_MASK REG_GENMASK(19, 18) |
5693 | #define DDI_BUF_PORT_DATA_10BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 0) |
5694 | #define DDI_BUF_PORT_DATA_20BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1) |
5695 | #define DDI_BUF_PORT_DATA_40BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2) |
5696 | #define DDI_BUF_PORT_REVERSAL (1 << 16) |
5697 | #define DDI_BUF_IS_IDLE (1 << 7) |
5698 | #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6) |
5699 | #define DDI_A_4_LANES (1 << 4) |
5700 | #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) |
5701 | #define DDI_PORT_WIDTH_MASK (7 << 1) |
5702 | #define DDI_PORT_WIDTH_SHIFT 1 |
5703 | #define DDI_INIT_DISPLAY_DETECTED (1 << 0) |
5704 | |
5705 | /* DDI Buffer Translations */ |
5706 | #define _DDI_BUF_TRANS_A 0x64E00 |
5707 | #define _DDI_BUF_TRANS_B 0x64E60 |
5708 | #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8) |
5709 | #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) |
5710 | #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) |
5711 | |
5712 | /* DDI DP Compliance Control */ |
5713 | #define _DDI_DP_COMP_CTL_A 0x605F0 |
5714 | #define _DDI_DP_COMP_CTL_B 0x615F0 |
5715 | #define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B) |
5716 | #define DDI_DP_COMP_CTL_ENABLE (1 << 31) |
5717 | #define DDI_DP_COMP_CTL_D10_2 (0 << 28) |
5718 | #define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28) |
5719 | #define DDI_DP_COMP_CTL_PRBS7 (2 << 28) |
5720 | #define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28) |
5721 | #define DDI_DP_COMP_CTL_HBR2 (4 << 28) |
5722 | #define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28) |
5723 | #define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0) |
5724 | |
5725 | /* DDI DP Compliance Pattern */ |
5726 | #define _DDI_DP_COMP_PAT_A 0x605F4 |
5727 | #define _DDI_DP_COMP_PAT_B 0x615F4 |
5728 | #define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4) |
5729 | |
5730 | /* Sideband Interface (SBI) is programmed indirectly, via |
5731 | * SBI_ADDR, which contains the register offset; and SBI_DATA, |
5732 | * which contains the payload */ |
5733 | #define SBI_ADDR _MMIO(0xC6000) |
5734 | #define SBI_DATA _MMIO(0xC6004) |
5735 | #define SBI_CTL_STAT _MMIO(0xC6008) |
5736 | #define SBI_CTL_DEST_ICLK (0x0 << 16) |
5737 | #define SBI_CTL_DEST_MPHY (0x1 << 16) |
5738 | #define SBI_CTL_OP_IORD (0x2 << 8) |
5739 | #define SBI_CTL_OP_IOWR (0x3 << 8) |
5740 | #define SBI_CTL_OP_CRRD (0x6 << 8) |
5741 | #define SBI_CTL_OP_CRWR (0x7 << 8) |
5742 | #define SBI_RESPONSE_FAIL (0x1 << 1) |
5743 | #define SBI_RESPONSE_SUCCESS (0x0 << 1) |
5744 | #define SBI_BUSY (0x1 << 0) |
5745 | #define SBI_READY (0x0 << 0) |
5746 | |
5747 | /* SBI offsets */ |
5748 | #define SBI_SSCDIVINTPHASE 0x0200 |
5749 | #define SBI_SSCDIVINTPHASE6 0x0600 |
5750 | #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 |
5751 | #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1) |
5752 | #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1) |
5753 | #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 |
5754 | #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8) |
5755 | #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8) |
5756 | #define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15) |
5757 | #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0) |
5758 | #define SBI_SSCDITHPHASE 0x0204 |
5759 | #define SBI_SSCCTL 0x020c |
5760 | #define SBI_SSCCTL6 0x060C |
5761 | #define SBI_SSCCTL_PATHALT (1 << 3) |
5762 | #define SBI_SSCCTL_DISABLE (1 << 0) |
5763 | #define SBI_SSCAUXDIV6 0x0610 |
5764 | #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 |
5765 | #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4) |
5766 | #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4) |
5767 | #define SBI_DBUFF0 0x2a00 |
5768 | #define SBI_GEN0 0x1f00 |
5769 | #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0) |
5770 | |
5771 | /* LPT PIXCLK_GATE */ |
5772 | #define PIXCLK_GATE _MMIO(0xC6020) |
5773 | #define PIXCLK_GATE_UNGATE (1 << 0) |
5774 | #define PIXCLK_GATE_GATE (0 << 0) |
5775 | |
5776 | /* SPLL */ |
5777 | #define SPLL_CTL _MMIO(0x46020) |
5778 | #define SPLL_PLL_ENABLE (1 << 31) |
5779 | #define SPLL_REF_BCLK (0 << 28) |
5780 | #define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ |
5781 | #define SPLL_REF_NON_SSC_HSW (2 << 28) |
5782 | #define SPLL_REF_PCH_SSC_BDW (2 << 28) |
5783 | #define SPLL_REF_LCPLL (3 << 28) |
5784 | #define SPLL_REF_MASK (3 << 28) |
5785 | #define SPLL_FREQ_810MHz (0 << 26) |
5786 | #define SPLL_FREQ_1350MHz (1 << 26) |
5787 | #define SPLL_FREQ_2700MHz (2 << 26) |
5788 | #define SPLL_FREQ_MASK (3 << 26) |
5789 | |
5790 | /* WRPLL */ |
5791 | #define _WRPLL_CTL1 0x46040 |
5792 | #define _WRPLL_CTL2 0x46060 |
5793 | #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) |
5794 | #define WRPLL_PLL_ENABLE (1 << 31) |
5795 | #define WRPLL_REF_BCLK (0 << 28) |
5796 | #define WRPLL_REF_PCH_SSC (1 << 28) |
5797 | #define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ |
5798 | #define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */ |
5799 | #define WRPLL_REF_LCPLL (3 << 28) |
5800 | #define WRPLL_REF_MASK (3 << 28) |
5801 | /* WRPLL divider programming */ |
5802 | #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0) |
5803 | #define WRPLL_DIVIDER_REF_MASK (0xff) |
5804 | #define WRPLL_DIVIDER_POST(x) ((x) << 8) |
5805 | #define WRPLL_DIVIDER_POST_MASK (0x3f << 8) |
5806 | #define WRPLL_DIVIDER_POST_SHIFT 8 |
5807 | #define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16) |
5808 | #define WRPLL_DIVIDER_FB_SHIFT 16 |
5809 | #define WRPLL_DIVIDER_FB_MASK (0xff << 16) |
5810 | |
5811 | /* Port clock selection */ |
5812 | #define _PORT_CLK_SEL_A 0x46100 |
5813 | #define _PORT_CLK_SEL_B 0x46104 |
5814 | #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B) |
5815 | #define PORT_CLK_SEL_MASK REG_GENMASK(31, 29) |
5816 | #define PORT_CLK_SEL_LCPLL_2700 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0) |
5817 | #define PORT_CLK_SEL_LCPLL_1350 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1) |
5818 | #define PORT_CLK_SEL_LCPLL_810 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2) |
5819 | #define PORT_CLK_SEL_SPLL REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3) |
5820 | #define PORT_CLK_SEL_WRPLL(pll) REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll)) |
5821 | #define PORT_CLK_SEL_WRPLL1 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4) |
5822 | #define PORT_CLK_SEL_WRPLL2 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5) |
5823 | #define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7) |
5824 | |
5825 | /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */ |
5826 | #define DDI_CLK_SEL(port) PORT_CLK_SEL(port) |
5827 | #define DDI_CLK_SEL_MASK REG_GENMASK(31, 28) |
5828 | #define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0) |
5829 | #define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8) |
5830 | #define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC) |
5831 | #define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD) |
5832 | #define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE) |
5833 | #define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF) |
5834 | |
5835 | /* Transcoder clock selection */ |
5836 | #define _TRANS_CLK_SEL_A 0x46140 |
5837 | #define _TRANS_CLK_SEL_B 0x46144 |
5838 | #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B) |
5839 | /* For each transcoder, we need to select the corresponding port clock */ |
5840 | #define TRANS_CLK_SEL_DISABLED (0x0 << 29) |
5841 | #define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29) |
5842 | #define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28) |
5843 | #define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28) |
5844 | |
5845 | |
5846 | #define CDCLK_FREQ _MMIO(0x46200) |
5847 | |
5848 | #define _TRANSA_MSA_MISC 0x60410 |
5849 | #define _TRANSB_MSA_MISC 0x61410 |
5850 | #define _TRANSC_MSA_MISC 0x62410 |
5851 | #define _TRANS_EDP_MSA_MISC 0x6f410 |
5852 | #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC) |
5853 | /* See DP_MSA_MISC_* for the bit definitions */ |
5854 | |
5855 | #define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C |
5856 | #define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C |
5857 | #define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C |
5858 | #define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C |
5859 | #define TRANS_SET_CONTEXT_LATENCY(tran) _MMIO_TRANS2(tran, _TRANS_A_SET_CONTEXT_LATENCY) |
5860 | #define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0) |
5861 | #define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x)) |
5862 | |
5863 | /* LCPLL Control */ |
5864 | #define LCPLL_CTL _MMIO(0x130040) |
5865 | #define LCPLL_PLL_DISABLE (1 << 31) |
5866 | #define LCPLL_PLL_LOCK (1 << 30) |
5867 | #define LCPLL_REF_NON_SSC (0 << 28) |
5868 | #define LCPLL_REF_BCLK (2 << 28) |
5869 | #define LCPLL_REF_PCH_SSC (3 << 28) |
5870 | #define LCPLL_REF_MASK (3 << 28) |
5871 | #define LCPLL_CLK_FREQ_MASK (3 << 26) |
5872 | #define LCPLL_CLK_FREQ_450 (0 << 26) |
5873 | #define LCPLL_CLK_FREQ_54O_BDW (1 << 26) |
5874 | #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26) |
5875 | #define LCPLL_CLK_FREQ_675_BDW (3 << 26) |
5876 | #define LCPLL_CD_CLOCK_DISABLE (1 << 25) |
5877 | #define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24) |
5878 | #define LCPLL_CD2X_CLOCK_DISABLE (1 << 23) |
5879 | #define LCPLL_POWER_DOWN_ALLOW (1 << 22) |
5880 | #define LCPLL_CD_SOURCE_FCLK (1 << 21) |
5881 | #define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19) |
5882 | |
5883 | /* |
5884 | * SKL Clocks |
5885 | */ |
5886 | |
5887 | /* CDCLK_CTL */ |
5888 | #define CDCLK_CTL _MMIO(0x46000) |
5889 | #define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26) |
5890 | #define CDCLK_FREQ_450_432 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0) |
5891 | #define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1) |
5892 | #define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2) |
5893 | #define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3) |
5894 | #define MDCLK_SOURCE_SEL_CDCLK_PLL REG_BIT(25) |
5895 | #define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22) |
5896 | #define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0) |
5897 | #define BXT_CDCLK_CD2X_DIV_SEL_1_5 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1) |
5898 | #define BXT_CDCLK_CD2X_DIV_SEL_2 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 2) |
5899 | #define BXT_CDCLK_CD2X_DIV_SEL_4 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 3) |
5900 | #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20) |
5901 | #define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19) |
5902 | #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) |
5903 | #define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19) |
5904 | #define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19) |
5905 | #define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe) |
5906 | #define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE |
5907 | #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16) |
5908 | #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) |
5909 | |
5910 | /* CDCLK_SQUASH_CTL */ |
5911 | #define CDCLK_SQUASH_CTL _MMIO(0x46008) |
5912 | #define CDCLK_SQUASH_ENABLE REG_BIT(31) |
5913 | #define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24) |
5914 | #define CDCLK_SQUASH_WINDOW_SIZE(x) REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x)) |
5915 | #define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0) |
5916 | #define CDCLK_SQUASH_WAVEFORM(x) REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x)) |
5917 | |
5918 | /* LCPLL_CTL */ |
5919 | #define LCPLL1_CTL _MMIO(0x46010) |
5920 | #define LCPLL2_CTL _MMIO(0x46014) |
5921 | #define LCPLL_PLL_ENABLE (1 << 31) |
5922 | |
5923 | /* DPLL control1 */ |
5924 | #define DPLL_CTRL1 _MMIO(0x6C058) |
5925 | #define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5)) |
5926 | #define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4)) |
5927 | #define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1)) |
5928 | #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1) |
5929 | #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1)) |
5930 | #define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6)) |
5931 | #define DPLL_CTRL1_LINK_RATE_2700 0 |
5932 | #define DPLL_CTRL1_LINK_RATE_1350 1 |
5933 | #define DPLL_CTRL1_LINK_RATE_810 2 |
5934 | #define DPLL_CTRL1_LINK_RATE_1620 3 |
5935 | #define DPLL_CTRL1_LINK_RATE_1080 4 |
5936 | #define DPLL_CTRL1_LINK_RATE_2160 5 |
5937 | |
5938 | /* DPLL control2 */ |
5939 | #define DPLL_CTRL2 _MMIO(0x6C05C) |
5940 | #define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15)) |
5941 | #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1)) |
5942 | #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1) |
5943 | #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1)) |
5944 | #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3)) |
5945 | |
5946 | /* DPLL Status */ |
5947 | #define DPLL_STATUS _MMIO(0x6C060) |
5948 | #define DPLL_LOCK(id) (1 << ((id) * 8)) |
5949 | |
5950 | /* DPLL cfg */ |
5951 | #define _DPLL1_CFGCR1 0x6C040 |
5952 | #define _DPLL2_CFGCR1 0x6C048 |
5953 | #define _DPLL3_CFGCR1 0x6C050 |
5954 | #define DPLL_CFGCR1_FREQ_ENABLE (1 << 31) |
5955 | #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9) |
5956 | #define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9) |
5957 | #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) |
5958 | |
5959 | #define _DPLL1_CFGCR2 0x6C044 |
5960 | #define _DPLL2_CFGCR2 0x6C04C |
5961 | #define _DPLL3_CFGCR2 0x6C054 |
5962 | #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8) |
5963 | #define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8) |
5964 | #define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7) |
5965 | #define DPLL_CFGCR2_KDIV_MASK (3 << 5) |
5966 | #define DPLL_CFGCR2_KDIV(x) ((x) << 5) |
5967 | #define DPLL_CFGCR2_KDIV_5 (0 << 5) |
5968 | #define DPLL_CFGCR2_KDIV_2 (1 << 5) |
5969 | #define DPLL_CFGCR2_KDIV_3 (2 << 5) |
5970 | #define DPLL_CFGCR2_KDIV_1 (3 << 5) |
5971 | #define DPLL_CFGCR2_PDIV_MASK (7 << 2) |
5972 | #define DPLL_CFGCR2_PDIV(x) ((x) << 2) |
5973 | #define DPLL_CFGCR2_PDIV_1 (0 << 2) |
5974 | #define DPLL_CFGCR2_PDIV_2 (1 << 2) |
5975 | #define DPLL_CFGCR2_PDIV_3 (2 << 2) |
5976 | #define DPLL_CFGCR2_PDIV_7 (4 << 2) |
5977 | #define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2) |
5978 | #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) |
5979 | |
5980 | #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1) |
5981 | #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2) |
5982 | |
5983 | /* ICL Clocks */ |
5984 | #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) |
5985 | #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5)) |
5986 | #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) |
5987 | #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \ |
5988 | (tc_port) + 12 : \ |
5989 | (tc_port) - TC_PORT_4 + 21)) |
5990 | #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2) |
5991 | #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) |
5992 | #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) |
5993 | #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27) |
5994 | #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \ |
5995 | (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) |
5996 | #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \ |
5997 | ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) |
5998 | |
5999 | /* |
6000 | * DG1 Clocks |
6001 | * First registers controls the first A and B, while the second register |
6002 | * controls the phy C and D. The bits on these registers are the |
6003 | * same, but refer to different phys |
6004 | */ |
6005 | #define _DG1_DPCLKA_CFGCR0 0x164280 |
6006 | #define _DG1_DPCLKA1_CFGCR0 0x16C280 |
6007 | #define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2) |
6008 | #define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2) |
6009 | #define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \ |
6010 | _DG1_DPCLKA_CFGCR0, \ |
6011 | _DG1_DPCLKA1_CFGCR0) |
6012 | #define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10) |
6013 | #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2) |
6014 | #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) |
6015 | #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) |
6016 | |
6017 | /* ADLS Clocks */ |
6018 | #define _ADLS_DPCLKA_CFGCR0 0x164280 |
6019 | #define _ADLS_DPCLKA_CFGCR1 0x1642BC |
6020 | #define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \ |
6021 | _ADLS_DPCLKA_CFGCR0, \ |
6022 | _ADLS_DPCLKA_CFGCR1) |
6023 | #define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2) |
6024 | /* ADLS DPCLKA_CFGCR0 DDI mask */ |
6025 | #define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4) |
6026 | #define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2) |
6027 | #define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0) |
6028 | /* ADLS DPCLKA_CFGCR1 DDI mask */ |
6029 | #define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2) |
6030 | #define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0) |
6031 | #define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \ |
6032 | ADLS_DPCLKA_DDIA_SEL_MASK, \ |
6033 | ADLS_DPCLKA_DDIB_SEL_MASK, \ |
6034 | ADLS_DPCLKA_DDII_SEL_MASK, \ |
6035 | ADLS_DPCLKA_DDIJ_SEL_MASK, \ |
6036 | ADLS_DPCLKA_DDIK_SEL_MASK) |
6037 | |
6038 | /* ICL PLL */ |
6039 | #define _DPLL0_ENABLE 0x46010 |
6040 | #define _DPLL1_ENABLE 0x46014 |
6041 | #define _ADLS_DPLL2_ENABLE 0x46018 |
6042 | #define _ADLS_DPLL3_ENABLE 0x46030 |
6043 | #define PLL_ENABLE REG_BIT(31) |
6044 | #define PLL_LOCK REG_BIT(30) |
6045 | #define PLL_POWER_ENABLE REG_BIT(27) |
6046 | #define PLL_POWER_STATE REG_BIT(26) |
6047 | #define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \ |
6048 | _DPLL0_ENABLE, _DPLL1_ENABLE, \ |
6049 | _ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE)) |
6050 | |
6051 | #define _DG2_PLL3_ENABLE 0x4601C |
6052 | |
6053 | #define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \ |
6054 | _DPLL0_ENABLE, _DPLL1_ENABLE, \ |
6055 | _DG2_PLL3_ENABLE, _DG2_PLL3_ENABLE)) |
6056 | |
6057 | #define TBT_PLL_ENABLE _MMIO(0x46020) |
6058 | |
6059 | #define _MG_PLL1_ENABLE 0x46030 |
6060 | #define _MG_PLL2_ENABLE 0x46034 |
6061 | #define _MG_PLL3_ENABLE 0x46038 |
6062 | #define _MG_PLL4_ENABLE 0x4603C |
6063 | /* Bits are the same as _DPLL0_ENABLE */ |
6064 | #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ |
6065 | _MG_PLL2_ENABLE) |
6066 | |
6067 | /* DG1 PLL */ |
6068 | #define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ |
6069 | _DPLL0_ENABLE, _DPLL1_ENABLE, \ |
6070 | _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)) |
6071 | |
6072 | /* ADL-P Type C PLL */ |
6073 | #define PORTTC1_PLL_ENABLE 0x46038 |
6074 | #define PORTTC2_PLL_ENABLE 0x46040 |
6075 | |
6076 | #define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \ |
6077 | PORTTC1_PLL_ENABLE, \ |
6078 | PORTTC2_PLL_ENABLE) |
6079 | |
6080 | #define _ICL_DPLL0_CFGCR0 0x164000 |
6081 | #define _ICL_DPLL1_CFGCR0 0x164080 |
6082 | #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \ |
6083 | _ICL_DPLL1_CFGCR0) |
6084 | #define DPLL_CFGCR0_HDMI_MODE (1 << 30) |
6085 | #define DPLL_CFGCR0_SSC_ENABLE (1 << 29) |
6086 | #define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25) |
6087 | #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25) |
6088 | #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25) |
6089 | #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25) |
6090 | #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25) |
6091 | #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25) |
6092 | #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25) |
6093 | #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25) |
6094 | #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25) |
6095 | #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25) |
6096 | #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10) |
6097 | #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10) |
6098 | #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10) |
6099 | #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff) |
6100 | |
6101 | #define _ICL_DPLL0_CFGCR1 0x164004 |
6102 | #define _ICL_DPLL1_CFGCR1 0x164084 |
6103 | #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \ |
6104 | _ICL_DPLL1_CFGCR1) |
6105 | #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10) |
6106 | #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10) |
6107 | #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10) |
6108 | #define DPLL_CFGCR1_QDIV_MODE_SHIFT (9) |
6109 | #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9) |
6110 | #define DPLL_CFGCR1_KDIV_MASK (7 << 6) |
6111 | #define DPLL_CFGCR1_KDIV_SHIFT (6) |
6112 | #define DPLL_CFGCR1_KDIV(x) ((x) << 6) |
6113 | #define DPLL_CFGCR1_KDIV_1 (1 << 6) |
6114 | #define DPLL_CFGCR1_KDIV_2 (2 << 6) |
6115 | #define DPLL_CFGCR1_KDIV_3 (4 << 6) |
6116 | #define DPLL_CFGCR1_PDIV_MASK (0xf << 2) |
6117 | #define DPLL_CFGCR1_PDIV_SHIFT (2) |
6118 | #define DPLL_CFGCR1_PDIV(x) ((x) << 2) |
6119 | #define DPLL_CFGCR1_PDIV_2 (1 << 2) |
6120 | #define DPLL_CFGCR1_PDIV_3 (2 << 2) |
6121 | #define DPLL_CFGCR1_PDIV_5 (4 << 2) |
6122 | #define DPLL_CFGCR1_PDIV_7 (8 << 2) |
6123 | #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0) |
6124 | #define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0) |
6125 | #define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0) |
6126 | |
6127 | #define _TGL_DPLL0_CFGCR0 0x164284 |
6128 | #define _TGL_DPLL1_CFGCR0 0x16428C |
6129 | #define _TGL_TBTPLL_CFGCR0 0x16429C |
6130 | #define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ |
6131 | _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ |
6132 | _TGL_TBTPLL_CFGCR0, _TGL_TBTPLL_CFGCR0)) |
6133 | #define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \ |
6134 | _TGL_DPLL1_CFGCR0) |
6135 | |
6136 | #define _TGL_DPLL0_DIV0 0x164B00 |
6137 | #define _TGL_DPLL1_DIV0 0x164C00 |
6138 | #define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0) |
6139 | #define TGL_DPLL0_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25) |
6140 | #define TGL_DPLL0_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val)) |
6141 | |
6142 | #define _TGL_DPLL0_CFGCR1 0x164288 |
6143 | #define _TGL_DPLL1_CFGCR1 0x164290 |
6144 | #define _TGL_TBTPLL_CFGCR1 0x1642A0 |
6145 | #define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ |
6146 | _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ |
6147 | _TGL_TBTPLL_CFGCR1, _TGL_TBTPLL_CFGCR1)) |
6148 | #define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ |
6149 | _TGL_DPLL1_CFGCR1) |
6150 | |
6151 | #define _DG1_DPLL2_CFGCR0 0x16C284 |
6152 | #define _DG1_DPLL3_CFGCR0 0x16C28C |
6153 | #define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ |
6154 | _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ |
6155 | _DG1_DPLL2_CFGCR0, _DG1_DPLL3_CFGCR0)) |
6156 | |
6157 | #define _DG1_DPLL2_CFGCR1 0x16C288 |
6158 | #define _DG1_DPLL3_CFGCR1 0x16C290 |
6159 | #define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ |
6160 | _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ |
6161 | _DG1_DPLL2_CFGCR1, _DG1_DPLL3_CFGCR1)) |
6162 | |
6163 | /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */ |
6164 | #define _ADLS_DPLL4_CFGCR0 0x164294 |
6165 | #define _ADLS_DPLL3_CFGCR0 0x1642C0 |
6166 | #define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ |
6167 | _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ |
6168 | _ADLS_DPLL4_CFGCR0, _ADLS_DPLL3_CFGCR0)) |
6169 | |
6170 | #define _ADLS_DPLL4_CFGCR1 0x164298 |
6171 | #define _ADLS_DPLL3_CFGCR1 0x1642C4 |
6172 | #define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ |
6173 | _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ |
6174 | _ADLS_DPLL4_CFGCR1, _ADLS_DPLL3_CFGCR1)) |
6175 | |
6176 | /* BXT display engine PLL */ |
6177 | #define BXT_DE_PLL_CTL _MMIO(0x6d000) |
6178 | #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ |
6179 | #define BXT_DE_PLL_RATIO_MASK 0xff |
6180 | |
6181 | #define BXT_DE_PLL_ENABLE _MMIO(0x46070) |
6182 | #define BXT_DE_PLL_PLL_ENABLE (1 << 31) |
6183 | #define BXT_DE_PLL_LOCK (1 << 30) |
6184 | #define BXT_DE_PLL_FREQ_REQ (1 << 23) |
6185 | #define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22) |
6186 | #define ICL_CDCLK_PLL_RATIO(x) (x) |
6187 | #define ICL_CDCLK_PLL_RATIO_MASK 0xff |
6188 | |
6189 | /* GEN9 DC */ |
6190 | #define DC_STATE_EN _MMIO(0x45504) |
6191 | #define DC_STATE_DISABLE 0 |
6192 | #define DC_STATE_EN_DC3CO REG_BIT(30) |
6193 | #define DC_STATE_DC3CO_STATUS REG_BIT(29) |
6194 | #define HOLD_PHY_CLKREQ_PG1_LATCH REG_BIT(21) |
6195 | #define HOLD_PHY_PG1_LATCH REG_BIT(20) |
6196 | #define DC_STATE_EN_UPTO_DC5 (1 << 0) |
6197 | #define DC_STATE_EN_DC9 (1 << 3) |
6198 | #define DC_STATE_EN_UPTO_DC6 (2 << 0) |
6199 | #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 |
6200 | |
6201 | #define DC_STATE_DEBUG _MMIO(0x45520) |
6202 | #define DC_STATE_DEBUG_MASK_CORES (1 << 0) |
6203 | #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1) |
6204 | |
6205 | #define D_COMP_BDW _MMIO(0x138144) |
6206 | |
6207 | /* Pipe WM_LINETIME - watermark line time */ |
6208 | #define _WM_LINETIME_A 0x45270 |
6209 | #define _WM_LINETIME_B 0x45274 |
6210 | #define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B) |
6211 | #define HSW_LINETIME_MASK REG_GENMASK(8, 0) |
6212 | #define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x)) |
6213 | #define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16) |
6214 | #define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x)) |
6215 | |
6216 | /* SFUSE_STRAP */ |
6217 | #define SFUSE_STRAP _MMIO(0xc2014) |
6218 | #define SFUSE_STRAP_FUSE_LOCK (1 << 13) |
6219 | #define SFUSE_STRAP_RAW_FREQUENCY (1 << 8) |
6220 | #define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7) |
6221 | #define SFUSE_STRAP_CRT_DISABLED (1 << 6) |
6222 | #define SFUSE_STRAP_DDIF_DETECTED (1 << 3) |
6223 | #define SFUSE_STRAP_DDIB_DETECTED (1 << 2) |
6224 | #define SFUSE_STRAP_DDIC_DETECTED (1 << 1) |
6225 | #define SFUSE_STRAP_DDID_DETECTED (1 << 0) |
6226 | |
6227 | #define WM_MISC _MMIO(0x45260) |
6228 | #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) |
6229 | |
6230 | #define WM_DBG _MMIO(0x45280) |
6231 | #define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0) |
6232 | #define WM_DBG_DISALLOW_MAXFIFO (1 << 1) |
6233 | #define WM_DBG_DISALLOW_SPRITE (1 << 2) |
6234 | |
6235 | #define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4) |
6236 | |
6237 | /* Plane CSC Registers */ |
6238 | #define _PLANE_CSC_RY_GY_1_A 0x70210 |
6239 | #define _PLANE_CSC_RY_GY_2_A 0x70310 |
6240 | |
6241 | #define _PLANE_CSC_RY_GY_1_B 0x71210 |
6242 | #define _PLANE_CSC_RY_GY_2_B 0x71310 |
6243 | |
6244 | #define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \ |
6245 | _PLANE_CSC_RY_GY_1_B) |
6246 | #define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, \ |
6247 | _PLANE_CSC_RY_GY_2_B) |
6248 | #define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \ |
6249 | _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \ |
6250 | _PLANE_CSC_RY_GY_2(pipe) + (index) * 4) |
6251 | |
6252 | #define _PLANE_CSC_PREOFF_HI_1_A 0x70228 |
6253 | #define _PLANE_CSC_PREOFF_HI_2_A 0x70328 |
6254 | |
6255 | #define _PLANE_CSC_PREOFF_HI_1_B 0x71228 |
6256 | #define _PLANE_CSC_PREOFF_HI_2_B 0x71328 |
6257 | |
6258 | #define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \ |
6259 | _PLANE_CSC_PREOFF_HI_1_B) |
6260 | #define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \ |
6261 | _PLANE_CSC_PREOFF_HI_2_B) |
6262 | #define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \ |
6263 | (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \ |
6264 | (index) * 4) |
6265 | |
6266 | #define _PLANE_CSC_POSTOFF_HI_1_A 0x70234 |
6267 | #define _PLANE_CSC_POSTOFF_HI_2_A 0x70334 |
6268 | |
6269 | #define _PLANE_CSC_POSTOFF_HI_1_B 0x71234 |
6270 | #define _PLANE_CSC_POSTOFF_HI_2_B 0x71334 |
6271 | |
6272 | #define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \ |
6273 | _PLANE_CSC_POSTOFF_HI_1_B) |
6274 | #define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \ |
6275 | _PLANE_CSC_POSTOFF_HI_2_B) |
6276 | #define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \ |
6277 | (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \ |
6278 | (index) * 4) |
6279 | |
6280 | /* Gen4+ Timestamp and Pipe Frame time stamp registers */ |
6281 | #define GEN4_TIMESTAMP _MMIO(0x2358) |
6282 | #define ILK_TIMESTAMP_HI _MMIO(0x70070) |
6283 | #define IVB_TIMESTAMP_CTR _MMIO(0x44070) |
6284 | |
6285 | #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074) |
6286 | #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0 |
6287 | #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff |
6288 | #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12 |
6289 | #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12) |
6290 | |
6291 | /* g4x+, except vlv/chv! */ |
6292 | #define _PIPE_FRMTMSTMP_A 0x70048 |
6293 | #define _PIPE_FRMTMSTMP_B 0x71048 |
6294 | #define PIPE_FRMTMSTMP(pipe) \ |
6295 | _MMIO_PIPE(pipe, _PIPE_FRMTMSTMP_A, _PIPE_FRMTMSTMP_B) |
6296 | |
6297 | /* g4x+, except vlv/chv! */ |
6298 | #define _PIPE_FLIPTMSTMP_A 0x7004C |
6299 | #define _PIPE_FLIPTMSTMP_B 0x7104C |
6300 | #define PIPE_FLIPTMSTMP(pipe) \ |
6301 | _MMIO_PIPE(pipe, _PIPE_FLIPTMSTMP_A, _PIPE_FLIPTMSTMP_B) |
6302 | |
6303 | /* tgl+ */ |
6304 | #define _PIPE_FLIPDONETMSTMP_A 0x70054 |
6305 | #define _PIPE_FLIPDONETMSTMP_B 0x71054 |
6306 | #define PIPE_FLIPDONETIMSTMP(pipe) \ |
6307 | _MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A, _PIPE_FLIPDONETMSTMP_B) |
6308 | |
6309 | #define _VLV_PIPE_MSA_MISC_A 0x70048 |
6310 | #define VLV_PIPE_MSA_MISC(pipe) \ |
6311 | _MMIO_PIPE2(pipe, _VLV_PIPE_MSA_MISC_A) |
6312 | #define VLV_MSA_MISC1_HW_ENABLE REG_BIT(31) |
6313 | #define VLV_MSA_MISC1_SW_S3D_MASK REG_GENMASK(2, 0) /* MSA MISC1 3:1 */ |
6314 | |
6315 | #define GGC _MMIO(0x108040) |
6316 | #define GMS_MASK REG_GENMASK(15, 8) |
6317 | #define GGMS_MASK REG_GENMASK(7, 6) |
6318 | |
6319 | #define GEN12_GSMBASE _MMIO(0x108100) |
6320 | #define GEN12_DSMBASE _MMIO(0x1080C0) |
6321 | #define GEN12_BDSM_MASK REG_GENMASK64(63, 20) |
6322 | |
6323 | #define XEHP_CLOCK_GATE_DIS _MMIO(0x101014) |
6324 | #define SGSI_SIDECLK_DIS REG_BIT(17) |
6325 | #define SGGI_DIS REG_BIT(15) |
6326 | #define SGR_DIS REG_BIT(13) |
6327 | |
6328 | #define _ICL_PHY_MISC_A 0x64C00 |
6329 | #define _ICL_PHY_MISC_B 0x64C04 |
6330 | #define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F" */ |
6331 | #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B) |
6332 | #define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \ |
6333 | ICL_PHY_MISC(port)) |
6334 | #define ICL_PHY_MISC_MUX_DDID (1 << 28) |
6335 | #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23) |
6336 | #define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20) |
6337 | |
6338 | #define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0) |
6339 | #define MODULAR_FIA_MASK (1 << 4) |
6340 | #define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6)) |
6341 | #define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5)) |
6342 | #define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8) |
6343 | #define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8)) |
6344 | #define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8)) |
6345 | |
6346 | #define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890) |
6347 | #define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx)) |
6348 | |
6349 | #define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894) |
6350 | #define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx)) |
6351 | |
6352 | #define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880) |
6353 | #define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4) |
6354 | #define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4)) |
6355 | #define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4)) |
6356 | |
6357 | #define _TCSS_DDI_STATUS_1 0x161500 |
6358 | #define _TCSS_DDI_STATUS_2 0x161504 |
6359 | #define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \ |
6360 | _TCSS_DDI_STATUS_1, \ |
6361 | _TCSS_DDI_STATUS_2)) |
6362 | #define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK REG_GENMASK(28, 25) |
6363 | #define TCSS_DDI_STATUS_READY REG_BIT(2) |
6364 | #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1) |
6365 | #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0) |
6366 | |
6367 | #define PRIMARY_SPI_TRIGGER _MMIO(0x102040) |
6368 | #define PRIMARY_SPI_ADDRESS _MMIO(0x102080) |
6369 | #define PRIMARY_SPI_REGIONID _MMIO(0x102084) |
6370 | #define SPI_STATIC_REGIONS _MMIO(0x102090) |
6371 | #define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0) |
6372 | #define OROM_OFFSET _MMIO(0x1020c0) |
6373 | #define OROM_OFFSET_MASK REG_GENMASK(20, 16) |
6374 | |
6375 | #define CLKREQ_POLICY _MMIO(0x101038) |
6376 | #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1) |
6377 | |
6378 | #define CLKGATE_DIS_MISC _MMIO(0x46534) |
6379 | #define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21) |
6380 | |
6381 | #define _MTL_CLKGATE_DIS_TRANS_A 0x604E8 |
6382 | #define _MTL_CLKGATE_DIS_TRANS_B 0x614E8 |
6383 | #define MTL_CLKGATE_DIS_TRANS(trans) _MMIO_TRANS2(trans, _MTL_CLKGATE_DIS_TRANS_A) |
6384 | #define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7) |
6385 | |
6386 | #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700) |
6387 | #define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8) |
6388 | #define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4) |
6389 | #define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0) |
6390 | |
6391 | #define MTL_MEM_SS_INFO_QGV_POINT_OFFSET 0x45710 |
6392 | #define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8) |
6393 | #define MTL_TRCD_MASK REG_GENMASK(31, 24) |
6394 | #define MTL_TRP_MASK REG_GENMASK(23, 16) |
6395 | #define MTL_DCLK_MASK REG_GENMASK(15, 0) |
6396 | |
6397 | #define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8 + 4) |
6398 | #define MTL_TRAS_MASK REG_GENMASK(16, 8) |
6399 | #define MTL_TRDPRE_MASK REG_GENMASK(7, 0) |
6400 | |
6401 | #define MTL_MEDIA_GSI_BASE 0x380000 |
6402 | |
6403 | #endif /* _I915_REG_H_ */ |
6404 | |