1#ifndef ADRENO_PM4_XML
2#define ADRENO_PM4_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
7http://gitlab.freedesktop.org/mesa/mesa/
8git clone https://gitlab.freedesktop.org/mesa/mesa.git
9
10The rules-ng-ng source files this header was generated from are:
11
12- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85856 bytes, from Fri Feb 23 13:07:00 2024)
13- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023)
14*/
15
16#ifdef __KERNEL__
17#include <linux/bug.h>
18#define assert(x) BUG_ON(!(x))
19#else
20#include <assert.h>
21#endif
22
23#ifdef __cplusplus
24#define __struct_cast(X)
25#else
26#define __struct_cast(X) (struct X)
27#endif
28
29enum vgt_event_type {
30 VS_DEALLOC = 0,
31 PS_DEALLOC = 1,
32 VS_DONE_TS = 2,
33 PS_DONE_TS = 3,
34 CACHE_FLUSH_TS = 4,
35 CONTEXT_DONE = 5,
36 CACHE_FLUSH = 6,
37 VIZQUERY_START = 7,
38 HLSQ_FLUSH = 7,
39 VIZQUERY_END = 8,
40 SC_WAIT_WC = 9,
41 WRITE_PRIMITIVE_COUNTS = 9,
42 START_PRIMITIVE_CTRS = 11,
43 STOP_PRIMITIVE_CTRS = 12,
44 RST_PIX_CNT = 13,
45 RST_VTX_CNT = 14,
46 TILE_FLUSH = 15,
47 STAT_EVENT = 16,
48 CACHE_FLUSH_AND_INV_TS_EVENT = 20,
49 ZPASS_DONE = 21,
50 CACHE_FLUSH_AND_INV_EVENT = 22,
51 RB_DONE_TS = 22,
52 PERFCOUNTER_START = 23,
53 PERFCOUNTER_STOP = 24,
54 VS_FETCH_DONE = 27,
55 FACENESS_FLUSH = 28,
56 WT_DONE_TS = 8,
57 START_FRAGMENT_CTRS = 13,
58 STOP_FRAGMENT_CTRS = 14,
59 START_COMPUTE_CTRS = 15,
60 STOP_COMPUTE_CTRS = 16,
61 FLUSH_SO_0 = 17,
62 FLUSH_SO_1 = 18,
63 FLUSH_SO_2 = 19,
64 FLUSH_SO_3 = 20,
65 PC_CCU_INVALIDATE_DEPTH = 24,
66 PC_CCU_INVALIDATE_COLOR = 25,
67 PC_CCU_RESOLVE_TS = 26,
68 PC_CCU_FLUSH_DEPTH_TS = 28,
69 PC_CCU_FLUSH_COLOR_TS = 29,
70 BLIT = 30,
71 LRZ_CLEAR = 37,
72 LRZ_FLUSH = 38,
73 BLIT_OP_FILL_2D = 39,
74 BLIT_OP_COPY_2D = 40,
75 UNK_40 = 40,
76 BLIT_OP_SCALE_2D = 42,
77 CONTEXT_DONE_2D = 43,
78 UNK_2C = 44,
79 UNK_2D = 45,
80 CACHE_INVALIDATE = 49,
81 LABEL = 63,
82 DUMMY_EVENT = 1,
83 CCU_INVALIDATE_DEPTH = 24,
84 CCU_INVALIDATE_COLOR = 25,
85 CCU_RESOLVE_CLEAN = 26,
86 CCU_FLUSH_DEPTH = 28,
87 CCU_FLUSH_COLOR = 29,
88 CCU_RESOLVE = 30,
89 CCU_END_RESOLVE_GROUP = 31,
90 CCU_CLEAN_DEPTH = 32,
91 CCU_CLEAN_COLOR = 33,
92 CACHE_RESET = 48,
93 CACHE_CLEAN = 49,
94 CACHE_FLUSH7 = 50,
95 CACHE_INVALIDATE7 = 51,
96};
97
98enum pc_di_primtype {
99 DI_PT_NONE = 0,
100 DI_PT_POINTLIST_PSIZE = 1,
101 DI_PT_LINELIST = 2,
102 DI_PT_LINESTRIP = 3,
103 DI_PT_TRILIST = 4,
104 DI_PT_TRIFAN = 5,
105 DI_PT_TRISTRIP = 6,
106 DI_PT_LINELOOP = 7,
107 DI_PT_RECTLIST = 8,
108 DI_PT_POINTLIST = 9,
109 DI_PT_LINE_ADJ = 10,
110 DI_PT_LINESTRIP_ADJ = 11,
111 DI_PT_TRI_ADJ = 12,
112 DI_PT_TRISTRIP_ADJ = 13,
113 DI_PT_PATCHES0 = 31,
114 DI_PT_PATCHES1 = 32,
115 DI_PT_PATCHES2 = 33,
116 DI_PT_PATCHES3 = 34,
117 DI_PT_PATCHES4 = 35,
118 DI_PT_PATCHES5 = 36,
119 DI_PT_PATCHES6 = 37,
120 DI_PT_PATCHES7 = 38,
121 DI_PT_PATCHES8 = 39,
122 DI_PT_PATCHES9 = 40,
123 DI_PT_PATCHES10 = 41,
124 DI_PT_PATCHES11 = 42,
125 DI_PT_PATCHES12 = 43,
126 DI_PT_PATCHES13 = 44,
127 DI_PT_PATCHES14 = 45,
128 DI_PT_PATCHES15 = 46,
129 DI_PT_PATCHES16 = 47,
130 DI_PT_PATCHES17 = 48,
131 DI_PT_PATCHES18 = 49,
132 DI_PT_PATCHES19 = 50,
133 DI_PT_PATCHES20 = 51,
134 DI_PT_PATCHES21 = 52,
135 DI_PT_PATCHES22 = 53,
136 DI_PT_PATCHES23 = 54,
137 DI_PT_PATCHES24 = 55,
138 DI_PT_PATCHES25 = 56,
139 DI_PT_PATCHES26 = 57,
140 DI_PT_PATCHES27 = 58,
141 DI_PT_PATCHES28 = 59,
142 DI_PT_PATCHES29 = 60,
143 DI_PT_PATCHES30 = 61,
144 DI_PT_PATCHES31 = 62,
145};
146
147enum pc_di_src_sel {
148 DI_SRC_SEL_DMA = 0,
149 DI_SRC_SEL_IMMEDIATE = 1,
150 DI_SRC_SEL_AUTO_INDEX = 2,
151 DI_SRC_SEL_AUTO_XFB = 3,
152};
153
154enum pc_di_face_cull_sel {
155 DI_FACE_CULL_NONE = 0,
156 DI_FACE_CULL_FETCH = 1,
157 DI_FACE_BACKFACE_CULL = 2,
158 DI_FACE_FRONTFACE_CULL = 3,
159};
160
161enum pc_di_index_size {
162 INDEX_SIZE_IGN = 0,
163 INDEX_SIZE_16_BIT = 0,
164 INDEX_SIZE_32_BIT = 1,
165 INDEX_SIZE_8_BIT = 2,
166 INDEX_SIZE_INVALID = 0,
167};
168
169enum pc_di_vis_cull_mode {
170 IGNORE_VISIBILITY = 0,
171 USE_VISIBILITY = 1,
172};
173
174enum adreno_pm4_packet_type {
175 CP_TYPE0_PKT = 0x00000000,
176 CP_TYPE1_PKT = 0x40000000,
177 CP_TYPE2_PKT = 0x80000000,
178 CP_TYPE3_PKT = 0xc0000000,
179 CP_TYPE4_PKT = 0x40000000,
180 CP_TYPE7_PKT = 0x70000000,
181};
182
183enum adreno_pm4_type3_packets {
184 CP_ME_INIT = 72,
185 CP_NOP = 16,
186 CP_PREEMPT_ENABLE = 28,
187 CP_PREEMPT_TOKEN = 30,
188 CP_INDIRECT_BUFFER = 63,
189 CP_INDIRECT_BUFFER_CHAIN = 87,
190 CP_INDIRECT_BUFFER_PFD = 55,
191 CP_WAIT_FOR_IDLE = 38,
192 CP_WAIT_REG_MEM = 60,
193 CP_WAIT_REG_EQ = 82,
194 CP_WAIT_REG_GTE = 83,
195 CP_WAIT_UNTIL_READ = 92,
196 CP_WAIT_IB_PFD_COMPLETE = 93,
197 CP_REG_RMW = 33,
198 CP_SET_BIN_DATA = 47,
199 CP_SET_BIN_DATA5 = 47,
200 CP_REG_TO_MEM = 62,
201 CP_MEM_WRITE = 61,
202 CP_MEM_WRITE_CNTR = 79,
203 CP_COND_EXEC = 68,
204 CP_COND_WRITE = 69,
205 CP_COND_WRITE5 = 69,
206 CP_EVENT_WRITE = 70,
207 CP_EVENT_WRITE7 = 70,
208 CP_EVENT_WRITE_SHD = 88,
209 CP_EVENT_WRITE_CFL = 89,
210 CP_EVENT_WRITE_ZPD = 91,
211 CP_RUN_OPENCL = 49,
212 CP_DRAW_INDX = 34,
213 CP_DRAW_INDX_2 = 54,
214 CP_DRAW_INDX_BIN = 52,
215 CP_DRAW_INDX_2_BIN = 53,
216 CP_VIZ_QUERY = 35,
217 CP_SET_STATE = 37,
218 CP_SET_CONSTANT = 45,
219 CP_IM_LOAD = 39,
220 CP_IM_LOAD_IMMEDIATE = 43,
221 CP_LOAD_CONSTANT_CONTEXT = 46,
222 CP_INVALIDATE_STATE = 59,
223 CP_SET_SHADER_BASES = 74,
224 CP_SET_BIN_MASK = 80,
225 CP_SET_BIN_SELECT = 81,
226 CP_CONTEXT_UPDATE = 94,
227 CP_INTERRUPT = 64,
228 CP_IM_STORE = 44,
229 CP_SET_DRAW_INIT_FLAGS = 75,
230 CP_SET_PROTECTED_MODE = 95,
231 CP_BOOTSTRAP_UCODE = 111,
232 CP_LOAD_STATE = 48,
233 CP_LOAD_STATE4 = 48,
234 CP_COND_INDIRECT_BUFFER_PFE = 58,
235 CP_COND_INDIRECT_BUFFER_PFD = 50,
236 CP_INDIRECT_BUFFER_PFE = 63,
237 CP_SET_BIN = 76,
238 CP_TEST_TWO_MEMS = 113,
239 CP_REG_WR_NO_CTXT = 120,
240 CP_RECORD_PFP_TIMESTAMP = 17,
241 CP_SET_SECURE_MODE = 102,
242 CP_WAIT_FOR_ME = 19,
243 CP_SET_DRAW_STATE = 67,
244 CP_DRAW_INDX_OFFSET = 56,
245 CP_DRAW_INDIRECT = 40,
246 CP_DRAW_INDX_INDIRECT = 41,
247 CP_DRAW_INDIRECT_MULTI = 42,
248 CP_DRAW_AUTO = 36,
249 CP_DRAW_PRED_ENABLE_GLOBAL = 25,
250 CP_DRAW_PRED_ENABLE_LOCAL = 26,
251 CP_DRAW_PRED_SET = 78,
252 CP_WIDE_REG_WRITE = 116,
253 CP_SCRATCH_TO_REG = 77,
254 CP_REG_TO_SCRATCH = 74,
255 CP_WAIT_MEM_WRITES = 18,
256 CP_COND_REG_EXEC = 71,
257 CP_MEM_TO_REG = 66,
258 CP_EXEC_CS_INDIRECT = 65,
259 CP_EXEC_CS = 51,
260 CP_PERFCOUNTER_ACTION = 80,
261 CP_SMMU_TABLE_UPDATE = 83,
262 CP_SET_MARKER = 101,
263 CP_SET_PSEUDO_REG = 86,
264 CP_CONTEXT_REG_BUNCH = 92,
265 CP_YIELD_ENABLE = 28,
266 CP_SKIP_IB2_ENABLE_GLOBAL = 29,
267 CP_SKIP_IB2_ENABLE_LOCAL = 35,
268 CP_SET_SUBDRAW_SIZE = 53,
269 CP_WHERE_AM_I = 98,
270 CP_SET_VISIBILITY_OVERRIDE = 100,
271 CP_PREEMPT_ENABLE_GLOBAL = 105,
272 CP_PREEMPT_ENABLE_LOCAL = 106,
273 CP_CONTEXT_SWITCH_YIELD = 107,
274 CP_SET_RENDER_MODE = 108,
275 CP_COMPUTE_CHECKPOINT = 110,
276 CP_MEM_TO_MEM = 115,
277 CP_BLIT = 44,
278 CP_REG_TEST = 57,
279 CP_SET_MODE = 99,
280 CP_LOAD_STATE6_GEOM = 50,
281 CP_LOAD_STATE6_FRAG = 52,
282 CP_LOAD_STATE6 = 54,
283 IN_IB_PREFETCH_END = 23,
284 IN_SUBBLK_PREFETCH = 31,
285 IN_INSTR_PREFETCH = 32,
286 IN_INSTR_MATCH = 71,
287 IN_CONST_PREFETCH = 73,
288 IN_INCR_UPDT_STATE = 85,
289 IN_INCR_UPDT_CONST = 86,
290 IN_INCR_UPDT_INSTR = 87,
291 PKT4 = 4,
292 IN_IB_END = 10,
293 IN_GMU_INTERRUPT = 11,
294 IN_PREEMPT = 15,
295 CP_SCRATCH_WRITE = 76,
296 CP_REG_TO_MEM_OFFSET_MEM = 116,
297 CP_REG_TO_MEM_OFFSET_REG = 114,
298 CP_WAIT_MEM_GTE = 20,
299 CP_WAIT_TWO_REGS = 112,
300 CP_MEMCPY = 117,
301 CP_SET_BIN_DATA5_OFFSET = 46,
302 CP_SET_UNK_BIN_DATA = 45,
303 CP_CONTEXT_SWITCH = 84,
304 CP_SET_CTXSWITCH_IB = 85,
305 CP_REG_WRITE = 109,
306 CP_START_BIN = 80,
307 CP_END_BIN = 81,
308 CP_PREEMPT_DISABLE = 108,
309 CP_WAIT_TIMESTAMP = 20,
310 CP_GLOBAL_TIMESTAMP = 21,
311 CP_LOCAL_TIMESTAMP = 22,
312 CP_THREAD_CONTROL = 23,
313 CP_RESOURCE_LIST = 24,
314 CP_BV_BR_COUNT_OPS = 27,
315 CP_MODIFY_TIMESTAMP = 28,
316 CP_CONTEXT_REG_BUNCH2 = 93,
317 CP_MEM_TO_SCRATCH_MEM = 73,
318 CP_FIXED_STRIDE_DRAW_TABLE = 127,
319 CP_RESET_CONTEXT_STATE = 31,
320};
321
322enum adreno_state_block {
323 SB_VERT_TEX = 0,
324 SB_VERT_MIPADDR = 1,
325 SB_FRAG_TEX = 2,
326 SB_FRAG_MIPADDR = 3,
327 SB_VERT_SHADER = 4,
328 SB_GEOM_SHADER = 5,
329 SB_FRAG_SHADER = 6,
330 SB_COMPUTE_SHADER = 7,
331};
332
333enum adreno_state_type {
334 ST_SHADER = 0,
335 ST_CONSTANTS = 1,
336};
337
338enum adreno_state_src {
339 SS_DIRECT = 0,
340 SS_INVALID_ALL_IC = 2,
341 SS_INVALID_PART_IC = 3,
342 SS_INDIRECT = 4,
343 SS_INDIRECT_TCM = 5,
344 SS_INDIRECT_STM = 6,
345};
346
347enum a4xx_state_block {
348 SB4_VS_TEX = 0,
349 SB4_HS_TEX = 1,
350 SB4_DS_TEX = 2,
351 SB4_GS_TEX = 3,
352 SB4_FS_TEX = 4,
353 SB4_CS_TEX = 5,
354 SB4_VS_SHADER = 8,
355 SB4_HS_SHADER = 9,
356 SB4_DS_SHADER = 10,
357 SB4_GS_SHADER = 11,
358 SB4_FS_SHADER = 12,
359 SB4_CS_SHADER = 13,
360 SB4_SSBO = 14,
361 SB4_CS_SSBO = 15,
362};
363
364enum a4xx_state_type {
365 ST4_SHADER = 0,
366 ST4_CONSTANTS = 1,
367 ST4_UBO = 2,
368};
369
370enum a4xx_state_src {
371 SS4_DIRECT = 0,
372 SS4_INDIRECT = 2,
373};
374
375enum a6xx_state_block {
376 SB6_VS_TEX = 0,
377 SB6_HS_TEX = 1,
378 SB6_DS_TEX = 2,
379 SB6_GS_TEX = 3,
380 SB6_FS_TEX = 4,
381 SB6_CS_TEX = 5,
382 SB6_VS_SHADER = 8,
383 SB6_HS_SHADER = 9,
384 SB6_DS_SHADER = 10,
385 SB6_GS_SHADER = 11,
386 SB6_FS_SHADER = 12,
387 SB6_CS_SHADER = 13,
388 SB6_IBO = 14,
389 SB6_CS_IBO = 15,
390};
391
392enum a6xx_state_type {
393 ST6_SHADER = 0,
394 ST6_CONSTANTS = 1,
395 ST6_UBO = 2,
396 ST6_IBO = 3,
397};
398
399enum a6xx_state_src {
400 SS6_DIRECT = 0,
401 SS6_BINDLESS = 1,
402 SS6_INDIRECT = 2,
403 SS6_UBO = 3,
404};
405
406enum a4xx_index_size {
407 INDEX4_SIZE_8_BIT = 0,
408 INDEX4_SIZE_16_BIT = 1,
409 INDEX4_SIZE_32_BIT = 2,
410};
411
412enum a6xx_patch_type {
413 TESS_QUADS = 0,
414 TESS_TRIANGLES = 1,
415 TESS_ISOLINES = 2,
416};
417
418enum a6xx_draw_indirect_opcode {
419 INDIRECT_OP_NORMAL = 2,
420 INDIRECT_OP_INDEXED = 4,
421 INDIRECT_OP_INDIRECT_COUNT = 6,
422 INDIRECT_OP_INDIRECT_COUNT_INDEXED = 7,
423};
424
425enum cp_draw_pred_src {
426 PRED_SRC_MEM = 5,
427};
428
429enum cp_draw_pred_test {
430 NE_0_PASS = 0,
431 EQ_0_PASS = 1,
432};
433
434enum cp_cond_function {
435 WRITE_ALWAYS = 0,
436 WRITE_LT = 1,
437 WRITE_LE = 2,
438 WRITE_EQ = 3,
439 WRITE_NE = 4,
440 WRITE_GE = 5,
441 WRITE_GT = 6,
442};
443
444enum poll_memory_type {
445 POLL_REGISTER = 0,
446 POLL_MEMORY = 1,
447 POLL_SCRATCH = 2,
448 POLL_ON_CHIP = 3,
449};
450
451enum render_mode_cmd {
452 BYPASS = 1,
453 BINNING = 2,
454 GMEM = 3,
455 BLIT2D = 5,
456 BLIT2DSCALE = 7,
457 END2D = 8,
458};
459
460enum event_write_src {
461 EV_WRITE_USER_32B = 0,
462 EV_WRITE_USER_64B = 1,
463 EV_WRITE_TIMESTAMP_SUM = 2,
464 EV_WRITE_ALWAYSON = 3,
465 EV_WRITE_REGS_CONTENT = 4,
466};
467
468enum event_write_dst {
469 EV_DST_RAM = 0,
470 EV_DST_ONCHIP = 1,
471};
472
473enum cp_blit_cmd {
474 BLIT_OP_FILL = 0,
475 BLIT_OP_COPY = 1,
476 BLIT_OP_SCALE = 3,
477};
478
479enum a6xx_marker {
480 RM6_BYPASS = 1,
481 RM6_BINNING = 2,
482 RM6_GMEM = 4,
483 RM6_ENDVIS = 5,
484 RM6_RESOLVE = 6,
485 RM6_YIELD = 7,
486 RM6_COMPUTE = 8,
487 RM6_BLIT2DSCALE = 12,
488 RM6_IB1LIST_START = 13,
489 RM6_IB1LIST_END = 14,
490 RM6_IFPC_ENABLE = 256,
491 RM6_IFPC_DISABLE = 257,
492};
493
494enum pseudo_reg {
495 SMMU_INFO = 0,
496 NON_SECURE_SAVE_ADDR = 1,
497 SECURE_SAVE_ADDR = 2,
498 NON_PRIV_SAVE_ADDR = 3,
499 COUNTER = 4,
500 DRAW_STRM_ADDRESS = 8,
501 DRAW_STRM_SIZE_ADDRESS = 9,
502 PRIM_STRM_ADDRESS = 10,
503 UNK_STRM_ADDRESS = 11,
504 UNK_STRM_SIZE_ADDRESS = 12,
505 BINDLESS_BASE_0_ADDR = 16,
506 BINDLESS_BASE_1_ADDR = 17,
507 BINDLESS_BASE_2_ADDR = 18,
508 BINDLESS_BASE_3_ADDR = 19,
509 BINDLESS_BASE_4_ADDR = 20,
510 BINDLESS_BASE_5_ADDR = 21,
511 BINDLESS_BASE_6_ADDR = 22,
512};
513
514enum source_type {
515 SOURCE_REG = 0,
516 SOURCE_SCRATCH_MEM = 1,
517};
518
519enum compare_mode {
520 PRED_TEST = 1,
521 REG_COMPARE = 2,
522 RENDER_MODE = 3,
523 REG_COMPARE_IMM = 4,
524 THREAD_MODE = 5,
525};
526
527enum ctxswitch_ib {
528 RESTORE_IB = 0,
529 YIELD_RESTORE_IB = 1,
530 SAVE_IB = 2,
531 RB_SAVE_IB = 3,
532};
533
534enum reg_tracker {
535 TRACK_CNTL_REG = 1,
536 TRACK_RENDER_CNTL = 2,
537 UNK_EVENT_WRITE = 4,
538 TRACK_LRZ = 8,
539};
540
541enum ts_wait_value_src {
542 TS_WAIT_GE_32B = 0,
543 TS_WAIT_GE_64B = 1,
544 TS_WAIT_GE_TIMESTAMP_SUM = 2,
545};
546
547enum ts_wait_type {
548 TS_WAIT_RAM = 0,
549 TS_WAIT_ONCHIP = 1,
550};
551
552enum pipe_count_op {
553 PIPE_CLEAR_BV_BR = 1,
554 PIPE_SET_BR_OFFSET = 2,
555 PIPE_BR_WAIT_FOR_BV = 3,
556 PIPE_BV_WAIT_FOR_BR = 4,
557};
558
559enum timestamp_op {
560 MODIFY_TIMESTAMP_CLEAR = 0,
561 MODIFY_TIMESTAMP_ADD_GLOBAL = 1,
562 MODIFY_TIMESTAMP_ADD_LOCAL = 2,
563};
564
565enum cp_thread {
566 CP_SET_THREAD_BR = 1,
567 CP_SET_THREAD_BV = 2,
568 CP_SET_THREAD_BOTH = 3,
569};
570
571#define REG_CP_LOAD_STATE_0 0x00000000
572#define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff
573#define CP_LOAD_STATE_0_DST_OFF__SHIFT 0
574static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
575{
576 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
577}
578#define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000
579#define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16
580static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
581{
582 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
583}
584#define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000
585#define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19
586static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
587{
588 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
589}
590#define CP_LOAD_STATE_0_NUM_UNIT__MASK 0xffc00000
591#define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22
592static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
593{
594 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
595}
596
597#define REG_CP_LOAD_STATE_1 0x00000001
598#define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003
599#define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0
600static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
601{
602 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
603}
604#define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc
605#define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2
606static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
607{
608 assert(!(val & 0x3));
609 return (((val >> 2)) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
610}
611
612#define REG_CP_LOAD_STATE4_0 0x00000000
613#define CP_LOAD_STATE4_0_DST_OFF__MASK 0x00003fff
614#define CP_LOAD_STATE4_0_DST_OFF__SHIFT 0
615static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val)
616{
617 return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK;
618}
619#define CP_LOAD_STATE4_0_STATE_SRC__MASK 0x00030000
620#define CP_LOAD_STATE4_0_STATE_SRC__SHIFT 16
621static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)
622{
623 return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK;
624}
625#define CP_LOAD_STATE4_0_STATE_BLOCK__MASK 0x003c0000
626#define CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT 18
627static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)
628{
629 return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK;
630}
631#define CP_LOAD_STATE4_0_NUM_UNIT__MASK 0xffc00000
632#define CP_LOAD_STATE4_0_NUM_UNIT__SHIFT 22
633static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)
634{
635 return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK;
636}
637
638#define REG_CP_LOAD_STATE4_1 0x00000001
639#define CP_LOAD_STATE4_1_STATE_TYPE__MASK 0x00000003
640#define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT 0
641static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)
642{
643 return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK;
644}
645#define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK 0xfffffffc
646#define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT 2
647static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)
648{
649 assert(!(val & 0x3));
650 return (((val >> 2)) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK;
651}
652
653#define REG_CP_LOAD_STATE4_2 0x00000002
654#define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
655#define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT 0
656static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)
657{
658 return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK;
659}
660
661#define REG_CP_LOAD_STATE6_0 0x00000000
662#define CP_LOAD_STATE6_0_DST_OFF__MASK 0x00003fff
663#define CP_LOAD_STATE6_0_DST_OFF__SHIFT 0
664static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val)
665{
666 return ((val) << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK;
667}
668#define CP_LOAD_STATE6_0_STATE_TYPE__MASK 0x0000c000
669#define CP_LOAD_STATE6_0_STATE_TYPE__SHIFT 14
670static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val)
671{
672 return ((val) << CP_LOAD_STATE6_0_STATE_TYPE__SHIFT) & CP_LOAD_STATE6_0_STATE_TYPE__MASK;
673}
674#define CP_LOAD_STATE6_0_STATE_SRC__MASK 0x00030000
675#define CP_LOAD_STATE6_0_STATE_SRC__SHIFT 16
676static inline uint32_t CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val)
677{
678 return ((val) << CP_LOAD_STATE6_0_STATE_SRC__SHIFT) & CP_LOAD_STATE6_0_STATE_SRC__MASK;
679}
680#define CP_LOAD_STATE6_0_STATE_BLOCK__MASK 0x003c0000
681#define CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT 18
682static inline uint32_t CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val)
683{
684 return ((val) << CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE6_0_STATE_BLOCK__MASK;
685}
686#define CP_LOAD_STATE6_0_NUM_UNIT__MASK 0xffc00000
687#define CP_LOAD_STATE6_0_NUM_UNIT__SHIFT 22
688static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val)
689{
690 return ((val) << CP_LOAD_STATE6_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE6_0_NUM_UNIT__MASK;
691}
692
693#define REG_CP_LOAD_STATE6_1 0x00000001
694#define CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK 0xfffffffc
695#define CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT 2
696static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val)
697{
698 assert(!(val & 0x3));
699 return (((val >> 2)) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK;
700}
701
702#define REG_CP_LOAD_STATE6_2 0x00000002
703#define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
704#define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT 0
705static inline uint32_t CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val)
706{
707 return ((val) << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK;
708}
709
710#define REG_CP_LOAD_STATE6_EXT_SRC_ADDR 0x00000001
711
712#define REG_CP_DRAW_INDX_0 0x00000000
713#define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff
714#define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0
715static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
716{
717 return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
718}
719
720#define REG_CP_DRAW_INDX_1 0x00000001
721#define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f
722#define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0
723static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
724{
725 return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
726}
727#define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0
728#define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6
729static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
730{
731 return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
732}
733#define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600
734#define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9
735static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
736{
737 return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
738}
739#define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800
740#define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11
741static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
742{
743 return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
744}
745#define CP_DRAW_INDX_1_NOT_EOP 0x00001000
746#define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000
747#define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
748#define CP_DRAW_INDX_1_NUM_INSTANCES__MASK 0xff000000
749#define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT 24
750static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)
751{
752 return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;
753}
754
755#define REG_CP_DRAW_INDX_2 0x00000002
756#define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff
757#define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0
758static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
759{
760 return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
761}
762
763#define REG_CP_DRAW_INDX_3 0x00000003
764#define CP_DRAW_INDX_3_INDX_BASE__MASK 0xffffffff
765#define CP_DRAW_INDX_3_INDX_BASE__SHIFT 0
766static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)
767{
768 return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;
769}
770
771#define REG_CP_DRAW_INDX_4 0x00000004
772#define CP_DRAW_INDX_4_INDX_SIZE__MASK 0xffffffff
773#define CP_DRAW_INDX_4_INDX_SIZE__SHIFT 0
774static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)
775{
776 return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;
777}
778
779#define REG_CP_DRAW_INDX_2_0 0x00000000
780#define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff
781#define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0
782static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
783{
784 return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
785}
786
787#define REG_CP_DRAW_INDX_2_1 0x00000001
788#define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f
789#define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0
790static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
791{
792 return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
793}
794#define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0
795#define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6
796static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
797{
798 return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
799}
800#define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600
801#define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9
802static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
803{
804 return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
805}
806#define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800
807#define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11
808static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
809{
810 return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
811}
812#define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000
813#define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000
814#define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
815#define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK 0xff000000
816#define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT 24
817static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)
818{
819 return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;
820}
821
822#define REG_CP_DRAW_INDX_2_2 0x00000002
823#define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff
824#define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0
825static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
826{
827 return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
828}
829
830#define REG_CP_DRAW_INDX_OFFSET_0 0x00000000
831#define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f
832#define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0
833static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
834{
835 return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
836}
837#define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0
838#define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6
839static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
840{
841 return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
842}
843#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000300
844#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8
845static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
846{
847 return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
848}
849#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00
850#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10
851static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
852{
853 return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
854}
855#define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK 0x00003000
856#define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT 12
857static inline uint32_t CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(enum a6xx_patch_type val)
858{
859 return ((val) << CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK;
860}
861#define CP_DRAW_INDX_OFFSET_0_GS_ENABLE 0x00010000
862#define CP_DRAW_INDX_OFFSET_0_TESS_ENABLE 0x00020000
863
864#define REG_CP_DRAW_INDX_OFFSET_1 0x00000001
865#define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff
866#define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT 0
867static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)
868{
869 return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK;
870}
871
872#define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
873#define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff
874#define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0
875static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
876{
877 return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
878}
879
880#define REG_CP_DRAW_INDX_OFFSET_3 0x00000003
881#define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK 0xffffffff
882#define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT 0
883static inline uint32_t CP_DRAW_INDX_OFFSET_3_FIRST_INDX(uint32_t val)
884{
885 return ((val) << CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT) & CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK;
886}
887
888#define REG_A5XX_CP_DRAW_INDX_OFFSET_4 0x00000004
889#define A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK 0xffffffff
890#define A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT 0
891static inline uint32_t A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(uint32_t val)
892{
893 return ((val) << A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK;
894}
895
896#define REG_A5XX_CP_DRAW_INDX_OFFSET_5 0x00000005
897#define A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK 0xffffffff
898#define A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT 0
899static inline uint32_t A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(uint32_t val)
900{
901 return ((val) << A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK;
902}
903
904#define REG_A5XX_CP_DRAW_INDX_OFFSET_INDX_BASE 0x00000004
905
906#define REG_A5XX_CP_DRAW_INDX_OFFSET_6 0x00000006
907#define A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK 0xffffffff
908#define A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT 0
909static inline uint32_t A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES(uint32_t val)
910{
911 return ((val) << A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK;
912}
913
914#define REG_CP_DRAW_INDX_OFFSET_4 0x00000004
915#define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff
916#define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0
917static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint64_t val)
918{
919 return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;
920}
921
922#define REG_CP_DRAW_INDX_OFFSET_5 0x00000005
923#define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK 0xffffffff
924#define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT 0
925static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
926{
927 return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;
928}
929
930#define REG_A4XX_CP_DRAW_INDIRECT_0 0x00000000
931#define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
932#define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT 0
933static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
934{
935 return ((val) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK;
936}
937#define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0
938#define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT 6
939static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
940{
941 return ((val) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK;
942}
943#define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK 0x00000300
944#define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT 8
945static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
946{
947 return ((val) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK;
948}
949#define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00
950#define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT 10
951static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
952{
953 return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK;
954}
955#define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK 0x00003000
956#define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT 12
957static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)
958{
959 return ((val) << A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK;
960}
961#define A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE 0x00010000
962#define A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE 0x00020000
963
964#define REG_A4XX_CP_DRAW_INDIRECT_1 0x00000001
965#define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK 0xffffffff
966#define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT 0
967static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val)
968{
969 return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK;
970}
971
972#define REG_A5XX_CP_DRAW_INDIRECT_1 0x00000001
973#define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK 0xffffffff
974#define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT 0
975static inline uint32_t A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO(uint32_t val)
976{
977 return ((val) << A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK;
978}
979
980#define REG_A5XX_CP_DRAW_INDIRECT_2 0x00000002
981#define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK 0xffffffff
982#define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT 0
983static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val)
984{
985 return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK;
986}
987
988#define REG_A5XX_CP_DRAW_INDIRECT_INDIRECT 0x00000001
989
990#define REG_A4XX_CP_DRAW_INDX_INDIRECT_0 0x00000000
991#define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
992#define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT 0
993static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
994{
995 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK;
996}
997#define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0
998#define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT 6
999static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
1000{
1001 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK;
1002}
1003#define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK 0x00000300
1004#define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT 8
1005static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
1006{
1007 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK;
1008}
1009#define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00
1010#define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT 10
1011static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
1012{
1013 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK;
1014}
1015#define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK 0x00003000
1016#define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT 12
1017static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)
1018{
1019 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK;
1020}
1021#define A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE 0x00010000
1022#define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE 0x00020000
1023
1024#define REG_A4XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
1025#define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK 0xffffffff
1026#define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT 0
1027static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val)
1028{
1029 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK;
1030}
1031
1032#define REG_A4XX_CP_DRAW_INDX_INDIRECT_2 0x00000002
1033#define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK 0xffffffff
1034#define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT 0
1035static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val)
1036{
1037 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK;
1038}
1039
1040#define REG_A4XX_CP_DRAW_INDX_INDIRECT_3 0x00000003
1041#define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK 0xffffffff
1042#define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT 0
1043static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val)
1044{
1045 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK;
1046}
1047
1048#define REG_A5XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
1049#define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK 0xffffffff
1050#define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT 0
1051static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val)
1052{
1053 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK;
1054}
1055
1056#define REG_A5XX_CP_DRAW_INDX_INDIRECT_2 0x00000002
1057#define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK 0xffffffff
1058#define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT 0
1059static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val)
1060{
1061 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK;
1062}
1063
1064#define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDX_BASE 0x00000001
1065
1066#define REG_A5XX_CP_DRAW_INDX_INDIRECT_3 0x00000003
1067#define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK 0xffffffff
1068#define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT 0
1069static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val)
1070{
1071 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK;
1072}
1073
1074#define REG_A5XX_CP_DRAW_INDX_INDIRECT_4 0x00000004
1075#define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK 0xffffffff
1076#define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT 0
1077static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val)
1078{
1079 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK;
1080}
1081
1082#define REG_A5XX_CP_DRAW_INDX_INDIRECT_5 0x00000005
1083#define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK 0xffffffff
1084#define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT 0
1085static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val)
1086{
1087 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK;
1088}
1089
1090#define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDIRECT 0x00000004
1091
1092#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_0 0x00000000
1093#define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK 0x0000003f
1094#define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT 0
1095static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE(enum pc_di_primtype val)
1096{
1097 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK;
1098}
1099#define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK 0x000000c0
1100#define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT 6
1101static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT(enum pc_di_src_sel val)
1102{
1103 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK;
1104}
1105#define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK 0x00000300
1106#define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT 8
1107static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL(enum pc_di_vis_cull_mode val)
1108{
1109 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK;
1110}
1111#define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK 0x00000c00
1112#define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT 10
1113static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE(enum a4xx_index_size val)
1114{
1115 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK;
1116}
1117#define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK 0x00003000
1118#define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT 12
1119static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE(enum a6xx_patch_type val)
1120{
1121 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK;
1122}
1123#define A6XX_CP_DRAW_INDIRECT_MULTI_0_GS_ENABLE 0x00010000
1124#define A6XX_CP_DRAW_INDIRECT_MULTI_0_TESS_ENABLE 0x00020000
1125
1126#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_1 0x00000001
1127#define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK 0x0000000f
1128#define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT 0
1129static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(enum a6xx_draw_indirect_opcode val)
1130{
1131 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK;
1132}
1133#define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK 0x003fff00
1134#define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT 8
1135static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(uint32_t val)
1136{
1137 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK;
1138}
1139
1140#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT 0x00000002
1141
1142#define REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000003
1143
1144#define REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000005
1145
1146#define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX 0x00000003
1147
1148#define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES 0x00000005
1149
1150#define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000006
1151
1152#define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000008
1153
1154#define REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000003
1155
1156#define REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT 0x00000005
1157
1158#define REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000007
1159
1160#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX 0x00000003
1161
1162#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES 0x00000005
1163
1164#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000006
1165
1166#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT 0x00000008
1167
1168#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE 0x0000000a
1169
1170#define REG_CP_DRAW_AUTO_0 0x00000000
1171#define CP_DRAW_AUTO_0_PRIM_TYPE__MASK 0x0000003f
1172#define CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT 0
1173static inline uint32_t CP_DRAW_AUTO_0_PRIM_TYPE(enum pc_di_primtype val)
1174{
1175 return ((val) << CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT) & CP_DRAW_AUTO_0_PRIM_TYPE__MASK;
1176}
1177#define CP_DRAW_AUTO_0_SOURCE_SELECT__MASK 0x000000c0
1178#define CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT 6
1179static inline uint32_t CP_DRAW_AUTO_0_SOURCE_SELECT(enum pc_di_src_sel val)
1180{
1181 return ((val) << CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT) & CP_DRAW_AUTO_0_SOURCE_SELECT__MASK;
1182}
1183#define CP_DRAW_AUTO_0_VIS_CULL__MASK 0x00000300
1184#define CP_DRAW_AUTO_0_VIS_CULL__SHIFT 8
1185static inline uint32_t CP_DRAW_AUTO_0_VIS_CULL(enum pc_di_vis_cull_mode val)
1186{
1187 return ((val) << CP_DRAW_AUTO_0_VIS_CULL__SHIFT) & CP_DRAW_AUTO_0_VIS_CULL__MASK;
1188}
1189#define CP_DRAW_AUTO_0_INDEX_SIZE__MASK 0x00000c00
1190#define CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT 10
1191static inline uint32_t CP_DRAW_AUTO_0_INDEX_SIZE(enum a4xx_index_size val)
1192{
1193 return ((val) << CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT) & CP_DRAW_AUTO_0_INDEX_SIZE__MASK;
1194}
1195#define CP_DRAW_AUTO_0_PATCH_TYPE__MASK 0x00003000
1196#define CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT 12
1197static inline uint32_t CP_DRAW_AUTO_0_PATCH_TYPE(enum a6xx_patch_type val)
1198{
1199 return ((val) << CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT) & CP_DRAW_AUTO_0_PATCH_TYPE__MASK;
1200}
1201#define CP_DRAW_AUTO_0_GS_ENABLE 0x00010000
1202#define CP_DRAW_AUTO_0_TESS_ENABLE 0x00020000
1203
1204#define REG_CP_DRAW_AUTO_1 0x00000001
1205#define CP_DRAW_AUTO_1_NUM_INSTANCES__MASK 0xffffffff
1206#define CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT 0
1207static inline uint32_t CP_DRAW_AUTO_1_NUM_INSTANCES(uint32_t val)
1208{
1209 return ((val) << CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT) & CP_DRAW_AUTO_1_NUM_INSTANCES__MASK;
1210}
1211
1212#define REG_CP_DRAW_AUTO_NUM_VERTICES_BASE 0x00000002
1213
1214#define REG_CP_DRAW_AUTO_4 0x00000004
1215#define CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK 0xffffffff
1216#define CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT 0
1217static inline uint32_t CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET(uint32_t val)
1218{
1219 return ((val) << CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT) & CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK;
1220}
1221
1222#define REG_CP_DRAW_AUTO_5 0x00000005
1223#define CP_DRAW_AUTO_5_STRIDE__MASK 0xffffffff
1224#define CP_DRAW_AUTO_5_STRIDE__SHIFT 0
1225static inline uint32_t CP_DRAW_AUTO_5_STRIDE(uint32_t val)
1226{
1227 return ((val) << CP_DRAW_AUTO_5_STRIDE__SHIFT) & CP_DRAW_AUTO_5_STRIDE__MASK;
1228}
1229
1230#define REG_CP_DRAW_PRED_ENABLE_GLOBAL_0 0x00000000
1231#define CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE 0x00000001
1232
1233#define REG_CP_DRAW_PRED_ENABLE_LOCAL_0 0x00000000
1234#define CP_DRAW_PRED_ENABLE_LOCAL_0_ENABLE 0x00000001
1235
1236#define REG_CP_DRAW_PRED_SET_0 0x00000000
1237#define CP_DRAW_PRED_SET_0_SRC__MASK 0x000000f0
1238#define CP_DRAW_PRED_SET_0_SRC__SHIFT 4
1239static inline uint32_t CP_DRAW_PRED_SET_0_SRC(enum cp_draw_pred_src val)
1240{
1241 return ((val) << CP_DRAW_PRED_SET_0_SRC__SHIFT) & CP_DRAW_PRED_SET_0_SRC__MASK;
1242}
1243#define CP_DRAW_PRED_SET_0_TEST__MASK 0x00000100
1244#define CP_DRAW_PRED_SET_0_TEST__SHIFT 8
1245static inline uint32_t CP_DRAW_PRED_SET_0_TEST(enum cp_draw_pred_test val)
1246{
1247 return ((val) << CP_DRAW_PRED_SET_0_TEST__SHIFT) & CP_DRAW_PRED_SET_0_TEST__MASK;
1248}
1249
1250#define REG_CP_DRAW_PRED_SET_MEM_ADDR 0x00000001
1251
1252#define REG_CP_SET_DRAW_STATE_(i0) (0x00000000 + 0x3*(i0))
1253
1254static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
1255#define CP_SET_DRAW_STATE__0_COUNT__MASK 0x0000ffff
1256#define CP_SET_DRAW_STATE__0_COUNT__SHIFT 0
1257static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val)
1258{
1259 return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK;
1260}
1261#define CP_SET_DRAW_STATE__0_DIRTY 0x00010000
1262#define CP_SET_DRAW_STATE__0_DISABLE 0x00020000
1263#define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS 0x00040000
1264#define CP_SET_DRAW_STATE__0_LOAD_IMMED 0x00080000
1265#define CP_SET_DRAW_STATE__0_BINNING 0x00100000
1266#define CP_SET_DRAW_STATE__0_GMEM 0x00200000
1267#define CP_SET_DRAW_STATE__0_SYSMEM 0x00400000
1268#define CP_SET_DRAW_STATE__0_GROUP_ID__MASK 0x1f000000
1269#define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT 24
1270static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)
1271{
1272 return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK;
1273}
1274
1275static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
1276#define CP_SET_DRAW_STATE__1_ADDR_LO__MASK 0xffffffff
1277#define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT 0
1278static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)
1279{
1280 return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK;
1281}
1282
1283static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
1284#define CP_SET_DRAW_STATE__2_ADDR_HI__MASK 0xffffffff
1285#define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT 0
1286static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)
1287{
1288 return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK;
1289}
1290
1291#define REG_CP_SET_BIN_0 0x00000000
1292
1293#define REG_CP_SET_BIN_1 0x00000001
1294#define CP_SET_BIN_1_X1__MASK 0x0000ffff
1295#define CP_SET_BIN_1_X1__SHIFT 0
1296static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
1297{
1298 return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
1299}
1300#define CP_SET_BIN_1_Y1__MASK 0xffff0000
1301#define CP_SET_BIN_1_Y1__SHIFT 16
1302static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
1303{
1304 return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
1305}
1306
1307#define REG_CP_SET_BIN_2 0x00000002
1308#define CP_SET_BIN_2_X2__MASK 0x0000ffff
1309#define CP_SET_BIN_2_X2__SHIFT 0
1310static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
1311{
1312 return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
1313}
1314#define CP_SET_BIN_2_Y2__MASK 0xffff0000
1315#define CP_SET_BIN_2_Y2__SHIFT 16
1316static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
1317{
1318 return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
1319}
1320
1321#define REG_CP_SET_BIN_DATA_0 0x00000000
1322#define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff
1323#define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0
1324static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
1325{
1326 return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
1327}
1328
1329#define REG_CP_SET_BIN_DATA_1 0x00000001
1330#define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff
1331#define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0
1332static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
1333{
1334 return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
1335}
1336
1337#define REG_CP_SET_BIN_DATA5_0 0x00000000
1338#define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK 0x003f0000
1339#define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT 16
1340static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)
1341{
1342 return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK;
1343}
1344#define CP_SET_BIN_DATA5_0_VSC_N__MASK 0x07c00000
1345#define CP_SET_BIN_DATA5_0_VSC_N__SHIFT 22
1346static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)
1347{
1348 return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK;
1349}
1350
1351#define REG_CP_SET_BIN_DATA5_1 0x00000001
1352#define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK 0xffffffff
1353#define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT 0
1354static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)
1355{
1356 return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK;
1357}
1358
1359#define REG_CP_SET_BIN_DATA5_2 0x00000002
1360#define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK 0xffffffff
1361#define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT 0
1362static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)
1363{
1364 return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK;
1365}
1366
1367#define REG_CP_SET_BIN_DATA5_3 0x00000003
1368#define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK 0xffffffff
1369#define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT 0
1370static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)
1371{
1372 return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK;
1373}
1374
1375#define REG_CP_SET_BIN_DATA5_4 0x00000004
1376#define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK 0xffffffff
1377#define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT 0
1378static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)
1379{
1380 return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK;
1381}
1382
1383#define REG_CP_SET_BIN_DATA5_5 0x00000005
1384#define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK 0xffffffff
1385#define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT 0
1386static inline uint32_t CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO(uint32_t val)
1387{
1388 return ((val) << CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK;
1389}
1390
1391#define REG_CP_SET_BIN_DATA5_6 0x00000006
1392#define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK 0xffffffff
1393#define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT 0
1394static inline uint32_t CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI(uint32_t val)
1395{
1396 return ((val) << CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT) & CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK;
1397}
1398
1399#define REG_CP_SET_BIN_DATA5_7 0x00000007
1400
1401#define REG_CP_SET_BIN_DATA5_9 0x00000009
1402
1403#define REG_CP_SET_BIN_DATA5_OFFSET_0 0x00000000
1404#define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK 0x003f0000
1405#define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT 16
1406static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE(uint32_t val)
1407{
1408 return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK;
1409}
1410#define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK 0x07c00000
1411#define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT 22
1412static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_N(uint32_t val)
1413{
1414 return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK;
1415}
1416
1417#define REG_CP_SET_BIN_DATA5_OFFSET_1 0x00000001
1418#define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK 0xffffffff
1419#define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT 0
1420static inline uint32_t CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET(uint32_t val)
1421{
1422 return ((val) << CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK;
1423}
1424
1425#define REG_CP_SET_BIN_DATA5_OFFSET_2 0x00000002
1426#define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK 0xffffffff
1427#define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT 0
1428static inline uint32_t CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET(uint32_t val)
1429{
1430 return ((val) << CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK;
1431}
1432
1433#define REG_CP_SET_BIN_DATA5_OFFSET_3 0x00000003
1434#define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK 0xffffffff
1435#define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT 0
1436static inline uint32_t CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET(uint32_t val)
1437{
1438 return ((val) << CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK;
1439}
1440
1441#define REG_CP_REG_RMW_0 0x00000000
1442#define CP_REG_RMW_0_DST_REG__MASK 0x0003ffff
1443#define CP_REG_RMW_0_DST_REG__SHIFT 0
1444static inline uint32_t CP_REG_RMW_0_DST_REG(uint32_t val)
1445{
1446 return ((val) << CP_REG_RMW_0_DST_REG__SHIFT) & CP_REG_RMW_0_DST_REG__MASK;
1447}
1448#define CP_REG_RMW_0_ROTATE__MASK 0x1f000000
1449#define CP_REG_RMW_0_ROTATE__SHIFT 24
1450static inline uint32_t CP_REG_RMW_0_ROTATE(uint32_t val)
1451{
1452 return ((val) << CP_REG_RMW_0_ROTATE__SHIFT) & CP_REG_RMW_0_ROTATE__MASK;
1453}
1454#define CP_REG_RMW_0_SRC1_ADD 0x20000000
1455#define CP_REG_RMW_0_SRC1_IS_REG 0x40000000
1456#define CP_REG_RMW_0_SRC0_IS_REG 0x80000000
1457
1458#define REG_CP_REG_RMW_1 0x00000001
1459#define CP_REG_RMW_1_SRC0__MASK 0xffffffff
1460#define CP_REG_RMW_1_SRC0__SHIFT 0
1461static inline uint32_t CP_REG_RMW_1_SRC0(uint32_t val)
1462{
1463 return ((val) << CP_REG_RMW_1_SRC0__SHIFT) & CP_REG_RMW_1_SRC0__MASK;
1464}
1465
1466#define REG_CP_REG_RMW_2 0x00000002
1467#define CP_REG_RMW_2_SRC1__MASK 0xffffffff
1468#define CP_REG_RMW_2_SRC1__SHIFT 0
1469static inline uint32_t CP_REG_RMW_2_SRC1(uint32_t val)
1470{
1471 return ((val) << CP_REG_RMW_2_SRC1__SHIFT) & CP_REG_RMW_2_SRC1__MASK;
1472}
1473
1474#define REG_CP_REG_TO_MEM_0 0x00000000
1475#define CP_REG_TO_MEM_0_REG__MASK 0x0003ffff
1476#define CP_REG_TO_MEM_0_REG__SHIFT 0
1477static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)
1478{
1479 return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;
1480}
1481#define CP_REG_TO_MEM_0_CNT__MASK 0x3ffc0000
1482#define CP_REG_TO_MEM_0_CNT__SHIFT 18
1483static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)
1484{
1485 return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;
1486}
1487#define CP_REG_TO_MEM_0_64B 0x40000000
1488#define CP_REG_TO_MEM_0_ACCUMULATE 0x80000000
1489
1490#define REG_CP_REG_TO_MEM_1 0x00000001
1491#define CP_REG_TO_MEM_1_DEST__MASK 0xffffffff
1492#define CP_REG_TO_MEM_1_DEST__SHIFT 0
1493static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
1494{
1495 return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
1496}
1497
1498#define REG_CP_REG_TO_MEM_2 0x00000002
1499#define CP_REG_TO_MEM_2_DEST_HI__MASK 0xffffffff
1500#define CP_REG_TO_MEM_2_DEST_HI__SHIFT 0
1501static inline uint32_t CP_REG_TO_MEM_2_DEST_HI(uint32_t val)
1502{
1503 return ((val) << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK;
1504}
1505
1506#define REG_CP_REG_TO_MEM_OFFSET_REG_0 0x00000000
1507#define CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK 0x0003ffff
1508#define CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT 0
1509static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_REG(uint32_t val)
1510{
1511 return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK;
1512}
1513#define CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK 0x3ffc0000
1514#define CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT 18
1515static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_CNT(uint32_t val)
1516{
1517 return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK;
1518}
1519#define CP_REG_TO_MEM_OFFSET_REG_0_64B 0x40000000
1520#define CP_REG_TO_MEM_OFFSET_REG_0_ACCUMULATE 0x80000000
1521
1522#define REG_CP_REG_TO_MEM_OFFSET_REG_1 0x00000001
1523#define CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK 0xffffffff
1524#define CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT 0
1525static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_1_DEST(uint32_t val)
1526{
1527 return ((val) << CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK;
1528}
1529
1530#define REG_CP_REG_TO_MEM_OFFSET_REG_2 0x00000002
1531#define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK 0xffffffff
1532#define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT 0
1533static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI(uint32_t val)
1534{
1535 return ((val) << CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK;
1536}
1537
1538#define REG_CP_REG_TO_MEM_OFFSET_REG_3 0x00000003
1539#define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK 0x0003ffff
1540#define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT 0
1541static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0(uint32_t val)
1542{
1543 return ((val) << CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK;
1544}
1545#define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0_SCRATCH 0x00080000
1546
1547#define REG_CP_REG_TO_MEM_OFFSET_MEM_0 0x00000000
1548#define CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK 0x0003ffff
1549#define CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT 0
1550static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_REG(uint32_t val)
1551{
1552 return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK;
1553}
1554#define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK 0x3ffc0000
1555#define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT 18
1556static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_CNT(uint32_t val)
1557{
1558 return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK;
1559}
1560#define CP_REG_TO_MEM_OFFSET_MEM_0_64B 0x40000000
1561#define CP_REG_TO_MEM_OFFSET_MEM_0_ACCUMULATE 0x80000000
1562
1563#define REG_CP_REG_TO_MEM_OFFSET_MEM_1 0x00000001
1564#define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK 0xffffffff
1565#define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT 0
1566static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_1_DEST(uint32_t val)
1567{
1568 return ((val) << CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK;
1569}
1570
1571#define REG_CP_REG_TO_MEM_OFFSET_MEM_2 0x00000002
1572#define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK 0xffffffff
1573#define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT 0
1574static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI(uint32_t val)
1575{
1576 return ((val) << CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK;
1577}
1578
1579#define REG_CP_REG_TO_MEM_OFFSET_MEM_3 0x00000003
1580#define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK 0xffffffff
1581#define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT 0
1582static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO(uint32_t val)
1583{
1584 return ((val) << CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK;
1585}
1586
1587#define REG_CP_REG_TO_MEM_OFFSET_MEM_4 0x00000004
1588#define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK 0xffffffff
1589#define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT 0
1590static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI(uint32_t val)
1591{
1592 return ((val) << CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK;
1593}
1594
1595#define REG_CP_MEM_TO_REG_0 0x00000000
1596#define CP_MEM_TO_REG_0_REG__MASK 0x0003ffff
1597#define CP_MEM_TO_REG_0_REG__SHIFT 0
1598static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val)
1599{
1600 return ((val) << CP_MEM_TO_REG_0_REG__SHIFT) & CP_MEM_TO_REG_0_REG__MASK;
1601}
1602#define CP_MEM_TO_REG_0_CNT__MASK 0x3ff80000
1603#define CP_MEM_TO_REG_0_CNT__SHIFT 19
1604static inline uint32_t CP_MEM_TO_REG_0_CNT(uint32_t val)
1605{
1606 return ((val) << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK;
1607}
1608#define CP_MEM_TO_REG_0_SHIFT_BY_2 0x40000000
1609#define CP_MEM_TO_REG_0_UNK31 0x80000000
1610
1611#define REG_CP_MEM_TO_REG_1 0x00000001
1612#define CP_MEM_TO_REG_1_SRC__MASK 0xffffffff
1613#define CP_MEM_TO_REG_1_SRC__SHIFT 0
1614static inline uint32_t CP_MEM_TO_REG_1_SRC(uint32_t val)
1615{
1616 return ((val) << CP_MEM_TO_REG_1_SRC__SHIFT) & CP_MEM_TO_REG_1_SRC__MASK;
1617}
1618
1619#define REG_CP_MEM_TO_REG_2 0x00000002
1620#define CP_MEM_TO_REG_2_SRC_HI__MASK 0xffffffff
1621#define CP_MEM_TO_REG_2_SRC_HI__SHIFT 0
1622static inline uint32_t CP_MEM_TO_REG_2_SRC_HI(uint32_t val)
1623{
1624 return ((val) << CP_MEM_TO_REG_2_SRC_HI__SHIFT) & CP_MEM_TO_REG_2_SRC_HI__MASK;
1625}
1626
1627#define REG_CP_MEM_TO_MEM_0 0x00000000
1628#define CP_MEM_TO_MEM_0_NEG_A 0x00000001
1629#define CP_MEM_TO_MEM_0_NEG_B 0x00000002
1630#define CP_MEM_TO_MEM_0_NEG_C 0x00000004
1631#define CP_MEM_TO_MEM_0_DOUBLE 0x20000000
1632#define CP_MEM_TO_MEM_0_WAIT_FOR_MEM_WRITES 0x40000000
1633#define CP_MEM_TO_MEM_0_UNK31 0x80000000
1634
1635#define REG_CP_MEMCPY_0 0x00000000
1636#define CP_MEMCPY_0_DWORDS__MASK 0xffffffff
1637#define CP_MEMCPY_0_DWORDS__SHIFT 0
1638static inline uint32_t CP_MEMCPY_0_DWORDS(uint32_t val)
1639{
1640 return ((val) << CP_MEMCPY_0_DWORDS__SHIFT) & CP_MEMCPY_0_DWORDS__MASK;
1641}
1642
1643#define REG_CP_MEMCPY_1 0x00000001
1644#define CP_MEMCPY_1_SRC_LO__MASK 0xffffffff
1645#define CP_MEMCPY_1_SRC_LO__SHIFT 0
1646static inline uint32_t CP_MEMCPY_1_SRC_LO(uint32_t val)
1647{
1648 return ((val) << CP_MEMCPY_1_SRC_LO__SHIFT) & CP_MEMCPY_1_SRC_LO__MASK;
1649}
1650
1651#define REG_CP_MEMCPY_2 0x00000002
1652#define CP_MEMCPY_2_SRC_HI__MASK 0xffffffff
1653#define CP_MEMCPY_2_SRC_HI__SHIFT 0
1654static inline uint32_t CP_MEMCPY_2_SRC_HI(uint32_t val)
1655{
1656 return ((val) << CP_MEMCPY_2_SRC_HI__SHIFT) & CP_MEMCPY_2_SRC_HI__MASK;
1657}
1658
1659#define REG_CP_MEMCPY_3 0x00000003
1660#define CP_MEMCPY_3_DST_LO__MASK 0xffffffff
1661#define CP_MEMCPY_3_DST_LO__SHIFT 0
1662static inline uint32_t CP_MEMCPY_3_DST_LO(uint32_t val)
1663{
1664 return ((val) << CP_MEMCPY_3_DST_LO__SHIFT) & CP_MEMCPY_3_DST_LO__MASK;
1665}
1666
1667#define REG_CP_MEMCPY_4 0x00000004
1668#define CP_MEMCPY_4_DST_HI__MASK 0xffffffff
1669#define CP_MEMCPY_4_DST_HI__SHIFT 0
1670static inline uint32_t CP_MEMCPY_4_DST_HI(uint32_t val)
1671{
1672 return ((val) << CP_MEMCPY_4_DST_HI__SHIFT) & CP_MEMCPY_4_DST_HI__MASK;
1673}
1674
1675#define REG_CP_REG_TO_SCRATCH_0 0x00000000
1676#define CP_REG_TO_SCRATCH_0_REG__MASK 0x0003ffff
1677#define CP_REG_TO_SCRATCH_0_REG__SHIFT 0
1678static inline uint32_t CP_REG_TO_SCRATCH_0_REG(uint32_t val)
1679{
1680 return ((val) << CP_REG_TO_SCRATCH_0_REG__SHIFT) & CP_REG_TO_SCRATCH_0_REG__MASK;
1681}
1682#define CP_REG_TO_SCRATCH_0_SCRATCH__MASK 0x00700000
1683#define CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT 20
1684static inline uint32_t CP_REG_TO_SCRATCH_0_SCRATCH(uint32_t val)
1685{
1686 return ((val) << CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT) & CP_REG_TO_SCRATCH_0_SCRATCH__MASK;
1687}
1688#define CP_REG_TO_SCRATCH_0_CNT__MASK 0x07000000
1689#define CP_REG_TO_SCRATCH_0_CNT__SHIFT 24
1690static inline uint32_t CP_REG_TO_SCRATCH_0_CNT(uint32_t val)
1691{
1692 return ((val) << CP_REG_TO_SCRATCH_0_CNT__SHIFT) & CP_REG_TO_SCRATCH_0_CNT__MASK;
1693}
1694
1695#define REG_CP_SCRATCH_TO_REG_0 0x00000000
1696#define CP_SCRATCH_TO_REG_0_REG__MASK 0x0003ffff
1697#define CP_SCRATCH_TO_REG_0_REG__SHIFT 0
1698static inline uint32_t CP_SCRATCH_TO_REG_0_REG(uint32_t val)
1699{
1700 return ((val) << CP_SCRATCH_TO_REG_0_REG__SHIFT) & CP_SCRATCH_TO_REG_0_REG__MASK;
1701}
1702#define CP_SCRATCH_TO_REG_0_UNK18 0x00040000
1703#define CP_SCRATCH_TO_REG_0_SCRATCH__MASK 0x00700000
1704#define CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT 20
1705static inline uint32_t CP_SCRATCH_TO_REG_0_SCRATCH(uint32_t val)
1706{
1707 return ((val) << CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT) & CP_SCRATCH_TO_REG_0_SCRATCH__MASK;
1708}
1709#define CP_SCRATCH_TO_REG_0_CNT__MASK 0x07000000
1710#define CP_SCRATCH_TO_REG_0_CNT__SHIFT 24
1711static inline uint32_t CP_SCRATCH_TO_REG_0_CNT(uint32_t val)
1712{
1713 return ((val) << CP_SCRATCH_TO_REG_0_CNT__SHIFT) & CP_SCRATCH_TO_REG_0_CNT__MASK;
1714}
1715
1716#define REG_CP_SCRATCH_WRITE_0 0x00000000
1717#define CP_SCRATCH_WRITE_0_SCRATCH__MASK 0x00700000
1718#define CP_SCRATCH_WRITE_0_SCRATCH__SHIFT 20
1719static inline uint32_t CP_SCRATCH_WRITE_0_SCRATCH(uint32_t val)
1720{
1721 return ((val) << CP_SCRATCH_WRITE_0_SCRATCH__SHIFT) & CP_SCRATCH_WRITE_0_SCRATCH__MASK;
1722}
1723
1724#define REG_CP_MEM_WRITE_0 0x00000000
1725#define CP_MEM_WRITE_0_ADDR_LO__MASK 0xffffffff
1726#define CP_MEM_WRITE_0_ADDR_LO__SHIFT 0
1727static inline uint32_t CP_MEM_WRITE_0_ADDR_LO(uint32_t val)
1728{
1729 return ((val) << CP_MEM_WRITE_0_ADDR_LO__SHIFT) & CP_MEM_WRITE_0_ADDR_LO__MASK;
1730}
1731
1732#define REG_CP_MEM_WRITE_1 0x00000001
1733#define CP_MEM_WRITE_1_ADDR_HI__MASK 0xffffffff
1734#define CP_MEM_WRITE_1_ADDR_HI__SHIFT 0
1735static inline uint32_t CP_MEM_WRITE_1_ADDR_HI(uint32_t val)
1736{
1737 return ((val) << CP_MEM_WRITE_1_ADDR_HI__SHIFT) & CP_MEM_WRITE_1_ADDR_HI__MASK;
1738}
1739
1740#define REG_CP_COND_WRITE_0 0x00000000
1741#define CP_COND_WRITE_0_FUNCTION__MASK 0x00000007
1742#define CP_COND_WRITE_0_FUNCTION__SHIFT 0
1743static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)
1744{
1745 return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK;
1746}
1747#define CP_COND_WRITE_0_POLL_MEMORY 0x00000010
1748#define CP_COND_WRITE_0_WRITE_MEMORY 0x00000100
1749
1750#define REG_CP_COND_WRITE_1 0x00000001
1751#define CP_COND_WRITE_1_POLL_ADDR__MASK 0xffffffff
1752#define CP_COND_WRITE_1_POLL_ADDR__SHIFT 0
1753static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val)
1754{
1755 return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK;
1756}
1757
1758#define REG_CP_COND_WRITE_2 0x00000002
1759#define CP_COND_WRITE_2_REF__MASK 0xffffffff
1760#define CP_COND_WRITE_2_REF__SHIFT 0
1761static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val)
1762{
1763 return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK;
1764}
1765
1766#define REG_CP_COND_WRITE_3 0x00000003
1767#define CP_COND_WRITE_3_MASK__MASK 0xffffffff
1768#define CP_COND_WRITE_3_MASK__SHIFT 0
1769static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val)
1770{
1771 return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK;
1772}
1773
1774#define REG_CP_COND_WRITE_4 0x00000004
1775#define CP_COND_WRITE_4_WRITE_ADDR__MASK 0xffffffff
1776#define CP_COND_WRITE_4_WRITE_ADDR__SHIFT 0
1777static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)
1778{
1779 return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK;
1780}
1781
1782#define REG_CP_COND_WRITE_5 0x00000005
1783#define CP_COND_WRITE_5_WRITE_DATA__MASK 0xffffffff
1784#define CP_COND_WRITE_5_WRITE_DATA__SHIFT 0
1785static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val)
1786{
1787 return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK;
1788}
1789
1790#define REG_CP_COND_WRITE5_0 0x00000000
1791#define CP_COND_WRITE5_0_FUNCTION__MASK 0x00000007
1792#define CP_COND_WRITE5_0_FUNCTION__SHIFT 0
1793static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)
1794{
1795 return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;
1796}
1797#define CP_COND_WRITE5_0_SIGNED_COMPARE 0x00000008
1798#define CP_COND_WRITE5_0_POLL__MASK 0x00000030
1799#define CP_COND_WRITE5_0_POLL__SHIFT 4
1800static inline uint32_t CP_COND_WRITE5_0_POLL(enum poll_memory_type val)
1801{
1802 return ((val) << CP_COND_WRITE5_0_POLL__SHIFT) & CP_COND_WRITE5_0_POLL__MASK;
1803}
1804#define CP_COND_WRITE5_0_WRITE_MEMORY 0x00000100
1805
1806#define REG_CP_COND_WRITE5_1 0x00000001
1807#define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK 0xffffffff
1808#define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT 0
1809static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)
1810{
1811 return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK;
1812}
1813
1814#define REG_CP_COND_WRITE5_2 0x00000002
1815#define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK 0xffffffff
1816#define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT 0
1817static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)
1818{
1819 return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK;
1820}
1821
1822#define REG_CP_COND_WRITE5_3 0x00000003
1823#define CP_COND_WRITE5_3_REF__MASK 0xffffffff
1824#define CP_COND_WRITE5_3_REF__SHIFT 0
1825static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val)
1826{
1827 return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK;
1828}
1829
1830#define REG_CP_COND_WRITE5_4 0x00000004
1831#define CP_COND_WRITE5_4_MASK__MASK 0xffffffff
1832#define CP_COND_WRITE5_4_MASK__SHIFT 0
1833static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val)
1834{
1835 return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK;
1836}
1837
1838#define REG_CP_COND_WRITE5_5 0x00000005
1839#define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK 0xffffffff
1840#define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT 0
1841static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)
1842{
1843 return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK;
1844}
1845
1846#define REG_CP_COND_WRITE5_6 0x00000006
1847#define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK 0xffffffff
1848#define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT 0
1849static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)
1850{
1851 return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK;
1852}
1853
1854#define REG_CP_COND_WRITE5_7 0x00000007
1855#define CP_COND_WRITE5_7_WRITE_DATA__MASK 0xffffffff
1856#define CP_COND_WRITE5_7_WRITE_DATA__SHIFT 0
1857static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)
1858{
1859 return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK;
1860}
1861
1862#define REG_CP_WAIT_MEM_GTE_0 0x00000000
1863#define CP_WAIT_MEM_GTE_0_RESERVED__MASK 0xffffffff
1864#define CP_WAIT_MEM_GTE_0_RESERVED__SHIFT 0
1865static inline uint32_t CP_WAIT_MEM_GTE_0_RESERVED(uint32_t val)
1866{
1867 return ((val) << CP_WAIT_MEM_GTE_0_RESERVED__SHIFT) & CP_WAIT_MEM_GTE_0_RESERVED__MASK;
1868}
1869
1870#define REG_CP_WAIT_MEM_GTE_1 0x00000001
1871#define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK 0xffffffff
1872#define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT 0
1873static inline uint32_t CP_WAIT_MEM_GTE_1_POLL_ADDR_LO(uint32_t val)
1874{
1875 return ((val) << CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK;
1876}
1877
1878#define REG_CP_WAIT_MEM_GTE_2 0x00000002
1879#define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK 0xffffffff
1880#define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT 0
1881static inline uint32_t CP_WAIT_MEM_GTE_2_POLL_ADDR_HI(uint32_t val)
1882{
1883 return ((val) << CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK;
1884}
1885
1886#define REG_CP_WAIT_MEM_GTE_3 0x00000003
1887#define CP_WAIT_MEM_GTE_3_REF__MASK 0xffffffff
1888#define CP_WAIT_MEM_GTE_3_REF__SHIFT 0
1889static inline uint32_t CP_WAIT_MEM_GTE_3_REF(uint32_t val)
1890{
1891 return ((val) << CP_WAIT_MEM_GTE_3_REF__SHIFT) & CP_WAIT_MEM_GTE_3_REF__MASK;
1892}
1893
1894#define REG_CP_WAIT_REG_MEM_0 0x00000000
1895#define CP_WAIT_REG_MEM_0_FUNCTION__MASK 0x00000007
1896#define CP_WAIT_REG_MEM_0_FUNCTION__SHIFT 0
1897static inline uint32_t CP_WAIT_REG_MEM_0_FUNCTION(enum cp_cond_function val)
1898{
1899 return ((val) << CP_WAIT_REG_MEM_0_FUNCTION__SHIFT) & CP_WAIT_REG_MEM_0_FUNCTION__MASK;
1900}
1901#define CP_WAIT_REG_MEM_0_SIGNED_COMPARE 0x00000008
1902#define CP_WAIT_REG_MEM_0_POLL__MASK 0x00000030
1903#define CP_WAIT_REG_MEM_0_POLL__SHIFT 4
1904static inline uint32_t CP_WAIT_REG_MEM_0_POLL(enum poll_memory_type val)
1905{
1906 return ((val) << CP_WAIT_REG_MEM_0_POLL__SHIFT) & CP_WAIT_REG_MEM_0_POLL__MASK;
1907}
1908#define CP_WAIT_REG_MEM_0_WRITE_MEMORY 0x00000100
1909
1910#define REG_CP_WAIT_REG_MEM_1 0x00000001
1911#define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK 0xffffffff
1912#define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT 0
1913static inline uint32_t CP_WAIT_REG_MEM_1_POLL_ADDR_LO(uint32_t val)
1914{
1915 return ((val) << CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK;
1916}
1917
1918#define REG_CP_WAIT_REG_MEM_2 0x00000002
1919#define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK 0xffffffff
1920#define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT 0
1921static inline uint32_t CP_WAIT_REG_MEM_2_POLL_ADDR_HI(uint32_t val)
1922{
1923 return ((val) << CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK;
1924}
1925
1926#define REG_CP_WAIT_REG_MEM_3 0x00000003
1927#define CP_WAIT_REG_MEM_3_REF__MASK 0xffffffff
1928#define CP_WAIT_REG_MEM_3_REF__SHIFT 0
1929static inline uint32_t CP_WAIT_REG_MEM_3_REF(uint32_t val)
1930{
1931 return ((val) << CP_WAIT_REG_MEM_3_REF__SHIFT) & CP_WAIT_REG_MEM_3_REF__MASK;
1932}
1933
1934#define REG_CP_WAIT_REG_MEM_4 0x00000004
1935#define CP_WAIT_REG_MEM_4_MASK__MASK 0xffffffff
1936#define CP_WAIT_REG_MEM_4_MASK__SHIFT 0
1937static inline uint32_t CP_WAIT_REG_MEM_4_MASK(uint32_t val)
1938{
1939 return ((val) << CP_WAIT_REG_MEM_4_MASK__SHIFT) & CP_WAIT_REG_MEM_4_MASK__MASK;
1940}
1941
1942#define REG_CP_WAIT_REG_MEM_5 0x00000005
1943#define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK 0xffffffff
1944#define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT 0
1945static inline uint32_t CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(uint32_t val)
1946{
1947 return ((val) << CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT) & CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK;
1948}
1949
1950#define REG_CP_WAIT_TWO_REGS_0 0x00000000
1951#define CP_WAIT_TWO_REGS_0_REG0__MASK 0x0003ffff
1952#define CP_WAIT_TWO_REGS_0_REG0__SHIFT 0
1953static inline uint32_t CP_WAIT_TWO_REGS_0_REG0(uint32_t val)
1954{
1955 return ((val) << CP_WAIT_TWO_REGS_0_REG0__SHIFT) & CP_WAIT_TWO_REGS_0_REG0__MASK;
1956}
1957
1958#define REG_CP_WAIT_TWO_REGS_1 0x00000001
1959#define CP_WAIT_TWO_REGS_1_REG1__MASK 0x0003ffff
1960#define CP_WAIT_TWO_REGS_1_REG1__SHIFT 0
1961static inline uint32_t CP_WAIT_TWO_REGS_1_REG1(uint32_t val)
1962{
1963 return ((val) << CP_WAIT_TWO_REGS_1_REG1__SHIFT) & CP_WAIT_TWO_REGS_1_REG1__MASK;
1964}
1965
1966#define REG_CP_WAIT_TWO_REGS_2 0x00000002
1967#define CP_WAIT_TWO_REGS_2_REF__MASK 0xffffffff
1968#define CP_WAIT_TWO_REGS_2_REF__SHIFT 0
1969static inline uint32_t CP_WAIT_TWO_REGS_2_REF(uint32_t val)
1970{
1971 return ((val) << CP_WAIT_TWO_REGS_2_REF__SHIFT) & CP_WAIT_TWO_REGS_2_REF__MASK;
1972}
1973
1974#define REG_CP_DISPATCH_COMPUTE_0 0x00000000
1975
1976#define REG_CP_DISPATCH_COMPUTE_1 0x00000001
1977#define CP_DISPATCH_COMPUTE_1_X__MASK 0xffffffff
1978#define CP_DISPATCH_COMPUTE_1_X__SHIFT 0
1979static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val)
1980{
1981 return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK;
1982}
1983
1984#define REG_CP_DISPATCH_COMPUTE_2 0x00000002
1985#define CP_DISPATCH_COMPUTE_2_Y__MASK 0xffffffff
1986#define CP_DISPATCH_COMPUTE_2_Y__SHIFT 0
1987static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val)
1988{
1989 return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK;
1990}
1991
1992#define REG_CP_DISPATCH_COMPUTE_3 0x00000003
1993#define CP_DISPATCH_COMPUTE_3_Z__MASK 0xffffffff
1994#define CP_DISPATCH_COMPUTE_3_Z__SHIFT 0
1995static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val)
1996{
1997 return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK;
1998}
1999
2000#define REG_CP_SET_RENDER_MODE_0 0x00000000
2001#define CP_SET_RENDER_MODE_0_MODE__MASK 0x000001ff
2002#define CP_SET_RENDER_MODE_0_MODE__SHIFT 0
2003static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)
2004{
2005 return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK;
2006}
2007
2008#define REG_CP_SET_RENDER_MODE_1 0x00000001
2009#define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK 0xffffffff
2010#define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT 0
2011static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)
2012{
2013 return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK;
2014}
2015
2016#define REG_CP_SET_RENDER_MODE_2 0x00000002
2017#define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK 0xffffffff
2018#define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT 0
2019static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)
2020{
2021 return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK;
2022}
2023
2024#define REG_CP_SET_RENDER_MODE_3 0x00000003
2025#define CP_SET_RENDER_MODE_3_VSC_ENABLE 0x00000008
2026#define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010
2027
2028#define REG_CP_SET_RENDER_MODE_4 0x00000004
2029
2030#define REG_CP_SET_RENDER_MODE_5 0x00000005
2031#define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK 0xffffffff
2032#define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT 0
2033static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)
2034{
2035 return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK;
2036}
2037
2038#define REG_CP_SET_RENDER_MODE_6 0x00000006
2039#define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK 0xffffffff
2040#define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT 0
2041static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)
2042{
2043 return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK;
2044}
2045
2046#define REG_CP_SET_RENDER_MODE_7 0x00000007
2047#define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK 0xffffffff
2048#define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT 0
2049static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)
2050{
2051 return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK;
2052}
2053
2054#define REG_CP_COMPUTE_CHECKPOINT_0 0x00000000
2055#define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK 0xffffffff
2056#define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT 0
2057static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)
2058{
2059 return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK;
2060}
2061
2062#define REG_CP_COMPUTE_CHECKPOINT_1 0x00000001
2063#define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK 0xffffffff
2064#define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT 0
2065static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)
2066{
2067 return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK;
2068}
2069
2070#define REG_CP_COMPUTE_CHECKPOINT_2 0x00000002
2071
2072#define REG_CP_COMPUTE_CHECKPOINT_3 0x00000003
2073
2074#define REG_CP_COMPUTE_CHECKPOINT_4 0x00000004
2075#define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK 0xffffffff
2076#define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT 0
2077static inline uint32_t CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN(uint32_t val)
2078{
2079 return ((val) << CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK;
2080}
2081
2082#define REG_CP_COMPUTE_CHECKPOINT_5 0x00000005
2083#define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK 0xffffffff
2084#define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT 0
2085static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)
2086{
2087 return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK;
2088}
2089
2090#define REG_CP_COMPUTE_CHECKPOINT_6 0x00000006
2091#define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK 0xffffffff
2092#define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT 0
2093static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)
2094{
2095 return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK;
2096}
2097
2098#define REG_CP_COMPUTE_CHECKPOINT_7 0x00000007
2099
2100#define REG_CP_PERFCOUNTER_ACTION_0 0x00000000
2101
2102#define REG_CP_PERFCOUNTER_ACTION_1 0x00000001
2103#define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK 0xffffffff
2104#define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT 0
2105static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)
2106{
2107 return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK;
2108}
2109
2110#define REG_CP_PERFCOUNTER_ACTION_2 0x00000002
2111#define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK 0xffffffff
2112#define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT 0
2113static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)
2114{
2115 return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK;
2116}
2117
2118#define REG_CP_EVENT_WRITE_0 0x00000000
2119#define CP_EVENT_WRITE_0_EVENT__MASK 0x000000ff
2120#define CP_EVENT_WRITE_0_EVENT__SHIFT 0
2121static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)
2122{
2123 return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;
2124}
2125#define CP_EVENT_WRITE_0_TIMESTAMP 0x40000000
2126#define CP_EVENT_WRITE_0_IRQ 0x80000000
2127
2128#define REG_CP_EVENT_WRITE_1 0x00000001
2129#define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff
2130#define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT 0
2131static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)
2132{
2133 return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK;
2134}
2135
2136#define REG_CP_EVENT_WRITE_2 0x00000002
2137#define CP_EVENT_WRITE_2_ADDR_0_HI__MASK 0xffffffff
2138#define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT 0
2139static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)
2140{
2141 return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK;
2142}
2143
2144#define REG_CP_EVENT_WRITE_3 0x00000003
2145
2146#define REG_CP_EVENT_WRITE7_0 0x00000000
2147#define CP_EVENT_WRITE7_0_EVENT__MASK 0x000000ff
2148#define CP_EVENT_WRITE7_0_EVENT__SHIFT 0
2149static inline uint32_t CP_EVENT_WRITE7_0_EVENT(enum vgt_event_type val)
2150{
2151 return ((val) << CP_EVENT_WRITE7_0_EVENT__SHIFT) & CP_EVENT_WRITE7_0_EVENT__MASK;
2152}
2153#define CP_EVENT_WRITE7_0_WRITE_SAMPLE_COUNT 0x00001000
2154#define CP_EVENT_WRITE7_0_SAMPLE_COUNT_END_OFFSET 0x00002000
2155#define CP_EVENT_WRITE7_0_WRITE_SAMPLE_COUNT_DIFF 0x00004000
2156#define CP_EVENT_WRITE7_0_INC_BV_COUNT 0x00010000
2157#define CP_EVENT_WRITE7_0_INC_BR_COUNT 0x00020000
2158#define CP_EVENT_WRITE7_0_CLEAR_RENDER_RESOURCE 0x00040000
2159#define CP_EVENT_WRITE7_0_CLEAR_LRZ_RESOURCE 0x00080000
2160#define CP_EVENT_WRITE7_0_WRITE_SRC__MASK 0x00700000
2161#define CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT 20
2162static inline uint32_t CP_EVENT_WRITE7_0_WRITE_SRC(enum event_write_src val)
2163{
2164 return ((val) << CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT) & CP_EVENT_WRITE7_0_WRITE_SRC__MASK;
2165}
2166#define CP_EVENT_WRITE7_0_WRITE_DST__MASK 0x01000000
2167#define CP_EVENT_WRITE7_0_WRITE_DST__SHIFT 24
2168static inline uint32_t CP_EVENT_WRITE7_0_WRITE_DST(enum event_write_dst val)
2169{
2170 return ((val) << CP_EVENT_WRITE7_0_WRITE_DST__SHIFT) & CP_EVENT_WRITE7_0_WRITE_DST__MASK;
2171}
2172#define CP_EVENT_WRITE7_0_WRITE_ENABLED 0x08000000
2173
2174#define REG_EV_DST_RAM_CP_EVENT_WRITE7_1 0x00000001
2175#define EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__MASK 0xffffffff
2176#define EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__SHIFT 0
2177static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO(uint32_t val)
2178{
2179 return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__MASK;
2180}
2181
2182#define REG_EV_DST_RAM_CP_EVENT_WRITE7_2 0x00000002
2183#define EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__MASK 0xffffffff
2184#define EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__SHIFT 0
2185static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI(uint32_t val)
2186{
2187 return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__MASK;
2188}
2189
2190#define REG_EV_DST_RAM_CP_EVENT_WRITE7_3 0x00000003
2191#define EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK 0xffffffff
2192#define EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT 0
2193static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0(uint32_t val)
2194{
2195 return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK;
2196}
2197
2198#define REG_EV_DST_RAM_CP_EVENT_WRITE7_4 0x00000004
2199#define EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK 0xffffffff
2200#define EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT 0
2201static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1(uint32_t val)
2202{
2203 return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK;
2204}
2205
2206#define REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_1 0x00000001
2207#define EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK 0xffffffff
2208#define EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT 0
2209static inline uint32_t EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0(uint32_t val)
2210{
2211 return ((val) << EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK;
2212}
2213
2214#define REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_3 0x00000003
2215#define EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK 0xffffffff
2216#define EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT 0
2217static inline uint32_t EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0(uint32_t val)
2218{
2219 return ((val) << EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK;
2220}
2221
2222#define REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_4 0x00000004
2223#define EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK 0xffffffff
2224#define EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT 0
2225static inline uint32_t EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1(uint32_t val)
2226{
2227 return ((val) << EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK;
2228}
2229
2230#define REG_CP_BLIT_0 0x00000000
2231#define CP_BLIT_0_OP__MASK 0x0000000f
2232#define CP_BLIT_0_OP__SHIFT 0
2233static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)
2234{
2235 return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK;
2236}
2237
2238#define REG_CP_BLIT_1 0x00000001
2239#define CP_BLIT_1_SRC_X1__MASK 0x00003fff
2240#define CP_BLIT_1_SRC_X1__SHIFT 0
2241static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val)
2242{
2243 return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK;
2244}
2245#define CP_BLIT_1_SRC_Y1__MASK 0x3fff0000
2246#define CP_BLIT_1_SRC_Y1__SHIFT 16
2247static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)
2248{
2249 return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK;
2250}
2251
2252#define REG_CP_BLIT_2 0x00000002
2253#define CP_BLIT_2_SRC_X2__MASK 0x00003fff
2254#define CP_BLIT_2_SRC_X2__SHIFT 0
2255static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val)
2256{
2257 return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK;
2258}
2259#define CP_BLIT_2_SRC_Y2__MASK 0x3fff0000
2260#define CP_BLIT_2_SRC_Y2__SHIFT 16
2261static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)
2262{
2263 return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK;
2264}
2265
2266#define REG_CP_BLIT_3 0x00000003
2267#define CP_BLIT_3_DST_X1__MASK 0x00003fff
2268#define CP_BLIT_3_DST_X1__SHIFT 0
2269static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val)
2270{
2271 return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK;
2272}
2273#define CP_BLIT_3_DST_Y1__MASK 0x3fff0000
2274#define CP_BLIT_3_DST_Y1__SHIFT 16
2275static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)
2276{
2277 return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK;
2278}
2279
2280#define REG_CP_BLIT_4 0x00000004
2281#define CP_BLIT_4_DST_X2__MASK 0x00003fff
2282#define CP_BLIT_4_DST_X2__SHIFT 0
2283static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val)
2284{
2285 return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK;
2286}
2287#define CP_BLIT_4_DST_Y2__MASK 0x3fff0000
2288#define CP_BLIT_4_DST_Y2__SHIFT 16
2289static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)
2290{
2291 return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK;
2292}
2293
2294#define REG_CP_EXEC_CS_0 0x00000000
2295
2296#define REG_CP_EXEC_CS_1 0x00000001
2297#define CP_EXEC_CS_1_NGROUPS_X__MASK 0xffffffff
2298#define CP_EXEC_CS_1_NGROUPS_X__SHIFT 0
2299static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val)
2300{
2301 return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK;
2302}
2303
2304#define REG_CP_EXEC_CS_2 0x00000002
2305#define CP_EXEC_CS_2_NGROUPS_Y__MASK 0xffffffff
2306#define CP_EXEC_CS_2_NGROUPS_Y__SHIFT 0
2307static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)
2308{
2309 return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK;
2310}
2311
2312#define REG_CP_EXEC_CS_3 0x00000003
2313#define CP_EXEC_CS_3_NGROUPS_Z__MASK 0xffffffff
2314#define CP_EXEC_CS_3_NGROUPS_Z__SHIFT 0
2315static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)
2316{
2317 return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK;
2318}
2319
2320#define REG_A4XX_CP_EXEC_CS_INDIRECT_0 0x00000000
2321
2322#define REG_A4XX_CP_EXEC_CS_INDIRECT_1 0x00000001
2323#define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK 0xffffffff
2324#define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT 0
2325static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val)
2326{
2327 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK;
2328}
2329
2330#define REG_A4XX_CP_EXEC_CS_INDIRECT_2 0x00000002
2331#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK 0x00000ffc
2332#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT 2
2333static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val)
2334{
2335 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK;
2336}
2337#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK 0x003ff000
2338#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT 12
2339static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val)
2340{
2341 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK;
2342}
2343#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK 0xffc00000
2344#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT 22
2345static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val)
2346{
2347 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK;
2348}
2349
2350#define REG_A5XX_CP_EXEC_CS_INDIRECT_1 0x00000001
2351#define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK 0xffffffff
2352#define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT 0
2353static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val)
2354{
2355 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK;
2356}
2357
2358#define REG_A5XX_CP_EXEC_CS_INDIRECT_2 0x00000002
2359#define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK 0xffffffff
2360#define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT 0
2361static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val)
2362{
2363 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK;
2364}
2365
2366#define REG_A5XX_CP_EXEC_CS_INDIRECT_3 0x00000003
2367#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK 0x00000ffc
2368#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT 2
2369static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val)
2370{
2371 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK;
2372}
2373#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK 0x003ff000
2374#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT 12
2375static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val)
2376{
2377 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK;
2378}
2379#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK 0xffc00000
2380#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT 22
2381static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)
2382{
2383 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK;
2384}
2385
2386#define REG_A6XX_CP_SET_MARKER_0 0x00000000
2387#define A6XX_CP_SET_MARKER_0_MODE__MASK 0x000001ff
2388#define A6XX_CP_SET_MARKER_0_MODE__SHIFT 0
2389static inline uint32_t A6XX_CP_SET_MARKER_0_MODE(enum a6xx_marker val)
2390{
2391 return ((val) << A6XX_CP_SET_MARKER_0_MODE__SHIFT) & A6XX_CP_SET_MARKER_0_MODE__MASK;
2392}
2393#define A6XX_CP_SET_MARKER_0_MARKER__MASK 0x0000000f
2394#define A6XX_CP_SET_MARKER_0_MARKER__SHIFT 0
2395static inline uint32_t A6XX_CP_SET_MARKER_0_MARKER(enum a6xx_marker val)
2396{
2397 return ((val) << A6XX_CP_SET_MARKER_0_MARKER__SHIFT) & A6XX_CP_SET_MARKER_0_MARKER__MASK;
2398}
2399
2400#define REG_A6XX_CP_SET_PSEUDO_REG_(i0) (0x00000000 + 0x3*(i0))
2401
2402static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
2403#define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK 0x000007ff
2404#define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT 0
2405static inline uint32_t A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val)
2406{
2407 return ((val) << A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK;
2408}
2409
2410static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
2411#define A6XX_CP_SET_PSEUDO_REG__1_LO__MASK 0xffffffff
2412#define A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT 0
2413static inline uint32_t A6XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val)
2414{
2415 return ((val) << A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A6XX_CP_SET_PSEUDO_REG__1_LO__MASK;
2416}
2417
2418static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
2419#define A6XX_CP_SET_PSEUDO_REG__2_HI__MASK 0xffffffff
2420#define A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT 0
2421static inline uint32_t A6XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val)
2422{
2423 return ((val) << A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A6XX_CP_SET_PSEUDO_REG__2_HI__MASK;
2424}
2425
2426#define REG_A6XX_CP_REG_TEST_0 0x00000000
2427#define A6XX_CP_REG_TEST_0_REG__MASK 0x0003ffff
2428#define A6XX_CP_REG_TEST_0_REG__SHIFT 0
2429static inline uint32_t A6XX_CP_REG_TEST_0_REG(uint32_t val)
2430{
2431 return ((val) << A6XX_CP_REG_TEST_0_REG__SHIFT) & A6XX_CP_REG_TEST_0_REG__MASK;
2432}
2433#define A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK 0x0003ffff
2434#define A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT 0
2435static inline uint32_t A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET(uint32_t val)
2436{
2437 return ((val) << A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT) & A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK;
2438}
2439#define A6XX_CP_REG_TEST_0_SOURCE__MASK 0x00040000
2440#define A6XX_CP_REG_TEST_0_SOURCE__SHIFT 18
2441static inline uint32_t A6XX_CP_REG_TEST_0_SOURCE(enum source_type val)
2442{
2443 return ((val) << A6XX_CP_REG_TEST_0_SOURCE__SHIFT) & A6XX_CP_REG_TEST_0_SOURCE__MASK;
2444}
2445#define A6XX_CP_REG_TEST_0_BIT__MASK 0x01f00000
2446#define A6XX_CP_REG_TEST_0_BIT__SHIFT 20
2447static inline uint32_t A6XX_CP_REG_TEST_0_BIT(uint32_t val)
2448{
2449 return ((val) << A6XX_CP_REG_TEST_0_BIT__SHIFT) & A6XX_CP_REG_TEST_0_BIT__MASK;
2450}
2451#define A6XX_CP_REG_TEST_0_SKIP_WAIT_FOR_ME 0x02000000
2452#define A6XX_CP_REG_TEST_0_PRED_BIT__MASK 0x7c000000
2453#define A6XX_CP_REG_TEST_0_PRED_BIT__SHIFT 26
2454static inline uint32_t A6XX_CP_REG_TEST_0_PRED_BIT(uint32_t val)
2455{
2456 return ((val) << A6XX_CP_REG_TEST_0_PRED_BIT__SHIFT) & A6XX_CP_REG_TEST_0_PRED_BIT__MASK;
2457}
2458#define A6XX_CP_REG_TEST_0_PRED_UPDATE 0x80000000
2459
2460#define REG_A6XX_CP_REG_TEST_PRED_MASK 0x00000001
2461
2462#define REG_A6XX_CP_REG_TEST_PRED_VAL 0x00000002
2463
2464#define REG_CP_COND_REG_EXEC_0 0x00000000
2465#define CP_COND_REG_EXEC_0_REG0__MASK 0x0003ffff
2466#define CP_COND_REG_EXEC_0_REG0__SHIFT 0
2467static inline uint32_t CP_COND_REG_EXEC_0_REG0(uint32_t val)
2468{
2469 return ((val) << CP_COND_REG_EXEC_0_REG0__SHIFT) & CP_COND_REG_EXEC_0_REG0__MASK;
2470}
2471#define CP_COND_REG_EXEC_0_PRED_BIT__MASK 0x007c0000
2472#define CP_COND_REG_EXEC_0_PRED_BIT__SHIFT 18
2473static inline uint32_t CP_COND_REG_EXEC_0_PRED_BIT(uint32_t val)
2474{
2475 return ((val) << CP_COND_REG_EXEC_0_PRED_BIT__SHIFT) & CP_COND_REG_EXEC_0_PRED_BIT__MASK;
2476}
2477#define CP_COND_REG_EXEC_0_SKIP_WAIT_FOR_ME 0x00800000
2478#define CP_COND_REG_EXEC_0_ONCHIP_MEM 0x01000000
2479#define CP_COND_REG_EXEC_0_BINNING 0x02000000
2480#define CP_COND_REG_EXEC_0_GMEM 0x04000000
2481#define CP_COND_REG_EXEC_0_SYSMEM 0x08000000
2482#define CP_COND_REG_EXEC_0_BV 0x02000000
2483#define CP_COND_REG_EXEC_0_BR 0x04000000
2484#define CP_COND_REG_EXEC_0_LPAC 0x08000000
2485#define CP_COND_REG_EXEC_0_MODE__MASK 0xf0000000
2486#define CP_COND_REG_EXEC_0_MODE__SHIFT 28
2487static inline uint32_t CP_COND_REG_EXEC_0_MODE(enum compare_mode val)
2488{
2489 return ((val) << CP_COND_REG_EXEC_0_MODE__SHIFT) & CP_COND_REG_EXEC_0_MODE__MASK;
2490}
2491
2492#define REG_PRED_TEST_CP_COND_REG_EXEC_1 0x00000001
2493#define PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK 0x00ffffff
2494#define PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT 0
2495static inline uint32_t PRED_TEST_CP_COND_REG_EXEC_1_DWORDS(uint32_t val)
2496{
2497 return ((val) << PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK;
2498}
2499
2500#define REG_REG_COMPARE_CP_COND_REG_EXEC_1 0x00000001
2501#define REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK 0x0003ffff
2502#define REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT 0
2503static inline uint32_t REG_COMPARE_CP_COND_REG_EXEC_1_REG1(uint32_t val)
2504{
2505 return ((val) << REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT) & REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK;
2506}
2507#define REG_COMPARE_CP_COND_REG_EXEC_1_ONCHIP_MEM 0x01000000
2508
2509#define REG_RENDER_MODE_CP_COND_REG_EXEC_1 0x00000001
2510#define RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK 0x00ffffff
2511#define RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT 0
2512static inline uint32_t RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS(uint32_t val)
2513{
2514 return ((val) << RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK;
2515}
2516
2517#define REG_REG_COMPARE_IMM_CP_COND_REG_EXEC_1 0x00000001
2518#define REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK 0xffffffff
2519#define REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT 0
2520static inline uint32_t REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM(uint32_t val)
2521{
2522 return ((val) << REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT) & REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK;
2523}
2524
2525#define REG_THREAD_MODE_CP_COND_REG_EXEC_1 0x00000001
2526#define THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK 0x00ffffff
2527#define THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT 0
2528static inline uint32_t THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS(uint32_t val)
2529{
2530 return ((val) << THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK;
2531}
2532
2533#define REG_CP_COND_REG_EXEC_2 0x00000002
2534#define CP_COND_REG_EXEC_2_DWORDS__MASK 0x00ffffff
2535#define CP_COND_REG_EXEC_2_DWORDS__SHIFT 0
2536static inline uint32_t CP_COND_REG_EXEC_2_DWORDS(uint32_t val)
2537{
2538 return ((val) << CP_COND_REG_EXEC_2_DWORDS__SHIFT) & CP_COND_REG_EXEC_2_DWORDS__MASK;
2539}
2540
2541#define REG_CP_COND_EXEC_0 0x00000000
2542#define CP_COND_EXEC_0_ADDR0_LO__MASK 0xffffffff
2543#define CP_COND_EXEC_0_ADDR0_LO__SHIFT 0
2544static inline uint32_t CP_COND_EXEC_0_ADDR0_LO(uint32_t val)
2545{
2546 return ((val) << CP_COND_EXEC_0_ADDR0_LO__SHIFT) & CP_COND_EXEC_0_ADDR0_LO__MASK;
2547}
2548
2549#define REG_CP_COND_EXEC_1 0x00000001
2550#define CP_COND_EXEC_1_ADDR0_HI__MASK 0xffffffff
2551#define CP_COND_EXEC_1_ADDR0_HI__SHIFT 0
2552static inline uint32_t CP_COND_EXEC_1_ADDR0_HI(uint32_t val)
2553{
2554 return ((val) << CP_COND_EXEC_1_ADDR0_HI__SHIFT) & CP_COND_EXEC_1_ADDR0_HI__MASK;
2555}
2556
2557#define REG_CP_COND_EXEC_2 0x00000002
2558#define CP_COND_EXEC_2_ADDR1_LO__MASK 0xffffffff
2559#define CP_COND_EXEC_2_ADDR1_LO__SHIFT 0
2560static inline uint32_t CP_COND_EXEC_2_ADDR1_LO(uint32_t val)
2561{
2562 return ((val) << CP_COND_EXEC_2_ADDR1_LO__SHIFT) & CP_COND_EXEC_2_ADDR1_LO__MASK;
2563}
2564
2565#define REG_CP_COND_EXEC_3 0x00000003
2566#define CP_COND_EXEC_3_ADDR1_HI__MASK 0xffffffff
2567#define CP_COND_EXEC_3_ADDR1_HI__SHIFT 0
2568static inline uint32_t CP_COND_EXEC_3_ADDR1_HI(uint32_t val)
2569{
2570 return ((val) << CP_COND_EXEC_3_ADDR1_HI__SHIFT) & CP_COND_EXEC_3_ADDR1_HI__MASK;
2571}
2572
2573#define REG_CP_COND_EXEC_4 0x00000004
2574#define CP_COND_EXEC_4_REF__MASK 0xffffffff
2575#define CP_COND_EXEC_4_REF__SHIFT 0
2576static inline uint32_t CP_COND_EXEC_4_REF(uint32_t val)
2577{
2578 return ((val) << CP_COND_EXEC_4_REF__SHIFT) & CP_COND_EXEC_4_REF__MASK;
2579}
2580
2581#define REG_CP_COND_EXEC_5 0x00000005
2582#define CP_COND_EXEC_5_DWORDS__MASK 0xffffffff
2583#define CP_COND_EXEC_5_DWORDS__SHIFT 0
2584static inline uint32_t CP_COND_EXEC_5_DWORDS(uint32_t val)
2585{
2586 return ((val) << CP_COND_EXEC_5_DWORDS__SHIFT) & CP_COND_EXEC_5_DWORDS__MASK;
2587}
2588
2589#define REG_CP_SET_CTXSWITCH_IB_0 0x00000000
2590#define CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK 0xffffffff
2591#define CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT 0
2592static inline uint32_t CP_SET_CTXSWITCH_IB_0_ADDR_LO(uint32_t val)
2593{
2594 return ((val) << CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT) & CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK;
2595}
2596
2597#define REG_CP_SET_CTXSWITCH_IB_1 0x00000001
2598#define CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK 0xffffffff
2599#define CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT 0
2600static inline uint32_t CP_SET_CTXSWITCH_IB_1_ADDR_HI(uint32_t val)
2601{
2602 return ((val) << CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT) & CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK;
2603}
2604
2605#define REG_CP_SET_CTXSWITCH_IB_2 0x00000002
2606#define CP_SET_CTXSWITCH_IB_2_DWORDS__MASK 0x000fffff
2607#define CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT 0
2608static inline uint32_t CP_SET_CTXSWITCH_IB_2_DWORDS(uint32_t val)
2609{
2610 return ((val) << CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT) & CP_SET_CTXSWITCH_IB_2_DWORDS__MASK;
2611}
2612#define CP_SET_CTXSWITCH_IB_2_TYPE__MASK 0x00300000
2613#define CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT 20
2614static inline uint32_t CP_SET_CTXSWITCH_IB_2_TYPE(enum ctxswitch_ib val)
2615{
2616 return ((val) << CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT) & CP_SET_CTXSWITCH_IB_2_TYPE__MASK;
2617}
2618
2619#define REG_CP_REG_WRITE_0 0x00000000
2620#define CP_REG_WRITE_0_TRACKER__MASK 0x0000000f
2621#define CP_REG_WRITE_0_TRACKER__SHIFT 0
2622static inline uint32_t CP_REG_WRITE_0_TRACKER(enum reg_tracker val)
2623{
2624 return ((val) << CP_REG_WRITE_0_TRACKER__SHIFT) & CP_REG_WRITE_0_TRACKER__MASK;
2625}
2626
2627#define REG_CP_REG_WRITE_1 0x00000001
2628
2629#define REG_CP_REG_WRITE_2 0x00000002
2630
2631#define REG_CP_SMMU_TABLE_UPDATE_0 0x00000000
2632#define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK 0xffffffff
2633#define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT 0
2634static inline uint32_t CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(uint32_t val)
2635{
2636 return ((val) << CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT) & CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK;
2637}
2638
2639#define REG_CP_SMMU_TABLE_UPDATE_1 0x00000001
2640#define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK 0x0000ffff
2641#define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT 0
2642static inline uint32_t CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(uint32_t val)
2643{
2644 return ((val) << CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT) & CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK;
2645}
2646#define CP_SMMU_TABLE_UPDATE_1_ASID__MASK 0xffff0000
2647#define CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT 16
2648static inline uint32_t CP_SMMU_TABLE_UPDATE_1_ASID(uint32_t val)
2649{
2650 return ((val) << CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT) & CP_SMMU_TABLE_UPDATE_1_ASID__MASK;
2651}
2652
2653#define REG_CP_SMMU_TABLE_UPDATE_2 0x00000002
2654#define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK 0xffffffff
2655#define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT 0
2656static inline uint32_t CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(uint32_t val)
2657{
2658 return ((val) << CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT) & CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK;
2659}
2660
2661#define REG_CP_SMMU_TABLE_UPDATE_3 0x00000003
2662#define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK 0xffffffff
2663#define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT 0
2664static inline uint32_t CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(uint32_t val)
2665{
2666 return ((val) << CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT) & CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK;
2667}
2668
2669#define REG_CP_START_BIN_BIN_COUNT 0x00000000
2670
2671#define REG_CP_START_BIN_PREFIX_ADDR 0x00000001
2672
2673#define REG_CP_START_BIN_PREFIX_DWORDS 0x00000003
2674
2675#define REG_CP_START_BIN_BODY_DWORDS 0x00000004
2676
2677#define REG_CP_WAIT_TIMESTAMP_0 0x00000000
2678#define CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK 0x00000003
2679#define CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT 0
2680static inline uint32_t CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC(enum ts_wait_value_src val)
2681{
2682 return ((val) << CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT) & CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK;
2683}
2684#define CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK 0x00000010
2685#define CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT 4
2686static inline uint32_t CP_WAIT_TIMESTAMP_0_WAIT_DST(enum ts_wait_type val)
2687{
2688 return ((val) << CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT) & CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK;
2689}
2690
2691#define REG_TS_WAIT_RAM_CP_WAIT_TIMESTAMP_ADDR 0x00000001
2692
2693#define REG_TS_WAIT_ONCHIP_CP_WAIT_TIMESTAMP_ONCHIP_ADDR_0 0x00000001
2694
2695#define REG_CP_WAIT_TIMESTAMP_SRC_0 0x00000003
2696
2697#define REG_CP_WAIT_TIMESTAMP_SRC_1 0x00000004
2698
2699#define REG_CP_BV_BR_COUNT_OPS_0 0x00000000
2700#define CP_BV_BR_COUNT_OPS_0_OP__MASK 0x0000000f
2701#define CP_BV_BR_COUNT_OPS_0_OP__SHIFT 0
2702static inline uint32_t CP_BV_BR_COUNT_OPS_0_OP(enum pipe_count_op val)
2703{
2704 return ((val) << CP_BV_BR_COUNT_OPS_0_OP__SHIFT) & CP_BV_BR_COUNT_OPS_0_OP__MASK;
2705}
2706
2707#define REG_CP_BV_BR_COUNT_OPS_1 0x00000001
2708#define CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK 0x0000ffff
2709#define CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT 0
2710static inline uint32_t CP_BV_BR_COUNT_OPS_1_BR_OFFSET(uint32_t val)
2711{
2712 return ((val) << CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT) & CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK;
2713}
2714
2715#define REG_CP_MODIFY_TIMESTAMP_0 0x00000000
2716#define CP_MODIFY_TIMESTAMP_0_ADD__MASK 0x000000ff
2717#define CP_MODIFY_TIMESTAMP_0_ADD__SHIFT 0
2718static inline uint32_t CP_MODIFY_TIMESTAMP_0_ADD(uint32_t val)
2719{
2720 return ((val) << CP_MODIFY_TIMESTAMP_0_ADD__SHIFT) & CP_MODIFY_TIMESTAMP_0_ADD__MASK;
2721}
2722#define CP_MODIFY_TIMESTAMP_0_OP__MASK 0xf0000000
2723#define CP_MODIFY_TIMESTAMP_0_OP__SHIFT 28
2724static inline uint32_t CP_MODIFY_TIMESTAMP_0_OP(enum timestamp_op val)
2725{
2726 return ((val) << CP_MODIFY_TIMESTAMP_0_OP__SHIFT) & CP_MODIFY_TIMESTAMP_0_OP__MASK;
2727}
2728
2729#define REG_CP_MEM_TO_SCRATCH_MEM_0 0x00000000
2730#define CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK 0x0000003f
2731#define CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT 0
2732static inline uint32_t CP_MEM_TO_SCRATCH_MEM_0_CNT(uint32_t val)
2733{
2734 return ((val) << CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT) & CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK;
2735}
2736
2737#define REG_CP_MEM_TO_SCRATCH_MEM_1 0x00000001
2738#define CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK 0x0000003f
2739#define CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT 0
2740static inline uint32_t CP_MEM_TO_SCRATCH_MEM_1_OFFSET(uint32_t val)
2741{
2742 return ((val) << CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT) & CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK;
2743}
2744
2745#define REG_CP_MEM_TO_SCRATCH_MEM_2 0x00000002
2746#define CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK 0xffffffff
2747#define CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT 0
2748static inline uint32_t CP_MEM_TO_SCRATCH_MEM_2_SRC(uint32_t val)
2749{
2750 return ((val) << CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT) & CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK;
2751}
2752
2753#define REG_CP_MEM_TO_SCRATCH_MEM_3 0x00000003
2754#define CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK 0xffffffff
2755#define CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT 0
2756static inline uint32_t CP_MEM_TO_SCRATCH_MEM_3_SRC_HI(uint32_t val)
2757{
2758 return ((val) << CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT) & CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK;
2759}
2760
2761#define REG_CP_THREAD_CONTROL_0 0x00000000
2762#define CP_THREAD_CONTROL_0_THREAD__MASK 0x00000003
2763#define CP_THREAD_CONTROL_0_THREAD__SHIFT 0
2764static inline uint32_t CP_THREAD_CONTROL_0_THREAD(enum cp_thread val)
2765{
2766 return ((val) << CP_THREAD_CONTROL_0_THREAD__SHIFT) & CP_THREAD_CONTROL_0_THREAD__MASK;
2767}
2768#define CP_THREAD_CONTROL_0_CONCURRENT_BIN_DISABLE 0x08000000
2769#define CP_THREAD_CONTROL_0_SYNC_THREADS 0x80000000
2770
2771#define REG_CP_FIXED_STRIDE_DRAW_TABLE_IB_BASE 0x00000000
2772
2773#define REG_CP_FIXED_STRIDE_DRAW_TABLE_2 0x00000002
2774#define CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK 0x00000fff
2775#define CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT 0
2776static inline uint32_t CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE(uint32_t val)
2777{
2778 return ((val) << CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK;
2779}
2780#define CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK 0xfff00000
2781#define CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT 20
2782static inline uint32_t CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE(uint32_t val)
2783{
2784 return ((val) << CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK;
2785}
2786
2787#define REG_CP_FIXED_STRIDE_DRAW_TABLE_3 0x00000003
2788#define CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK 0xffffffff
2789#define CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT 0
2790static inline uint32_t CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT(uint32_t val)
2791{
2792 return ((val) << CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK;
2793}
2794
2795#define REG_CP_RESET_CONTEXT_STATE_0 0x00000000
2796#define CP_RESET_CONTEXT_STATE_0_CLEAR_ON_CHIP_TS 0x00000001
2797#define CP_RESET_CONTEXT_STATE_0_CLEAR_RESOURCE_TABLE 0x00000002
2798#define CP_RESET_CONTEXT_STATE_0_CLEAR_GLOBAL_LOCAL_TS 0x00000004
2799
2800#ifdef __cplusplus
2801#endif
2802
2803#endif /* ADRENO_PM4_XML */
2804

source code of linux/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h