| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef _DP_REG_H_ |
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| 7 | #define _DP_REG_H_ |
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| 8 | |
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| 9 | #include <linux/bitfield.h> |
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| 10 | #include <linux/bits.h> |
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| 11 | |
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| 12 | /* DP_TX Registers */ |
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| 13 | #define REG_DP_HW_VERSION (0x00000000) |
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| 14 | |
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| 15 | #define REG_DP_SW_RESET (0x00000010) |
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| 16 | #define DP_SW_RESET (0x00000001) |
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| 17 | |
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| 18 | #define REG_DP_PHY_CTRL (0x00000014) |
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| 19 | #define DP_PHY_CTRL_SW_RESET_PLL (0x00000001) |
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| 20 | #define DP_PHY_CTRL_SW_RESET (0x00000004) |
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| 21 | |
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| 22 | #define REG_DP_CLK_CTRL (0x00000018) |
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| 23 | #define REG_DP_CLK_ACTIVE (0x0000001C) |
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| 24 | #define REG_DP_INTR_STATUS (0x00000020) |
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| 25 | #define REG_DP_INTR_STATUS2 (0x00000024) |
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| 26 | #define REG_DP_INTR_STATUS3 (0x00000028) |
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| 27 | |
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| 28 | #define REG_DP_INTR_STATUS4 (0x0000002C) |
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| 29 | #define PSR_UPDATE_INT (0x00000001) |
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| 30 | #define PSR_CAPTURE_INT (0x00000004) |
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| 31 | #define PSR_EXIT_INT (0x00000010) |
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| 32 | #define PSR_UPDATE_ERROR_INT (0x00000040) |
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| 33 | #define PSR_WAKE_ERROR_INT (0x00000100) |
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| 34 | |
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| 35 | #define REG_DP_INTR_MASK4 (0x00000030) |
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| 36 | #define PSR_UPDATE_MASK (0x00000001) |
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| 37 | #define PSR_CAPTURE_MASK (0x00000002) |
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| 38 | #define PSR_EXIT_MASK (0x00000004) |
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| 39 | #define PSR_UPDATE_ERROR_MASK (0x00000008) |
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| 40 | #define PSR_WAKE_ERROR_MASK (0x00000010) |
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| 41 | |
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| 42 | #define REG_DP_DP_HPD_CTRL (0x00000000) |
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| 43 | #define DP_DP_HPD_CTRL_HPD_EN (0x00000001) |
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| 44 | |
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| 45 | #define REG_DP_DP_HPD_INT_STATUS (0x00000004) |
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| 46 | |
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| 47 | #define REG_DP_DP_HPD_INT_ACK (0x00000008) |
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| 48 | #define DP_DP_HPD_PLUG_INT_ACK (0x00000001) |
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| 49 | #define DP_DP_IRQ_HPD_INT_ACK (0x00000002) |
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| 50 | #define DP_DP_HPD_REPLUG_INT_ACK (0x00000004) |
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| 51 | #define DP_DP_HPD_UNPLUG_INT_ACK (0x00000008) |
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| 52 | #define DP_DP_HPD_STATE_STATUS_BITS_MASK (0x0000000F) |
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| 53 | #define DP_DP_HPD_STATE_STATUS_BITS_SHIFT (0x1C) |
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| 54 | |
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| 55 | #define REG_DP_DP_HPD_INT_MASK (0x0000000C) |
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| 56 | #define DP_DP_HPD_PLUG_INT_MASK (0x00000001) |
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| 57 | #define DP_DP_IRQ_HPD_INT_MASK (0x00000002) |
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| 58 | #define DP_DP_HPD_REPLUG_INT_MASK (0x00000004) |
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| 59 | #define DP_DP_HPD_UNPLUG_INT_MASK (0x00000008) |
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| 60 | #define DP_DP_HPD_INT_MASK (DP_DP_HPD_PLUG_INT_MASK | \ |
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| 61 | DP_DP_IRQ_HPD_INT_MASK | \ |
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| 62 | DP_DP_HPD_REPLUG_INT_MASK | \ |
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| 63 | DP_DP_HPD_UNPLUG_INT_MASK) |
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| 64 | #define DP_DP_HPD_STATE_STATUS_CONNECTED (0x40000000) |
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| 65 | #define DP_DP_HPD_STATE_STATUS_PENDING (0x20000000) |
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| 66 | #define DP_DP_HPD_STATE_STATUS_DISCONNECTED (0x00000000) |
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| 67 | #define DP_DP_HPD_STATE_STATUS_MASK (0xE0000000) |
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| 68 | |
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| 69 | #define REG_DP_DP_HPD_REFTIMER (0x00000018) |
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| 70 | #define DP_DP_HPD_REFTIMER_ENABLE (1 << 16) |
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| 71 | |
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| 72 | #define REG_DP_DP_HPD_EVENT_TIME_0 (0x0000001C) |
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| 73 | #define REG_DP_DP_HPD_EVENT_TIME_1 (0x00000020) |
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| 74 | #define DP_DP_HPD_EVENT_TIME_0_VAL (0x3E800FA) |
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| 75 | #define DP_DP_HPD_EVENT_TIME_1_VAL (0x1F407D0) |
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| 76 | |
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| 77 | #define REG_DP_AUX_CTRL (0x00000030) |
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| 78 | #define DP_AUX_CTRL_ENABLE (0x00000001) |
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| 79 | #define DP_AUX_CTRL_RESET (0x00000002) |
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| 80 | |
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| 81 | #define REG_DP_AUX_DATA (0x00000034) |
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| 82 | #define DP_AUX_DATA_READ (0x00000001) |
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| 83 | #define DP_AUX_DATA_WRITE (0x00000000) |
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| 84 | #define DP_AUX_DATA_OFFSET (0x00000008) |
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| 85 | #define DP_AUX_DATA_INDEX_OFFSET (0x00000010) |
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| 86 | #define DP_AUX_DATA_MASK (0x0000ff00) |
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| 87 | #define DP_AUX_DATA_INDEX_WRITE (0x80000000) |
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| 88 | |
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| 89 | #define REG_DP_AUX_TRANS_CTRL (0x00000038) |
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| 90 | #define DP_AUX_TRANS_CTRL_I2C (0x00000100) |
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| 91 | #define DP_AUX_TRANS_CTRL_GO (0x00000200) |
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| 92 | #define DP_AUX_TRANS_CTRL_NO_SEND_ADDR (0x00000400) |
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| 93 | #define DP_AUX_TRANS_CTRL_NO_SEND_STOP (0x00000800) |
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| 94 | |
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| 95 | #define REG_DP_TIMEOUT_COUNT (0x0000003C) |
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| 96 | #define REG_DP_AUX_LIMITS (0x00000040) |
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| 97 | #define REG_DP_AUX_STATUS (0x00000044) |
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| 98 | |
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| 99 | #define DP_DPCD_CP_IRQ (0x201) |
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| 100 | #define DP_DPCD_RXSTATUS (0x69493) |
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| 101 | |
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| 102 | #define DP_INTERRUPT_TRANS_NUM (0x000000A0) |
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| 103 | |
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| 104 | #define REG_DP_MAINLINK_CTRL (0x00000000) |
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| 105 | #define DP_MAINLINK_CTRL_ENABLE (0x00000001) |
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| 106 | #define DP_MAINLINK_CTRL_RESET (0x00000002) |
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| 107 | #define DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER (0x00000010) |
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| 108 | #define DP_MAINLINK_CTRL_FLUSH_MODE_MASK GENMASK(24, 23) |
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| 109 | #define DP_MAINLINK_FLUSH_MODE_UPDATE_SDP FIELD_PREP(DP_MAINLINK_CTRL_FLUSH_MODE_MASK, 1) |
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| 110 | #define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE FIELD_PREP(DP_MAINLINK_CTRL_FLUSH_MODE_MASK, 3) |
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| 111 | #define DP_MAINLINK_FB_BOUNDARY_SEL (0x02000000) |
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| 112 | |
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| 113 | #define REG_DP_STATE_CTRL (0x00000004) |
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| 114 | #define DP_STATE_CTRL_LINK_TRAINING_PATTERN1 (0x00000001) |
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| 115 | #define DP_STATE_CTRL_LINK_TRAINING_PATTERN2 (0x00000002) |
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| 116 | #define DP_STATE_CTRL_LINK_TRAINING_PATTERN3 (0x00000004) |
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| 117 | #define DP_STATE_CTRL_LINK_TRAINING_PATTERN4 (0x00000008) |
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| 118 | #define DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE (0x00000010) |
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| 119 | #define DP_STATE_CTRL_LINK_PRBS7 (0x00000020) |
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| 120 | #define DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN (0x00000040) |
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| 121 | #define DP_STATE_CTRL_SEND_VIDEO (0x00000080) |
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| 122 | #define DP_STATE_CTRL_PUSH_IDLE (0x00000100) |
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| 123 | |
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| 124 | #define REG_DP_CONFIGURATION_CTRL (0x00000008) |
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| 125 | #define DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK (0x00000001) |
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| 126 | #define DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN (0x00000002) |
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| 127 | #define DP_CONFIGURATION_CTRL_P_INTERLACED (0x00000004) |
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| 128 | #define DP_CONFIGURATION_CTRL_INTERLACED_BTF (0x00000008) |
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| 129 | #define DP_CONFIGURATION_CTRL_NUM_OF_LANES (0x00000010) |
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| 130 | #define DP_CONFIGURATION_CTRL_ENHANCED_FRAMING (0x00000040) |
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| 131 | #define DP_CONFIGURATION_CTRL_SEND_VSC (0x00000080) |
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| 132 | #define DP_CONFIGURATION_CTRL_BPC (0x00000100) |
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| 133 | #define DP_CONFIGURATION_CTRL_ASSR (0x00000400) |
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| 134 | #define DP_CONFIGURATION_CTRL_RGB_YUV (0x00000800) |
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| 135 | #define DP_CONFIGURATION_CTRL_LSCLK_DIV (0x00002000) |
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| 136 | #define DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT (0x04) |
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| 137 | #define DP_CONFIGURATION_CTRL_BPC_SHIFT (0x08) |
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| 138 | #define DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT (0x0D) |
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| 139 | |
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| 140 | #define REG_DP_SOFTWARE_MVID (0x00000010) |
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| 141 | #define REG_DP_SOFTWARE_NVID (0x00000018) |
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| 142 | #define REG_DP_TOTAL_HOR_VER (0x0000001C) |
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| 143 | #define REG_DP_START_HOR_VER_FROM_SYNC (0x00000020) |
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| 144 | #define REG_DP_HSYNC_VSYNC_WIDTH_POLARITY (0x00000024) |
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| 145 | #define REG_DP_ACTIVE_HOR_VER (0x00000028) |
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| 146 | |
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| 147 | #define REG_DP_MISC1_MISC0 (0x0000002C) |
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| 148 | #define DP_MISC0_SYNCHRONOUS_CLK (0x00000001) |
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| 149 | #define DP_MISC0_COLORIMETRY_CFG_SHIFT (0x00000001) |
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| 150 | #define DP_MISC0_TEST_BITS_DEPTH_SHIFT (0x00000005) |
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| 151 | #define DP_MISC1_VSC_SDP (0x00004000) |
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| 152 | |
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| 153 | #define DP_MISC0_COLORIMERY_CFG_LEGACY_RGB (0) |
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| 154 | #define DP_MISC0_COLORIMERY_CFG_CEA_RGB (0x04) |
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| 155 | |
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| 156 | #define REG_DP_VALID_BOUNDARY (0x00000030) |
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| 157 | #define REG_DP_VALID_BOUNDARY_2 (0x00000034) |
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| 158 | |
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| 159 | #define REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING (0x00000038) |
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| 160 | #define LANE0_MAPPING_SHIFT (0x00000000) |
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| 161 | #define LANE1_MAPPING_SHIFT (0x00000002) |
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| 162 | #define LANE2_MAPPING_SHIFT (0x00000004) |
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| 163 | #define LANE3_MAPPING_SHIFT (0x00000006) |
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| 164 | |
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| 165 | #define REG_DP_MAINLINK_READY (0x00000040) |
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| 166 | #define DP_MAINLINK_READY_FOR_VIDEO (0x00000001) |
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| 167 | #define DP_MAINLINK_READY_LINK_TRAINING_SHIFT (0x00000003) |
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| 168 | |
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| 169 | #define REG_DP_MAINLINK_LEVELS (0x00000044) |
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| 170 | #define DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2 (0x00000002) |
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| 171 | |
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| 172 | |
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| 173 | #define REG_DP_TU (0x0000004C) |
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| 174 | |
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| 175 | #define REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET (0x00000054) |
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| 176 | #define DP_HBR2_ERM_PATTERN (0x00010000) |
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| 177 | |
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| 178 | #define REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0 (0x000000C0) |
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| 179 | #define REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1 (0x000000C4) |
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| 180 | #define REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2 (0x000000C8) |
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| 181 | |
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| 182 | #define MMSS_DP_MISC1_MISC0 (0x0000002C) |
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| 183 | #define MMSS_DP_AUDIO_TIMING_GEN (0x00000080) |
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| 184 | #define MMSS_DP_AUDIO_TIMING_RBR_32 (0x00000084) |
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| 185 | #define MMSS_DP_AUDIO_TIMING_HBR_32 (0x00000088) |
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| 186 | #define MMSS_DP_AUDIO_TIMING_RBR_44 (0x0000008C) |
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| 187 | #define MMSS_DP_AUDIO_TIMING_HBR_44 (0x00000090) |
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| 188 | #define MMSS_DP_AUDIO_TIMING_RBR_48 (0x00000094) |
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| 189 | #define MMSS_DP_AUDIO_TIMING_HBR_48 (0x00000098) |
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| 190 | |
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| 191 | #define REG_PSR_CONFIG (0x00000100) |
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| 192 | #define DISABLE_PSR (0x00000000) |
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| 193 | #define PSR1_SUPPORTED (0x00000001) |
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| 194 | #define PSR2_WITHOUT_FRAMESYNC (0x00000002) |
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| 195 | #define PSR2_WITH_FRAMESYNC (0x00000003) |
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| 196 | |
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| 197 | #define REG_PSR_CMD (0x00000110) |
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| 198 | #define PSR_ENTER (0x00000001) |
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| 199 | #define PSR_EXIT (0x00000002) |
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| 200 | |
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| 201 | #define MMSS_DP_PSR_CRC_RG (0x00000154) |
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| 202 | #define MMSS_DP_PSR_CRC_B (0x00000158) |
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| 203 | |
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| 204 | #define REG_DP_COMPRESSION_MODE_CTRL (0x00000180) |
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| 205 | |
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| 206 | #define MMSS_DP_AUDIO_CFG (0x00000200) |
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| 207 | #define MMSS_DP_AUDIO_STATUS (0x00000204) |
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| 208 | #define MMSS_DP_AUDIO_PKT_CTRL (0x00000208) |
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| 209 | #define MMSS_DP_AUDIO_PKT_CTRL2 (0x0000020C) |
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| 210 | #define MMSS_DP_AUDIO_ACR_CTRL (0x00000210) |
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| 211 | #define MMSS_DP_AUDIO_CTRL_RESET (0x00000214) |
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| 212 | |
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| 213 | #define MMSS_DP_SDP_CFG (0x00000228) |
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| 214 | #define GEN0_SDP_EN (0x00020000) |
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| 215 | #define MMSS_DP_SDP_CFG2 (0x0000022C) |
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| 216 | #define MMSS_DP_AUDIO_TIMESTAMP_0 (0x00000230) |
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| 217 | #define MMSS_DP_AUDIO_TIMESTAMP_1 (0x00000234) |
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| 218 | #define GENERIC0_SDPSIZE_VALID (0x00010000) |
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| 219 | |
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| 220 | #define MMSS_DP_AUDIO_STREAM_0 (0x00000240) |
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| 221 | #define MMSS_DP_AUDIO_STREAM_1 (0x00000244) |
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| 222 | |
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| 223 | #define MMSS_DP_SDP_CFG3 (0x0000024c) |
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| 224 | #define UPDATE_SDP (0x00000001) |
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| 225 | |
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| 226 | #define MMSS_DP_EXTENSION_0 (0x00000250) |
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| 227 | #define MMSS_DP_EXTENSION_1 (0x00000254) |
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| 228 | #define MMSS_DP_EXTENSION_2 (0x00000258) |
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| 229 | #define MMSS_DP_EXTENSION_3 (0x0000025C) |
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| 230 | #define MMSS_DP_EXTENSION_4 (0x00000260) |
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| 231 | #define MMSS_DP_EXTENSION_5 (0x00000264) |
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| 232 | #define MMSS_DP_EXTENSION_6 (0x00000268) |
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| 233 | #define MMSS_DP_EXTENSION_7 (0x0000026C) |
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| 234 | #define MMSS_DP_EXTENSION_8 (0x00000270) |
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| 235 | #define MMSS_DP_EXTENSION_9 (0x00000274) |
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| 236 | #define MMSS_DP_AUDIO_COPYMANAGEMENT_0 (0x00000278) |
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| 237 | #define MMSS_DP_AUDIO_COPYMANAGEMENT_1 (0x0000027C) |
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| 238 | #define MMSS_DP_AUDIO_COPYMANAGEMENT_2 (0x00000280) |
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| 239 | #define MMSS_DP_AUDIO_COPYMANAGEMENT_3 (0x00000284) |
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| 240 | #define MMSS_DP_AUDIO_COPYMANAGEMENT_4 (0x00000288) |
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| 241 | #define MMSS_DP_AUDIO_COPYMANAGEMENT_5 (0x0000028C) |
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| 242 | #define MMSS_DP_AUDIO_ISRC_0 (0x00000290) |
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| 243 | #define MMSS_DP_AUDIO_ISRC_1 (0x00000294) |
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| 244 | #define MMSS_DP_AUDIO_ISRC_2 (0x00000298) |
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| 245 | #define MMSS_DP_AUDIO_ISRC_3 (0x0000029C) |
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| 246 | #define MMSS_DP_AUDIO_ISRC_4 (0x000002A0) |
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| 247 | #define MMSS_DP_AUDIO_ISRC_5 (0x000002A4) |
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| 248 | #define MMSS_DP_AUDIO_INFOFRAME_0 (0x000002A8) |
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| 249 | #define MMSS_DP_AUDIO_INFOFRAME_1 (0x000002AC) |
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| 250 | #define MMSS_DP_AUDIO_INFOFRAME_2 (0x000002B0) |
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| 251 | |
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| 252 | #define MMSS_DP_GENERIC0_0 (0x00000300) |
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| 253 | #define MMSS_DP_GENERIC0_1 (0x00000304) |
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| 254 | #define MMSS_DP_GENERIC0_2 (0x00000308) |
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| 255 | #define MMSS_DP_GENERIC0_3 (0x0000030C) |
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| 256 | #define MMSS_DP_GENERIC0_4 (0x00000310) |
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| 257 | #define MMSS_DP_GENERIC0_5 (0x00000314) |
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| 258 | #define MMSS_DP_GENERIC0_6 (0x00000318) |
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| 259 | #define MMSS_DP_GENERIC0_7 (0x0000031C) |
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| 260 | #define MMSS_DP_GENERIC0_8 (0x00000320) |
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| 261 | #define MMSS_DP_GENERIC0_9 (0x00000324) |
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| 262 | #define MMSS_DP_GENERIC1_0 (0x00000328) |
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| 263 | #define MMSS_DP_GENERIC1_1 (0x0000032C) |
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| 264 | #define MMSS_DP_GENERIC1_2 (0x00000330) |
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| 265 | #define MMSS_DP_GENERIC1_3 (0x00000334) |
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| 266 | #define MMSS_DP_GENERIC1_4 (0x00000338) |
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| 267 | #define MMSS_DP_GENERIC1_5 (0x0000033C) |
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| 268 | #define MMSS_DP_GENERIC1_6 (0x00000340) |
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| 269 | #define MMSS_DP_GENERIC1_7 (0x00000344) |
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| 270 | #define MMSS_DP_GENERIC1_8 (0x00000348) |
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| 271 | #define MMSS_DP_GENERIC1_9 (0x0000034C) |
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| 272 | |
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| 273 | #define MMSS_DP_VSCEXT_0 (0x000002D0) |
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| 274 | #define MMSS_DP_VSCEXT_1 (0x000002D4) |
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| 275 | #define MMSS_DP_VSCEXT_2 (0x000002D8) |
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| 276 | #define MMSS_DP_VSCEXT_3 (0x000002DC) |
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| 277 | #define MMSS_DP_VSCEXT_4 (0x000002E0) |
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| 278 | #define MMSS_DP_VSCEXT_5 (0x000002E4) |
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| 279 | #define MMSS_DP_VSCEXT_6 (0x000002E8) |
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| 280 | #define MMSS_DP_VSCEXT_7 (0x000002EC) |
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| 281 | #define MMSS_DP_VSCEXT_8 (0x000002F0) |
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| 282 | #define MMSS_DP_VSCEXT_9 (0x000002F4) |
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| 283 | |
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| 284 | #define MMSS_DP_BIST_ENABLE (0x00000000) |
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| 285 | #define DP_BIST_ENABLE_DPBIST_EN (0x00000001) |
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| 286 | |
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| 287 | #define MMSS_DP_TIMING_ENGINE_EN (0x00000010) |
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| 288 | #define DP_TIMING_ENGINE_EN_EN (0x00000001) |
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| 289 | |
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| 290 | #define MMSS_DP_INTF_CONFIG (0x00000014) |
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| 291 | #define MMSS_DP_INTF_HSYNC_CTL (0x00000018) |
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| 292 | #define MMSS_DP_INTF_VSYNC_PERIOD_F0 (0x0000001C) |
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| 293 | #define MMSS_DP_INTF_VSYNC_PERIOD_F1 (0x00000020) |
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| 294 | #define MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0 (0x00000024) |
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| 295 | #define MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1 (0x00000028) |
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| 296 | #define MMSS_INTF_DISPLAY_V_START_F0 (0x0000002C) |
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| 297 | #define MMSS_INTF_DISPLAY_V_START_F1 (0x00000030) |
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| 298 | #define MMSS_DP_INTF_DISPLAY_V_END_F0 (0x00000034) |
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| 299 | #define MMSS_DP_INTF_DISPLAY_V_END_F1 (0x00000038) |
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| 300 | #define MMSS_DP_INTF_ACTIVE_V_START_F0 (0x0000003C) |
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| 301 | #define MMSS_DP_INTF_ACTIVE_V_START_F1 (0x00000040) |
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| 302 | #define MMSS_DP_INTF_ACTIVE_V_END_F0 (0x00000044) |
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| 303 | #define MMSS_DP_INTF_ACTIVE_V_END_F1 (0x00000048) |
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| 304 | #define MMSS_DP_INTF_DISPLAY_HCTL (0x0000004C) |
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| 305 | #define MMSS_DP_INTF_ACTIVE_HCTL (0x00000050) |
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| 306 | #define MMSS_DP_INTF_POLARITY_CTL (0x00000058) |
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| 307 | |
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| 308 | #define MMSS_DP_TPG_MAIN_CONTROL (0x00000060) |
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| 309 | #define MMSS_DP_DSC_DTO (0x0000007C) |
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| 310 | #define DP_TPG_CHECKERED_RECT_PATTERN (0x00000100) |
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| 311 | |
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| 312 | #define MMSS_DP_TPG_VIDEO_CONFIG (0x00000064) |
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| 313 | #define DP_TPG_VIDEO_CONFIG_BPP_8BIT (0x00000001) |
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| 314 | #define DP_TPG_VIDEO_CONFIG_RGB (0x00000004) |
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| 315 | |
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| 316 | #define MMSS_DP_ASYNC_FIFO_CONFIG (0x00000088) |
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| 317 | |
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| 318 | #define REG_DP_PHY_AUX_INTERRUPT_CLEAR (0x0000004C) |
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| 319 | #define REG_DP_PHY_AUX_BIST_CFG (0x00000050) |
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| 320 | #define REG_DP_PHY_AUX_INTERRUPT_STATUS (0x000000BC) |
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| 321 | |
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| 322 | /* DP HDCP 1.3 registers */ |
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| 323 | #define DP_HDCP_CTRL (0x0A0) |
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| 324 | #define DP_HDCP_STATUS (0x0A4) |
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| 325 | #define DP_HDCP_SW_UPPER_AKSV (0x098) |
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| 326 | #define DP_HDCP_SW_LOWER_AKSV (0x09C) |
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| 327 | #define DP_HDCP_ENTROPY_CTRL0 (0x350) |
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| 328 | #define DP_HDCP_ENTROPY_CTRL1 (0x35C) |
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| 329 | #define DP_HDCP_SHA_STATUS (0x0C8) |
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| 330 | #define DP_HDCP_RCVPORT_DATA2_0 (0x0B0) |
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| 331 | #define DP_HDCP_RCVPORT_DATA3 (0x0A4) |
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| 332 | #define DP_HDCP_RCVPORT_DATA4 (0x0A8) |
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| 333 | #define DP_HDCP_RCVPORT_DATA5 (0x0C0) |
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| 334 | #define DP_HDCP_RCVPORT_DATA6 (0x0C4) |
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| 335 | |
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| 336 | #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_SHA_CTRL (0x024) |
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| 337 | #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_SHA_DATA (0x028) |
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| 338 | #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA0 (0x004) |
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| 339 | #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA1 (0x008) |
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| 340 | #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA7 (0x00C) |
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| 341 | #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA8 (0x010) |
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| 342 | #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA9 (0x014) |
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| 343 | #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA10 (0x018) |
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| 344 | #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA11 (0x01C) |
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| 345 | #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA12 (0x020) |
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| 346 | |
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| 347 | #endif /* _DP_REG_H_ */ |
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| 348 | |
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