1 | #ifndef DSI_XML |
2 | #define DSI_XML |
3 | |
4 | /* Autogenerated file, DO NOT EDIT manually! |
5 | |
6 | This file was generated by the rules-ng-ng headergen tool in this git repository: |
7 | http://github.com/freedreno/envytools/ |
8 | git clone https://github.com/freedreno/envytools.git |
9 | |
10 | The rules-ng-ng source files this header was generated from are: |
11 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46) |
12 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46) |
13 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42) |
14 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42) |
15 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42) |
16 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36) |
17 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42) |
18 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42) |
19 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42) |
20 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42) |
21 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42) |
22 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42) |
23 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42) |
24 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42) |
25 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42) |
26 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42) |
27 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56) |
28 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42) |
29 | |
30 | Copyright (C) 2013-2022 by the following authors: |
31 | - Rob Clark <robdclark@gmail.com> (robclark) |
32 | - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) |
33 | |
34 | Permission is hereby granted, free of charge, to any person obtaining |
35 | a copy of this software and associated documentation files (the |
36 | "Software"), to deal in the Software without restriction, including |
37 | without limitation the rights to use, copy, modify, merge, publish, |
38 | distribute, sublicense, and/or sell copies of the Software, and to |
39 | permit persons to whom the Software is furnished to do so, subject to |
40 | the following conditions: |
41 | |
42 | The above copyright notice and this permission notice (including the |
43 | next paragraph) shall be included in all copies or substantial |
44 | portions of the Software. |
45 | |
46 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
47 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
48 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
49 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
50 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
51 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
52 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
53 | */ |
54 | |
55 | |
56 | enum dsi_traffic_mode { |
57 | NON_BURST_SYNCH_PULSE = 0, |
58 | NON_BURST_SYNCH_EVENT = 1, |
59 | BURST_MODE = 2, |
60 | }; |
61 | |
62 | enum dsi_vid_dst_format { |
63 | VID_DST_FORMAT_RGB565 = 0, |
64 | VID_DST_FORMAT_RGB666 = 1, |
65 | VID_DST_FORMAT_RGB666_LOOSE = 2, |
66 | VID_DST_FORMAT_RGB888 = 3, |
67 | }; |
68 | |
69 | enum dsi_rgb_swap { |
70 | SWAP_RGB = 0, |
71 | SWAP_RBG = 1, |
72 | SWAP_BGR = 2, |
73 | SWAP_BRG = 3, |
74 | SWAP_GRB = 4, |
75 | SWAP_GBR = 5, |
76 | }; |
77 | |
78 | enum dsi_cmd_trigger { |
79 | TRIGGER_NONE = 0, |
80 | TRIGGER_SEOF = 1, |
81 | TRIGGER_TE = 2, |
82 | TRIGGER_SW = 4, |
83 | TRIGGER_SW_SEOF = 5, |
84 | TRIGGER_SW_TE = 6, |
85 | }; |
86 | |
87 | enum dsi_cmd_dst_format { |
88 | CMD_DST_FORMAT_RGB111 = 0, |
89 | CMD_DST_FORMAT_RGB332 = 3, |
90 | CMD_DST_FORMAT_RGB444 = 4, |
91 | CMD_DST_FORMAT_RGB565 = 6, |
92 | CMD_DST_FORMAT_RGB666 = 7, |
93 | CMD_DST_FORMAT_RGB888 = 8, |
94 | }; |
95 | |
96 | enum dsi_lane_swap { |
97 | LANE_SWAP_0123 = 0, |
98 | LANE_SWAP_3012 = 1, |
99 | LANE_SWAP_2301 = 2, |
100 | LANE_SWAP_1230 = 3, |
101 | LANE_SWAP_0321 = 4, |
102 | LANE_SWAP_1032 = 5, |
103 | LANE_SWAP_2103 = 6, |
104 | LANE_SWAP_3210 = 7, |
105 | }; |
106 | |
107 | enum video_config_bpp { |
108 | VIDEO_CONFIG_18BPP = 0, |
109 | VIDEO_CONFIG_24BPP = 1, |
110 | }; |
111 | |
112 | enum video_pattern_sel { |
113 | VID_PRBS = 0, |
114 | VID_INCREMENTAL = 1, |
115 | VID_FIXED = 2, |
116 | VID_MDSS_GENERAL_PATTERN = 3, |
117 | }; |
118 | |
119 | enum cmd_mdp_stream0_pattern_sel { |
120 | CMD_MDP_PRBS = 0, |
121 | CMD_MDP_INCREMENTAL = 1, |
122 | CMD_MDP_FIXED = 2, |
123 | CMD_MDP_MDSS_GENERAL_PATTERN = 3, |
124 | }; |
125 | |
126 | enum cmd_dma_pattern_sel { |
127 | CMD_DMA_PRBS = 0, |
128 | CMD_DMA_INCREMENTAL = 1, |
129 | CMD_DMA_FIXED = 2, |
130 | CMD_DMA_CUSTOM_PATTERN_DMA_FIFO = 3, |
131 | }; |
132 | |
133 | #define DSI_IRQ_CMD_DMA_DONE 0x00000001 |
134 | #define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002 |
135 | #define DSI_IRQ_CMD_MDP_DONE 0x00000100 |
136 | #define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200 |
137 | #define DSI_IRQ_VIDEO_DONE 0x00010000 |
138 | #define DSI_IRQ_MASK_VIDEO_DONE 0x00020000 |
139 | #define DSI_IRQ_BTA_DONE 0x00100000 |
140 | #define DSI_IRQ_MASK_BTA_DONE 0x00200000 |
141 | #define DSI_IRQ_ERROR 0x01000000 |
142 | #define DSI_IRQ_MASK_ERROR 0x02000000 |
143 | #define REG_DSI_6G_HW_VERSION 0x00000000 |
144 | #define DSI_6G_HW_VERSION_MAJOR__MASK 0xf0000000 |
145 | #define DSI_6G_HW_VERSION_MAJOR__SHIFT 28 |
146 | static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val) |
147 | { |
148 | return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK; |
149 | } |
150 | #define DSI_6G_HW_VERSION_MINOR__MASK 0x0fff0000 |
151 | #define DSI_6G_HW_VERSION_MINOR__SHIFT 16 |
152 | static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val) |
153 | { |
154 | return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK; |
155 | } |
156 | #define DSI_6G_HW_VERSION_STEP__MASK 0x0000ffff |
157 | #define DSI_6G_HW_VERSION_STEP__SHIFT 0 |
158 | static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val) |
159 | { |
160 | return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK; |
161 | } |
162 | |
163 | #define REG_DSI_CTRL 0x00000000 |
164 | #define DSI_CTRL_ENABLE 0x00000001 |
165 | #define DSI_CTRL_VID_MODE_EN 0x00000002 |
166 | #define DSI_CTRL_CMD_MODE_EN 0x00000004 |
167 | #define DSI_CTRL_LANE0 0x00000010 |
168 | #define DSI_CTRL_LANE1 0x00000020 |
169 | #define DSI_CTRL_LANE2 0x00000040 |
170 | #define DSI_CTRL_LANE3 0x00000080 |
171 | #define DSI_CTRL_CLK_EN 0x00000100 |
172 | #define DSI_CTRL_ECC_CHECK 0x00100000 |
173 | #define DSI_CTRL_CRC_CHECK 0x01000000 |
174 | |
175 | #define REG_DSI_STATUS0 0x00000004 |
176 | #define DSI_STATUS0_CMD_MODE_ENGINE_BUSY 0x00000001 |
177 | #define DSI_STATUS0_CMD_MODE_DMA_BUSY 0x00000002 |
178 | #define DSI_STATUS0_CMD_MODE_MDP_BUSY 0x00000004 |
179 | #define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY 0x00000008 |
180 | #define DSI_STATUS0_DSI_BUSY 0x00000010 |
181 | #define DSI_STATUS0_INTERLEAVE_OP_CONTENTION 0x80000000 |
182 | |
183 | #define REG_DSI_FIFO_STATUS 0x00000008 |
184 | #define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_OVERFLOW 0x00000001 |
185 | #define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_UNDERFLOW 0x00000008 |
186 | #define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW 0x00000080 |
187 | #define DSI_FIFO_STATUS_CMD_DMA_FIFO_RD_WATERMARK_REACH 0x00000100 |
188 | #define DSI_FIFO_STATUS_CMD_DMA_FIFO_WR_WATERMARK_REACH 0x00000200 |
189 | #define DSI_FIFO_STATUS_CMD_DMA_FIFO_UNDERFLOW 0x00000400 |
190 | #define DSI_FIFO_STATUS_DLN0_LP_FIFO_EMPTY 0x00001000 |
191 | #define DSI_FIFO_STATUS_DLN0_LP_FIFO_FULL 0x00002000 |
192 | #define DSI_FIFO_STATUS_DLN0_LP_FIFO_OVERFLOW 0x00004000 |
193 | #define DSI_FIFO_STATUS_DLN0_HS_FIFO_EMPTY 0x00010000 |
194 | #define DSI_FIFO_STATUS_DLN0_HS_FIFO_FULL 0x00020000 |
195 | #define DSI_FIFO_STATUS_DLN0_HS_FIFO_OVERFLOW 0x00040000 |
196 | #define DSI_FIFO_STATUS_DLN0_HS_FIFO_UNDERFLOW 0x00080000 |
197 | #define DSI_FIFO_STATUS_DLN1_HS_FIFO_EMPTY 0x00100000 |
198 | #define DSI_FIFO_STATUS_DLN1_HS_FIFO_FULL 0x00200000 |
199 | #define DSI_FIFO_STATUS_DLN1_HS_FIFO_OVERFLOW 0x00400000 |
200 | #define DSI_FIFO_STATUS_DLN1_HS_FIFO_UNDERFLOW 0x00800000 |
201 | #define DSI_FIFO_STATUS_DLN2_HS_FIFO_EMPTY 0x01000000 |
202 | #define DSI_FIFO_STATUS_DLN2_HS_FIFO_FULL 0x02000000 |
203 | #define DSI_FIFO_STATUS_DLN2_HS_FIFO_OVERFLOW 0x04000000 |
204 | #define DSI_FIFO_STATUS_DLN2_HS_FIFO_UNDERFLOW 0x08000000 |
205 | #define DSI_FIFO_STATUS_DLN3_HS_FIFO_EMPTY 0x10000000 |
206 | #define DSI_FIFO_STATUS_DLN3_HS_FIFO_FULL 0x20000000 |
207 | #define DSI_FIFO_STATUS_DLN3_HS_FIFO_OVERFLOW 0x40000000 |
208 | #define DSI_FIFO_STATUS_DLN3_HS_FIFO_UNDERFLOW 0x80000000 |
209 | |
210 | #define REG_DSI_VID_CFG0 0x0000000c |
211 | #define DSI_VID_CFG0_VIRT_CHANNEL__MASK 0x00000003 |
212 | #define DSI_VID_CFG0_VIRT_CHANNEL__SHIFT 0 |
213 | static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val) |
214 | { |
215 | return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK; |
216 | } |
217 | #define DSI_VID_CFG0_DST_FORMAT__MASK 0x00000030 |
218 | #define DSI_VID_CFG0_DST_FORMAT__SHIFT 4 |
219 | static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val) |
220 | { |
221 | return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK; |
222 | } |
223 | #define DSI_VID_CFG0_TRAFFIC_MODE__MASK 0x00000300 |
224 | #define DSI_VID_CFG0_TRAFFIC_MODE__SHIFT 8 |
225 | static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val) |
226 | { |
227 | return ((val) << DSI_VID_CFG0_TRAFFIC_MODE__SHIFT) & DSI_VID_CFG0_TRAFFIC_MODE__MASK; |
228 | } |
229 | #define DSI_VID_CFG0_BLLP_POWER_STOP 0x00001000 |
230 | #define DSI_VID_CFG0_EOF_BLLP_POWER_STOP 0x00008000 |
231 | #define DSI_VID_CFG0_HSA_POWER_STOP 0x00010000 |
232 | #define DSI_VID_CFG0_HBP_POWER_STOP 0x00100000 |
233 | #define DSI_VID_CFG0_HFP_POWER_STOP 0x01000000 |
234 | #define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x10000000 |
235 | |
236 | #define REG_DSI_VID_CFG1 0x0000001c |
237 | #define DSI_VID_CFG1_R_SEL 0x00000001 |
238 | #define DSI_VID_CFG1_G_SEL 0x00000010 |
239 | #define DSI_VID_CFG1_B_SEL 0x00000100 |
240 | #define DSI_VID_CFG1_RGB_SWAP__MASK 0x00007000 |
241 | #define DSI_VID_CFG1_RGB_SWAP__SHIFT 12 |
242 | static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val) |
243 | { |
244 | return ((val) << DSI_VID_CFG1_RGB_SWAP__SHIFT) & DSI_VID_CFG1_RGB_SWAP__MASK; |
245 | } |
246 | |
247 | #define REG_DSI_ACTIVE_H 0x00000020 |
248 | #define DSI_ACTIVE_H_START__MASK 0x00000fff |
249 | #define DSI_ACTIVE_H_START__SHIFT 0 |
250 | static inline uint32_t DSI_ACTIVE_H_START(uint32_t val) |
251 | { |
252 | return ((val) << DSI_ACTIVE_H_START__SHIFT) & DSI_ACTIVE_H_START__MASK; |
253 | } |
254 | #define DSI_ACTIVE_H_END__MASK 0x0fff0000 |
255 | #define DSI_ACTIVE_H_END__SHIFT 16 |
256 | static inline uint32_t DSI_ACTIVE_H_END(uint32_t val) |
257 | { |
258 | return ((val) << DSI_ACTIVE_H_END__SHIFT) & DSI_ACTIVE_H_END__MASK; |
259 | } |
260 | |
261 | #define REG_DSI_ACTIVE_V 0x00000024 |
262 | #define DSI_ACTIVE_V_START__MASK 0x00000fff |
263 | #define DSI_ACTIVE_V_START__SHIFT 0 |
264 | static inline uint32_t DSI_ACTIVE_V_START(uint32_t val) |
265 | { |
266 | return ((val) << DSI_ACTIVE_V_START__SHIFT) & DSI_ACTIVE_V_START__MASK; |
267 | } |
268 | #define DSI_ACTIVE_V_END__MASK 0x0fff0000 |
269 | #define DSI_ACTIVE_V_END__SHIFT 16 |
270 | static inline uint32_t DSI_ACTIVE_V_END(uint32_t val) |
271 | { |
272 | return ((val) << DSI_ACTIVE_V_END__SHIFT) & DSI_ACTIVE_V_END__MASK; |
273 | } |
274 | |
275 | #define REG_DSI_TOTAL 0x00000028 |
276 | #define DSI_TOTAL_H_TOTAL__MASK 0x00000fff |
277 | #define DSI_TOTAL_H_TOTAL__SHIFT 0 |
278 | static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val) |
279 | { |
280 | return ((val) << DSI_TOTAL_H_TOTAL__SHIFT) & DSI_TOTAL_H_TOTAL__MASK; |
281 | } |
282 | #define DSI_TOTAL_V_TOTAL__MASK 0x0fff0000 |
283 | #define DSI_TOTAL_V_TOTAL__SHIFT 16 |
284 | static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val) |
285 | { |
286 | return ((val) << DSI_TOTAL_V_TOTAL__SHIFT) & DSI_TOTAL_V_TOTAL__MASK; |
287 | } |
288 | |
289 | #define REG_DSI_ACTIVE_HSYNC 0x0000002c |
290 | #define DSI_ACTIVE_HSYNC_START__MASK 0x00000fff |
291 | #define DSI_ACTIVE_HSYNC_START__SHIFT 0 |
292 | static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val) |
293 | { |
294 | return ((val) << DSI_ACTIVE_HSYNC_START__SHIFT) & DSI_ACTIVE_HSYNC_START__MASK; |
295 | } |
296 | #define DSI_ACTIVE_HSYNC_END__MASK 0x0fff0000 |
297 | #define DSI_ACTIVE_HSYNC_END__SHIFT 16 |
298 | static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val) |
299 | { |
300 | return ((val) << DSI_ACTIVE_HSYNC_END__SHIFT) & DSI_ACTIVE_HSYNC_END__MASK; |
301 | } |
302 | |
303 | #define REG_DSI_ACTIVE_VSYNC_HPOS 0x00000030 |
304 | #define DSI_ACTIVE_VSYNC_HPOS_START__MASK 0x00000fff |
305 | #define DSI_ACTIVE_VSYNC_HPOS_START__SHIFT 0 |
306 | static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val) |
307 | { |
308 | return ((val) << DSI_ACTIVE_VSYNC_HPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_START__MASK; |
309 | } |
310 | #define DSI_ACTIVE_VSYNC_HPOS_END__MASK 0x0fff0000 |
311 | #define DSI_ACTIVE_VSYNC_HPOS_END__SHIFT 16 |
312 | static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val) |
313 | { |
314 | return ((val) << DSI_ACTIVE_VSYNC_HPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_END__MASK; |
315 | } |
316 | |
317 | #define REG_DSI_ACTIVE_VSYNC_VPOS 0x00000034 |
318 | #define DSI_ACTIVE_VSYNC_VPOS_START__MASK 0x00000fff |
319 | #define DSI_ACTIVE_VSYNC_VPOS_START__SHIFT 0 |
320 | static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val) |
321 | { |
322 | return ((val) << DSI_ACTIVE_VSYNC_VPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_START__MASK; |
323 | } |
324 | #define DSI_ACTIVE_VSYNC_VPOS_END__MASK 0x0fff0000 |
325 | #define DSI_ACTIVE_VSYNC_VPOS_END__SHIFT 16 |
326 | static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val) |
327 | { |
328 | return ((val) << DSI_ACTIVE_VSYNC_VPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_END__MASK; |
329 | } |
330 | |
331 | #define REG_DSI_CMD_DMA_CTRL 0x00000038 |
332 | #define DSI_CMD_DMA_CTRL_BROADCAST_EN 0x80000000 |
333 | #define DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER 0x10000000 |
334 | #define DSI_CMD_DMA_CTRL_LOW_POWER 0x04000000 |
335 | |
336 | #define REG_DSI_CMD_CFG0 0x0000003c |
337 | #define DSI_CMD_CFG0_DST_FORMAT__MASK 0x0000000f |
338 | #define DSI_CMD_CFG0_DST_FORMAT__SHIFT 0 |
339 | static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val) |
340 | { |
341 | return ((val) << DSI_CMD_CFG0_DST_FORMAT__SHIFT) & DSI_CMD_CFG0_DST_FORMAT__MASK; |
342 | } |
343 | #define DSI_CMD_CFG0_R_SEL 0x00000010 |
344 | #define DSI_CMD_CFG0_G_SEL 0x00000100 |
345 | #define DSI_CMD_CFG0_B_SEL 0x00001000 |
346 | #define DSI_CMD_CFG0_INTERLEAVE_MAX__MASK 0x00f00000 |
347 | #define DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT 20 |
348 | static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val) |
349 | { |
350 | return ((val) << DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT) & DSI_CMD_CFG0_INTERLEAVE_MAX__MASK; |
351 | } |
352 | #define DSI_CMD_CFG0_RGB_SWAP__MASK 0x00070000 |
353 | #define DSI_CMD_CFG0_RGB_SWAP__SHIFT 16 |
354 | static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val) |
355 | { |
356 | return ((val) << DSI_CMD_CFG0_RGB_SWAP__SHIFT) & DSI_CMD_CFG0_RGB_SWAP__MASK; |
357 | } |
358 | |
359 | #define REG_DSI_CMD_CFG1 0x00000040 |
360 | #define DSI_CMD_CFG1_WR_MEM_START__MASK 0x000000ff |
361 | #define DSI_CMD_CFG1_WR_MEM_START__SHIFT 0 |
362 | static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val) |
363 | { |
364 | return ((val) << DSI_CMD_CFG1_WR_MEM_START__SHIFT) & DSI_CMD_CFG1_WR_MEM_START__MASK; |
365 | } |
366 | #define DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK 0x0000ff00 |
367 | #define DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT 8 |
368 | static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val) |
369 | { |
370 | return ((val) << DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT) & DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK; |
371 | } |
372 | #define DSI_CMD_CFG1_INSERT_DCS_COMMAND 0x00010000 |
373 | |
374 | #define REG_DSI_DMA_BASE 0x00000044 |
375 | |
376 | #define REG_DSI_DMA_LEN 0x00000048 |
377 | |
378 | #define REG_DSI_CMD_MDP_STREAM0_CTRL 0x00000054 |
379 | #define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK 0x0000003f |
380 | #define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT 0 |
381 | static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(uint32_t val) |
382 | { |
383 | return ((val) << DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK; |
384 | } |
385 | #define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300 |
386 | #define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT 8 |
387 | static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(uint32_t val) |
388 | { |
389 | return ((val) << DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK; |
390 | } |
391 | #define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK 0xffff0000 |
392 | #define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT 16 |
393 | static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(uint32_t val) |
394 | { |
395 | return ((val) << DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK; |
396 | } |
397 | |
398 | #define REG_DSI_CMD_MDP_STREAM0_TOTAL 0x00000058 |
399 | #define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK 0x00000fff |
400 | #define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT 0 |
401 | static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(uint32_t val) |
402 | { |
403 | return ((val) << DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK; |
404 | } |
405 | #define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK 0x0fff0000 |
406 | #define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT 16 |
407 | static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(uint32_t val) |
408 | { |
409 | return ((val) << DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK; |
410 | } |
411 | |
412 | #define REG_DSI_CMD_MDP_STREAM1_CTRL 0x0000005c |
413 | #define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK 0x0000003f |
414 | #define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT 0 |
415 | static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE(uint32_t val) |
416 | { |
417 | return ((val) << DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK; |
418 | } |
419 | #define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300 |
420 | #define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT 8 |
421 | static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL(uint32_t val) |
422 | { |
423 | return ((val) << DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK; |
424 | } |
425 | #define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK 0xffff0000 |
426 | #define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT 16 |
427 | static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT(uint32_t val) |
428 | { |
429 | return ((val) << DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK; |
430 | } |
431 | |
432 | #define REG_DSI_CMD_MDP_STREAM1_TOTAL 0x00000060 |
433 | #define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK 0x0000ffff |
434 | #define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT 0 |
435 | static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL(uint32_t val) |
436 | { |
437 | return ((val) << DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK; |
438 | } |
439 | #define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK 0xffff0000 |
440 | #define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT 16 |
441 | static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL(uint32_t val) |
442 | { |
443 | return ((val) << DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK; |
444 | } |
445 | |
446 | #define REG_DSI_ACK_ERR_STATUS 0x00000064 |
447 | |
448 | static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; } |
449 | |
450 | static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; } |
451 | |
452 | #define REG_DSI_TRIG_CTRL 0x00000080 |
453 | #define DSI_TRIG_CTRL_DMA_TRIGGER__MASK 0x00000007 |
454 | #define DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT 0 |
455 | static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val) |
456 | { |
457 | return ((val) << DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT) & DSI_TRIG_CTRL_DMA_TRIGGER__MASK; |
458 | } |
459 | #define DSI_TRIG_CTRL_MDP_TRIGGER__MASK 0x00000070 |
460 | #define DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT 4 |
461 | static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val) |
462 | { |
463 | return ((val) << DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT) & DSI_TRIG_CTRL_MDP_TRIGGER__MASK; |
464 | } |
465 | #define DSI_TRIG_CTRL_STREAM__MASK 0x00000300 |
466 | #define DSI_TRIG_CTRL_STREAM__SHIFT 8 |
467 | static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val) |
468 | { |
469 | return ((val) << DSI_TRIG_CTRL_STREAM__SHIFT) & DSI_TRIG_CTRL_STREAM__MASK; |
470 | } |
471 | #define DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME 0x00001000 |
472 | #define DSI_TRIG_CTRL_TE 0x80000000 |
473 | |
474 | #define REG_DSI_TRIG_DMA 0x0000008c |
475 | |
476 | #define REG_DSI_DLN0_PHY_ERR 0x000000b0 |
477 | #define DSI_DLN0_PHY_ERR_DLN0_ERR_ESC 0x00000001 |
478 | #define DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC 0x00000010 |
479 | #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL 0x00000100 |
480 | #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 0x00001000 |
481 | #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1 0x00010000 |
482 | |
483 | #define REG_DSI_LP_TIMER_CTRL 0x000000b4 |
484 | #define DSI_LP_TIMER_CTRL_LP_RX_TO__MASK 0x0000ffff |
485 | #define DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT 0 |
486 | static inline uint32_t DSI_LP_TIMER_CTRL_LP_RX_TO(uint32_t val) |
487 | { |
488 | return ((val) << DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT) & DSI_LP_TIMER_CTRL_LP_RX_TO__MASK; |
489 | } |
490 | #define DSI_LP_TIMER_CTRL_BTA_TO__MASK 0xffff0000 |
491 | #define DSI_LP_TIMER_CTRL_BTA_TO__SHIFT 16 |
492 | static inline uint32_t DSI_LP_TIMER_CTRL_BTA_TO(uint32_t val) |
493 | { |
494 | return ((val) << DSI_LP_TIMER_CTRL_BTA_TO__SHIFT) & DSI_LP_TIMER_CTRL_BTA_TO__MASK; |
495 | } |
496 | |
497 | #define REG_DSI_HS_TIMER_CTRL 0x000000b8 |
498 | #define DSI_HS_TIMER_CTRL_HS_TX_TO__MASK 0x0000ffff |
499 | #define DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT 0 |
500 | static inline uint32_t DSI_HS_TIMER_CTRL_HS_TX_TO(uint32_t val) |
501 | { |
502 | return ((val) << DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT) & DSI_HS_TIMER_CTRL_HS_TX_TO__MASK; |
503 | } |
504 | #define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK 0x000f0000 |
505 | #define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT 16 |
506 | static inline uint32_t DSI_HS_TIMER_CTRL_TIMER_RESOLUTION(uint32_t val) |
507 | { |
508 | return ((val) << DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT) & DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK; |
509 | } |
510 | #define DSI_HS_TIMER_CTRL_HS_TX_TO_STOP_EN 0x10000000 |
511 | |
512 | #define REG_DSI_TIMEOUT_STATUS 0x000000bc |
513 | |
514 | #define REG_DSI_CLKOUT_TIMING_CTRL 0x000000c0 |
515 | #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK 0x0000003f |
516 | #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT 0 |
517 | static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val) |
518 | { |
519 | return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK; |
520 | } |
521 | #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK 0x00003f00 |
522 | #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT 8 |
523 | static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val) |
524 | { |
525 | return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK; |
526 | } |
527 | |
528 | #define REG_DSI_EOT_PACKET_CTRL 0x000000c8 |
529 | #define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001 |
530 | #define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010 |
531 | |
532 | #define REG_DSI_LANE_STATUS 0x000000a4 |
533 | #define DSI_LANE_STATUS_DLN0_STOPSTATE 0x00000001 |
534 | #define DSI_LANE_STATUS_DLN1_STOPSTATE 0x00000002 |
535 | #define DSI_LANE_STATUS_DLN2_STOPSTATE 0x00000004 |
536 | #define DSI_LANE_STATUS_DLN3_STOPSTATE 0x00000008 |
537 | #define DSI_LANE_STATUS_CLKLN_STOPSTATE 0x00000010 |
538 | #define DSI_LANE_STATUS_DLN0_ULPS_ACTIVE_NOT 0x00000100 |
539 | #define DSI_LANE_STATUS_DLN1_ULPS_ACTIVE_NOT 0x00000200 |
540 | #define DSI_LANE_STATUS_DLN2_ULPS_ACTIVE_NOT 0x00000400 |
541 | #define DSI_LANE_STATUS_DLN3_ULPS_ACTIVE_NOT 0x00000800 |
542 | #define DSI_LANE_STATUS_CLKLN_ULPS_ACTIVE_NOT 0x00001000 |
543 | #define DSI_LANE_STATUS_DLN0_DIRECTION 0x00010000 |
544 | |
545 | #define REG_DSI_LANE_CTRL 0x000000a8 |
546 | #define DSI_LANE_CTRL_HS_REQ_SEL_PHY 0x01000000 |
547 | #define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST 0x10000000 |
548 | |
549 | #define REG_DSI_LANE_SWAP_CTRL 0x000000ac |
550 | #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK 0x00000007 |
551 | #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT 0 |
552 | static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val) |
553 | { |
554 | return ((val) << DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT) & DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK; |
555 | } |
556 | |
557 | #define REG_DSI_ERR_INT_MASK0 0x00000108 |
558 | |
559 | #define REG_DSI_INTR_CTRL 0x0000010c |
560 | |
561 | #define REG_DSI_RESET 0x00000114 |
562 | |
563 | #define REG_DSI_CLK_CTRL 0x00000118 |
564 | #define DSI_CLK_CTRL_AHBS_HCLK_ON 0x00000001 |
565 | #define DSI_CLK_CTRL_AHBM_SCLK_ON 0x00000002 |
566 | #define DSI_CLK_CTRL_PCLK_ON 0x00000004 |
567 | #define DSI_CLK_CTRL_DSICLK_ON 0x00000008 |
568 | #define DSI_CLK_CTRL_BYTECLK_ON 0x00000010 |
569 | #define DSI_CLK_CTRL_ESCCLK_ON 0x00000020 |
570 | #define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK 0x00000200 |
571 | |
572 | #define REG_DSI_CLK_STATUS 0x0000011c |
573 | #define DSI_CLK_STATUS_DSI_AON_AHBM_HCLK_ACTIVE 0x00000001 |
574 | #define DSI_CLK_STATUS_DSI_DYN_AHBM_HCLK_ACTIVE 0x00000002 |
575 | #define DSI_CLK_STATUS_DSI_AON_AHBS_HCLK_ACTIVE 0x00000004 |
576 | #define DSI_CLK_STATUS_DSI_DYN_AHBS_HCLK_ACTIVE 0x00000008 |
577 | #define DSI_CLK_STATUS_DSI_AON_DSICLK_ACTIVE 0x00000010 |
578 | #define DSI_CLK_STATUS_DSI_DYN_DSICLK_ACTIVE 0x00000020 |
579 | #define DSI_CLK_STATUS_DSI_AON_BYTECLK_ACTIVE 0x00000040 |
580 | #define DSI_CLK_STATUS_DSI_DYN_BYTECLK_ACTIVE 0x00000080 |
581 | #define DSI_CLK_STATUS_DSI_AON_ESCCLK_ACTIVE 0x00000100 |
582 | #define DSI_CLK_STATUS_DSI_AON_PCLK_ACTIVE 0x00000200 |
583 | #define DSI_CLK_STATUS_DSI_DYN_PCLK_ACTIVE 0x00000400 |
584 | #define DSI_CLK_STATUS_DSI_DYN_CMD_PCLK_ACTIVE 0x00001000 |
585 | #define DSI_CLK_STATUS_DSI_CMD_PCLK_ACTIVE 0x00002000 |
586 | #define DSI_CLK_STATUS_DSI_VID_PCLK_ACTIVE 0x00004000 |
587 | #define DSI_CLK_STATUS_DSI_CAM_BIST_PCLK_ACT 0x00008000 |
588 | #define DSI_CLK_STATUS_PLL_UNLOCKED 0x00010000 |
589 | |
590 | #define REG_DSI_PHY_RESET 0x00000128 |
591 | #define DSI_PHY_RESET_RESET 0x00000001 |
592 | |
593 | #define REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL 0x00000160 |
594 | |
595 | #define REG_DSI_TPG_MAIN_CONTROL 0x00000198 |
596 | #define DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN 0x00000100 |
597 | |
598 | #define REG_DSI_TPG_VIDEO_CONFIG 0x000001a0 |
599 | #define DSI_TPG_VIDEO_CONFIG_BPP__MASK 0x00000003 |
600 | #define DSI_TPG_VIDEO_CONFIG_BPP__SHIFT 0 |
601 | static inline uint32_t DSI_TPG_VIDEO_CONFIG_BPP(enum video_config_bpp val) |
602 | { |
603 | return ((val) << DSI_TPG_VIDEO_CONFIG_BPP__SHIFT) & DSI_TPG_VIDEO_CONFIG_BPP__MASK; |
604 | } |
605 | #define DSI_TPG_VIDEO_CONFIG_RGB 0x00000004 |
606 | |
607 | #define REG_DSI_TEST_PATTERN_GEN_CTRL 0x00000158 |
608 | #define DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__MASK 0x00030000 |
609 | #define DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__SHIFT 16 |
610 | static inline uint32_t DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL(enum cmd_dma_pattern_sel val) |
611 | { |
612 | return ((val) << DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__SHIFT) & DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__MASK; |
613 | } |
614 | #define DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__MASK 0x00000300 |
615 | #define DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__SHIFT 8 |
616 | static inline uint32_t DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(enum cmd_mdp_stream0_pattern_sel val) |
617 | { |
618 | return ((val) << DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__SHIFT) & DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__MASK; |
619 | } |
620 | #define DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__MASK 0x00000030 |
621 | #define DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__SHIFT 4 |
622 | static inline uint32_t DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(enum video_pattern_sel val) |
623 | { |
624 | return ((val) << DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__SHIFT) & DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__MASK; |
625 | } |
626 | #define DSI_TEST_PATTERN_GEN_CTRL_TPG_DMA_FIFO_MODE 0x00000004 |
627 | #define DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_TPG_EN 0x00000002 |
628 | #define DSI_TEST_PATTERN_GEN_CTRL_EN 0x00000001 |
629 | |
630 | #define REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0 0x00000168 |
631 | |
632 | #define REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER 0x00000180 |
633 | #define DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER 0x00000001 |
634 | |
635 | #define REG_DSI_TPG_MAIN_CONTROL2 0x0000019c |
636 | #define DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN 0x00000080 |
637 | #define DSI_TPG_MAIN_CONTROL2_CMD_MDP1_CHECKERED_RECTANGLE_PATTERN 0x00010000 |
638 | #define DSI_TPG_MAIN_CONTROL2_CMD_MDP2_CHECKERED_RECTANGLE_PATTERN 0x02000000 |
639 | |
640 | #define REG_DSI_T_CLK_PRE_EXTEND 0x0000017c |
641 | #define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK 0x00000001 |
642 | |
643 | #define REG_DSI_CMD_MODE_MDP_CTRL2 0x000001b4 |
644 | #define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK 0x0000000f |
645 | #define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT 0 |
646 | static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2(enum dsi_cmd_dst_format val) |
647 | { |
648 | return ((val) << DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK; |
649 | } |
650 | #define DSI_CMD_MODE_MDP_CTRL2_R_SEL 0x00000010 |
651 | #define DSI_CMD_MODE_MDP_CTRL2_G_SEL 0x00000020 |
652 | #define DSI_CMD_MODE_MDP_CTRL2_B_SEL 0x00000040 |
653 | #define DSI_CMD_MODE_MDP_CTRL2_BYTE_MSB_LSB_FLIP 0x00000080 |
654 | #define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK 0x00000700 |
655 | #define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT 8 |
656 | static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP(enum dsi_rgb_swap val) |
657 | { |
658 | return ((val) << DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK; |
659 | } |
660 | #define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK 0x00007000 |
661 | #define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT 12 |
662 | static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP(enum dsi_rgb_swap val) |
663 | { |
664 | return ((val) << DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK; |
665 | } |
666 | #define DSI_CMD_MODE_MDP_CTRL2_BURST_MODE 0x00010000 |
667 | #define DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN 0x00100000 |
668 | |
669 | #define REG_DSI_CMD_MODE_MDP_STREAM2_CTRL 0x000001b8 |
670 | #define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK 0x0000003f |
671 | #define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT 0 |
672 | static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE(uint32_t val) |
673 | { |
674 | return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK; |
675 | } |
676 | #define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300 |
677 | #define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT 8 |
678 | static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL(uint32_t val) |
679 | { |
680 | return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK; |
681 | } |
682 | #define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK 0xffff0000 |
683 | #define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT 16 |
684 | static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT(uint32_t val) |
685 | { |
686 | return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK; |
687 | } |
688 | |
689 | #define REG_DSI_RDBK_DATA_CTRL 0x000001d0 |
690 | #define DSI_RDBK_DATA_CTRL_COUNT__MASK 0x00ff0000 |
691 | #define DSI_RDBK_DATA_CTRL_COUNT__SHIFT 16 |
692 | static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val) |
693 | { |
694 | return ((val) << DSI_RDBK_DATA_CTRL_COUNT__SHIFT) & DSI_RDBK_DATA_CTRL_COUNT__MASK; |
695 | } |
696 | #define DSI_RDBK_DATA_CTRL_CLR 0x00000001 |
697 | |
698 | #define REG_DSI_VERSION 0x000001f0 |
699 | #define DSI_VERSION_MAJOR__MASK 0xff000000 |
700 | #define DSI_VERSION_MAJOR__SHIFT 24 |
701 | static inline uint32_t DSI_VERSION_MAJOR(uint32_t val) |
702 | { |
703 | return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK; |
704 | } |
705 | |
706 | #define REG_DSI_CPHY_MODE_CTRL 0x000002d4 |
707 | |
708 | #define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL 0x0000029c |
709 | #define DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__MASK 0xffff0000 |
710 | #define DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__SHIFT 16 |
711 | static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_WC(uint32_t val) |
712 | { |
713 | return ((val) << DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__SHIFT) & DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__MASK; |
714 | } |
715 | #define DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__MASK 0x00003f00 |
716 | #define DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__SHIFT 8 |
717 | static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(uint32_t val) |
718 | { |
719 | return ((val) << DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__SHIFT) & DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__MASK; |
720 | } |
721 | #define DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__MASK 0x000000c0 |
722 | #define DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__SHIFT 6 |
723 | static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(uint32_t val) |
724 | { |
725 | return ((val) << DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__SHIFT) & DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__MASK; |
726 | } |
727 | #define DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__MASK 0x00000030 |
728 | #define DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__SHIFT 4 |
729 | static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(uint32_t val) |
730 | { |
731 | return ((val) << DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__SHIFT) & DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__MASK; |
732 | } |
733 | #define DSI_VIDEO_COMPRESSION_MODE_CTRL_EN 0x00000001 |
734 | |
735 | #define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL 0x000002a4 |
736 | #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__MASK 0x3f000000 |
737 | #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__SHIFT 24 |
738 | static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE(uint32_t val) |
739 | { |
740 | return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__MASK; |
741 | } |
742 | #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__MASK 0x00c00000 |
743 | #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__SHIFT 22 |
744 | static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE(uint32_t val) |
745 | { |
746 | return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__MASK; |
747 | } |
748 | #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__MASK 0x00300000 |
749 | #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__SHIFT 20 |
750 | static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM(uint32_t val) |
751 | { |
752 | return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__MASK; |
753 | } |
754 | #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EN 0x00010000 |
755 | #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__MASK 0x00003f00 |
756 | #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__SHIFT 8 |
757 | static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(uint32_t val) |
758 | { |
759 | return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__MASK; |
760 | } |
761 | #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__MASK 0x000000c0 |
762 | #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__SHIFT 6 |
763 | static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE(uint32_t val) |
764 | { |
765 | return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__MASK; |
766 | } |
767 | #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__MASK 0x00000030 |
768 | #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__SHIFT 4 |
769 | static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM(uint32_t val) |
770 | { |
771 | return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__MASK; |
772 | } |
773 | #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EN 0x00000001 |
774 | |
775 | #define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2 0x000002a8 |
776 | #define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__MASK 0xffff0000 |
777 | #define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__SHIFT 16 |
778 | static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH(uint32_t val) |
779 | { |
780 | return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__MASK; |
781 | } |
782 | #define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK 0x0000ffff |
783 | #define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__SHIFT 0 |
784 | static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(uint32_t val) |
785 | { |
786 | return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK; |
787 | } |
788 | |
789 | |
790 | #endif /* DSI_XML */ |
791 | |