| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2013-2016 Red Hat |
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| 4 | * Author: Rob Clark <robdclark@gmail.com> |
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| 5 | */ |
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| 6 | |
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| 7 | #ifndef __MSM_FENCE_H__ |
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| 8 | #define __MSM_FENCE_H__ |
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| 9 | |
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| 10 | #include "msm_drv.h" |
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| 11 | |
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| 12 | /** |
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| 13 | * struct msm_fence_context - fence context for gpu |
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| 14 | * |
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| 15 | * Each ringbuffer has a single fence context, with the GPU writing an |
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| 16 | * incrementing fence seqno at the end of each submit |
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| 17 | */ |
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| 18 | struct msm_fence_context { |
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| 19 | struct drm_device *dev; |
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| 20 | /** name: human readable name for fence timeline */ |
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| 21 | char name[32]; |
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| 22 | /** context: see dma_fence_context_alloc() */ |
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| 23 | unsigned context; |
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| 24 | /** index: similar to context, but local to msm_fence_context's */ |
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| 25 | unsigned index; |
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| 26 | |
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| 27 | /** |
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| 28 | * last_fence: |
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| 29 | * |
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| 30 | * Last assigned fence, incremented each time a fence is created |
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| 31 | * on this fence context. If last_fence == completed_fence, |
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| 32 | * there is no remaining pending work |
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| 33 | */ |
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| 34 | uint32_t last_fence; |
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| 35 | |
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| 36 | /** |
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| 37 | * completed_fence: |
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| 38 | * |
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| 39 | * The last completed fence, updated from the CPU after interrupt |
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| 40 | * from GPU |
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| 41 | */ |
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| 42 | uint32_t completed_fence; |
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| 43 | |
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| 44 | /** |
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| 45 | * fenceptr: |
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| 46 | * |
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| 47 | * The address that the GPU directly writes with completed fence |
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| 48 | * seqno. This can be ahead of completed_fence. We can peek at |
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| 49 | * this to see if a fence has already signaled but the CPU hasn't |
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| 50 | * gotten around to handling the irq and updating completed_fence |
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| 51 | */ |
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| 52 | volatile uint32_t *fenceptr; |
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| 53 | |
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| 54 | spinlock_t spinlock; |
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| 55 | |
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| 56 | /* |
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| 57 | * TODO this doesn't really deal with multiple deadlines, like |
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| 58 | * if userspace got multiple frames ahead.. OTOH atomic updates |
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| 59 | * don't queue, so maybe that is ok |
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| 60 | */ |
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| 61 | |
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| 62 | /** next_deadline: Time of next deadline */ |
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| 63 | ktime_t next_deadline; |
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| 64 | |
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| 65 | /** |
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| 66 | * next_deadline_fence: |
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| 67 | * |
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| 68 | * Fence value for next pending deadline. The deadline timer is |
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| 69 | * canceled when this fence is signaled. |
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| 70 | */ |
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| 71 | uint32_t next_deadline_fence; |
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| 72 | |
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| 73 | struct hrtimer deadline_timer; |
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| 74 | struct kthread_work deadline_work; |
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| 75 | }; |
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| 76 | |
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| 77 | struct msm_fence_context * msm_fence_context_alloc(struct drm_device *dev, |
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| 78 | volatile uint32_t *fenceptr, const char *name); |
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| 79 | void msm_fence_context_free(struct msm_fence_context *fctx); |
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| 80 | |
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| 81 | bool msm_fence_completed(struct msm_fence_context *fctx, uint32_t fence); |
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| 82 | void msm_update_fence(struct msm_fence_context *fctx, uint32_t fence); |
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| 83 | |
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| 84 | struct dma_fence * msm_fence_alloc(void); |
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| 85 | void msm_fence_init(struct dma_fence *fence, struct msm_fence_context *fctx); |
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| 86 | |
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| 87 | static inline bool |
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| 88 | fence_before(uint32_t a, uint32_t b) |
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| 89 | { |
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| 90 | return (int32_t)(a - b) < 0; |
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| 91 | } |
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| 92 | |
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| 93 | static inline bool |
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| 94 | fence_after(uint32_t a, uint32_t b) |
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| 95 | { |
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| 96 | return (int32_t)(a - b) > 0; |
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| 97 | } |
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| 98 | |
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| 99 | #endif |
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| 100 | |
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