1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * Copyright (C) 2022 Marek Vasut <marex@denx.de> |
4 | * |
5 | * i.MX8MP/i.MXRT LCDIF LCD controller driver. |
6 | */ |
7 | |
8 | #ifndef __LCDIF_REGS_H__ |
9 | #define __LCDIF_REGS_H__ |
10 | |
11 | #define REG_SET 4 |
12 | #define REG_CLR 8 |
13 | |
14 | /* V8 register set */ |
15 | #define LCDC_V8_CTRL 0x00 |
16 | #define LCDC_V8_DISP_PARA 0x10 |
17 | #define LCDC_V8_DISP_SIZE 0x14 |
18 | #define LCDC_V8_HSYN_PARA 0x18 |
19 | #define LCDC_V8_VSYN_PARA 0x1c |
20 | #define LCDC_V8_VSYN_HSYN_WIDTH 0x20 |
21 | #define LCDC_V8_INT_STATUS_D0 0x24 |
22 | #define LCDC_V8_INT_ENABLE_D0 0x28 |
23 | #define LCDC_V8_INT_STATUS_D1 0x30 |
24 | #define LCDC_V8_INT_ENABLE_D1 0x34 |
25 | #define LCDC_V8_CTRLDESCL0_1 0x200 |
26 | #define LCDC_V8_CTRLDESCL0_3 0x208 |
27 | #define LCDC_V8_CTRLDESCL_LOW0_4 0x20c |
28 | #define LCDC_V8_CTRLDESCL_HIGH0_4 0x210 |
29 | #define LCDC_V8_CTRLDESCL0_5 0x214 |
30 | #define LCDC_V8_CSC0_CTRL 0x21c |
31 | #define LCDC_V8_CSC0_COEF0 0x220 |
32 | #define LCDC_V8_CSC0_COEF1 0x224 |
33 | #define LCDC_V8_CSC0_COEF2 0x228 |
34 | #define LCDC_V8_CSC0_COEF3 0x22c |
35 | #define LCDC_V8_CSC0_COEF4 0x230 |
36 | #define LCDC_V8_CSC0_COEF5 0x234 |
37 | #define LCDC_V8_PANIC0_THRES 0x238 |
38 | |
39 | #define CTRL_SFTRST BIT(31) |
40 | #define CTRL_CLKGATE BIT(30) |
41 | #define CTRL_BYPASS_COUNT BIT(19) |
42 | #define CTRL_VSYNC_MODE BIT(18) |
43 | #define CTRL_DOTCLK_MODE BIT(17) |
44 | #define CTRL_DATA_SELECT BIT(16) |
45 | #define CTRL_BUS_WIDTH_16 (0 << 10) |
46 | #define CTRL_BUS_WIDTH_8 (1 << 10) |
47 | #define CTRL_BUS_WIDTH_18 (2 << 10) |
48 | #define CTRL_BUS_WIDTH_24 (3 << 10) |
49 | #define CTRL_BUS_WIDTH_MASK (0x3 << 10) |
50 | #define CTRL_WORD_LENGTH_16 (0 << 8) |
51 | #define CTRL_WORD_LENGTH_8 (1 << 8) |
52 | #define CTRL_WORD_LENGTH_18 (2 << 8) |
53 | #define CTRL_WORD_LENGTH_24 (3 << 8) |
54 | #define CTRL_MASTER BIT(5) |
55 | #define CTRL_DF16 BIT(3) |
56 | #define CTRL_DF18 BIT(2) |
57 | #define CTRL_DF24 BIT(1) |
58 | #define CTRL_RUN BIT(0) |
59 | |
60 | #define CTRL1_RECOVER_ON_UNDERFLOW BIT(24) |
61 | #define CTRL1_FIFO_CLEAR BIT(21) |
62 | #define CTRL1_SET_BYTE_PACKAGING(x) (((x) & 0xf) << 16) |
63 | #define CTRL1_GET_BYTE_PACKAGING(x) (((x) >> 16) & 0xf) |
64 | #define CTRL1_CUR_FRAME_DONE_IRQ_EN BIT(13) |
65 | #define CTRL1_CUR_FRAME_DONE_IRQ BIT(9) |
66 | |
67 | #define CTRL2_SET_OUTSTANDING_REQS_1 0 |
68 | #define CTRL2_SET_OUTSTANDING_REQS_2 (0x1 << 21) |
69 | #define CTRL2_SET_OUTSTANDING_REQS_4 (0x2 << 21) |
70 | #define CTRL2_SET_OUTSTANDING_REQS_8 (0x3 << 21) |
71 | #define CTRL2_SET_OUTSTANDING_REQS_16 (0x4 << 21) |
72 | #define CTRL2_SET_OUTSTANDING_REQS_MASK (0x7 << 21) |
73 | |
74 | #define TRANSFER_COUNT_SET_VCOUNT(x) (((x) & 0xffff) << 16) |
75 | #define TRANSFER_COUNT_GET_VCOUNT(x) (((x) >> 16) & 0xffff) |
76 | #define TRANSFER_COUNT_SET_HCOUNT(x) ((x) & 0xffff) |
77 | #define TRANSFER_COUNT_GET_HCOUNT(x) ((x) & 0xffff) |
78 | |
79 | #define VDCTRL0_ENABLE_PRESENT BIT(28) |
80 | #define VDCTRL0_VSYNC_ACT_HIGH BIT(27) |
81 | #define VDCTRL0_HSYNC_ACT_HIGH BIT(26) |
82 | #define VDCTRL0_DOTCLK_ACT_FALLING BIT(25) |
83 | #define VDCTRL0_ENABLE_ACT_HIGH BIT(24) |
84 | #define VDCTRL0_VSYNC_PERIOD_UNIT BIT(21) |
85 | #define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT BIT(20) |
86 | #define VDCTRL0_HALF_LINE BIT(19) |
87 | #define VDCTRL0_HALF_LINE_MODE BIT(18) |
88 | #define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff) |
89 | #define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff) |
90 | |
91 | #define VDCTRL2_SET_HSYNC_PERIOD(x) ((x) & 0x3ffff) |
92 | #define VDCTRL2_GET_HSYNC_PERIOD(x) ((x) & 0x3ffff) |
93 | |
94 | #define VDCTRL3_MUX_SYNC_SIGNALS BIT(29) |
95 | #define VDCTRL3_VSYNC_ONLY BIT(28) |
96 | #define SET_HOR_WAIT_CNT(x) (((x) & 0xfff) << 16) |
97 | #define GET_HOR_WAIT_CNT(x) (((x) >> 16) & 0xfff) |
98 | #define SET_VERT_WAIT_CNT(x) ((x) & 0xffff) |
99 | #define GET_VERT_WAIT_CNT(x) ((x) & 0xffff) |
100 | |
101 | #define VDCTRL4_SET_DOTCLK_DLY(x) (((x) & 0x7) << 29) /* v4 only */ |
102 | #define VDCTRL4_GET_DOTCLK_DLY(x) (((x) >> 29) & 0x7) /* v4 only */ |
103 | #define VDCTRL4_SYNC_SIGNALS_ON BIT(18) |
104 | #define SET_DOTCLK_H_VALID_DATA_CNT(x) ((x) & 0x3ffff) |
105 | |
106 | #define DEBUG0_HSYNC BIT(26) |
107 | #define DEBUG0_VSYNC BIT(25) |
108 | |
109 | #define AS_CTRL_PS_DISABLE BIT(23) |
110 | #define AS_CTRL_ALPHA_INVERT BIT(20) |
111 | #define AS_CTRL_ALPHA(a) (((a) & 0xff) << 8) |
112 | #define AS_CTRL_FORMAT_RGB565 (0xe << 4) |
113 | #define AS_CTRL_FORMAT_RGB444 (0xd << 4) |
114 | #define AS_CTRL_FORMAT_RGB555 (0xc << 4) |
115 | #define AS_CTRL_FORMAT_ARGB4444 (0x9 << 4) |
116 | #define AS_CTRL_FORMAT_ARGB1555 (0x8 << 4) |
117 | #define AS_CTRL_FORMAT_RGB888 (0x4 << 4) |
118 | #define AS_CTRL_FORMAT_ARGB8888 (0x0 << 4) |
119 | #define AS_CTRL_ENABLE_COLORKEY BIT(3) |
120 | #define AS_CTRL_ALPHA_CTRL_ROP (3 << 1) |
121 | #define AS_CTRL_ALPHA_CTRL_MULTIPLY (2 << 1) |
122 | #define AS_CTRL_ALPHA_CTRL_OVERRIDE (1 << 1) |
123 | #define AS_CTRL_ALPHA_CTRL_EMBEDDED (0 << 1) |
124 | #define AS_CTRL_AS_ENABLE BIT(0) |
125 | |
126 | /* V8 register set */ |
127 | #define CTRL_SW_RESET BIT(31) |
128 | #define CTRL_FETCH_START_OPTION_FPV 0 |
129 | #define CTRL_FETCH_START_OPTION_PWV BIT(8) |
130 | #define CTRL_FETCH_START_OPTION_BPV BIT(9) |
131 | #define CTRL_FETCH_START_OPTION_RESV GENMASK(9, 8) |
132 | #define CTRL_FETCH_START_OPTION_MASK GENMASK(9, 8) |
133 | #define CTRL_NEG BIT(4) |
134 | #define CTRL_INV_PXCK BIT(3) |
135 | #define CTRL_INV_DE BIT(2) |
136 | #define CTRL_INV_VS BIT(1) |
137 | #define CTRL_INV_HS BIT(0) |
138 | |
139 | #define DISP_PARA_DISP_ON BIT(31) |
140 | #define DISP_PARA_SWAP_EN BIT(30) |
141 | #define DISP_PARA_LINE_PATTERN_UYVY_H (0xd << 26) |
142 | #define DISP_PARA_LINE_PATTERN_RGB565 (0x7 << 26) |
143 | #define DISP_PARA_LINE_PATTERN_RGB888 (0x0 << 26) |
144 | #define DISP_PARA_LINE_PATTERN_MASK GENMASK(29, 26) |
145 | #define DISP_PARA_DISP_MODE_MASK GENMASK(25, 24) |
146 | #define DISP_PARA_BGND_R_MASK GENMASK(23, 16) |
147 | #define DISP_PARA_BGND_G_MASK GENMASK(15, 8) |
148 | #define DISP_PARA_BGND_B_MASK GENMASK(7, 0) |
149 | |
150 | #define DISP_SIZE_DELTA_Y(n) (((n) & 0xffff) << 16) |
151 | #define DISP_SIZE_DELTA_Y_MASK GENMASK(31, 16) |
152 | #define DISP_SIZE_DELTA_X(n) ((n) & 0xffff) |
153 | #define DISP_SIZE_DELTA_X_MASK GENMASK(15, 0) |
154 | |
155 | #define HSYN_PARA_BP_H(n) (((n) & 0xffff) << 16) |
156 | #define HSYN_PARA_BP_H_MASK GENMASK(31, 16) |
157 | #define HSYN_PARA_FP_H(n) ((n) & 0xffff) |
158 | #define HSYN_PARA_FP_H_MASK GENMASK(15, 0) |
159 | |
160 | #define VSYN_PARA_BP_V(n) (((n) & 0xffff) << 16) |
161 | #define VSYN_PARA_BP_V_MASK GENMASK(31, 16) |
162 | #define VSYN_PARA_FP_V(n) ((n) & 0xffff) |
163 | #define VSYN_PARA_FP_V_MASK GENMASK(15, 0) |
164 | |
165 | #define VSYN_HSYN_WIDTH_PW_V(n) (((n) & 0xffff) << 16) |
166 | #define VSYN_HSYN_WIDTH_PW_V_MASK GENMASK(31, 16) |
167 | #define VSYN_HSYN_WIDTH_PW_H(n) ((n) & 0xffff) |
168 | #define VSYN_HSYN_WIDTH_PW_H_MASK GENMASK(15, 0) |
169 | |
170 | #define INT_STATUS_D0_FIFO_EMPTY BIT(24) |
171 | #define INT_STATUS_D0_DMA_DONE BIT(16) |
172 | #define INT_STATUS_D0_DMA_ERR BIT(8) |
173 | #define INT_STATUS_D0_VS_BLANK BIT(2) |
174 | #define INT_STATUS_D0_UNDERRUN BIT(1) |
175 | #define INT_STATUS_D0_VSYNC BIT(0) |
176 | |
177 | #define INT_ENABLE_D0_FIFO_EMPTY_EN BIT(24) |
178 | #define INT_ENABLE_D0_DMA_DONE_EN BIT(16) |
179 | #define INT_ENABLE_D0_DMA_ERR_EN BIT(8) |
180 | #define INT_ENABLE_D0_VS_BLANK_EN BIT(2) |
181 | #define INT_ENABLE_D0_UNDERRUN_EN BIT(1) |
182 | #define INT_ENABLE_D0_VSYNC_EN BIT(0) |
183 | |
184 | #define INT_STATUS_D1_PLANE_PANIC BIT(0) |
185 | |
186 | #define INT_ENABLE_D1_PLANE_PANIC_EN BIT(0) |
187 | |
188 | #define CTRLDESCL0_1_HEIGHT(n) (((n) & 0xffff) << 16) |
189 | #define CTRLDESCL0_1_HEIGHT_MASK GENMASK(31, 16) |
190 | #define CTRLDESCL0_1_WIDTH(n) ((n) & 0xffff) |
191 | #define CTRLDESCL0_1_WIDTH_MASK GENMASK(15, 0) |
192 | |
193 | #define CTRLDESCL0_3_P_SIZE(n) (((n) << 20) & CTRLDESCL0_3_P_SIZE_MASK) |
194 | #define CTRLDESCL0_3_P_SIZE_MASK GENMASK(22, 20) |
195 | #define CTRLDESCL0_3_T_SIZE(n) (((n) << 16) & CTRLDESCL0_3_T_SIZE_MASK) |
196 | #define CTRLDESCL0_3_T_SIZE_MASK GENMASK(17, 16) |
197 | #define CTRLDESCL0_3_PITCH(n) ((n) & 0xffff) |
198 | #define CTRLDESCL0_3_PITCH_MASK GENMASK(15, 0) |
199 | |
200 | #define CTRLDESCL_HIGH0_4_ADDR_HIGH(n) ((n) & 0xf) |
201 | #define CTRLDESCL_HIGH0_4_ADDR_HIGH_MASK GENMASK(3, 0) |
202 | |
203 | #define CTRLDESCL0_5_EN BIT(31) |
204 | #define CTRLDESCL0_5_SHADOW_LOAD_EN BIT(30) |
205 | #define CTRLDESCL0_5_BPP_16_RGB565 (0x4 << 24) |
206 | #define CTRLDESCL0_5_BPP_16_ARGB1555 (0x5 << 24) |
207 | #define CTRLDESCL0_5_BPP_16_ARGB4444 (0x6 << 24) |
208 | #define CTRLDESCL0_5_BPP_YCbCr422 (0x7 << 24) |
209 | #define CTRLDESCL0_5_BPP_24_RGB888 (0x8 << 24) |
210 | #define CTRLDESCL0_5_BPP_32_ARGB8888 (0x9 << 24) |
211 | #define CTRLDESCL0_5_BPP_32_ABGR8888 (0xa << 24) |
212 | #define CTRLDESCL0_5_BPP_MASK GENMASK(27, 24) |
213 | #define CTRLDESCL0_5_YUV_FORMAT_Y2VY1U (0x0 << 14) |
214 | #define CTRLDESCL0_5_YUV_FORMAT_Y2UY1V (0x1 << 14) |
215 | #define CTRLDESCL0_5_YUV_FORMAT_VY2UY1 (0x2 << 14) |
216 | #define CTRLDESCL0_5_YUV_FORMAT_UY2VY1 (0x3 << 14) |
217 | #define CTRLDESCL0_5_YUV_FORMAT_MASK GENMASK(15, 14) |
218 | |
219 | #define CSC0_CTRL_CSC_MODE_YUV2RGB (0x0 << 1) |
220 | #define CSC0_CTRL_CSC_MODE_YCbCr2RGB (0x1 << 1) |
221 | #define CSC0_CTRL_CSC_MODE_RGB2YUV (0x2 << 1) |
222 | #define CSC0_CTRL_CSC_MODE_RGB2YCbCr (0x3 << 1) |
223 | #define CSC0_CTRL_CSC_MODE_MASK GENMASK(2, 1) |
224 | #define CSC0_CTRL_BYPASS BIT(0) |
225 | |
226 | #define CSC0_COEF0_A2(n) (((n) << 16) & CSC0_COEF0_A2_MASK) |
227 | #define CSC0_COEF0_A2_MASK GENMASK(26, 16) |
228 | #define CSC0_COEF0_A1(n) ((n) & CSC0_COEF0_A1_MASK) |
229 | #define CSC0_COEF0_A1_MASK GENMASK(10, 0) |
230 | |
231 | #define CSC0_COEF1_B1(n) (((n) << 16) & CSC0_COEF1_B1_MASK) |
232 | #define CSC0_COEF1_B1_MASK GENMASK(26, 16) |
233 | #define CSC0_COEF1_A3(n) ((n) & CSC0_COEF1_A3_MASK) |
234 | #define CSC0_COEF1_A3_MASK GENMASK(10, 0) |
235 | |
236 | #define CSC0_COEF2_B3(n) (((n) << 16) & CSC0_COEF2_B3_MASK) |
237 | #define CSC0_COEF2_B3_MASK GENMASK(26, 16) |
238 | #define CSC0_COEF2_B2(n) ((n) & CSC0_COEF2_B2_MASK) |
239 | #define CSC0_COEF2_B2_MASK GENMASK(10, 0) |
240 | |
241 | #define CSC0_COEF3_C2(n) (((n) << 16) & CSC0_COEF3_C2_MASK) |
242 | #define CSC0_COEF3_C2_MASK GENMASK(26, 16) |
243 | #define CSC0_COEF3_C1(n) ((n) & CSC0_COEF3_C1_MASK) |
244 | #define CSC0_COEF3_C1_MASK GENMASK(10, 0) |
245 | |
246 | #define CSC0_COEF4_D1(n) (((n) << 16) & CSC0_COEF4_D1_MASK) |
247 | #define CSC0_COEF4_D1_MASK GENMASK(24, 16) |
248 | #define CSC0_COEF4_C3(n) ((n) & CSC0_COEF4_C3_MASK) |
249 | #define CSC0_COEF4_C3_MASK GENMASK(10, 0) |
250 | |
251 | #define CSC0_COEF5_D3(n) (((n) << 16) & CSC0_COEF5_D3_MASK) |
252 | #define CSC0_COEF5_D3_MASK GENMASK(24, 16) |
253 | #define CSC0_COEF5_D2(n) ((n) & CSC0_COEF5_D2_MASK) |
254 | #define CSC0_COEF5_D2_MASK GENMASK(8, 0) |
255 | |
256 | #define PANIC0_THRES_LOW_MASK GENMASK(24, 16) |
257 | #define PANIC0_THRES_HIGH_MASK GENMASK(8, 0) |
258 | #define PANIC0_THRES_MAX 511 |
259 | |
260 | #define LCDIF_MIN_XRES 120 |
261 | #define LCDIF_MIN_YRES 120 |
262 | #define LCDIF_MAX_XRES 0xffff |
263 | #define LCDIF_MAX_YRES 0xffff |
264 | |
265 | #endif /* __LCDIF_REGS_H__ */ |
266 | |