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| 1 | /* SPDX-License-Identifier: MIT */ |
|---|---|
| 2 | #ifndef __NVIF_IF0012_H__ |
| 3 | #define __NVIF_IF0012_H__ |
| 4 | |
| 5 | #include <drm/display/drm_dp.h> |
| 6 | |
| 7 | union nvif_outp_args { |
| 8 | struct nvif_outp_v0 { |
| 9 | __u8 version; |
| 10 | __u8 id; /* DCB device index. */ |
| 11 | #define NVIF_OUTP_V0_TYPE_DAC 0x00 |
| 12 | #define NVIF_OUTP_V0_TYPE_SOR 0x01 |
| 13 | #define NVIF_OUTP_V0_TYPE_PIOR 0x02 |
| 14 | __u8 type; |
| 15 | #define NVIF_OUTP_V0_PROTO_RGB_CRT 0x00 |
| 16 | #define NVIF_OUTP_V0_PROTO_TMDS 0x01 |
| 17 | #define NVIF_OUTP_V0_PROTO_LVDS 0x02 |
| 18 | #define NVIF_OUTP_V0_PROTO_DP 0x03 |
| 19 | __u8 proto; |
| 20 | __u8 heads; |
| 21 | __u8 ddc; |
| 22 | __u8 conn; |
| 23 | union { |
| 24 | struct { |
| 25 | __u32 freq_max; |
| 26 | } rgb_crt; |
| 27 | struct { |
| 28 | __u8 dual; |
| 29 | } tmds; |
| 30 | struct { |
| 31 | __u8 acpi_edid; |
| 32 | } lvds; |
| 33 | struct { |
| 34 | __u8 aux; |
| 35 | __u8 mst; |
| 36 | __u8 increased_wm; |
| 37 | __u8 link_nr; |
| 38 | __u32 link_bw; |
| 39 | } dp; |
| 40 | }; |
| 41 | } v0; |
| 42 | }; |
| 43 | |
| 44 | #define NVIF_OUTP_V0_DETECT 0x00 |
| 45 | #define NVIF_OUTP_V0_EDID_GET 0x01 |
| 46 | |
| 47 | #define NVIF_OUTP_V0_INHERIT 0x10 |
| 48 | #define NVIF_OUTP_V0_ACQUIRE 0x11 |
| 49 | #define NVIF_OUTP_V0_RELEASE 0x12 |
| 50 | |
| 51 | #define NVIF_OUTP_V0_LOAD_DETECT 0x20 |
| 52 | |
| 53 | #define NVIF_OUTP_V0_BL_GET 0x30 |
| 54 | #define NVIF_OUTP_V0_BL_SET 0x31 |
| 55 | |
| 56 | #define NVIF_OUTP_V0_LVDS 0x40 |
| 57 | |
| 58 | #define NVIF_OUTP_V0_HDMI 0x50 |
| 59 | |
| 60 | #define NVIF_OUTP_V0_INFOFRAME 0x60 |
| 61 | #define NVIF_OUTP_V0_HDA_ELD 0x61 |
| 62 | |
| 63 | #define NVIF_OUTP_V0_DP_AUX_PWR 0x70 |
| 64 | #define NVIF_OUTP_V0_DP_AUX_XFER 0x71 |
| 65 | #define NVIF_OUTP_V0_DP_RATES 0x72 |
| 66 | #define NVIF_OUTP_V0_DP_TRAIN 0x73 |
| 67 | #define NVIF_OUTP_V0_DP_DRIVE 0x74 |
| 68 | #define NVIF_OUTP_V0_DP_SST 0x75 |
| 69 | #define NVIF_OUTP_V0_DP_MST_ID_GET 0x76 |
| 70 | #define NVIF_OUTP_V0_DP_MST_ID_PUT 0x77 |
| 71 | #define NVIF_OUTP_V0_DP_MST_VCPI 0x78 |
| 72 | |
| 73 | union nvif_outp_detect_args { |
| 74 | struct nvif_outp_detect_v0 { |
| 75 | __u8 version; |
| 76 | #define NVIF_OUTP_DETECT_V0_NOT_PRESENT 0x00 |
| 77 | #define NVIF_OUTP_DETECT_V0_PRESENT 0x01 |
| 78 | #define NVIF_OUTP_DETECT_V0_UNKNOWN 0x02 |
| 79 | __u8 status; |
| 80 | } v0; |
| 81 | }; |
| 82 | |
| 83 | union nvif_outp_edid_get_args { |
| 84 | struct nvif_outp_edid_get_v0 { |
| 85 | __u8 version; |
| 86 | __u8 pad01; |
| 87 | __u16 size; |
| 88 | __u8 data[2048]; |
| 89 | } v0; |
| 90 | }; |
| 91 | |
| 92 | union nvif_outp_load_detect_args { |
| 93 | struct nvif_outp_load_detect_v0 { |
| 94 | __u8 version; |
| 95 | __u8 load; |
| 96 | __u8 pad02[2]; |
| 97 | __u32 data; /*TODO: move vbios loadval parsing into nvkm */ |
| 98 | } v0; |
| 99 | }; |
| 100 | |
| 101 | union nvif_outp_acquire_args { |
| 102 | struct nvif_outp_acquire_v0 { |
| 103 | __u8 version; |
| 104 | #define NVIF_OUTP_ACQUIRE_V0_DAC 0x00 |
| 105 | #define NVIF_OUTP_ACQUIRE_V0_SOR 0x01 |
| 106 | #define NVIF_OUTP_ACQUIRE_V0_PIOR 0x02 |
| 107 | __u8 type; |
| 108 | __u8 or; |
| 109 | __u8 link; |
| 110 | __u8 pad04[4]; |
| 111 | union { |
| 112 | struct { |
| 113 | __u8 hda; |
| 114 | } sor; |
| 115 | }; |
| 116 | } v0; |
| 117 | }; |
| 118 | |
| 119 | union nvif_outp_inherit_args { |
| 120 | struct nvif_outp_inherit_v0 { |
| 121 | __u8 version; |
| 122 | #define NVIF_OUTP_INHERIT_V0_RGB_CRT 0x00 |
| 123 | #define NVIF_OUTP_INHERIT_V0_TV 0x01 |
| 124 | #define NVIF_OUTP_INHERIT_V0_TMDS 0x02 |
| 125 | #define NVIF_OUTP_INHERIT_V0_LVDS 0x03 |
| 126 | #define NVIF_OUTP_INHERIT_V0_DP 0x04 |
| 127 | // In/out. Input is one of the above values, output is the actual hw protocol |
| 128 | __u8 proto; |
| 129 | __u8 or; |
| 130 | __u8 link; |
| 131 | __u8 head; |
| 132 | union { |
| 133 | struct { |
| 134 | // TODO: Figure out padding, and whether we even want this field |
| 135 | __u8 hda; |
| 136 | } tmds; |
| 137 | }; |
| 138 | } v0; |
| 139 | }; |
| 140 | |
| 141 | union nvif_outp_release_args { |
| 142 | struct nvif_outp_release_vn { |
| 143 | } vn; |
| 144 | }; |
| 145 | |
| 146 | union nvif_outp_bl_get_args { |
| 147 | struct nvif_outp_bl_get_v0 { |
| 148 | __u8 version; |
| 149 | __u8 level; |
| 150 | } v0; |
| 151 | }; |
| 152 | |
| 153 | union nvif_outp_bl_set_args { |
| 154 | struct nvif_outp_bl_set_v0 { |
| 155 | __u8 version; |
| 156 | __u8 level; |
| 157 | } v0; |
| 158 | }; |
| 159 | |
| 160 | union nvif_outp_lvds_args { |
| 161 | struct nvif_outp_lvds_v0 { |
| 162 | __u8 version; |
| 163 | __u8 dual; |
| 164 | __u8 bpc8; |
| 165 | } v0; |
| 166 | }; |
| 167 | |
| 168 | union nvif_outp_hdmi_args { |
| 169 | struct nvif_outp_hdmi_v0 { |
| 170 | __u8 version; |
| 171 | __u8 head; |
| 172 | __u8 enable; |
| 173 | __u8 max_ac_packet; |
| 174 | __u8 rekey; |
| 175 | __u8 scdc; |
| 176 | __u8 scdc_scrambling; |
| 177 | __u8 scdc_low_rates; |
| 178 | __u32 khz; |
| 179 | } v0; |
| 180 | }; |
| 181 | |
| 182 | union nvif_outp_infoframe_args { |
| 183 | struct nvif_outp_infoframe_v0 { |
| 184 | __u8 version; |
| 185 | #define NVIF_OUTP_INFOFRAME_V0_AVI 0 |
| 186 | #define NVIF_OUTP_INFOFRAME_V0_VSI 1 |
| 187 | __u8 type; |
| 188 | __u8 head; |
| 189 | __u8 pad03[5]; |
| 190 | __u8 data[]; |
| 191 | } v0; |
| 192 | }; |
| 193 | |
| 194 | union nvif_outp_hda_eld_args { |
| 195 | struct nvif_outp_hda_eld_v0 { |
| 196 | __u8 version; |
| 197 | __u8 head; |
| 198 | __u8 pad02[6]; |
| 199 | __u8 data[]; |
| 200 | } v0; |
| 201 | }; |
| 202 | |
| 203 | union nvif_outp_dp_aux_pwr_args { |
| 204 | struct nvif_outp_dp_aux_pwr_v0 { |
| 205 | __u8 version; |
| 206 | __u8 state; |
| 207 | __u8 pad02[6]; |
| 208 | } v0; |
| 209 | }; |
| 210 | |
| 211 | union nvif_outp_dp_aux_xfer_args { |
| 212 | struct nvif_outp_dp_aux_xfer_v0 { |
| 213 | __u8 version; |
| 214 | __u8 pad01; |
| 215 | __u8 type; |
| 216 | __u8 size; |
| 217 | __u32 addr; |
| 218 | __u8 data[16]; |
| 219 | } v0; |
| 220 | }; |
| 221 | |
| 222 | union nvif_outp_dp_rates_args { |
| 223 | struct nvif_outp_dp_rates_v0 { |
| 224 | __u8 version; |
| 225 | __u8 pad01[6]; |
| 226 | __u8 rates; |
| 227 | struct { |
| 228 | __s8 dpcd; |
| 229 | __u32 rate; |
| 230 | } rate[8]; |
| 231 | } v0; |
| 232 | }; |
| 233 | |
| 234 | union nvif_outp_dp_train_args { |
| 235 | struct nvif_outp_dp_train_v0 { |
| 236 | __u8 version; |
| 237 | __u8 retrain; |
| 238 | __u8 mst; |
| 239 | __u8 lttprs; |
| 240 | __u8 post_lt_adj; |
| 241 | __u8 link_nr; |
| 242 | __u32 link_bw; |
| 243 | __u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
| 244 | } v0; |
| 245 | }; |
| 246 | |
| 247 | union nvif_outp_dp_drive_args { |
| 248 | struct nvif_outp_dp_drive_v0 { |
| 249 | __u8 version; |
| 250 | __u8 pad01[2]; |
| 251 | __u8 lanes; |
| 252 | __u8 pe[4]; |
| 253 | __u8 vs[4]; |
| 254 | } v0; |
| 255 | }; |
| 256 | |
| 257 | union nvif_outp_dp_sst_args { |
| 258 | struct nvif_outp_dp_sst_v0 { |
| 259 | __u8 version; |
| 260 | __u8 head; |
| 261 | __u8 pad02[2]; |
| 262 | __u32 watermark; |
| 263 | __u32 hblanksym; |
| 264 | __u32 vblanksym; |
| 265 | } v0; |
| 266 | }; |
| 267 | |
| 268 | union nvif_outp_dp_mst_id_put_args { |
| 269 | struct nvif_outp_dp_mst_id_put_v0 { |
| 270 | __u8 version; |
| 271 | __u8 pad01[3]; |
| 272 | __u32 id; |
| 273 | } v0; |
| 274 | }; |
| 275 | |
| 276 | union nvif_outp_dp_mst_id_get_args { |
| 277 | struct nvif_outp_dp_mst_id_get_v0 { |
| 278 | __u8 version; |
| 279 | __u8 pad01[3]; |
| 280 | __u32 id; |
| 281 | } v0; |
| 282 | }; |
| 283 | |
| 284 | union nvif_outp_dp_mst_vcpi_args { |
| 285 | struct nvif_outp_dp_mst_vcpi_v0 { |
| 286 | __u8 version; |
| 287 | __u8 head; |
| 288 | __u8 start_slot; |
| 289 | __u8 num_slots; |
| 290 | __u16 pbn; |
| 291 | __u16 aligned_pbn; |
| 292 | } v0; |
| 293 | }; |
| 294 | #endif |
| 295 |
Warning: This file is not a C or C++ file. It does not have highlighting.