1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (c) 2018 MediaTek Inc. |
4 | * Author: Jitao Shi <jitao.shi@mediatek.com> |
5 | */ |
6 | |
7 | #include <linux/delay.h> |
8 | #include <linux/gpio/consumer.h> |
9 | #include <linux/module.h> |
10 | #include <linux/of.h> |
11 | #include <linux/regulator/consumer.h> |
12 | |
13 | #include <drm/drm_connector.h> |
14 | #include <drm/drm_crtc.h> |
15 | #include <drm/drm_mipi_dsi.h> |
16 | #include <drm/drm_panel.h> |
17 | |
18 | #include <video/mipi_display.h> |
19 | |
20 | struct panel_desc { |
21 | const struct drm_display_mode *modes; |
22 | unsigned int bpc; |
23 | |
24 | /** |
25 | * @width_mm: width of the panel's active display area |
26 | * @height_mm: height of the panel's active display area |
27 | */ |
28 | struct { |
29 | unsigned int width_mm; |
30 | unsigned int height_mm; |
31 | } size; |
32 | |
33 | unsigned long mode_flags; |
34 | enum mipi_dsi_pixel_format format; |
35 | const struct panel_init_cmd *init_cmds; |
36 | unsigned int lanes; |
37 | bool discharge_on_disable; |
38 | bool lp11_before_reset; |
39 | }; |
40 | |
41 | struct boe_panel { |
42 | struct drm_panel base; |
43 | struct mipi_dsi_device *dsi; |
44 | |
45 | const struct panel_desc *desc; |
46 | |
47 | enum drm_panel_orientation orientation; |
48 | struct regulator *pp3300; |
49 | struct regulator *pp1800; |
50 | struct regulator *avee; |
51 | struct regulator *avdd; |
52 | struct gpio_desc *enable_gpio; |
53 | |
54 | bool prepared; |
55 | }; |
56 | |
57 | enum dsi_cmd_type { |
58 | INIT_DCS_CMD, |
59 | DELAY_CMD, |
60 | }; |
61 | |
62 | struct panel_init_cmd { |
63 | enum dsi_cmd_type type; |
64 | size_t len; |
65 | const char *data; |
66 | }; |
67 | |
68 | #define _INIT_DCS_CMD(...) { \ |
69 | .type = INIT_DCS_CMD, \ |
70 | .len = sizeof((char[]){__VA_ARGS__}), \ |
71 | .data = (char[]){__VA_ARGS__} } |
72 | |
73 | #define _INIT_DELAY_CMD(...) { \ |
74 | .type = DELAY_CMD,\ |
75 | .len = sizeof((char[]){__VA_ARGS__}), \ |
76 | .data = (char[]){__VA_ARGS__} } |
77 | |
78 | static const struct panel_init_cmd boe_tv110c9m_init_cmd[] = { |
79 | _INIT_DCS_CMD(0xFF, 0x20), |
80 | _INIT_DCS_CMD(0xFB, 0x01), |
81 | _INIT_DCS_CMD(0x05, 0xD9), |
82 | _INIT_DCS_CMD(0x07, 0x78), |
83 | _INIT_DCS_CMD(0x08, 0x5A), |
84 | _INIT_DCS_CMD(0x0D, 0x63), |
85 | _INIT_DCS_CMD(0x0E, 0x91), |
86 | _INIT_DCS_CMD(0x0F, 0x73), |
87 | _INIT_DCS_CMD(0x95, 0xE6), |
88 | _INIT_DCS_CMD(0x96, 0xF0), |
89 | _INIT_DCS_CMD(0x30, 0x00), |
90 | _INIT_DCS_CMD(0x6D, 0x66), |
91 | _INIT_DCS_CMD(0x75, 0xA2), |
92 | _INIT_DCS_CMD(0x77, 0x3B), |
93 | |
94 | _INIT_DCS_CMD(0xB0, 0x00, 0x08, 0x00, 0x23, 0x00, 0x4D, 0x00, 0x6D, 0x00, 0x89, 0x00, 0xA1, 0x00, 0xB6, 0x00, 0xC9), |
95 | _INIT_DCS_CMD(0xB1, 0x00, 0xDA, 0x01, 0x13, 0x01, 0x3C, 0x01, 0x7E, 0x01, 0xAB, 0x01, 0xF7, 0x02, 0x2F, 0x02, 0x31), |
96 | _INIT_DCS_CMD(0xB2, 0x02, 0x67, 0x02, 0xA6, 0x02, 0xD1, 0x03, 0x08, 0x03, 0x2E, 0x03, 0x5B, 0x03, 0x6B, 0x03, 0x7B), |
97 | _INIT_DCS_CMD(0xB3, 0x03, 0x8E, 0x03, 0xA2, 0x03, 0xB7, 0x03, 0xE7, 0x03, 0xFD, 0x03, 0xFF), |
98 | |
99 | _INIT_DCS_CMD(0xB4, 0x00, 0x08, 0x00, 0x23, 0x00, 0x4D, 0x00, 0x6D, 0x00, 0x89, 0x00, 0xA1, 0x00, 0xB6, 0x00, 0xC9), |
100 | _INIT_DCS_CMD(0xB5, 0x00, 0xDA, 0x01, 0x13, 0x01, 0x3C, 0x01, 0x7E, 0x01, 0xAB, 0x01, 0xF7, 0x02, 0x2F, 0x02, 0x31), |
101 | _INIT_DCS_CMD(0xB6, 0x02, 0x67, 0x02, 0xA6, 0x02, 0xD1, 0x03, 0x08, 0x03, 0x2E, 0x03, 0x5B, 0x03, 0x6B, 0x03, 0x7B), |
102 | _INIT_DCS_CMD(0xB7, 0x03, 0x8E, 0x03, 0xA2, 0x03, 0xB7, 0x03, 0xE7, 0x03, 0xFD, 0x03, 0xFF), |
103 | _INIT_DCS_CMD(0xB8, 0x00, 0x08, 0x00, 0x23, 0x00, 0x4D, 0x00, 0x6D, 0x00, 0x89, 0x00, 0xA1, 0x00, 0xB6, 0x00, 0xC9), |
104 | _INIT_DCS_CMD(0xB9, 0x00, 0xDA, 0x01, 0x13, 0x01, 0x3C, 0x01, 0x7E, 0x01, 0xAB, 0x01, 0xF7, 0x02, 0x2F, 0x02, 0x31), |
105 | _INIT_DCS_CMD(0xBA, 0x02, 0x67, 0x02, 0xA6, 0x02, 0xD1, 0x03, 0x08, 0x03, 0x2E, 0x03, 0x5B, 0x03, 0x6B, 0x03, 0x7B), |
106 | _INIT_DCS_CMD(0xBB, 0x03, 0x8E, 0x03, 0xA2, 0x03, 0xB7, 0x03, 0xE7, 0x03, 0xFD, 0x03, 0xFF), |
107 | |
108 | _INIT_DCS_CMD(0xFF, 0x21), |
109 | _INIT_DCS_CMD(0xFB, 0x01), |
110 | |
111 | _INIT_DCS_CMD(0xB0, 0x00, 0x00, 0x00, 0x1B, 0x00, 0x45, 0x00, 0x65, 0x00, 0x81, 0x00, 0x99, 0x00, 0xAE, 0x00, 0xC1), |
112 | _INIT_DCS_CMD(0xB1, 0x00, 0xD2, 0x01, 0x0B, 0x01, 0x34, 0x01, 0x76, 0x01, 0xA3, 0x01, 0xEF, 0x02, 0x27, 0x02, 0x29), |
113 | _INIT_DCS_CMD(0xB2, 0x02, 0x5F, 0x02, 0x9E, 0x02, 0xC9, 0x03, 0x00, 0x03, 0x26, 0x03, 0x53, 0x03, 0x63, 0x03, 0x73), |
114 | |
115 | _INIT_DCS_CMD(0xB3, 0x03, 0x86, 0x03, 0x9A, 0x03, 0xAF, 0x03, 0xDF, 0x03, 0xF5, 0x03, 0xE0), |
116 | _INIT_DCS_CMD(0xB4, 0x00, 0x00, 0x00, 0x1B, 0x00, 0x45, 0x00, 0x65, 0x00, 0x81, 0x00, 0x99, 0x00, 0xAE, 0x00, 0xC1), |
117 | _INIT_DCS_CMD(0xB5, 0x00, 0xD2, 0x01, 0x0B, 0x01, 0x34, 0x01, 0x76, 0x01, 0xA3, 0x01, 0xEF, 0x02, 0x27, 0x02, 0x29), |
118 | _INIT_DCS_CMD(0xB6, 0x02, 0x5F, 0x02, 0x9E, 0x02, 0xC9, 0x03, 0x00, 0x03, 0x26, 0x03, 0x53, 0x03, 0x63, 0x03, 0x73), |
119 | _INIT_DCS_CMD(0xB7, 0x03, 0x86, 0x03, 0x9A, 0x03, 0xAF, 0x03, 0xDF, 0x03, 0xF5, 0x03, 0xE0), |
120 | |
121 | _INIT_DCS_CMD(0xB8, 0x00, 0x00, 0x00, 0x1B, 0x00, 0x45, 0x00, 0x65, 0x00, 0x81, 0x00, 0x99, 0x00, 0xAE, 0x00, 0xC1), |
122 | _INIT_DCS_CMD(0xB9, 0x00, 0xD2, 0x01, 0x0B, 0x01, 0x34, 0x01, 0x76, 0x01, 0xA3, 0x01, 0xEF, 0x02, 0x27, 0x02, 0x29), |
123 | _INIT_DCS_CMD(0xBA, 0x02, 0x5F, 0x02, 0x9E, 0x02, 0xC9, 0x03, 0x00, 0x03, 0x26, 0x03, 0x53, 0x03, 0x63, 0x03, 0x73), |
124 | |
125 | _INIT_DCS_CMD(0xBB, 0x03, 0x86, 0x03, 0x9A, 0x03, 0xAF, 0x03, 0xDF, 0x03, 0xF5, 0x03, 0xE0), |
126 | _INIT_DCS_CMD(0xFF, 0x24), |
127 | _INIT_DCS_CMD(0xFB, 0x01), |
128 | |
129 | _INIT_DCS_CMD(0x00, 0x00), |
130 | _INIT_DCS_CMD(0x01, 0x00), |
131 | |
132 | _INIT_DCS_CMD(0x02, 0x1C), |
133 | _INIT_DCS_CMD(0x03, 0x1C), |
134 | |
135 | _INIT_DCS_CMD(0x04, 0x1D), |
136 | _INIT_DCS_CMD(0x05, 0x1D), |
137 | |
138 | _INIT_DCS_CMD(0x06, 0x04), |
139 | _INIT_DCS_CMD(0x07, 0x04), |
140 | |
141 | _INIT_DCS_CMD(0x08, 0x0F), |
142 | _INIT_DCS_CMD(0x09, 0x0F), |
143 | |
144 | _INIT_DCS_CMD(0x0A, 0x0E), |
145 | _INIT_DCS_CMD(0x0B, 0x0E), |
146 | |
147 | _INIT_DCS_CMD(0x0C, 0x0D), |
148 | _INIT_DCS_CMD(0x0D, 0x0D), |
149 | |
150 | _INIT_DCS_CMD(0x0E, 0x0C), |
151 | _INIT_DCS_CMD(0x0F, 0x0C), |
152 | |
153 | _INIT_DCS_CMD(0x10, 0x08), |
154 | _INIT_DCS_CMD(0x11, 0x08), |
155 | |
156 | _INIT_DCS_CMD(0x12, 0x00), |
157 | _INIT_DCS_CMD(0x13, 0x00), |
158 | _INIT_DCS_CMD(0x14, 0x00), |
159 | _INIT_DCS_CMD(0x15, 0x00), |
160 | |
161 | _INIT_DCS_CMD(0x16, 0x00), |
162 | _INIT_DCS_CMD(0x17, 0x00), |
163 | |
164 | _INIT_DCS_CMD(0x18, 0x1C), |
165 | _INIT_DCS_CMD(0x19, 0x1C), |
166 | |
167 | _INIT_DCS_CMD(0x1A, 0x1D), |
168 | _INIT_DCS_CMD(0x1B, 0x1D), |
169 | |
170 | _INIT_DCS_CMD(0x1C, 0x04), |
171 | _INIT_DCS_CMD(0x1D, 0x04), |
172 | |
173 | _INIT_DCS_CMD(0x1E, 0x0F), |
174 | _INIT_DCS_CMD(0x1F, 0x0F), |
175 | |
176 | _INIT_DCS_CMD(0x20, 0x0E), |
177 | _INIT_DCS_CMD(0x21, 0x0E), |
178 | |
179 | _INIT_DCS_CMD(0x22, 0x0D), |
180 | _INIT_DCS_CMD(0x23, 0x0D), |
181 | |
182 | _INIT_DCS_CMD(0x24, 0x0C), |
183 | _INIT_DCS_CMD(0x25, 0x0C), |
184 | |
185 | _INIT_DCS_CMD(0x26, 0x08), |
186 | _INIT_DCS_CMD(0x27, 0x08), |
187 | |
188 | _INIT_DCS_CMD(0x28, 0x00), |
189 | _INIT_DCS_CMD(0x29, 0x00), |
190 | _INIT_DCS_CMD(0x2A, 0x00), |
191 | _INIT_DCS_CMD(0x2B, 0x00), |
192 | |
193 | _INIT_DCS_CMD(0x2D, 0x20), |
194 | _INIT_DCS_CMD(0x2F, 0x0A), |
195 | _INIT_DCS_CMD(0x30, 0x44), |
196 | _INIT_DCS_CMD(0x33, 0x0C), |
197 | _INIT_DCS_CMD(0x34, 0x32), |
198 | |
199 | _INIT_DCS_CMD(0x37, 0x44), |
200 | _INIT_DCS_CMD(0x38, 0x40), |
201 | _INIT_DCS_CMD(0x39, 0x00), |
202 | _INIT_DCS_CMD(0x3A, 0x5D), |
203 | _INIT_DCS_CMD(0x3B, 0x60), |
204 | _INIT_DCS_CMD(0x3D, 0x42), |
205 | _INIT_DCS_CMD(0x3F, 0x06), |
206 | _INIT_DCS_CMD(0x43, 0x06), |
207 | _INIT_DCS_CMD(0x47, 0x66), |
208 | _INIT_DCS_CMD(0x4A, 0x5D), |
209 | _INIT_DCS_CMD(0x4B, 0x60), |
210 | _INIT_DCS_CMD(0x4C, 0x91), |
211 | _INIT_DCS_CMD(0x4D, 0x21), |
212 | _INIT_DCS_CMD(0x4E, 0x43), |
213 | _INIT_DCS_CMD(0x51, 0x12), |
214 | _INIT_DCS_CMD(0x52, 0x34), |
215 | _INIT_DCS_CMD(0x55, 0x82, 0x02), |
216 | _INIT_DCS_CMD(0x56, 0x04), |
217 | _INIT_DCS_CMD(0x58, 0x21), |
218 | _INIT_DCS_CMD(0x59, 0x30), |
219 | _INIT_DCS_CMD(0x5A, 0x60), |
220 | _INIT_DCS_CMD(0x5B, 0x50), |
221 | _INIT_DCS_CMD(0x5E, 0x00, 0x06), |
222 | _INIT_DCS_CMD(0x5F, 0x00), |
223 | _INIT_DCS_CMD(0x65, 0x82), |
224 | _INIT_DCS_CMD(0x7E, 0x20), |
225 | _INIT_DCS_CMD(0x7F, 0x3C), |
226 | _INIT_DCS_CMD(0x82, 0x04), |
227 | _INIT_DCS_CMD(0x97, 0xC0), |
228 | |
229 | _INIT_DCS_CMD(0xB6, 0x05, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x05, 0x00, 0x00), |
230 | _INIT_DCS_CMD(0x91, 0x44), |
231 | _INIT_DCS_CMD(0x92, 0xA9), |
232 | _INIT_DCS_CMD(0x93, 0x1A), |
233 | _INIT_DCS_CMD(0x94, 0x96), |
234 | _INIT_DCS_CMD(0xD7, 0x55), |
235 | _INIT_DCS_CMD(0xDA, 0x0A), |
236 | _INIT_DCS_CMD(0xDE, 0x08), |
237 | _INIT_DCS_CMD(0xDB, 0x05), |
238 | _INIT_DCS_CMD(0xDC, 0xA9), |
239 | _INIT_DCS_CMD(0xDD, 0x22), |
240 | |
241 | _INIT_DCS_CMD(0xDF, 0x05), |
242 | _INIT_DCS_CMD(0xE0, 0xA9), |
243 | _INIT_DCS_CMD(0xE1, 0x05), |
244 | _INIT_DCS_CMD(0xE2, 0xA9), |
245 | _INIT_DCS_CMD(0xE3, 0x05), |
246 | _INIT_DCS_CMD(0xE4, 0xA9), |
247 | _INIT_DCS_CMD(0xE5, 0x05), |
248 | _INIT_DCS_CMD(0xE6, 0xA9), |
249 | _INIT_DCS_CMD(0x5C, 0x00), |
250 | _INIT_DCS_CMD(0x5D, 0x00), |
251 | _INIT_DCS_CMD(0x8D, 0x00), |
252 | _INIT_DCS_CMD(0x8E, 0x00), |
253 | _INIT_DCS_CMD(0xB5, 0x90), |
254 | _INIT_DCS_CMD(0xFF, 0x25), |
255 | _INIT_DCS_CMD(0xFB, 0x01), |
256 | _INIT_DCS_CMD(0x05, 0x00), |
257 | _INIT_DCS_CMD(0x19, 0x07), |
258 | _INIT_DCS_CMD(0x1F, 0x60), |
259 | _INIT_DCS_CMD(0x20, 0x50), |
260 | _INIT_DCS_CMD(0x26, 0x60), |
261 | _INIT_DCS_CMD(0x27, 0x50), |
262 | _INIT_DCS_CMD(0x33, 0x60), |
263 | _INIT_DCS_CMD(0x34, 0x50), |
264 | _INIT_DCS_CMD(0x3F, 0xE0), |
265 | _INIT_DCS_CMD(0x40, 0x00), |
266 | _INIT_DCS_CMD(0x44, 0x00), |
267 | _INIT_DCS_CMD(0x45, 0x40), |
268 | _INIT_DCS_CMD(0x48, 0x60), |
269 | _INIT_DCS_CMD(0x49, 0x50), |
270 | _INIT_DCS_CMD(0x5B, 0x00), |
271 | _INIT_DCS_CMD(0x5C, 0x00), |
272 | _INIT_DCS_CMD(0x5D, 0x00), |
273 | _INIT_DCS_CMD(0x5E, 0xD0), |
274 | _INIT_DCS_CMD(0x61, 0x60), |
275 | _INIT_DCS_CMD(0x62, 0x50), |
276 | _INIT_DCS_CMD(0xF1, 0x10), |
277 | _INIT_DCS_CMD(0xFF, 0x2A), |
278 | _INIT_DCS_CMD(0xFB, 0x01), |
279 | |
280 | _INIT_DCS_CMD(0x64, 0x16), |
281 | _INIT_DCS_CMD(0x67, 0x16), |
282 | _INIT_DCS_CMD(0x6A, 0x16), |
283 | |
284 | _INIT_DCS_CMD(0x70, 0x30), |
285 | |
286 | _INIT_DCS_CMD(0xA2, 0xF3), |
287 | _INIT_DCS_CMD(0xA3, 0xFF), |
288 | _INIT_DCS_CMD(0xA4, 0xFF), |
289 | _INIT_DCS_CMD(0xA5, 0xFF), |
290 | |
291 | _INIT_DCS_CMD(0xD6, 0x08), |
292 | |
293 | _INIT_DCS_CMD(0xFF, 0x26), |
294 | _INIT_DCS_CMD(0xFB, 0x01), |
295 | _INIT_DCS_CMD(0x00, 0xA1), |
296 | |
297 | _INIT_DCS_CMD(0x02, 0x31), |
298 | _INIT_DCS_CMD(0x04, 0x28), |
299 | _INIT_DCS_CMD(0x06, 0x30), |
300 | _INIT_DCS_CMD(0x0C, 0x16), |
301 | _INIT_DCS_CMD(0x0D, 0x0D), |
302 | _INIT_DCS_CMD(0x0F, 0x00), |
303 | _INIT_DCS_CMD(0x11, 0x00), |
304 | _INIT_DCS_CMD(0x12, 0x50), |
305 | _INIT_DCS_CMD(0x13, 0x56), |
306 | _INIT_DCS_CMD(0x14, 0x57), |
307 | _INIT_DCS_CMD(0x15, 0x00), |
308 | _INIT_DCS_CMD(0x16, 0x10), |
309 | _INIT_DCS_CMD(0x17, 0xA0), |
310 | _INIT_DCS_CMD(0x18, 0x86), |
311 | _INIT_DCS_CMD(0x19, 0x0D), |
312 | _INIT_DCS_CMD(0x1A, 0x7F), |
313 | _INIT_DCS_CMD(0x1B, 0x0C), |
314 | _INIT_DCS_CMD(0x1C, 0xBF), |
315 | _INIT_DCS_CMD(0x22, 0x00), |
316 | _INIT_DCS_CMD(0x23, 0x00), |
317 | _INIT_DCS_CMD(0x2A, 0x0D), |
318 | _INIT_DCS_CMD(0x2B, 0x7F), |
319 | |
320 | _INIT_DCS_CMD(0x1D, 0x00), |
321 | _INIT_DCS_CMD(0x1E, 0x65), |
322 | _INIT_DCS_CMD(0x1F, 0x65), |
323 | _INIT_DCS_CMD(0x24, 0x00), |
324 | _INIT_DCS_CMD(0x25, 0x65), |
325 | _INIT_DCS_CMD(0x2F, 0x05), |
326 | _INIT_DCS_CMD(0x30, 0x65), |
327 | _INIT_DCS_CMD(0x31, 0x05), |
328 | _INIT_DCS_CMD(0x32, 0x7D), |
329 | _INIT_DCS_CMD(0x39, 0x00), |
330 | _INIT_DCS_CMD(0x3A, 0x65), |
331 | _INIT_DCS_CMD(0x20, 0x01), |
332 | _INIT_DCS_CMD(0x33, 0x11), |
333 | _INIT_DCS_CMD(0x34, 0x78), |
334 | _INIT_DCS_CMD(0x35, 0x16), |
335 | _INIT_DCS_CMD(0xC8, 0x04), |
336 | _INIT_DCS_CMD(0xC9, 0x9E), |
337 | _INIT_DCS_CMD(0xCA, 0x4E), |
338 | _INIT_DCS_CMD(0xCB, 0x00), |
339 | |
340 | _INIT_DCS_CMD(0xA9, 0x49), |
341 | _INIT_DCS_CMD(0xAA, 0x4B), |
342 | _INIT_DCS_CMD(0xAB, 0x48), |
343 | _INIT_DCS_CMD(0xAC, 0x43), |
344 | _INIT_DCS_CMD(0xAD, 0x40), |
345 | _INIT_DCS_CMD(0xAE, 0x50), |
346 | _INIT_DCS_CMD(0xAF, 0x44), |
347 | _INIT_DCS_CMD(0xB0, 0x54), |
348 | _INIT_DCS_CMD(0xB1, 0x4E), |
349 | _INIT_DCS_CMD(0xB2, 0x4D), |
350 | _INIT_DCS_CMD(0xB3, 0x4C), |
351 | _INIT_DCS_CMD(0xB4, 0x41), |
352 | _INIT_DCS_CMD(0xB5, 0x47), |
353 | _INIT_DCS_CMD(0xB6, 0x53), |
354 | _INIT_DCS_CMD(0xB7, 0x3E), |
355 | _INIT_DCS_CMD(0xB8, 0x51), |
356 | _INIT_DCS_CMD(0xB9, 0x3C), |
357 | _INIT_DCS_CMD(0xBA, 0x3B), |
358 | _INIT_DCS_CMD(0xBB, 0x46), |
359 | _INIT_DCS_CMD(0xBC, 0x45), |
360 | _INIT_DCS_CMD(0xBD, 0x55), |
361 | _INIT_DCS_CMD(0xBE, 0x3D), |
362 | _INIT_DCS_CMD(0xBF, 0x3F), |
363 | _INIT_DCS_CMD(0xC0, 0x52), |
364 | _INIT_DCS_CMD(0xC1, 0x4A), |
365 | _INIT_DCS_CMD(0xC2, 0x39), |
366 | _INIT_DCS_CMD(0xC3, 0x4F), |
367 | _INIT_DCS_CMD(0xC4, 0x3A), |
368 | _INIT_DCS_CMD(0xC5, 0x42), |
369 | _INIT_DCS_CMD(0xFF, 0x27), |
370 | _INIT_DCS_CMD(0xFB, 0x01), |
371 | |
372 | _INIT_DCS_CMD(0x56, 0x06), |
373 | _INIT_DCS_CMD(0x58, 0x80), |
374 | _INIT_DCS_CMD(0x59, 0x75), |
375 | _INIT_DCS_CMD(0x5A, 0x00), |
376 | _INIT_DCS_CMD(0x5B, 0x02), |
377 | _INIT_DCS_CMD(0x5C, 0x00), |
378 | _INIT_DCS_CMD(0x5D, 0x00), |
379 | _INIT_DCS_CMD(0x5E, 0x20), |
380 | _INIT_DCS_CMD(0x5F, 0x10), |
381 | _INIT_DCS_CMD(0x60, 0x00), |
382 | _INIT_DCS_CMD(0x61, 0x2E), |
383 | _INIT_DCS_CMD(0x62, 0x00), |
384 | _INIT_DCS_CMD(0x63, 0x01), |
385 | _INIT_DCS_CMD(0x64, 0x43), |
386 | _INIT_DCS_CMD(0x65, 0x2D), |
387 | _INIT_DCS_CMD(0x66, 0x00), |
388 | _INIT_DCS_CMD(0x67, 0x01), |
389 | _INIT_DCS_CMD(0x68, 0x44), |
390 | |
391 | _INIT_DCS_CMD(0x00, 0x00), |
392 | _INIT_DCS_CMD(0x78, 0x00), |
393 | _INIT_DCS_CMD(0xC3, 0x00), |
394 | |
395 | _INIT_DCS_CMD(0xFF, 0x2A), |
396 | _INIT_DCS_CMD(0xFB, 0x01), |
397 | |
398 | _INIT_DCS_CMD(0x22, 0x2F), |
399 | _INIT_DCS_CMD(0x23, 0x08), |
400 | |
401 | _INIT_DCS_CMD(0x24, 0x00), |
402 | _INIT_DCS_CMD(0x25, 0x65), |
403 | _INIT_DCS_CMD(0x26, 0xF8), |
404 | _INIT_DCS_CMD(0x27, 0x00), |
405 | _INIT_DCS_CMD(0x28, 0x1A), |
406 | _INIT_DCS_CMD(0x29, 0x00), |
407 | _INIT_DCS_CMD(0x2A, 0x1A), |
408 | _INIT_DCS_CMD(0x2B, 0x00), |
409 | _INIT_DCS_CMD(0x2D, 0x1A), |
410 | |
411 | _INIT_DCS_CMD(0xFF, 0x23), |
412 | _INIT_DCS_CMD(0xFB, 0x01), |
413 | |
414 | _INIT_DCS_CMD(0x00, 0x80), |
415 | _INIT_DCS_CMD(0x07, 0x00), |
416 | |
417 | _INIT_DCS_CMD(0xFF, 0xE0), |
418 | _INIT_DCS_CMD(0xFB, 0x01), |
419 | _INIT_DCS_CMD(0x14, 0x60), |
420 | _INIT_DCS_CMD(0x16, 0xC0), |
421 | |
422 | _INIT_DCS_CMD(0xFF, 0xF0), |
423 | _INIT_DCS_CMD(0xFB, 0x01), |
424 | _INIT_DCS_CMD(0x3A, 0x08), |
425 | |
426 | _INIT_DCS_CMD(0xFF, 0x10), |
427 | _INIT_DCS_CMD(0xFB, 0x01), |
428 | _INIT_DCS_CMD(0xB9, 0x01), |
429 | _INIT_DCS_CMD(0xFF, 0x20), |
430 | _INIT_DCS_CMD(0xFB, 0x01), |
431 | _INIT_DCS_CMD(0x18, 0x40), |
432 | |
433 | _INIT_DCS_CMD(0xFF, 0x10), |
434 | _INIT_DCS_CMD(0xFB, 0x01), |
435 | _INIT_DCS_CMD(0xB9, 0x02), |
436 | _INIT_DCS_CMD(0x35, 0x00), |
437 | _INIT_DCS_CMD(0x51, 0x00, 0xFF), |
438 | _INIT_DCS_CMD(0x53, 0x24), |
439 | _INIT_DCS_CMD(0x55, 0x00), |
440 | _INIT_DCS_CMD(0xBB, 0x13), |
441 | _INIT_DCS_CMD(0x3B, 0x03, 0x96, 0x1A, 0x04, 0x04), |
442 | _INIT_DELAY_CMD(100), |
443 | _INIT_DCS_CMD(0x11), |
444 | _INIT_DELAY_CMD(200), |
445 | _INIT_DCS_CMD(0x29), |
446 | _INIT_DELAY_CMD(100), |
447 | {}, |
448 | }; |
449 | |
450 | static const struct panel_init_cmd inx_hj110iz_init_cmd[] = { |
451 | _INIT_DCS_CMD(0xFF, 0x20), |
452 | _INIT_DCS_CMD(0xFB, 0x01), |
453 | _INIT_DCS_CMD(0x05, 0xD1), |
454 | _INIT_DCS_CMD(0x06, 0xC0), |
455 | _INIT_DCS_CMD(0x07, 0x87), |
456 | _INIT_DCS_CMD(0x08, 0x4B), |
457 | |
458 | _INIT_DCS_CMD(0x0D, 0x63), |
459 | _INIT_DCS_CMD(0x0E, 0x91), |
460 | _INIT_DCS_CMD(0x0F, 0x69), |
461 | _INIT_DCS_CMD(0x94, 0x00), |
462 | _INIT_DCS_CMD(0x95, 0xF5), |
463 | _INIT_DCS_CMD(0x96, 0xF5), |
464 | _INIT_DCS_CMD(0x9D, 0x00), |
465 | _INIT_DCS_CMD(0x9E, 0x00), |
466 | _INIT_DCS_CMD(0x69, 0x98), |
467 | _INIT_DCS_CMD(0x75, 0xA2), |
468 | _INIT_DCS_CMD(0x77, 0xB3), |
469 | |
470 | _INIT_DCS_CMD(0x58, 0x43), |
471 | _INIT_DCS_CMD(0xFF, 0x24), |
472 | _INIT_DCS_CMD(0xFB, 0x01), |
473 | _INIT_DCS_CMD(0x91, 0x44), |
474 | _INIT_DCS_CMD(0x92, 0x4C), |
475 | _INIT_DCS_CMD(0x94, 0x86), |
476 | _INIT_DCS_CMD(0x60, 0x96), |
477 | _INIT_DCS_CMD(0x61, 0xD0), |
478 | _INIT_DCS_CMD(0x63, 0x70), |
479 | _INIT_DCS_CMD(0xC2, 0xCA), |
480 | |
481 | _INIT_DCS_CMD(0x00, 0x03), |
482 | _INIT_DCS_CMD(0x01, 0x03), |
483 | _INIT_DCS_CMD(0x02, 0x03), |
484 | _INIT_DCS_CMD(0x03, 0x29), |
485 | _INIT_DCS_CMD(0x04, 0x22), |
486 | _INIT_DCS_CMD(0x05, 0x22), |
487 | _INIT_DCS_CMD(0x06, 0x0B), |
488 | _INIT_DCS_CMD(0x07, 0x1D), |
489 | _INIT_DCS_CMD(0x08, 0x1C), |
490 | _INIT_DCS_CMD(0x09, 0x05), |
491 | _INIT_DCS_CMD(0x0A, 0x08), |
492 | _INIT_DCS_CMD(0x0B, 0x09), |
493 | _INIT_DCS_CMD(0x0C, 0x0A), |
494 | _INIT_DCS_CMD(0x0D, 0x0C), |
495 | _INIT_DCS_CMD(0x0E, 0x0D), |
496 | _INIT_DCS_CMD(0x0F, 0x0E), |
497 | _INIT_DCS_CMD(0x10, 0x0F), |
498 | _INIT_DCS_CMD(0x11, 0x10), |
499 | _INIT_DCS_CMD(0x12, 0x11), |
500 | _INIT_DCS_CMD(0x13, 0x04), |
501 | _INIT_DCS_CMD(0x14, 0x00), |
502 | _INIT_DCS_CMD(0x15, 0x03), |
503 | _INIT_DCS_CMD(0x16, 0x03), |
504 | _INIT_DCS_CMD(0x17, 0x03), |
505 | _INIT_DCS_CMD(0x18, 0x03), |
506 | _INIT_DCS_CMD(0x19, 0x29), |
507 | _INIT_DCS_CMD(0x1A, 0x22), |
508 | _INIT_DCS_CMD(0x1B, 0x22), |
509 | _INIT_DCS_CMD(0x1C, 0x0B), |
510 | _INIT_DCS_CMD(0x1D, 0x1D), |
511 | _INIT_DCS_CMD(0x1E, 0x1C), |
512 | _INIT_DCS_CMD(0x1F, 0x05), |
513 | _INIT_DCS_CMD(0x20, 0x08), |
514 | _INIT_DCS_CMD(0x21, 0x09), |
515 | _INIT_DCS_CMD(0x22, 0x0A), |
516 | _INIT_DCS_CMD(0x23, 0x0C), |
517 | _INIT_DCS_CMD(0x24, 0x0D), |
518 | _INIT_DCS_CMD(0x25, 0x0E), |
519 | _INIT_DCS_CMD(0x26, 0x0F), |
520 | _INIT_DCS_CMD(0x27, 0x10), |
521 | _INIT_DCS_CMD(0x28, 0x11), |
522 | _INIT_DCS_CMD(0x29, 0x04), |
523 | _INIT_DCS_CMD(0x2A, 0x00), |
524 | _INIT_DCS_CMD(0x2B, 0x03), |
525 | |
526 | _INIT_DCS_CMD(0x2F, 0x0A), |
527 | _INIT_DCS_CMD(0x30, 0x35), |
528 | _INIT_DCS_CMD(0x37, 0xA7), |
529 | _INIT_DCS_CMD(0x39, 0x00), |
530 | _INIT_DCS_CMD(0x3A, 0x46), |
531 | _INIT_DCS_CMD(0x3B, 0x32), |
532 | _INIT_DCS_CMD(0x3D, 0x12), |
533 | |
534 | _INIT_DCS_CMD(0x3F, 0x33), |
535 | _INIT_DCS_CMD(0x40, 0x31), |
536 | _INIT_DCS_CMD(0x41, 0x40), |
537 | _INIT_DCS_CMD(0x42, 0x42), |
538 | _INIT_DCS_CMD(0x47, 0x77), |
539 | _INIT_DCS_CMD(0x48, 0x77), |
540 | _INIT_DCS_CMD(0x4A, 0x45), |
541 | _INIT_DCS_CMD(0x4B, 0x45), |
542 | _INIT_DCS_CMD(0x4C, 0x14), |
543 | |
544 | _INIT_DCS_CMD(0x4D, 0x21), |
545 | _INIT_DCS_CMD(0x4E, 0x43), |
546 | _INIT_DCS_CMD(0x4F, 0x65), |
547 | _INIT_DCS_CMD(0x55, 0x06), |
548 | _INIT_DCS_CMD(0x56, 0x06), |
549 | _INIT_DCS_CMD(0x58, 0x21), |
550 | _INIT_DCS_CMD(0x59, 0x70), |
551 | _INIT_DCS_CMD(0x5A, 0x46), |
552 | _INIT_DCS_CMD(0x5B, 0x32), |
553 | _INIT_DCS_CMD(0x5C, 0x88), |
554 | _INIT_DCS_CMD(0x5E, 0x00, 0x00), |
555 | _INIT_DCS_CMD(0x5F, 0x00), |
556 | |
557 | _INIT_DCS_CMD(0x7A, 0xFF), |
558 | _INIT_DCS_CMD(0x7B, 0xFF), |
559 | _INIT_DCS_CMD(0x7C, 0x00), |
560 | _INIT_DCS_CMD(0x7D, 0x00), |
561 | _INIT_DCS_CMD(0x7E, 0x20), |
562 | _INIT_DCS_CMD(0x7F, 0x3C), |
563 | _INIT_DCS_CMD(0x80, 0x00), |
564 | _INIT_DCS_CMD(0x81, 0x00), |
565 | _INIT_DCS_CMD(0x82, 0x08), |
566 | _INIT_DCS_CMD(0x97, 0x02), |
567 | _INIT_DCS_CMD(0xC5, 0x10), |
568 | |
569 | _INIT_DCS_CMD(0xD7, 0x55), |
570 | _INIT_DCS_CMD(0xD8, 0x55), |
571 | _INIT_DCS_CMD(0xD9, 0x23), |
572 | _INIT_DCS_CMD(0xDA, 0x05), |
573 | _INIT_DCS_CMD(0xDB, 0x01), |
574 | _INIT_DCS_CMD(0xDC, 0x65), |
575 | _INIT_DCS_CMD(0xDD, 0x55), |
576 | _INIT_DCS_CMD(0xDE, 0x27), |
577 | _INIT_DCS_CMD(0xDF, 0x01), |
578 | _INIT_DCS_CMD(0xE0, 0x65), |
579 | _INIT_DCS_CMD(0xE1, 0x01), |
580 | _INIT_DCS_CMD(0xE2, 0x65), |
581 | _INIT_DCS_CMD(0xE3, 0x01), |
582 | _INIT_DCS_CMD(0xE4, 0x65), |
583 | _INIT_DCS_CMD(0xE5, 0x01), |
584 | _INIT_DCS_CMD(0xE6, 0x65), |
585 | _INIT_DCS_CMD(0xE7, 0x00), |
586 | _INIT_DCS_CMD(0xE8, 0x00), |
587 | _INIT_DCS_CMD(0xE9, 0x01), |
588 | _INIT_DCS_CMD(0xEA, 0x65), |
589 | _INIT_DCS_CMD(0xEB, 0x01), |
590 | _INIT_DCS_CMD(0xEE, 0x65), |
591 | _INIT_DCS_CMD(0xEF, 0x01), |
592 | _INIT_DCS_CMD(0xF0, 0x65), |
593 | _INIT_DCS_CMD(0xB6, 0x05, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x05, 0x00, 0x00), |
594 | |
595 | _INIT_DCS_CMD(0xFF, 0x25), |
596 | |
597 | _INIT_DCS_CMD(0xFB, 0x01), |
598 | _INIT_DCS_CMD(0x05, 0x00), |
599 | _INIT_DCS_CMD(0xF1, 0x10), |
600 | |
601 | _INIT_DCS_CMD(0x1E, 0x00), |
602 | _INIT_DCS_CMD(0x1F, 0x46), |
603 | _INIT_DCS_CMD(0x20, 0x32), |
604 | |
605 | _INIT_DCS_CMD(0x25, 0x00), |
606 | _INIT_DCS_CMD(0x26, 0x46), |
607 | _INIT_DCS_CMD(0x27, 0x32), |
608 | |
609 | _INIT_DCS_CMD(0x3F, 0x80), |
610 | _INIT_DCS_CMD(0x40, 0x00), |
611 | _INIT_DCS_CMD(0x43, 0x00), |
612 | |
613 | _INIT_DCS_CMD(0x44, 0x46), |
614 | _INIT_DCS_CMD(0x45, 0x46), |
615 | |
616 | _INIT_DCS_CMD(0x48, 0x46), |
617 | _INIT_DCS_CMD(0x49, 0x32), |
618 | |
619 | _INIT_DCS_CMD(0x5B, 0x80), |
620 | |
621 | _INIT_DCS_CMD(0x5C, 0x00), |
622 | _INIT_DCS_CMD(0x5D, 0x46), |
623 | _INIT_DCS_CMD(0x5E, 0x32), |
624 | |
625 | _INIT_DCS_CMD(0x5F, 0x46), |
626 | _INIT_DCS_CMD(0x60, 0x32), |
627 | |
628 | _INIT_DCS_CMD(0x61, 0x46), |
629 | _INIT_DCS_CMD(0x62, 0x32), |
630 | _INIT_DCS_CMD(0x68, 0x0C), |
631 | |
632 | _INIT_DCS_CMD(0x6C, 0x0D), |
633 | _INIT_DCS_CMD(0x6E, 0x0D), |
634 | _INIT_DCS_CMD(0x78, 0x00), |
635 | _INIT_DCS_CMD(0x79, 0xC5), |
636 | _INIT_DCS_CMD(0x7A, 0x0C), |
637 | _INIT_DCS_CMD(0x7B, 0xB0), |
638 | |
639 | _INIT_DCS_CMD(0xFF, 0x26), |
640 | _INIT_DCS_CMD(0xFB, 0x01), |
641 | |
642 | _INIT_DCS_CMD(0x00, 0xA1), |
643 | _INIT_DCS_CMD(0x02, 0x31), |
644 | _INIT_DCS_CMD(0x0A, 0xF4), |
645 | _INIT_DCS_CMD(0x04, 0x50), |
646 | _INIT_DCS_CMD(0x06, 0x30), |
647 | _INIT_DCS_CMD(0x0C, 0x16), |
648 | _INIT_DCS_CMD(0x0D, 0x0D), |
649 | _INIT_DCS_CMD(0x0F, 0x00), |
650 | _INIT_DCS_CMD(0x11, 0x00), |
651 | _INIT_DCS_CMD(0x12, 0x50), |
652 | _INIT_DCS_CMD(0x13, 0x40), |
653 | _INIT_DCS_CMD(0x14, 0x58), |
654 | _INIT_DCS_CMD(0x15, 0x00), |
655 | _INIT_DCS_CMD(0x16, 0x10), |
656 | _INIT_DCS_CMD(0x17, 0xA0), |
657 | _INIT_DCS_CMD(0x18, 0x86), |
658 | _INIT_DCS_CMD(0x22, 0x00), |
659 | _INIT_DCS_CMD(0x23, 0x00), |
660 | |
661 | _INIT_DCS_CMD(0x19, 0x0E), |
662 | _INIT_DCS_CMD(0x1A, 0x31), |
663 | _INIT_DCS_CMD(0x1B, 0x0D), |
664 | _INIT_DCS_CMD(0x1C, 0x29), |
665 | _INIT_DCS_CMD(0x2A, 0x0E), |
666 | _INIT_DCS_CMD(0x2B, 0x31), |
667 | |
668 | _INIT_DCS_CMD(0x1D, 0x00), |
669 | _INIT_DCS_CMD(0x1E, 0x62), |
670 | _INIT_DCS_CMD(0x1F, 0x62), |
671 | |
672 | _INIT_DCS_CMD(0x2F, 0x06), |
673 | _INIT_DCS_CMD(0x30, 0x62), |
674 | _INIT_DCS_CMD(0x31, 0x06), |
675 | _INIT_DCS_CMD(0x32, 0x7F), |
676 | _INIT_DCS_CMD(0x33, 0x11), |
677 | _INIT_DCS_CMD(0x34, 0x89), |
678 | _INIT_DCS_CMD(0x35, 0x67), |
679 | |
680 | _INIT_DCS_CMD(0x39, 0x0B), |
681 | _INIT_DCS_CMD(0x3A, 0x62), |
682 | _INIT_DCS_CMD(0x3B, 0x06), |
683 | |
684 | _INIT_DCS_CMD(0xC8, 0x04), |
685 | _INIT_DCS_CMD(0xC9, 0x89), |
686 | _INIT_DCS_CMD(0xCA, 0x4E), |
687 | _INIT_DCS_CMD(0xCB, 0x00), |
688 | _INIT_DCS_CMD(0xA9, 0x3F), |
689 | _INIT_DCS_CMD(0xAA, 0x3E), |
690 | _INIT_DCS_CMD(0xAB, 0x3D), |
691 | _INIT_DCS_CMD(0xAC, 0x3C), |
692 | _INIT_DCS_CMD(0xAD, 0x3B), |
693 | _INIT_DCS_CMD(0xAE, 0x3A), |
694 | _INIT_DCS_CMD(0xAF, 0x39), |
695 | _INIT_DCS_CMD(0xB0, 0x38), |
696 | |
697 | _INIT_DCS_CMD(0xFF, 0x27), |
698 | _INIT_DCS_CMD(0xFB, 0x01), |
699 | |
700 | _INIT_DCS_CMD(0xD0, 0x11), |
701 | _INIT_DCS_CMD(0xD1, 0x54), |
702 | _INIT_DCS_CMD(0xDE, 0x43), |
703 | _INIT_DCS_CMD(0xDF, 0x02), |
704 | |
705 | _INIT_DCS_CMD(0xC0, 0x18), |
706 | _INIT_DCS_CMD(0xC1, 0x00), |
707 | _INIT_DCS_CMD(0xC2, 0x00), |
708 | _INIT_DCS_CMD(0x00, 0x00), |
709 | _INIT_DCS_CMD(0xC3, 0x00), |
710 | _INIT_DCS_CMD(0x56, 0x06), |
711 | |
712 | _INIT_DCS_CMD(0x58, 0x80), |
713 | _INIT_DCS_CMD(0x59, 0x78), |
714 | _INIT_DCS_CMD(0x5A, 0x00), |
715 | _INIT_DCS_CMD(0x5B, 0x18), |
716 | _INIT_DCS_CMD(0x5C, 0x00), |
717 | _INIT_DCS_CMD(0x5D, 0x01), |
718 | _INIT_DCS_CMD(0x5E, 0x20), |
719 | _INIT_DCS_CMD(0x5F, 0x10), |
720 | _INIT_DCS_CMD(0x60, 0x00), |
721 | _INIT_DCS_CMD(0x61, 0x1C), |
722 | _INIT_DCS_CMD(0x62, 0x00), |
723 | _INIT_DCS_CMD(0x63, 0x01), |
724 | _INIT_DCS_CMD(0x64, 0x44), |
725 | _INIT_DCS_CMD(0x65, 0x1B), |
726 | _INIT_DCS_CMD(0x66, 0x00), |
727 | _INIT_DCS_CMD(0x67, 0x01), |
728 | _INIT_DCS_CMD(0x68, 0x44), |
729 | |
730 | _INIT_DCS_CMD(0x98, 0x01), |
731 | _INIT_DCS_CMD(0xB4, 0x03), |
732 | _INIT_DCS_CMD(0x9B, 0xBE), |
733 | |
734 | _INIT_DCS_CMD(0xAB, 0x14), |
735 | _INIT_DCS_CMD(0xBC, 0x08), |
736 | _INIT_DCS_CMD(0xBD, 0x28), |
737 | |
738 | _INIT_DCS_CMD(0xFF, 0x2A), |
739 | _INIT_DCS_CMD(0xFB, 0x01), |
740 | _INIT_DCS_CMD(0x22, 0x2F), |
741 | _INIT_DCS_CMD(0x23, 0x08), |
742 | |
743 | _INIT_DCS_CMD(0x24, 0x00), |
744 | _INIT_DCS_CMD(0x25, 0x62), |
745 | _INIT_DCS_CMD(0x26, 0xF8), |
746 | _INIT_DCS_CMD(0x27, 0x00), |
747 | _INIT_DCS_CMD(0x28, 0x1A), |
748 | _INIT_DCS_CMD(0x29, 0x00), |
749 | _INIT_DCS_CMD(0x2A, 0x1A), |
750 | _INIT_DCS_CMD(0x2B, 0x00), |
751 | _INIT_DCS_CMD(0x2D, 0x1A), |
752 | |
753 | _INIT_DCS_CMD(0x64, 0x96), |
754 | _INIT_DCS_CMD(0x65, 0x10), |
755 | _INIT_DCS_CMD(0x66, 0x00), |
756 | _INIT_DCS_CMD(0x67, 0x96), |
757 | _INIT_DCS_CMD(0x68, 0x10), |
758 | _INIT_DCS_CMD(0x69, 0x00), |
759 | _INIT_DCS_CMD(0x6A, 0x96), |
760 | _INIT_DCS_CMD(0x6B, 0x10), |
761 | _INIT_DCS_CMD(0x6C, 0x00), |
762 | _INIT_DCS_CMD(0x70, 0x92), |
763 | _INIT_DCS_CMD(0x71, 0x10), |
764 | _INIT_DCS_CMD(0x72, 0x00), |
765 | _INIT_DCS_CMD(0x79, 0x96), |
766 | _INIT_DCS_CMD(0x7A, 0x10), |
767 | _INIT_DCS_CMD(0x88, 0x96), |
768 | _INIT_DCS_CMD(0x89, 0x10), |
769 | |
770 | _INIT_DCS_CMD(0xA2, 0x3F), |
771 | _INIT_DCS_CMD(0xA3, 0x30), |
772 | _INIT_DCS_CMD(0xA4, 0xC0), |
773 | _INIT_DCS_CMD(0xA5, 0x03), |
774 | |
775 | _INIT_DCS_CMD(0xE8, 0x00), |
776 | |
777 | _INIT_DCS_CMD(0x97, 0x3C), |
778 | _INIT_DCS_CMD(0x98, 0x02), |
779 | _INIT_DCS_CMD(0x99, 0x95), |
780 | _INIT_DCS_CMD(0x9A, 0x06), |
781 | _INIT_DCS_CMD(0x9B, 0x00), |
782 | _INIT_DCS_CMD(0x9C, 0x0B), |
783 | _INIT_DCS_CMD(0x9D, 0x0A), |
784 | _INIT_DCS_CMD(0x9E, 0x90), |
785 | |
786 | _INIT_DCS_CMD(0xFF, 0x25), |
787 | _INIT_DCS_CMD(0x13, 0x02), |
788 | _INIT_DCS_CMD(0x14, 0xD7), |
789 | _INIT_DCS_CMD(0xDB, 0x02), |
790 | _INIT_DCS_CMD(0xDC, 0xD7), |
791 | _INIT_DCS_CMD(0x17, 0xCF), |
792 | _INIT_DCS_CMD(0x19, 0x0F), |
793 | _INIT_DCS_CMD(0x1B, 0x5B), |
794 | |
795 | _INIT_DCS_CMD(0xFF, 0x20), |
796 | |
797 | _INIT_DCS_CMD(0xB0, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x24, 0x00, 0x38, 0x00, 0x4C, 0x00, 0x5E, 0x00, 0x6F, 0x00, 0x7E), |
798 | _INIT_DCS_CMD(0xB1, 0x00, 0x8C, 0x00, 0xBE, 0x00, 0xE5, 0x01, 0x27, 0x01, 0x58, 0x01, 0xA8, 0x01, 0xE8, 0x01, 0xEA), |
799 | _INIT_DCS_CMD(0xB2, 0x02, 0x28, 0x02, 0x71, 0x02, 0x9E, 0x02, 0xDA, 0x03, 0x00, 0x03, 0x31, 0x03, 0x40, 0x03, 0x51), |
800 | _INIT_DCS_CMD(0xB3, 0x03, 0x62, 0x03, 0x75, 0x03, 0x89, 0x03, 0x9C, 0x03, 0xAA, 0x03, 0xB2), |
801 | |
802 | _INIT_DCS_CMD(0xB4, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x27, 0x00, 0x3D, 0x00, 0x52, 0x00, 0x64, 0x00, 0x75, 0x00, 0x84), |
803 | _INIT_DCS_CMD(0xB5, 0x00, 0x93, 0x00, 0xC5, 0x00, 0xEC, 0x01, 0x2C, 0x01, 0x5D, 0x01, 0xAC, 0x01, 0xEC, 0x01, 0xEE), |
804 | _INIT_DCS_CMD(0xB6, 0x02, 0x2B, 0x02, 0x73, 0x02, 0xA0, 0x02, 0xDB, 0x03, 0x01, 0x03, 0x31, 0x03, 0x41, 0x03, 0x51), |
805 | _INIT_DCS_CMD(0xB7, 0x03, 0x63, 0x03, 0x75, 0x03, 0x89, 0x03, 0x9C, 0x03, 0xAA, 0x03, 0xB2), |
806 | |
807 | _INIT_DCS_CMD(0xB8, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x2A, 0x00, 0x40, 0x00, 0x56, 0x00, 0x68, 0x00, 0x7A, 0x00, 0x89), |
808 | _INIT_DCS_CMD(0xB9, 0x00, 0x98, 0x00, 0xC9, 0x00, 0xF1, 0x01, 0x30, 0x01, 0x61, 0x01, 0xB0, 0x01, 0xEF, 0x01, 0xF1), |
809 | _INIT_DCS_CMD(0xBA, 0x02, 0x2E, 0x02, 0x76, 0x02, 0xA3, 0x02, 0xDD, 0x03, 0x02, 0x03, 0x32, 0x03, 0x42, 0x03, 0x53), |
810 | _INIT_DCS_CMD(0xBB, 0x03, 0x66, 0x03, 0x75, 0x03, 0x89, 0x03, 0x9C, 0x03, 0xAA, 0x03, 0xB2), |
811 | |
812 | _INIT_DCS_CMD(0xFF, 0x21), |
813 | _INIT_DCS_CMD(0xB0, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x24, 0x00, 0x38, 0x00, 0x4C, 0x00, 0x5E, 0x00, 0x6F, 0x00, 0x7E), |
814 | _INIT_DCS_CMD(0xB1, 0x00, 0x8C, 0x00, 0xBE, 0x00, 0xE5, 0x01, 0x27, 0x01, 0x58, 0x01, 0xA8, 0x01, 0xE8, 0x01, 0xEA), |
815 | _INIT_DCS_CMD(0xB2, 0x02, 0x28, 0x02, 0x71, 0x02, 0x9E, 0x02, 0xDA, 0x03, 0x00, 0x03, 0x31, 0x03, 0x40, 0x03, 0x51), |
816 | _INIT_DCS_CMD(0xB3, 0x03, 0x62, 0x03, 0x77, 0x03, 0x90, 0x03, 0xAC, 0x03, 0xCA, 0x03, 0xDA), |
817 | |
818 | _INIT_DCS_CMD(0xB4, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x27, 0x00, 0x3D, 0x00, 0x52, 0x00, 0x64, 0x00, 0x75, 0x00, 0x84), |
819 | _INIT_DCS_CMD(0xB5, 0x00, 0x93, 0x00, 0xC5, 0x00, 0xEC, 0x01, 0x2C, 0x01, 0x5D, 0x01, 0xAC, 0x01, 0xEC, 0x01, 0xEE), |
820 | _INIT_DCS_CMD(0xB6, 0x02, 0x2B, 0x02, 0x73, 0x02, 0xA0, 0x02, 0xDB, 0x03, 0x01, 0x03, 0x31, 0x03, 0x41, 0x03, 0x51), |
821 | _INIT_DCS_CMD(0xB7, 0x03, 0x63, 0x03, 0x77, 0x03, 0x90, 0x03, 0xAC, 0x03, 0xCA, 0x03, 0xDA), |
822 | |
823 | _INIT_DCS_CMD(0xB8, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x2A, 0x00, 0x40, 0x00, 0x56, 0x00, 0x68, 0x00, 0x7A, 0x00, 0x89), |
824 | _INIT_DCS_CMD(0xB9, 0x00, 0x98, 0x00, 0xC9, 0x00, 0xF1, 0x01, 0x30, 0x01, 0x61, 0x01, 0xB0, 0x01, 0xEF, 0x01, 0xF1), |
825 | _INIT_DCS_CMD(0xBA, 0x02, 0x2E, 0x02, 0x76, 0x02, 0xA3, 0x02, 0xDD, 0x03, 0x02, 0x03, 0x32, 0x03, 0x42, 0x03, 0x53), |
826 | _INIT_DCS_CMD(0xBB, 0x03, 0x66, 0x03, 0x77, 0x03, 0x90, 0x03, 0xAC, 0x03, 0xCA, 0x03, 0xDA), |
827 | |
828 | _INIT_DCS_CMD(0xFF, 0xF0), |
829 | _INIT_DCS_CMD(0xFB, 0x01), |
830 | _INIT_DCS_CMD(0x3A, 0x08), |
831 | |
832 | _INIT_DCS_CMD(0xFF, 0x10), |
833 | _INIT_DCS_CMD(0xB9, 0x01), |
834 | |
835 | _INIT_DCS_CMD(0xFF, 0x20), |
836 | |
837 | _INIT_DCS_CMD(0x18, 0x40), |
838 | _INIT_DCS_CMD(0xFF, 0x10), |
839 | |
840 | _INIT_DCS_CMD(0xB9, 0x02), |
841 | _INIT_DCS_CMD(0xFF, 0x10), |
842 | |
843 | _INIT_DCS_CMD(0xFB, 0x01), |
844 | _INIT_DCS_CMD(0xB0, 0x01), |
845 | _INIT_DCS_CMD(0x35, 0x00), |
846 | _INIT_DCS_CMD(0x3B, 0x03, 0xAE, 0x1A, 0x04, 0x04), |
847 | _INIT_DELAY_CMD(100), |
848 | _INIT_DCS_CMD(0x11), |
849 | _INIT_DELAY_CMD(200), |
850 | _INIT_DCS_CMD(0x29), |
851 | _INIT_DELAY_CMD(100), |
852 | {}, |
853 | }; |
854 | |
855 | static const struct panel_init_cmd boe_init_cmd[] = { |
856 | _INIT_DCS_CMD(0xB0, 0x05), |
857 | _INIT_DCS_CMD(0xB1, 0xE5), |
858 | _INIT_DCS_CMD(0xB3, 0x52), |
859 | _INIT_DCS_CMD(0xB0, 0x00), |
860 | _INIT_DCS_CMD(0xB3, 0x88), |
861 | _INIT_DCS_CMD(0xB0, 0x04), |
862 | _INIT_DCS_CMD(0xB8, 0x00), |
863 | _INIT_DCS_CMD(0xB0, 0x00), |
864 | _INIT_DCS_CMD(0xB6, 0x03), |
865 | _INIT_DCS_CMD(0xBA, 0x8B), |
866 | _INIT_DCS_CMD(0xBF, 0x1A), |
867 | _INIT_DCS_CMD(0xC0, 0x0F), |
868 | _INIT_DCS_CMD(0xC2, 0x0C), |
869 | _INIT_DCS_CMD(0xC3, 0x02), |
870 | _INIT_DCS_CMD(0xC4, 0x0C), |
871 | _INIT_DCS_CMD(0xC5, 0x02), |
872 | _INIT_DCS_CMD(0xB0, 0x01), |
873 | _INIT_DCS_CMD(0xE0, 0x26), |
874 | _INIT_DCS_CMD(0xE1, 0x26), |
875 | _INIT_DCS_CMD(0xDC, 0x00), |
876 | _INIT_DCS_CMD(0xDD, 0x00), |
877 | _INIT_DCS_CMD(0xCC, 0x26), |
878 | _INIT_DCS_CMD(0xCD, 0x26), |
879 | _INIT_DCS_CMD(0xC8, 0x00), |
880 | _INIT_DCS_CMD(0xC9, 0x00), |
881 | _INIT_DCS_CMD(0xD2, 0x03), |
882 | _INIT_DCS_CMD(0xD3, 0x03), |
883 | _INIT_DCS_CMD(0xE6, 0x04), |
884 | _INIT_DCS_CMD(0xE7, 0x04), |
885 | _INIT_DCS_CMD(0xC4, 0x09), |
886 | _INIT_DCS_CMD(0xC5, 0x09), |
887 | _INIT_DCS_CMD(0xD8, 0x0A), |
888 | _INIT_DCS_CMD(0xD9, 0x0A), |
889 | _INIT_DCS_CMD(0xC2, 0x0B), |
890 | _INIT_DCS_CMD(0xC3, 0x0B), |
891 | _INIT_DCS_CMD(0xD6, 0x0C), |
892 | _INIT_DCS_CMD(0xD7, 0x0C), |
893 | _INIT_DCS_CMD(0xC0, 0x05), |
894 | _INIT_DCS_CMD(0xC1, 0x05), |
895 | _INIT_DCS_CMD(0xD4, 0x06), |
896 | _INIT_DCS_CMD(0xD5, 0x06), |
897 | _INIT_DCS_CMD(0xCA, 0x07), |
898 | _INIT_DCS_CMD(0xCB, 0x07), |
899 | _INIT_DCS_CMD(0xDE, 0x08), |
900 | _INIT_DCS_CMD(0xDF, 0x08), |
901 | _INIT_DCS_CMD(0xB0, 0x02), |
902 | _INIT_DCS_CMD(0xC0, 0x00), |
903 | _INIT_DCS_CMD(0xC1, 0x0D), |
904 | _INIT_DCS_CMD(0xC2, 0x17), |
905 | _INIT_DCS_CMD(0xC3, 0x26), |
906 | _INIT_DCS_CMD(0xC4, 0x31), |
907 | _INIT_DCS_CMD(0xC5, 0x1C), |
908 | _INIT_DCS_CMD(0xC6, 0x2C), |
909 | _INIT_DCS_CMD(0xC7, 0x33), |
910 | _INIT_DCS_CMD(0xC8, 0x31), |
911 | _INIT_DCS_CMD(0xC9, 0x37), |
912 | _INIT_DCS_CMD(0xCA, 0x37), |
913 | _INIT_DCS_CMD(0xCB, 0x37), |
914 | _INIT_DCS_CMD(0xCC, 0x39), |
915 | _INIT_DCS_CMD(0xCD, 0x2E), |
916 | _INIT_DCS_CMD(0xCE, 0x2F), |
917 | _INIT_DCS_CMD(0xCF, 0x2F), |
918 | _INIT_DCS_CMD(0xD0, 0x07), |
919 | _INIT_DCS_CMD(0xD2, 0x00), |
920 | _INIT_DCS_CMD(0xD3, 0x0D), |
921 | _INIT_DCS_CMD(0xD4, 0x17), |
922 | _INIT_DCS_CMD(0xD5, 0x26), |
923 | _INIT_DCS_CMD(0xD6, 0x31), |
924 | _INIT_DCS_CMD(0xD7, 0x3F), |
925 | _INIT_DCS_CMD(0xD8, 0x3F), |
926 | _INIT_DCS_CMD(0xD9, 0x3F), |
927 | _INIT_DCS_CMD(0xDA, 0x3F), |
928 | _INIT_DCS_CMD(0xDB, 0x37), |
929 | _INIT_DCS_CMD(0xDC, 0x37), |
930 | _INIT_DCS_CMD(0xDD, 0x37), |
931 | _INIT_DCS_CMD(0xDE, 0x39), |
932 | _INIT_DCS_CMD(0xDF, 0x2E), |
933 | _INIT_DCS_CMD(0xE0, 0x2F), |
934 | _INIT_DCS_CMD(0xE1, 0x2F), |
935 | _INIT_DCS_CMD(0xE2, 0x07), |
936 | _INIT_DCS_CMD(0xB0, 0x03), |
937 | _INIT_DCS_CMD(0xC8, 0x0B), |
938 | _INIT_DCS_CMD(0xC9, 0x07), |
939 | _INIT_DCS_CMD(0xC3, 0x00), |
940 | _INIT_DCS_CMD(0xE7, 0x00), |
941 | _INIT_DCS_CMD(0xC5, 0x2A), |
942 | _INIT_DCS_CMD(0xDE, 0x2A), |
943 | _INIT_DCS_CMD(0xCA, 0x43), |
944 | _INIT_DCS_CMD(0xC9, 0x07), |
945 | _INIT_DCS_CMD(0xE4, 0xC0), |
946 | _INIT_DCS_CMD(0xE5, 0x0D), |
947 | _INIT_DCS_CMD(0xCB, 0x00), |
948 | _INIT_DCS_CMD(0xB0, 0x06), |
949 | _INIT_DCS_CMD(0xB8, 0xA5), |
950 | _INIT_DCS_CMD(0xC0, 0xA5), |
951 | _INIT_DCS_CMD(0xC7, 0x0F), |
952 | _INIT_DCS_CMD(0xD5, 0x32), |
953 | _INIT_DCS_CMD(0xB8, 0x00), |
954 | _INIT_DCS_CMD(0xC0, 0x00), |
955 | _INIT_DCS_CMD(0xBC, 0x00), |
956 | _INIT_DCS_CMD(0xB0, 0x07), |
957 | _INIT_DCS_CMD(0xB1, 0x00), |
958 | _INIT_DCS_CMD(0xB2, 0x02), |
959 | _INIT_DCS_CMD(0xB3, 0x0F), |
960 | _INIT_DCS_CMD(0xB4, 0x25), |
961 | _INIT_DCS_CMD(0xB5, 0x39), |
962 | _INIT_DCS_CMD(0xB6, 0x4E), |
963 | _INIT_DCS_CMD(0xB7, 0x72), |
964 | _INIT_DCS_CMD(0xB8, 0x97), |
965 | _INIT_DCS_CMD(0xB9, 0xDC), |
966 | _INIT_DCS_CMD(0xBA, 0x22), |
967 | _INIT_DCS_CMD(0xBB, 0xA4), |
968 | _INIT_DCS_CMD(0xBC, 0x2B), |
969 | _INIT_DCS_CMD(0xBD, 0x2F), |
970 | _INIT_DCS_CMD(0xBE, 0xA9), |
971 | _INIT_DCS_CMD(0xBF, 0x25), |
972 | _INIT_DCS_CMD(0xC0, 0x61), |
973 | _INIT_DCS_CMD(0xC1, 0x97), |
974 | _INIT_DCS_CMD(0xC2, 0xB2), |
975 | _INIT_DCS_CMD(0xC3, 0xCD), |
976 | _INIT_DCS_CMD(0xC4, 0xD9), |
977 | _INIT_DCS_CMD(0xC5, 0xE7), |
978 | _INIT_DCS_CMD(0xC6, 0xF4), |
979 | _INIT_DCS_CMD(0xC7, 0xFA), |
980 | _INIT_DCS_CMD(0xC8, 0xFC), |
981 | _INIT_DCS_CMD(0xC9, 0x00), |
982 | _INIT_DCS_CMD(0xCA, 0x00), |
983 | _INIT_DCS_CMD(0xCB, 0x16), |
984 | _INIT_DCS_CMD(0xCC, 0xAF), |
985 | _INIT_DCS_CMD(0xCD, 0xFF), |
986 | _INIT_DCS_CMD(0xCE, 0xFF), |
987 | _INIT_DCS_CMD(0xB0, 0x08), |
988 | _INIT_DCS_CMD(0xB1, 0x04), |
989 | _INIT_DCS_CMD(0xB2, 0x05), |
990 | _INIT_DCS_CMD(0xB3, 0x11), |
991 | _INIT_DCS_CMD(0xB4, 0x24), |
992 | _INIT_DCS_CMD(0xB5, 0x39), |
993 | _INIT_DCS_CMD(0xB6, 0x4F), |
994 | _INIT_DCS_CMD(0xB7, 0x72), |
995 | _INIT_DCS_CMD(0xB8, 0x98), |
996 | _INIT_DCS_CMD(0xB9, 0xDC), |
997 | _INIT_DCS_CMD(0xBA, 0x23), |
998 | _INIT_DCS_CMD(0xBB, 0xA6), |
999 | _INIT_DCS_CMD(0xBC, 0x2C), |
1000 | _INIT_DCS_CMD(0xBD, 0x30), |
1001 | _INIT_DCS_CMD(0xBE, 0xAA), |
1002 | _INIT_DCS_CMD(0xBF, 0x26), |
1003 | _INIT_DCS_CMD(0xC0, 0x62), |
1004 | _INIT_DCS_CMD(0xC1, 0x9B), |
1005 | _INIT_DCS_CMD(0xC2, 0xB5), |
1006 | _INIT_DCS_CMD(0xC3, 0xCF), |
1007 | _INIT_DCS_CMD(0xC4, 0xDB), |
1008 | _INIT_DCS_CMD(0xC5, 0xE8), |
1009 | _INIT_DCS_CMD(0xC6, 0xF5), |
1010 | _INIT_DCS_CMD(0xC7, 0xFA), |
1011 | _INIT_DCS_CMD(0xC8, 0xFC), |
1012 | _INIT_DCS_CMD(0xC9, 0x00), |
1013 | _INIT_DCS_CMD(0xCA, 0x00), |
1014 | _INIT_DCS_CMD(0xCB, 0x16), |
1015 | _INIT_DCS_CMD(0xCC, 0xAF), |
1016 | _INIT_DCS_CMD(0xCD, 0xFF), |
1017 | _INIT_DCS_CMD(0xCE, 0xFF), |
1018 | _INIT_DCS_CMD(0xB0, 0x09), |
1019 | _INIT_DCS_CMD(0xB1, 0x04), |
1020 | _INIT_DCS_CMD(0xB2, 0x02), |
1021 | _INIT_DCS_CMD(0xB3, 0x16), |
1022 | _INIT_DCS_CMD(0xB4, 0x24), |
1023 | _INIT_DCS_CMD(0xB5, 0x3B), |
1024 | _INIT_DCS_CMD(0xB6, 0x4F), |
1025 | _INIT_DCS_CMD(0xB7, 0x73), |
1026 | _INIT_DCS_CMD(0xB8, 0x99), |
1027 | _INIT_DCS_CMD(0xB9, 0xE0), |
1028 | _INIT_DCS_CMD(0xBA, 0x26), |
1029 | _INIT_DCS_CMD(0xBB, 0xAD), |
1030 | _INIT_DCS_CMD(0xBC, 0x36), |
1031 | _INIT_DCS_CMD(0xBD, 0x3A), |
1032 | _INIT_DCS_CMD(0xBE, 0xAE), |
1033 | _INIT_DCS_CMD(0xBF, 0x2A), |
1034 | _INIT_DCS_CMD(0xC0, 0x66), |
1035 | _INIT_DCS_CMD(0xC1, 0x9E), |
1036 | _INIT_DCS_CMD(0xC2, 0xB8), |
1037 | _INIT_DCS_CMD(0xC3, 0xD1), |
1038 | _INIT_DCS_CMD(0xC4, 0xDD), |
1039 | _INIT_DCS_CMD(0xC5, 0xE9), |
1040 | _INIT_DCS_CMD(0xC6, 0xF6), |
1041 | _INIT_DCS_CMD(0xC7, 0xFA), |
1042 | _INIT_DCS_CMD(0xC8, 0xFC), |
1043 | _INIT_DCS_CMD(0xC9, 0x00), |
1044 | _INIT_DCS_CMD(0xCA, 0x00), |
1045 | _INIT_DCS_CMD(0xCB, 0x16), |
1046 | _INIT_DCS_CMD(0xCC, 0xAF), |
1047 | _INIT_DCS_CMD(0xCD, 0xFF), |
1048 | _INIT_DCS_CMD(0xCE, 0xFF), |
1049 | _INIT_DCS_CMD(0xB0, 0x0A), |
1050 | _INIT_DCS_CMD(0xB1, 0x00), |
1051 | _INIT_DCS_CMD(0xB2, 0x02), |
1052 | _INIT_DCS_CMD(0xB3, 0x0F), |
1053 | _INIT_DCS_CMD(0xB4, 0x25), |
1054 | _INIT_DCS_CMD(0xB5, 0x39), |
1055 | _INIT_DCS_CMD(0xB6, 0x4E), |
1056 | _INIT_DCS_CMD(0xB7, 0x72), |
1057 | _INIT_DCS_CMD(0xB8, 0x97), |
1058 | _INIT_DCS_CMD(0xB9, 0xDC), |
1059 | _INIT_DCS_CMD(0xBA, 0x22), |
1060 | _INIT_DCS_CMD(0xBB, 0xA4), |
1061 | _INIT_DCS_CMD(0xBC, 0x2B), |
1062 | _INIT_DCS_CMD(0xBD, 0x2F), |
1063 | _INIT_DCS_CMD(0xBE, 0xA9), |
1064 | _INIT_DCS_CMD(0xBF, 0x25), |
1065 | _INIT_DCS_CMD(0xC0, 0x61), |
1066 | _INIT_DCS_CMD(0xC1, 0x97), |
1067 | _INIT_DCS_CMD(0xC2, 0xB2), |
1068 | _INIT_DCS_CMD(0xC3, 0xCD), |
1069 | _INIT_DCS_CMD(0xC4, 0xD9), |
1070 | _INIT_DCS_CMD(0xC5, 0xE7), |
1071 | _INIT_DCS_CMD(0xC6, 0xF4), |
1072 | _INIT_DCS_CMD(0xC7, 0xFA), |
1073 | _INIT_DCS_CMD(0xC8, 0xFC), |
1074 | _INIT_DCS_CMD(0xC9, 0x00), |
1075 | _INIT_DCS_CMD(0xCA, 0x00), |
1076 | _INIT_DCS_CMD(0xCB, 0x16), |
1077 | _INIT_DCS_CMD(0xCC, 0xAF), |
1078 | _INIT_DCS_CMD(0xCD, 0xFF), |
1079 | _INIT_DCS_CMD(0xCE, 0xFF), |
1080 | _INIT_DCS_CMD(0xB0, 0x0B), |
1081 | _INIT_DCS_CMD(0xB1, 0x04), |
1082 | _INIT_DCS_CMD(0xB2, 0x05), |
1083 | _INIT_DCS_CMD(0xB3, 0x11), |
1084 | _INIT_DCS_CMD(0xB4, 0x24), |
1085 | _INIT_DCS_CMD(0xB5, 0x39), |
1086 | _INIT_DCS_CMD(0xB6, 0x4F), |
1087 | _INIT_DCS_CMD(0xB7, 0x72), |
1088 | _INIT_DCS_CMD(0xB8, 0x98), |
1089 | _INIT_DCS_CMD(0xB9, 0xDC), |
1090 | _INIT_DCS_CMD(0xBA, 0x23), |
1091 | _INIT_DCS_CMD(0xBB, 0xA6), |
1092 | _INIT_DCS_CMD(0xBC, 0x2C), |
1093 | _INIT_DCS_CMD(0xBD, 0x30), |
1094 | _INIT_DCS_CMD(0xBE, 0xAA), |
1095 | _INIT_DCS_CMD(0xBF, 0x26), |
1096 | _INIT_DCS_CMD(0xC0, 0x62), |
1097 | _INIT_DCS_CMD(0xC1, 0x9B), |
1098 | _INIT_DCS_CMD(0xC2, 0xB5), |
1099 | _INIT_DCS_CMD(0xC3, 0xCF), |
1100 | _INIT_DCS_CMD(0xC4, 0xDB), |
1101 | _INIT_DCS_CMD(0xC5, 0xE8), |
1102 | _INIT_DCS_CMD(0xC6, 0xF5), |
1103 | _INIT_DCS_CMD(0xC7, 0xFA), |
1104 | _INIT_DCS_CMD(0xC8, 0xFC), |
1105 | _INIT_DCS_CMD(0xC9, 0x00), |
1106 | _INIT_DCS_CMD(0xCA, 0x00), |
1107 | _INIT_DCS_CMD(0xCB, 0x16), |
1108 | _INIT_DCS_CMD(0xCC, 0xAF), |
1109 | _INIT_DCS_CMD(0xCD, 0xFF), |
1110 | _INIT_DCS_CMD(0xCE, 0xFF), |
1111 | _INIT_DCS_CMD(0xB0, 0x0C), |
1112 | _INIT_DCS_CMD(0xB1, 0x04), |
1113 | _INIT_DCS_CMD(0xB2, 0x02), |
1114 | _INIT_DCS_CMD(0xB3, 0x16), |
1115 | _INIT_DCS_CMD(0xB4, 0x24), |
1116 | _INIT_DCS_CMD(0xB5, 0x3B), |
1117 | _INIT_DCS_CMD(0xB6, 0x4F), |
1118 | _INIT_DCS_CMD(0xB7, 0x73), |
1119 | _INIT_DCS_CMD(0xB8, 0x99), |
1120 | _INIT_DCS_CMD(0xB9, 0xE0), |
1121 | _INIT_DCS_CMD(0xBA, 0x26), |
1122 | _INIT_DCS_CMD(0xBB, 0xAD), |
1123 | _INIT_DCS_CMD(0xBC, 0x36), |
1124 | _INIT_DCS_CMD(0xBD, 0x3A), |
1125 | _INIT_DCS_CMD(0xBE, 0xAE), |
1126 | _INIT_DCS_CMD(0xBF, 0x2A), |
1127 | _INIT_DCS_CMD(0xC0, 0x66), |
1128 | _INIT_DCS_CMD(0xC1, 0x9E), |
1129 | _INIT_DCS_CMD(0xC2, 0xB8), |
1130 | _INIT_DCS_CMD(0xC3, 0xD1), |
1131 | _INIT_DCS_CMD(0xC4, 0xDD), |
1132 | _INIT_DCS_CMD(0xC5, 0xE9), |
1133 | _INIT_DCS_CMD(0xC6, 0xF6), |
1134 | _INIT_DCS_CMD(0xC7, 0xFA), |
1135 | _INIT_DCS_CMD(0xC8, 0xFC), |
1136 | _INIT_DCS_CMD(0xC9, 0x00), |
1137 | _INIT_DCS_CMD(0xCA, 0x00), |
1138 | _INIT_DCS_CMD(0xCB, 0x16), |
1139 | _INIT_DCS_CMD(0xCC, 0xAF), |
1140 | _INIT_DCS_CMD(0xCD, 0xFF), |
1141 | _INIT_DCS_CMD(0xCE, 0xFF), |
1142 | _INIT_DCS_CMD(0xB0, 0x00), |
1143 | _INIT_DCS_CMD(0xB3, 0x08), |
1144 | _INIT_DCS_CMD(0xB0, 0x04), |
1145 | _INIT_DCS_CMD(0xB8, 0x68), |
1146 | _INIT_DELAY_CMD(150), |
1147 | {}, |
1148 | }; |
1149 | |
1150 | static const struct panel_init_cmd auo_kd101n80_45na_init_cmd[] = { |
1151 | _INIT_DELAY_CMD(24), |
1152 | _INIT_DCS_CMD(0x11), |
1153 | _INIT_DELAY_CMD(120), |
1154 | _INIT_DCS_CMD(0x29), |
1155 | _INIT_DELAY_CMD(120), |
1156 | {}, |
1157 | }; |
1158 | |
1159 | static const struct panel_init_cmd auo_b101uan08_3_init_cmd[] = { |
1160 | _INIT_DELAY_CMD(24), |
1161 | _INIT_DCS_CMD(0xB0, 0x01), |
1162 | _INIT_DCS_CMD(0xC0, 0x48), |
1163 | _INIT_DCS_CMD(0xC1, 0x48), |
1164 | _INIT_DCS_CMD(0xC2, 0x47), |
1165 | _INIT_DCS_CMD(0xC3, 0x47), |
1166 | _INIT_DCS_CMD(0xC4, 0x46), |
1167 | _INIT_DCS_CMD(0xC5, 0x46), |
1168 | _INIT_DCS_CMD(0xC6, 0x45), |
1169 | _INIT_DCS_CMD(0xC7, 0x45), |
1170 | _INIT_DCS_CMD(0xC8, 0x64), |
1171 | _INIT_DCS_CMD(0xC9, 0x64), |
1172 | _INIT_DCS_CMD(0xCA, 0x4F), |
1173 | _INIT_DCS_CMD(0xCB, 0x4F), |
1174 | _INIT_DCS_CMD(0xCC, 0x40), |
1175 | _INIT_DCS_CMD(0xCD, 0x40), |
1176 | _INIT_DCS_CMD(0xCE, 0x66), |
1177 | _INIT_DCS_CMD(0xCF, 0x66), |
1178 | _INIT_DCS_CMD(0xD0, 0x4F), |
1179 | _INIT_DCS_CMD(0xD1, 0x4F), |
1180 | _INIT_DCS_CMD(0xD2, 0x41), |
1181 | _INIT_DCS_CMD(0xD3, 0x41), |
1182 | _INIT_DCS_CMD(0xD4, 0x48), |
1183 | _INIT_DCS_CMD(0xD5, 0x48), |
1184 | _INIT_DCS_CMD(0xD6, 0x47), |
1185 | _INIT_DCS_CMD(0xD7, 0x47), |
1186 | _INIT_DCS_CMD(0xD8, 0x46), |
1187 | _INIT_DCS_CMD(0xD9, 0x46), |
1188 | _INIT_DCS_CMD(0xDA, 0x45), |
1189 | _INIT_DCS_CMD(0xDB, 0x45), |
1190 | _INIT_DCS_CMD(0xDC, 0x64), |
1191 | _INIT_DCS_CMD(0xDD, 0x64), |
1192 | _INIT_DCS_CMD(0xDE, 0x4F), |
1193 | _INIT_DCS_CMD(0xDF, 0x4F), |
1194 | _INIT_DCS_CMD(0xE0, 0x40), |
1195 | _INIT_DCS_CMD(0xE1, 0x40), |
1196 | _INIT_DCS_CMD(0xE2, 0x66), |
1197 | _INIT_DCS_CMD(0xE3, 0x66), |
1198 | _INIT_DCS_CMD(0xE4, 0x4F), |
1199 | _INIT_DCS_CMD(0xE5, 0x4F), |
1200 | _INIT_DCS_CMD(0xE6, 0x41), |
1201 | _INIT_DCS_CMD(0xE7, 0x41), |
1202 | _INIT_DELAY_CMD(150), |
1203 | {}, |
1204 | }; |
1205 | |
1206 | static const struct panel_init_cmd starry_qfh032011_53g_init_cmd[] = { |
1207 | _INIT_DCS_CMD(0xB0, 0x01), |
1208 | _INIT_DCS_CMD(0xC3, 0x4F), |
1209 | _INIT_DCS_CMD(0xC4, 0x40), |
1210 | _INIT_DCS_CMD(0xC5, 0x40), |
1211 | _INIT_DCS_CMD(0xC6, 0x40), |
1212 | _INIT_DCS_CMD(0xC7, 0x40), |
1213 | _INIT_DCS_CMD(0xC8, 0x4D), |
1214 | _INIT_DCS_CMD(0xC9, 0x52), |
1215 | _INIT_DCS_CMD(0xCA, 0x51), |
1216 | _INIT_DCS_CMD(0xCD, 0x5D), |
1217 | _INIT_DCS_CMD(0xCE, 0x5B), |
1218 | _INIT_DCS_CMD(0xCF, 0x4B), |
1219 | _INIT_DCS_CMD(0xD0, 0x49), |
1220 | _INIT_DCS_CMD(0xD1, 0x47), |
1221 | _INIT_DCS_CMD(0xD2, 0x45), |
1222 | _INIT_DCS_CMD(0xD3, 0x41), |
1223 | _INIT_DCS_CMD(0xD7, 0x50), |
1224 | _INIT_DCS_CMD(0xD8, 0x40), |
1225 | _INIT_DCS_CMD(0xD9, 0x40), |
1226 | _INIT_DCS_CMD(0xDA, 0x40), |
1227 | _INIT_DCS_CMD(0xDB, 0x40), |
1228 | _INIT_DCS_CMD(0xDC, 0x4E), |
1229 | _INIT_DCS_CMD(0xDD, 0x52), |
1230 | _INIT_DCS_CMD(0xDE, 0x51), |
1231 | _INIT_DCS_CMD(0xE1, 0x5E), |
1232 | _INIT_DCS_CMD(0xE2, 0x5C), |
1233 | _INIT_DCS_CMD(0xE3, 0x4C), |
1234 | _INIT_DCS_CMD(0xE4, 0x4A), |
1235 | _INIT_DCS_CMD(0xE5, 0x48), |
1236 | _INIT_DCS_CMD(0xE6, 0x46), |
1237 | _INIT_DCS_CMD(0xE7, 0x42), |
1238 | _INIT_DCS_CMD(0xB0, 0x03), |
1239 | _INIT_DCS_CMD(0xBE, 0x03), |
1240 | _INIT_DCS_CMD(0xCC, 0x44), |
1241 | _INIT_DCS_CMD(0xC8, 0x07), |
1242 | _INIT_DCS_CMD(0xC9, 0x05), |
1243 | _INIT_DCS_CMD(0xCA, 0x42), |
1244 | _INIT_DCS_CMD(0xCD, 0x3E), |
1245 | _INIT_DCS_CMD(0xCF, 0x60), |
1246 | _INIT_DCS_CMD(0xD2, 0x04), |
1247 | _INIT_DCS_CMD(0xD3, 0x04), |
1248 | _INIT_DCS_CMD(0xD4, 0x01), |
1249 | _INIT_DCS_CMD(0xD5, 0x00), |
1250 | _INIT_DCS_CMD(0xD6, 0x03), |
1251 | _INIT_DCS_CMD(0xD7, 0x04), |
1252 | _INIT_DCS_CMD(0xD9, 0x01), |
1253 | _INIT_DCS_CMD(0xDB, 0x01), |
1254 | _INIT_DCS_CMD(0xE4, 0xF0), |
1255 | _INIT_DCS_CMD(0xE5, 0x0A), |
1256 | _INIT_DCS_CMD(0xB0, 0x00), |
1257 | _INIT_DCS_CMD(0xCC, 0x08), |
1258 | _INIT_DCS_CMD(0xC2, 0x08), |
1259 | _INIT_DCS_CMD(0xC4, 0x10), |
1260 | _INIT_DCS_CMD(0xB0, 0x02), |
1261 | _INIT_DCS_CMD(0xC0, 0x00), |
1262 | _INIT_DCS_CMD(0xC1, 0x0A), |
1263 | _INIT_DCS_CMD(0xC2, 0x20), |
1264 | _INIT_DCS_CMD(0xC3, 0x24), |
1265 | _INIT_DCS_CMD(0xC4, 0x23), |
1266 | _INIT_DCS_CMD(0xC5, 0x29), |
1267 | _INIT_DCS_CMD(0xC6, 0x23), |
1268 | _INIT_DCS_CMD(0xC7, 0x1C), |
1269 | _INIT_DCS_CMD(0xC8, 0x19), |
1270 | _INIT_DCS_CMD(0xC9, 0x17), |
1271 | _INIT_DCS_CMD(0xCA, 0x17), |
1272 | _INIT_DCS_CMD(0xCB, 0x18), |
1273 | _INIT_DCS_CMD(0xCC, 0x1A), |
1274 | _INIT_DCS_CMD(0xCD, 0x1E), |
1275 | _INIT_DCS_CMD(0xCE, 0x20), |
1276 | _INIT_DCS_CMD(0xCF, 0x23), |
1277 | _INIT_DCS_CMD(0xD0, 0x07), |
1278 | _INIT_DCS_CMD(0xD1, 0x00), |
1279 | _INIT_DCS_CMD(0xD2, 0x00), |
1280 | _INIT_DCS_CMD(0xD3, 0x0A), |
1281 | _INIT_DCS_CMD(0xD4, 0x13), |
1282 | _INIT_DCS_CMD(0xD5, 0x1C), |
1283 | _INIT_DCS_CMD(0xD6, 0x1A), |
1284 | _INIT_DCS_CMD(0xD7, 0x13), |
1285 | _INIT_DCS_CMD(0xD8, 0x17), |
1286 | _INIT_DCS_CMD(0xD9, 0x1C), |
1287 | _INIT_DCS_CMD(0xDA, 0x19), |
1288 | _INIT_DCS_CMD(0xDB, 0x17), |
1289 | _INIT_DCS_CMD(0xDC, 0x17), |
1290 | _INIT_DCS_CMD(0xDD, 0x18), |
1291 | _INIT_DCS_CMD(0xDE, 0x1A), |
1292 | _INIT_DCS_CMD(0xDF, 0x1E), |
1293 | _INIT_DCS_CMD(0xE0, 0x20), |
1294 | _INIT_DCS_CMD(0xE1, 0x23), |
1295 | _INIT_DCS_CMD(0xE2, 0x07), |
1296 | _INIT_DCS_CMD(0X11), |
1297 | _INIT_DELAY_CMD(120), |
1298 | _INIT_DCS_CMD(0X29), |
1299 | _INIT_DELAY_CMD(80), |
1300 | {}, |
1301 | }; |
1302 | |
1303 | static const struct panel_init_cmd starry_himax83102_j02_init_cmd[] = { |
1304 | _INIT_DCS_CMD(0xB9, 0x83, 0x10, 0x21, 0x55, 0x00), |
1305 | _INIT_DCS_CMD(0xB1, 0x2C, 0xB5, 0xB5, 0x31, 0xF1, 0x31, 0xD7, 0x2F, 0x36, 0x36, 0x36, 0x36, 0x1A, 0x8B, 0x11, |
1306 | 0x65, 0x00, 0x88, 0xFA, 0xFF, 0xFF, 0x8F, 0xFF, 0x08, 0x74, 0x33), |
1307 | _INIT_DCS_CMD(0xB2, 0x00, 0x47, 0xB0, 0x80, 0x00, 0x12, 0x72, 0x3C, 0xA3, 0x03, 0x03, 0x00, 0x00, 0x88, 0xF5), |
1308 | _INIT_DCS_CMD(0xB4, 0x76, 0x76, 0x76, 0x76, 0x76, 0x76, 0x63, 0x5C, 0x63, 0x5C, 0x01, 0x9E), |
1309 | _INIT_DCS_CMD(0xE9, 0xCD), |
1310 | _INIT_DCS_CMD(0xBA, 0x84), |
1311 | _INIT_DCS_CMD(0xE9, 0x3F), |
1312 | _INIT_DCS_CMD(0xBC, 0x1B, 0x04), |
1313 | _INIT_DCS_CMD(0xBE, 0x20), |
1314 | _INIT_DCS_CMD(0xBF, 0xFC, 0xC4), |
1315 | _INIT_DCS_CMD(0xC0, 0x36, 0x36, 0x22, 0x11, 0x22, 0xA0, 0x61, 0x08, 0xF5, 0x03), |
1316 | _INIT_DCS_CMD(0xE9, 0xCC), |
1317 | _INIT_DCS_CMD(0xC7, 0x80), |
1318 | _INIT_DCS_CMD(0xE9, 0x3F), |
1319 | _INIT_DCS_CMD(0xE9, 0xC6), |
1320 | _INIT_DCS_CMD(0xC8, 0x97), |
1321 | _INIT_DCS_CMD(0xE9, 0x3F), |
1322 | _INIT_DCS_CMD(0xC9, 0x00, 0x1E, 0x13, 0x88, 0x01), |
1323 | _INIT_DCS_CMD(0xCB, 0x08, 0x13, 0x07, 0x00, 0x0F, 0x33), |
1324 | _INIT_DCS_CMD(0xCC, 0x02), |
1325 | _INIT_DCS_CMD(0xE9, 0xC4), |
1326 | _INIT_DCS_CMD(0xD0, 0x03), |
1327 | _INIT_DCS_CMD(0xE9, 0x3F), |
1328 | _INIT_DCS_CMD(0xD1, 0x37, 0x06, 0x00, 0x02, 0x04, 0x0C, 0xFF), |
1329 | _INIT_DCS_CMD(0xD2, 0x1F, 0x11, 0x1F), |
1330 | _INIT_DCS_CMD(0xD3, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x08, 0x37, 0x47, 0x34, 0x3B, 0x12, 0x12, 0x03, |
1331 | 0x03, 0x32, 0x10, 0x10, 0x00, 0x10, 0x32, 0x10, 0x08, 0x00, 0x08, 0x32, 0x17, 0x94, 0x07, 0x94, 0x00, 0x00), |
1332 | _INIT_DCS_CMD(0xD5, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x19, 0x19, 0x40, 0x40, 0x1A, 0x1A, |
1333 | 0x1B, 0x1B, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x20, 0x21, 0x28, 0x29, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18), |
1334 | _INIT_DCS_CMD(0xD6, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x40, 0x40, 0x19, 0x19, 0x1A, 0x1A, |
1335 | 0x1B, 0x1B, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x29, 0x28, 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18), |
1336 | _INIT_DCS_CMD(0xD8, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA, |
1337 | 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0), |
1338 | _INIT_DCS_CMD(0xE0, 0x00, 0x09, 0x14, 0x1E, 0x26, 0x48, 0x61, 0x67, 0x6C, 0x67, 0x7D, 0x7F, 0x80, 0x8B, 0x87, 0x8F, 0x98, 0xAB, |
1339 | 0xAB, 0x55, 0x5C, 0x68, 0x73, 0x00, 0x09, 0x14, 0x1E, 0x26, 0x48, 0x61, 0x67, 0x6C, 0x67, 0x7D, 0x7F, 0x80, 0x8B, 0x87, 0x8F, 0x98, 0xAB, 0xAB, 0x55, 0x5C, 0x68, 0x73), |
1340 | _INIT_DCS_CMD(0xE7, 0x0E, 0x10, 0x10, 0x21, 0x2B, 0x9A, 0x02, 0x54, 0x9A, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x12, 0x05, 0x02, 0x02, 0x10), |
1341 | _INIT_DCS_CMD(0xBD, 0x01), |
1342 | _INIT_DCS_CMD(0xB1, 0x01, 0xBF, 0x11), |
1343 | _INIT_DCS_CMD(0xCB, 0x86), |
1344 | _INIT_DCS_CMD(0xD2, 0x3C, 0xFA), |
1345 | _INIT_DCS_CMD(0xD3, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0C, 0x01), |
1346 | _INIT_DCS_CMD(0xE7, 0x02, 0x00, 0x28, 0x01, 0x7E, 0x0F, 0x7E, 0x10, 0xA0, 0x00, 0x00, 0x20, 0x40, 0x50, 0x40), |
1347 | _INIT_DCS_CMD(0xBD, 0x02), |
1348 | _INIT_DCS_CMD(0xD8, 0xFF, 0xFF, 0xBF, 0xFE, 0xAA, 0xA0, 0xFF, 0xFF, 0xBF, 0xFE, 0xAA, 0xA0), |
1349 | _INIT_DCS_CMD(0xE7, 0xFE, 0x04, 0xFE, 0x04, 0xFE, 0x04, 0x03, 0x03, 0x03, 0x26, 0x00, 0x26, 0x81, 0x02, 0x40, 0x00, 0x20, 0x9E, 0x04, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00), |
1350 | _INIT_DCS_CMD(0xBD, 0x03), |
1351 | _INIT_DCS_CMD(0xE9, 0xC6), |
1352 | _INIT_DCS_CMD(0xB4, 0x03, 0xFF, 0xF8), |
1353 | _INIT_DCS_CMD(0xE9, 0x3F), |
1354 | _INIT_DCS_CMD(0xD8, 0x00, 0x2A, 0xAA, 0xA8, 0x00, 0x00, 0x00, 0x2A, 0xAA, 0xA8, 0x00, 0x00, 0x00, 0x3F, 0xFF, 0xFC, 0x00, 0x00, 0x00, 0x3F, 0xFF, 0xFC, 0x00, 0x00, 0x00, 0x2A, 0xAA, 0xA8, |
1355 | 0x00, 0x00, 0x00, 0x2A, 0xAA, 0xA8, 0x00, 0x00), |
1356 | _INIT_DCS_CMD(0xBD, 0x00), |
1357 | _INIT_DCS_CMD(0xE9, 0xC4), |
1358 | _INIT_DCS_CMD(0xBA, 0x96), |
1359 | _INIT_DCS_CMD(0xE9, 0x3F), |
1360 | _INIT_DCS_CMD(0xBD, 0x01), |
1361 | _INIT_DCS_CMD(0xE9, 0xC5), |
1362 | _INIT_DCS_CMD(0xBA, 0x4F), |
1363 | _INIT_DCS_CMD(0xE9, 0x3F), |
1364 | _INIT_DCS_CMD(0xBD, 0x00), |
1365 | _INIT_DCS_CMD(0x11), |
1366 | _INIT_DELAY_CMD(120), |
1367 | _INIT_DCS_CMD(0x29), |
1368 | {}, |
1369 | }; |
1370 | |
1371 | static inline struct boe_panel *to_boe_panel(struct drm_panel *panel) |
1372 | { |
1373 | return container_of(panel, struct boe_panel, base); |
1374 | } |
1375 | |
1376 | static int boe_panel_init_dcs_cmd(struct boe_panel *boe) |
1377 | { |
1378 | struct mipi_dsi_device *dsi = boe->dsi; |
1379 | struct drm_panel *panel = &boe->base; |
1380 | int i, err = 0; |
1381 | |
1382 | if (boe->desc->init_cmds) { |
1383 | const struct panel_init_cmd *init_cmds = boe->desc->init_cmds; |
1384 | |
1385 | for (i = 0; init_cmds[i].len != 0; i++) { |
1386 | const struct panel_init_cmd *cmd = &init_cmds[i]; |
1387 | |
1388 | switch (cmd->type) { |
1389 | case DELAY_CMD: |
1390 | msleep(msecs: cmd->data[0]); |
1391 | err = 0; |
1392 | break; |
1393 | |
1394 | case INIT_DCS_CMD: |
1395 | err = mipi_dsi_dcs_write(dsi, cmd: cmd->data[0], |
1396 | data: cmd->len <= 1 ? NULL : |
1397 | &cmd->data[1], |
1398 | len: cmd->len - 1); |
1399 | break; |
1400 | |
1401 | default: |
1402 | err = -EINVAL; |
1403 | } |
1404 | |
1405 | if (err < 0) { |
1406 | dev_err(panel->dev, |
1407 | "failed to write command %u\n" , i); |
1408 | return err; |
1409 | } |
1410 | } |
1411 | } |
1412 | return 0; |
1413 | } |
1414 | |
1415 | static int boe_panel_enter_sleep_mode(struct boe_panel *boe) |
1416 | { |
1417 | struct mipi_dsi_device *dsi = boe->dsi; |
1418 | int ret; |
1419 | |
1420 | dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; |
1421 | |
1422 | ret = mipi_dsi_dcs_set_display_off(dsi); |
1423 | if (ret < 0) |
1424 | return ret; |
1425 | |
1426 | ret = mipi_dsi_dcs_enter_sleep_mode(dsi); |
1427 | if (ret < 0) |
1428 | return ret; |
1429 | |
1430 | return 0; |
1431 | } |
1432 | |
1433 | static int boe_panel_disable(struct drm_panel *panel) |
1434 | { |
1435 | struct boe_panel *boe = to_boe_panel(panel); |
1436 | int ret; |
1437 | |
1438 | ret = boe_panel_enter_sleep_mode(boe); |
1439 | if (ret < 0) { |
1440 | dev_err(panel->dev, "failed to set panel off: %d\n" , ret); |
1441 | return ret; |
1442 | } |
1443 | |
1444 | msleep(msecs: 150); |
1445 | |
1446 | return 0; |
1447 | } |
1448 | |
1449 | static int boe_panel_unprepare(struct drm_panel *panel) |
1450 | { |
1451 | struct boe_panel *boe = to_boe_panel(panel); |
1452 | |
1453 | if (!boe->prepared) |
1454 | return 0; |
1455 | |
1456 | if (boe->desc->discharge_on_disable) { |
1457 | regulator_disable(regulator: boe->avee); |
1458 | regulator_disable(regulator: boe->avdd); |
1459 | usleep_range(min: 5000, max: 7000); |
1460 | gpiod_set_value(desc: boe->enable_gpio, value: 0); |
1461 | usleep_range(min: 5000, max: 7000); |
1462 | regulator_disable(regulator: boe->pp1800); |
1463 | regulator_disable(regulator: boe->pp3300); |
1464 | } else { |
1465 | gpiod_set_value(desc: boe->enable_gpio, value: 0); |
1466 | usleep_range(min: 1000, max: 2000); |
1467 | regulator_disable(regulator: boe->avee); |
1468 | regulator_disable(regulator: boe->avdd); |
1469 | usleep_range(min: 5000, max: 7000); |
1470 | regulator_disable(regulator: boe->pp1800); |
1471 | regulator_disable(regulator: boe->pp3300); |
1472 | } |
1473 | |
1474 | boe->prepared = false; |
1475 | |
1476 | return 0; |
1477 | } |
1478 | |
1479 | static int boe_panel_prepare(struct drm_panel *panel) |
1480 | { |
1481 | struct boe_panel *boe = to_boe_panel(panel); |
1482 | int ret; |
1483 | |
1484 | if (boe->prepared) |
1485 | return 0; |
1486 | |
1487 | gpiod_set_value(desc: boe->enable_gpio, value: 0); |
1488 | usleep_range(min: 1000, max: 1500); |
1489 | |
1490 | ret = regulator_enable(regulator: boe->pp3300); |
1491 | if (ret < 0) |
1492 | return ret; |
1493 | |
1494 | ret = regulator_enable(regulator: boe->pp1800); |
1495 | if (ret < 0) |
1496 | return ret; |
1497 | |
1498 | usleep_range(min: 3000, max: 5000); |
1499 | |
1500 | ret = regulator_enable(regulator: boe->avdd); |
1501 | if (ret < 0) |
1502 | goto poweroff1v8; |
1503 | ret = regulator_enable(regulator: boe->avee); |
1504 | if (ret < 0) |
1505 | goto poweroffavdd; |
1506 | |
1507 | usleep_range(min: 10000, max: 11000); |
1508 | |
1509 | if (boe->desc->lp11_before_reset) { |
1510 | mipi_dsi_dcs_nop(dsi: boe->dsi); |
1511 | usleep_range(min: 1000, max: 2000); |
1512 | } |
1513 | gpiod_set_value(desc: boe->enable_gpio, value: 1); |
1514 | usleep_range(min: 1000, max: 2000); |
1515 | gpiod_set_value(desc: boe->enable_gpio, value: 0); |
1516 | usleep_range(min: 1000, max: 2000); |
1517 | gpiod_set_value(desc: boe->enable_gpio, value: 1); |
1518 | usleep_range(min: 6000, max: 10000); |
1519 | |
1520 | ret = boe_panel_init_dcs_cmd(boe); |
1521 | if (ret < 0) { |
1522 | dev_err(panel->dev, "failed to init panel: %d\n" , ret); |
1523 | goto poweroff; |
1524 | } |
1525 | |
1526 | boe->prepared = true; |
1527 | |
1528 | return 0; |
1529 | |
1530 | poweroff: |
1531 | regulator_disable(regulator: boe->avee); |
1532 | poweroffavdd: |
1533 | regulator_disable(regulator: boe->avdd); |
1534 | poweroff1v8: |
1535 | usleep_range(min: 5000, max: 7000); |
1536 | regulator_disable(regulator: boe->pp1800); |
1537 | gpiod_set_value(desc: boe->enable_gpio, value: 0); |
1538 | |
1539 | return ret; |
1540 | } |
1541 | |
1542 | static int boe_panel_enable(struct drm_panel *panel) |
1543 | { |
1544 | msleep(msecs: 130); |
1545 | return 0; |
1546 | } |
1547 | |
1548 | static const struct drm_display_mode boe_tv110c9m_default_mode = { |
1549 | .clock = 166594, |
1550 | .hdisplay = 1200, |
1551 | .hsync_start = 1200 + 40, |
1552 | .hsync_end = 1200 + 40 + 8, |
1553 | .htotal = 1200 + 40 + 8 + 28, |
1554 | .vdisplay = 2000, |
1555 | .vsync_start = 2000 + 26, |
1556 | .vsync_end = 2000 + 26 + 2, |
1557 | .vtotal = 2000 + 26 + 2 + 148, |
1558 | .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, |
1559 | }; |
1560 | |
1561 | static const struct panel_desc boe_tv110c9m_desc = { |
1562 | .modes = &boe_tv110c9m_default_mode, |
1563 | .bpc = 8, |
1564 | .size = { |
1565 | .width_mm = 143, |
1566 | .height_mm = 238, |
1567 | }, |
1568 | .lanes = 4, |
1569 | .format = MIPI_DSI_FMT_RGB888, |
1570 | .mode_flags = MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_VIDEO |
1571 | | MIPI_DSI_MODE_VIDEO_HSE |
1572 | | MIPI_DSI_CLOCK_NON_CONTINUOUS |
1573 | | MIPI_DSI_MODE_VIDEO_BURST, |
1574 | .init_cmds = boe_tv110c9m_init_cmd, |
1575 | }; |
1576 | |
1577 | static const struct drm_display_mode inx_hj110iz_default_mode = { |
1578 | .clock = 168432, |
1579 | .hdisplay = 1200, |
1580 | .hsync_start = 1200 + 40, |
1581 | .hsync_end = 1200 + 40 + 8, |
1582 | .htotal = 1200 + 40 + 8 + 28, |
1583 | .vdisplay = 2000, |
1584 | .vsync_start = 2000 + 26, |
1585 | .vsync_end = 2000 + 26 + 2, |
1586 | .vtotal = 2000 + 26 + 2 + 172, |
1587 | .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, |
1588 | }; |
1589 | |
1590 | static const struct panel_desc inx_hj110iz_desc = { |
1591 | .modes = &inx_hj110iz_default_mode, |
1592 | .bpc = 8, |
1593 | .size = { |
1594 | .width_mm = 143, |
1595 | .height_mm = 238, |
1596 | }, |
1597 | .lanes = 4, |
1598 | .format = MIPI_DSI_FMT_RGB888, |
1599 | .mode_flags = MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_VIDEO |
1600 | | MIPI_DSI_MODE_VIDEO_HSE |
1601 | | MIPI_DSI_CLOCK_NON_CONTINUOUS |
1602 | | MIPI_DSI_MODE_VIDEO_BURST, |
1603 | .init_cmds = inx_hj110iz_init_cmd, |
1604 | }; |
1605 | |
1606 | static const struct drm_display_mode boe_tv101wum_nl6_default_mode = { |
1607 | .clock = 159425, |
1608 | .hdisplay = 1200, |
1609 | .hsync_start = 1200 + 100, |
1610 | .hsync_end = 1200 + 100 + 40, |
1611 | .htotal = 1200 + 100 + 40 + 24, |
1612 | .vdisplay = 1920, |
1613 | .vsync_start = 1920 + 10, |
1614 | .vsync_end = 1920 + 10 + 14, |
1615 | .vtotal = 1920 + 10 + 14 + 4, |
1616 | }; |
1617 | |
1618 | static const struct panel_desc boe_tv101wum_nl6_desc = { |
1619 | .modes = &boe_tv101wum_nl6_default_mode, |
1620 | .bpc = 8, |
1621 | .size = { |
1622 | .width_mm = 135, |
1623 | .height_mm = 216, |
1624 | }, |
1625 | .lanes = 4, |
1626 | .format = MIPI_DSI_FMT_RGB888, |
1627 | .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | |
1628 | MIPI_DSI_MODE_LPM, |
1629 | .init_cmds = boe_init_cmd, |
1630 | .discharge_on_disable = false, |
1631 | }; |
1632 | |
1633 | static const struct drm_display_mode auo_kd101n80_45na_default_mode = { |
1634 | .clock = 157000, |
1635 | .hdisplay = 1200, |
1636 | .hsync_start = 1200 + 60, |
1637 | .hsync_end = 1200 + 60 + 24, |
1638 | .htotal = 1200 + 60 + 24 + 56, |
1639 | .vdisplay = 1920, |
1640 | .vsync_start = 1920 + 16, |
1641 | .vsync_end = 1920 + 16 + 4, |
1642 | .vtotal = 1920 + 16 + 4 + 16, |
1643 | }; |
1644 | |
1645 | static const struct panel_desc auo_kd101n80_45na_desc = { |
1646 | .modes = &auo_kd101n80_45na_default_mode, |
1647 | .bpc = 8, |
1648 | .size = { |
1649 | .width_mm = 135, |
1650 | .height_mm = 216, |
1651 | }, |
1652 | .lanes = 4, |
1653 | .format = MIPI_DSI_FMT_RGB888, |
1654 | .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | |
1655 | MIPI_DSI_MODE_LPM, |
1656 | .init_cmds = auo_kd101n80_45na_init_cmd, |
1657 | .discharge_on_disable = true, |
1658 | }; |
1659 | |
1660 | static const struct drm_display_mode boe_tv101wum_n53_default_mode = { |
1661 | .clock = 159916, |
1662 | .hdisplay = 1200, |
1663 | .hsync_start = 1200 + 80, |
1664 | .hsync_end = 1200 + 80 + 24, |
1665 | .htotal = 1200 + 80 + 24 + 60, |
1666 | .vdisplay = 1920, |
1667 | .vsync_start = 1920 + 20, |
1668 | .vsync_end = 1920 + 20 + 4, |
1669 | .vtotal = 1920 + 20 + 4 + 10, |
1670 | .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, |
1671 | }; |
1672 | |
1673 | static const struct panel_desc boe_tv101wum_n53_desc = { |
1674 | .modes = &boe_tv101wum_n53_default_mode, |
1675 | .bpc = 8, |
1676 | .size = { |
1677 | .width_mm = 135, |
1678 | .height_mm = 216, |
1679 | }, |
1680 | .lanes = 4, |
1681 | .format = MIPI_DSI_FMT_RGB888, |
1682 | .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | |
1683 | MIPI_DSI_MODE_LPM, |
1684 | .init_cmds = boe_init_cmd, |
1685 | }; |
1686 | |
1687 | static const struct drm_display_mode auo_b101uan08_3_default_mode = { |
1688 | .clock = 159667, |
1689 | .hdisplay = 1200, |
1690 | .hsync_start = 1200 + 60, |
1691 | .hsync_end = 1200 + 60 + 4, |
1692 | .htotal = 1200 + 60 + 4 + 80, |
1693 | .vdisplay = 1920, |
1694 | .vsync_start = 1920 + 34, |
1695 | .vsync_end = 1920 + 34 + 2, |
1696 | .vtotal = 1920 + 34 + 2 + 24, |
1697 | .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, |
1698 | }; |
1699 | |
1700 | static const struct panel_desc auo_b101uan08_3_desc = { |
1701 | .modes = &auo_b101uan08_3_default_mode, |
1702 | .bpc = 8, |
1703 | .size = { |
1704 | .width_mm = 135, |
1705 | .height_mm = 216, |
1706 | }, |
1707 | .lanes = 4, |
1708 | .format = MIPI_DSI_FMT_RGB888, |
1709 | .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | |
1710 | MIPI_DSI_MODE_LPM, |
1711 | .init_cmds = auo_b101uan08_3_init_cmd, |
1712 | .lp11_before_reset = true, |
1713 | }; |
1714 | |
1715 | static const struct drm_display_mode boe_tv105wum_nw0_default_mode = { |
1716 | .clock = 159916, |
1717 | .hdisplay = 1200, |
1718 | .hsync_start = 1200 + 80, |
1719 | .hsync_end = 1200 + 80 + 24, |
1720 | .htotal = 1200 + 80 + 24 + 60, |
1721 | .vdisplay = 1920, |
1722 | .vsync_start = 1920 + 20, |
1723 | .vsync_end = 1920 + 20 + 4, |
1724 | .vtotal = 1920 + 20 + 4 + 10, |
1725 | .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, |
1726 | }; |
1727 | |
1728 | static const struct panel_desc boe_tv105wum_nw0_desc = { |
1729 | .modes = &boe_tv105wum_nw0_default_mode, |
1730 | .bpc = 8, |
1731 | .size = { |
1732 | .width_mm = 141, |
1733 | .height_mm = 226, |
1734 | }, |
1735 | .lanes = 4, |
1736 | .format = MIPI_DSI_FMT_RGB888, |
1737 | .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | |
1738 | MIPI_DSI_MODE_LPM, |
1739 | .init_cmds = boe_init_cmd, |
1740 | .lp11_before_reset = true, |
1741 | }; |
1742 | |
1743 | static const struct drm_display_mode starry_qfh032011_53g_default_mode = { |
1744 | .clock = 165731, |
1745 | .hdisplay = 1200, |
1746 | .hsync_start = 1200 + 100, |
1747 | .hsync_end = 1200 + 100 + 10, |
1748 | .htotal = 1200 + 100 + 10 + 100, |
1749 | .vdisplay = 1920, |
1750 | .vsync_start = 1920 + 14, |
1751 | .vsync_end = 1920 + 14 + 10, |
1752 | .vtotal = 1920 + 14 + 10 + 15, |
1753 | }; |
1754 | |
1755 | static const struct panel_desc starry_qfh032011_53g_desc = { |
1756 | .modes = &starry_qfh032011_53g_default_mode, |
1757 | .bpc = 8, |
1758 | .size = { |
1759 | .width_mm = 135, |
1760 | .height_mm = 216, |
1761 | }, |
1762 | .lanes = 4, |
1763 | .format = MIPI_DSI_FMT_RGB888, |
1764 | .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | |
1765 | MIPI_DSI_MODE_LPM, |
1766 | .init_cmds = starry_qfh032011_53g_init_cmd, |
1767 | .lp11_before_reset = true, |
1768 | }; |
1769 | |
1770 | static const struct drm_display_mode starry_himax83102_j02_default_mode = { |
1771 | .clock = 162680, |
1772 | .hdisplay = 1200, |
1773 | .hsync_start = 1200 + 60, |
1774 | .hsync_end = 1200 + 60 + 20, |
1775 | .htotal = 1200 + 60 + 20 + 40, |
1776 | .vdisplay = 1920, |
1777 | .vsync_start = 1920 + 116, |
1778 | .vsync_end = 1920 + 116 + 8, |
1779 | .vtotal = 1920 + 116 + 8 + 12, |
1780 | .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, |
1781 | }; |
1782 | |
1783 | static const struct panel_desc starry_himax83102_j02_desc = { |
1784 | .modes = &starry_himax83102_j02_default_mode, |
1785 | .bpc = 8, |
1786 | .size = { |
1787 | .width_mm = 141, |
1788 | .height_mm = 226, |
1789 | }, |
1790 | .lanes = 4, |
1791 | .format = MIPI_DSI_FMT_RGB888, |
1792 | .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | |
1793 | MIPI_DSI_MODE_LPM, |
1794 | .init_cmds = starry_himax83102_j02_init_cmd, |
1795 | .lp11_before_reset = true, |
1796 | }; |
1797 | |
1798 | static int boe_panel_get_modes(struct drm_panel *panel, |
1799 | struct drm_connector *connector) |
1800 | { |
1801 | struct boe_panel *boe = to_boe_panel(panel); |
1802 | const struct drm_display_mode *m = boe->desc->modes; |
1803 | struct drm_display_mode *mode; |
1804 | |
1805 | mode = drm_mode_duplicate(dev: connector->dev, mode: m); |
1806 | if (!mode) { |
1807 | dev_err(panel->dev, "failed to add mode %ux%u@%u\n" , |
1808 | m->hdisplay, m->vdisplay, drm_mode_vrefresh(m)); |
1809 | return -ENOMEM; |
1810 | } |
1811 | |
1812 | mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; |
1813 | drm_mode_set_name(mode); |
1814 | drm_mode_probed_add(connector, mode); |
1815 | |
1816 | connector->display_info.width_mm = boe->desc->size.width_mm; |
1817 | connector->display_info.height_mm = boe->desc->size.height_mm; |
1818 | connector->display_info.bpc = boe->desc->bpc; |
1819 | /* |
1820 | * TODO: Remove once all drm drivers call |
1821 | * drm_connector_set_orientation_from_panel() |
1822 | */ |
1823 | drm_connector_set_panel_orientation(connector, panel_orientation: boe->orientation); |
1824 | |
1825 | return 1; |
1826 | } |
1827 | |
1828 | static enum drm_panel_orientation boe_panel_get_orientation(struct drm_panel *panel) |
1829 | { |
1830 | struct boe_panel *boe = to_boe_panel(panel); |
1831 | |
1832 | return boe->orientation; |
1833 | } |
1834 | |
1835 | static const struct drm_panel_funcs boe_panel_funcs = { |
1836 | .disable = boe_panel_disable, |
1837 | .unprepare = boe_panel_unprepare, |
1838 | .prepare = boe_panel_prepare, |
1839 | .enable = boe_panel_enable, |
1840 | .get_modes = boe_panel_get_modes, |
1841 | .get_orientation = boe_panel_get_orientation, |
1842 | }; |
1843 | |
1844 | static int boe_panel_add(struct boe_panel *boe) |
1845 | { |
1846 | struct device *dev = &boe->dsi->dev; |
1847 | int err; |
1848 | |
1849 | boe->avdd = devm_regulator_get(dev, id: "avdd" ); |
1850 | if (IS_ERR(ptr: boe->avdd)) |
1851 | return PTR_ERR(ptr: boe->avdd); |
1852 | |
1853 | boe->avee = devm_regulator_get(dev, id: "avee" ); |
1854 | if (IS_ERR(ptr: boe->avee)) |
1855 | return PTR_ERR(ptr: boe->avee); |
1856 | |
1857 | boe->pp3300 = devm_regulator_get(dev, id: "pp3300" ); |
1858 | if (IS_ERR(ptr: boe->pp3300)) |
1859 | return PTR_ERR(ptr: boe->pp3300); |
1860 | |
1861 | boe->pp1800 = devm_regulator_get(dev, id: "pp1800" ); |
1862 | if (IS_ERR(ptr: boe->pp1800)) |
1863 | return PTR_ERR(ptr: boe->pp1800); |
1864 | |
1865 | boe->enable_gpio = devm_gpiod_get(dev, con_id: "enable" , flags: GPIOD_OUT_LOW); |
1866 | if (IS_ERR(ptr: boe->enable_gpio)) { |
1867 | dev_err(dev, "cannot get reset-gpios %ld\n" , |
1868 | PTR_ERR(boe->enable_gpio)); |
1869 | return PTR_ERR(ptr: boe->enable_gpio); |
1870 | } |
1871 | |
1872 | gpiod_set_value(desc: boe->enable_gpio, value: 0); |
1873 | |
1874 | boe->base.prepare_prev_first = true; |
1875 | |
1876 | drm_panel_init(panel: &boe->base, dev, funcs: &boe_panel_funcs, |
1877 | DRM_MODE_CONNECTOR_DSI); |
1878 | err = of_drm_get_panel_orientation(np: dev->of_node, orientation: &boe->orientation); |
1879 | if (err < 0) { |
1880 | dev_err(dev, "%pOF: failed to get orientation %d\n" , dev->of_node, err); |
1881 | return err; |
1882 | } |
1883 | |
1884 | err = drm_panel_of_backlight(panel: &boe->base); |
1885 | if (err) |
1886 | return err; |
1887 | |
1888 | boe->base.funcs = &boe_panel_funcs; |
1889 | boe->base.dev = &boe->dsi->dev; |
1890 | |
1891 | drm_panel_add(panel: &boe->base); |
1892 | |
1893 | return 0; |
1894 | } |
1895 | |
1896 | static int boe_panel_probe(struct mipi_dsi_device *dsi) |
1897 | { |
1898 | struct boe_panel *boe; |
1899 | int ret; |
1900 | const struct panel_desc *desc; |
1901 | |
1902 | boe = devm_kzalloc(dev: &dsi->dev, size: sizeof(*boe), GFP_KERNEL); |
1903 | if (!boe) |
1904 | return -ENOMEM; |
1905 | |
1906 | desc = of_device_get_match_data(dev: &dsi->dev); |
1907 | dsi->lanes = desc->lanes; |
1908 | dsi->format = desc->format; |
1909 | dsi->mode_flags = desc->mode_flags; |
1910 | boe->desc = desc; |
1911 | boe->dsi = dsi; |
1912 | ret = boe_panel_add(boe); |
1913 | if (ret < 0) |
1914 | return ret; |
1915 | |
1916 | mipi_dsi_set_drvdata(dsi, data: boe); |
1917 | |
1918 | ret = mipi_dsi_attach(dsi); |
1919 | if (ret) |
1920 | drm_panel_remove(panel: &boe->base); |
1921 | |
1922 | return ret; |
1923 | } |
1924 | |
1925 | static void boe_panel_shutdown(struct mipi_dsi_device *dsi) |
1926 | { |
1927 | struct boe_panel *boe = mipi_dsi_get_drvdata(dsi); |
1928 | |
1929 | drm_panel_disable(panel: &boe->base); |
1930 | drm_panel_unprepare(panel: &boe->base); |
1931 | } |
1932 | |
1933 | static void boe_panel_remove(struct mipi_dsi_device *dsi) |
1934 | { |
1935 | struct boe_panel *boe = mipi_dsi_get_drvdata(dsi); |
1936 | int ret; |
1937 | |
1938 | boe_panel_shutdown(dsi); |
1939 | |
1940 | ret = mipi_dsi_detach(dsi); |
1941 | if (ret < 0) |
1942 | dev_err(&dsi->dev, "failed to detach from DSI host: %d\n" , ret); |
1943 | |
1944 | if (boe->base.dev) |
1945 | drm_panel_remove(panel: &boe->base); |
1946 | } |
1947 | |
1948 | static const struct of_device_id boe_of_match[] = { |
1949 | { .compatible = "boe,tv101wum-nl6" , |
1950 | .data = &boe_tv101wum_nl6_desc |
1951 | }, |
1952 | { .compatible = "auo,kd101n80-45na" , |
1953 | .data = &auo_kd101n80_45na_desc |
1954 | }, |
1955 | { .compatible = "boe,tv101wum-n53" , |
1956 | .data = &boe_tv101wum_n53_desc |
1957 | }, |
1958 | { .compatible = "auo,b101uan08.3" , |
1959 | .data = &auo_b101uan08_3_desc |
1960 | }, |
1961 | { .compatible = "boe,tv105wum-nw0" , |
1962 | .data = &boe_tv105wum_nw0_desc |
1963 | }, |
1964 | { .compatible = "boe,tv110c9m-ll3" , |
1965 | .data = &boe_tv110c9m_desc |
1966 | }, |
1967 | { .compatible = "innolux,hj110iz-01a" , |
1968 | .data = &inx_hj110iz_desc |
1969 | }, |
1970 | { .compatible = "starry,2081101qfh032011-53g" , |
1971 | .data = &starry_qfh032011_53g_desc |
1972 | }, |
1973 | { .compatible = "starry,himax83102-j02" , |
1974 | .data = &starry_himax83102_j02_desc |
1975 | }, |
1976 | { /* sentinel */ } |
1977 | }; |
1978 | MODULE_DEVICE_TABLE(of, boe_of_match); |
1979 | |
1980 | static struct mipi_dsi_driver boe_panel_driver = { |
1981 | .driver = { |
1982 | .name = "panel-boe-tv101wum-nl6" , |
1983 | .of_match_table = boe_of_match, |
1984 | }, |
1985 | .probe = boe_panel_probe, |
1986 | .remove = boe_panel_remove, |
1987 | .shutdown = boe_panel_shutdown, |
1988 | }; |
1989 | module_mipi_dsi_driver(boe_panel_driver); |
1990 | |
1991 | MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>" ); |
1992 | MODULE_DESCRIPTION("BOE tv101wum-nl6 1200x1920 video mode panel driver" ); |
1993 | MODULE_LICENSE("GPL v2" ); |
1994 | |