| 1 | /* |
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| 2 | * Copyright 2011 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | */ |
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| 23 | #ifndef RV6XXD_H |
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| 24 | #define RV6XXD_H |
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| 25 | |
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| 26 | /* RV6xx power management */ |
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| 27 | #define SPLL_CNTL_MODE 0x60c |
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| 28 | # define SPLL_DIV_SYNC (1 << 5) |
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| 29 | |
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| 30 | #define GENERAL_PWRMGT 0x618 |
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| 31 | # define GLOBAL_PWRMGT_EN (1 << 0) |
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| 32 | # define STATIC_PM_EN (1 << 1) |
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| 33 | # define MOBILE_SU (1 << 2) |
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| 34 | # define THERMAL_PROTECTION_DIS (1 << 3) |
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| 35 | # define THERMAL_PROTECTION_TYPE (1 << 4) |
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| 36 | # define ENABLE_GEN2PCIE (1 << 5) |
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| 37 | # define SW_GPIO_INDEX(x) ((x) << 6) |
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| 38 | # define SW_GPIO_INDEX_MASK (3 << 6) |
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| 39 | # define LOW_VOLT_D2_ACPI (1 << 8) |
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| 40 | # define LOW_VOLT_D3_ACPI (1 << 9) |
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| 41 | # define VOLT_PWRMGT_EN (1 << 10) |
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| 42 | # define BACKBIAS_PAD_EN (1 << 16) |
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| 43 | # define BACKBIAS_VALUE (1 << 17) |
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| 44 | # define BACKBIAS_DPM_CNTL (1 << 18) |
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| 45 | # define DYN_SPREAD_SPECTRUM_EN (1 << 21) |
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| 46 | |
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| 47 | #define MCLK_PWRMGT_CNTL 0x624 |
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| 48 | # define MPLL_PWRMGT_OFF (1 << 0) |
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| 49 | # define YCLK_TURNOFF (1 << 1) |
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| 50 | # define MPLL_TURNOFF (1 << 2) |
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| 51 | # define SU_MCLK_USE_BCLK (1 << 3) |
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| 52 | # define DLL_READY (1 << 4) |
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| 53 | # define MC_BUSY (1 << 5) |
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| 54 | # define MC_INT_CNTL (1 << 7) |
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| 55 | # define MRDCKA_SLEEP (1 << 8) |
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| 56 | # define MRDCKB_SLEEP (1 << 9) |
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| 57 | # define MRDCKC_SLEEP (1 << 10) |
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| 58 | # define MRDCKD_SLEEP (1 << 11) |
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| 59 | # define MRDCKE_SLEEP (1 << 12) |
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| 60 | # define MRDCKF_SLEEP (1 << 13) |
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| 61 | # define MRDCKG_SLEEP (1 << 14) |
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| 62 | # define MRDCKH_SLEEP (1 << 15) |
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| 63 | # define MRDCKA_RESET (1 << 16) |
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| 64 | # define MRDCKB_RESET (1 << 17) |
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| 65 | # define MRDCKC_RESET (1 << 18) |
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| 66 | # define MRDCKD_RESET (1 << 19) |
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| 67 | # define MRDCKE_RESET (1 << 20) |
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| 68 | # define MRDCKF_RESET (1 << 21) |
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| 69 | # define MRDCKG_RESET (1 << 22) |
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| 70 | # define MRDCKH_RESET (1 << 23) |
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| 71 | # define DLL_READY_READ (1 << 24) |
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| 72 | # define USE_DISPLAY_GAP (1 << 25) |
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| 73 | # define USE_DISPLAY_URGENT_NORMAL (1 << 26) |
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| 74 | # define USE_DISPLAY_GAP_CTXSW (1 << 27) |
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| 75 | # define MPLL_TURNOFF_D2 (1 << 28) |
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| 76 | # define USE_DISPLAY_URGENT_CTXSW (1 << 29) |
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| 77 | |
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| 78 | #define MPLL_FREQ_LEVEL_0 0x6e8 |
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| 79 | # define LEVEL0_MPLL_POST_DIV(x) ((x) << 0) |
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| 80 | # define LEVEL0_MPLL_POST_DIV_MASK (0xff << 0) |
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| 81 | # define LEVEL0_MPLL_FB_DIV(x) ((x) << 8) |
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| 82 | # define LEVEL0_MPLL_FB_DIV_MASK (0xfff << 8) |
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| 83 | # define LEVEL0_MPLL_REF_DIV(x) ((x) << 20) |
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| 84 | # define LEVEL0_MPLL_REF_DIV_MASK (0x3f << 20) |
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| 85 | # define LEVEL0_MPLL_DIV_EN (1 << 28) |
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| 86 | # define LEVEL0_DLL_BYPASS (1 << 29) |
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| 87 | # define LEVEL0_DLL_RESET (1 << 30) |
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| 88 | |
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| 89 | #define VID_RT 0x6f8 |
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| 90 | # define VID_CRT(x) ((x) << 0) |
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| 91 | # define VID_CRT_MASK (0x1fff << 0) |
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| 92 | # define VID_CRTU(x) ((x) << 13) |
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| 93 | # define VID_CRTU_MASK (7 << 13) |
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| 94 | # define SSTU(x) ((x) << 16) |
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| 95 | # define SSTU_MASK (7 << 16) |
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| 96 | # define VID_SWT(x) ((x) << 19) |
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| 97 | # define VID_SWT_MASK (0x1f << 19) |
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| 98 | # define BRT(x) ((x) << 24) |
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| 99 | # define BRT_MASK (0xff << 24) |
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| 100 | |
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| 101 | #define TARGET_AND_CURRENT_PROFILE_INDEX 0x70c |
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| 102 | # define TARGET_PROFILE_INDEX_MASK (3 << 0) |
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| 103 | # define TARGET_PROFILE_INDEX_SHIFT 0 |
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| 104 | # define CURRENT_PROFILE_INDEX_MASK (3 << 2) |
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| 105 | # define CURRENT_PROFILE_INDEX_SHIFT 2 |
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| 106 | # define DYN_PWR_ENTER_INDEX(x) ((x) << 4) |
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| 107 | # define DYN_PWR_ENTER_INDEX_MASK (3 << 4) |
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| 108 | # define DYN_PWR_ENTER_INDEX_SHIFT 4 |
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| 109 | # define CURR_MCLK_INDEX_MASK (3 << 6) |
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| 110 | # define CURR_MCLK_INDEX_SHIFT 6 |
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| 111 | # define CURR_SCLK_INDEX_MASK (0x1f << 8) |
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| 112 | # define CURR_SCLK_INDEX_SHIFT 8 |
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| 113 | # define CURR_VID_INDEX_MASK (3 << 13) |
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| 114 | # define CURR_VID_INDEX_SHIFT 13 |
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| 115 | |
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| 116 | #define VID_UPPER_GPIO_CNTL 0x740 |
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| 117 | # define CTXSW_UPPER_GPIO_VALUES(x) ((x) << 0) |
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| 118 | # define CTXSW_UPPER_GPIO_VALUES_MASK (7 << 0) |
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| 119 | # define HIGH_UPPER_GPIO_VALUES(x) ((x) << 3) |
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| 120 | # define HIGH_UPPER_GPIO_VALUES_MASK (7 << 3) |
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| 121 | # define MEDIUM_UPPER_GPIO_VALUES(x) ((x) << 6) |
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| 122 | # define MEDIUM_UPPER_GPIO_VALUES_MASK (7 << 6) |
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| 123 | # define LOW_UPPER_GPIO_VALUES(x) ((x) << 9) |
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| 124 | # define LOW_UPPER_GPIO_VALUES_MASK (7 << 9) |
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| 125 | # define CTXSW_BACKBIAS_VALUE (1 << 12) |
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| 126 | # define HIGH_BACKBIAS_VALUE (1 << 13) |
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| 127 | # define MEDIUM_BACKBIAS_VALUE (1 << 14) |
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| 128 | # define LOW_BACKBIAS_VALUE (1 << 15) |
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| 129 | |
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| 130 | #define CG_DISPLAY_GAP_CNTL 0x7dc |
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| 131 | # define DISP1_GAP(x) ((x) << 0) |
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| 132 | # define DISP1_GAP_MASK (3 << 0) |
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| 133 | # define DISP2_GAP(x) ((x) << 2) |
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| 134 | # define DISP2_GAP_MASK (3 << 2) |
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| 135 | # define VBI_TIMER_COUNT(x) ((x) << 4) |
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| 136 | # define VBI_TIMER_COUNT_MASK (0x3fff << 4) |
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| 137 | # define VBI_TIMER_UNIT(x) ((x) << 20) |
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| 138 | # define VBI_TIMER_UNIT_MASK (7 << 20) |
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| 139 | # define DISP1_GAP_MCHG(x) ((x) << 24) |
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| 140 | # define DISP1_GAP_MCHG_MASK (3 << 24) |
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| 141 | # define DISP2_GAP_MCHG(x) ((x) << 26) |
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| 142 | # define DISP2_GAP_MCHG_MASK (3 << 26) |
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| 143 | |
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| 144 | #define CG_THERMAL_CTRL 0x7f0 |
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| 145 | # define DPM_EVENT_SRC(x) ((x) << 0) |
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| 146 | # define DPM_EVENT_SRC_MASK (7 << 0) |
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| 147 | # define THERM_INC_CLK (1 << 3) |
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| 148 | # define TOFFSET(x) ((x) << 4) |
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| 149 | # define TOFFSET_MASK (0xff << 4) |
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| 150 | # define DIG_THERM_DPM(x) ((x) << 12) |
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| 151 | # define DIG_THERM_DPM_MASK (0xff << 12) |
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| 152 | # define CTF_SEL(x) ((x) << 20) |
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| 153 | # define CTF_SEL_MASK (7 << 20) |
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| 154 | # define CTF_PAD_POLARITY (1 << 23) |
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| 155 | # define CTF_PAD_EN (1 << 24) |
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| 156 | |
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| 157 | #define CG_SPLL_SPREAD_SPECTRUM_LOW 0x820 |
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| 158 | # define SSEN (1 << 0) |
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| 159 | # define CLKS(x) ((x) << 3) |
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| 160 | # define CLKS_MASK (0xff << 3) |
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| 161 | # define CLKS_SHIFT 3 |
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| 162 | # define CLKV(x) ((x) << 11) |
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| 163 | # define CLKV_MASK (0x7ff << 11) |
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| 164 | # define CLKV_SHIFT 11 |
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| 165 | #define CG_MPLL_SPREAD_SPECTRUM 0x830 |
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| 166 | |
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| 167 | #define CITF_CNTL 0x200c |
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| 168 | # define BLACKOUT_RD (1 << 0) |
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| 169 | # define BLACKOUT_WR (1 << 1) |
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| 170 | |
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| 171 | #define RAMCFG 0x2408 |
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| 172 | #define NOOFBANK_SHIFT 0 |
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| 173 | #define NOOFBANK_MASK 0x00000001 |
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| 174 | #define NOOFRANK_SHIFT 1 |
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| 175 | #define NOOFRANK_MASK 0x00000002 |
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| 176 | #define NOOFROWS_SHIFT 2 |
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| 177 | #define NOOFROWS_MASK 0x0000001C |
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| 178 | #define NOOFCOLS_SHIFT 5 |
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| 179 | #define NOOFCOLS_MASK 0x00000060 |
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| 180 | #define CHANSIZE_SHIFT 7 |
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| 181 | #define CHANSIZE_MASK 0x00000080 |
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| 182 | #define BURSTLENGTH_SHIFT 8 |
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| 183 | #define BURSTLENGTH_MASK 0x00000100 |
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| 184 | #define CHANSIZE_OVERRIDE (1 << 10) |
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| 185 | |
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| 186 | #define SQM_RATIO 0x2424 |
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| 187 | # define STATE0(x) ((x) << 0) |
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| 188 | # define STATE0_MASK (0xff << 0) |
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| 189 | # define STATE1(x) ((x) << 8) |
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| 190 | # define STATE1_MASK (0xff << 8) |
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| 191 | # define STATE2(x) ((x) << 16) |
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| 192 | # define STATE2_MASK (0xff << 16) |
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| 193 | # define STATE3(x) ((x) << 24) |
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| 194 | # define STATE3_MASK (0xff << 24) |
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| 195 | |
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| 196 | #define ARB_RFSH_CNTL 0x2460 |
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| 197 | # define ENABLE (1 << 0) |
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| 198 | #define ARB_RFSH_RATE 0x2464 |
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| 199 | # define POWERMODE0(x) ((x) << 0) |
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| 200 | # define POWERMODE0_MASK (0xff << 0) |
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| 201 | # define POWERMODE1(x) ((x) << 8) |
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| 202 | # define POWERMODE1_MASK (0xff << 8) |
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| 203 | # define POWERMODE2(x) ((x) << 16) |
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| 204 | # define POWERMODE2_MASK (0xff << 16) |
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| 205 | # define POWERMODE3(x) ((x) << 24) |
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| 206 | # define POWERMODE3_MASK (0xff << 24) |
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| 207 | |
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| 208 | #define MC_SEQ_DRAM 0x2608 |
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| 209 | # define CKE_DYN (1 << 12) |
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| 210 | |
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| 211 | #define MC_SEQ_CMD 0x26c4 |
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| 212 | |
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| 213 | #define MC_SEQ_RESERVE_S 0x2890 |
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| 214 | #define MC_SEQ_RESERVE_M 0x2894 |
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| 215 | |
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| 216 | #define LVTMA_DATA_SYNCHRONIZATION 0x7adc |
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| 217 | # define LVTMA_PFREQCHG (1 << 8) |
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| 218 | #define DCE3_LVTMA_DATA_SYNCHRONIZATION 0x7f98 |
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| 219 | |
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| 220 | /* PCIE indirect regs */ |
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| 221 | #define PCIE_P_CNTL 0x40 |
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| 222 | # define P_PLL_PWRDN_IN_L1L23 (1 << 3) |
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| 223 | # define P_PLL_BUF_PDNB (1 << 4) |
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| 224 | # define P_PLL_PDNB (1 << 9) |
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| 225 | # define P_ALLOW_PRX_FRONTEND_SHUTOFF (1 << 12) |
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| 226 | /* PCIE PORT indirect regs */ |
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| 227 | #define PCIE_LC_CNTL 0xa0 |
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| 228 | # define LC_L0S_INACTIVITY(x) ((x) << 8) |
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| 229 | # define LC_L0S_INACTIVITY_MASK (0xf << 8) |
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| 230 | # define LC_L0S_INACTIVITY_SHIFT 8 |
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| 231 | # define LC_L1_INACTIVITY(x) ((x) << 12) |
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| 232 | # define LC_L1_INACTIVITY_MASK (0xf << 12) |
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| 233 | # define LC_L1_INACTIVITY_SHIFT 12 |
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| 234 | # define LC_PMI_TO_L1_DIS (1 << 16) |
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| 235 | # define LC_ASPM_TO_L1_DIS (1 << 24) |
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| 236 | #define PCIE_LC_SPEED_CNTL 0xa4 |
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| 237 | # define LC_GEN2_EN (1 << 0) |
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| 238 | # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 7) |
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| 239 | # define LC_CURRENT_DATA_RATE (1 << 11) |
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| 240 | # define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12) |
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| 241 | # define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12) |
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| 242 | # define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12 |
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| 243 | # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) |
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| 244 | # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) |
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| 245 | |
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| 246 | #endif |
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| 247 | |
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