| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * R-Car Display Unit Registers Definitions |
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| 4 | * |
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| 5 | * Copyright (C) 2013-2015 Renesas Electronics Corporation |
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| 6 | * |
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| 7 | * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) |
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| 8 | */ |
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| 9 | |
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| 10 | #ifndef __RCAR_DU_REGS_H__ |
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| 11 | #define __RCAR_DU_REGS_H__ |
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| 12 | |
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| 13 | #define DU0_REG_OFFSET 0x00000 |
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| 14 | #define DU1_REG_OFFSET 0x30000 |
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| 15 | #define DU2_REG_OFFSET 0x40000 |
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| 16 | #define DU3_REG_OFFSET 0x70000 |
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| 17 | |
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| 18 | /* ----------------------------------------------------------------------------- |
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| 19 | * Display Control Registers |
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| 20 | */ |
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| 21 | |
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| 22 | #define DSYSR 0x00000 /* display 1 */ |
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| 23 | #define DSYSR_ILTS (1 << 29) |
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| 24 | #define DSYSR_DSEC (1 << 20) |
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| 25 | #define DSYSR_IUPD (1 << 16) |
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| 26 | #define DSYSR_DRES (1 << 9) |
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| 27 | #define DSYSR_DEN (1 << 8) |
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| 28 | #define DSYSR_TVM_MASTER (0 << 6) |
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| 29 | #define DSYSR_TVM_SWITCH (1 << 6) |
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| 30 | #define DSYSR_TVM_TVSYNC (2 << 6) |
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| 31 | #define DSYSR_TVM_MASK (3 << 6) |
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| 32 | #define DSYSR_SCM_INT_NONE (0 << 4) |
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| 33 | #define DSYSR_SCM_INT_SYNC (2 << 4) |
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| 34 | #define DSYSR_SCM_INT_VIDEO (3 << 4) |
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| 35 | #define DSYSR_SCM_MASK (3 << 4) |
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| 36 | |
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| 37 | #define DSMR 0x00004 |
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| 38 | #define DSMR_VSPM (1 << 28) |
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| 39 | #define DSMR_ODPM (1 << 27) |
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| 40 | #define DSMR_DIPM_DISP (0 << 25) |
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| 41 | #define DSMR_DIPM_CSYNC (1 << 25) |
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| 42 | #define DSMR_DIPM_DE (3 << 25) |
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| 43 | #define DSMR_DIPM_MASK (3 << 25) |
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| 44 | #define DSMR_CSPM (1 << 24) |
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| 45 | #define DSMR_DIL (1 << 19) |
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| 46 | #define DSMR_VSL (1 << 18) |
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| 47 | #define DSMR_HSL (1 << 17) |
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| 48 | #define DSMR_DDIS (1 << 16) |
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| 49 | #define DSMR_CDEL (1 << 15) |
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| 50 | #define DSMR_CDEM_CDE (0 << 13) |
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| 51 | #define DSMR_CDEM_LOW (2 << 13) |
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| 52 | #define DSMR_CDEM_HIGH (3 << 13) |
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| 53 | #define DSMR_CDEM_MASK (3 << 13) |
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| 54 | #define DSMR_CDED (1 << 12) |
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| 55 | #define DSMR_ODEV (1 << 8) |
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| 56 | #define DSMR_CSY_VH_OR (0 << 6) |
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| 57 | #define DSMR_CSY_333 (2 << 6) |
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| 58 | #define DSMR_CSY_222 (3 << 6) |
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| 59 | #define DSMR_CSY_MASK (3 << 6) |
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| 60 | |
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| 61 | #define DSSR 0x00008 |
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| 62 | #define DSSR_VC1FB_DSA0 (0 << 30) |
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| 63 | #define DSSR_VC1FB_DSA1 (1 << 30) |
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| 64 | #define DSSR_VC1FB_DSA2 (2 << 30) |
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| 65 | #define DSSR_VC1FB_INIT (3 << 30) |
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| 66 | #define DSSR_VC1FB_MASK (3 << 30) |
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| 67 | #define DSSR_VC0FB_DSA0 (0 << 28) |
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| 68 | #define DSSR_VC0FB_DSA1 (1 << 28) |
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| 69 | #define DSSR_VC0FB_DSA2 (2 << 28) |
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| 70 | #define DSSR_VC0FB_INIT (3 << 28) |
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| 71 | #define DSSR_VC0FB_MASK (3 << 28) |
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| 72 | #define DSSR_DFB(n) (1 << ((n)+15)) |
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| 73 | #define DSSR_TVR (1 << 15) |
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| 74 | #define DSSR_FRM (1 << 14) |
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| 75 | #define DSSR_VBK (1 << 11) |
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| 76 | #define DSSR_RINT (1 << 9) |
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| 77 | #define DSSR_HBK (1 << 8) |
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| 78 | #define DSSR_ADC(n) (1 << ((n)-1)) |
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| 79 | |
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| 80 | #define DSRCR 0x0000c |
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| 81 | #define DSRCR_TVCL (1 << 15) |
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| 82 | #define DSRCR_FRCL (1 << 14) |
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| 83 | #define DSRCR_VBCL (1 << 11) |
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| 84 | #define DSRCR_RICL (1 << 9) |
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| 85 | #define DSRCR_HBCL (1 << 8) |
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| 86 | #define DSRCR_ADCL(n) (1 << ((n)-1)) |
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| 87 | #define DSRCR_MASK 0x0000cbff |
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| 88 | |
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| 89 | #define DIER 0x00010 |
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| 90 | #define DIER_TVE (1 << 15) |
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| 91 | #define DIER_FRE (1 << 14) |
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| 92 | #define DIER_VBE (1 << 11) |
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| 93 | #define DIER_RIE (1 << 9) |
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| 94 | #define DIER_HBE (1 << 8) |
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| 95 | #define DIER_ADCE(n) (1 << ((n)-1)) |
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| 96 | |
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| 97 | #define CPCR 0x00014 |
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| 98 | #define CPCR_CP4CE (1 << 19) |
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| 99 | #define CPCR_CP3CE (1 << 18) |
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| 100 | #define CPCR_CP2CE (1 << 17) |
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| 101 | #define CPCR_CP1CE (1 << 16) |
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| 102 | |
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| 103 | #define DPPR 0x00018 |
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| 104 | #define DPPR_DPE(n) (1 << ((n)*4-1)) |
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| 105 | #define DPPR_DPS(n, p) (((p)-1) << DPPR_DPS_SHIFT(n)) |
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| 106 | #define DPPR_DPS_SHIFT(n) (((n)-1)*4) |
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| 107 | #define DPPR_BPP16 (DPPR_DPE(8) | DPPR_DPS(8, 1)) /* plane1 */ |
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| 108 | #define DPPR_BPP32_P1 (DPPR_DPE(7) | DPPR_DPS(7, 1)) |
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| 109 | #define DPPR_BPP32_P2 (DPPR_DPE(8) | DPPR_DPS(8, 2)) |
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| 110 | #define DPPR_BPP32 (DPPR_BPP32_P1 | DPPR_BPP32_P2) /* plane1 & 2 */ |
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| 111 | |
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| 112 | #define DEFR 0x00020 |
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| 113 | #define DEFR_CODE (0x7773 << 16) |
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| 114 | #define DEFR_EXSL (1 << 12) |
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| 115 | #define DEFR_EXVL (1 << 11) |
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| 116 | #define DEFR_EXUP (1 << 5) |
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| 117 | #define DEFR_VCUP (1 << 4) |
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| 118 | #define DEFR_DEFE (1 << 0) |
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| 119 | |
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| 120 | #define DAPCR 0x00024 |
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| 121 | #define DAPCR_CODE (0x7773 << 16) |
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| 122 | #define DAPCR_AP2E (1 << 4) |
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| 123 | #define DAPCR_AP1E (1 << 0) |
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| 124 | |
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| 125 | #define DCPCR 0x00028 |
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| 126 | #define DCPCR_CODE (0x7773 << 16) |
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| 127 | #define DCPCR_CA2B (1 << 13) |
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| 128 | #define DCPCR_CD2F (1 << 12) |
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| 129 | #define DCPCR_DC2E (1 << 8) |
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| 130 | #define DCPCR_CAB (1 << 5) |
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| 131 | #define DCPCR_CDF (1 << 4) |
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| 132 | #define DCPCR_DCE (1 << 0) |
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| 133 | |
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| 134 | #define DEFR2 0x00034 |
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| 135 | #define DEFR2_CODE (0x7775 << 16) |
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| 136 | #define DEFR2_DEFE2G (1 << 0) |
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| 137 | |
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| 138 | #define DEFR3 0x00038 |
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| 139 | #define DEFR3_CODE (0x7776 << 16) |
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| 140 | #define DEFR3_EVDA (1 << 14) |
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| 141 | #define DEFR3_EVDM_1 (1 << 12) |
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| 142 | #define DEFR3_EVDM_2 (2 << 12) |
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| 143 | #define DEFR3_EVDM_3 (3 << 12) |
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| 144 | #define DEFR3_VMSM2_EMA (1 << 6) |
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| 145 | #define DEFR3_VMSM1_ENA (1 << 4) |
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| 146 | #define DEFR3_DEFE3 (1 << 0) |
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| 147 | |
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| 148 | #define DEFR4 0x0003c |
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| 149 | #define DEFR4_CODE (0x7777 << 16) |
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| 150 | #define DEFR4_LRUO (1 << 5) |
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| 151 | #define DEFR4_SPCE (1 << 4) |
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| 152 | |
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| 153 | #define DVCSR 0x000d0 |
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| 154 | #define DVCSR_VCnFB2_DSA0(n) (0 << ((n)*2+16)) |
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| 155 | #define DVCSR_VCnFB2_DSA1(n) (1 << ((n)*2+16)) |
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| 156 | #define DVCSR_VCnFB2_DSA2(n) (2 << ((n)*2+16)) |
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| 157 | #define DVCSR_VCnFB2_INIT(n) (3 << ((n)*2+16)) |
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| 158 | #define DVCSR_VCnFB2_MASK(n) (3 << ((n)*2+16)) |
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| 159 | #define DVCSR_VCnFB_DSA0(n) (0 << ((n)*2)) |
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| 160 | #define DVCSR_VCnFB_DSA1(n) (1 << ((n)*2)) |
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| 161 | #define DVCSR_VCnFB_DSA2(n) (2 << ((n)*2)) |
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| 162 | #define DVCSR_VCnFB_INIT(n) (3 << ((n)*2)) |
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| 163 | #define DVCSR_VCnFB_MASK(n) (3 << ((n)*2)) |
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| 164 | |
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| 165 | #define DEFR5 0x000e0 |
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| 166 | #define DEFR5_CODE (0x66 << 24) |
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| 167 | #define DEFR5_YCRGB2_DIS (0 << 14) |
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| 168 | #define DEFR5_YCRGB2_PRI1 (1 << 14) |
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| 169 | #define DEFR5_YCRGB2_PRI2 (2 << 14) |
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| 170 | #define DEFR5_YCRGB2_PRI3 (3 << 14) |
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| 171 | #define DEFR5_YCRGB2_MASK (3 << 14) |
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| 172 | #define DEFR5_YCRGB1_DIS (0 << 12) |
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| 173 | #define DEFR5_YCRGB1_PRI1 (1 << 12) |
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| 174 | #define DEFR5_YCRGB1_PRI2 (2 << 12) |
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| 175 | #define DEFR5_YCRGB1_PRI3 (3 << 12) |
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| 176 | #define DEFR5_YCRGB1_MASK (3 << 12) |
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| 177 | #define DEFR5_DEFE5 (1 << 0) |
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| 178 | |
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| 179 | #define DDLTR 0x000e4 |
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| 180 | #define DDLTR_CODE (0x7766 << 16) |
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| 181 | #define DDLTR_DLAR2 (1 << 6) |
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| 182 | #define DDLTR_DLAY2 (1 << 5) |
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| 183 | #define DDLTR_DLAY1 (1 << 1) |
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| 184 | |
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| 185 | #define DEFR6 0x000e8 |
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| 186 | #define DEFR6_CODE (0x7778 << 16) |
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| 187 | #define DEFR6_ODPM12_DSMR (0 << 10) |
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| 188 | #define DEFR6_ODPM12_DISP (2 << 10) |
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| 189 | #define DEFR6_ODPM12_CDE (3 << 10) |
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| 190 | #define DEFR6_ODPM12_MASK (3 << 10) |
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| 191 | #define DEFR6_ODPM02_DSMR (0 << 8) |
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| 192 | #define DEFR6_ODPM02_DISP (2 << 8) |
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| 193 | #define DEFR6_ODPM02_CDE (3 << 8) |
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| 194 | #define DEFR6_ODPM02_MASK (3 << 8) |
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| 195 | #define DEFR6_TCNE1 (1 << 6) |
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| 196 | #define DEFR6_TCNE0 (1 << 4) |
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| 197 | #define DEFR6_MLOS1 (1 << 2) |
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| 198 | #define DEFR6_DEFAULT (DEFR6_CODE | DEFR6_TCNE1) |
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| 199 | |
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| 200 | #define DEFR7 0x000ec |
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| 201 | #define DEFR7_CODE (0x7779 << 16) |
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| 202 | #define DEFR7_CMME1 BIT(6) |
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| 203 | #define DEFR7_CMME0 BIT(4) |
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| 204 | |
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| 205 | /* ----------------------------------------------------------------------------- |
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| 206 | * R8A7790-only Control Registers |
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| 207 | */ |
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| 208 | |
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| 209 | #define DD1SSR 0x20008 |
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| 210 | #define DD1SSR_TVR (1 << 15) |
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| 211 | #define DD1SSR_FRM (1 << 14) |
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| 212 | #define DD1SSR_BUF (1 << 12) |
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| 213 | #define DD1SSR_VBK (1 << 11) |
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| 214 | #define DD1SSR_RINT (1 << 9) |
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| 215 | #define DD1SSR_HBK (1 << 8) |
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| 216 | #define DD1SSR_ADC(n) (1 << ((n)-1)) |
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| 217 | |
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| 218 | #define DD1SRCR 0x2000c |
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| 219 | #define DD1SRCR_TVR (1 << 15) |
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| 220 | #define DD1SRCR_FRM (1 << 14) |
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| 221 | #define DD1SRCR_BUF (1 << 12) |
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| 222 | #define DD1SRCR_VBK (1 << 11) |
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| 223 | #define DD1SRCR_RINT (1 << 9) |
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| 224 | #define DD1SRCR_HBK (1 << 8) |
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| 225 | #define DD1SRCR_ADC(n) (1 << ((n)-1)) |
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| 226 | |
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| 227 | #define DD1IER 0x20010 |
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| 228 | #define DD1IER_TVR (1 << 15) |
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| 229 | #define DD1IER_FRM (1 << 14) |
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| 230 | #define DD1IER_BUF (1 << 12) |
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| 231 | #define DD1IER_VBK (1 << 11) |
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| 232 | #define DD1IER_RINT (1 << 9) |
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| 233 | #define DD1IER_HBK (1 << 8) |
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| 234 | #define DD1IER_ADC(n) (1 << ((n)-1)) |
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| 235 | |
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| 236 | #define DEFR8 0x20020 |
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| 237 | #define DEFR8_CODE (0x7790 << 16) |
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| 238 | #define DEFR8_VSCS (1 << 6) |
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| 239 | #define DEFR8_DRGBS_DU(n) ((n) << 4) |
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| 240 | #define DEFR8_DRGBS_MASK (3 << 4) |
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| 241 | #define DEFR8_DEFE8 (1 << 0) |
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| 242 | |
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| 243 | #define DOFLR 0x20024 |
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| 244 | #define DOFLR_CODE (0x7790 << 16) |
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| 245 | #define DOFLR_HSYCFL1 (1 << 13) |
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| 246 | #define DOFLR_VSYCFL1 (1 << 12) |
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| 247 | #define DOFLR_ODDFL1 (1 << 11) |
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| 248 | #define DOFLR_DISPFL1 (1 << 10) |
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| 249 | #define DOFLR_CDEFL1 (1 << 9) |
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| 250 | #define DOFLR_RGBFL1 (1 << 8) |
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| 251 | #define DOFLR_HSYCFL0 (1 << 5) |
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| 252 | #define DOFLR_VSYCFL0 (1 << 4) |
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| 253 | #define DOFLR_ODDFL0 (1 << 3) |
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| 254 | #define DOFLR_DISPFL0 (1 << 2) |
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| 255 | #define DOFLR_CDEFL0 (1 << 1) |
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| 256 | #define DOFLR_RGBFL0 (1 << 0) |
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| 257 | |
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| 258 | #define DIDSR 0x20028 |
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| 259 | #define DIDSR_CODE (0x7790 << 16) |
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| 260 | #define DIDSR_LDCS_DCLKIN(n) (0 << (8 + (n) * 2)) |
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| 261 | #define DIDSR_LDCS_DSI(n) (2 << (8 + (n) * 2)) /* V3U only */ |
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| 262 | #define DIDSR_LDCS_LVDS0(n) (2 << (8 + (n) * 2)) |
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| 263 | #define DIDSR_LDCS_LVDS1(n) (3 << (8 + (n) * 2)) |
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| 264 | #define DIDSR_LDCS_MASK(n) (3 << (8 + (n) * 2)) |
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| 265 | #define DIDSR_PDCS_CLK(n, clk) (clk << ((n) * 2)) |
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| 266 | #define DIDSR_PDCS_MASK(n) (3 << ((n) * 2)) |
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| 267 | |
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| 268 | #define DEFR10 0x20038 |
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| 269 | #define DEFR10_CODE (0x7795 << 16) |
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| 270 | #define DEFR10_VSPF1_RGB (0 << 14) |
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| 271 | #define DEFR10_VSPF1_YC (1 << 14) |
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| 272 | #define DEFR10_DOCF1_RGB (0 << 12) |
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| 273 | #define DEFR10_DOCF1_YC (1 << 12) |
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| 274 | #define DEFR10_YCDF0_YCBCR444 (0 << 11) |
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| 275 | #define DEFR10_YCDF0_YCBCR422 (1 << 11) |
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| 276 | #define DEFR10_VSPF0_RGB (0 << 10) |
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| 277 | #define DEFR10_VSPF0_YC (1 << 10) |
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| 278 | #define DEFR10_DOCF0_RGB (0 << 8) |
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| 279 | #define DEFR10_DOCF0_YC (1 << 8) |
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| 280 | #define DEFR10_TSEL_H3_TCON1 (0 << 1) /* DEFR102 register only (DU2/DU3) */ |
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| 281 | #define DEFR10_DEFE10 (1 << 0) |
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| 282 | |
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| 283 | #define DPLLCR 0x20044 |
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| 284 | #define DPLLCR_CODE (0x95 << 24) |
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| 285 | #define DPLLCR_PLCS1 (1 << 23) |
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| 286 | #define DPLLCR_PLCS0 (1 << 21) |
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| 287 | #define DPLLCR_CLKE (1 << 18) |
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| 288 | #define DPLLCR_FDPLL(n) ((n) << 12) |
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| 289 | #define DPLLCR_N(n) ((n) << 5) |
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| 290 | #define DPLLCR_M(n) ((n) << 3) |
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| 291 | #define DPLLCR_STBY (1 << 2) |
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| 292 | #define DPLLCR_INCS_DOTCLKIN0 (0 << 0) |
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| 293 | #define DPLLCR_INCS_DOTCLKIN1 (1 << 1) |
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| 294 | |
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| 295 | #define DPLLC2R 0x20048 |
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| 296 | #define DPLLC2R_CODE (0x95 << 24) |
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| 297 | #define DPLLC2R_SELC (1 << 12) |
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| 298 | #define DPLLC2R_M(n) ((n) << 8) |
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| 299 | #define DPLLC2R_FDPLL(n) ((n) << 0) |
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| 300 | |
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| 301 | /* ----------------------------------------------------------------------------- |
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| 302 | * Display Timing Generation Registers |
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| 303 | */ |
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| 304 | |
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| 305 | #define HDSR 0x00040 |
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| 306 | #define HDER 0x00044 |
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| 307 | #define VDSR 0x00048 |
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| 308 | #define VDER 0x0004c |
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| 309 | #define HCR 0x00050 |
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| 310 | #define HSWR 0x00054 |
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| 311 | #define VCR 0x00058 |
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| 312 | #define VSPR 0x0005c |
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| 313 | #define EQWR 0x00060 |
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| 314 | #define SPWR 0x00064 |
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| 315 | #define CLAMPSR 0x00070 |
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| 316 | #define CLAMPWR 0x00074 |
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| 317 | #define DESR 0x00078 |
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| 318 | #define DEWR 0x0007c |
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| 319 | |
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| 320 | /* ----------------------------------------------------------------------------- |
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| 321 | * Display Attribute Registers |
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| 322 | */ |
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| 323 | |
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| 324 | #define CP1TR 0x00080 |
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| 325 | #define CP2TR 0x00084 |
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| 326 | #define CP3TR 0x00088 |
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| 327 | #define CP4TR 0x0008c |
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| 328 | |
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| 329 | #define DOOR 0x00090 |
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| 330 | #define DOOR_RGB(r, g, b) (((r) << 18) | ((g) << 10) | ((b) << 2)) |
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| 331 | #define CDER 0x00094 |
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| 332 | #define CDER_RGB(r, g, b) (((r) << 18) | ((g) << 10) | ((b) << 2)) |
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| 333 | #define BPOR 0x00098 |
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| 334 | #define BPOR_RGB(r, g, b) (((r) << 18) | ((g) << 10) | ((b) << 2)) |
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| 335 | |
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| 336 | #define RINTOFSR 0x0009c |
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| 337 | |
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| 338 | #define DSHPR 0x000c8 |
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| 339 | #define DSHPR_CODE (0x7776 << 16) |
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| 340 | #define DSHPR_PRIH (0xa << 4) |
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| 341 | #define DSHPR_PRIL_BPP16 (0x8 << 0) |
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| 342 | #define DSHPR_PRIL_BPP32 (0x9 << 0) |
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| 343 | |
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| 344 | /* ----------------------------------------------------------------------------- |
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| 345 | * Display Plane Registers |
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| 346 | */ |
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| 347 | |
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| 348 | #define PLANE_OFF 0x00100 |
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| 349 | |
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| 350 | #define PnMR 0x00100 /* plane 1 */ |
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| 351 | #define PnMR_VISL_VIN0 (0 << 26) /* use Video Input 0 */ |
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| 352 | #define PnMR_VISL_VIN1 (1 << 26) /* use Video Input 1 */ |
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| 353 | #define PnMR_VISL_VIN2 (2 << 26) /* use Video Input 2 */ |
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| 354 | #define PnMR_VISL_VIN3 (3 << 26) /* use Video Input 3 */ |
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| 355 | #define PnMR_YCDF_YUYV (1 << 20) /* YUYV format */ |
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| 356 | #define PnMR_TC_R (0 << 17) /* Tranparent color is PnTC1R */ |
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| 357 | #define PnMR_TC_CP (1 << 17) /* Tranparent color is color palette */ |
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| 358 | #define PnMR_WAE (1 << 16) /* Wrap around Enable */ |
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| 359 | #define PnMR_SPIM_TP (0 << 12) /* Transparent Color */ |
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| 360 | #define PnMR_SPIM_ALP (1 << 12) /* Alpha Blending */ |
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| 361 | #define PnMR_SPIM_EOR (2 << 12) /* EOR */ |
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| 362 | #define PnMR_SPIM_TP_OFF (1 << 14) /* No Transparent Color */ |
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| 363 | #define PnMR_CPSL_CP1 (0 << 8) /* Color Palette selected 1 */ |
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| 364 | #define PnMR_CPSL_CP2 (1 << 8) /* Color Palette selected 2 */ |
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| 365 | #define PnMR_CPSL_CP3 (2 << 8) /* Color Palette selected 3 */ |
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| 366 | #define PnMR_CPSL_CP4 (3 << 8) /* Color Palette selected 4 */ |
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| 367 | #define PnMR_DC (1 << 7) /* Display Area Change */ |
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| 368 | #define PnMR_BM_MD (0 << 4) /* Manual Display Change Mode */ |
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| 369 | #define PnMR_BM_AR (1 << 4) /* Auto Rendering Mode */ |
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| 370 | #define PnMR_BM_AD (2 << 4) /* Auto Display Change Mode */ |
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| 371 | #define PnMR_BM_VC (3 << 4) /* Video Capture Mode */ |
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| 372 | #define PnMR_DDDF_8BPP (0 << 0) /* 8bit */ |
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| 373 | #define PnMR_DDDF_16BPP (1 << 0) /* 16bit or 32bit */ |
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| 374 | #define PnMR_DDDF_ARGB (2 << 0) /* ARGB */ |
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| 375 | #define PnMR_DDDF_YC (3 << 0) /* YC */ |
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| 376 | #define PnMR_DDDF_MASK (3 << 0) |
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| 377 | |
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| 378 | #define PnMWR 0x00104 |
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| 379 | |
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| 380 | #define PnALPHAR 0x00108 |
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| 381 | #define PnALPHAR_ABIT_1 (0 << 12) |
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| 382 | #define PnALPHAR_ABIT_0 (1 << 12) |
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| 383 | #define PnALPHAR_ABIT_X (2 << 12) |
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| 384 | |
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| 385 | #define PnDSXR 0x00110 |
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| 386 | #define PnDSYR 0x00114 |
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| 387 | #define PnDPXR 0x00118 |
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| 388 | #define PnDPYR 0x0011c |
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| 389 | |
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| 390 | #define PnDSA0R 0x00120 |
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| 391 | #define PnDSA1R 0x00124 |
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| 392 | #define PnDSA2R 0x00128 |
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| 393 | #define PnDSA_MASK 0xfffffff0 |
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| 394 | |
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| 395 | #define PnSPXR 0x00130 |
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| 396 | #define PnSPYR 0x00134 |
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| 397 | #define PnWASPR 0x00138 |
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| 398 | #define PnWAMWR 0x0013c |
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| 399 | |
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| 400 | #define PnBTR 0x00140 |
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| 401 | |
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| 402 | #define PnTC1R 0x00144 |
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| 403 | #define PnTC2R 0x00148 |
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| 404 | #define PnTC3R 0x0014c |
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| 405 | #define PnTC3R_CODE (0x66 << 24) |
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| 406 | |
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| 407 | #define PnMLR 0x00150 |
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| 408 | |
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| 409 | #define PnSWAPR 0x00180 |
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| 410 | #define PnSWAPR_DIGN (1 << 4) |
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| 411 | #define PnSWAPR_SPQW (1 << 3) |
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| 412 | #define PnSWAPR_SPLW (1 << 2) |
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| 413 | #define PnSWAPR_SPWD (1 << 1) |
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| 414 | #define PnSWAPR_SPBY (1 << 0) |
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| 415 | |
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| 416 | #define PnDDCR 0x00184 |
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| 417 | #define PnDDCR_CODE (0x7775 << 16) |
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| 418 | #define PnDDCR_LRGB1 (1 << 11) |
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| 419 | #define PnDDCR_LRGB0 (1 << 10) |
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| 420 | |
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| 421 | #define PnDDCR2 0x00188 |
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| 422 | #define PnDDCR2_CODE (0x7776 << 16) |
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| 423 | #define PnDDCR2_NV21 (1 << 5) |
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| 424 | #define PnDDCR2_Y420 (1 << 4) |
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| 425 | #define PnDDCR2_DIVU (1 << 1) |
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| 426 | #define PnDDCR2_DIVY (1 << 0) |
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| 427 | |
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| 428 | #define PnDDCR4 0x00190 |
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| 429 | #define PnDDCR4_CODE (0x7766 << 16) |
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| 430 | #define PnDDCR4_VSPS (1 << 13) |
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| 431 | #define PnDDCR4_SDFS_RGB (0 << 4) |
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| 432 | #define PnDDCR4_SDFS_YC (5 << 4) |
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| 433 | #define PnDDCR4_SDFS_MASK (7 << 4) |
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| 434 | #define PnDDCR4_EDF_NONE (0 << 0) |
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| 435 | #define PnDDCR4_EDF_ARGB8888 (1 << 0) |
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| 436 | #define PnDDCR4_EDF_RGB888 (2 << 0) |
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| 437 | #define PnDDCR4_EDF_RGB666 (3 << 0) |
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| 438 | #define PnDDCR4_EDF_MASK (7 << 0) |
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| 439 | |
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| 440 | #define APnMR 0x0a100 |
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| 441 | #define APnMR_WAE (1 << 16) /* Wrap around Enable */ |
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| 442 | #define APnMR_DC (1 << 7) /* Display Area Change */ |
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| 443 | #define APnMR_BM_MD (0 << 4) /* Manual Display Change Mode */ |
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| 444 | #define APnMR_BM_AD (2 << 4) /* Auto Display Change Mode */ |
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| 445 | |
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| 446 | #define APnMWR 0x0a104 |
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| 447 | |
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| 448 | #define APnDSXR 0x0a110 |
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| 449 | #define APnDSYR 0x0a114 |
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| 450 | #define APnDPXR 0x0a118 |
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| 451 | #define APnDPYR 0x0a11c |
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| 452 | |
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| 453 | #define APnDSA0R 0x0a120 |
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| 454 | #define APnDSA1R 0x0a124 |
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| 455 | #define APnDSA2R 0x0a128 |
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| 456 | |
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| 457 | #define APnSPXR 0x0a130 |
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| 458 | #define APnSPYR 0x0a134 |
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| 459 | #define APnWASPR 0x0a138 |
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| 460 | #define APnWAMWR 0x0a13c |
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| 461 | |
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| 462 | #define APnBTR 0x0a140 |
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| 463 | |
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| 464 | #define APnMLR 0x0a150 |
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| 465 | #define APnSWAPR 0x0a180 |
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| 466 | |
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| 467 | /* ----------------------------------------------------------------------------- |
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| 468 | * Display Capture Registers |
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| 469 | */ |
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| 470 | |
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| 471 | #define DCMR 0x0c100 |
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| 472 | #define DCMWR 0x0c104 |
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| 473 | #define DCSAR 0x0c120 |
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| 474 | #define DCMLR 0x0c150 |
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| 475 | |
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| 476 | /* ----------------------------------------------------------------------------- |
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| 477 | * Color Palette Registers |
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| 478 | */ |
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| 479 | |
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| 480 | #define CP1_000R 0x01000 |
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| 481 | #define CP1_255R 0x013fc |
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| 482 | #define CP2_000R 0x02000 |
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| 483 | #define CP2_255R 0x023fc |
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| 484 | #define CP3_000R 0x03000 |
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| 485 | #define CP3_255R 0x033fc |
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| 486 | #define CP4_000R 0x04000 |
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| 487 | #define CP4_255R 0x043fc |
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| 488 | |
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| 489 | /* ----------------------------------------------------------------------------- |
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| 490 | * External Synchronization Control Registers |
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| 491 | */ |
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| 492 | |
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| 493 | #define ESCR02 0x10000 |
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| 494 | #define ESCR13 0x01000 |
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| 495 | #define ESCR_DCLKOINV (1 << 25) |
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| 496 | #define ESCR_DCLKSEL_DCLKIN (0 << 20) |
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| 497 | #define ESCR_DCLKSEL_CLKS (1 << 20) |
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| 498 | #define ESCR_DCLKSEL_MASK (1 << 20) |
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| 499 | #define ESCR_DCLKDIS (1 << 16) |
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| 500 | #define ESCR_SYNCSEL_OFF (0 << 8) |
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| 501 | #define ESCR_SYNCSEL_EXVSYNC (2 << 8) |
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| 502 | #define ESCR_SYNCSEL_EXHSYNC (3 << 8) |
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| 503 | #define ESCR_FRQSEL_MASK (0x3f << 0) |
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| 504 | |
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| 505 | #define OTAR02 0x10004 |
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| 506 | #define OTAR13 0x01004 |
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| 507 | |
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| 508 | /* ----------------------------------------------------------------------------- |
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| 509 | * Dual Display Output Control Registers |
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| 510 | */ |
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| 511 | |
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| 512 | #define DORCR 0x11000 |
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| 513 | #define DORCR_PG1T (1 << 30) |
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| 514 | #define DORCR_DK1S (1 << 28) |
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| 515 | #define DORCR_PG1D_DS0 (0 << 24) |
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| 516 | #define DORCR_PG1D_DS1 (1 << 24) |
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| 517 | #define DORCR_PG1D_FIX0 (2 << 24) |
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| 518 | #define DORCR_PG1D_DOOR (3 << 24) |
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| 519 | #define DORCR_PG1D_MASK (3 << 24) |
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| 520 | #define DORCR_DR0D (1 << 21) |
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| 521 | #define DORCR_PG0D_DS0 (0 << 16) |
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| 522 | #define DORCR_PG0D_DS1 (1 << 16) |
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| 523 | #define DORCR_PG0D_FIX0 (2 << 16) |
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| 524 | #define DORCR_PG0D_DOOR (3 << 16) |
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| 525 | #define DORCR_PG0D_MASK (3 << 16) |
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| 526 | #define DORCR_RGPV (1 << 4) |
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| 527 | #define DORCR_DPRS (1 << 0) |
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| 528 | |
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| 529 | #define DPTSR 0x11004 |
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| 530 | #define DPTSR_PnDK(n) (1 << ((n) + 16)) |
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| 531 | #define DPTSR_PnTS(n) (1 << (n)) |
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| 532 | |
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| 533 | #define DAPTSR 0x11008 |
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| 534 | #define DAPTSR_APnDK(n) (1 << ((n) + 16)) |
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| 535 | #define DAPTSR_APnTS(n) (1 << (n)) |
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| 536 | |
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| 537 | #define DS1PR 0x11020 |
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| 538 | #define DS2PR 0x11024 |
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| 539 | |
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| 540 | /* ----------------------------------------------------------------------------- |
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| 541 | * YC-RGB Conversion Coefficient Registers |
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| 542 | */ |
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| 543 | |
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| 544 | #define YNCR 0x11080 |
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| 545 | #define YNOR 0x11084 |
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| 546 | #define CRNOR 0x11088 |
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| 547 | #define CBNOR 0x1108c |
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| 548 | #define RCRCR 0x11090 |
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| 549 | #define GCRCR 0x11094 |
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| 550 | #define GCBCR 0x11098 |
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| 551 | #define BCBCR 0x1109c |
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| 552 | |
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| 553 | #endif /* __RCAR_DU_REGS_H__ */ |
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| 554 | |
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