1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved. |
4 | */ |
5 | |
6 | #ifndef TEGRA_PLANE_H |
7 | #define TEGRA_PLANE_H 1 |
8 | |
9 | #include <drm/drm_plane.h> |
10 | |
11 | struct icc_path; |
12 | struct tegra_bo; |
13 | struct tegra_dc; |
14 | |
15 | struct tegra_plane { |
16 | struct drm_plane base; |
17 | struct tegra_dc *dc; |
18 | unsigned int offset; |
19 | unsigned int index; |
20 | |
21 | struct icc_path *icc_mem; |
22 | struct icc_path *icc_mem_vfilter; |
23 | }; |
24 | |
25 | struct tegra_cursor { |
26 | struct tegra_plane base; |
27 | |
28 | struct tegra_bo *bo; |
29 | unsigned int width; |
30 | unsigned int height; |
31 | }; |
32 | |
33 | static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane) |
34 | { |
35 | return container_of(plane, struct tegra_plane, base); |
36 | } |
37 | |
38 | struct tegra_plane_legacy_blending_state { |
39 | bool alpha; |
40 | bool top; |
41 | }; |
42 | |
43 | struct tegra_plane_state { |
44 | struct drm_plane_state base; |
45 | |
46 | struct host1x_bo_mapping *map[3]; |
47 | dma_addr_t iova[3]; |
48 | |
49 | struct tegra_bo_tiling tiling; |
50 | u32 format; |
51 | u32 swap; |
52 | |
53 | bool reflect_x; |
54 | bool reflect_y; |
55 | |
56 | /* used for legacy blending support only */ |
57 | struct tegra_plane_legacy_blending_state blending[2]; |
58 | bool opaque; |
59 | |
60 | /* bandwidths are in ICC units, i.e. kbytes/sec */ |
61 | u32 total_peak_memory_bandwidth; |
62 | u32 peak_memory_bandwidth; |
63 | u32 avg_memory_bandwidth; |
64 | }; |
65 | |
66 | static inline struct tegra_plane_state * |
67 | to_tegra_plane_state(struct drm_plane_state *state) |
68 | { |
69 | if (state) |
70 | return container_of(state, struct tegra_plane_state, base); |
71 | |
72 | return NULL; |
73 | } |
74 | |
75 | static inline const struct tegra_plane_state * |
76 | to_const_tegra_plane_state(const struct drm_plane_state *state) |
77 | { |
78 | return to_tegra_plane_state(state: (struct drm_plane_state *)state); |
79 | } |
80 | |
81 | extern const struct drm_plane_funcs tegra_plane_funcs; |
82 | |
83 | int tegra_plane_prepare_fb(struct drm_plane *plane, |
84 | struct drm_plane_state *state); |
85 | void tegra_plane_cleanup_fb(struct drm_plane *plane, |
86 | struct drm_plane_state *state); |
87 | |
88 | int tegra_plane_state_add(struct tegra_plane *plane, |
89 | struct drm_plane_state *state); |
90 | |
91 | int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap); |
92 | bool tegra_plane_format_is_indexed(unsigned int format); |
93 | bool tegra_plane_format_is_yuv(unsigned int format, unsigned int *planes, unsigned int *bpc); |
94 | int tegra_plane_setup_legacy_state(struct tegra_plane *tegra, |
95 | struct tegra_plane_state *state); |
96 | int tegra_plane_interconnect_init(struct tegra_plane *plane); |
97 | |
98 | #endif /* TEGRA_PLANE_H */ |
99 | |