| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | |
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| 3 | #ifndef UDL_PROTO_H |
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| 4 | #define UDL_PROTO_H |
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| 5 | |
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| 6 | #include <linux/bits.h> |
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| 7 | |
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| 8 | #define UDL_MSG_BULK 0xaf |
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| 9 | |
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| 10 | /* Register access */ |
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| 11 | #define UDL_CMD_WRITEREG 0x20 /* See register constants below */ |
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| 12 | |
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| 13 | /* Framebuffer access */ |
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| 14 | #define UDL_CMD_WRITERAW8 0x60 /* 8 bit raw write command. */ |
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| 15 | #define UDL_CMD_WRITERL8 0x61 /* 8 bit run length command. */ |
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| 16 | #define UDL_CMD_WRITECOPY8 0x62 /* 8 bit copy command. */ |
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| 17 | #define UDL_CMD_WRITERLX8 0x63 /* 8 bit extended run length command. */ |
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| 18 | #define UDL_CMD_WRITERAW16 0x68 /* 16 bit raw write command. */ |
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| 19 | #define UDL_CMD_WRITERL16 0x69 /* 16 bit run length command. */ |
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| 20 | #define UDL_CMD_WRITECOPY16 0x6a /* 16 bit copy command. */ |
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| 21 | #define UDL_CMD_WRITERLX16 0x6b /* 16 bit extended run length command. */ |
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| 22 | |
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| 23 | /* Color depth */ |
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| 24 | #define UDL_REG_COLORDEPTH 0x00 |
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| 25 | #define UDL_COLORDEPTH_16BPP 0 |
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| 26 | #define UDL_COLORDEPTH_24BPP 1 |
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| 27 | |
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| 28 | /* Display-mode settings */ |
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| 29 | #define UDL_REG_XDISPLAYSTART 0x01 |
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| 30 | #define UDL_REG_XDISPLAYEND 0x03 |
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| 31 | #define UDL_REG_YDISPLAYSTART 0x05 |
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| 32 | #define UDL_REG_YDISPLAYEND 0x07 |
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| 33 | #define UDL_REG_XENDCOUNT 0x09 |
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| 34 | #define UDL_REG_HSYNCSTART 0x0b |
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| 35 | #define UDL_REG_HSYNCEND 0x0d |
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| 36 | #define UDL_REG_HPIXELS 0x0f |
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| 37 | #define UDL_REG_YENDCOUNT 0x11 |
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| 38 | #define UDL_REG_VSYNCSTART 0x13 |
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| 39 | #define UDL_REG_VSYNCEND 0x15 |
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| 40 | #define UDL_REG_VPIXELS 0x17 |
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| 41 | #define UDL_REG_PIXELCLOCK5KHZ 0x1b |
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| 42 | |
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| 43 | /* On/Off for driving the DisplayLink framebuffer to the display */ |
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| 44 | #define UDL_REG_BLANKMODE 0x1f |
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| 45 | #define UDL_BLANKMODE_ON 0x00 /* hsync and vsync on, visible */ |
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| 46 | #define UDL_BLANKMODE_BLANKED 0x01 /* hsync and vsync on, blanked */ |
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| 47 | #define UDL_BLANKMODE_VSYNC_OFF 0x03 /* vsync off, blanked */ |
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| 48 | #define UDL_BLANKMODE_HSYNC_OFF 0x05 /* hsync off, blanked */ |
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| 49 | #define UDL_BLANKMODE_POWERDOWN 0x07 /* powered off; requires modeset */ |
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| 50 | |
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| 51 | /* Framebuffer address */ |
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| 52 | #define UDL_REG_BASE16BPP_ADDR2 0x20 |
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| 53 | #define UDL_REG_BASE16BPP_ADDR1 0x21 |
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| 54 | #define UDL_REG_BASE16BPP_ADDR0 0x22 |
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| 55 | #define UDL_REG_BASE8BPP_ADDR2 0x26 |
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| 56 | #define UDL_REG_BASE8BPP_ADDR1 0x27 |
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| 57 | #define UDL_REG_BASE8BPP_ADDR0 0x28 |
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| 58 | |
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| 59 | #define UDL_BASE_ADDR0_MASK GENMASK(7, 0) |
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| 60 | #define UDL_BASE_ADDR1_MASK GENMASK(15, 8) |
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| 61 | #define UDL_BASE_ADDR2_MASK GENMASK(23, 16) |
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| 62 | |
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| 63 | /* Lock/unlock video registers */ |
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| 64 | #define UDL_REG_VIDREG 0xff |
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| 65 | #define UDL_VIDREG_LOCK 0x00 |
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| 66 | #define UDL_VIDREG_UNLOCK 0xff |
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| 67 | |
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| 68 | #endif |
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| 69 | |
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