1// SPDX-License-Identifier: GPL-2.0+
2/* Copyright (C) 2015-2018 Broadcom */
3
4#include <linux/delay.h>
5#include <linux/mutex.h>
6#include <linux/spinlock_types.h>
7#include <linux/workqueue.h>
8
9#include <drm/drm_encoder.h>
10#include <drm/drm_gem.h>
11#include <drm/drm_gem_shmem_helper.h>
12#include <drm/gpu_scheduler.h>
13
14#include "uapi/drm/v3d_drm.h"
15
16struct clk;
17struct platform_device;
18struct reset_control;
19
20#define GMP_GRANULARITY (128 * 1024)
21
22#define V3D_MMU_PAGE_SHIFT 12
23
24#define V3D_MAX_QUEUES (V3D_CPU + 1)
25
26static inline char *v3d_queue_to_string(enum v3d_queue queue)
27{
28 switch (queue) {
29 case V3D_BIN: return "bin";
30 case V3D_RENDER: return "render";
31 case V3D_TFU: return "tfu";
32 case V3D_CSD: return "csd";
33 case V3D_CACHE_CLEAN: return "cache_clean";
34 case V3D_CPU: return "cpu";
35 }
36 return "UNKNOWN";
37}
38
39struct v3d_queue_state {
40 struct drm_gpu_scheduler sched;
41
42 u64 fence_context;
43 u64 emit_seqno;
44
45 u64 start_ns;
46 u64 enabled_ns;
47 u64 jobs_sent;
48};
49
50/* Performance monitor object. The perform lifetime is controlled by userspace
51 * using perfmon related ioctls. A perfmon can be attached to a submit_cl
52 * request, and when this is the case, HW perf counters will be activated just
53 * before the submit_cl is submitted to the GPU and disabled when the job is
54 * done. This way, only events related to a specific job will be counted.
55 */
56struct v3d_perfmon {
57 /* Tracks the number of users of the perfmon, when this counter reaches
58 * zero the perfmon is destroyed.
59 */
60 refcount_t refcnt;
61
62 /* Protects perfmon stop, as it can be invoked from multiple places. */
63 struct mutex lock;
64
65 /* Number of counters activated in this perfmon instance
66 * (should be less than DRM_V3D_MAX_PERF_COUNTERS).
67 */
68 u8 ncounters;
69
70 /* Events counted by the HW perf counters. */
71 u8 counters[DRM_V3D_MAX_PERF_COUNTERS];
72
73 /* Storage for counter values. Counters are incremented by the
74 * HW perf counter values every time the perfmon is attached
75 * to a GPU job. This way, perfmon users don't have to
76 * retrieve the results after each job if they want to track
77 * events covering several submissions. Note that counter
78 * values can't be reset, but you can fake a reset by
79 * destroying the perfmon and creating a new one.
80 */
81 u64 values[] __counted_by(ncounters);
82};
83
84struct v3d_dev {
85 struct drm_device drm;
86
87 /* Short representation (e.g. 33, 41) of the V3D tech version
88 * and revision.
89 */
90 int ver;
91 bool single_irq_line;
92
93 void __iomem *hub_regs;
94 void __iomem *core_regs[3];
95 void __iomem *bridge_regs;
96 void __iomem *gca_regs;
97 struct clk *clk;
98 struct reset_control *reset;
99
100 /* Virtual and DMA addresses of the single shared page table. */
101 volatile u32 *pt;
102 dma_addr_t pt_paddr;
103
104 /* Virtual and DMA addresses of the MMU's scratch page. When
105 * a read or write is invalid in the MMU, it will be
106 * redirected here.
107 */
108 void *mmu_scratch;
109 dma_addr_t mmu_scratch_paddr;
110 /* virtual address bits from V3D to the MMU. */
111 int va_width;
112
113 /* Number of V3D cores. */
114 u32 cores;
115
116 /* Allocator managing the address space. All units are in
117 * number of pages.
118 */
119 struct drm_mm mm;
120 spinlock_t mm_lock;
121
122 struct work_struct overflow_mem_work;
123
124 struct v3d_bin_job *bin_job;
125 struct v3d_render_job *render_job;
126 struct v3d_tfu_job *tfu_job;
127 struct v3d_csd_job *csd_job;
128 struct v3d_cpu_job *cpu_job;
129
130 struct v3d_queue_state queue[V3D_MAX_QUEUES];
131
132 /* Spinlock used to synchronize the overflow memory
133 * management against bin job submission.
134 */
135 spinlock_t job_lock;
136
137 /* Used to track the active perfmon if any. */
138 struct v3d_perfmon *active_perfmon;
139
140 /* Protects bo_stats */
141 struct mutex bo_lock;
142
143 /* Lock taken when resetting the GPU, to keep multiple
144 * processes from trying to park the scheduler threads and
145 * reset at once.
146 */
147 struct mutex reset_lock;
148
149 /* Lock taken when creating and pushing the GPU scheduler
150 * jobs, to keep the sched-fence seqnos in order.
151 */
152 struct mutex sched_lock;
153
154 /* Lock taken during a cache clean and when initiating an L2
155 * flush, to keep L2 flushes from interfering with the
156 * synchronous L2 cleans.
157 */
158 struct mutex cache_clean_lock;
159
160 struct {
161 u32 num_allocated;
162 u32 pages_allocated;
163 } bo_stats;
164};
165
166static inline struct v3d_dev *
167to_v3d_dev(struct drm_device *dev)
168{
169 return container_of(dev, struct v3d_dev, drm);
170}
171
172static inline bool
173v3d_has_csd(struct v3d_dev *v3d)
174{
175 return v3d->ver >= 41;
176}
177
178#define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev)
179
180/* The per-fd struct, which tracks the MMU mappings. */
181struct v3d_file_priv {
182 struct v3d_dev *v3d;
183
184 struct {
185 struct idr idr;
186 struct mutex lock;
187 } perfmon;
188
189 struct drm_sched_entity sched_entity[V3D_MAX_QUEUES];
190
191 u64 start_ns[V3D_MAX_QUEUES];
192
193 u64 enabled_ns[V3D_MAX_QUEUES];
194
195 u64 jobs_sent[V3D_MAX_QUEUES];
196};
197
198struct v3d_bo {
199 struct drm_gem_shmem_object base;
200
201 struct drm_mm_node node;
202
203 /* List entry for the BO's position in
204 * v3d_render_job->unref_list
205 */
206 struct list_head unref_head;
207
208 void *vaddr;
209};
210
211static inline struct v3d_bo *
212to_v3d_bo(struct drm_gem_object *bo)
213{
214 return (struct v3d_bo *)bo;
215}
216
217struct v3d_fence {
218 struct dma_fence base;
219 struct drm_device *dev;
220 /* v3d seqno for signaled() test */
221 u64 seqno;
222 enum v3d_queue queue;
223};
224
225static inline struct v3d_fence *
226to_v3d_fence(struct dma_fence *fence)
227{
228 return (struct v3d_fence *)fence;
229}
230
231#define V3D_READ(offset) readl(v3d->hub_regs + offset)
232#define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset)
233
234#define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset)
235#define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset)
236
237#define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset)
238#define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset)
239
240#define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset)
241#define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset)
242
243struct v3d_job {
244 struct drm_sched_job base;
245
246 struct kref refcount;
247
248 struct v3d_dev *v3d;
249
250 /* This is the array of BOs that were looked up at the start
251 * of submission.
252 */
253 struct drm_gem_object **bo;
254 u32 bo_count;
255
256 /* v3d fence to be signaled by IRQ handler when the job is complete. */
257 struct dma_fence *irq_fence;
258
259 /* scheduler fence for when the job is considered complete and
260 * the BO reservations can be released.
261 */
262 struct dma_fence *done_fence;
263
264 /* Pointer to a performance monitor object if the user requested it,
265 * NULL otherwise.
266 */
267 struct v3d_perfmon *perfmon;
268
269 /* File descriptor of the process that submitted the job that could be used
270 * for collecting stats by process of GPU usage.
271 */
272 struct drm_file *file;
273
274 /* Callback for the freeing of the job on refcount going to 0. */
275 void (*free)(struct kref *ref);
276};
277
278struct v3d_bin_job {
279 struct v3d_job base;
280
281 /* GPU virtual addresses of the start/end of the CL job. */
282 u32 start, end;
283
284 u32 timedout_ctca, timedout_ctra;
285
286 /* Corresponding render job, for attaching our overflow memory. */
287 struct v3d_render_job *render;
288
289 /* Submitted tile memory allocation start/size, tile state. */
290 u32 qma, qms, qts;
291};
292
293struct v3d_render_job {
294 struct v3d_job base;
295
296 /* GPU virtual addresses of the start/end of the CL job. */
297 u32 start, end;
298
299 u32 timedout_ctca, timedout_ctra;
300
301 /* List of overflow BOs used in the job that need to be
302 * released once the job is complete.
303 */
304 struct list_head unref_list;
305};
306
307struct v3d_tfu_job {
308 struct v3d_job base;
309
310 struct drm_v3d_submit_tfu args;
311};
312
313struct v3d_csd_job {
314 struct v3d_job base;
315
316 u32 timedout_batches;
317
318 struct drm_v3d_submit_csd args;
319};
320
321enum v3d_cpu_job_type {
322 V3D_CPU_JOB_TYPE_INDIRECT_CSD = 1,
323 V3D_CPU_JOB_TYPE_TIMESTAMP_QUERY,
324 V3D_CPU_JOB_TYPE_RESET_TIMESTAMP_QUERY,
325 V3D_CPU_JOB_TYPE_COPY_TIMESTAMP_QUERY,
326 V3D_CPU_JOB_TYPE_RESET_PERFORMANCE_QUERY,
327 V3D_CPU_JOB_TYPE_COPY_PERFORMANCE_QUERY,
328};
329
330struct v3d_timestamp_query {
331 /* Offset of this query in the timestamp BO for its value. */
332 u32 offset;
333
334 /* Syncobj that indicates the timestamp availability */
335 struct drm_syncobj *syncobj;
336};
337
338/* Number of perfmons required to handle all supported performance counters */
339#define V3D_MAX_PERFMONS DIV_ROUND_UP(V3D_PERFCNT_NUM, \
340 DRM_V3D_MAX_PERF_COUNTERS)
341
342struct v3d_performance_query {
343 /* Performance monitor IDs for this query */
344 u32 kperfmon_ids[V3D_MAX_PERFMONS];
345
346 /* Syncobj that indicates the query availability */
347 struct drm_syncobj *syncobj;
348};
349
350struct v3d_indirect_csd_info {
351 /* Indirect CSD */
352 struct v3d_csd_job *job;
353
354 /* Clean cache job associated to the Indirect CSD job */
355 struct v3d_job *clean_job;
356
357 /* Offset within the BO where the workgroup counts are stored */
358 u32 offset;
359
360 /* Workgroups size */
361 u32 wg_size;
362
363 /* Indices of the uniforms with the workgroup dispatch counts
364 * in the uniform stream.
365 */
366 u32 wg_uniform_offsets[3];
367
368 /* Indirect BO */
369 struct drm_gem_object *indirect;
370
371 /* Context of the Indirect CSD job */
372 struct ww_acquire_ctx acquire_ctx;
373};
374
375struct v3d_timestamp_query_info {
376 struct v3d_timestamp_query *queries;
377
378 u32 count;
379};
380
381struct v3d_performance_query_info {
382 struct v3d_performance_query *queries;
383
384 /* Number of performance queries */
385 u32 count;
386
387 /* Number of performance monitors related to that query pool */
388 u32 nperfmons;
389
390 /* Number of performance counters related to that query pool */
391 u32 ncounters;
392};
393
394struct v3d_copy_query_results_info {
395 /* Define if should write to buffer using 64 or 32 bits */
396 bool do_64bit;
397
398 /* Define if it can write to buffer even if the query is not available */
399 bool do_partial;
400
401 /* Define if it should write availability bit to buffer */
402 bool availability_bit;
403
404 /* Offset of the copy buffer in the BO */
405 u32 offset;
406
407 /* Stride of the copy buffer in the BO */
408 u32 stride;
409};
410
411struct v3d_cpu_job {
412 struct v3d_job base;
413
414 enum v3d_cpu_job_type job_type;
415
416 struct v3d_indirect_csd_info indirect_csd;
417
418 struct v3d_timestamp_query_info timestamp_query;
419
420 struct v3d_copy_query_results_info copy;
421
422 struct v3d_performance_query_info performance_query;
423};
424
425typedef void (*v3d_cpu_job_fn)(struct v3d_cpu_job *);
426
427struct v3d_submit_outsync {
428 struct drm_syncobj *syncobj;
429};
430
431struct v3d_submit_ext {
432 u32 flags;
433 u32 wait_stage;
434
435 u32 in_sync_count;
436 u64 in_syncs;
437
438 u32 out_sync_count;
439 struct v3d_submit_outsync *out_syncs;
440};
441
442/**
443 * __wait_for - magic wait macro
444 *
445 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
446 * important that we check the condition again after having timed out, since the
447 * timeout could be due to preemption or similar and we've never had a chance to
448 * check the condition before the timeout.
449 */
450#define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
451 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
452 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
453 int ret__; \
454 might_sleep(); \
455 for (;;) { \
456 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
457 OP; \
458 /* Guarantee COND check prior to timeout */ \
459 barrier(); \
460 if (COND) { \
461 ret__ = 0; \
462 break; \
463 } \
464 if (expired__) { \
465 ret__ = -ETIMEDOUT; \
466 break; \
467 } \
468 usleep_range(wait__, wait__ * 2); \
469 if (wait__ < (Wmax)) \
470 wait__ <<= 1; \
471 } \
472 ret__; \
473})
474
475#define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
476 (Wmax))
477#define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
478
479static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
480{
481 /* nsecs_to_jiffies64() does not guard against overflow */
482 if ((NSEC_PER_SEC % HZ) != 0 &&
483 div_u64(dividend: n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
484 return MAX_JIFFY_OFFSET;
485
486 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
487}
488
489/* v3d_bo.c */
490struct drm_gem_object *v3d_create_object(struct drm_device *dev, size_t size);
491void v3d_free_object(struct drm_gem_object *gem_obj);
492struct v3d_bo *v3d_bo_create(struct drm_device *dev, struct drm_file *file_priv,
493 size_t size);
494void v3d_get_bo_vaddr(struct v3d_bo *bo);
495void v3d_put_bo_vaddr(struct v3d_bo *bo);
496int v3d_create_bo_ioctl(struct drm_device *dev, void *data,
497 struct drm_file *file_priv);
498int v3d_mmap_bo_ioctl(struct drm_device *dev, void *data,
499 struct drm_file *file_priv);
500int v3d_get_bo_offset_ioctl(struct drm_device *dev, void *data,
501 struct drm_file *file_priv);
502int v3d_wait_bo_ioctl(struct drm_device *dev, void *data,
503 struct drm_file *file_priv);
504struct drm_gem_object *v3d_prime_import_sg_table(struct drm_device *dev,
505 struct dma_buf_attachment *attach,
506 struct sg_table *sgt);
507
508/* v3d_debugfs.c */
509void v3d_debugfs_init(struct drm_minor *minor);
510
511/* v3d_fence.c */
512extern const struct dma_fence_ops v3d_fence_ops;
513struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue);
514
515/* v3d_gem.c */
516int v3d_gem_init(struct drm_device *dev);
517void v3d_gem_destroy(struct drm_device *dev);
518void v3d_reset(struct v3d_dev *v3d);
519void v3d_invalidate_caches(struct v3d_dev *v3d);
520void v3d_clean_caches(struct v3d_dev *v3d);
521
522/* v3d_submit.c */
523void v3d_job_cleanup(struct v3d_job *job);
524void v3d_job_put(struct v3d_job *job);
525int v3d_submit_cl_ioctl(struct drm_device *dev, void *data,
526 struct drm_file *file_priv);
527int v3d_submit_tfu_ioctl(struct drm_device *dev, void *data,
528 struct drm_file *file_priv);
529int v3d_submit_csd_ioctl(struct drm_device *dev, void *data,
530 struct drm_file *file_priv);
531int v3d_submit_cpu_ioctl(struct drm_device *dev, void *data,
532 struct drm_file *file_priv);
533
534/* v3d_irq.c */
535int v3d_irq_init(struct v3d_dev *v3d);
536void v3d_irq_enable(struct v3d_dev *v3d);
537void v3d_irq_disable(struct v3d_dev *v3d);
538void v3d_irq_reset(struct v3d_dev *v3d);
539
540/* v3d_mmu.c */
541int v3d_mmu_set_page_table(struct v3d_dev *v3d);
542void v3d_mmu_insert_ptes(struct v3d_bo *bo);
543void v3d_mmu_remove_ptes(struct v3d_bo *bo);
544
545/* v3d_sched.c */
546int v3d_sched_init(struct v3d_dev *v3d);
547void v3d_sched_fini(struct v3d_dev *v3d);
548
549/* v3d_perfmon.c */
550void v3d_perfmon_get(struct v3d_perfmon *perfmon);
551void v3d_perfmon_put(struct v3d_perfmon *perfmon);
552void v3d_perfmon_start(struct v3d_dev *v3d, struct v3d_perfmon *perfmon);
553void v3d_perfmon_stop(struct v3d_dev *v3d, struct v3d_perfmon *perfmon,
554 bool capture);
555struct v3d_perfmon *v3d_perfmon_find(struct v3d_file_priv *v3d_priv, int id);
556void v3d_perfmon_open_file(struct v3d_file_priv *v3d_priv);
557void v3d_perfmon_close_file(struct v3d_file_priv *v3d_priv);
558int v3d_perfmon_create_ioctl(struct drm_device *dev, void *data,
559 struct drm_file *file_priv);
560int v3d_perfmon_destroy_ioctl(struct drm_device *dev, void *data,
561 struct drm_file *file_priv);
562int v3d_perfmon_get_values_ioctl(struct drm_device *dev, void *data,
563 struct drm_file *file_priv);
564
565/* v3d_sysfs.c */
566int v3d_sysfs_init(struct device *dev);
567void v3d_sysfs_destroy(struct device *dev);
568

source code of linux/drivers/gpu/drm/v3d/v3d_drv.h