| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef _CORESIGHT_CORESIGHT_TPDA_H |
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| 7 | #define _CORESIGHT_CORESIGHT_TPDA_H |
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| 8 | |
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| 9 | #define TPDA_CR (0x000) |
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| 10 | #define TPDA_Pn_CR(n) (0x004 + (n * 4)) |
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| 11 | /* Aggregator port enable bit */ |
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| 12 | #define TPDA_Pn_CR_ENA BIT(0) |
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| 13 | /* Aggregator port CMB data set element size bit */ |
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| 14 | #define TPDA_Pn_CR_CMBSIZE GENMASK(7, 6) |
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| 15 | /* Aggregator port DSB data set element size bit */ |
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| 16 | #define TPDA_Pn_CR_DSBSIZE BIT(8) |
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| 17 | |
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| 18 | #define TPDA_MAX_INPORTS 32 |
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| 19 | |
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| 20 | /* Bits 6 ~ 12 is for atid value */ |
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| 21 | #define TPDA_CR_ATID GENMASK(12, 6) |
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| 22 | |
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| 23 | /** |
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| 24 | * struct tpda_drvdata - specifics associated to an TPDA component |
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| 25 | * @base: memory mapped base address for this component. |
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| 26 | * @dev: The device entity associated to this component. |
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| 27 | * @csdev: component vitals needed by the framework. |
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| 28 | * @spinlock: lock for the drvdata value. |
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| 29 | * @enable: enable status of the component. |
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| 30 | * @dsb_esize Record the DSB element size. |
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| 31 | * @cmb_esize Record the CMB element size. |
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| 32 | */ |
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| 33 | struct tpda_drvdata { |
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| 34 | void __iomem *base; |
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| 35 | struct device *dev; |
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| 36 | struct coresight_device *csdev; |
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| 37 | spinlock_t spinlock; |
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| 38 | u8 atid; |
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| 39 | u32 dsb_esize; |
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| 40 | u32 cmb_esize; |
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| 41 | }; |
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| 42 | |
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| 43 | #endif /* _CORESIGHT_CORESIGHT_TPDA_H */ |
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| 44 | |
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