1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * Driver for the ADC present in the Atmel AT91 evaluation boards. |
4 | * |
5 | * Copyright 2011 Free Electrons |
6 | */ |
7 | |
8 | #include <linux/bitmap.h> |
9 | #include <linux/bitops.h> |
10 | #include <linux/clk.h> |
11 | #include <linux/err.h> |
12 | #include <linux/io.h> |
13 | #include <linux/input.h> |
14 | #include <linux/interrupt.h> |
15 | #include <linux/jiffies.h> |
16 | #include <linux/kernel.h> |
17 | #include <linux/module.h> |
18 | #include <linux/of.h> |
19 | #include <linux/platform_device.h> |
20 | #include <linux/sched.h> |
21 | #include <linux/slab.h> |
22 | #include <linux/wait.h> |
23 | |
24 | #include <linux/iio/iio.h> |
25 | #include <linux/iio/buffer.h> |
26 | #include <linux/iio/trigger.h> |
27 | #include <linux/iio/trigger_consumer.h> |
28 | #include <linux/iio/triggered_buffer.h> |
29 | #include <linux/pinctrl/consumer.h> |
30 | |
31 | /* Registers */ |
32 | #define AT91_ADC_CR 0x00 /* Control Register */ |
33 | #define AT91_ADC_SWRST (1 << 0) /* Software Reset */ |
34 | #define AT91_ADC_START (1 << 1) /* Start Conversion */ |
35 | |
36 | #define AT91_ADC_MR 0x04 /* Mode Register */ |
37 | #define AT91_ADC_TSAMOD (3 << 0) /* ADC mode */ |
38 | #define AT91_ADC_TSAMOD_ADC_ONLY_MODE (0 << 0) /* ADC Mode */ |
39 | #define AT91_ADC_TSAMOD_TS_ONLY_MODE (1 << 0) /* Touch Screen Only Mode */ |
40 | #define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */ |
41 | #define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */ |
42 | #define AT91_ADC_TRGSEL_TC0 (0 << 1) |
43 | #define AT91_ADC_TRGSEL_TC1 (1 << 1) |
44 | #define AT91_ADC_TRGSEL_TC2 (2 << 1) |
45 | #define AT91_ADC_TRGSEL_EXTERNAL (6 << 1) |
46 | #define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */ |
47 | #define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */ |
48 | #define AT91_ADC_PENDET (1 << 6) /* Pen contact detection enable */ |
49 | #define AT91_ADC_PRESCAL_9260 (0x3f << 8) /* Prescalar Rate Selection */ |
50 | #define AT91_ADC_PRESCAL_9G45 (0xff << 8) |
51 | #define AT91_ADC_PRESCAL_(x) ((x) << 8) |
52 | #define AT91_ADC_STARTUP_9260 (0x1f << 16) /* Startup Up Time */ |
53 | #define AT91_ADC_STARTUP_9G45 (0x7f << 16) |
54 | #define AT91_ADC_STARTUP_9X5 (0xf << 16) |
55 | #define AT91_ADC_STARTUP_(x) ((x) << 16) |
56 | #define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */ |
57 | #define AT91_ADC_SHTIM_(x) ((x) << 24) |
58 | #define AT91_ADC_PENDBC (0x0f << 28) /* Pen Debounce time */ |
59 | #define AT91_ADC_PENDBC_(x) ((x) << 28) |
60 | |
61 | #define AT91_ADC_TSR 0x0C |
62 | #define AT91_ADC_TSR_SHTIM (0xf << 24) /* Sample & Hold Time */ |
63 | #define AT91_ADC_TSR_SHTIM_(x) ((x) << 24) |
64 | |
65 | #define AT91_ADC_CHER 0x10 /* Channel Enable Register */ |
66 | #define AT91_ADC_CHDR 0x14 /* Channel Disable Register */ |
67 | #define AT91_ADC_CHSR 0x18 /* Channel Status Register */ |
68 | #define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */ |
69 | |
70 | #define AT91_ADC_SR 0x1C /* Status Register */ |
71 | #define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */ |
72 | #define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */ |
73 | #define AT91_ADC_DRDY (1 << 16) /* Data Ready */ |
74 | #define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */ |
75 | #define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */ |
76 | #define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */ |
77 | |
78 | #define AT91_ADC_SR_9X5 0x30 /* Status Register for 9x5 */ |
79 | #define AT91_ADC_SR_DRDY_9X5 (1 << 24) /* Data Ready */ |
80 | |
81 | #define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */ |
82 | #define AT91_ADC_LDATA (0x3ff) |
83 | |
84 | #define AT91_ADC_IER 0x24 /* Interrupt Enable Register */ |
85 | #define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */ |
86 | #define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */ |
87 | #define AT91RL_ADC_IER_PEN (1 << 20) |
88 | #define AT91RL_ADC_IER_NOPEN (1 << 21) |
89 | #define AT91_ADC_IER_PEN (1 << 29) |
90 | #define AT91_ADC_IER_NOPEN (1 << 30) |
91 | #define AT91_ADC_IER_XRDY (1 << 20) |
92 | #define AT91_ADC_IER_YRDY (1 << 21) |
93 | #define AT91_ADC_IER_PRDY (1 << 22) |
94 | #define AT91_ADC_ISR_PENS (1 << 31) |
95 | |
96 | #define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */ |
97 | #define AT91_ADC_DATA (0x3ff) |
98 | |
99 | #define AT91_ADC_CDR0_9X5 (0x50) /* Channel Data Register 0 for 9X5 */ |
100 | |
101 | #define AT91_ADC_ACR 0x94 /* Analog Control Register */ |
102 | #define AT91_ADC_ACR_PENDETSENS (0x3 << 0) /* pull-up resistor */ |
103 | |
104 | #define AT91_ADC_TSMR 0xB0 |
105 | #define AT91_ADC_TSMR_TSMODE (3 << 0) /* Touch Screen Mode */ |
106 | #define AT91_ADC_TSMR_TSMODE_NONE (0 << 0) |
107 | #define AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS (1 << 0) |
108 | #define AT91_ADC_TSMR_TSMODE_4WIRE_PRESS (2 << 0) |
109 | #define AT91_ADC_TSMR_TSMODE_5WIRE (3 << 0) |
110 | #define AT91_ADC_TSMR_TSAV (3 << 4) /* Averages samples */ |
111 | #define AT91_ADC_TSMR_TSAV_(x) ((x) << 4) |
112 | #define AT91_ADC_TSMR_SCTIM (0x0f << 16) /* Switch closure time */ |
113 | #define AT91_ADC_TSMR_SCTIM_(x) ((x) << 16) |
114 | #define AT91_ADC_TSMR_PENDBC (0x0f << 28) /* Pen Debounce time */ |
115 | #define AT91_ADC_TSMR_PENDBC_(x) ((x) << 28) |
116 | #define AT91_ADC_TSMR_NOTSDMA (1 << 22) /* No Touchscreen DMA */ |
117 | #define AT91_ADC_TSMR_PENDET_DIS (0 << 24) /* Pen contact detection disable */ |
118 | #define AT91_ADC_TSMR_PENDET_ENA (1 << 24) /* Pen contact detection enable */ |
119 | |
120 | #define AT91_ADC_TSXPOSR 0xB4 |
121 | #define AT91_ADC_TSYPOSR 0xB8 |
122 | #define AT91_ADC_TSPRESSR 0xBC |
123 | |
124 | #define AT91_ADC_TRGR_9260 AT91_ADC_MR |
125 | #define AT91_ADC_TRGR_9G45 0x08 |
126 | #define AT91_ADC_TRGR_9X5 0xC0 |
127 | |
128 | /* Trigger Register bit field */ |
129 | #define AT91_ADC_TRGR_TRGPER (0xffff << 16) |
130 | #define AT91_ADC_TRGR_TRGPER_(x) ((x) << 16) |
131 | #define AT91_ADC_TRGR_TRGMOD (0x7 << 0) |
132 | #define AT91_ADC_TRGR_NONE (0 << 0) |
133 | #define AT91_ADC_TRGR_MOD_PERIOD_TRIG (5 << 0) |
134 | |
135 | #define AT91_ADC_CHAN(st, ch) \ |
136 | (st->registers->channel_base + (ch * 4)) |
137 | #define at91_adc_readl(st, reg) \ |
138 | (readl_relaxed(st->reg_base + reg)) |
139 | #define at91_adc_writel(st, reg, val) \ |
140 | (writel_relaxed(val, st->reg_base + reg)) |
141 | |
142 | #define DRIVER_NAME "at91_adc" |
143 | #define MAX_POS_BITS 12 |
144 | |
145 | #define TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */ |
146 | #define TOUCH_PEN_DETECT_DEBOUNCE_US 200 |
147 | |
148 | #define MAX_RLPOS_BITS 10 |
149 | #define TOUCH_SAMPLE_PERIOD_US_RL 10000 /* 10ms, the SoC can't keep up with 2ms */ |
150 | #define TOUCH_SHTIM 0xa |
151 | #define TOUCH_SCTIM_US 10 /* 10us for the Touchscreen Switches Closure Time */ |
152 | |
153 | enum atmel_adc_ts_type { |
154 | ATMEL_ADC_TOUCHSCREEN_NONE = 0, |
155 | ATMEL_ADC_TOUCHSCREEN_4WIRE = 4, |
156 | ATMEL_ADC_TOUCHSCREEN_5WIRE = 5, |
157 | }; |
158 | |
159 | /** |
160 | * struct at91_adc_trigger - description of triggers |
161 | * @name: name of the trigger advertised to the user |
162 | * @value: value to set in the ADC's trigger setup register |
163 | * to enable the trigger |
164 | * @is_external: Does the trigger rely on an external pin? |
165 | */ |
166 | struct at91_adc_trigger { |
167 | const char *name; |
168 | u8 value; |
169 | bool is_external; |
170 | }; |
171 | |
172 | /** |
173 | * struct at91_adc_reg_desc - Various informations relative to registers |
174 | * @channel_base: Base offset for the channel data registers |
175 | * @drdy_mask: Mask of the DRDY field in the relevant registers |
176 | * (Interruptions registers mostly) |
177 | * @status_register: Offset of the Interrupt Status Register |
178 | * @trigger_register: Offset of the Trigger setup register |
179 | * @mr_prescal_mask: Mask of the PRESCAL field in the adc MR register |
180 | * @mr_startup_mask: Mask of the STARTUP field in the adc MR register |
181 | */ |
182 | struct at91_adc_reg_desc { |
183 | u8 channel_base; |
184 | u32 drdy_mask; |
185 | u8 status_register; |
186 | u8 trigger_register; |
187 | u32 mr_prescal_mask; |
188 | u32 mr_startup_mask; |
189 | }; |
190 | |
191 | struct at91_adc_caps { |
192 | bool has_ts; /* Support touch screen */ |
193 | bool has_tsmr; /* only at91sam9x5, sama5d3 have TSMR reg */ |
194 | /* |
195 | * Numbers of sampling data will be averaged. Can be 0~3. |
196 | * Hardware can average (2 ^ ts_filter_average) sample data. |
197 | */ |
198 | u8 ts_filter_average; |
199 | /* Pen Detection input pull-up resistor, can be 0~3 */ |
200 | u8 ts_pen_detect_sensitivity; |
201 | |
202 | /* startup time calculate function */ |
203 | u32 (*calc_startup_ticks)(u32 startup_time, u32 adc_clk_khz); |
204 | |
205 | u8 num_channels; |
206 | |
207 | u8 low_res_bits; |
208 | u8 high_res_bits; |
209 | u32 trigger_number; |
210 | const struct at91_adc_trigger *triggers; |
211 | struct at91_adc_reg_desc registers; |
212 | }; |
213 | |
214 | struct at91_adc_state { |
215 | struct clk *adc_clk; |
216 | u16 *buffer; |
217 | unsigned long channels_mask; |
218 | struct clk *clk; |
219 | bool done; |
220 | int irq; |
221 | u16 last_value; |
222 | int chnb; |
223 | struct mutex lock; |
224 | u8 num_channels; |
225 | void __iomem *reg_base; |
226 | const struct at91_adc_reg_desc *registers; |
227 | u32 startup_time; |
228 | u8 sample_hold_time; |
229 | bool sleep_mode; |
230 | struct iio_trigger **trig; |
231 | bool use_external; |
232 | u32 vref_mv; |
233 | u32 res; /* resolution used for convertions */ |
234 | wait_queue_head_t wq_data_avail; |
235 | const struct at91_adc_caps *caps; |
236 | |
237 | /* |
238 | * Following ADC channels are shared by touchscreen: |
239 | * |
240 | * CH0 -- Touch screen XP/UL |
241 | * CH1 -- Touch screen XM/UR |
242 | * CH2 -- Touch screen YP/LL |
243 | * CH3 -- Touch screen YM/Sense |
244 | * CH4 -- Touch screen LR(5-wire only) |
245 | * |
246 | * The bitfields below represents the reserved channel in the |
247 | * touchscreen mode. |
248 | */ |
249 | #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 0) |
250 | #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 0) |
251 | enum atmel_adc_ts_type touchscreen_type; |
252 | struct input_dev *ts_input; |
253 | |
254 | u16 ts_sample_period_val; |
255 | u32 ts_pressure_threshold; |
256 | u16 ts_pendbc; |
257 | |
258 | bool ts_bufferedmeasure; |
259 | u32 ts_prev_absx; |
260 | u32 ts_prev_absy; |
261 | }; |
262 | |
263 | static irqreturn_t at91_adc_trigger_handler(int irq, void *p) |
264 | { |
265 | struct iio_poll_func *pf = p; |
266 | struct iio_dev *idev = pf->indio_dev; |
267 | struct at91_adc_state *st = iio_priv(indio_dev: idev); |
268 | struct iio_chan_spec const *chan; |
269 | int i, j = 0; |
270 | |
271 | for (i = 0; i < idev->masklength; i++) { |
272 | if (!test_bit(i, idev->active_scan_mask)) |
273 | continue; |
274 | chan = idev->channels + i; |
275 | st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, chan->channel)); |
276 | j++; |
277 | } |
278 | |
279 | iio_push_to_buffers_with_timestamp(indio_dev: idev, data: st->buffer, timestamp: pf->timestamp); |
280 | |
281 | iio_trigger_notify_done(trig: idev->trig); |
282 | |
283 | /* Needed to ACK the DRDY interruption */ |
284 | at91_adc_readl(st, AT91_ADC_LCDR); |
285 | |
286 | enable_irq(irq: st->irq); |
287 | |
288 | return IRQ_HANDLED; |
289 | } |
290 | |
291 | /* Handler for classic adc channel eoc trigger */ |
292 | static void handle_adc_eoc_trigger(int irq, struct iio_dev *idev) |
293 | { |
294 | struct at91_adc_state *st = iio_priv(indio_dev: idev); |
295 | |
296 | if (iio_buffer_enabled(indio_dev: idev)) { |
297 | disable_irq_nosync(irq); |
298 | iio_trigger_poll(trig: idev->trig); |
299 | } else { |
300 | st->last_value = at91_adc_readl(st, AT91_ADC_CHAN(st, st->chnb)); |
301 | /* Needed to ACK the DRDY interruption */ |
302 | at91_adc_readl(st, AT91_ADC_LCDR); |
303 | st->done = true; |
304 | wake_up_interruptible(&st->wq_data_avail); |
305 | } |
306 | } |
307 | |
308 | static int at91_ts_sample(struct iio_dev *idev) |
309 | { |
310 | struct at91_adc_state *st = iio_priv(indio_dev: idev); |
311 | unsigned int xscale, yscale, reg, z1, z2; |
312 | unsigned int x, y, pres, xpos, ypos; |
313 | unsigned int rxp = 1; |
314 | unsigned int factor = 1000; |
315 | |
316 | unsigned int xyz_mask_bits = st->res; |
317 | unsigned int xyz_mask = (1 << xyz_mask_bits) - 1; |
318 | |
319 | /* calculate position */ |
320 | /* x position = (x / xscale) * max, max = 2^MAX_POS_BITS - 1 */ |
321 | reg = at91_adc_readl(st, AT91_ADC_TSXPOSR); |
322 | xpos = reg & xyz_mask; |
323 | x = (xpos << MAX_POS_BITS) - xpos; |
324 | xscale = (reg >> 16) & xyz_mask; |
325 | if (xscale == 0) { |
326 | dev_err(&idev->dev, "Error: xscale == 0!\n" ); |
327 | return -1; |
328 | } |
329 | x /= xscale; |
330 | |
331 | /* y position = (y / yscale) * max, max = 2^MAX_POS_BITS - 1 */ |
332 | reg = at91_adc_readl(st, AT91_ADC_TSYPOSR); |
333 | ypos = reg & xyz_mask; |
334 | y = (ypos << MAX_POS_BITS) - ypos; |
335 | yscale = (reg >> 16) & xyz_mask; |
336 | if (yscale == 0) { |
337 | dev_err(&idev->dev, "Error: yscale == 0!\n" ); |
338 | return -1; |
339 | } |
340 | y /= yscale; |
341 | |
342 | /* calculate the pressure */ |
343 | reg = at91_adc_readl(st, AT91_ADC_TSPRESSR); |
344 | z1 = reg & xyz_mask; |
345 | z2 = (reg >> 16) & xyz_mask; |
346 | |
347 | if (z1 != 0) |
348 | pres = rxp * (x * factor / 1024) * (z2 * factor / z1 - factor) |
349 | / factor; |
350 | else |
351 | pres = st->ts_pressure_threshold; /* no pen contacted */ |
352 | |
353 | dev_dbg(&idev->dev, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n" , |
354 | xpos, xscale, ypos, yscale, z1, z2, pres); |
355 | |
356 | if (pres < st->ts_pressure_threshold) { |
357 | dev_dbg(&idev->dev, "x = %d, y = %d, pressure = %d\n" , |
358 | x, y, pres / factor); |
359 | input_report_abs(dev: st->ts_input, ABS_X, value: x); |
360 | input_report_abs(dev: st->ts_input, ABS_Y, value: y); |
361 | input_report_abs(dev: st->ts_input, ABS_PRESSURE, value: pres); |
362 | input_report_key(dev: st->ts_input, BTN_TOUCH, value: 1); |
363 | input_sync(dev: st->ts_input); |
364 | } else { |
365 | dev_dbg(&idev->dev, "pressure too low: not reporting\n" ); |
366 | } |
367 | |
368 | return 0; |
369 | } |
370 | |
371 | static irqreturn_t at91_adc_rl_interrupt(int irq, void *private) |
372 | { |
373 | struct iio_dev *idev = private; |
374 | struct at91_adc_state *st = iio_priv(indio_dev: idev); |
375 | u32 status = at91_adc_readl(st, st->registers->status_register); |
376 | unsigned int reg; |
377 | |
378 | status &= at91_adc_readl(st, AT91_ADC_IMR); |
379 | if (status & GENMASK(st->num_channels - 1, 0)) |
380 | handle_adc_eoc_trigger(irq, idev); |
381 | |
382 | if (status & AT91RL_ADC_IER_PEN) { |
383 | /* Disabling pen debounce is required to get a NOPEN irq */ |
384 | reg = at91_adc_readl(st, AT91_ADC_MR); |
385 | reg &= ~AT91_ADC_PENDBC; |
386 | at91_adc_writel(st, AT91_ADC_MR, reg); |
387 | |
388 | at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN); |
389 | at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_NOPEN |
390 | | AT91_ADC_EOC(3)); |
391 | /* Set up period trigger for sampling */ |
392 | at91_adc_writel(st, st->registers->trigger_register, |
393 | AT91_ADC_TRGR_MOD_PERIOD_TRIG | |
394 | AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val)); |
395 | } else if (status & AT91RL_ADC_IER_NOPEN) { |
396 | reg = at91_adc_readl(st, AT91_ADC_MR); |
397 | reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC; |
398 | at91_adc_writel(st, AT91_ADC_MR, reg); |
399 | at91_adc_writel(st, st->registers->trigger_register, |
400 | AT91_ADC_TRGR_NONE); |
401 | |
402 | at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_NOPEN |
403 | | AT91_ADC_EOC(3)); |
404 | at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN); |
405 | st->ts_bufferedmeasure = false; |
406 | input_report_key(dev: st->ts_input, BTN_TOUCH, value: 0); |
407 | input_sync(dev: st->ts_input); |
408 | } else if (status & AT91_ADC_EOC(3) && st->ts_input) { |
409 | /* Conversion finished and we've a touchscreen */ |
410 | if (st->ts_bufferedmeasure) { |
411 | /* |
412 | * Last measurement is always discarded, since it can |
413 | * be erroneous. |
414 | * Always report previous measurement |
415 | */ |
416 | input_report_abs(dev: st->ts_input, ABS_X, value: st->ts_prev_absx); |
417 | input_report_abs(dev: st->ts_input, ABS_Y, value: st->ts_prev_absy); |
418 | input_report_key(dev: st->ts_input, BTN_TOUCH, value: 1); |
419 | input_sync(dev: st->ts_input); |
420 | } else |
421 | st->ts_bufferedmeasure = true; |
422 | |
423 | /* Now make new measurement */ |
424 | st->ts_prev_absx = at91_adc_readl(st, AT91_ADC_CHAN(st, 3)) |
425 | << MAX_RLPOS_BITS; |
426 | st->ts_prev_absx /= at91_adc_readl(st, AT91_ADC_CHAN(st, 2)); |
427 | |
428 | st->ts_prev_absy = at91_adc_readl(st, AT91_ADC_CHAN(st, 1)) |
429 | << MAX_RLPOS_BITS; |
430 | st->ts_prev_absy /= at91_adc_readl(st, AT91_ADC_CHAN(st, 0)); |
431 | } |
432 | |
433 | return IRQ_HANDLED; |
434 | } |
435 | |
436 | static irqreturn_t at91_adc_9x5_interrupt(int irq, void *private) |
437 | { |
438 | struct iio_dev *idev = private; |
439 | struct at91_adc_state *st = iio_priv(indio_dev: idev); |
440 | u32 status = at91_adc_readl(st, st->registers->status_register); |
441 | const uint32_t ts_data_irq_mask = |
442 | AT91_ADC_IER_XRDY | |
443 | AT91_ADC_IER_YRDY | |
444 | AT91_ADC_IER_PRDY; |
445 | |
446 | if (status & GENMASK(st->num_channels - 1, 0)) |
447 | handle_adc_eoc_trigger(irq, idev); |
448 | |
449 | if (status & AT91_ADC_IER_PEN) { |
450 | at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN); |
451 | at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN | |
452 | ts_data_irq_mask); |
453 | /* Set up period trigger for sampling */ |
454 | at91_adc_writel(st, st->registers->trigger_register, |
455 | AT91_ADC_TRGR_MOD_PERIOD_TRIG | |
456 | AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val)); |
457 | } else if (status & AT91_ADC_IER_NOPEN) { |
458 | at91_adc_writel(st, st->registers->trigger_register, 0); |
459 | at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN | |
460 | ts_data_irq_mask); |
461 | at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN); |
462 | |
463 | input_report_key(dev: st->ts_input, BTN_TOUCH, value: 0); |
464 | input_sync(dev: st->ts_input); |
465 | } else if ((status & ts_data_irq_mask) == ts_data_irq_mask) { |
466 | /* Now all touchscreen data is ready */ |
467 | |
468 | if (status & AT91_ADC_ISR_PENS) { |
469 | /* validate data by pen contact */ |
470 | at91_ts_sample(idev); |
471 | } else { |
472 | /* triggered by event that is no pen contact, just read |
473 | * them to clean the interrupt and discard all. |
474 | */ |
475 | at91_adc_readl(st, AT91_ADC_TSXPOSR); |
476 | at91_adc_readl(st, AT91_ADC_TSYPOSR); |
477 | at91_adc_readl(st, AT91_ADC_TSPRESSR); |
478 | } |
479 | } |
480 | |
481 | return IRQ_HANDLED; |
482 | } |
483 | |
484 | static int at91_adc_channel_init(struct iio_dev *idev) |
485 | { |
486 | struct at91_adc_state *st = iio_priv(indio_dev: idev); |
487 | struct iio_chan_spec *chan_array, *timestamp; |
488 | int bit, idx = 0; |
489 | unsigned long rsvd_mask = 0; |
490 | |
491 | /* If touchscreen is enable, then reserve the adc channels */ |
492 | if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE) |
493 | rsvd_mask = CHAN_MASK_TOUCHSCREEN_4WIRE; |
494 | else if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_5WIRE) |
495 | rsvd_mask = CHAN_MASK_TOUCHSCREEN_5WIRE; |
496 | |
497 | /* set up the channel mask to reserve touchscreen channels */ |
498 | st->channels_mask &= ~rsvd_mask; |
499 | |
500 | idev->num_channels = bitmap_weight(src: &st->channels_mask, |
501 | nbits: st->num_channels) + 1; |
502 | |
503 | chan_array = devm_kzalloc(dev: &idev->dev, |
504 | size: ((idev->num_channels + 1) * |
505 | sizeof(struct iio_chan_spec)), |
506 | GFP_KERNEL); |
507 | |
508 | if (!chan_array) |
509 | return -ENOMEM; |
510 | |
511 | for_each_set_bit(bit, &st->channels_mask, st->num_channels) { |
512 | struct iio_chan_spec *chan = chan_array + idx; |
513 | |
514 | chan->type = IIO_VOLTAGE; |
515 | chan->indexed = 1; |
516 | chan->channel = bit; |
517 | chan->scan_index = idx; |
518 | chan->scan_type.sign = 'u'; |
519 | chan->scan_type.realbits = st->res; |
520 | chan->scan_type.storagebits = 16; |
521 | chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); |
522 | chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); |
523 | idx++; |
524 | } |
525 | timestamp = chan_array + idx; |
526 | |
527 | timestamp->type = IIO_TIMESTAMP; |
528 | timestamp->channel = -1; |
529 | timestamp->scan_index = idx; |
530 | timestamp->scan_type.sign = 's'; |
531 | timestamp->scan_type.realbits = 64; |
532 | timestamp->scan_type.storagebits = 64; |
533 | |
534 | idev->channels = chan_array; |
535 | return idev->num_channels; |
536 | } |
537 | |
538 | static int at91_adc_get_trigger_value_by_name(struct iio_dev *idev, |
539 | const struct at91_adc_trigger *triggers, |
540 | const char *trigger_name) |
541 | { |
542 | struct at91_adc_state *st = iio_priv(indio_dev: idev); |
543 | int i; |
544 | |
545 | for (i = 0; i < st->caps->trigger_number; i++) { |
546 | char *name = kasprintf(GFP_KERNEL, |
547 | fmt: "%s-dev%d-%s" , |
548 | idev->name, |
549 | iio_device_id(indio_dev: idev), |
550 | triggers[i].name); |
551 | if (!name) |
552 | return -ENOMEM; |
553 | |
554 | if (strcmp(trigger_name, name) == 0) { |
555 | kfree(objp: name); |
556 | if (triggers[i].value == 0) |
557 | return -EINVAL; |
558 | return triggers[i].value; |
559 | } |
560 | |
561 | kfree(objp: name); |
562 | } |
563 | |
564 | return -EINVAL; |
565 | } |
566 | |
567 | static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) |
568 | { |
569 | struct iio_dev *idev = iio_trigger_get_drvdata(trig); |
570 | struct at91_adc_state *st = iio_priv(indio_dev: idev); |
571 | const struct at91_adc_reg_desc *reg = st->registers; |
572 | u32 status = at91_adc_readl(st, reg->trigger_register); |
573 | int value; |
574 | u8 bit; |
575 | |
576 | value = at91_adc_get_trigger_value_by_name(idev, |
577 | triggers: st->caps->triggers, |
578 | trigger_name: idev->trig->name); |
579 | if (value < 0) |
580 | return value; |
581 | |
582 | if (state) { |
583 | st->buffer = kmalloc(size: idev->scan_bytes, GFP_KERNEL); |
584 | if (st->buffer == NULL) |
585 | return -ENOMEM; |
586 | |
587 | at91_adc_writel(st, reg->trigger_register, |
588 | status | value); |
589 | |
590 | for_each_set_bit(bit, idev->active_scan_mask, |
591 | st->num_channels) { |
592 | struct iio_chan_spec const *chan = idev->channels + bit; |
593 | at91_adc_writel(st, AT91_ADC_CHER, |
594 | AT91_ADC_CH(chan->channel)); |
595 | } |
596 | |
597 | at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask); |
598 | |
599 | } else { |
600 | at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask); |
601 | |
602 | at91_adc_writel(st, reg->trigger_register, |
603 | status & ~value); |
604 | |
605 | for_each_set_bit(bit, idev->active_scan_mask, |
606 | st->num_channels) { |
607 | struct iio_chan_spec const *chan = idev->channels + bit; |
608 | at91_adc_writel(st, AT91_ADC_CHDR, |
609 | AT91_ADC_CH(chan->channel)); |
610 | } |
611 | kfree(objp: st->buffer); |
612 | } |
613 | |
614 | return 0; |
615 | } |
616 | |
617 | static const struct iio_trigger_ops at91_adc_trigger_ops = { |
618 | .set_trigger_state = &at91_adc_configure_trigger, |
619 | }; |
620 | |
621 | static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev, |
622 | const struct at91_adc_trigger *trigger) |
623 | { |
624 | struct iio_trigger *trig; |
625 | int ret; |
626 | |
627 | trig = iio_trigger_alloc(idev->dev.parent, "%s-dev%d-%s" , idev->name, |
628 | iio_device_id(idev), trigger->name); |
629 | if (trig == NULL) |
630 | return NULL; |
631 | |
632 | iio_trigger_set_drvdata(trig, data: idev); |
633 | trig->ops = &at91_adc_trigger_ops; |
634 | |
635 | ret = iio_trigger_register(trig_info: trig); |
636 | if (ret) { |
637 | iio_trigger_free(trig); |
638 | return NULL; |
639 | } |
640 | |
641 | return trig; |
642 | } |
643 | |
644 | static int at91_adc_trigger_init(struct iio_dev *idev) |
645 | { |
646 | struct at91_adc_state *st = iio_priv(indio_dev: idev); |
647 | int i, ret; |
648 | |
649 | st->trig = devm_kcalloc(dev: &idev->dev, |
650 | n: st->caps->trigger_number, size: sizeof(*st->trig), |
651 | GFP_KERNEL); |
652 | |
653 | if (st->trig == NULL) { |
654 | ret = -ENOMEM; |
655 | goto error_ret; |
656 | } |
657 | |
658 | for (i = 0; i < st->caps->trigger_number; i++) { |
659 | if (st->caps->triggers[i].is_external && !(st->use_external)) |
660 | continue; |
661 | |
662 | st->trig[i] = at91_adc_allocate_trigger(idev, |
663 | trigger: st->caps->triggers + i); |
664 | if (st->trig[i] == NULL) { |
665 | dev_err(&idev->dev, |
666 | "Could not allocate trigger %d\n" , i); |
667 | ret = -ENOMEM; |
668 | goto error_trigger; |
669 | } |
670 | } |
671 | |
672 | return 0; |
673 | |
674 | error_trigger: |
675 | for (i--; i >= 0; i--) { |
676 | iio_trigger_unregister(trig_info: st->trig[i]); |
677 | iio_trigger_free(trig: st->trig[i]); |
678 | } |
679 | error_ret: |
680 | return ret; |
681 | } |
682 | |
683 | static void at91_adc_trigger_remove(struct iio_dev *idev) |
684 | { |
685 | struct at91_adc_state *st = iio_priv(indio_dev: idev); |
686 | int i; |
687 | |
688 | for (i = 0; i < st->caps->trigger_number; i++) { |
689 | iio_trigger_unregister(trig_info: st->trig[i]); |
690 | iio_trigger_free(trig: st->trig[i]); |
691 | } |
692 | } |
693 | |
694 | static int at91_adc_buffer_init(struct iio_dev *idev) |
695 | { |
696 | return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time, |
697 | &at91_adc_trigger_handler, NULL); |
698 | } |
699 | |
700 | static void at91_adc_buffer_remove(struct iio_dev *idev) |
701 | { |
702 | iio_triggered_buffer_cleanup(indio_dev: idev); |
703 | } |
704 | |
705 | static int at91_adc_read_raw(struct iio_dev *idev, |
706 | struct iio_chan_spec const *chan, |
707 | int *val, int *val2, long mask) |
708 | { |
709 | struct at91_adc_state *st = iio_priv(indio_dev: idev); |
710 | int ret; |
711 | |
712 | switch (mask) { |
713 | case IIO_CHAN_INFO_RAW: |
714 | mutex_lock(&st->lock); |
715 | |
716 | st->chnb = chan->channel; |
717 | at91_adc_writel(st, AT91_ADC_CHER, |
718 | AT91_ADC_CH(chan->channel)); |
719 | at91_adc_writel(st, AT91_ADC_IER, BIT(chan->channel)); |
720 | at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START); |
721 | |
722 | ret = wait_event_interruptible_timeout(st->wq_data_avail, |
723 | st->done, |
724 | msecs_to_jiffies(1000)); |
725 | |
726 | /* Disable interrupts, regardless if adc conversion was |
727 | * successful or not |
728 | */ |
729 | at91_adc_writel(st, AT91_ADC_CHDR, |
730 | AT91_ADC_CH(chan->channel)); |
731 | at91_adc_writel(st, AT91_ADC_IDR, BIT(chan->channel)); |
732 | |
733 | if (ret > 0) { |
734 | /* a valid conversion took place */ |
735 | *val = st->last_value; |
736 | st->last_value = 0; |
737 | st->done = false; |
738 | ret = IIO_VAL_INT; |
739 | } else if (ret == 0) { |
740 | /* conversion timeout */ |
741 | dev_err(&idev->dev, "ADC Channel %d timeout.\n" , |
742 | chan->channel); |
743 | ret = -ETIMEDOUT; |
744 | } |
745 | |
746 | mutex_unlock(lock: &st->lock); |
747 | return ret; |
748 | |
749 | case IIO_CHAN_INFO_SCALE: |
750 | *val = st->vref_mv; |
751 | *val2 = chan->scan_type.realbits; |
752 | return IIO_VAL_FRACTIONAL_LOG2; |
753 | default: |
754 | break; |
755 | } |
756 | return -EINVAL; |
757 | } |
758 | |
759 | |
760 | static u32 calc_startup_ticks_9260(u32 startup_time, u32 adc_clk_khz) |
761 | { |
762 | /* |
763 | * Number of ticks needed to cover the startup time of the ADC |
764 | * as defined in the electrical characteristics of the board, |
765 | * divided by 8. The formula thus is : |
766 | * Startup Time = (ticks + 1) * 8 / ADC Clock |
767 | */ |
768 | return round_up((startup_time * adc_clk_khz / 1000) - 1, 8) / 8; |
769 | } |
770 | |
771 | static u32 calc_startup_ticks_9x5(u32 startup_time, u32 adc_clk_khz) |
772 | { |
773 | /* |
774 | * For sama5d3x and at91sam9x5, the formula changes to: |
775 | * Startup Time = <lookup_table_value> / ADC Clock |
776 | */ |
777 | static const int startup_lookup[] = { |
778 | 0, 8, 16, 24, |
779 | 64, 80, 96, 112, |
780 | 512, 576, 640, 704, |
781 | 768, 832, 896, 960 |
782 | }; |
783 | int i, size = ARRAY_SIZE(startup_lookup); |
784 | unsigned int ticks; |
785 | |
786 | ticks = startup_time * adc_clk_khz / 1000; |
787 | for (i = 0; i < size; i++) |
788 | if (ticks < startup_lookup[i]) |
789 | break; |
790 | |
791 | ticks = i; |
792 | if (ticks == size) |
793 | /* Reach the end of lookup table */ |
794 | ticks = size - 1; |
795 | |
796 | return ticks; |
797 | } |
798 | |
799 | static int at91_adc_probe_dt_ts(struct device_node *node, |
800 | struct at91_adc_state *st, struct device *dev) |
801 | { |
802 | int ret; |
803 | u32 prop; |
804 | |
805 | ret = of_property_read_u32(np: node, propname: "atmel,adc-ts-wires" , out_value: &prop); |
806 | if (ret) { |
807 | dev_info(dev, "ADC Touch screen is disabled.\n" ); |
808 | return 0; |
809 | } |
810 | |
811 | switch (prop) { |
812 | case 4: |
813 | case 5: |
814 | st->touchscreen_type = prop; |
815 | break; |
816 | default: |
817 | dev_err(dev, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n" , prop); |
818 | return -EINVAL; |
819 | } |
820 | |
821 | if (!st->caps->has_tsmr) |
822 | return 0; |
823 | prop = 0; |
824 | of_property_read_u32(np: node, propname: "atmel,adc-ts-pressure-threshold" , out_value: &prop); |
825 | st->ts_pressure_threshold = prop; |
826 | if (st->ts_pressure_threshold) { |
827 | return 0; |
828 | } else { |
829 | dev_err(dev, "Invalid pressure threshold for the touchscreen\n" ); |
830 | return -EINVAL; |
831 | } |
832 | } |
833 | |
834 | static const struct iio_info at91_adc_info = { |
835 | .read_raw = &at91_adc_read_raw, |
836 | }; |
837 | |
838 | /* Touchscreen related functions */ |
839 | static int atmel_ts_open(struct input_dev *dev) |
840 | { |
841 | struct at91_adc_state *st = input_get_drvdata(dev); |
842 | |
843 | if (st->caps->has_tsmr) |
844 | at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN); |
845 | else |
846 | at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN); |
847 | return 0; |
848 | } |
849 | |
850 | static void atmel_ts_close(struct input_dev *dev) |
851 | { |
852 | struct at91_adc_state *st = input_get_drvdata(dev); |
853 | |
854 | if (st->caps->has_tsmr) |
855 | at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN); |
856 | else |
857 | at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN); |
858 | } |
859 | |
860 | static int at91_ts_hw_init(struct iio_dev *idev, u32 adc_clk_khz) |
861 | { |
862 | struct at91_adc_state *st = iio_priv(indio_dev: idev); |
863 | u32 reg = 0; |
864 | u32 tssctim = 0; |
865 | int i = 0; |
866 | |
867 | /* a Pen Detect Debounce Time is necessary for the ADC Touch to avoid |
868 | * pen detect noise. |
869 | * The formula is : Pen Detect Debounce Time = (2 ^ pendbc) / ADCClock |
870 | */ |
871 | st->ts_pendbc = round_up(TOUCH_PEN_DETECT_DEBOUNCE_US * adc_clk_khz / |
872 | 1000, 1); |
873 | |
874 | while (st->ts_pendbc >> ++i) |
875 | ; /* Empty! Find the shift offset */ |
876 | if (abs(st->ts_pendbc - (1 << i)) < abs(st->ts_pendbc - (1 << (i - 1)))) |
877 | st->ts_pendbc = i; |
878 | else |
879 | st->ts_pendbc = i - 1; |
880 | |
881 | if (!st->caps->has_tsmr) { |
882 | reg = at91_adc_readl(st, AT91_ADC_MR); |
883 | reg |= AT91_ADC_TSAMOD_TS_ONLY_MODE | AT91_ADC_PENDET; |
884 | |
885 | reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC; |
886 | at91_adc_writel(st, AT91_ADC_MR, reg); |
887 | |
888 | reg = AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM) & AT91_ADC_TSR_SHTIM; |
889 | at91_adc_writel(st, AT91_ADC_TSR, reg); |
890 | |
891 | st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US_RL * |
892 | adc_clk_khz / 1000) - 1, 1); |
893 | |
894 | return 0; |
895 | } |
896 | |
897 | /* Touchscreen Switches Closure time needed for allowing the value to |
898 | * stabilize. |
899 | * Switch Closure Time = (TSSCTIM * 4) ADCClock periods |
900 | */ |
901 | tssctim = DIV_ROUND_UP(TOUCH_SCTIM_US * adc_clk_khz / 1000, 4); |
902 | dev_dbg(&idev->dev, "adc_clk at: %d KHz, tssctim at: %d\n" , |
903 | adc_clk_khz, tssctim); |
904 | |
905 | if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE) |
906 | reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS; |
907 | else |
908 | reg = AT91_ADC_TSMR_TSMODE_5WIRE; |
909 | |
910 | reg |= AT91_ADC_TSMR_SCTIM_(tssctim) & AT91_ADC_TSMR_SCTIM; |
911 | reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average) |
912 | & AT91_ADC_TSMR_TSAV; |
913 | reg |= AT91_ADC_TSMR_PENDBC_(st->ts_pendbc) & AT91_ADC_TSMR_PENDBC; |
914 | reg |= AT91_ADC_TSMR_NOTSDMA; |
915 | reg |= AT91_ADC_TSMR_PENDET_ENA; |
916 | reg |= 0x03 << 8; /* TSFREQ, needs to be bigger than TSAV */ |
917 | |
918 | at91_adc_writel(st, AT91_ADC_TSMR, reg); |
919 | |
920 | /* Change adc internal resistor value for better pen detection, |
921 | * default value is 100 kOhm. |
922 | * 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm |
923 | * option only available on ES2 and higher |
924 | */ |
925 | at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity |
926 | & AT91_ADC_ACR_PENDETSENS); |
927 | |
928 | /* Sample Period Time = (TRGPER + 1) / ADCClock */ |
929 | st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US * |
930 | adc_clk_khz / 1000) - 1, 1); |
931 | |
932 | return 0; |
933 | } |
934 | |
935 | static int at91_ts_register(struct iio_dev *idev, |
936 | struct platform_device *pdev) |
937 | { |
938 | struct at91_adc_state *st = iio_priv(indio_dev: idev); |
939 | struct input_dev *input; |
940 | int ret; |
941 | |
942 | input = input_allocate_device(); |
943 | if (!input) { |
944 | dev_err(&idev->dev, "Failed to allocate TS device!\n" ); |
945 | return -ENOMEM; |
946 | } |
947 | |
948 | input->name = DRIVER_NAME; |
949 | input->id.bustype = BUS_HOST; |
950 | input->dev.parent = &pdev->dev; |
951 | input->open = atmel_ts_open; |
952 | input->close = atmel_ts_close; |
953 | |
954 | __set_bit(EV_ABS, input->evbit); |
955 | __set_bit(EV_KEY, input->evbit); |
956 | __set_bit(BTN_TOUCH, input->keybit); |
957 | if (st->caps->has_tsmr) { |
958 | input_set_abs_params(dev: input, ABS_X, min: 0, max: (1 << MAX_POS_BITS) - 1, |
959 | fuzz: 0, flat: 0); |
960 | input_set_abs_params(dev: input, ABS_Y, min: 0, max: (1 << MAX_POS_BITS) - 1, |
961 | fuzz: 0, flat: 0); |
962 | input_set_abs_params(dev: input, ABS_PRESSURE, min: 0, max: 0xffffff, fuzz: 0, flat: 0); |
963 | } else { |
964 | if (st->touchscreen_type != ATMEL_ADC_TOUCHSCREEN_4WIRE) { |
965 | dev_err(&pdev->dev, |
966 | "This touchscreen controller only support 4 wires\n" ); |
967 | ret = -EINVAL; |
968 | goto err; |
969 | } |
970 | |
971 | input_set_abs_params(dev: input, ABS_X, min: 0, max: (1 << MAX_RLPOS_BITS) - 1, |
972 | fuzz: 0, flat: 0); |
973 | input_set_abs_params(dev: input, ABS_Y, min: 0, max: (1 << MAX_RLPOS_BITS) - 1, |
974 | fuzz: 0, flat: 0); |
975 | } |
976 | |
977 | st->ts_input = input; |
978 | input_set_drvdata(dev: input, data: st); |
979 | |
980 | ret = input_register_device(input); |
981 | if (ret) |
982 | goto err; |
983 | |
984 | return ret; |
985 | |
986 | err: |
987 | input_free_device(dev: st->ts_input); |
988 | return ret; |
989 | } |
990 | |
991 | static void at91_ts_unregister(struct at91_adc_state *st) |
992 | { |
993 | input_unregister_device(st->ts_input); |
994 | } |
995 | |
996 | static int at91_adc_probe(struct platform_device *pdev) |
997 | { |
998 | unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim; |
999 | struct device_node *node = pdev->dev.of_node; |
1000 | int ret; |
1001 | struct iio_dev *idev; |
1002 | struct at91_adc_state *st; |
1003 | u32 reg, prop; |
1004 | char *s; |
1005 | |
1006 | idev = devm_iio_device_alloc(parent: &pdev->dev, sizeof_priv: sizeof(struct at91_adc_state)); |
1007 | if (!idev) |
1008 | return -ENOMEM; |
1009 | |
1010 | st = iio_priv(indio_dev: idev); |
1011 | |
1012 | st->caps = of_device_get_match_data(dev: &pdev->dev); |
1013 | |
1014 | st->use_external = of_property_read_bool(np: node, propname: "atmel,adc-use-external-triggers" ); |
1015 | |
1016 | if (of_property_read_u32(np: node, propname: "atmel,adc-channels-used" , out_value: &prop)) |
1017 | return dev_err_probe(dev: &idev->dev, err: -EINVAL, |
1018 | fmt: "Missing adc-channels-used property in the DT.\n" ); |
1019 | st->channels_mask = prop; |
1020 | |
1021 | st->sleep_mode = of_property_read_bool(np: node, propname: "atmel,adc-sleep-mode" ); |
1022 | |
1023 | if (of_property_read_u32(np: node, propname: "atmel,adc-startup-time" , out_value: &prop)) |
1024 | return dev_err_probe(dev: &idev->dev, err: -EINVAL, |
1025 | fmt: "Missing adc-startup-time property in the DT.\n" ); |
1026 | st->startup_time = prop; |
1027 | |
1028 | prop = 0; |
1029 | of_property_read_u32(np: node, propname: "atmel,adc-sample-hold-time" , out_value: &prop); |
1030 | st->sample_hold_time = prop; |
1031 | |
1032 | if (of_property_read_u32(np: node, propname: "atmel,adc-vref" , out_value: &prop)) |
1033 | return dev_err_probe(dev: &idev->dev, err: -EINVAL, |
1034 | fmt: "Missing adc-vref property in the DT.\n" ); |
1035 | st->vref_mv = prop; |
1036 | |
1037 | st->res = st->caps->high_res_bits; |
1038 | if (st->caps->low_res_bits && |
1039 | !of_property_read_string(np: node, propname: "atmel,adc-use-res" , out_string: (const char **)&s) |
1040 | && !strcmp(s, "lowres" )) |
1041 | st->res = st->caps->low_res_bits; |
1042 | |
1043 | dev_info(&idev->dev, "Resolution used: %u bits\n" , st->res); |
1044 | |
1045 | st->registers = &st->caps->registers; |
1046 | st->num_channels = st->caps->num_channels; |
1047 | |
1048 | /* Check if touchscreen is supported. */ |
1049 | if (st->caps->has_ts) { |
1050 | ret = at91_adc_probe_dt_ts(node, st, dev: &idev->dev); |
1051 | if (ret) |
1052 | return ret; |
1053 | } |
1054 | |
1055 | platform_set_drvdata(pdev, data: idev); |
1056 | |
1057 | idev->name = dev_name(dev: &pdev->dev); |
1058 | idev->modes = INDIO_DIRECT_MODE; |
1059 | idev->info = &at91_adc_info; |
1060 | |
1061 | st->irq = platform_get_irq(pdev, 0); |
1062 | if (st->irq < 0) |
1063 | return -ENODEV; |
1064 | |
1065 | st->reg_base = devm_platform_ioremap_resource(pdev, index: 0); |
1066 | if (IS_ERR(ptr: st->reg_base)) |
1067 | return PTR_ERR(ptr: st->reg_base); |
1068 | |
1069 | /* |
1070 | * Disable all IRQs before setting up the handler |
1071 | */ |
1072 | at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST); |
1073 | at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF); |
1074 | |
1075 | if (st->caps->has_tsmr) |
1076 | ret = devm_request_irq(dev: &pdev->dev, irq: st->irq, |
1077 | handler: at91_adc_9x5_interrupt, irqflags: 0, |
1078 | devname: pdev->dev.driver->name, dev_id: idev); |
1079 | else |
1080 | ret = devm_request_irq(dev: &pdev->dev, irq: st->irq, |
1081 | handler: at91_adc_rl_interrupt, irqflags: 0, |
1082 | devname: pdev->dev.driver->name, dev_id: idev); |
1083 | if (ret) |
1084 | return dev_err_probe(dev: &pdev->dev, err: ret, |
1085 | fmt: "Failed to allocate IRQ.\n" ); |
1086 | |
1087 | st->clk = devm_clk_get_enabled(dev: &pdev->dev, id: "adc_clk" ); |
1088 | if (IS_ERR(ptr: st->clk)) |
1089 | return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: st->clk), |
1090 | fmt: "Could not prepare or enable the clock.\n" ); |
1091 | |
1092 | st->adc_clk = devm_clk_get_enabled(dev: &pdev->dev, id: "adc_op_clk" ); |
1093 | if (IS_ERR(ptr: st->adc_clk)) |
1094 | return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: st->adc_clk), |
1095 | fmt: "Could not prepare or enable the ADC clock.\n" ); |
1096 | |
1097 | /* |
1098 | * Prescaler rate computation using the formula from the Atmel's |
1099 | * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being |
1100 | * specified by the electrical characteristics of the board. |
1101 | */ |
1102 | mstrclk = clk_get_rate(clk: st->clk); |
1103 | adc_clk = clk_get_rate(clk: st->adc_clk); |
1104 | adc_clk_khz = adc_clk / 1000; |
1105 | |
1106 | dev_dbg(&pdev->dev, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n" , |
1107 | mstrclk, adc_clk); |
1108 | |
1109 | prsc = (mstrclk / (2 * adc_clk)) - 1; |
1110 | |
1111 | if (!st->startup_time) |
1112 | return dev_err_probe(dev: &pdev->dev, err: -EINVAL, |
1113 | fmt: "No startup time available.\n" ); |
1114 | ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz); |
1115 | |
1116 | /* |
1117 | * a minimal Sample and Hold Time is necessary for the ADC to guarantee |
1118 | * the best converted final value between two channels selection |
1119 | * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock |
1120 | */ |
1121 | if (st->sample_hold_time > 0) |
1122 | shtim = round_up((st->sample_hold_time * adc_clk_khz / 1000) |
1123 | - 1, 1); |
1124 | else |
1125 | shtim = 0; |
1126 | |
1127 | reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask; |
1128 | reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask; |
1129 | if (st->res == st->caps->low_res_bits) |
1130 | reg |= AT91_ADC_LOWRES; |
1131 | if (st->sleep_mode) |
1132 | reg |= AT91_ADC_SLEEP; |
1133 | reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM; |
1134 | at91_adc_writel(st, AT91_ADC_MR, reg); |
1135 | |
1136 | /* Setup the ADC channels available on the board */ |
1137 | ret = at91_adc_channel_init(idev); |
1138 | if (ret < 0) |
1139 | return dev_err_probe(dev: &pdev->dev, err: ret, |
1140 | fmt: "Couldn't initialize the channels.\n" ); |
1141 | |
1142 | init_waitqueue_head(&st->wq_data_avail); |
1143 | mutex_init(&st->lock); |
1144 | |
1145 | /* |
1146 | * Since touch screen will set trigger register as period trigger. So |
1147 | * when touch screen is enabled, then we have to disable hardware |
1148 | * trigger for classic adc. |
1149 | */ |
1150 | if (!st->touchscreen_type) { |
1151 | ret = at91_adc_buffer_init(idev); |
1152 | if (ret < 0) |
1153 | return dev_err_probe(dev: &pdev->dev, err: ret, |
1154 | fmt: "Couldn't initialize the buffer.\n" ); |
1155 | |
1156 | ret = at91_adc_trigger_init(idev); |
1157 | if (ret < 0) { |
1158 | dev_err(&pdev->dev, "Couldn't setup the triggers.\n" ); |
1159 | at91_adc_buffer_remove(idev); |
1160 | return ret; |
1161 | } |
1162 | } else { |
1163 | ret = at91_ts_register(idev, pdev); |
1164 | if (ret) |
1165 | return ret; |
1166 | |
1167 | at91_ts_hw_init(idev, adc_clk_khz); |
1168 | } |
1169 | |
1170 | ret = iio_device_register(idev); |
1171 | if (ret < 0) { |
1172 | dev_err(&pdev->dev, "Couldn't register the device.\n" ); |
1173 | goto error_iio_device_register; |
1174 | } |
1175 | |
1176 | return 0; |
1177 | |
1178 | error_iio_device_register: |
1179 | if (!st->touchscreen_type) { |
1180 | at91_adc_trigger_remove(idev); |
1181 | at91_adc_buffer_remove(idev); |
1182 | } else { |
1183 | at91_ts_unregister(st); |
1184 | } |
1185 | return ret; |
1186 | } |
1187 | |
1188 | static void at91_adc_remove(struct platform_device *pdev) |
1189 | { |
1190 | struct iio_dev *idev = platform_get_drvdata(pdev); |
1191 | struct at91_adc_state *st = iio_priv(indio_dev: idev); |
1192 | |
1193 | iio_device_unregister(indio_dev: idev); |
1194 | if (!st->touchscreen_type) { |
1195 | at91_adc_trigger_remove(idev); |
1196 | at91_adc_buffer_remove(idev); |
1197 | } else { |
1198 | at91_ts_unregister(st); |
1199 | } |
1200 | } |
1201 | |
1202 | static int at91_adc_suspend(struct device *dev) |
1203 | { |
1204 | struct iio_dev *idev = dev_get_drvdata(dev); |
1205 | struct at91_adc_state *st = iio_priv(indio_dev: idev); |
1206 | |
1207 | pinctrl_pm_select_sleep_state(dev); |
1208 | clk_disable_unprepare(clk: st->clk); |
1209 | |
1210 | return 0; |
1211 | } |
1212 | |
1213 | static int at91_adc_resume(struct device *dev) |
1214 | { |
1215 | struct iio_dev *idev = dev_get_drvdata(dev); |
1216 | struct at91_adc_state *st = iio_priv(indio_dev: idev); |
1217 | |
1218 | clk_prepare_enable(clk: st->clk); |
1219 | pinctrl_pm_select_default_state(dev); |
1220 | |
1221 | return 0; |
1222 | } |
1223 | |
1224 | static DEFINE_SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, |
1225 | at91_adc_resume); |
1226 | |
1227 | static const struct at91_adc_trigger at91sam9260_triggers[] = { |
1228 | { .name = "timer-counter-0" , .value = 0x1 }, |
1229 | { .name = "timer-counter-1" , .value = 0x3 }, |
1230 | { .name = "timer-counter-2" , .value = 0x5 }, |
1231 | { .name = "external" , .value = 0xd, .is_external = true }, |
1232 | }; |
1233 | |
1234 | static struct at91_adc_caps at91sam9260_caps = { |
1235 | .calc_startup_ticks = calc_startup_ticks_9260, |
1236 | .num_channels = 4, |
1237 | .low_res_bits = 8, |
1238 | .high_res_bits = 10, |
1239 | .registers = { |
1240 | .channel_base = AT91_ADC_CHR(0), |
1241 | .drdy_mask = AT91_ADC_DRDY, |
1242 | .status_register = AT91_ADC_SR, |
1243 | .trigger_register = AT91_ADC_TRGR_9260, |
1244 | .mr_prescal_mask = AT91_ADC_PRESCAL_9260, |
1245 | .mr_startup_mask = AT91_ADC_STARTUP_9260, |
1246 | }, |
1247 | .triggers = at91sam9260_triggers, |
1248 | .trigger_number = ARRAY_SIZE(at91sam9260_triggers), |
1249 | }; |
1250 | |
1251 | static const struct at91_adc_trigger at91sam9x5_triggers[] = { |
1252 | { .name = "external-rising" , .value = 0x1, .is_external = true }, |
1253 | { .name = "external-falling" , .value = 0x2, .is_external = true }, |
1254 | { .name = "external-any" , .value = 0x3, .is_external = true }, |
1255 | { .name = "continuous" , .value = 0x6 }, |
1256 | }; |
1257 | |
1258 | static struct at91_adc_caps at91sam9rl_caps = { |
1259 | .has_ts = true, |
1260 | .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */ |
1261 | .num_channels = 6, |
1262 | .low_res_bits = 8, |
1263 | .high_res_bits = 10, |
1264 | .registers = { |
1265 | .channel_base = AT91_ADC_CHR(0), |
1266 | .drdy_mask = AT91_ADC_DRDY, |
1267 | .status_register = AT91_ADC_SR, |
1268 | .trigger_register = AT91_ADC_TRGR_9G45, |
1269 | .mr_prescal_mask = AT91_ADC_PRESCAL_9260, |
1270 | .mr_startup_mask = AT91_ADC_STARTUP_9G45, |
1271 | }, |
1272 | .triggers = at91sam9x5_triggers, |
1273 | .trigger_number = ARRAY_SIZE(at91sam9x5_triggers), |
1274 | }; |
1275 | |
1276 | static struct at91_adc_caps at91sam9g45_caps = { |
1277 | .has_ts = true, |
1278 | .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */ |
1279 | .num_channels = 8, |
1280 | .low_res_bits = 8, |
1281 | .high_res_bits = 10, |
1282 | .registers = { |
1283 | .channel_base = AT91_ADC_CHR(0), |
1284 | .drdy_mask = AT91_ADC_DRDY, |
1285 | .status_register = AT91_ADC_SR, |
1286 | .trigger_register = AT91_ADC_TRGR_9G45, |
1287 | .mr_prescal_mask = AT91_ADC_PRESCAL_9G45, |
1288 | .mr_startup_mask = AT91_ADC_STARTUP_9G45, |
1289 | }, |
1290 | .triggers = at91sam9x5_triggers, |
1291 | .trigger_number = ARRAY_SIZE(at91sam9x5_triggers), |
1292 | }; |
1293 | |
1294 | static struct at91_adc_caps at91sam9x5_caps = { |
1295 | .has_ts = true, |
1296 | .has_tsmr = true, |
1297 | .ts_filter_average = 3, |
1298 | .ts_pen_detect_sensitivity = 2, |
1299 | .calc_startup_ticks = calc_startup_ticks_9x5, |
1300 | .num_channels = 12, |
1301 | .low_res_bits = 8, |
1302 | .high_res_bits = 10, |
1303 | .registers = { |
1304 | .channel_base = AT91_ADC_CDR0_9X5, |
1305 | .drdy_mask = AT91_ADC_SR_DRDY_9X5, |
1306 | .status_register = AT91_ADC_SR_9X5, |
1307 | .trigger_register = AT91_ADC_TRGR_9X5, |
1308 | /* prescal mask is same as 9G45 */ |
1309 | .mr_prescal_mask = AT91_ADC_PRESCAL_9G45, |
1310 | .mr_startup_mask = AT91_ADC_STARTUP_9X5, |
1311 | }, |
1312 | .triggers = at91sam9x5_triggers, |
1313 | .trigger_number = ARRAY_SIZE(at91sam9x5_triggers), |
1314 | }; |
1315 | |
1316 | static struct at91_adc_caps sama5d3_caps = { |
1317 | .has_ts = true, |
1318 | .has_tsmr = true, |
1319 | .ts_filter_average = 3, |
1320 | .ts_pen_detect_sensitivity = 2, |
1321 | .calc_startup_ticks = calc_startup_ticks_9x5, |
1322 | .num_channels = 12, |
1323 | .low_res_bits = 0, |
1324 | .high_res_bits = 12, |
1325 | .registers = { |
1326 | .channel_base = AT91_ADC_CDR0_9X5, |
1327 | .drdy_mask = AT91_ADC_SR_DRDY_9X5, |
1328 | .status_register = AT91_ADC_SR_9X5, |
1329 | .trigger_register = AT91_ADC_TRGR_9X5, |
1330 | .mr_prescal_mask = AT91_ADC_PRESCAL_9G45, |
1331 | .mr_startup_mask = AT91_ADC_STARTUP_9X5, |
1332 | }, |
1333 | .triggers = at91sam9x5_triggers, |
1334 | .trigger_number = ARRAY_SIZE(at91sam9x5_triggers), |
1335 | }; |
1336 | |
1337 | static const struct of_device_id at91_adc_dt_ids[] = { |
1338 | { .compatible = "atmel,at91sam9260-adc" , .data = &at91sam9260_caps }, |
1339 | { .compatible = "atmel,at91sam9rl-adc" , .data = &at91sam9rl_caps }, |
1340 | { .compatible = "atmel,at91sam9g45-adc" , .data = &at91sam9g45_caps }, |
1341 | { .compatible = "atmel,at91sam9x5-adc" , .data = &at91sam9x5_caps }, |
1342 | { .compatible = "atmel,sama5d3-adc" , .data = &sama5d3_caps }, |
1343 | {}, |
1344 | }; |
1345 | MODULE_DEVICE_TABLE(of, at91_adc_dt_ids); |
1346 | |
1347 | static struct platform_driver at91_adc_driver = { |
1348 | .probe = at91_adc_probe, |
1349 | .remove_new = at91_adc_remove, |
1350 | .driver = { |
1351 | .name = DRIVER_NAME, |
1352 | .of_match_table = at91_adc_dt_ids, |
1353 | .pm = pm_sleep_ptr(&at91_adc_pm_ops), |
1354 | }, |
1355 | }; |
1356 | |
1357 | module_platform_driver(at91_adc_driver); |
1358 | |
1359 | MODULE_LICENSE("GPL" ); |
1360 | MODULE_DESCRIPTION("Atmel AT91 ADC Driver" ); |
1361 | MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>" ); |
1362 | |