1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2014-2015 Imagination Technologies Ltd. |
4 | */ |
5 | |
6 | #include <linux/clk.h> |
7 | #include <linux/delay.h> |
8 | #include <linux/err.h> |
9 | #include <linux/kernel.h> |
10 | #include <linux/module.h> |
11 | #include <linux/of.h> |
12 | #include <linux/platform_device.h> |
13 | #include <linux/regulator/consumer.h> |
14 | #include <linux/slab.h> |
15 | |
16 | #include <linux/iio/buffer.h> |
17 | #include <linux/iio/iio.h> |
18 | #include <linux/iio/sysfs.h> |
19 | #include <linux/iio/trigger.h> |
20 | #include <linux/iio/trigger_consumer.h> |
21 | #include <linux/iio/triggered_buffer.h> |
22 | |
23 | /* Registers */ |
24 | #define CC10001_ADC_CONFIG 0x00 |
25 | #define CC10001_ADC_START_CONV BIT(4) |
26 | #define CC10001_ADC_MODE_SINGLE_CONV BIT(5) |
27 | |
28 | #define CC10001_ADC_DDATA_OUT 0x04 |
29 | #define CC10001_ADC_EOC 0x08 |
30 | #define CC10001_ADC_EOC_SET BIT(0) |
31 | |
32 | #define CC10001_ADC_CHSEL_SAMPLED 0x0c |
33 | #define CC10001_ADC_POWER_DOWN 0x10 |
34 | #define CC10001_ADC_POWER_DOWN_SET BIT(0) |
35 | |
36 | #define CC10001_ADC_DEBUG 0x14 |
37 | #define CC10001_ADC_DATA_COUNT 0x20 |
38 | |
39 | #define CC10001_ADC_DATA_MASK GENMASK(9, 0) |
40 | #define CC10001_ADC_NUM_CHANNELS 8 |
41 | #define CC10001_ADC_CH_MASK GENMASK(2, 0) |
42 | |
43 | #define CC10001_INVALID_SAMPLED 0xffff |
44 | #define CC10001_MAX_POLL_COUNT 20 |
45 | |
46 | /* |
47 | * As per device specification, wait six clock cycles after power-up to |
48 | * activate START. Since adding two more clock cycles delay does not |
49 | * impact the performance too much, we are adding two additional cycles delay |
50 | * intentionally here. |
51 | */ |
52 | #define CC10001_WAIT_CYCLES 8 |
53 | |
54 | struct cc10001_adc_device { |
55 | void __iomem *reg_base; |
56 | struct clk *adc_clk; |
57 | struct regulator *reg; |
58 | u16 *buf; |
59 | |
60 | bool shared; |
61 | struct mutex lock; |
62 | unsigned int start_delay_ns; |
63 | unsigned int eoc_delay_ns; |
64 | }; |
65 | |
66 | static inline void cc10001_adc_write_reg(struct cc10001_adc_device *adc_dev, |
67 | u32 reg, u32 val) |
68 | { |
69 | writel(val, addr: adc_dev->reg_base + reg); |
70 | } |
71 | |
72 | static inline u32 cc10001_adc_read_reg(struct cc10001_adc_device *adc_dev, |
73 | u32 reg) |
74 | { |
75 | return readl(addr: adc_dev->reg_base + reg); |
76 | } |
77 | |
78 | static void cc10001_adc_power_up(struct cc10001_adc_device *adc_dev) |
79 | { |
80 | cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_DOWN, val: 0); |
81 | ndelay(adc_dev->start_delay_ns); |
82 | } |
83 | |
84 | static void cc10001_adc_power_down(struct cc10001_adc_device *adc_dev) |
85 | { |
86 | cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_DOWN, |
87 | CC10001_ADC_POWER_DOWN_SET); |
88 | } |
89 | |
90 | static void cc10001_adc_start(struct cc10001_adc_device *adc_dev, |
91 | unsigned int channel) |
92 | { |
93 | u32 val; |
94 | |
95 | /* Channel selection and mode of operation */ |
96 | val = (channel & CC10001_ADC_CH_MASK) | CC10001_ADC_MODE_SINGLE_CONV; |
97 | cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val); |
98 | |
99 | udelay(1); |
100 | val = cc10001_adc_read_reg(adc_dev, CC10001_ADC_CONFIG); |
101 | val = val | CC10001_ADC_START_CONV; |
102 | cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val); |
103 | } |
104 | |
105 | static u16 cc10001_adc_poll_done(struct iio_dev *indio_dev, |
106 | unsigned int channel, |
107 | unsigned int delay) |
108 | { |
109 | struct cc10001_adc_device *adc_dev = iio_priv(indio_dev); |
110 | unsigned int poll_count = 0; |
111 | |
112 | while (!(cc10001_adc_read_reg(adc_dev, CC10001_ADC_EOC) & |
113 | CC10001_ADC_EOC_SET)) { |
114 | |
115 | ndelay(delay); |
116 | if (poll_count++ == CC10001_MAX_POLL_COUNT) |
117 | return CC10001_INVALID_SAMPLED; |
118 | } |
119 | |
120 | poll_count = 0; |
121 | while ((cc10001_adc_read_reg(adc_dev, CC10001_ADC_CHSEL_SAMPLED) & |
122 | CC10001_ADC_CH_MASK) != channel) { |
123 | |
124 | ndelay(delay); |
125 | if (poll_count++ == CC10001_MAX_POLL_COUNT) |
126 | return CC10001_INVALID_SAMPLED; |
127 | } |
128 | |
129 | /* Read the 10 bit output register */ |
130 | return cc10001_adc_read_reg(adc_dev, CC10001_ADC_DDATA_OUT) & |
131 | CC10001_ADC_DATA_MASK; |
132 | } |
133 | |
134 | static irqreturn_t cc10001_adc_trigger_h(int irq, void *p) |
135 | { |
136 | struct cc10001_adc_device *adc_dev; |
137 | struct iio_poll_func *pf = p; |
138 | struct iio_dev *indio_dev; |
139 | unsigned int delay_ns; |
140 | unsigned int channel; |
141 | unsigned int scan_idx; |
142 | bool sample_invalid; |
143 | u16 *data; |
144 | int i; |
145 | |
146 | indio_dev = pf->indio_dev; |
147 | adc_dev = iio_priv(indio_dev); |
148 | data = adc_dev->buf; |
149 | |
150 | mutex_lock(&adc_dev->lock); |
151 | |
152 | if (!adc_dev->shared) |
153 | cc10001_adc_power_up(adc_dev); |
154 | |
155 | /* Calculate delay step for eoc and sampled data */ |
156 | delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT; |
157 | |
158 | i = 0; |
159 | sample_invalid = false; |
160 | for_each_set_bit(scan_idx, indio_dev->active_scan_mask, |
161 | indio_dev->masklength) { |
162 | |
163 | channel = indio_dev->channels[scan_idx].channel; |
164 | cc10001_adc_start(adc_dev, channel); |
165 | |
166 | data[i] = cc10001_adc_poll_done(indio_dev, channel, delay: delay_ns); |
167 | if (data[i] == CC10001_INVALID_SAMPLED) { |
168 | dev_warn(&indio_dev->dev, |
169 | "invalid sample on channel %d\n" , channel); |
170 | sample_invalid = true; |
171 | goto done; |
172 | } |
173 | i++; |
174 | } |
175 | |
176 | done: |
177 | if (!adc_dev->shared) |
178 | cc10001_adc_power_down(adc_dev); |
179 | |
180 | mutex_unlock(lock: &adc_dev->lock); |
181 | |
182 | if (!sample_invalid) |
183 | iio_push_to_buffers_with_timestamp(indio_dev, data, |
184 | timestamp: iio_get_time_ns(indio_dev)); |
185 | iio_trigger_notify_done(trig: indio_dev->trig); |
186 | |
187 | return IRQ_HANDLED; |
188 | } |
189 | |
190 | static u16 cc10001_adc_read_raw_voltage(struct iio_dev *indio_dev, |
191 | struct iio_chan_spec const *chan) |
192 | { |
193 | struct cc10001_adc_device *adc_dev = iio_priv(indio_dev); |
194 | unsigned int delay_ns; |
195 | u16 val; |
196 | |
197 | if (!adc_dev->shared) |
198 | cc10001_adc_power_up(adc_dev); |
199 | |
200 | /* Calculate delay step for eoc and sampled data */ |
201 | delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT; |
202 | |
203 | cc10001_adc_start(adc_dev, channel: chan->channel); |
204 | |
205 | val = cc10001_adc_poll_done(indio_dev, channel: chan->channel, delay: delay_ns); |
206 | |
207 | if (!adc_dev->shared) |
208 | cc10001_adc_power_down(adc_dev); |
209 | |
210 | return val; |
211 | } |
212 | |
213 | static int cc10001_adc_read_raw(struct iio_dev *indio_dev, |
214 | struct iio_chan_spec const *chan, |
215 | int *val, int *val2, long mask) |
216 | { |
217 | struct cc10001_adc_device *adc_dev = iio_priv(indio_dev); |
218 | int ret; |
219 | |
220 | switch (mask) { |
221 | case IIO_CHAN_INFO_RAW: |
222 | if (iio_buffer_enabled(indio_dev)) |
223 | return -EBUSY; |
224 | mutex_lock(&adc_dev->lock); |
225 | *val = cc10001_adc_read_raw_voltage(indio_dev, chan); |
226 | mutex_unlock(lock: &adc_dev->lock); |
227 | |
228 | if (*val == CC10001_INVALID_SAMPLED) |
229 | return -EIO; |
230 | return IIO_VAL_INT; |
231 | |
232 | case IIO_CHAN_INFO_SCALE: |
233 | ret = regulator_get_voltage(regulator: adc_dev->reg); |
234 | if (ret < 0) |
235 | return ret; |
236 | |
237 | *val = ret / 1000; |
238 | *val2 = chan->scan_type.realbits; |
239 | return IIO_VAL_FRACTIONAL_LOG2; |
240 | |
241 | default: |
242 | return -EINVAL; |
243 | } |
244 | } |
245 | |
246 | static int cc10001_update_scan_mode(struct iio_dev *indio_dev, |
247 | const unsigned long *scan_mask) |
248 | { |
249 | struct cc10001_adc_device *adc_dev = iio_priv(indio_dev); |
250 | |
251 | kfree(objp: adc_dev->buf); |
252 | adc_dev->buf = kmalloc(size: indio_dev->scan_bytes, GFP_KERNEL); |
253 | if (!adc_dev->buf) |
254 | return -ENOMEM; |
255 | |
256 | return 0; |
257 | } |
258 | |
259 | static const struct iio_info cc10001_adc_info = { |
260 | .read_raw = &cc10001_adc_read_raw, |
261 | .update_scan_mode = &cc10001_update_scan_mode, |
262 | }; |
263 | |
264 | static int cc10001_adc_channel_init(struct iio_dev *indio_dev, |
265 | unsigned long channel_map) |
266 | { |
267 | struct iio_chan_spec *chan_array, *timestamp; |
268 | unsigned int bit, idx = 0; |
269 | |
270 | indio_dev->num_channels = bitmap_weight(src: &channel_map, |
271 | CC10001_ADC_NUM_CHANNELS) + 1; |
272 | |
273 | chan_array = devm_kcalloc(dev: &indio_dev->dev, n: indio_dev->num_channels, |
274 | size: sizeof(struct iio_chan_spec), |
275 | GFP_KERNEL); |
276 | if (!chan_array) |
277 | return -ENOMEM; |
278 | |
279 | for_each_set_bit(bit, &channel_map, CC10001_ADC_NUM_CHANNELS) { |
280 | struct iio_chan_spec *chan = &chan_array[idx]; |
281 | |
282 | chan->type = IIO_VOLTAGE; |
283 | chan->indexed = 1; |
284 | chan->channel = bit; |
285 | chan->scan_index = idx; |
286 | chan->scan_type.sign = 'u'; |
287 | chan->scan_type.realbits = 10; |
288 | chan->scan_type.storagebits = 16; |
289 | chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); |
290 | chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); |
291 | idx++; |
292 | } |
293 | |
294 | timestamp = &chan_array[idx]; |
295 | timestamp->type = IIO_TIMESTAMP; |
296 | timestamp->channel = -1; |
297 | timestamp->scan_index = idx; |
298 | timestamp->scan_type.sign = 's'; |
299 | timestamp->scan_type.realbits = 64; |
300 | timestamp->scan_type.storagebits = 64; |
301 | |
302 | indio_dev->channels = chan_array; |
303 | |
304 | return 0; |
305 | } |
306 | |
307 | static void cc10001_reg_disable(void *priv) |
308 | { |
309 | regulator_disable(regulator: priv); |
310 | } |
311 | |
312 | static void cc10001_pd_cb(void *priv) |
313 | { |
314 | cc10001_adc_power_down(adc_dev: priv); |
315 | } |
316 | |
317 | static int cc10001_adc_probe(struct platform_device *pdev) |
318 | { |
319 | struct device *dev = &pdev->dev; |
320 | struct device_node *node = dev->of_node; |
321 | struct cc10001_adc_device *adc_dev; |
322 | unsigned long adc_clk_rate; |
323 | struct iio_dev *indio_dev; |
324 | unsigned long channel_map; |
325 | int ret; |
326 | |
327 | indio_dev = devm_iio_device_alloc(parent: dev, sizeof_priv: sizeof(*adc_dev)); |
328 | if (indio_dev == NULL) |
329 | return -ENOMEM; |
330 | |
331 | adc_dev = iio_priv(indio_dev); |
332 | |
333 | channel_map = GENMASK(CC10001_ADC_NUM_CHANNELS - 1, 0); |
334 | if (!of_property_read_u32(np: node, propname: "adc-reserved-channels" , out_value: &ret)) { |
335 | adc_dev->shared = true; |
336 | channel_map &= ~ret; |
337 | } |
338 | |
339 | adc_dev->reg = devm_regulator_get(dev, id: "vref" ); |
340 | if (IS_ERR(ptr: adc_dev->reg)) |
341 | return PTR_ERR(ptr: adc_dev->reg); |
342 | |
343 | ret = regulator_enable(regulator: adc_dev->reg); |
344 | if (ret) |
345 | return ret; |
346 | |
347 | ret = devm_add_action_or_reset(dev, cc10001_reg_disable, adc_dev->reg); |
348 | if (ret) |
349 | return ret; |
350 | |
351 | indio_dev->name = dev_name(dev); |
352 | indio_dev->info = &cc10001_adc_info; |
353 | indio_dev->modes = INDIO_DIRECT_MODE; |
354 | |
355 | adc_dev->reg_base = devm_platform_ioremap_resource(pdev, index: 0); |
356 | if (IS_ERR(ptr: adc_dev->reg_base)) |
357 | return PTR_ERR(ptr: adc_dev->reg_base); |
358 | |
359 | adc_dev->adc_clk = devm_clk_get_enabled(dev, id: "adc" ); |
360 | if (IS_ERR(ptr: adc_dev->adc_clk)) { |
361 | dev_err(dev, "failed to get/enable the clock\n" ); |
362 | return PTR_ERR(ptr: adc_dev->adc_clk); |
363 | } |
364 | |
365 | adc_clk_rate = clk_get_rate(clk: adc_dev->adc_clk); |
366 | if (!adc_clk_rate) { |
367 | dev_err(dev, "null clock rate!\n" ); |
368 | return -EINVAL; |
369 | } |
370 | |
371 | adc_dev->eoc_delay_ns = NSEC_PER_SEC / adc_clk_rate; |
372 | adc_dev->start_delay_ns = adc_dev->eoc_delay_ns * CC10001_WAIT_CYCLES; |
373 | |
374 | /* |
375 | * There is only one register to power-up/power-down the AUX ADC. |
376 | * If the ADC is shared among multiple CPUs, always power it up here. |
377 | * If the ADC is used only by the MIPS, power-up/power-down at runtime. |
378 | */ |
379 | if (adc_dev->shared) |
380 | cc10001_adc_power_up(adc_dev); |
381 | |
382 | ret = devm_add_action_or_reset(dev, cc10001_pd_cb, adc_dev); |
383 | if (ret) |
384 | return ret; |
385 | /* Setup the ADC channels available on the device */ |
386 | ret = cc10001_adc_channel_init(indio_dev, channel_map); |
387 | if (ret < 0) |
388 | return ret; |
389 | |
390 | mutex_init(&adc_dev->lock); |
391 | |
392 | ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, |
393 | &cc10001_adc_trigger_h, NULL); |
394 | if (ret < 0) |
395 | return ret; |
396 | |
397 | return devm_iio_device_register(dev, indio_dev); |
398 | } |
399 | |
400 | static const struct of_device_id cc10001_adc_dt_ids[] = { |
401 | { .compatible = "cosmic,10001-adc" , }, |
402 | { } |
403 | }; |
404 | MODULE_DEVICE_TABLE(of, cc10001_adc_dt_ids); |
405 | |
406 | static struct platform_driver cc10001_adc_driver = { |
407 | .driver = { |
408 | .name = "cc10001-adc" , |
409 | .of_match_table = cc10001_adc_dt_ids, |
410 | }, |
411 | .probe = cc10001_adc_probe, |
412 | }; |
413 | module_platform_driver(cc10001_adc_driver); |
414 | |
415 | MODULE_AUTHOR("Phani Movva <Phani.Movva@imgtec.com>" ); |
416 | MODULE_DESCRIPTION("Cosmic Circuits ADC driver" ); |
417 | MODULE_LICENSE("GPL v2" ); |
418 | |