1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (C) 2017 Tony Lindgren <tony@atomide.com> |
4 | * |
5 | * Rewritten for Linux IIO framework with some code based on |
6 | * earlier driver found in the Motorola Linux kernel: |
7 | * |
8 | * Copyright (C) 2009-2010 Motorola, Inc. |
9 | */ |
10 | |
11 | #include <linux/delay.h> |
12 | #include <linux/device.h> |
13 | #include <linux/err.h> |
14 | #include <linux/init.h> |
15 | #include <linux/interrupt.h> |
16 | #include <linux/kernel.h> |
17 | #include <linux/module.h> |
18 | #include <linux/mod_devicetable.h> |
19 | #include <linux/platform_device.h> |
20 | #include <linux/property.h> |
21 | #include <linux/regmap.h> |
22 | |
23 | #include <linux/iio/buffer.h> |
24 | #include <linux/iio/driver.h> |
25 | #include <linux/iio/iio.h> |
26 | #include <linux/iio/kfifo_buf.h> |
27 | #include <linux/mfd/motorola-cpcap.h> |
28 | |
29 | /* Register CPCAP_REG_ADCC1 bits */ |
30 | #define CPCAP_BIT_ADEN_AUTO_CLR BIT(15) /* Currently unused */ |
31 | #define CPCAP_BIT_CAL_MODE BIT(14) /* Set with BIT_RAND0 */ |
32 | #define CPCAP_BIT_ADC_CLK_SEL1 BIT(13) /* Currently unused */ |
33 | #define CPCAP_BIT_ADC_CLK_SEL0 BIT(12) /* Currently unused */ |
34 | #define CPCAP_BIT_ATOX BIT(11) |
35 | #define CPCAP_BIT_ATO3 BIT(10) |
36 | #define CPCAP_BIT_ATO2 BIT(9) |
37 | #define CPCAP_BIT_ATO1 BIT(8) |
38 | #define CPCAP_BIT_ATO0 BIT(7) |
39 | #define CPCAP_BIT_ADA2 BIT(6) |
40 | #define CPCAP_BIT_ADA1 BIT(5) |
41 | #define CPCAP_BIT_ADA0 BIT(4) |
42 | #define CPCAP_BIT_AD_SEL1 BIT(3) /* Set for bank1 */ |
43 | #define CPCAP_BIT_RAND1 BIT(2) /* Set for channel 16 & 17 */ |
44 | #define CPCAP_BIT_RAND0 BIT(1) /* Set with CAL_MODE */ |
45 | #define CPCAP_BIT_ADEN BIT(0) /* Currently unused */ |
46 | |
47 | #define CPCAP_REG_ADCC1_DEFAULTS (CPCAP_BIT_ADEN_AUTO_CLR | \ |
48 | CPCAP_BIT_ADC_CLK_SEL0 | \ |
49 | CPCAP_BIT_RAND1) |
50 | |
51 | /* Register CPCAP_REG_ADCC2 bits */ |
52 | #define CPCAP_BIT_CAL_FACTOR_ENABLE BIT(15) /* Currently unused */ |
53 | #define CPCAP_BIT_BATDETB_EN BIT(14) /* Currently unused */ |
54 | #define CPCAP_BIT_ADTRIG_ONESHOT BIT(13) /* Set for !TIMING_IMM */ |
55 | #define CPCAP_BIT_ASC BIT(12) /* Set for TIMING_IMM */ |
56 | #define CPCAP_BIT_ATOX_PS_FACTOR BIT(11) |
57 | #define CPCAP_BIT_ADC_PS_FACTOR1 BIT(10) |
58 | #define CPCAP_BIT_ADC_PS_FACTOR0 BIT(9) |
59 | #define CPCAP_BIT_AD4_SELECT BIT(8) /* Currently unused */ |
60 | #define CPCAP_BIT_ADC_BUSY BIT(7) /* Currently unused */ |
61 | #define CPCAP_BIT_THERMBIAS_EN BIT(6) /* Bias for AD0_BATTDETB */ |
62 | #define CPCAP_BIT_ADTRIG_DIS BIT(5) /* Disable interrupt */ |
63 | #define CPCAP_BIT_LIADC BIT(4) /* Currently unused */ |
64 | #define CPCAP_BIT_TS_REFEN BIT(3) /* Currently unused */ |
65 | #define CPCAP_BIT_TS_M2 BIT(2) /* Currently unused */ |
66 | #define CPCAP_BIT_TS_M1 BIT(1) /* Currently unused */ |
67 | #define CPCAP_BIT_TS_M0 BIT(0) /* Currently unused */ |
68 | |
69 | #define CPCAP_REG_ADCC2_DEFAULTS (CPCAP_BIT_AD4_SELECT | \ |
70 | CPCAP_BIT_ADTRIG_DIS | \ |
71 | CPCAP_BIT_LIADC | \ |
72 | CPCAP_BIT_TS_M2 | \ |
73 | CPCAP_BIT_TS_M1) |
74 | |
75 | #define CPCAP_MAX_TEMP_LVL 27 |
76 | #define CPCAP_FOUR_POINT_TWO_ADC 801 |
77 | #define ST_ADC_CAL_CHRGI_HIGH_THRESHOLD 530 |
78 | #define ST_ADC_CAL_CHRGI_LOW_THRESHOLD 494 |
79 | #define ST_ADC_CAL_BATTI_HIGH_THRESHOLD 530 |
80 | #define ST_ADC_CAL_BATTI_LOW_THRESHOLD 494 |
81 | #define ST_ADC_CALIBRATE_DIFF_THRESHOLD 3 |
82 | |
83 | #define CPCAP_ADC_MAX_RETRIES 5 /* Calibration */ |
84 | |
85 | /* |
86 | * struct cpcap_adc_ato - timing settings for cpcap adc |
87 | * |
88 | * Unfortunately no cpcap documentation available, please document when |
89 | * using these. |
90 | */ |
91 | struct cpcap_adc_ato { |
92 | unsigned short ato_in; |
93 | unsigned short atox_in; |
94 | unsigned short adc_ps_factor_in; |
95 | unsigned short atox_ps_factor_in; |
96 | unsigned short ato_out; |
97 | unsigned short atox_out; |
98 | unsigned short adc_ps_factor_out; |
99 | unsigned short atox_ps_factor_out; |
100 | }; |
101 | |
102 | /** |
103 | * struct cpcap_adc - cpcap adc device driver data |
104 | * @reg: cpcap regmap |
105 | * @dev: struct device |
106 | * @vendor: cpcap vendor |
107 | * @irq: interrupt |
108 | * @lock: mutex |
109 | * @ato: request timings |
110 | * @wq_data_avail: work queue |
111 | * @done: work done |
112 | */ |
113 | struct cpcap_adc { |
114 | struct regmap *reg; |
115 | struct device *dev; |
116 | u16 vendor; |
117 | int irq; |
118 | struct mutex lock; /* ADC register access lock */ |
119 | const struct cpcap_adc_ato *ato; |
120 | wait_queue_head_t wq_data_avail; |
121 | bool done; |
122 | }; |
123 | |
124 | /* |
125 | * enum cpcap_adc_channel - cpcap adc channels |
126 | */ |
127 | enum cpcap_adc_channel { |
128 | /* Bank0 channels */ |
129 | CPCAP_ADC_AD0, /* Battery temperature */ |
130 | CPCAP_ADC_BATTP, /* Battery voltage */ |
131 | CPCAP_ADC_VBUS, /* USB VBUS voltage */ |
132 | CPCAP_ADC_AD3, /* Die temperature when charging */ |
133 | CPCAP_ADC_BPLUS_AD4, /* Another battery or system voltage */ |
134 | CPCAP_ADC_CHG_ISENSE, /* Calibrated charge current */ |
135 | CPCAP_ADC_BATTI, /* Calibrated system current */ |
136 | CPCAP_ADC_USB_ID, /* USB OTG ID, unused on droid 4? */ |
137 | |
138 | /* Bank1 channels */ |
139 | CPCAP_ADC_AD8, /* Seems unused */ |
140 | CPCAP_ADC_AD9, /* Seems unused */ |
141 | CPCAP_ADC_LICELL, /* Maybe system voltage? Always 3V */ |
142 | CPCAP_ADC_HV_BATTP, /* Another battery detection? */ |
143 | CPCAP_ADC_TSX1_AD12, /* Seems unused, for touchscreen? */ |
144 | CPCAP_ADC_TSX2_AD13, /* Seems unused, for touchscreen? */ |
145 | CPCAP_ADC_TSY1_AD14, /* Seems unused, for touchscreen? */ |
146 | CPCAP_ADC_TSY2_AD15, /* Seems unused, for touchscreen? */ |
147 | |
148 | /* Remuxed channels using bank0 entries */ |
149 | CPCAP_ADC_BATTP_PI16, /* Alternative mux mode for BATTP */ |
150 | CPCAP_ADC_BATTI_PI17, /* Alternative mux mode for BATTI */ |
151 | |
152 | CPCAP_ADC_CHANNEL_NUM, |
153 | }; |
154 | |
155 | /* |
156 | * enum cpcap_adc_timing - cpcap adc timing options |
157 | * |
158 | * CPCAP_ADC_TIMING_IMM seems to be immediate with no timings. |
159 | * Please document when using. |
160 | */ |
161 | enum cpcap_adc_timing { |
162 | CPCAP_ADC_TIMING_IMM, |
163 | CPCAP_ADC_TIMING_IN, |
164 | CPCAP_ADC_TIMING_OUT, |
165 | }; |
166 | |
167 | /** |
168 | * struct cpcap_adc_phasing_tbl - cpcap phasing table |
169 | * @offset: offset in the phasing table |
170 | * @multiplier: multiplier in the phasing table |
171 | * @divider: divider in the phasing table |
172 | * @min: minimum value |
173 | * @max: maximum value |
174 | */ |
175 | struct cpcap_adc_phasing_tbl { |
176 | short offset; |
177 | unsigned short multiplier; |
178 | unsigned short divider; |
179 | short min; |
180 | short max; |
181 | }; |
182 | |
183 | /** |
184 | * struct cpcap_adc_conversion_tbl - cpcap conversion table |
185 | * @conv_type: conversion type |
186 | * @align_offset: align offset |
187 | * @conv_offset: conversion offset |
188 | * @cal_offset: calibration offset |
189 | * @multiplier: conversion multiplier |
190 | * @divider: conversion divider |
191 | */ |
192 | struct cpcap_adc_conversion_tbl { |
193 | enum iio_chan_info_enum conv_type; |
194 | int align_offset; |
195 | int conv_offset; |
196 | int cal_offset; |
197 | int multiplier; |
198 | int divider; |
199 | }; |
200 | |
201 | /** |
202 | * struct cpcap_adc_request - cpcap adc request |
203 | * @channel: request channel |
204 | * @phase_tbl: channel phasing table |
205 | * @conv_tbl: channel conversion table |
206 | * @bank_index: channel index within the bank |
207 | * @timing: timing settings |
208 | * @result: result |
209 | */ |
210 | struct cpcap_adc_request { |
211 | int channel; |
212 | const struct cpcap_adc_phasing_tbl *phase_tbl; |
213 | const struct cpcap_adc_conversion_tbl *conv_tbl; |
214 | int bank_index; |
215 | enum cpcap_adc_timing timing; |
216 | int result; |
217 | }; |
218 | |
219 | /* Phasing table for channels. Note that channels 16 & 17 use BATTP and BATTI */ |
220 | static const struct cpcap_adc_phasing_tbl bank_phasing[] = { |
221 | /* Bank0 */ |
222 | [CPCAP_ADC_AD0] = {.offset: 0, .multiplier: 0x80, .divider: 0x80, .min: 0, .max: 1023}, |
223 | [CPCAP_ADC_BATTP] = {.offset: 0, .multiplier: 0x80, .divider: 0x80, .min: 0, .max: 1023}, |
224 | [CPCAP_ADC_VBUS] = {.offset: 0, .multiplier: 0x80, .divider: 0x80, .min: 0, .max: 1023}, |
225 | [CPCAP_ADC_AD3] = {.offset: 0, .multiplier: 0x80, .divider: 0x80, .min: 0, .max: 1023}, |
226 | [CPCAP_ADC_BPLUS_AD4] = {.offset: 0, .multiplier: 0x80, .divider: 0x80, .min: 0, .max: 1023}, |
227 | [CPCAP_ADC_CHG_ISENSE] = {.offset: 0, .multiplier: 0x80, .divider: 0x80, .min: -512, .max: 511}, |
228 | [CPCAP_ADC_BATTI] = {.offset: 0, .multiplier: 0x80, .divider: 0x80, .min: -512, .max: 511}, |
229 | [CPCAP_ADC_USB_ID] = {.offset: 0, .multiplier: 0x80, .divider: 0x80, .min: 0, .max: 1023}, |
230 | |
231 | /* Bank1 */ |
232 | [CPCAP_ADC_AD8] = {.offset: 0, .multiplier: 0x80, .divider: 0x80, .min: 0, .max: 1023}, |
233 | [CPCAP_ADC_AD9] = {.offset: 0, .multiplier: 0x80, .divider: 0x80, .min: 0, .max: 1023}, |
234 | [CPCAP_ADC_LICELL] = {.offset: 0, .multiplier: 0x80, .divider: 0x80, .min: 0, .max: 1023}, |
235 | [CPCAP_ADC_HV_BATTP] = {.offset: 0, .multiplier: 0x80, .divider: 0x80, .min: 0, .max: 1023}, |
236 | [CPCAP_ADC_TSX1_AD12] = {.offset: 0, .multiplier: 0x80, .divider: 0x80, .min: 0, .max: 1023}, |
237 | [CPCAP_ADC_TSX2_AD13] = {.offset: 0, .multiplier: 0x80, .divider: 0x80, .min: 0, .max: 1023}, |
238 | [CPCAP_ADC_TSY1_AD14] = {.offset: 0, .multiplier: 0x80, .divider: 0x80, .min: 0, .max: 1023}, |
239 | [CPCAP_ADC_TSY2_AD15] = {.offset: 0, .multiplier: 0x80, .divider: 0x80, .min: 0, .max: 1023}, |
240 | }; |
241 | |
242 | /* |
243 | * Conversion table for channels. Updated during init based on calibration. |
244 | * Here too channels 16 & 17 use BATTP and BATTI. |
245 | */ |
246 | static struct cpcap_adc_conversion_tbl bank_conversion[] = { |
247 | /* Bank0 */ |
248 | [CPCAP_ADC_AD0] = { |
249 | .conv_type: IIO_CHAN_INFO_PROCESSED, .align_offset: 0, .conv_offset: 0, .cal_offset: 0, .multiplier: 1, .divider: 1, |
250 | }, |
251 | [CPCAP_ADC_BATTP] = { |
252 | .conv_type: IIO_CHAN_INFO_PROCESSED, .align_offset: 0, .conv_offset: 2400, .cal_offset: 0, .multiplier: 2300, .divider: 1023, |
253 | }, |
254 | [CPCAP_ADC_VBUS] = { |
255 | .conv_type: IIO_CHAN_INFO_PROCESSED, .align_offset: 0, .conv_offset: 0, .cal_offset: 0, .multiplier: 10000, .divider: 1023, |
256 | }, |
257 | [CPCAP_ADC_AD3] = { |
258 | .conv_type: IIO_CHAN_INFO_PROCESSED, .align_offset: 0, .conv_offset: 0, .cal_offset: 0, .multiplier: 1, .divider: 1, |
259 | }, |
260 | [CPCAP_ADC_BPLUS_AD4] = { |
261 | .conv_type: IIO_CHAN_INFO_PROCESSED, .align_offset: 0, .conv_offset: 2400, .cal_offset: 0, .multiplier: 2300, .divider: 1023, |
262 | }, |
263 | [CPCAP_ADC_CHG_ISENSE] = { |
264 | .conv_type: IIO_CHAN_INFO_PROCESSED, .align_offset: -512, .conv_offset: 2, .cal_offset: 0, .multiplier: 5000, .divider: 1023, |
265 | }, |
266 | [CPCAP_ADC_BATTI] = { |
267 | .conv_type: IIO_CHAN_INFO_PROCESSED, .align_offset: -512, .conv_offset: 2, .cal_offset: 0, .multiplier: 5000, .divider: 1023, |
268 | }, |
269 | [CPCAP_ADC_USB_ID] = { |
270 | .conv_type: IIO_CHAN_INFO_RAW, .align_offset: 0, .conv_offset: 0, .cal_offset: 0, .multiplier: 1, .divider: 1, |
271 | }, |
272 | |
273 | /* Bank1 */ |
274 | [CPCAP_ADC_AD8] = { |
275 | .conv_type: IIO_CHAN_INFO_RAW, .align_offset: 0, .conv_offset: 0, .cal_offset: 0, .multiplier: 1, .divider: 1, |
276 | }, |
277 | [CPCAP_ADC_AD9] = { |
278 | .conv_type: IIO_CHAN_INFO_RAW, .align_offset: 0, .conv_offset: 0, .cal_offset: 0, .multiplier: 1, .divider: 1, |
279 | }, |
280 | [CPCAP_ADC_LICELL] = { |
281 | .conv_type: IIO_CHAN_INFO_PROCESSED, .align_offset: 0, .conv_offset: 0, .cal_offset: 0, .multiplier: 3400, .divider: 1023, |
282 | }, |
283 | [CPCAP_ADC_HV_BATTP] = { |
284 | .conv_type: IIO_CHAN_INFO_RAW, .align_offset: 0, .conv_offset: 0, .cal_offset: 0, .multiplier: 1, .divider: 1, |
285 | }, |
286 | [CPCAP_ADC_TSX1_AD12] = { |
287 | .conv_type: IIO_CHAN_INFO_RAW, .align_offset: 0, .conv_offset: 0, .cal_offset: 0, .multiplier: 1, .divider: 1, |
288 | }, |
289 | [CPCAP_ADC_TSX2_AD13] = { |
290 | .conv_type: IIO_CHAN_INFO_RAW, .align_offset: 0, .conv_offset: 0, .cal_offset: 0, .multiplier: 1, .divider: 1, |
291 | }, |
292 | [CPCAP_ADC_TSY1_AD14] = { |
293 | .conv_type: IIO_CHAN_INFO_RAW, .align_offset: 0, .conv_offset: 0, .cal_offset: 0, .multiplier: 1, .divider: 1, |
294 | }, |
295 | [CPCAP_ADC_TSY2_AD15] = { |
296 | .conv_type: IIO_CHAN_INFO_RAW, .align_offset: 0, .conv_offset: 0, .cal_offset: 0, .multiplier: 1, .divider: 1, |
297 | }, |
298 | }; |
299 | |
300 | /* |
301 | * Temperature lookup table of register values to milliCelcius. |
302 | * REVISIT: Check the duplicate 0x3ff entry in a freezer |
303 | */ |
304 | static const int temp_map[CPCAP_MAX_TEMP_LVL][2] = { |
305 | { 0x03ff, -40000 }, |
306 | { 0x03ff, -35000 }, |
307 | { 0x03ef, -30000 }, |
308 | { 0x03b2, -25000 }, |
309 | { 0x036c, -20000 }, |
310 | { 0x0320, -15000 }, |
311 | { 0x02d0, -10000 }, |
312 | { 0x027f, -5000 }, |
313 | { 0x022f, 0 }, |
314 | { 0x01e4, 5000 }, |
315 | { 0x019f, 10000 }, |
316 | { 0x0161, 15000 }, |
317 | { 0x012b, 20000 }, |
318 | { 0x00fc, 25000 }, |
319 | { 0x00d4, 30000 }, |
320 | { 0x00b2, 35000 }, |
321 | { 0x0095, 40000 }, |
322 | { 0x007d, 45000 }, |
323 | { 0x0069, 50000 }, |
324 | { 0x0059, 55000 }, |
325 | { 0x004b, 60000 }, |
326 | { 0x003f, 65000 }, |
327 | { 0x0036, 70000 }, |
328 | { 0x002e, 75000 }, |
329 | { 0x0027, 80000 }, |
330 | { 0x0022, 85000 }, |
331 | { 0x001d, 90000 }, |
332 | }; |
333 | |
334 | #define CPCAP_CHAN(_type, _index, _address, _datasheet_name) { \ |
335 | .type = (_type), \ |
336 | .address = (_address), \ |
337 | .indexed = 1, \ |
338 | .channel = (_index), \ |
339 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ |
340 | BIT(IIO_CHAN_INFO_PROCESSED), \ |
341 | .scan_index = (_index), \ |
342 | .scan_type = { \ |
343 | .sign = 'u', \ |
344 | .realbits = 10, \ |
345 | .storagebits = 16, \ |
346 | .endianness = IIO_CPU, \ |
347 | }, \ |
348 | .datasheet_name = (_datasheet_name), \ |
349 | } |
350 | |
351 | /* |
352 | * The datasheet names are from Motorola mapphone Linux kernel except |
353 | * for the last two which might be uncalibrated charge voltage and |
354 | * current. |
355 | */ |
356 | static const struct iio_chan_spec cpcap_adc_channels[] = { |
357 | /* Bank0 */ |
358 | CPCAP_CHAN(IIO_TEMP, 0, CPCAP_REG_ADCD0, "battdetb" ), |
359 | CPCAP_CHAN(IIO_VOLTAGE, 1, CPCAP_REG_ADCD1, "battp" ), |
360 | CPCAP_CHAN(IIO_VOLTAGE, 2, CPCAP_REG_ADCD2, "vbus" ), |
361 | CPCAP_CHAN(IIO_TEMP, 3, CPCAP_REG_ADCD3, "ad3" ), |
362 | CPCAP_CHAN(IIO_VOLTAGE, 4, CPCAP_REG_ADCD4, "ad4" ), |
363 | CPCAP_CHAN(IIO_CURRENT, 5, CPCAP_REG_ADCD5, "chg_isense" ), |
364 | CPCAP_CHAN(IIO_CURRENT, 6, CPCAP_REG_ADCD6, "batti" ), |
365 | CPCAP_CHAN(IIO_VOLTAGE, 7, CPCAP_REG_ADCD7, "usb_id" ), |
366 | |
367 | /* Bank1 */ |
368 | CPCAP_CHAN(IIO_CURRENT, 8, CPCAP_REG_ADCD0, "ad8" ), |
369 | CPCAP_CHAN(IIO_VOLTAGE, 9, CPCAP_REG_ADCD1, "ad9" ), |
370 | CPCAP_CHAN(IIO_VOLTAGE, 10, CPCAP_REG_ADCD2, "licell" ), |
371 | CPCAP_CHAN(IIO_VOLTAGE, 11, CPCAP_REG_ADCD3, "hv_battp" ), |
372 | CPCAP_CHAN(IIO_VOLTAGE, 12, CPCAP_REG_ADCD4, "tsx1_ad12" ), |
373 | CPCAP_CHAN(IIO_VOLTAGE, 13, CPCAP_REG_ADCD5, "tsx2_ad13" ), |
374 | CPCAP_CHAN(IIO_VOLTAGE, 14, CPCAP_REG_ADCD6, "tsy1_ad14" ), |
375 | CPCAP_CHAN(IIO_VOLTAGE, 15, CPCAP_REG_ADCD7, "tsy2_ad15" ), |
376 | |
377 | /* There are two registers with multiplexed functionality */ |
378 | CPCAP_CHAN(IIO_VOLTAGE, 16, CPCAP_REG_ADCD0, "chg_vsense" ), |
379 | CPCAP_CHAN(IIO_CURRENT, 17, CPCAP_REG_ADCD1, "batti2" ), |
380 | }; |
381 | |
382 | static irqreturn_t cpcap_adc_irq_thread(int irq, void *data) |
383 | { |
384 | struct iio_dev *indio_dev = data; |
385 | struct cpcap_adc *ddata = iio_priv(indio_dev); |
386 | int error; |
387 | |
388 | error = regmap_update_bits(map: ddata->reg, CPCAP_REG_ADCC2, |
389 | CPCAP_BIT_ADTRIG_DIS, |
390 | CPCAP_BIT_ADTRIG_DIS); |
391 | if (error) |
392 | return IRQ_NONE; |
393 | |
394 | ddata->done = true; |
395 | wake_up_interruptible(&ddata->wq_data_avail); |
396 | |
397 | return IRQ_HANDLED; |
398 | } |
399 | |
400 | /* ADC calibration functions */ |
401 | static void cpcap_adc_setup_calibrate(struct cpcap_adc *ddata, |
402 | enum cpcap_adc_channel chan) |
403 | { |
404 | unsigned int value = 0; |
405 | unsigned long timeout = jiffies + msecs_to_jiffies(m: 3000); |
406 | int error; |
407 | |
408 | if ((chan != CPCAP_ADC_CHG_ISENSE) && |
409 | (chan != CPCAP_ADC_BATTI)) |
410 | return; |
411 | |
412 | value |= CPCAP_BIT_CAL_MODE | CPCAP_BIT_RAND0; |
413 | value |= ((chan << 4) & |
414 | (CPCAP_BIT_ADA2 | CPCAP_BIT_ADA1 | CPCAP_BIT_ADA0)); |
415 | |
416 | error = regmap_update_bits(map: ddata->reg, CPCAP_REG_ADCC1, |
417 | CPCAP_BIT_CAL_MODE | CPCAP_BIT_ATOX | |
418 | CPCAP_BIT_ATO3 | CPCAP_BIT_ATO2 | |
419 | CPCAP_BIT_ATO1 | CPCAP_BIT_ATO0 | |
420 | CPCAP_BIT_ADA2 | CPCAP_BIT_ADA1 | |
421 | CPCAP_BIT_ADA0 | CPCAP_BIT_AD_SEL1 | |
422 | CPCAP_BIT_RAND1 | CPCAP_BIT_RAND0, |
423 | val: value); |
424 | if (error) |
425 | return; |
426 | |
427 | error = regmap_update_bits(map: ddata->reg, CPCAP_REG_ADCC2, |
428 | CPCAP_BIT_ATOX_PS_FACTOR | |
429 | CPCAP_BIT_ADC_PS_FACTOR1 | |
430 | CPCAP_BIT_ADC_PS_FACTOR0, |
431 | val: 0); |
432 | if (error) |
433 | return; |
434 | |
435 | error = regmap_update_bits(map: ddata->reg, CPCAP_REG_ADCC2, |
436 | CPCAP_BIT_ADTRIG_DIS, |
437 | CPCAP_BIT_ADTRIG_DIS); |
438 | if (error) |
439 | return; |
440 | |
441 | error = regmap_update_bits(map: ddata->reg, CPCAP_REG_ADCC2, |
442 | CPCAP_BIT_ASC, |
443 | CPCAP_BIT_ASC); |
444 | if (error) |
445 | return; |
446 | |
447 | do { |
448 | schedule_timeout_uninterruptible(timeout: 1); |
449 | error = regmap_read(map: ddata->reg, CPCAP_REG_ADCC2, val: &value); |
450 | if (error) |
451 | return; |
452 | } while ((value & CPCAP_BIT_ASC) && time_before(jiffies, timeout)); |
453 | |
454 | if (value & CPCAP_BIT_ASC) |
455 | dev_err(ddata->dev, |
456 | "Timeout waiting for calibration to complete\n" ); |
457 | |
458 | error = regmap_update_bits(map: ddata->reg, CPCAP_REG_ADCC1, |
459 | CPCAP_BIT_CAL_MODE, val: 0); |
460 | if (error) |
461 | return; |
462 | } |
463 | |
464 | static int cpcap_adc_calibrate_one(struct cpcap_adc *ddata, |
465 | int channel, |
466 | u16 calibration_register, |
467 | int lower_threshold, |
468 | int upper_threshold) |
469 | { |
470 | unsigned int calibration_data[2]; |
471 | unsigned short cal_data_diff; |
472 | int i, error; |
473 | |
474 | for (i = 0; i < CPCAP_ADC_MAX_RETRIES; i++) { |
475 | calibration_data[0] = 0; |
476 | calibration_data[1] = 0; |
477 | |
478 | cpcap_adc_setup_calibrate(ddata, chan: channel); |
479 | error = regmap_read(map: ddata->reg, reg: calibration_register, |
480 | val: &calibration_data[0]); |
481 | if (error) |
482 | return error; |
483 | cpcap_adc_setup_calibrate(ddata, chan: channel); |
484 | error = regmap_read(map: ddata->reg, reg: calibration_register, |
485 | val: &calibration_data[1]); |
486 | if (error) |
487 | return error; |
488 | |
489 | if (calibration_data[0] > calibration_data[1]) |
490 | cal_data_diff = |
491 | calibration_data[0] - calibration_data[1]; |
492 | else |
493 | cal_data_diff = |
494 | calibration_data[1] - calibration_data[0]; |
495 | |
496 | if (((calibration_data[1] >= lower_threshold) && |
497 | (calibration_data[1] <= upper_threshold) && |
498 | (cal_data_diff <= ST_ADC_CALIBRATE_DIFF_THRESHOLD)) || |
499 | (ddata->vendor == CPCAP_VENDOR_TI)) { |
500 | bank_conversion[channel].cal_offset = |
501 | ((short)calibration_data[1] * -1) + 512; |
502 | dev_dbg(ddata->dev, "ch%i calibration complete: %i\n" , |
503 | channel, bank_conversion[channel].cal_offset); |
504 | break; |
505 | } |
506 | usleep_range(min: 5000, max: 10000); |
507 | } |
508 | |
509 | return 0; |
510 | } |
511 | |
512 | static int cpcap_adc_calibrate(struct cpcap_adc *ddata) |
513 | { |
514 | int error; |
515 | |
516 | error = cpcap_adc_calibrate_one(ddata, channel: CPCAP_ADC_CHG_ISENSE, |
517 | CPCAP_REG_ADCAL1, |
518 | ST_ADC_CAL_CHRGI_LOW_THRESHOLD, |
519 | ST_ADC_CAL_CHRGI_HIGH_THRESHOLD); |
520 | if (error) |
521 | return error; |
522 | |
523 | error = cpcap_adc_calibrate_one(ddata, channel: CPCAP_ADC_BATTI, |
524 | CPCAP_REG_ADCAL2, |
525 | ST_ADC_CAL_BATTI_LOW_THRESHOLD, |
526 | ST_ADC_CAL_BATTI_HIGH_THRESHOLD); |
527 | if (error) |
528 | return error; |
529 | |
530 | return 0; |
531 | } |
532 | |
533 | /* ADC setup, read and scale functions */ |
534 | static void cpcap_adc_setup_bank(struct cpcap_adc *ddata, |
535 | struct cpcap_adc_request *req) |
536 | { |
537 | const struct cpcap_adc_ato *ato = ddata->ato; |
538 | unsigned short value1 = 0; |
539 | unsigned short value2 = 0; |
540 | int error; |
541 | |
542 | if (!ato) |
543 | return; |
544 | |
545 | switch (req->channel) { |
546 | case CPCAP_ADC_AD0: |
547 | value2 |= CPCAP_BIT_THERMBIAS_EN; |
548 | error = regmap_update_bits(map: ddata->reg, CPCAP_REG_ADCC2, |
549 | CPCAP_BIT_THERMBIAS_EN, |
550 | val: value2); |
551 | if (error) |
552 | return; |
553 | usleep_range(min: 800, max: 1000); |
554 | break; |
555 | case CPCAP_ADC_AD8 ... CPCAP_ADC_TSY2_AD15: |
556 | value1 |= CPCAP_BIT_AD_SEL1; |
557 | break; |
558 | case CPCAP_ADC_BATTP_PI16 ... CPCAP_ADC_BATTI_PI17: |
559 | value1 |= CPCAP_BIT_RAND1; |
560 | break; |
561 | default: |
562 | break; |
563 | } |
564 | |
565 | switch (req->timing) { |
566 | case CPCAP_ADC_TIMING_IN: |
567 | value1 |= ato->ato_in; |
568 | value1 |= ato->atox_in; |
569 | value2 |= ato->adc_ps_factor_in; |
570 | value2 |= ato->atox_ps_factor_in; |
571 | break; |
572 | case CPCAP_ADC_TIMING_OUT: |
573 | value1 |= ato->ato_out; |
574 | value1 |= ato->atox_out; |
575 | value2 |= ato->adc_ps_factor_out; |
576 | value2 |= ato->atox_ps_factor_out; |
577 | break; |
578 | |
579 | case CPCAP_ADC_TIMING_IMM: |
580 | default: |
581 | break; |
582 | } |
583 | |
584 | error = regmap_update_bits(map: ddata->reg, CPCAP_REG_ADCC1, |
585 | CPCAP_BIT_CAL_MODE | CPCAP_BIT_ATOX | |
586 | CPCAP_BIT_ATO3 | CPCAP_BIT_ATO2 | |
587 | CPCAP_BIT_ATO1 | CPCAP_BIT_ATO0 | |
588 | CPCAP_BIT_ADA2 | CPCAP_BIT_ADA1 | |
589 | CPCAP_BIT_ADA0 | CPCAP_BIT_AD_SEL1 | |
590 | CPCAP_BIT_RAND1 | CPCAP_BIT_RAND0, |
591 | val: value1); |
592 | if (error) |
593 | return; |
594 | |
595 | error = regmap_update_bits(map: ddata->reg, CPCAP_REG_ADCC2, |
596 | CPCAP_BIT_ATOX_PS_FACTOR | |
597 | CPCAP_BIT_ADC_PS_FACTOR1 | |
598 | CPCAP_BIT_ADC_PS_FACTOR0 | |
599 | CPCAP_BIT_THERMBIAS_EN, |
600 | val: value2); |
601 | if (error) |
602 | return; |
603 | |
604 | if (req->timing == CPCAP_ADC_TIMING_IMM) { |
605 | error = regmap_update_bits(map: ddata->reg, CPCAP_REG_ADCC2, |
606 | CPCAP_BIT_ADTRIG_DIS, |
607 | CPCAP_BIT_ADTRIG_DIS); |
608 | if (error) |
609 | return; |
610 | |
611 | error = regmap_update_bits(map: ddata->reg, CPCAP_REG_ADCC2, |
612 | CPCAP_BIT_ASC, |
613 | CPCAP_BIT_ASC); |
614 | if (error) |
615 | return; |
616 | } else { |
617 | error = regmap_update_bits(map: ddata->reg, CPCAP_REG_ADCC2, |
618 | CPCAP_BIT_ADTRIG_ONESHOT, |
619 | CPCAP_BIT_ADTRIG_ONESHOT); |
620 | if (error) |
621 | return; |
622 | |
623 | error = regmap_update_bits(map: ddata->reg, CPCAP_REG_ADCC2, |
624 | CPCAP_BIT_ADTRIG_DIS, val: 0); |
625 | if (error) |
626 | return; |
627 | } |
628 | } |
629 | |
630 | static int cpcap_adc_start_bank(struct cpcap_adc *ddata, |
631 | struct cpcap_adc_request *req) |
632 | { |
633 | int i, error; |
634 | |
635 | req->timing = CPCAP_ADC_TIMING_IMM; |
636 | ddata->done = false; |
637 | |
638 | for (i = 0; i < CPCAP_ADC_MAX_RETRIES; i++) { |
639 | cpcap_adc_setup_bank(ddata, req); |
640 | error = wait_event_interruptible_timeout(ddata->wq_data_avail, |
641 | ddata->done, |
642 | msecs_to_jiffies(50)); |
643 | if (error > 0) |
644 | return 0; |
645 | |
646 | if (error == 0) { |
647 | error = -ETIMEDOUT; |
648 | continue; |
649 | } |
650 | |
651 | if (error < 0) |
652 | return error; |
653 | } |
654 | |
655 | return error; |
656 | } |
657 | |
658 | static int cpcap_adc_stop_bank(struct cpcap_adc *ddata) |
659 | { |
660 | int error; |
661 | |
662 | error = regmap_update_bits(map: ddata->reg, CPCAP_REG_ADCC1, |
663 | mask: 0xffff, |
664 | CPCAP_REG_ADCC1_DEFAULTS); |
665 | if (error) |
666 | return error; |
667 | |
668 | return regmap_update_bits(map: ddata->reg, CPCAP_REG_ADCC2, |
669 | mask: 0xffff, |
670 | CPCAP_REG_ADCC2_DEFAULTS); |
671 | } |
672 | |
673 | static void cpcap_adc_phase(struct cpcap_adc_request *req) |
674 | { |
675 | const struct cpcap_adc_conversion_tbl *conv_tbl = req->conv_tbl; |
676 | const struct cpcap_adc_phasing_tbl *phase_tbl = req->phase_tbl; |
677 | int index = req->channel; |
678 | |
679 | /* Remuxed channels 16 and 17 use BATTP and BATTI entries */ |
680 | switch (req->channel) { |
681 | case CPCAP_ADC_BATTP: |
682 | case CPCAP_ADC_BATTP_PI16: |
683 | index = req->bank_index; |
684 | req->result -= phase_tbl[index].offset; |
685 | req->result -= CPCAP_FOUR_POINT_TWO_ADC; |
686 | req->result *= phase_tbl[index].multiplier; |
687 | if (phase_tbl[index].divider == 0) |
688 | return; |
689 | req->result /= phase_tbl[index].divider; |
690 | req->result += CPCAP_FOUR_POINT_TWO_ADC; |
691 | break; |
692 | case CPCAP_ADC_BATTI_PI17: |
693 | index = req->bank_index; |
694 | fallthrough; |
695 | default: |
696 | req->result += conv_tbl[index].cal_offset; |
697 | req->result += conv_tbl[index].align_offset; |
698 | req->result *= phase_tbl[index].multiplier; |
699 | if (phase_tbl[index].divider == 0) |
700 | return; |
701 | req->result /= phase_tbl[index].divider; |
702 | req->result += phase_tbl[index].offset; |
703 | break; |
704 | } |
705 | |
706 | if (req->result < phase_tbl[index].min) |
707 | req->result = phase_tbl[index].min; |
708 | else if (req->result > phase_tbl[index].max) |
709 | req->result = phase_tbl[index].max; |
710 | } |
711 | |
712 | /* Looks up temperatures in a table and calculates averages if needed */ |
713 | static int cpcap_adc_table_to_millicelcius(unsigned short value) |
714 | { |
715 | int i, result = 0, alpha; |
716 | |
717 | if (value <= temp_map[CPCAP_MAX_TEMP_LVL - 1][0]) |
718 | return temp_map[CPCAP_MAX_TEMP_LVL - 1][1]; |
719 | |
720 | if (value >= temp_map[0][0]) |
721 | return temp_map[0][1]; |
722 | |
723 | for (i = 0; i < CPCAP_MAX_TEMP_LVL - 1; i++) { |
724 | if ((value <= temp_map[i][0]) && |
725 | (value >= temp_map[i + 1][0])) { |
726 | if (value == temp_map[i][0]) { |
727 | result = temp_map[i][1]; |
728 | } else if (value == temp_map[i + 1][0]) { |
729 | result = temp_map[i + 1][1]; |
730 | } else { |
731 | alpha = ((value - temp_map[i][0]) * 1000) / |
732 | (temp_map[i + 1][0] - temp_map[i][0]); |
733 | |
734 | result = temp_map[i][1] + |
735 | ((alpha * (temp_map[i + 1][1] - |
736 | temp_map[i][1])) / 1000); |
737 | } |
738 | break; |
739 | } |
740 | } |
741 | |
742 | return result; |
743 | } |
744 | |
745 | static void cpcap_adc_convert(struct cpcap_adc_request *req) |
746 | { |
747 | const struct cpcap_adc_conversion_tbl *conv_tbl = req->conv_tbl; |
748 | int index = req->channel; |
749 | |
750 | /* Remuxed channels 16 and 17 use BATTP and BATTI entries */ |
751 | switch (req->channel) { |
752 | case CPCAP_ADC_BATTP_PI16: |
753 | index = CPCAP_ADC_BATTP; |
754 | break; |
755 | case CPCAP_ADC_BATTI_PI17: |
756 | index = CPCAP_ADC_BATTI; |
757 | break; |
758 | default: |
759 | break; |
760 | } |
761 | |
762 | /* No conversion for raw channels */ |
763 | if (conv_tbl[index].conv_type == IIO_CHAN_INFO_RAW) |
764 | return; |
765 | |
766 | /* Temperatures use a lookup table instead of conversion table */ |
767 | if ((req->channel == CPCAP_ADC_AD0) || |
768 | (req->channel == CPCAP_ADC_AD3)) { |
769 | req->result = |
770 | cpcap_adc_table_to_millicelcius(value: req->result); |
771 | |
772 | return; |
773 | } |
774 | |
775 | /* All processed channels use a conversion table */ |
776 | req->result *= conv_tbl[index].multiplier; |
777 | if (conv_tbl[index].divider == 0) |
778 | return; |
779 | req->result /= conv_tbl[index].divider; |
780 | req->result += conv_tbl[index].conv_offset; |
781 | } |
782 | |
783 | /* |
784 | * REVISIT: Check if timed sampling can use multiple channels at the |
785 | * same time. If not, replace channel_mask with just channel. |
786 | */ |
787 | static int cpcap_adc_read_bank_scaled(struct cpcap_adc *ddata, |
788 | struct cpcap_adc_request *req) |
789 | { |
790 | int calibration_data, error, addr; |
791 | |
792 | if (ddata->vendor == CPCAP_VENDOR_TI) { |
793 | error = regmap_read(map: ddata->reg, CPCAP_REG_ADCAL1, |
794 | val: &calibration_data); |
795 | if (error) |
796 | return error; |
797 | bank_conversion[CPCAP_ADC_CHG_ISENSE].cal_offset = |
798 | ((short)calibration_data * -1) + 512; |
799 | |
800 | error = regmap_read(map: ddata->reg, CPCAP_REG_ADCAL2, |
801 | val: &calibration_data); |
802 | if (error) |
803 | return error; |
804 | bank_conversion[CPCAP_ADC_BATTI].cal_offset = |
805 | ((short)calibration_data * -1) + 512; |
806 | } |
807 | |
808 | addr = CPCAP_REG_ADCD0 + req->bank_index * 4; |
809 | |
810 | error = regmap_read(map: ddata->reg, reg: addr, val: &req->result); |
811 | if (error) |
812 | return error; |
813 | |
814 | req->result &= 0x3ff; |
815 | cpcap_adc_phase(req); |
816 | cpcap_adc_convert(req); |
817 | |
818 | return 0; |
819 | } |
820 | |
821 | static int cpcap_adc_init_request(struct cpcap_adc_request *req, |
822 | int channel) |
823 | { |
824 | req->channel = channel; |
825 | req->phase_tbl = bank_phasing; |
826 | req->conv_tbl = bank_conversion; |
827 | |
828 | switch (channel) { |
829 | case CPCAP_ADC_AD0 ... CPCAP_ADC_USB_ID: |
830 | req->bank_index = channel; |
831 | break; |
832 | case CPCAP_ADC_AD8 ... CPCAP_ADC_TSY2_AD15: |
833 | req->bank_index = channel - 8; |
834 | break; |
835 | case CPCAP_ADC_BATTP_PI16: |
836 | req->bank_index = CPCAP_ADC_BATTP; |
837 | break; |
838 | case CPCAP_ADC_BATTI_PI17: |
839 | req->bank_index = CPCAP_ADC_BATTI; |
840 | break; |
841 | default: |
842 | return -EINVAL; |
843 | } |
844 | |
845 | return 0; |
846 | } |
847 | |
848 | static int cpcap_adc_read_st_die_temp(struct cpcap_adc *ddata, |
849 | int addr, int *val) |
850 | { |
851 | int error; |
852 | |
853 | error = regmap_read(map: ddata->reg, reg: addr, val); |
854 | if (error) |
855 | return error; |
856 | |
857 | *val -= 282; |
858 | *val *= 114; |
859 | *val += 25000; |
860 | |
861 | return 0; |
862 | } |
863 | |
864 | static int cpcap_adc_read(struct iio_dev *indio_dev, |
865 | struct iio_chan_spec const *chan, |
866 | int *val, int *val2, long mask) |
867 | { |
868 | struct cpcap_adc *ddata = iio_priv(indio_dev); |
869 | struct cpcap_adc_request req; |
870 | int error; |
871 | |
872 | error = cpcap_adc_init_request(req: &req, channel: chan->channel); |
873 | if (error) |
874 | return error; |
875 | |
876 | switch (mask) { |
877 | case IIO_CHAN_INFO_RAW: |
878 | mutex_lock(&ddata->lock); |
879 | error = cpcap_adc_start_bank(ddata, req: &req); |
880 | if (error) |
881 | goto err_unlock; |
882 | error = regmap_read(map: ddata->reg, reg: chan->address, val); |
883 | if (error) |
884 | goto err_unlock; |
885 | error = cpcap_adc_stop_bank(ddata); |
886 | if (error) |
887 | goto err_unlock; |
888 | mutex_unlock(lock: &ddata->lock); |
889 | break; |
890 | case IIO_CHAN_INFO_PROCESSED: |
891 | mutex_lock(&ddata->lock); |
892 | error = cpcap_adc_start_bank(ddata, req: &req); |
893 | if (error) |
894 | goto err_unlock; |
895 | if ((ddata->vendor == CPCAP_VENDOR_ST) && |
896 | (chan->channel == CPCAP_ADC_AD3)) { |
897 | error = cpcap_adc_read_st_die_temp(ddata, |
898 | addr: chan->address, |
899 | val: &req.result); |
900 | if (error) |
901 | goto err_unlock; |
902 | } else { |
903 | error = cpcap_adc_read_bank_scaled(ddata, req: &req); |
904 | if (error) |
905 | goto err_unlock; |
906 | } |
907 | error = cpcap_adc_stop_bank(ddata); |
908 | if (error) |
909 | goto err_unlock; |
910 | mutex_unlock(lock: &ddata->lock); |
911 | *val = req.result; |
912 | break; |
913 | default: |
914 | return -EINVAL; |
915 | } |
916 | |
917 | return IIO_VAL_INT; |
918 | |
919 | err_unlock: |
920 | mutex_unlock(lock: &ddata->lock); |
921 | dev_err(ddata->dev, "error reading ADC: %i\n" , error); |
922 | |
923 | return error; |
924 | } |
925 | |
926 | static const struct iio_info cpcap_adc_info = { |
927 | .read_raw = &cpcap_adc_read, |
928 | }; |
929 | |
930 | /* |
931 | * Configuration for Motorola mapphone series such as droid 4. |
932 | * Copied from the Motorola mapphone kernel tree. |
933 | */ |
934 | static const struct cpcap_adc_ato mapphone_adc = { |
935 | .ato_in = 0x0480, |
936 | .atox_in = 0, |
937 | .adc_ps_factor_in = 0x0200, |
938 | .atox_ps_factor_in = 0, |
939 | .ato_out = 0, |
940 | .atox_out = 0, |
941 | .adc_ps_factor_out = 0, |
942 | .atox_ps_factor_out = 0, |
943 | }; |
944 | |
945 | static const struct of_device_id cpcap_adc_id_table[] = { |
946 | { |
947 | .compatible = "motorola,cpcap-adc" , |
948 | }, |
949 | { |
950 | .compatible = "motorola,mapphone-cpcap-adc" , |
951 | .data = &mapphone_adc, |
952 | }, |
953 | { /* sentinel */ }, |
954 | }; |
955 | MODULE_DEVICE_TABLE(of, cpcap_adc_id_table); |
956 | |
957 | static int cpcap_adc_probe(struct platform_device *pdev) |
958 | { |
959 | struct cpcap_adc *ddata; |
960 | struct iio_dev *indio_dev; |
961 | int error; |
962 | |
963 | indio_dev = devm_iio_device_alloc(parent: &pdev->dev, sizeof_priv: sizeof(*ddata)); |
964 | if (!indio_dev) { |
965 | dev_err(&pdev->dev, "failed to allocate iio device\n" ); |
966 | |
967 | return -ENOMEM; |
968 | } |
969 | ddata = iio_priv(indio_dev); |
970 | ddata->ato = device_get_match_data(dev: &pdev->dev); |
971 | if (!ddata->ato) |
972 | return -ENODEV; |
973 | ddata->dev = &pdev->dev; |
974 | |
975 | mutex_init(&ddata->lock); |
976 | init_waitqueue_head(&ddata->wq_data_avail); |
977 | |
978 | indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; |
979 | indio_dev->channels = cpcap_adc_channels; |
980 | indio_dev->num_channels = ARRAY_SIZE(cpcap_adc_channels); |
981 | indio_dev->name = dev_name(dev: &pdev->dev); |
982 | indio_dev->info = &cpcap_adc_info; |
983 | |
984 | ddata->reg = dev_get_regmap(dev: pdev->dev.parent, NULL); |
985 | if (!ddata->reg) |
986 | return -ENODEV; |
987 | |
988 | error = cpcap_get_vendor(dev: ddata->dev, regmap: ddata->reg, vendor: &ddata->vendor); |
989 | if (error) |
990 | return error; |
991 | |
992 | platform_set_drvdata(pdev, data: indio_dev); |
993 | |
994 | ddata->irq = platform_get_irq_byname(pdev, "adcdone" ); |
995 | if (ddata->irq < 0) |
996 | return -ENODEV; |
997 | |
998 | error = devm_request_threaded_irq(dev: &pdev->dev, irq: ddata->irq, NULL, |
999 | thread_fn: cpcap_adc_irq_thread, |
1000 | IRQF_TRIGGER_NONE | IRQF_ONESHOT, |
1001 | devname: "cpcap-adc" , dev_id: indio_dev); |
1002 | if (error) { |
1003 | dev_err(&pdev->dev, "could not get irq: %i\n" , |
1004 | error); |
1005 | |
1006 | return error; |
1007 | } |
1008 | |
1009 | error = cpcap_adc_calibrate(ddata); |
1010 | if (error) |
1011 | return error; |
1012 | |
1013 | dev_info(&pdev->dev, "CPCAP ADC device probed\n" ); |
1014 | |
1015 | return devm_iio_device_register(&pdev->dev, indio_dev); |
1016 | } |
1017 | |
1018 | static struct platform_driver cpcap_adc_driver = { |
1019 | .driver = { |
1020 | .name = "cpcap_adc" , |
1021 | .of_match_table = cpcap_adc_id_table, |
1022 | }, |
1023 | .probe = cpcap_adc_probe, |
1024 | }; |
1025 | |
1026 | module_platform_driver(cpcap_adc_driver); |
1027 | |
1028 | MODULE_ALIAS("platform:cpcap_adc" ); |
1029 | MODULE_DESCRIPTION("CPCAP ADC driver" ); |
1030 | MODULE_AUTHOR("Tony Lindgren <tony@atomide.com" ); |
1031 | MODULE_LICENSE("GPL v2" ); |
1032 | |