1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * This file is part of AD5686 DAC driver |
4 | * |
5 | * Copyright 2018 Analog Devices Inc. |
6 | */ |
7 | |
8 | #ifndef __DRIVERS_IIO_DAC_AD5686_H__ |
9 | #define __DRIVERS_IIO_DAC_AD5686_H__ |
10 | |
11 | #include <linux/types.h> |
12 | #include <linux/cache.h> |
13 | #include <linux/mutex.h> |
14 | #include <linux/kernel.h> |
15 | |
16 | #include <linux/iio/iio.h> |
17 | |
18 | #define AD5310_CMD(x) ((x) << 12) |
19 | |
20 | #define AD5683_DATA(x) ((x) << 4) |
21 | |
22 | #define AD5686_ADDR(x) ((x) << 16) |
23 | #define AD5686_CMD(x) ((x) << 20) |
24 | |
25 | #define AD5686_ADDR_DAC(chan) (0x1 << (chan)) |
26 | #define AD5686_ADDR_ALL_DAC 0xF |
27 | |
28 | #define AD5686_CMD_NOOP 0x0 |
29 | #define AD5686_CMD_WRITE_INPUT_N 0x1 |
30 | #define AD5686_CMD_UPDATE_DAC_N 0x2 |
31 | #define AD5686_CMD_WRITE_INPUT_N_UPDATE_N 0x3 |
32 | #define AD5686_CMD_POWERDOWN_DAC 0x4 |
33 | #define AD5686_CMD_LDAC_MASK 0x5 |
34 | #define AD5686_CMD_RESET 0x6 |
35 | #define AD5686_CMD_INTERNAL_REFER_SETUP 0x7 |
36 | #define AD5686_CMD_DAISY_CHAIN_ENABLE 0x8 |
37 | #define AD5686_CMD_READBACK_ENABLE 0x9 |
38 | |
39 | #define AD5686_LDAC_PWRDN_NONE 0x0 |
40 | #define AD5686_LDAC_PWRDN_1K 0x1 |
41 | #define AD5686_LDAC_PWRDN_100K 0x2 |
42 | #define AD5686_LDAC_PWRDN_3STATE 0x3 |
43 | |
44 | #define AD5686_CMD_CONTROL_REG 0x4 |
45 | #define AD5686_CMD_READBACK_ENABLE_V2 0x5 |
46 | |
47 | #define AD5310_REF_BIT_MSK BIT(8) |
48 | #define AD5683_REF_BIT_MSK BIT(12) |
49 | #define AD5693_REF_BIT_MSK BIT(12) |
50 | |
51 | /** |
52 | * ad5686_supported_device_ids: |
53 | */ |
54 | enum ad5686_supported_device_ids { |
55 | ID_AD5310R, |
56 | ID_AD5311R, |
57 | ID_AD5337R, |
58 | ID_AD5338R, |
59 | ID_AD5671R, |
60 | ID_AD5672R, |
61 | ID_AD5673R, |
62 | ID_AD5674R, |
63 | ID_AD5675R, |
64 | ID_AD5676, |
65 | ID_AD5676R, |
66 | ID_AD5677R, |
67 | ID_AD5679R, |
68 | ID_AD5681R, |
69 | ID_AD5682R, |
70 | ID_AD5683, |
71 | ID_AD5683R, |
72 | ID_AD5684, |
73 | ID_AD5684R, |
74 | ID_AD5685R, |
75 | ID_AD5686, |
76 | ID_AD5686R, |
77 | ID_AD5691R, |
78 | ID_AD5692R, |
79 | ID_AD5693, |
80 | ID_AD5693R, |
81 | ID_AD5694, |
82 | ID_AD5694R, |
83 | ID_AD5695R, |
84 | ID_AD5696, |
85 | ID_AD5696R, |
86 | }; |
87 | |
88 | enum ad5686_regmap_type { |
89 | AD5310_REGMAP, |
90 | AD5683_REGMAP, |
91 | AD5686_REGMAP, |
92 | AD5693_REGMAP |
93 | }; |
94 | |
95 | struct ad5686_state; |
96 | |
97 | typedef int (*ad5686_write_func)(struct ad5686_state *st, |
98 | u8 cmd, u8 addr, u16 val); |
99 | |
100 | typedef int (*ad5686_read_func)(struct ad5686_state *st, u8 addr); |
101 | |
102 | /** |
103 | * struct ad5686_chip_info - chip specific information |
104 | * @int_vref_mv: AD5620/40/60: the internal reference voltage |
105 | * @num_channels: number of channels |
106 | * @channel: channel specification |
107 | * @regmap_type: register map layout variant |
108 | */ |
109 | |
110 | struct ad5686_chip_info { |
111 | u16 int_vref_mv; |
112 | unsigned int num_channels; |
113 | const struct iio_chan_spec *channels; |
114 | enum ad5686_regmap_type regmap_type; |
115 | }; |
116 | |
117 | /** |
118 | * struct ad5446_state - driver instance specific data |
119 | * @spi: spi_device |
120 | * @chip_info: chip model specific constants, available modes etc |
121 | * @reg: supply regulator |
122 | * @vref_mv: actual reference voltage used |
123 | * @pwr_down_mask: power down mask |
124 | * @pwr_down_mode: current power down mode |
125 | * @use_internal_vref: set to true if the internal reference voltage is used |
126 | * @lock lock to protect the data buffer during regmap ops |
127 | * @data: spi transfer buffers |
128 | */ |
129 | |
130 | struct ad5686_state { |
131 | struct device *dev; |
132 | const struct ad5686_chip_info *chip_info; |
133 | struct regulator *reg; |
134 | unsigned short vref_mv; |
135 | unsigned int pwr_down_mask; |
136 | unsigned int pwr_down_mode; |
137 | ad5686_write_func write; |
138 | ad5686_read_func read; |
139 | bool use_internal_vref; |
140 | struct mutex lock; |
141 | |
142 | /* |
143 | * DMA (thus cache coherency maintenance) may require the |
144 | * transfer buffers to live in their own cache lines. |
145 | */ |
146 | |
147 | union { |
148 | __be32 d32; |
149 | __be16 d16; |
150 | u8 d8[4]; |
151 | } data[3] __aligned(IIO_DMA_MINALIGN); |
152 | }; |
153 | |
154 | |
155 | int ad5686_probe(struct device *dev, |
156 | enum ad5686_supported_device_ids chip_type, |
157 | const char *name, ad5686_write_func write, |
158 | ad5686_read_func read); |
159 | |
160 | void ad5686_remove(struct device *dev); |
161 | |
162 | |
163 | #endif /* __DRIVERS_IIO_DAC_AD5686_H__ */ |
164 | |