1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * This file is part of STM32 DAC driver |
4 | * |
5 | * Copyright (C) 2017, STMicroelectronics - All Rights Reserved |
6 | * Authors: Amelie Delaunay <amelie.delaunay@st.com> |
7 | * Fabrice Gasnier <fabrice.gasnier@st.com> |
8 | */ |
9 | |
10 | #include <linux/bitfield.h> |
11 | #include <linux/delay.h> |
12 | #include <linux/iio/iio.h> |
13 | #include <linux/kernel.h> |
14 | #include <linux/kstrtox.h> |
15 | #include <linux/module.h> |
16 | #include <linux/mod_devicetable.h> |
17 | #include <linux/of.h> |
18 | #include <linux/platform_device.h> |
19 | #include <linux/pm_runtime.h> |
20 | #include <linux/string_choices.h> |
21 | |
22 | #include "stm32-dac-core.h" |
23 | |
24 | #define STM32_DAC_CHANNEL_1 1 |
25 | #define STM32_DAC_CHANNEL_2 2 |
26 | #define STM32_DAC_IS_CHAN_1(ch) ((ch) & STM32_DAC_CHANNEL_1) |
27 | |
28 | #define STM32_DAC_AUTO_SUSPEND_DELAY_MS 2000 |
29 | |
30 | /** |
31 | * struct stm32_dac - private data of DAC driver |
32 | * @common: reference to DAC common data |
33 | * @lock: lock to protect against potential races when reading |
34 | * and update CR, to keep it in sync with pm_runtime |
35 | */ |
36 | struct stm32_dac { |
37 | struct stm32_dac_common *common; |
38 | struct mutex lock; |
39 | }; |
40 | |
41 | static int stm32_dac_is_enabled(struct iio_dev *indio_dev, int channel) |
42 | { |
43 | struct stm32_dac *dac = iio_priv(indio_dev); |
44 | u32 en, val; |
45 | int ret; |
46 | |
47 | ret = regmap_read(map: dac->common->regmap, STM32_DAC_CR, val: &val); |
48 | if (ret < 0) |
49 | return ret; |
50 | if (STM32_DAC_IS_CHAN_1(channel)) |
51 | en = FIELD_GET(STM32_DAC_CR_EN1, val); |
52 | else |
53 | en = FIELD_GET(STM32_DAC_CR_EN2, val); |
54 | |
55 | return !!en; |
56 | } |
57 | |
58 | static int stm32_dac_set_enable_state(struct iio_dev *indio_dev, int ch, |
59 | bool enable) |
60 | { |
61 | struct stm32_dac *dac = iio_priv(indio_dev); |
62 | struct device *dev = indio_dev->dev.parent; |
63 | u32 msk = STM32_DAC_IS_CHAN_1(ch) ? STM32_DAC_CR_EN1 : STM32_DAC_CR_EN2; |
64 | u32 en = enable ? msk : 0; |
65 | int ret; |
66 | |
67 | /* already enabled / disabled ? */ |
68 | mutex_lock(&dac->lock); |
69 | ret = stm32_dac_is_enabled(indio_dev, channel: ch); |
70 | if (ret < 0 || enable == !!ret) { |
71 | mutex_unlock(lock: &dac->lock); |
72 | return ret < 0 ? ret : 0; |
73 | } |
74 | |
75 | if (enable) { |
76 | ret = pm_runtime_resume_and_get(dev); |
77 | if (ret < 0) { |
78 | mutex_unlock(lock: &dac->lock); |
79 | return ret; |
80 | } |
81 | } |
82 | |
83 | ret = regmap_update_bits(map: dac->common->regmap, STM32_DAC_CR, mask: msk, val: en); |
84 | mutex_unlock(lock: &dac->lock); |
85 | if (ret < 0) { |
86 | dev_err(&indio_dev->dev, "%s failed\n" , str_enable_disable(en)); |
87 | goto err_put_pm; |
88 | } |
89 | |
90 | /* |
91 | * When HFSEL is set, it is not allowed to write the DHRx register |
92 | * during 8 clock cycles after the ENx bit is set. It is not allowed |
93 | * to make software/hardware trigger during this period either. |
94 | */ |
95 | if (en && dac->common->hfsel) |
96 | udelay(1); |
97 | |
98 | if (!enable) { |
99 | pm_runtime_mark_last_busy(dev); |
100 | pm_runtime_put_autosuspend(dev); |
101 | } |
102 | |
103 | return 0; |
104 | |
105 | err_put_pm: |
106 | if (enable) { |
107 | pm_runtime_mark_last_busy(dev); |
108 | pm_runtime_put_autosuspend(dev); |
109 | } |
110 | |
111 | return ret; |
112 | } |
113 | |
114 | static int stm32_dac_get_value(struct stm32_dac *dac, int channel, int *val) |
115 | { |
116 | int ret; |
117 | |
118 | if (STM32_DAC_IS_CHAN_1(channel)) |
119 | ret = regmap_read(map: dac->common->regmap, STM32_DAC_DOR1, val); |
120 | else |
121 | ret = regmap_read(map: dac->common->regmap, STM32_DAC_DOR2, val); |
122 | |
123 | return ret ? ret : IIO_VAL_INT; |
124 | } |
125 | |
126 | static int stm32_dac_set_value(struct stm32_dac *dac, int channel, int val) |
127 | { |
128 | int ret; |
129 | |
130 | if (STM32_DAC_IS_CHAN_1(channel)) |
131 | ret = regmap_write(map: dac->common->regmap, STM32_DAC_DHR12R1, val); |
132 | else |
133 | ret = regmap_write(map: dac->common->regmap, STM32_DAC_DHR12R2, val); |
134 | |
135 | return ret; |
136 | } |
137 | |
138 | static int stm32_dac_read_raw(struct iio_dev *indio_dev, |
139 | struct iio_chan_spec const *chan, |
140 | int *val, int *val2, long mask) |
141 | { |
142 | struct stm32_dac *dac = iio_priv(indio_dev); |
143 | |
144 | switch (mask) { |
145 | case IIO_CHAN_INFO_RAW: |
146 | return stm32_dac_get_value(dac, channel: chan->channel, val); |
147 | case IIO_CHAN_INFO_SCALE: |
148 | *val = dac->common->vref_mv; |
149 | *val2 = chan->scan_type.realbits; |
150 | return IIO_VAL_FRACTIONAL_LOG2; |
151 | default: |
152 | return -EINVAL; |
153 | } |
154 | } |
155 | |
156 | static int stm32_dac_write_raw(struct iio_dev *indio_dev, |
157 | struct iio_chan_spec const *chan, |
158 | int val, int val2, long mask) |
159 | { |
160 | struct stm32_dac *dac = iio_priv(indio_dev); |
161 | |
162 | switch (mask) { |
163 | case IIO_CHAN_INFO_RAW: |
164 | return stm32_dac_set_value(dac, channel: chan->channel, val); |
165 | default: |
166 | return -EINVAL; |
167 | } |
168 | } |
169 | |
170 | static int stm32_dac_debugfs_reg_access(struct iio_dev *indio_dev, |
171 | unsigned reg, unsigned writeval, |
172 | unsigned *readval) |
173 | { |
174 | struct stm32_dac *dac = iio_priv(indio_dev); |
175 | |
176 | if (!readval) |
177 | return regmap_write(map: dac->common->regmap, reg, val: writeval); |
178 | else |
179 | return regmap_read(map: dac->common->regmap, reg, val: readval); |
180 | } |
181 | |
182 | static const struct iio_info stm32_dac_iio_info = { |
183 | .read_raw = stm32_dac_read_raw, |
184 | .write_raw = stm32_dac_write_raw, |
185 | .debugfs_reg_access = stm32_dac_debugfs_reg_access, |
186 | }; |
187 | |
188 | static const char * const stm32_dac_powerdown_modes[] = { |
189 | "three_state" , |
190 | }; |
191 | |
192 | static int stm32_dac_get_powerdown_mode(struct iio_dev *indio_dev, |
193 | const struct iio_chan_spec *chan) |
194 | { |
195 | return 0; |
196 | } |
197 | |
198 | static int stm32_dac_set_powerdown_mode(struct iio_dev *indio_dev, |
199 | const struct iio_chan_spec *chan, |
200 | unsigned int type) |
201 | { |
202 | return 0; |
203 | } |
204 | |
205 | static ssize_t stm32_dac_read_powerdown(struct iio_dev *indio_dev, |
206 | uintptr_t private, |
207 | const struct iio_chan_spec *chan, |
208 | char *buf) |
209 | { |
210 | int ret = stm32_dac_is_enabled(indio_dev, channel: chan->channel); |
211 | |
212 | if (ret < 0) |
213 | return ret; |
214 | |
215 | return sysfs_emit(buf, fmt: "%d\n" , ret ? 0 : 1); |
216 | } |
217 | |
218 | static ssize_t stm32_dac_write_powerdown(struct iio_dev *indio_dev, |
219 | uintptr_t private, |
220 | const struct iio_chan_spec *chan, |
221 | const char *buf, size_t len) |
222 | { |
223 | bool powerdown; |
224 | int ret; |
225 | |
226 | ret = kstrtobool(s: buf, res: &powerdown); |
227 | if (ret) |
228 | return ret; |
229 | |
230 | ret = stm32_dac_set_enable_state(indio_dev, ch: chan->channel, enable: !powerdown); |
231 | if (ret) |
232 | return ret; |
233 | |
234 | return len; |
235 | } |
236 | |
237 | static const struct iio_enum stm32_dac_powerdown_mode_en = { |
238 | .items = stm32_dac_powerdown_modes, |
239 | .num_items = ARRAY_SIZE(stm32_dac_powerdown_modes), |
240 | .get = stm32_dac_get_powerdown_mode, |
241 | .set = stm32_dac_set_powerdown_mode, |
242 | }; |
243 | |
244 | static const struct iio_chan_spec_ext_info stm32_dac_ext_info[] = { |
245 | { |
246 | .name = "powerdown" , |
247 | .read = stm32_dac_read_powerdown, |
248 | .write = stm32_dac_write_powerdown, |
249 | .shared = IIO_SEPARATE, |
250 | }, |
251 | IIO_ENUM("powerdown_mode" , IIO_SEPARATE, &stm32_dac_powerdown_mode_en), |
252 | IIO_ENUM_AVAILABLE("powerdown_mode" , IIO_SHARED_BY_TYPE, &stm32_dac_powerdown_mode_en), |
253 | {}, |
254 | }; |
255 | |
256 | #define STM32_DAC_CHANNEL(chan, name) { \ |
257 | .type = IIO_VOLTAGE, \ |
258 | .indexed = 1, \ |
259 | .output = 1, \ |
260 | .channel = chan, \ |
261 | .info_mask_separate = \ |
262 | BIT(IIO_CHAN_INFO_RAW) | \ |
263 | BIT(IIO_CHAN_INFO_SCALE), \ |
264 | /* scan_index is always 0 as num_channels is 1 */ \ |
265 | .scan_type = { \ |
266 | .sign = 'u', \ |
267 | .realbits = 12, \ |
268 | .storagebits = 16, \ |
269 | }, \ |
270 | .datasheet_name = name, \ |
271 | .ext_info = stm32_dac_ext_info \ |
272 | } |
273 | |
274 | static const struct iio_chan_spec stm32_dac_channels[] = { |
275 | STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_1, "out1" ), |
276 | STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_2, "out2" ), |
277 | }; |
278 | |
279 | static int stm32_dac_chan_of_init(struct iio_dev *indio_dev) |
280 | { |
281 | struct device_node *np = indio_dev->dev.of_node; |
282 | unsigned int i; |
283 | u32 channel; |
284 | int ret; |
285 | |
286 | ret = of_property_read_u32(np, propname: "reg" , out_value: &channel); |
287 | if (ret) { |
288 | dev_err(&indio_dev->dev, "Failed to read reg property\n" ); |
289 | return ret; |
290 | } |
291 | |
292 | for (i = 0; i < ARRAY_SIZE(stm32_dac_channels); i++) { |
293 | if (stm32_dac_channels[i].channel == channel) |
294 | break; |
295 | } |
296 | if (i >= ARRAY_SIZE(stm32_dac_channels)) { |
297 | dev_err(&indio_dev->dev, "Invalid reg property\n" ); |
298 | return -EINVAL; |
299 | } |
300 | |
301 | indio_dev->channels = &stm32_dac_channels[i]; |
302 | /* |
303 | * Expose only one channel here, as they can be used independently, |
304 | * with separate trigger. Then separate IIO devices are instantiated |
305 | * to manage this. |
306 | */ |
307 | indio_dev->num_channels = 1; |
308 | |
309 | return 0; |
310 | }; |
311 | |
312 | static int stm32_dac_probe(struct platform_device *pdev) |
313 | { |
314 | struct device_node *np = pdev->dev.of_node; |
315 | struct device *dev = &pdev->dev; |
316 | struct iio_dev *indio_dev; |
317 | struct stm32_dac *dac; |
318 | int ret; |
319 | |
320 | if (!np) |
321 | return -ENODEV; |
322 | |
323 | indio_dev = devm_iio_device_alloc(parent: &pdev->dev, sizeof_priv: sizeof(*dac)); |
324 | if (!indio_dev) |
325 | return -ENOMEM; |
326 | platform_set_drvdata(pdev, data: indio_dev); |
327 | |
328 | dac = iio_priv(indio_dev); |
329 | dac->common = dev_get_drvdata(dev: pdev->dev.parent); |
330 | indio_dev->name = dev_name(dev: &pdev->dev); |
331 | indio_dev->dev.of_node = pdev->dev.of_node; |
332 | indio_dev->info = &stm32_dac_iio_info; |
333 | indio_dev->modes = INDIO_DIRECT_MODE; |
334 | |
335 | mutex_init(&dac->lock); |
336 | |
337 | ret = stm32_dac_chan_of_init(indio_dev); |
338 | if (ret < 0) |
339 | return ret; |
340 | |
341 | /* Get stm32-dac-core PM online */ |
342 | pm_runtime_get_noresume(dev); |
343 | pm_runtime_set_active(dev); |
344 | pm_runtime_set_autosuspend_delay(dev, STM32_DAC_AUTO_SUSPEND_DELAY_MS); |
345 | pm_runtime_use_autosuspend(dev); |
346 | pm_runtime_enable(dev); |
347 | |
348 | ret = iio_device_register(indio_dev); |
349 | if (ret) |
350 | goto err_pm_put; |
351 | |
352 | pm_runtime_mark_last_busy(dev); |
353 | pm_runtime_put_autosuspend(dev); |
354 | |
355 | return 0; |
356 | |
357 | err_pm_put: |
358 | pm_runtime_disable(dev); |
359 | pm_runtime_set_suspended(dev); |
360 | pm_runtime_put_noidle(dev); |
361 | |
362 | return ret; |
363 | } |
364 | |
365 | static void stm32_dac_remove(struct platform_device *pdev) |
366 | { |
367 | struct iio_dev *indio_dev = platform_get_drvdata(pdev); |
368 | |
369 | pm_runtime_get_sync(dev: &pdev->dev); |
370 | iio_device_unregister(indio_dev); |
371 | pm_runtime_disable(dev: &pdev->dev); |
372 | pm_runtime_set_suspended(dev: &pdev->dev); |
373 | pm_runtime_put_noidle(dev: &pdev->dev); |
374 | } |
375 | |
376 | static int stm32_dac_suspend(struct device *dev) |
377 | { |
378 | struct iio_dev *indio_dev = dev_get_drvdata(dev); |
379 | int channel = indio_dev->channels[0].channel; |
380 | int ret; |
381 | |
382 | /* Ensure DAC is disabled before suspend */ |
383 | ret = stm32_dac_is_enabled(indio_dev, channel); |
384 | if (ret) |
385 | return ret < 0 ? ret : -EBUSY; |
386 | |
387 | return pm_runtime_force_suspend(dev); |
388 | } |
389 | |
390 | static DEFINE_SIMPLE_DEV_PM_OPS(stm32_dac_pm_ops, stm32_dac_suspend, |
391 | pm_runtime_force_resume); |
392 | |
393 | static const struct of_device_id stm32_dac_of_match[] = { |
394 | { .compatible = "st,stm32-dac" , }, |
395 | {}, |
396 | }; |
397 | MODULE_DEVICE_TABLE(of, stm32_dac_of_match); |
398 | |
399 | static struct platform_driver stm32_dac_driver = { |
400 | .probe = stm32_dac_probe, |
401 | .remove_new = stm32_dac_remove, |
402 | .driver = { |
403 | .name = "stm32-dac" , |
404 | .of_match_table = stm32_dac_of_match, |
405 | .pm = pm_sleep_ptr(&stm32_dac_pm_ops), |
406 | }, |
407 | }; |
408 | module_platform_driver(stm32_dac_driver); |
409 | |
410 | MODULE_ALIAS("platform:stm32-dac" ); |
411 | MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>" ); |
412 | MODULE_DESCRIPTION("STMicroelectronics STM32 DAC driver" ); |
413 | MODULE_LICENSE("GPL v2" ); |
414 | |