1	/*
2	* Broadcom NetXtreme-E RoCE driver.
3	*
4	* Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5	* Broadcom refers to Broadcom Limited and/or its subsidiaries.
6	*
7	* This software is available to you under a choice of one of two
8	* licenses. You may choose to be licensed under the terms of the GNU
9	* General Public License (GPL) Version 2, available from the file
10	* COPYING in the main directory of this source tree, or the
11	* BSD license below:
12	*
13	* Redistribution and use in source and binary forms, with or without
14	* modification, are permitted provided that the following conditions
15	* are met:
16	*
17	* 1. Redistributions of source code must retain the above copyright
18	* notice, this list of conditions and the following disclaimer.
19	* 2. Redistributions in binary form must reproduce the above copyright
20	* notice, this list of conditions and the following disclaimer in
21	* the documentation and/or other materials provided with the
22	* distribution.
23	*
24	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26	* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27	* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28	* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31	* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33	* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34	* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35	*
36	* Description: RoCE HSI File - Autogenerated
37	*/
38
39	#ifndef __BNXT_RE_HSI_H__
40	#define __BNXT_RE_HSI_H__
41
42	/* include bnxt_hsi.h from bnxt_en driver */
43	#include "bnxt_hsi.h"
44
45	/* tx_doorbell (size:32b/4B) */
46	struct tx_doorbell {
47	__le32 key_idx;
48	#define TX_DOORBELL_IDX_MASK 0xffffffUL
49	#define TX_DOORBELL_IDX_SFT 0
50	#define TX_DOORBELL_KEY_MASK 0xf0000000UL
51	#define TX_DOORBELL_KEY_SFT 28
52	#define TX_DOORBELL_KEY_TX (0x0UL << 28)
53	#define TX_DOORBELL_KEY_LAST TX_DOORBELL_KEY_TX
54	};
55
56	/* rx_doorbell (size:32b/4B) */
57	struct rx_doorbell {
58	__le32 key_idx;
59	#define RX_DOORBELL_IDX_MASK 0xffffffUL
60	#define RX_DOORBELL_IDX_SFT 0
61	#define RX_DOORBELL_KEY_MASK 0xf0000000UL
62	#define RX_DOORBELL_KEY_SFT 28
63	#define RX_DOORBELL_KEY_RX (0x1UL << 28)
64	#define RX_DOORBELL_KEY_LAST RX_DOORBELL_KEY_RX
65	};
66
67	/* cmpl_doorbell (size:32b/4B) */
68	struct cmpl_doorbell {
69	__le32 key_mask_valid_idx;
70	#define CMPL_DOORBELL_IDX_MASK 0xffffffUL
71	#define CMPL_DOORBELL_IDX_SFT 0
72	#define CMPL_DOORBELL_IDX_VALID 0x4000000UL
73	#define CMPL_DOORBELL_MASK 0x8000000UL
74	#define CMPL_DOORBELL_KEY_MASK 0xf0000000UL
75	#define CMPL_DOORBELL_KEY_SFT 28
76	#define CMPL_DOORBELL_KEY_CMPL (0x2UL << 28)
77	#define CMPL_DOORBELL_KEY_LAST CMPL_DOORBELL_KEY_CMPL
78	};
79
80	/* status_doorbell (size:32b/4B) */
81	struct status_doorbell {
82	__le32 key_idx;
83	#define STATUS_DOORBELL_IDX_MASK 0xffffffUL
84	#define STATUS_DOORBELL_IDX_SFT 0
85	#define STATUS_DOORBELL_KEY_MASK 0xf0000000UL
86	#define STATUS_DOORBELL_KEY_SFT 28
87	#define STATUS_DOORBELL_KEY_STAT (0x3UL << 28)
88	#define STATUS_DOORBELL_KEY_LAST STATUS_DOORBELL_KEY_STAT
89	};
90
91	/* cmdq_init (size:128b/16B) */
92	struct cmdq_init {
93	__le64 cmdq_pbl;
94	__le16 cmdq_size_cmdq_lvl;
95	#define CMDQ_INIT_CMDQ_LVL_MASK 0x3UL
96	#define CMDQ_INIT_CMDQ_LVL_SFT 0
97	#define CMDQ_INIT_CMDQ_SIZE_MASK 0xfffcUL
98	#define CMDQ_INIT_CMDQ_SIZE_SFT 2
99	__le16 creq_ring_id;
100	__le32 prod_idx;
101	};
102
103	/* cmdq_base (size:128b/16B) */
104	struct cmdq_base {
105	u8 opcode;
106	#define CMDQ_BASE_OPCODE_CREATE_QP 0x1UL
107	#define CMDQ_BASE_OPCODE_DESTROY_QP 0x2UL
108	#define CMDQ_BASE_OPCODE_MODIFY_QP 0x3UL
109	#define CMDQ_BASE_OPCODE_QUERY_QP 0x4UL
110	#define CMDQ_BASE_OPCODE_CREATE_SRQ 0x5UL
111	#define CMDQ_BASE_OPCODE_DESTROY_SRQ 0x6UL
112	#define CMDQ_BASE_OPCODE_QUERY_SRQ 0x8UL
113	#define CMDQ_BASE_OPCODE_CREATE_CQ 0x9UL
114	#define CMDQ_BASE_OPCODE_DESTROY_CQ 0xaUL
115	#define CMDQ_BASE_OPCODE_RESIZE_CQ 0xcUL
116	#define CMDQ_BASE_OPCODE_ALLOCATE_MRW 0xdUL
117	#define CMDQ_BASE_OPCODE_DEALLOCATE_KEY 0xeUL
118	#define CMDQ_BASE_OPCODE_REGISTER_MR 0xfUL
119	#define CMDQ_BASE_OPCODE_DEREGISTER_MR 0x10UL
120	#define CMDQ_BASE_OPCODE_ADD_GID 0x11UL
121	#define CMDQ_BASE_OPCODE_DELETE_GID 0x12UL
122	#define CMDQ_BASE_OPCODE_MODIFY_GID 0x17UL
123	#define CMDQ_BASE_OPCODE_QUERY_GID 0x18UL
124	#define CMDQ_BASE_OPCODE_CREATE_QP1 0x13UL
125	#define CMDQ_BASE_OPCODE_DESTROY_QP1 0x14UL
126	#define CMDQ_BASE_OPCODE_CREATE_AH 0x15UL
127	#define CMDQ_BASE_OPCODE_DESTROY_AH 0x16UL
128	#define CMDQ_BASE_OPCODE_INITIALIZE_FW 0x80UL
129	#define CMDQ_BASE_OPCODE_DEINITIALIZE_FW 0x81UL
130	#define CMDQ_BASE_OPCODE_STOP_FUNC 0x82UL
131	#define CMDQ_BASE_OPCODE_QUERY_FUNC 0x83UL
132	#define CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES 0x84UL
133	#define CMDQ_BASE_OPCODE_READ_CONTEXT 0x85UL
134	#define CMDQ_BASE_OPCODE_VF_BACKCHANNEL_REQUEST 0x86UL
135	#define CMDQ_BASE_OPCODE_READ_VF_MEMORY 0x87UL
136	#define CMDQ_BASE_OPCODE_COMPLETE_VF_REQUEST 0x88UL
137	#define CMDQ_BASE_OPCODE_EXTEND_CONTEXT_ARRRAY 0x89UL
138	#define CMDQ_BASE_OPCODE_MAP_TC_TO_COS 0x8aUL
139	#define CMDQ_BASE_OPCODE_QUERY_VERSION 0x8bUL
140	#define CMDQ_BASE_OPCODE_MODIFY_ROCE_CC 0x8cUL
141	#define CMDQ_BASE_OPCODE_QUERY_ROCE_CC 0x8dUL
142	#define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS 0x8eUL
143	#define CMDQ_BASE_OPCODE_SET_LINK_AGGR_MODE 0x8fUL
144	#define CMDQ_BASE_OPCODE_MODIFY_CQ 0x90UL
145	#define CMDQ_BASE_OPCODE_QUERY_QP_EXTEND 0x91UL
146	#define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT 0x92UL
147	#define CMDQ_BASE_OPCODE_LAST CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT
148	u8 cmd_size;
149	__le16 flags;
150	__le16 cookie;
151	u8 resp_size;
152	u8 reserved8;
153	__le64 resp_addr;
154	};
155
156	/* creq_base (size:128b/16B) */
157	struct creq_base {
158	u8 type;
159	#define CREQ_BASE_TYPE_MASK 0x3fUL
160	#define CREQ_BASE_TYPE_SFT 0
161	#define CREQ_BASE_TYPE_QP_EVENT 0x38UL
162	#define CREQ_BASE_TYPE_FUNC_EVENT 0x3aUL
163	#define CREQ_BASE_TYPE_LAST CREQ_BASE_TYPE_FUNC_EVENT
164	u8 reserved56[7];
165	u8 v;
166	#define CREQ_BASE_V 0x1UL
167	u8 event;
168	u8 reserved48[6];
169	};
170
171	/* cmdq_query_version (size:128b/16B) */
172	struct cmdq_query_version {
173	u8 opcode;
174	#define CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION 0x8bUL
175	#define CMDQ_QUERY_VERSION_OPCODE_LAST CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION
176	u8 cmd_size;
177	__le16 flags;
178	__le16 cookie;
179	u8 resp_size;
180	u8 reserved8;
181	__le64 resp_addr;
182	};
183
184	/* creq_query_version_resp (size:128b/16B) */
185	struct creq_query_version_resp {
186	u8 type;
187	#define CREQ_QUERY_VERSION_RESP_TYPE_MASK 0x3fUL
188	#define CREQ_QUERY_VERSION_RESP_TYPE_SFT 0
189	#define CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT 0x38UL
190	#define CREQ_QUERY_VERSION_RESP_TYPE_LAST CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT
191	u8 status;
192	__le16 cookie;
193	u8 fw_maj;
194	u8 fw_minor;
195	u8 fw_bld;
196	u8 fw_rsvd;
197	u8 v;
198	#define CREQ_QUERY_VERSION_RESP_V 0x1UL
199	u8 event;
200	#define CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION 0x8bUL
201	#define CREQ_QUERY_VERSION_RESP_EVENT_LAST \
202	CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION
203	__le16 reserved16;
204	u8 intf_maj;
205	u8 intf_minor;
206	u8 intf_bld;
207	u8 intf_rsvd;
208	};
209
210	/* cmdq_initialize_fw (size:896b/112B) */
211	struct cmdq_initialize_fw {
212	u8 opcode;
213	#define CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW 0x80UL
214	#define CMDQ_INITIALIZE_FW_OPCODE_LAST CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW
215	u8 cmd_size;
216	__le16 flags;
217	#define CMDQ_INITIALIZE_FW_FLAGS_MRAV_RESERVATION_SPLIT 0x1UL
218	#define CMDQ_INITIALIZE_FW_FLAGS_HW_REQUESTER_RETX_SUPPORTED 0x2UL
219	__le16 cookie;
220	u8 resp_size;
221	u8 reserved8;
222	__le64 resp_addr;
223	u8 qpc_pg_size_qpc_lvl;
224	#define CMDQ_INITIALIZE_FW_QPC_LVL_MASK 0xfUL
225	#define CMDQ_INITIALIZE_FW_QPC_LVL_SFT 0
226	#define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_0 0x0UL
227	#define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_1 0x1UL
228	#define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2 0x2UL
229	#define CMDQ_INITIALIZE_FW_QPC_LVL_LAST CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2
230	#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_MASK 0xf0UL
231	#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT 4
232	#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K (0x0UL << 4)
233	#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8K (0x1UL << 4)
234	#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_64K (0x2UL << 4)
235	#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_2M (0x3UL << 4)
236	#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8M (0x4UL << 4)
237	#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G (0x5UL << 4)
238	#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_LAST CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G
239	u8 mrw_pg_size_mrw_lvl;
240	#define CMDQ_INITIALIZE_FW_MRW_LVL_MASK 0xfUL
241	#define CMDQ_INITIALIZE_FW_MRW_LVL_SFT 0
242	#define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_0 0x0UL
243	#define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_1 0x1UL
244	#define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2 0x2UL
245	#define CMDQ_INITIALIZE_FW_MRW_LVL_LAST CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2
246	#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_MASK 0xf0UL
247	#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_SFT 4
248	#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_4K (0x0UL << 4)
249	#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8K (0x1UL << 4)
250	#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_64K (0x2UL << 4)
251	#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_2M (0x3UL << 4)
252	#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8M (0x4UL << 4)
253	#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G (0x5UL << 4)
254	#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_LAST CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G
255	u8 srq_pg_size_srq_lvl;
256	#define CMDQ_INITIALIZE_FW_SRQ_LVL_MASK 0xfUL
257	#define CMDQ_INITIALIZE_FW_SRQ_LVL_SFT 0
258	#define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_0 0x0UL
259	#define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_1 0x1UL
260	#define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2 0x2UL
261	#define CMDQ_INITIALIZE_FW_SRQ_LVL_LAST CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2
262	#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_MASK 0xf0UL
263	#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_SFT 4
264	#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_4K (0x0UL << 4)
265	#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8K (0x1UL << 4)
266	#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_64K (0x2UL << 4)
267	#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_2M (0x3UL << 4)
268	#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8M (0x4UL << 4)
269	#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G (0x5UL << 4)
270	#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_LAST CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G
271	u8 cq_pg_size_cq_lvl;
272	#define CMDQ_INITIALIZE_FW_CQ_LVL_MASK 0xfUL
273	#define CMDQ_INITIALIZE_FW_CQ_LVL_SFT 0
274	#define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_0 0x0UL
275	#define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_1 0x1UL
276	#define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2 0x2UL
277	#define CMDQ_INITIALIZE_FW_CQ_LVL_LAST CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2
278	#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_MASK 0xf0UL
279	#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_SFT 4
280	#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_4K (0x0UL << 4)
281	#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8K (0x1UL << 4)
282	#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_64K (0x2UL << 4)
283	#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_2M (0x3UL << 4)
284	#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8M (0x4UL << 4)
285	#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G (0x5UL << 4)
286	#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_LAST CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G
287	u8 tqm_pg_size_tqm_lvl;
288	#define CMDQ_INITIALIZE_FW_TQM_LVL_MASK 0xfUL
289	#define CMDQ_INITIALIZE_FW_TQM_LVL_SFT 0
290	#define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_0 0x0UL
291	#define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_1 0x1UL
292	#define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2 0x2UL
293	#define CMDQ_INITIALIZE_FW_TQM_LVL_LAST CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2
294	#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_MASK 0xf0UL
295	#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_SFT 4
296	#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_4K (0x0UL << 4)
297	#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8K (0x1UL << 4)
298	#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_64K (0x2UL << 4)
299	#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_2M (0x3UL << 4)
300	#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8M (0x4UL << 4)
301	#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G (0x5UL << 4)
302	#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_LAST CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G
303	u8 tim_pg_size_tim_lvl;
304	#define CMDQ_INITIALIZE_FW_TIM_LVL_MASK 0xfUL
305	#define CMDQ_INITIALIZE_FW_TIM_LVL_SFT 0
306	#define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_0 0x0UL
307	#define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_1 0x1UL
308	#define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2 0x2UL
309	#define CMDQ_INITIALIZE_FW_TIM_LVL_LAST CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2
310	#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_MASK 0xf0UL
311	#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_SFT 4
312	#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_4K (0x0UL << 4)
313	#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8K (0x1UL << 4)
314	#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_64K (0x2UL << 4)
315	#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_2M (0x3UL << 4)
316	#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8M (0x4UL << 4)
317	#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G (0x5UL << 4)
318	#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_LAST CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G
319	__le16 log2_dbr_pg_size;
320	#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_MASK 0xfUL
321	#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_SFT 0
322	#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4K 0x0UL
323	#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8K 0x1UL
324	#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16K 0x2UL
325	#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32K 0x3UL
326	#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64K 0x4UL
327	#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128K 0x5UL
328	#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_256K 0x6UL
329	#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_512K 0x7UL
330	#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_1M 0x8UL
331	#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_2M 0x9UL
332	#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4M 0xaUL
333	#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8M 0xbUL
334	#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16M 0xcUL
335	#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32M 0xdUL
336	#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64M 0xeUL
337	#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M 0xfUL
338	#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_LAST \
339	CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M
340	#define CMDQ_INITIALIZE_FW_RSVD_MASK 0xfff0UL
341	#define CMDQ_INITIALIZE_FW_RSVD_SFT 4
342	__le64 qpc_page_dir;
343	__le64 mrw_page_dir;
344	__le64 srq_page_dir;
345	__le64 cq_page_dir;
346	__le64 tqm_page_dir;
347	__le64 tim_page_dir;
348	__le32 number_of_qp;
349	__le32 number_of_mrw;
350	__le32 number_of_srq;
351	__le32 number_of_cq;
352	__le32 max_qp_per_vf;
353	__le32 max_mrw_per_vf;
354	__le32 max_srq_per_vf;
355	__le32 max_cq_per_vf;
356	__le32 max_gid_per_vf;
357	__le32 stat_ctx_id;
358	};
359
360	/* creq_initialize_fw_resp (size:128b/16B) */
361	struct creq_initialize_fw_resp {
362	u8 type;
363	#define CREQ_INITIALIZE_FW_RESP_TYPE_MASK 0x3fUL
364	#define CREQ_INITIALIZE_FW_RESP_TYPE_SFT 0
365	#define CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT 0x38UL
366	#define CREQ_INITIALIZE_FW_RESP_TYPE_LAST CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT
367	u8 status;
368	__le16 cookie;
369	__le32 reserved32;
370	u8 v;
371	#define CREQ_INITIALIZE_FW_RESP_V 0x1UL
372	u8 event;
373	#define CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW 0x80UL
374	#define CREQ_INITIALIZE_FW_RESP_EVENT_LAST \
375	CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW
376	u8 reserved48[6];
377	};
378
379	/* cmdq_deinitialize_fw (size:128b/16B) */
380	struct cmdq_deinitialize_fw {
381	u8 opcode;
382	#define CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW 0x81UL
383	#define CMDQ_DEINITIALIZE_FW_OPCODE_LAST \
384	CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW
385	u8 cmd_size;
386	__le16 flags;
387	__le16 cookie;
388	u8 resp_size;
389	u8 reserved8;
390	__le64 resp_addr;
391	};
392
393	/* creq_deinitialize_fw_resp (size:128b/16B) */
394	struct creq_deinitialize_fw_resp {
395	u8 type;
396	#define CREQ_DEINITIALIZE_FW_RESP_TYPE_MASK 0x3fUL
397	#define CREQ_DEINITIALIZE_FW_RESP_TYPE_SFT 0
398	#define CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT 0x38UL
399	#define CREQ_DEINITIALIZE_FW_RESP_TYPE_LAST CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT
400	u8 status;
401	__le16 cookie;
402	__le32 reserved32;
403	u8 v;
404	#define CREQ_DEINITIALIZE_FW_RESP_V 0x1UL
405	u8 event;
406	#define CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW 0x81UL
407	#define CREQ_DEINITIALIZE_FW_RESP_EVENT_LAST \
408	CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW
409	u8 reserved48[6];
410	};
411
412	/* cmdq_create_qp (size:768b/96B) */
413	struct cmdq_create_qp {
414	u8 opcode;
415	#define CMDQ_CREATE_QP_OPCODE_CREATE_QP 0x1UL
416	#define CMDQ_CREATE_QP_OPCODE_LAST CMDQ_CREATE_QP_OPCODE_CREATE_QP
417	u8 cmd_size;
418	__le16 flags;
419	__le16 cookie;
420	u8 resp_size;
421	u8 reserved8;
422	__le64 resp_addr;
423	__le64 qp_handle;
424	__le32 qp_flags;
425	#define CMDQ_CREATE_QP_QP_FLAGS_SRQ_USED 0x1UL
426	#define CMDQ_CREATE_QP_QP_FLAGS_FORCE_COMPLETION 0x2UL
427	#define CMDQ_CREATE_QP_QP_FLAGS_RESERVED_LKEY_ENABLE 0x4UL
428	#define CMDQ_CREATE_QP_QP_FLAGS_FR_PMR_ENABLED 0x8UL
429	#define CMDQ_CREATE_QP_QP_FLAGS_VARIABLE_SIZED_WQE_ENABLED 0x10UL
430	#define CMDQ_CREATE_QP_QP_FLAGS_OPTIMIZED_TRANSMIT_ENABLED 0x20UL
431	#define CMDQ_CREATE_QP_QP_FLAGS_RESPONDER_UD_CQE_WITH_CFA 0x40UL
432	#define CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_ENABLED 0x80UL
433	#define CMDQ_CREATE_QP_QP_FLAGS_LAST \
434	CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_ENABLED
435	u8 type;
436	#define CMDQ_CREATE_QP_TYPE_RC 0x2UL
437	#define CMDQ_CREATE_QP_TYPE_UD 0x4UL
438	#define CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE 0x6UL
439	#define CMDQ_CREATE_QP_TYPE_GSI 0x7UL
440	#define CMDQ_CREATE_QP_TYPE_LAST CMDQ_CREATE_QP_TYPE_GSI
441	u8 sq_pg_size_sq_lvl;
442	#define CMDQ_CREATE_QP_SQ_LVL_MASK 0xfUL
443	#define CMDQ_CREATE_QP_SQ_LVL_SFT 0
444	#define CMDQ_CREATE_QP_SQ_LVL_LVL_0 0x0UL
445	#define CMDQ_CREATE_QP_SQ_LVL_LVL_1 0x1UL
446	#define CMDQ_CREATE_QP_SQ_LVL_LVL_2 0x2UL
447	#define CMDQ_CREATE_QP_SQ_LVL_LAST CMDQ_CREATE_QP_SQ_LVL_LVL_2
448	#define CMDQ_CREATE_QP_SQ_PG_SIZE_MASK 0xf0UL
449	#define CMDQ_CREATE_QP_SQ_PG_SIZE_SFT 4
450	#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_4K (0x0UL << 4)
451	#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8K (0x1UL << 4)
452	#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_64K (0x2UL << 4)
453	#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_2M (0x3UL << 4)
454	#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8M (0x4UL << 4)
455	#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G (0x5UL << 4)
456	#define CMDQ_CREATE_QP_SQ_PG_SIZE_LAST CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G
457	u8 rq_pg_size_rq_lvl;
458	#define CMDQ_CREATE_QP_RQ_LVL_MASK 0xfUL
459	#define CMDQ_CREATE_QP_RQ_LVL_SFT 0
460	#define CMDQ_CREATE_QP_RQ_LVL_LVL_0 0x0UL
461	#define CMDQ_CREATE_QP_RQ_LVL_LVL_1 0x1UL
462	#define CMDQ_CREATE_QP_RQ_LVL_LVL_2 0x2UL
463	#define CMDQ_CREATE_QP_RQ_LVL_LAST CMDQ_CREATE_QP_RQ_LVL_LVL_2
464	#define CMDQ_CREATE_QP_RQ_PG_SIZE_MASK 0xf0UL
465	#define CMDQ_CREATE_QP_RQ_PG_SIZE_SFT 4
466	#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_4K (0x0UL << 4)
467	#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8K (0x1UL << 4)
468	#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_64K (0x2UL << 4)
469	#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_2M (0x3UL << 4)
470	#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8M (0x4UL << 4)
471	#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G (0x5UL << 4)
472	#define CMDQ_CREATE_QP_RQ_PG_SIZE_LAST CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G
473	u8 unused_0;
474	__le32 dpi;
475	__le32 sq_size;
476	__le32 rq_size;
477	__le16 sq_fwo_sq_sge;
478	#define CMDQ_CREATE_QP_SQ_SGE_MASK 0xfUL
479	#define CMDQ_CREATE_QP_SQ_SGE_SFT 0
480	#define CMDQ_CREATE_QP_SQ_FWO_MASK 0xfff0UL
481	#define CMDQ_CREATE_QP_SQ_FWO_SFT 4
482	__le16 rq_fwo_rq_sge;
483	#define CMDQ_CREATE_QP_RQ_SGE_MASK 0xfUL
484	#define CMDQ_CREATE_QP_RQ_SGE_SFT 0
485	#define CMDQ_CREATE_QP_RQ_FWO_MASK 0xfff0UL
486	#define CMDQ_CREATE_QP_RQ_FWO_SFT 4
487	__le32 scq_cid;
488	__le32 rcq_cid;
489	__le32 srq_cid;
490	__le32 pd_id;
491	__le64 sq_pbl;
492	__le64 rq_pbl;
493	__le64 irrq_addr;
494	__le64 orrq_addr;
495	};
496
497	/* creq_create_qp_resp (size:128b/16B) */
498	struct creq_create_qp_resp {
499	u8 type;
500	#define CREQ_CREATE_QP_RESP_TYPE_MASK 0x3fUL
501	#define CREQ_CREATE_QP_RESP_TYPE_SFT 0
502	#define CREQ_CREATE_QP_RESP_TYPE_QP_EVENT 0x38UL
503	#define CREQ_CREATE_QP_RESP_TYPE_LAST CREQ_CREATE_QP_RESP_TYPE_QP_EVENT
504	u8 status;
505	__le16 cookie;
506	__le32 xid;
507	u8 v;
508	#define CREQ_CREATE_QP_RESP_V 0x1UL
509	u8 event;
510	#define CREQ_CREATE_QP_RESP_EVENT_CREATE_QP 0x1UL
511	#define CREQ_CREATE_QP_RESP_EVENT_LAST CREQ_CREATE_QP_RESP_EVENT_CREATE_QP
512	u8 optimized_transmit_enabled;
513	u8 reserved48[5];
514	};
515
516	/* cmdq_destroy_qp (size:192b/24B) */
517	struct cmdq_destroy_qp {
518	u8 opcode;
519	#define CMDQ_DESTROY_QP_OPCODE_DESTROY_QP 0x2UL
520	#define CMDQ_DESTROY_QP_OPCODE_LAST CMDQ_DESTROY_QP_OPCODE_DESTROY_QP
521	u8 cmd_size;
522	__le16 flags;
523	__le16 cookie;
524	u8 resp_size;
525	u8 reserved8;
526	__le64 resp_addr;
527	__le32 qp_cid;
528	__le32 unused_0;
529	};
530
531	/* creq_destroy_qp_resp (size:128b/16B) */
532	struct creq_destroy_qp_resp {
533	u8 type;
534	#define CREQ_DESTROY_QP_RESP_TYPE_MASK 0x3fUL
535	#define CREQ_DESTROY_QP_RESP_TYPE_SFT 0
536	#define CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT 0x38UL
537	#define CREQ_DESTROY_QP_RESP_TYPE_LAST CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT
538	u8 status;
539	__le16 cookie;
540	__le32 xid;
541	u8 v;
542	#define CREQ_DESTROY_QP_RESP_V 0x1UL
543	u8 event;
544	#define CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP 0x2UL
545	#define CREQ_DESTROY_QP_RESP_EVENT_LAST CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP
546	u8 reserved48[6];
547	};
548
549	/* cmdq_modify_qp (size:1024b/128B) */
550	struct cmdq_modify_qp {
551	u8 opcode;
552	#define CMDQ_MODIFY_QP_OPCODE_MODIFY_QP 0x3UL
553	#define CMDQ_MODIFY_QP_OPCODE_LAST CMDQ_MODIFY_QP_OPCODE_MODIFY_QP
554	u8 cmd_size;
555	__le16 flags;
556	__le16 cookie;
557	u8 resp_size;
558	u8 qp_type;
559	#define CMDQ_MODIFY_QP_QP_TYPE_RC 0x2UL
560	#define CMDQ_MODIFY_QP_QP_TYPE_UD 0x4UL
561	#define CMDQ_MODIFY_QP_QP_TYPE_RAW_ETHERTYPE 0x6UL
562	#define CMDQ_MODIFY_QP_QP_TYPE_GSI 0x7UL
563	#define CMDQ_MODIFY_QP_QP_TYPE_LAST CMDQ_MODIFY_QP_QP_TYPE_GSI
564	__le64 resp_addr;
565	__le32 modify_mask;
566	#define CMDQ_MODIFY_QP_MODIFY_MASK_STATE 0x1UL
567	#define CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY 0x2UL
568	#define CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS 0x4UL
569	#define CMDQ_MODIFY_QP_MODIFY_MASK_PKEY 0x8UL
570	#define CMDQ_MODIFY_QP_MODIFY_MASK_QKEY 0x10UL
571	#define CMDQ_MODIFY_QP_MODIFY_MASK_DGID 0x20UL
572	#define CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL 0x40UL
573	#define CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX 0x80UL
574	#define CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT 0x100UL
575	#define CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS 0x200UL
576	#define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC 0x400UL
577	#define CMDQ_MODIFY_QP_MODIFY_MASK_PINGPONG_PUSH_MODE 0x800UL
578	#define CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU 0x1000UL
579	#define CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT 0x2000UL
580	#define CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT 0x4000UL
581	#define CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY 0x8000UL
582	#define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN 0x10000UL
583	#define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC 0x20000UL
584	#define CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER 0x40000UL
585	#define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN 0x80000UL
586	#define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC 0x100000UL
587	#define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE 0x200000UL
588	#define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE 0x400000UL
589	#define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE 0x800000UL
590	#define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE 0x1000000UL
591	#define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA 0x2000000UL
592	#define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID 0x4000000UL
593	#define CMDQ_MODIFY_QP_MODIFY_MASK_SRC_MAC 0x8000000UL
594	#define CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID 0x10000000UL
595	#define CMDQ_MODIFY_QP_MODIFY_MASK_ENABLE_CC 0x20000000UL
596	#define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_ECN 0x40000000UL
597	#define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_DSCP 0x80000000UL
598	__le32 qp_cid;
599	u8 network_type_en_sqd_async_notify_new_state;
600	#define CMDQ_MODIFY_QP_NEW_STATE_MASK 0xfUL
601	#define CMDQ_MODIFY_QP_NEW_STATE_SFT 0
602	#define CMDQ_MODIFY_QP_NEW_STATE_RESET 0x0UL
603	#define CMDQ_MODIFY_QP_NEW_STATE_INIT 0x1UL
604	#define CMDQ_MODIFY_QP_NEW_STATE_RTR 0x2UL
605	#define CMDQ_MODIFY_QP_NEW_STATE_RTS 0x3UL
606	#define CMDQ_MODIFY_QP_NEW_STATE_SQD 0x4UL
607	#define CMDQ_MODIFY_QP_NEW_STATE_SQE 0x5UL
608	#define CMDQ_MODIFY_QP_NEW_STATE_ERR 0x6UL
609	#define CMDQ_MODIFY_QP_NEW_STATE_LAST CMDQ_MODIFY_QP_NEW_STATE_ERR
610	#define CMDQ_MODIFY_QP_EN_SQD_ASYNC_NOTIFY 0x10UL
611	#define CMDQ_MODIFY_QP_UNUSED1 0x20UL
612	#define CMDQ_MODIFY_QP_NETWORK_TYPE_MASK 0xc0UL
613	#define CMDQ_MODIFY_QP_NETWORK_TYPE_SFT 6
614	#define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1 (0x0UL << 6)
615	#define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4 (0x2UL << 6)
616	#define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6 (0x3UL << 6)
617	#define CMDQ_MODIFY_QP_NETWORK_TYPE_LAST CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6
618	u8 access;
619	#define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK 0xffUL
620	#define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT 0
621	#define CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE 0x1UL
622	#define CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE 0x2UL
623	#define CMDQ_MODIFY_QP_ACCESS_REMOTE_READ 0x4UL
624	#define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC 0x8UL
625	__le16 pkey;
626	__le32 qkey;
627	__le32 dgid[4];
628	__le32 flow_label;
629	__le16 sgid_index;
630	u8 hop_limit;
631	u8 traffic_class;
632	__le16 dest_mac[3];
633	u8 tos_dscp_tos_ecn;
634	#define CMDQ_MODIFY_QP_TOS_ECN_MASK 0x3UL
635	#define CMDQ_MODIFY_QP_TOS_ECN_SFT 0
636	#define CMDQ_MODIFY_QP_TOS_DSCP_MASK 0xfcUL
637	#define CMDQ_MODIFY_QP_TOS_DSCP_SFT 2
638	u8 path_mtu_pingpong_push_enable;
639	#define CMDQ_MODIFY_QP_PINGPONG_PUSH_ENABLE 0x1UL
640	#define CMDQ_MODIFY_QP_UNUSED3_MASK 0xeUL
641	#define CMDQ_MODIFY_QP_UNUSED3_SFT 1
642	#define CMDQ_MODIFY_QP_PATH_MTU_MASK 0xf0UL
643	#define CMDQ_MODIFY_QP_PATH_MTU_SFT 4
644	#define CMDQ_MODIFY_QP_PATH_MTU_MTU_256 (0x0UL << 4)
645	#define CMDQ_MODIFY_QP_PATH_MTU_MTU_512 (0x1UL << 4)
646	#define CMDQ_MODIFY_QP_PATH_MTU_MTU_1024 (0x2UL << 4)
647	#define CMDQ_MODIFY_QP_PATH_MTU_MTU_2048 (0x3UL << 4)
648	#define CMDQ_MODIFY_QP_PATH_MTU_MTU_4096 (0x4UL << 4)
649	#define CMDQ_MODIFY_QP_PATH_MTU_MTU_8192 (0x5UL << 4)
650	#define CMDQ_MODIFY_QP_PATH_MTU_LAST CMDQ_MODIFY_QP_PATH_MTU_MTU_8192
651	u8 timeout;
652	u8 retry_cnt;
653	u8 rnr_retry;
654	u8 min_rnr_timer;
655	__le32 rq_psn;
656	__le32 sq_psn;
657	u8 max_rd_atomic;
658	u8 max_dest_rd_atomic;
659	__le16 enable_cc;
660	#define CMDQ_MODIFY_QP_ENABLE_CC 0x1UL
661	#define CMDQ_MODIFY_QP_UNUSED15_MASK 0xfffeUL
662	#define CMDQ_MODIFY_QP_UNUSED15_SFT 1
663	__le32 sq_size;
664	__le32 rq_size;
665	__le16 sq_sge;
666	__le16 rq_sge;
667	__le32 max_inline_data;
668	__le32 dest_qp_id;
669	__le32 pingpong_push_dpi;
670	__le16 src_mac[3];
671	__le16 vlan_pcp_vlan_dei_vlan_id;
672	#define CMDQ_MODIFY_QP_VLAN_ID_MASK 0xfffUL
673	#define CMDQ_MODIFY_QP_VLAN_ID_SFT 0
674	#define CMDQ_MODIFY_QP_VLAN_DEI 0x1000UL
675	#define CMDQ_MODIFY_QP_VLAN_PCP_MASK 0xe000UL
676	#define CMDQ_MODIFY_QP_VLAN_PCP_SFT 13
677	__le64 irrq_addr;
678	__le64 orrq_addr;
679	__le32 ext_modify_mask;
680	#define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_EXT_STATS_CTX 0x1UL
681	#define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_SCHQ_ID_VALID 0x2UL
682	__le32 ext_stats_ctx_id;
683	__le16 schq_id;
684	__le16 unused_0;
685	__le32 reserved32;
686	};
687
688	/* creq_modify_qp_resp (size:128b/16B) */
689	struct creq_modify_qp_resp {
690	u8 type;
691	#define CREQ_MODIFY_QP_RESP_TYPE_MASK 0x3fUL
692	#define CREQ_MODIFY_QP_RESP_TYPE_SFT 0
693	#define CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT 0x38UL
694	#define CREQ_MODIFY_QP_RESP_TYPE_LAST CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT
695	u8 status;
696	__le16 cookie;
697	__le32 xid;
698	u8 v;
699	#define CREQ_MODIFY_QP_RESP_V 0x1UL
700	u8 event;
701	#define CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP 0x3UL
702	#define CREQ_MODIFY_QP_RESP_EVENT_LAST CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP
703	u8 pingpong_push_state_index_enabled;
704	#define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_ENABLED 0x1UL
705	#define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_MASK 0xeUL
706	#define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_SFT 1
707	#define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_STATE 0x10UL
708	u8 reserved8;
709	__le32 lag_src_mac;
710	};
711
712	/* cmdq_query_qp (size:192b/24B) */
713	struct cmdq_query_qp {
714	u8 opcode;
715	#define CMDQ_QUERY_QP_OPCODE_QUERY_QP 0x4UL
716	#define CMDQ_QUERY_QP_OPCODE_LAST CMDQ_QUERY_QP_OPCODE_QUERY_QP
717	u8 cmd_size;
718	__le16 flags;
719	__le16 cookie;
720	u8 resp_size;
721	u8 reserved8;
722	__le64 resp_addr;
723	__le32 qp_cid;
724	__le32 unused_0;
725	};
726
727	/* creq_query_qp_resp (size:128b/16B) */
728	struct creq_query_qp_resp {
729	u8 type;
730	#define CREQ_QUERY_QP_RESP_TYPE_MASK 0x3fUL
731	#define CREQ_QUERY_QP_RESP_TYPE_SFT 0
732	#define CREQ_QUERY_QP_RESP_TYPE_QP_EVENT 0x38UL
733	#define CREQ_QUERY_QP_RESP_TYPE_LAST CREQ_QUERY_QP_RESP_TYPE_QP_EVENT
734	u8 status;
735	__le16 cookie;
736	__le32 size;
737	u8 v;
738	#define CREQ_QUERY_QP_RESP_V 0x1UL
739	u8 event;
740	#define CREQ_QUERY_QP_RESP_EVENT_QUERY_QP 0x4UL
741	#define CREQ_QUERY_QP_RESP_EVENT_LAST CREQ_QUERY_QP_RESP_EVENT_QUERY_QP
742	u8 reserved48[6];
743	};
744
745	/* creq_query_qp_resp_sb (size:832b/104B) */
746	struct creq_query_qp_resp_sb {
747	u8 opcode;
748	#define CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP 0x4UL
749	#define CREQ_QUERY_QP_RESP_SB_OPCODE_LAST CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP
750	u8 status;
751	__le16 cookie;
752	__le16 flags;
753	u8 resp_size;
754	u8 reserved8;
755	__le32 xid;
756	u8 en_sqd_async_notify_state;
757	#define CREQ_QUERY_QP_RESP_SB_STATE_MASK 0xfUL
758	#define CREQ_QUERY_QP_RESP_SB_STATE_SFT 0
759	#define CREQ_QUERY_QP_RESP_SB_STATE_RESET 0x0UL
760	#define CREQ_QUERY_QP_RESP_SB_STATE_INIT 0x1UL
761	#define CREQ_QUERY_QP_RESP_SB_STATE_RTR 0x2UL
762	#define CREQ_QUERY_QP_RESP_SB_STATE_RTS 0x3UL
763	#define CREQ_QUERY_QP_RESP_SB_STATE_SQD 0x4UL
764	#define CREQ_QUERY_QP_RESP_SB_STATE_SQE 0x5UL
765	#define CREQ_QUERY_QP_RESP_SB_STATE_ERR 0x6UL
766	#define CREQ_QUERY_QP_RESP_SB_STATE_LAST CREQ_QUERY_QP_RESP_SB_STATE_ERR
767	#define CREQ_QUERY_QP_RESP_SB_EN_SQD_ASYNC_NOTIFY 0x10UL
768	#define CREQ_QUERY_QP_RESP_SB_UNUSED3_MASK 0xe0UL
769	#define CREQ_QUERY_QP_RESP_SB_UNUSED3_SFT 5
770	u8 access;
771	#define \
772	CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK\
773	0xffUL
774	#define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT\
775	0
776	#define CREQ_QUERY_QP_RESP_SB_ACCESS_LOCAL_WRITE 0x1UL
777	#define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_WRITE 0x2UL
778	#define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_READ 0x4UL
779	#define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC 0x8UL
780	__le16 pkey;
781	__le32 qkey;
782	__le32 reserved32;
783	__le32 dgid[4];
784	__le32 flow_label;
785	__le16 sgid_index;
786	u8 hop_limit;
787	u8 traffic_class;
788	__le16 dest_mac[3];
789	__le16 path_mtu_dest_vlan_id;
790	#define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_MASK 0xfffUL
791	#define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_SFT 0
792	#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK 0xf000UL
793	#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_SFT 12
794	#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_256 (0x0UL << 12)
795	#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_512 (0x1UL << 12)
796	#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_1024 (0x2UL << 12)
797	#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_2048 (0x3UL << 12)
798	#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_4096 (0x4UL << 12)
799	#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192 (0x5UL << 12)
800	#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_LAST CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192
801	u8 timeout;
802	u8 retry_cnt;
803	u8 rnr_retry;
804	u8 min_rnr_timer;
805	__le32 rq_psn;
806	__le32 sq_psn;
807	u8 max_rd_atomic;
808	u8 max_dest_rd_atomic;
809	u8 tos_dscp_tos_ecn;
810	#define CREQ_QUERY_QP_RESP_SB_TOS_ECN_MASK 0x3UL
811	#define CREQ_QUERY_QP_RESP_SB_TOS_ECN_SFT 0
812	#define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_MASK 0xfcUL
813	#define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_SFT 2
814	u8 enable_cc;
815	#define CREQ_QUERY_QP_RESP_SB_ENABLE_CC 0x1UL
816	__le32 sq_size;
817	__le32 rq_size;
818	__le16 sq_sge;
819	__le16 rq_sge;
820	__le32 max_inline_data;
821	__le32 dest_qp_id;
822	__le16 port_id;
823	u8 unused_0;
824	u8 stat_collection_id;
825	__le16 src_mac[3];
826	__le16 vlan_pcp_vlan_dei_vlan_id;
827	#define CREQ_QUERY_QP_RESP_SB_VLAN_ID_MASK 0xfffUL
828	#define CREQ_QUERY_QP_RESP_SB_VLAN_ID_SFT 0
829	#define CREQ_QUERY_QP_RESP_SB_VLAN_DEI 0x1000UL
830	#define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_MASK 0xe000UL
831	#define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_SFT 13
832	};
833
834	/* cmdq_query_qp_extend (size:192b/24B) */
835	struct cmdq_query_qp_extend {
836	u8 opcode;
837	#define CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND 0x91UL
838	#define CMDQ_QUERY_QP_EXTEND_OPCODE_LAST CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND
839	u8 cmd_size;
840	__le16 flags;
841	__le16 cookie;
842	u8 resp_size;
843	u8 num_qps;
844	__le64 resp_addr;
845	__le32 function_id;
846	#define CMDQ_QUERY_QP_EXTEND_PF_NUM_MASK 0xffUL
847	#define CMDQ_QUERY_QP_EXTEND_PF_NUM_SFT 0
848	#define CMDQ_QUERY_QP_EXTEND_VF_NUM_MASK 0xffff00UL
849	#define CMDQ_QUERY_QP_EXTEND_VF_NUM_SFT 8
850	#define CMDQ_QUERY_QP_EXTEND_VF_VALID 0x1000000UL
851	__le32 current_index;
852	};
853
854	/* creq_query_qp_extend_resp (size:128b/16B) */
855	struct creq_query_qp_extend_resp {
856	u8 type;
857	#define CREQ_QUERY_QP_EXTEND_RESP_TYPE_MASK 0x3fUL
858	#define CREQ_QUERY_QP_EXTEND_RESP_TYPE_SFT 0
859	#define CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT 0x38UL
860	#define CREQ_QUERY_QP_EXTEND_RESP_TYPE_LAST CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT
861	u8 status;
862	__le16 cookie;
863	__le32 size;
864	u8 v;
865	#define CREQ_QUERY_QP_EXTEND_RESP_V 0x1UL
866	u8 event;
867	#define CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND 0x91UL
868	#define CREQ_QUERY_QP_EXTEND_RESP_EVENT_LAST CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND
869	__le16 reserved16;
870	__le32 current_index;
871	};
872
873	/* creq_query_qp_extend_resp_sb (size:384b/48B) */
874	struct creq_query_qp_extend_resp_sb {
875	u8 opcode;
876	#define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND 0x91UL
877	#define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_LAST \
878	CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND
879	u8 status;
880	__le16 cookie;
881	__le16 flags;
882	u8 resp_size;
883	u8 reserved8;
884	__le32 xid;
885	u8 state;
886	#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_MASK 0xfUL
887	#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SFT 0
888	#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RESET 0x0UL
889	#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_INIT 0x1UL
890	#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTR 0x2UL
891	#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTS 0x3UL
892	#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQD 0x4UL
893	#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQE 0x5UL
894	#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR 0x6UL
895	#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR
896	#define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_MASK 0xf0UL
897	#define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_SFT 4
898	u8 reserved_8;
899	__le16 port_id;
900	__le32 qkey;
901	__le16 sgid_index;
902	u8 network_type;
903	#define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV1 0x0UL
904	#define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV4 0x2UL
905	#define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6 0x3UL
906	#define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_LAST \
907	CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6
908	u8 unused_0;
909	__le32 dgid[4];
910	__le32 dest_qp_id;
911	u8 stat_collection_id;
912	u8 reservred_8;
913	__le16 reserved_16;
914	};
915
916	/* creq_query_qp_extend_resp_sb_tlv (size:512b/64B) */
917	struct creq_query_qp_extend_resp_sb_tlv {
918	__le16 cmd_discr;
919	u8 reserved_8b;
920	u8 tlv_flags;
921	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL
922	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL
923	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL
924	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL
925	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
926	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
927	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST \
928	CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES
929	__le16 tlv_type;
930	__le16 length;
931	u8 total_size;
932	u8 reserved56[7];
933	u8 opcode;
934	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND 0x91UL
935	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_LAST \
936	CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND
937	u8 status;
938	__le16 cookie;
939	__le16 flags;
940	u8 resp_size;
941	u8 reserved8;
942	__le32 xid;
943	u8 state;
944	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_MASK 0xfUL
945	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SFT 0
946	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RESET 0x0UL
947	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_INIT 0x1UL
948	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTR 0x2UL
949	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTS 0x3UL
950	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQD 0x4UL
951	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQE 0x5UL
952	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR 0x6UL
953	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_LAST \
954	CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR
955	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_MASK 0xf0UL
956	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_SFT 4
957	u8 reserved_8;
958	__le16 port_id;
959	__le32 qkey;
960	__le16 sgid_index;
961	u8 network_type;
962	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV1 0x0UL
963	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV4 0x2UL
964	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6 0x3UL
965	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_LAST \
966	CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6
967	u8 unused_0;
968	__le32 dgid[4];
969	__le32 dest_qp_id;
970	u8 stat_collection_id;
971	u8 reservred_8;
972	__le16 reserved_16;
973	};
974
975	/* cmdq_create_srq (size:384b/48B) */
976	struct cmdq_create_srq {
977	u8 opcode;
978	#define CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ 0x5UL
979	#define CMDQ_CREATE_SRQ_OPCODE_LAST CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ
980	u8 cmd_size;
981	__le16 flags;
982	__le16 cookie;
983	u8 resp_size;
984	u8 reserved8;
985	__le64 resp_addr;
986	__le64 srq_handle;
987	__le16 pg_size_lvl;
988	#define CMDQ_CREATE_SRQ_LVL_MASK 0x3UL
989	#define CMDQ_CREATE_SRQ_LVL_SFT 0
990	#define CMDQ_CREATE_SRQ_LVL_LVL_0 0x0UL
991	#define CMDQ_CREATE_SRQ_LVL_LVL_1 0x1UL
992	#define CMDQ_CREATE_SRQ_LVL_LVL_2 0x2UL
993	#define CMDQ_CREATE_SRQ_LVL_LAST CMDQ_CREATE_SRQ_LVL_LVL_2
994	#define CMDQ_CREATE_SRQ_PG_SIZE_MASK 0x1cUL
995	#define CMDQ_CREATE_SRQ_PG_SIZE_SFT 2
996	#define CMDQ_CREATE_SRQ_PG_SIZE_PG_4K (0x0UL << 2)
997	#define CMDQ_CREATE_SRQ_PG_SIZE_PG_8K (0x1UL << 2)
998	#define CMDQ_CREATE_SRQ_PG_SIZE_PG_64K (0x2UL << 2)
999	#define CMDQ_CREATE_SRQ_PG_SIZE_PG_2M (0x3UL << 2)
1000	#define CMDQ_CREATE_SRQ_PG_SIZE_PG_8M (0x4UL << 2)
1001	#define CMDQ_CREATE_SRQ_PG_SIZE_PG_1G (0x5UL << 2)
1002	#define CMDQ_CREATE_SRQ_PG_SIZE_LAST CMDQ_CREATE_SRQ_PG_SIZE_PG_1G
1003	#define CMDQ_CREATE_SRQ_UNUSED11_MASK 0xffe0UL
1004	#define CMDQ_CREATE_SRQ_UNUSED11_SFT 5
1005	__le16 eventq_id;
1006	#define CMDQ_CREATE_SRQ_EVENTQ_ID_MASK 0xfffUL
1007	#define CMDQ_CREATE_SRQ_EVENTQ_ID_SFT 0
1008	#define CMDQ_CREATE_SRQ_UNUSED4_MASK 0xf000UL
1009	#define CMDQ_CREATE_SRQ_UNUSED4_SFT 12
1010	__le16 srq_size;
1011	__le16 srq_fwo;
1012	__le32 dpi;
1013	__le32 pd_id;
1014	__le64 pbl;
1015	};
1016
1017	/* creq_create_srq_resp (size:128b/16B) */
1018	struct creq_create_srq_resp {
1019	u8 type;
1020	#define CREQ_CREATE_SRQ_RESP_TYPE_MASK 0x3fUL
1021	#define CREQ_CREATE_SRQ_RESP_TYPE_SFT 0
1022	#define CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT 0x38UL
1023	#define CREQ_CREATE_SRQ_RESP_TYPE_LAST CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT
1024	u8 status;
1025	__le16 cookie;
1026	__le32 xid;
1027	u8 v;
1028	#define CREQ_CREATE_SRQ_RESP_V 0x1UL
1029	u8 event;
1030	#define CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ 0x5UL
1031	#define CREQ_CREATE_SRQ_RESP_EVENT_LAST CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ
1032	u8 reserved48[6];
1033	};
1034
1035	/* cmdq_destroy_srq (size:192b/24B) */
1036	struct cmdq_destroy_srq {
1037	u8 opcode;
1038	#define CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ 0x6UL
1039	#define CMDQ_DESTROY_SRQ_OPCODE_LAST CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ
1040	u8 cmd_size;
1041	__le16 flags;
1042	__le16 cookie;
1043	u8 resp_size;
1044	u8 reserved8;
1045	__le64 resp_addr;
1046	__le32 srq_cid;
1047	__le32 unused_0;
1048	};
1049
1050	/* creq_destroy_srq_resp (size:128b/16B) */
1051	struct creq_destroy_srq_resp {
1052	u8 type;
1053	#define CREQ_DESTROY_SRQ_RESP_TYPE_MASK 0x3fUL
1054	#define CREQ_DESTROY_SRQ_RESP_TYPE_SFT 0
1055	#define CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT 0x38UL
1056	#define CREQ_DESTROY_SRQ_RESP_TYPE_LAST CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT
1057	u8 status;
1058	__le16 cookie;
1059	__le32 xid;
1060	u8 v;
1061	#define CREQ_DESTROY_SRQ_RESP_V 0x1UL
1062	u8 event;
1063	#define CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ 0x6UL
1064	#define CREQ_DESTROY_SRQ_RESP_EVENT_LAST CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ
1065	__le16 enable_for_arm[3];
1066	#define CREQ_DESTROY_SRQ_RESP_UNUSED0_MASK 0xffffUL
1067	#define CREQ_DESTROY_SRQ_RESP_UNUSED0_SFT 0
1068	#define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_MASK 0x30000UL
1069	#define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_SFT 16
1070	};
1071
1072	/* cmdq_query_srq (size:192b/24B) */
1073	struct cmdq_query_srq {
1074	u8 opcode;
1075	#define CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ 0x8UL
1076	#define CMDQ_QUERY_SRQ_OPCODE_LAST CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ
1077	u8 cmd_size;
1078	__le16 flags;
1079	__le16 cookie;
1080	u8 resp_size;
1081	u8 reserved8;
1082	__le64 resp_addr;
1083	__le32 srq_cid;
1084	__le32 unused_0;
1085	};
1086
1087	/* creq_query_srq_resp (size:128b/16B) */
1088	struct creq_query_srq_resp {
1089	u8 type;
1090	#define CREQ_QUERY_SRQ_RESP_TYPE_MASK 0x3fUL
1091	#define CREQ_QUERY_SRQ_RESP_TYPE_SFT 0
1092	#define CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT 0x38UL
1093	#define CREQ_QUERY_SRQ_RESP_TYPE_LAST CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT
1094	u8 status;
1095	__le16 cookie;
1096	__le32 size;
1097	u8 v;
1098	#define CREQ_QUERY_SRQ_RESP_V 0x1UL
1099	u8 event;
1100	#define CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ 0x8UL
1101	#define CREQ_QUERY_SRQ_RESP_EVENT_LAST CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ
1102	u8 reserved48[6];
1103	};
1104
1105	/* creq_query_srq_resp_sb (size:256b/32B) */
1106	struct creq_query_srq_resp_sb {
1107	u8 opcode;
1108	#define CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ 0x8UL
1109	#define CREQ_QUERY_SRQ_RESP_SB_OPCODE_LAST CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ
1110	u8 status;
1111	__le16 cookie;
1112	__le16 flags;
1113	u8 resp_size;
1114	u8 reserved8;
1115	__le32 xid;
1116	__le16 srq_limit;
1117	__le16 reserved16;
1118	__le32 data[4];
1119	};
1120
1121	/* cmdq_create_cq (size:384b/48B) */
1122	struct cmdq_create_cq {
1123	u8 opcode;
1124	#define CMDQ_CREATE_CQ_OPCODE_CREATE_CQ 0x9UL
1125	#define CMDQ_CREATE_CQ_OPCODE_LAST CMDQ_CREATE_CQ_OPCODE_CREATE_CQ
1126	u8 cmd_size;
1127	__le16 flags;
1128	#define CMDQ_CREATE_CQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION 0x1UL
1129	__le16 cookie;
1130	u8 resp_size;
1131	u8 reserved8;
1132	__le64 resp_addr;
1133	__le64 cq_handle;
1134	__le32 pg_size_lvl;
1135	#define CMDQ_CREATE_CQ_LVL_MASK 0x3UL
1136	#define CMDQ_CREATE_CQ_LVL_SFT 0
1137	#define CMDQ_CREATE_CQ_LVL_LVL_0 0x0UL
1138	#define CMDQ_CREATE_CQ_LVL_LVL_1 0x1UL
1139	#define CMDQ_CREATE_CQ_LVL_LVL_2 0x2UL
1140	#define CMDQ_CREATE_CQ_LVL_LAST CMDQ_CREATE_CQ_LVL_LVL_2
1141	#define CMDQ_CREATE_CQ_PG_SIZE_MASK 0x1cUL
1142	#define CMDQ_CREATE_CQ_PG_SIZE_SFT 2
1143	#define CMDQ_CREATE_CQ_PG_SIZE_PG_4K (0x0UL << 2)
1144	#define CMDQ_CREATE_CQ_PG_SIZE_PG_8K (0x1UL << 2)
1145	#define CMDQ_CREATE_CQ_PG_SIZE_PG_64K (0x2UL << 2)
1146	#define CMDQ_CREATE_CQ_PG_SIZE_PG_2M (0x3UL << 2)
1147	#define CMDQ_CREATE_CQ_PG_SIZE_PG_8M (0x4UL << 2)
1148	#define CMDQ_CREATE_CQ_PG_SIZE_PG_1G (0x5UL << 2)
1149	#define CMDQ_CREATE_CQ_PG_SIZE_LAST CMDQ_CREATE_CQ_PG_SIZE_PG_1G
1150	#define CMDQ_CREATE_CQ_UNUSED27_MASK 0xffffffe0UL
1151	#define CMDQ_CREATE_CQ_UNUSED27_SFT 5
1152	__le32 cq_fco_cnq_id;
1153	#define CMDQ_CREATE_CQ_CNQ_ID_MASK 0xfffUL
1154	#define CMDQ_CREATE_CQ_CNQ_ID_SFT 0
1155	#define CMDQ_CREATE_CQ_CQ_FCO_MASK 0xfffff000UL
1156	#define CMDQ_CREATE_CQ_CQ_FCO_SFT 12
1157	__le32 dpi;
1158	__le32 cq_size;
1159	__le64 pbl;
1160	};
1161
1162	/* creq_create_cq_resp (size:128b/16B) */
1163	struct creq_create_cq_resp {
1164	u8 type;
1165	#define CREQ_CREATE_CQ_RESP_TYPE_MASK 0x3fUL
1166	#define CREQ_CREATE_CQ_RESP_TYPE_SFT 0
1167	#define CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT 0x38UL
1168	#define CREQ_CREATE_CQ_RESP_TYPE_LAST CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT
1169	u8 status;
1170	__le16 cookie;
1171	__le32 xid;
1172	u8 v;
1173	#define CREQ_CREATE_CQ_RESP_V 0x1UL
1174	u8 event;
1175	#define CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ 0x9UL
1176	#define CREQ_CREATE_CQ_RESP_EVENT_LAST CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ
1177	u8 reserved48[6];
1178	};
1179
1180	/* cmdq_destroy_cq (size:192b/24B) */
1181	struct cmdq_destroy_cq {
1182	u8 opcode;
1183	#define CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ 0xaUL
1184	#define CMDQ_DESTROY_CQ_OPCODE_LAST CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ
1185	u8 cmd_size;
1186	__le16 flags;
1187	__le16 cookie;
1188	u8 resp_size;
1189	u8 reserved8;
1190	__le64 resp_addr;
1191	__le32 cq_cid;
1192	__le32 unused_0;
1193	};
1194
1195	/* creq_destroy_cq_resp (size:128b/16B) */
1196	struct creq_destroy_cq_resp {
1197	u8 type;
1198	#define CREQ_DESTROY_CQ_RESP_TYPE_MASK 0x3fUL
1199	#define CREQ_DESTROY_CQ_RESP_TYPE_SFT 0
1200	#define CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT 0x38UL
1201	#define CREQ_DESTROY_CQ_RESP_TYPE_LAST CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT
1202	u8 status;
1203	__le16 cookie;
1204	__le32 xid;
1205	u8 v;
1206	#define CREQ_DESTROY_CQ_RESP_V 0x1UL
1207	u8 event;
1208	#define CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ 0xaUL
1209	#define CREQ_DESTROY_CQ_RESP_EVENT_LAST CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ
1210	__le16 cq_arm_lvl;
1211	#define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_MASK 0x3UL
1212	#define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_SFT 0
1213	__le16 total_cnq_events;
1214	__le16 reserved16;
1215	};
1216
1217	/* cmdq_resize_cq (size:320b/40B) */
1218	struct cmdq_resize_cq {
1219	u8 opcode;
1220	#define CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ 0xcUL
1221	#define CMDQ_RESIZE_CQ_OPCODE_LAST CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ
1222	u8 cmd_size;
1223	__le16 flags;
1224	__le16 cookie;
1225	u8 resp_size;
1226	u8 reserved8;
1227	__le64 resp_addr;
1228	__le32 cq_cid;
1229	__le32 new_cq_size_pg_size_lvl;
1230	#define CMDQ_RESIZE_CQ_LVL_MASK 0x3UL
1231	#define CMDQ_RESIZE_CQ_LVL_SFT 0
1232	#define CMDQ_RESIZE_CQ_LVL_LVL_0 0x0UL
1233	#define CMDQ_RESIZE_CQ_LVL_LVL_1 0x1UL
1234	#define CMDQ_RESIZE_CQ_LVL_LVL_2 0x2UL
1235	#define CMDQ_RESIZE_CQ_LVL_LAST CMDQ_RESIZE_CQ_LVL_LVL_2
1236	#define CMDQ_RESIZE_CQ_PG_SIZE_MASK 0x1cUL
1237	#define CMDQ_RESIZE_CQ_PG_SIZE_SFT 2
1238	#define CMDQ_RESIZE_CQ_PG_SIZE_PG_4K (0x0UL << 2)
1239	#define CMDQ_RESIZE_CQ_PG_SIZE_PG_8K (0x1UL << 2)
1240	#define CMDQ_RESIZE_CQ_PG_SIZE_PG_64K (0x2UL << 2)
1241	#define CMDQ_RESIZE_CQ_PG_SIZE_PG_2M (0x3UL << 2)
1242	#define CMDQ_RESIZE_CQ_PG_SIZE_PG_8M (0x4UL << 2)
1243	#define CMDQ_RESIZE_CQ_PG_SIZE_PG_1G (0x5UL << 2)
1244	#define CMDQ_RESIZE_CQ_PG_SIZE_LAST CMDQ_RESIZE_CQ_PG_SIZE_PG_1G
1245	#define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_MASK 0x1fffffe0UL
1246	#define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_SFT 5
1247	__le64 new_pbl;
1248	__le32 new_cq_fco;
1249	__le32 unused_0;
1250	};
1251
1252	/* creq_resize_cq_resp (size:128b/16B) */
1253	struct creq_resize_cq_resp {
1254	u8 type;
1255	#define CREQ_RESIZE_CQ_RESP_TYPE_MASK 0x3fUL
1256	#define CREQ_RESIZE_CQ_RESP_TYPE_SFT 0
1257	#define CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT 0x38UL
1258	#define CREQ_RESIZE_CQ_RESP_TYPE_LAST CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT
1259	u8 status;
1260	__le16 cookie;
1261	__le32 xid;
1262	u8 v;
1263	#define CREQ_RESIZE_CQ_RESP_V 0x1UL
1264	u8 event;
1265	#define CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ 0xcUL
1266	#define CREQ_RESIZE_CQ_RESP_EVENT_LAST CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ
1267	u8 reserved48[6];
1268	};
1269
1270	/* cmdq_allocate_mrw (size:256b/32B) */
1271	struct cmdq_allocate_mrw {
1272	u8 opcode;
1273	#define CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW 0xdUL
1274	#define CMDQ_ALLOCATE_MRW_OPCODE_LAST CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW
1275	u8 cmd_size;
1276	__le16 flags;
1277	__le16 cookie;
1278	u8 resp_size;
1279	u8 reserved8;
1280	__le64 resp_addr;
1281	__le64 mrw_handle;
1282	u8 mrw_flags;
1283	#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MASK 0xfUL
1284	#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_SFT 0
1285	#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR 0x0UL
1286	#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR 0x1UL
1287	#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 0x2UL
1288	#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A 0x3UL
1289	#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B 0x4UL
1290	#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_LAST CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B
1291	#define CMDQ_ALLOCATE_MRW_UNUSED4_MASK 0xf0UL
1292	#define CMDQ_ALLOCATE_MRW_UNUSED4_SFT 4
1293	u8 access;
1294	#define CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY 0x20UL
1295	__le16 unused16;
1296	__le32 pd_id;
1297	};
1298
1299	/* creq_allocate_mrw_resp (size:128b/16B) */
1300	struct creq_allocate_mrw_resp {
1301	u8 type;
1302	#define CREQ_ALLOCATE_MRW_RESP_TYPE_MASK 0x3fUL
1303	#define CREQ_ALLOCATE_MRW_RESP_TYPE_SFT 0
1304	#define CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT 0x38UL
1305	#define CREQ_ALLOCATE_MRW_RESP_TYPE_LAST CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT
1306	u8 status;
1307	__le16 cookie;
1308	__le32 xid;
1309	u8 v;
1310	#define CREQ_ALLOCATE_MRW_RESP_V 0x1UL
1311	u8 event;
1312	#define CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW 0xdUL
1313	#define CREQ_ALLOCATE_MRW_RESP_EVENT_LAST CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW
1314	u8 reserved48[6];
1315	};
1316
1317	/* cmdq_deallocate_key (size:192b/24B) */
1318	struct cmdq_deallocate_key {
1319	u8 opcode;
1320	#define CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY 0xeUL
1321	#define CMDQ_DEALLOCATE_KEY_OPCODE_LAST CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY
1322	u8 cmd_size;
1323	__le16 flags;
1324	__le16 cookie;
1325	u8 resp_size;
1326	u8 reserved8;
1327	__le64 resp_addr;
1328	u8 mrw_flags;
1329	#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MASK 0xfUL
1330	#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_SFT 0
1331	#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MR 0x0UL
1332	#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_PMR 0x1UL
1333	#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE1 0x2UL
1334	#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2A 0x3UL
1335	#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B 0x4UL
1336	#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_LAST CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B
1337	#define CMDQ_DEALLOCATE_KEY_UNUSED4_MASK 0xf0UL
1338	#define CMDQ_DEALLOCATE_KEY_UNUSED4_SFT 4
1339	u8 unused24[3];
1340	__le32 key;
1341	};
1342
1343	/* creq_deallocate_key_resp (size:128b/16B) */
1344	struct creq_deallocate_key_resp {
1345	u8 type;
1346	#define CREQ_DEALLOCATE_KEY_RESP_TYPE_MASK 0x3fUL
1347	#define CREQ_DEALLOCATE_KEY_RESP_TYPE_SFT 0
1348	#define CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT 0x38UL
1349	#define CREQ_DEALLOCATE_KEY_RESP_TYPE_LAST CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT
1350	u8 status;
1351	__le16 cookie;
1352	__le32 xid;
1353	u8 v;
1354	#define CREQ_DEALLOCATE_KEY_RESP_V 0x1UL
1355	u8 event;
1356	#define CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY 0xeUL
1357	#define CREQ_DEALLOCATE_KEY_RESP_EVENT_LAST CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY
1358	__le16 reserved16;
1359	__le32 bound_window_info;
1360	};
1361
1362	/* cmdq_register_mr (size:384b/48B) */
1363	struct cmdq_register_mr {
1364	u8 opcode;
1365	#define CMDQ_REGISTER_MR_OPCODE_REGISTER_MR 0xfUL
1366	#define CMDQ_REGISTER_MR_OPCODE_LAST CMDQ_REGISTER_MR_OPCODE_REGISTER_MR
1367	u8 cmd_size;
1368	__le16 flags;
1369	#define CMDQ_REGISTER_MR_FLAGS_ALLOC_MR 0x1UL
1370	__le16 cookie;
1371	u8 resp_size;
1372	u8 reserved8;
1373	__le64 resp_addr;
1374	u8 log2_pg_size_lvl;
1375	#define CMDQ_REGISTER_MR_LVL_MASK 0x3UL
1376	#define CMDQ_REGISTER_MR_LVL_SFT 0
1377	#define CMDQ_REGISTER_MR_LVL_LVL_0 0x0UL
1378	#define CMDQ_REGISTER_MR_LVL_LVL_1 0x1UL
1379	#define CMDQ_REGISTER_MR_LVL_LVL_2 0x2UL
1380	#define CMDQ_REGISTER_MR_LVL_LAST CMDQ_REGISTER_MR_LVL_LVL_2
1381	#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK 0x7cUL
1382	#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT 2
1383	#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4K (0xcUL << 2)
1384	#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_8K (0xdUL << 2)
1385	#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_64K (0x10UL << 2)
1386	#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_256K (0x12UL << 2)
1387	#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1M (0x14UL << 2)
1388	#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_2M (0x15UL << 2)
1389	#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4M (0x16UL << 2)
1390	#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G (0x1eUL << 2)
1391	#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_LAST CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G
1392	#define CMDQ_REGISTER_MR_UNUSED1 0x80UL
1393	u8 access;
1394	#define CMDQ_REGISTER_MR_ACCESS_LOCAL_WRITE 0x1UL
1395	#define CMDQ_REGISTER_MR_ACCESS_REMOTE_READ 0x2UL
1396	#define CMDQ_REGISTER_MR_ACCESS_REMOTE_WRITE 0x4UL
1397	#define CMDQ_REGISTER_MR_ACCESS_REMOTE_ATOMIC 0x8UL
1398	#define CMDQ_REGISTER_MR_ACCESS_MW_BIND 0x10UL
1399	#define CMDQ_REGISTER_MR_ACCESS_ZERO_BASED 0x20UL
1400	__le16 log2_pbl_pg_size;
1401	#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK 0x1fUL
1402	#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT 0
1403	#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K 0xcUL
1404	#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K 0xdUL
1405	#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K 0x10UL
1406	#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K 0x12UL
1407	#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M 0x14UL
1408	#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M 0x15UL
1409	#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M 0x16UL
1410	#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G 0x1eUL
1411	#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_LAST CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G
1412	#define CMDQ_REGISTER_MR_UNUSED11_MASK 0xffe0UL
1413	#define CMDQ_REGISTER_MR_UNUSED11_SFT 5
1414	__le32 key;
1415	__le64 pbl;
1416	__le64 va;
1417	__le64 mr_size;
1418	};
1419
1420	/* creq_register_mr_resp (size:128b/16B) */
1421	struct creq_register_mr_resp {
1422	u8 type;
1423	#define CREQ_REGISTER_MR_RESP_TYPE_MASK 0x3fUL
1424	#define CREQ_REGISTER_MR_RESP_TYPE_SFT 0
1425	#define CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT 0x38UL
1426	#define CREQ_REGISTER_MR_RESP_TYPE_LAST CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT
1427	u8 status;
1428	__le16 cookie;
1429	__le32 xid;
1430	u8 v;
1431	#define CREQ_REGISTER_MR_RESP_V 0x1UL
1432	u8 event;
1433	#define CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR 0xfUL
1434	#define CREQ_REGISTER_MR_RESP_EVENT_LAST CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR
1435	u8 reserved48[6];
1436	};
1437
1438	/* cmdq_deregister_mr (size:192b/24B) */
1439	struct cmdq_deregister_mr {
1440	u8 opcode;
1441	#define CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR 0x10UL
1442	#define CMDQ_DEREGISTER_MR_OPCODE_LAST CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR
1443	u8 cmd_size;
1444	__le16 flags;
1445	__le16 cookie;
1446	u8 resp_size;
1447	u8 reserved8;
1448	__le64 resp_addr;
1449	__le32 lkey;
1450	__le32 unused_0;
1451	};
1452
1453	/* creq_deregister_mr_resp (size:128b/16B) */
1454	struct creq_deregister_mr_resp {
1455	u8 type;
1456	#define CREQ_DEREGISTER_MR_RESP_TYPE_MASK 0x3fUL
1457	#define CREQ_DEREGISTER_MR_RESP_TYPE_SFT 0
1458	#define CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT 0x38UL
1459	#define CREQ_DEREGISTER_MR_RESP_TYPE_LAST CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT
1460	u8 status;
1461	__le16 cookie;
1462	__le32 xid;
1463	u8 v;
1464	#define CREQ_DEREGISTER_MR_RESP_V 0x1UL
1465	u8 event;
1466	#define CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR 0x10UL
1467	#define CREQ_DEREGISTER_MR_RESP_EVENT_LAST CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR
1468	__le16 reserved16;
1469	__le32 bound_windows;
1470	};
1471
1472	/* cmdq_add_gid (size:384b/48B) */
1473	struct cmdq_add_gid {
1474	u8 opcode;
1475	#define CMDQ_ADD_GID_OPCODE_ADD_GID 0x11UL
1476	#define CMDQ_ADD_GID_OPCODE_LAST CMDQ_ADD_GID_OPCODE_ADD_GID
1477	u8 cmd_size;
1478	__le16 flags;
1479	__le16 cookie;
1480	u8 resp_size;
1481	u8 reserved8;
1482	__le64 resp_addr;
1483	__be32 gid[4];
1484	__be16 src_mac[3];
1485	__le16 vlan;
1486	#define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_MASK 0xffffUL
1487	#define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_SFT 0
1488	#define CMDQ_ADD_GID_VLAN_VLAN_ID_MASK 0xfffUL
1489	#define CMDQ_ADD_GID_VLAN_VLAN_ID_SFT 0
1490	#define CMDQ_ADD_GID_VLAN_TPID_MASK 0x7000UL
1491	#define CMDQ_ADD_GID_VLAN_TPID_SFT 12
1492	#define CMDQ_ADD_GID_VLAN_TPID_TPID_88A8 (0x0UL << 12)
1493	#define CMDQ_ADD_GID_VLAN_TPID_TPID_8100 (0x1UL << 12)
1494	#define CMDQ_ADD_GID_VLAN_TPID_TPID_9100 (0x2UL << 12)
1495	#define CMDQ_ADD_GID_VLAN_TPID_TPID_9200 (0x3UL << 12)
1496	#define CMDQ_ADD_GID_VLAN_TPID_TPID_9300 (0x4UL << 12)
1497	#define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG1 (0x5UL << 12)
1498	#define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG2 (0x6UL << 12)
1499	#define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 (0x7UL << 12)
1500	#define CMDQ_ADD_GID_VLAN_TPID_LAST CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3
1501	#define CMDQ_ADD_GID_VLAN_VLAN_EN 0x8000UL
1502	__le16 ipid;
1503	__le16 stats_ctx;
1504	#define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_MASK 0xffffUL
1505	#define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_SFT 0
1506	#define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_MASK 0x7fffUL
1507	#define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_SFT 0
1508	#define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID 0x8000UL
1509	__le32 unused_0;
1510	};
1511
1512	/* creq_add_gid_resp (size:128b/16B) */
1513	struct creq_add_gid_resp {
1514	u8 type;
1515	#define CREQ_ADD_GID_RESP_TYPE_MASK 0x3fUL
1516	#define CREQ_ADD_GID_RESP_TYPE_SFT 0
1517	#define CREQ_ADD_GID_RESP_TYPE_QP_EVENT 0x38UL
1518	#define CREQ_ADD_GID_RESP_TYPE_LAST CREQ_ADD_GID_RESP_TYPE_QP_EVENT
1519	u8 status;
1520	__le16 cookie;
1521	__le32 xid;
1522	u8 v;
1523	#define CREQ_ADD_GID_RESP_V 0x1UL
1524	u8 event;
1525	#define CREQ_ADD_GID_RESP_EVENT_ADD_GID 0x11UL
1526	#define CREQ_ADD_GID_RESP_EVENT_LAST CREQ_ADD_GID_RESP_EVENT_ADD_GID
1527	u8 reserved48[6];
1528	};
1529
1530	/* cmdq_delete_gid (size:192b/24B) */
1531	struct cmdq_delete_gid {
1532	u8 opcode;
1533	#define CMDQ_DELETE_GID_OPCODE_DELETE_GID 0x12UL
1534	#define CMDQ_DELETE_GID_OPCODE_LAST CMDQ_DELETE_GID_OPCODE_DELETE_GID
1535	u8 cmd_size;
1536	__le16 flags;
1537	__le16 cookie;
1538	u8 resp_size;
1539	u8 reserved8;
1540	__le64 resp_addr;
1541	__le16 gid_index;
1542	u8 unused_0[6];
1543	};
1544
1545	/* creq_delete_gid_resp (size:128b/16B) */
1546	struct creq_delete_gid_resp {
1547	u8 type;
1548	#define CREQ_DELETE_GID_RESP_TYPE_MASK 0x3fUL
1549	#define CREQ_DELETE_GID_RESP_TYPE_SFT 0
1550	#define CREQ_DELETE_GID_RESP_TYPE_QP_EVENT 0x38UL
1551	#define CREQ_DELETE_GID_RESP_TYPE_LAST CREQ_DELETE_GID_RESP_TYPE_QP_EVENT
1552	u8 status;
1553	__le16 cookie;
1554	__le32 xid;
1555	u8 v;
1556	#define CREQ_DELETE_GID_RESP_V 0x1UL
1557	u8 event;
1558	#define CREQ_DELETE_GID_RESP_EVENT_DELETE_GID 0x12UL
1559	#define CREQ_DELETE_GID_RESP_EVENT_LAST CREQ_DELETE_GID_RESP_EVENT_DELETE_GID
1560	u8 reserved48[6];
1561	};
1562
1563	/* cmdq_modify_gid (size:384b/48B) */
1564	struct cmdq_modify_gid {
1565	u8 opcode;
1566	#define CMDQ_MODIFY_GID_OPCODE_MODIFY_GID 0x17UL
1567	#define CMDQ_MODIFY_GID_OPCODE_LAST CMDQ_MODIFY_GID_OPCODE_MODIFY_GID
1568	u8 cmd_size;
1569	__le16 flags;
1570	__le16 cookie;
1571	u8 resp_size;
1572	u8 reserved8;
1573	__le64 resp_addr;
1574	__be32 gid[4];
1575	__be16 src_mac[3];
1576	__le16 vlan;
1577	#define CMDQ_MODIFY_GID_VLAN_VLAN_ID_MASK 0xfffUL
1578	#define CMDQ_MODIFY_GID_VLAN_VLAN_ID_SFT 0
1579	#define CMDQ_MODIFY_GID_VLAN_TPID_MASK 0x7000UL
1580	#define CMDQ_MODIFY_GID_VLAN_TPID_SFT 12
1581	#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_88A8 (0x0UL << 12)
1582	#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_8100 (0x1UL << 12)
1583	#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9100 (0x2UL << 12)
1584	#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9200 (0x3UL << 12)
1585	#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9300 (0x4UL << 12)
1586	#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG1 (0x5UL << 12)
1587	#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG2 (0x6UL << 12)
1588	#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 (0x7UL << 12)
1589	#define CMDQ_MODIFY_GID_VLAN_TPID_LAST CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3
1590	#define CMDQ_MODIFY_GID_VLAN_VLAN_EN 0x8000UL
1591	__le16 ipid;
1592	__le16 gid_index;
1593	__le16 stats_ctx;
1594	#define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_MASK 0x7fffUL
1595	#define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_SFT 0
1596	#define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_VALID 0x8000UL
1597	__le16 unused_0;
1598	};
1599
1600	/* creq_modify_gid_resp (size:128b/16B) */
1601	struct creq_modify_gid_resp {
1602	u8 type;
1603	#define CREQ_MODIFY_GID_RESP_TYPE_MASK 0x3fUL
1604	#define CREQ_MODIFY_GID_RESP_TYPE_SFT 0
1605	#define CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT 0x38UL
1606	#define CREQ_MODIFY_GID_RESP_TYPE_LAST CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT
1607	u8 status;
1608	__le16 cookie;
1609	__le32 xid;
1610	u8 v;
1611	#define CREQ_MODIFY_GID_RESP_V 0x1UL
1612	u8 event;
1613	#define CREQ_MODIFY_GID_RESP_EVENT_ADD_GID 0x11UL
1614	#define CREQ_MODIFY_GID_RESP_EVENT_LAST CREQ_MODIFY_GID_RESP_EVENT_ADD_GID
1615	u8 reserved48[6];
1616	};
1617
1618	/* cmdq_query_gid (size:192b/24B) */
1619	struct cmdq_query_gid {
1620	u8 opcode;
1621	#define CMDQ_QUERY_GID_OPCODE_QUERY_GID 0x18UL
1622	#define CMDQ_QUERY_GID_OPCODE_LAST CMDQ_QUERY_GID_OPCODE_QUERY_GID
1623	u8 cmd_size;
1624	__le16 flags;
1625	__le16 cookie;
1626	u8 resp_size;
1627	u8 reserved8;
1628	__le64 resp_addr;
1629	__le16 gid_index;
1630	u8 unused16[6];
1631	};
1632
1633	/* creq_query_gid_resp (size:128b/16B) */
1634	struct creq_query_gid_resp {
1635	u8 type;
1636	#define CREQ_QUERY_GID_RESP_TYPE_MASK 0x3fUL
1637	#define CREQ_QUERY_GID_RESP_TYPE_SFT 0
1638	#define CREQ_QUERY_GID_RESP_TYPE_QP_EVENT 0x38UL
1639	#define CREQ_QUERY_GID_RESP_TYPE_LAST CREQ_QUERY_GID_RESP_TYPE_QP_EVENT
1640	u8 status;
1641	__le16 cookie;
1642	__le32 size;
1643	u8 v;
1644	#define CREQ_QUERY_GID_RESP_V 0x1UL
1645	u8 event;
1646	#define CREQ_QUERY_GID_RESP_EVENT_QUERY_GID 0x18UL
1647	#define CREQ_QUERY_GID_RESP_EVENT_LAST CREQ_QUERY_GID_RESP_EVENT_QUERY_GID
1648	u8 reserved48[6];
1649	};
1650
1651	/* creq_query_gid_resp_sb (size:320b/40B) */
1652	struct creq_query_gid_resp_sb {
1653	u8 opcode;
1654	#define CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID 0x18UL
1655	#define CREQ_QUERY_GID_RESP_SB_OPCODE_LAST CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID
1656	u8 status;
1657	__le16 cookie;
1658	__le16 flags;
1659	u8 resp_size;
1660	u8 reserved8;
1661	__le32 gid[4];
1662	__le16 src_mac[3];
1663	__le16 vlan;
1664	#define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_MASK 0xffffUL
1665	#define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_SFT 0
1666	#define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_MASK 0xfffUL
1667	#define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_SFT 0
1668	#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_MASK 0x7000UL
1669	#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_SFT 12
1670	#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_88A8 (0x0UL << 12)
1671	#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_8100 (0x1UL << 12)
1672	#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9100 (0x2UL << 12)
1673	#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9200 (0x3UL << 12)
1674	#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9300 (0x4UL << 12)
1675	#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG1 (0x5UL << 12)
1676	#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG2 (0x6UL << 12)
1677	#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 (0x7UL << 12)
1678	#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_LAST CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3
1679	#define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN 0x8000UL
1680	__le16 ipid;
1681	__le16 gid_index;
1682	__le32 unused_0;
1683	};
1684
1685	/* cmdq_create_qp1 (size:640b/80B) */
1686	struct cmdq_create_qp1 {
1687	u8 opcode;
1688	#define CMDQ_CREATE_QP1_OPCODE_CREATE_QP1 0x13UL
1689	#define CMDQ_CREATE_QP1_OPCODE_LAST CMDQ_CREATE_QP1_OPCODE_CREATE_QP1
1690	u8 cmd_size;
1691	__le16 flags;
1692	__le16 cookie;
1693	u8 resp_size;
1694	u8 reserved8;
1695	__le64 resp_addr;
1696	__le64 qp_handle;
1697	__le32 qp_flags;
1698	#define CMDQ_CREATE_QP1_QP_FLAGS_SRQ_USED 0x1UL
1699	#define CMDQ_CREATE_QP1_QP_FLAGS_FORCE_COMPLETION 0x2UL
1700	#define CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE 0x4UL
1701	#define CMDQ_CREATE_QP1_QP_FLAGS_LAST CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE
1702	u8 type;
1703	#define CMDQ_CREATE_QP1_TYPE_GSI 0x1UL
1704	#define CMDQ_CREATE_QP1_TYPE_LAST CMDQ_CREATE_QP1_TYPE_GSI
1705	u8 sq_pg_size_sq_lvl;
1706	#define CMDQ_CREATE_QP1_SQ_LVL_MASK 0xfUL
1707	#define CMDQ_CREATE_QP1_SQ_LVL_SFT 0
1708	#define CMDQ_CREATE_QP1_SQ_LVL_LVL_0 0x0UL
1709	#define CMDQ_CREATE_QP1_SQ_LVL_LVL_1 0x1UL
1710	#define CMDQ_CREATE_QP1_SQ_LVL_LVL_2 0x2UL
1711	#define CMDQ_CREATE_QP1_SQ_LVL_LAST CMDQ_CREATE_QP1_SQ_LVL_LVL_2
1712	#define CMDQ_CREATE_QP1_SQ_PG_SIZE_MASK 0xf0UL
1713	#define CMDQ_CREATE_QP1_SQ_PG_SIZE_SFT 4
1714	#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_4K (0x0UL << 4)
1715	#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8K (0x1UL << 4)
1716	#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_64K (0x2UL << 4)
1717	#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_2M (0x3UL << 4)
1718	#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8M (0x4UL << 4)
1719	#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G (0x5UL << 4)
1720	#define CMDQ_CREATE_QP1_SQ_PG_SIZE_LAST CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G
1721	u8 rq_pg_size_rq_lvl;
1722	#define CMDQ_CREATE_QP1_RQ_LVL_MASK 0xfUL
1723	#define CMDQ_CREATE_QP1_RQ_LVL_SFT 0
1724	#define CMDQ_CREATE_QP1_RQ_LVL_LVL_0 0x0UL
1725	#define CMDQ_CREATE_QP1_RQ_LVL_LVL_1 0x1UL
1726	#define CMDQ_CREATE_QP1_RQ_LVL_LVL_2 0x2UL
1727	#define CMDQ_CREATE_QP1_RQ_LVL_LAST CMDQ_CREATE_QP1_RQ_LVL_LVL_2
1728	#define CMDQ_CREATE_QP1_RQ_PG_SIZE_MASK 0xf0UL
1729	#define CMDQ_CREATE_QP1_RQ_PG_SIZE_SFT 4
1730	#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_4K (0x0UL << 4)
1731	#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8K (0x1UL << 4)
1732	#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_64K (0x2UL << 4)
1733	#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_2M (0x3UL << 4)
1734	#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8M (0x4UL << 4)
1735	#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G (0x5UL << 4)
1736	#define CMDQ_CREATE_QP1_RQ_PG_SIZE_LAST CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G
1737	u8 unused_0;
1738	__le32 dpi;
1739	__le32 sq_size;
1740	__le32 rq_size;
1741	__le16 sq_fwo_sq_sge;
1742	#define CMDQ_CREATE_QP1_SQ_SGE_MASK 0xfUL
1743	#define CMDQ_CREATE_QP1_SQ_SGE_SFT 0
1744	#define CMDQ_CREATE_QP1_SQ_FWO_MASK 0xfff0UL
1745	#define CMDQ_CREATE_QP1_SQ_FWO_SFT 4
1746	__le16 rq_fwo_rq_sge;
1747	#define CMDQ_CREATE_QP1_RQ_SGE_MASK 0xfUL
1748	#define CMDQ_CREATE_QP1_RQ_SGE_SFT 0
1749	#define CMDQ_CREATE_QP1_RQ_FWO_MASK 0xfff0UL
1750	#define CMDQ_CREATE_QP1_RQ_FWO_SFT 4
1751	__le32 scq_cid;
1752	__le32 rcq_cid;
1753	__le32 srq_cid;
1754	__le32 pd_id;
1755	__le64 sq_pbl;
1756	__le64 rq_pbl;
1757	};
1758
1759	/* creq_create_qp1_resp (size:128b/16B) */
1760	struct creq_create_qp1_resp {
1761	u8 type;
1762	#define CREQ_CREATE_QP1_RESP_TYPE_MASK 0x3fUL
1763	#define CREQ_CREATE_QP1_RESP_TYPE_SFT 0
1764	#define CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT 0x38UL
1765	#define CREQ_CREATE_QP1_RESP_TYPE_LAST CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT
1766	u8 status;
1767	__le16 cookie;
1768	__le32 xid;
1769	u8 v;
1770	#define CREQ_CREATE_QP1_RESP_V 0x1UL
1771	u8 event;
1772	#define CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1 0x13UL
1773	#define CREQ_CREATE_QP1_RESP_EVENT_LAST CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1
1774	u8 reserved48[6];
1775	};
1776
1777	/* cmdq_destroy_qp1 (size:192b/24B) */
1778	struct cmdq_destroy_qp1 {
1779	u8 opcode;
1780	#define CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1 0x14UL
1781	#define CMDQ_DESTROY_QP1_OPCODE_LAST CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1
1782	u8 cmd_size;
1783	__le16 flags;
1784	__le16 cookie;
1785	u8 resp_size;
1786	u8 reserved8;
1787	__le64 resp_addr;
1788	__le32 qp1_cid;
1789	__le32 unused_0;
1790	};
1791
1792	/* creq_destroy_qp1_resp (size:128b/16B) */
1793	struct creq_destroy_qp1_resp {
1794	u8 type;
1795	#define CREQ_DESTROY_QP1_RESP_TYPE_MASK 0x3fUL
1796	#define CREQ_DESTROY_QP1_RESP_TYPE_SFT 0
1797	#define CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT 0x38UL
1798	#define CREQ_DESTROY_QP1_RESP_TYPE_LAST CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT
1799	u8 status;
1800	__le16 cookie;
1801	__le32 xid;
1802	u8 v;
1803	#define CREQ_DESTROY_QP1_RESP_V 0x1UL
1804	u8 event;
1805	#define CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1 0x14UL
1806	#define CREQ_DESTROY_QP1_RESP_EVENT_LAST CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1
1807	u8 reserved48[6];
1808	};
1809
1810	/* cmdq_create_ah (size:512b/64B) */
1811	struct cmdq_create_ah {
1812	u8 opcode;
1813	#define CMDQ_CREATE_AH_OPCODE_CREATE_AH 0x15UL
1814	#define CMDQ_CREATE_AH_OPCODE_LAST CMDQ_CREATE_AH_OPCODE_CREATE_AH
1815	u8 cmd_size;
1816	__le16 flags;
1817	__le16 cookie;
1818	u8 resp_size;
1819	u8 reserved8;
1820	__le64 resp_addr;
1821	__le64 ah_handle;
1822	__le32 dgid[4];
1823	u8 type;
1824	#define CMDQ_CREATE_AH_TYPE_V1 0x0UL
1825	#define CMDQ_CREATE_AH_TYPE_V2IPV4 0x2UL
1826	#define CMDQ_CREATE_AH_TYPE_V2IPV6 0x3UL
1827	#define CMDQ_CREATE_AH_TYPE_LAST CMDQ_CREATE_AH_TYPE_V2IPV6
1828	u8 hop_limit;
1829	__le16 sgid_index;
1830	__le32 dest_vlan_id_flow_label;
1831	#define CMDQ_CREATE_AH_FLOW_LABEL_MASK 0xfffffUL
1832	#define CMDQ_CREATE_AH_FLOW_LABEL_SFT 0
1833	#define CMDQ_CREATE_AH_DEST_VLAN_ID_MASK 0xfff00000UL
1834	#define CMDQ_CREATE_AH_DEST_VLAN_ID_SFT 20
1835	__le32 pd_id;
1836	__le32 unused_0;
1837	__le16 dest_mac[3];
1838	u8 traffic_class;
1839	u8 enable_cc;
1840	#define CMDQ_CREATE_AH_ENABLE_CC 0x1UL
1841	};
1842
1843	/* creq_create_ah_resp (size:128b/16B) */
1844	struct creq_create_ah_resp {
1845	u8 type;
1846	#define CREQ_CREATE_AH_RESP_TYPE_MASK 0x3fUL
1847	#define CREQ_CREATE_AH_RESP_TYPE_SFT 0
1848	#define CREQ_CREATE_AH_RESP_TYPE_QP_EVENT 0x38UL
1849	#define CREQ_CREATE_AH_RESP_TYPE_LAST CREQ_CREATE_AH_RESP_TYPE_QP_EVENT
1850	u8 status;
1851	__le16 cookie;
1852	__le32 xid;
1853	u8 v;
1854	#define CREQ_CREATE_AH_RESP_V 0x1UL
1855	u8 event;
1856	#define CREQ_CREATE_AH_RESP_EVENT_CREATE_AH 0x15UL
1857	#define CREQ_CREATE_AH_RESP_EVENT_LAST CREQ_CREATE_AH_RESP_EVENT_CREATE_AH
1858	u8 reserved48[6];
1859	};
1860
1861	/* cmdq_destroy_ah (size:192b/24B) */
1862	struct cmdq_destroy_ah {
1863	u8 opcode;
1864	#define CMDQ_DESTROY_AH_OPCODE_DESTROY_AH 0x16UL
1865	#define CMDQ_DESTROY_AH_OPCODE_LAST CMDQ_DESTROY_AH_OPCODE_DESTROY_AH
1866	u8 cmd_size;
1867	__le16 flags;
1868	__le16 cookie;
1869	u8 resp_size;
1870	u8 reserved8;
1871	__le64 resp_addr;
1872	__le32 ah_cid;
1873	__le32 unused_0;
1874	};
1875
1876	/* creq_destroy_ah_resp (size:128b/16B) */
1877	struct creq_destroy_ah_resp {
1878	u8 type;
1879	#define CREQ_DESTROY_AH_RESP_TYPE_MASK 0x3fUL
1880	#define CREQ_DESTROY_AH_RESP_TYPE_SFT 0
1881	#define CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT 0x38UL
1882	#define CREQ_DESTROY_AH_RESP_TYPE_LAST CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT
1883	u8 status;
1884	__le16 cookie;
1885	__le32 xid;
1886	u8 v;
1887	#define CREQ_DESTROY_AH_RESP_V 0x1UL
1888	u8 event;
1889	#define CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH 0x16UL
1890	#define CREQ_DESTROY_AH_RESP_EVENT_LAST CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH
1891	u8 reserved48[6];
1892	};
1893
1894	/* cmdq_query_roce_stats (size:192b/24B) */
1895	struct cmdq_query_roce_stats {
1896	u8 opcode;
1897	#define CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS 0x8eUL
1898	#define CMDQ_QUERY_ROCE_STATS_OPCODE_LAST CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS
1899	u8 cmd_size;
1900	__le16 flags;
1901	#define CMDQ_QUERY_ROCE_STATS_FLAGS_COLLECTION_ID 0x1UL
1902	#define CMDQ_QUERY_ROCE_STATS_FLAGS_FUNCTION_ID 0x2UL
1903	__le16 cookie;
1904	u8 resp_size;
1905	u8 collection_id;
1906	__le64 resp_addr;
1907	__le32 function_id;
1908	#define CMDQ_QUERY_ROCE_STATS_PF_NUM_MASK 0xffUL
1909	#define CMDQ_QUERY_ROCE_STATS_PF_NUM_SFT 0
1910	#define CMDQ_QUERY_ROCE_STATS_VF_NUM_MASK 0xffff00UL
1911	#define CMDQ_QUERY_ROCE_STATS_VF_NUM_SFT 8
1912	#define CMDQ_QUERY_ROCE_STATS_VF_VALID 0x1000000UL
1913	__le32 reserved32;
1914	};
1915
1916	/* creq_query_roce_stats_resp (size:128b/16B) */
1917	struct creq_query_roce_stats_resp {
1918	u8 type;
1919	#define CREQ_QUERY_ROCE_STATS_RESP_TYPE_MASK 0x3fUL
1920	#define CREQ_QUERY_ROCE_STATS_RESP_TYPE_SFT 0
1921	#define CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT 0x38UL
1922	#define CREQ_QUERY_ROCE_STATS_RESP_TYPE_LAST CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT
1923	u8 status;
1924	__le16 cookie;
1925	__le32 size;
1926	u8 v;
1927	#define CREQ_QUERY_ROCE_STATS_RESP_V 0x1UL
1928	u8 event;
1929	#define CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS 0x8eUL
1930	#define CREQ_QUERY_ROCE_STATS_RESP_EVENT_LAST \
1931	CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS
1932	u8 reserved48[6];
1933	};
1934
1935	/* creq_query_roce_stats_resp_sb (size:2944b/368B) */
1936	struct creq_query_roce_stats_resp_sb {
1937	u8 opcode;
1938	#define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS 0x8eUL
1939	#define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_LAST \
1940	CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS
1941	u8 status;
1942	__le16 cookie;
1943	__le16 flags;
1944	u8 resp_size;
1945	u8 rsvd;
1946	__le32 num_counters;
1947	__le32 rsvd1;
1948	__le64 to_retransmits;
1949	__le64 seq_err_naks_rcvd;
1950	__le64 max_retry_exceeded;
1951	__le64 rnr_naks_rcvd;
1952	__le64 missing_resp;
1953	__le64 unrecoverable_err;
1954	__le64 bad_resp_err;
1955	__le64 local_qp_op_err;
1956	__le64 local_protection_err;
1957	__le64 mem_mgmt_op_err;
1958	__le64 remote_invalid_req_err;
1959	__le64 remote_access_err;
1960	__le64 remote_op_err;
1961	__le64 dup_req;
1962	__le64 res_exceed_max;
1963	__le64 res_length_mismatch;
1964	__le64 res_exceeds_wqe;
1965	__le64 res_opcode_err;
1966	__le64 res_rx_invalid_rkey;
1967	__le64 res_rx_domain_err;
1968	__le64 res_rx_no_perm;
1969	__le64 res_rx_range_err;
1970	__le64 res_tx_invalid_rkey;
1971	__le64 res_tx_domain_err;
1972	__le64 res_tx_no_perm;
1973	__le64 res_tx_range_err;
1974	__le64 res_irrq_oflow;
1975	__le64 res_unsup_opcode;
1976	__le64 res_unaligned_atomic;
1977	__le64 res_rem_inv_err;
1978	__le64 res_mem_error;
1979	__le64 res_srq_err;
1980	__le64 res_cmp_err;
1981	__le64 res_invalid_dup_rkey;
1982	__le64 res_wqe_format_err;
1983	__le64 res_cq_load_err;
1984	__le64 res_srq_load_err;
1985	__le64 res_tx_pci_err;
1986	__le64 res_rx_pci_err;
1987	__le64 res_oos_drop_count;
1988	__le64 active_qp_count_p0;
1989	__le64 active_qp_count_p1;
1990	__le64 active_qp_count_p2;
1991	__le64 active_qp_count_p3;
1992	};
1993
1994	/* cmdq_query_roce_stats_ext (size:192b/24B) */
1995	struct cmdq_query_roce_stats_ext {
1996	u8 opcode;
1997	#define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS 0x92UL
1998	#define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_LAST \
1999	CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS
2000	u8 cmd_size;
2001	__le16 flags;
2002	#define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_COLLECTION_ID 0x1UL
2003	#define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID 0x2UL
2004	__le16 cookie;
2005	u8 resp_size;
2006	u8 collection_id;
2007	__le64 resp_addr;
2008	__le32 function_id;
2009	#define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_MASK 0xffUL
2010	#define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_SFT 0
2011	#define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_MASK 0xffff00UL
2012	#define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_SFT 8
2013	#define CMDQ_QUERY_ROCE_STATS_EXT_VF_VALID 0x1000000UL
2014	__le32 reserved32;
2015	};
2016
2017	/* creq_query_roce_stats_ext_resp (size:128b/16B) */
2018	struct creq_query_roce_stats_ext_resp {
2019	u8 type;
2020	#define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_MASK 0x3fUL
2021	#define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_SFT 0
2022	#define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT 0x38UL
2023	#define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_LAST \
2024	CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT
2025	u8 status;
2026	__le16 cookie;
2027	__le32 size;
2028	u8 v;
2029	#define CREQ_QUERY_ROCE_STATS_EXT_RESP_V 0x1UL
2030	u8 event;
2031	#define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT 0x92UL
2032	#define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_LAST \
2033	CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT
2034	u8 reserved48[6];
2035	};
2036
2037	/* creq_query_roce_stats_ext_resp_sb (size:1856b/232B) */
2038	struct creq_query_roce_stats_ext_resp_sb {
2039	u8 opcode;
2040	#define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT 0x92UL
2041	#define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_LAST \
2042	CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT
2043	u8 status;
2044	__le16 cookie;
2045	__le16 flags;
2046	u8 resp_size;
2047	u8 rsvd;
2048	__le64 tx_atomic_req_pkts;
2049	__le64 tx_read_req_pkts;
2050	__le64 tx_read_res_pkts;
2051	__le64 tx_write_req_pkts;
2052	__le64 tx_send_req_pkts;
2053	__le64 tx_roce_pkts;
2054	__le64 tx_roce_bytes;
2055	__le64 rx_atomic_req_pkts;
2056	__le64 rx_read_req_pkts;
2057	__le64 rx_read_res_pkts;
2058	__le64 rx_write_req_pkts;
2059	__le64 rx_send_req_pkts;
2060	__le64 rx_roce_pkts;
2061	__le64 rx_roce_bytes;
2062	__le64 rx_roce_good_pkts;
2063	__le64 rx_roce_good_bytes;
2064	__le64 rx_out_of_buffer_pkts;
2065	__le64 rx_out_of_sequence_pkts;
2066	__le64 tx_cnp_pkts;
2067	__le64 rx_cnp_pkts;
2068	__le64 rx_ecn_marked_pkts;
2069	__le64 tx_cnp_bytes;
2070	__le64 rx_cnp_bytes;
2071	__le64 seq_err_naks_rcvd;
2072	__le64 rnr_naks_rcvd;
2073	__le64 missing_resp;
2074	__le64 to_retransmit;
2075	__le64 dup_req;
2076	};
2077
2078	/* cmdq_query_func (size:128b/16B) */
2079	struct cmdq_query_func {
2080	u8 opcode;
2081	#define CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC 0x83UL
2082	#define CMDQ_QUERY_FUNC_OPCODE_LAST CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC
2083	u8 cmd_size;
2084	__le16 flags;
2085	__le16 cookie;
2086	u8 resp_size;
2087	u8 reserved8;
2088	__le64 resp_addr;
2089	};
2090
2091	/* creq_query_func_resp (size:128b/16B) */
2092	struct creq_query_func_resp {
2093	u8 type;
2094	#define CREQ_QUERY_FUNC_RESP_TYPE_MASK 0x3fUL
2095	#define CREQ_QUERY_FUNC_RESP_TYPE_SFT 0
2096	#define CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT 0x38UL
2097	#define CREQ_QUERY_FUNC_RESP_TYPE_LAST CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT
2098	u8 status;
2099	__le16 cookie;
2100	__le32 size;
2101	u8 v;
2102	#define CREQ_QUERY_FUNC_RESP_V 0x1UL
2103	u8 event;
2104	#define CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC 0x83UL
2105	#define CREQ_QUERY_FUNC_RESP_EVENT_LAST CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC
2106	u8 reserved48[6];
2107	};
2108
2109	/* creq_query_func_resp_sb (size:1088b/136B) */
2110	struct creq_query_func_resp_sb {
2111	u8 opcode;
2112	#define CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC 0x83UL
2113	#define CREQ_QUERY_FUNC_RESP_SB_OPCODE_LAST CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC
2114	u8 status;
2115	__le16 cookie;
2116	__le16 flags;
2117	u8 resp_size;
2118	u8 reserved8;
2119	__le64 max_mr_size;
2120	__le32 max_qp;
2121	__le16 max_qp_wr;
2122	__le16 dev_cap_flags;
2123	#define CREQ_QUERY_FUNC_RESP_SB_RESIZE_QP 0x1UL
2124	#define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_MASK 0xeUL
2125	#define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_SFT 1
2126	#define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN0 (0x0UL << 1)
2127	#define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1 (0x1UL << 1)
2128	#define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1_EXT (0x2UL << 1)
2129	#define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_LAST \
2130	CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1_EXT
2131	#define CREQ_QUERY_FUNC_RESP_SB_EXT_STATS 0x10UL
2132	#define CREQ_QUERY_FUNC_RESP_SB_MR_REGISTER_ALLOC 0x20UL
2133	#define CREQ_QUERY_FUNC_RESP_SB_OPTIMIZED_TRANSMIT_ENABLED 0x40UL
2134	#define CREQ_QUERY_FUNC_RESP_SB_CQE_V2 0x80UL
2135	#define CREQ_QUERY_FUNC_RESP_SB_PINGPONG_PUSH_MODE 0x100UL
2136	#define CREQ_QUERY_FUNC_RESP_SB_HW_REQUESTER_RETX_ENABLED 0x200UL
2137	#define CREQ_QUERY_FUNC_RESP_SB_HW_RESPONDER_RETX_ENABLED 0x400UL
2138	__le32 max_cq;
2139	__le32 max_cqe;
2140	__le32 max_pd;
2141	u8 max_sge;
2142	u8 max_srq_sge;
2143	u8 max_qp_rd_atom;
2144	u8 max_qp_init_rd_atom;
2145	__le32 max_mr;
2146	__le32 max_mw;
2147	__le32 max_raw_eth_qp;
2148	__le32 max_ah;
2149	__le32 max_fmr;
2150	__le32 max_srq_wr;
2151	__le32 max_pkeys;
2152	__le32 max_inline_data;
2153	u8 max_map_per_fmr;
2154	u8 l2_db_space_size;
2155	__le16 max_srq;
2156	__le32 max_gid;
2157	__le32 tqm_alloc_reqs[12];
2158	__le32 max_dpi;
2159	u8 max_sge_var_wqe;
2160	u8 reserved_8;
2161	__le16 max_inline_data_var_wqe;
2162	};
2163
2164	/* cmdq_set_func_resources (size:448b/56B) */
2165	struct cmdq_set_func_resources {
2166	u8 opcode;
2167	#define CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES 0x84UL
2168	#define CMDQ_SET_FUNC_RESOURCES_OPCODE_LAST\
2169	CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES
2170	u8 cmd_size;
2171	__le16 flags;
2172	#define CMDQ_SET_FUNC_RESOURCES_FLAGS_MRAV_RESERVATION_SPLIT 0x1UL
2173	__le16 cookie;
2174	u8 resp_size;
2175	u8 reserved8;
2176	__le64 resp_addr;
2177	__le32 number_of_qp;
2178	__le32 number_of_mrw;
2179	__le32 number_of_srq;
2180	__le32 number_of_cq;
2181	__le32 max_qp_per_vf;
2182	__le32 max_mrw_per_vf;
2183	__le32 max_srq_per_vf;
2184	__le32 max_cq_per_vf;
2185	__le32 max_gid_per_vf;
2186	__le32 stat_ctx_id;
2187	};
2188
2189	/* creq_set_func_resources_resp (size:128b/16B) */
2190	struct creq_set_func_resources_resp {
2191	u8 type;
2192	#define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_MASK 0x3fUL
2193	#define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_SFT 0
2194	#define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT 0x38UL
2195	#define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_LAST CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT
2196	u8 status;
2197	__le16 cookie;
2198	__le32 reserved32;
2199	u8 v;
2200	#define CREQ_SET_FUNC_RESOURCES_RESP_V 0x1UL
2201	u8 event;
2202	#define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES 0x84UL
2203	#define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_LAST \
2204	CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES
2205	u8 reserved48[6];
2206	};
2207
2208	/* cmdq_map_tc_to_cos (size:192b/24B) */
2209	struct cmdq_map_tc_to_cos {
2210	u8 opcode;
2211	#define CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS 0x8aUL
2212	#define CMDQ_MAP_TC_TO_COS_OPCODE_LAST CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS
2213	u8 cmd_size;
2214	__le16 flags;
2215	__le16 cookie;
2216	u8 resp_size;
2217	u8 reserved8;
2218	__le64 resp_addr;
2219	__le16 cos0;
2220	#define CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE 0xffffUL
2221	#define CMDQ_MAP_TC_TO_COS_COS0_LAST CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE
2222	__le16 cos1;
2223	#define CMDQ_MAP_TC_TO_COS_COS1_DISABLE 0x8000UL
2224	#define CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE 0xffffUL
2225	#define CMDQ_MAP_TC_TO_COS_COS1_LAST CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE
2226	__le32 unused_0;
2227	};
2228
2229	/* creq_map_tc_to_cos_resp (size:128b/16B) */
2230	struct creq_map_tc_to_cos_resp {
2231	u8 type;
2232	#define CREQ_MAP_TC_TO_COS_RESP_TYPE_MASK 0x3fUL
2233	#define CREQ_MAP_TC_TO_COS_RESP_TYPE_SFT 0
2234	#define CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT 0x38UL
2235	#define CREQ_MAP_TC_TO_COS_RESP_TYPE_LAST CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT
2236	u8 status;
2237	__le16 cookie;
2238	__le32 reserved32;
2239	u8 v;
2240	#define CREQ_MAP_TC_TO_COS_RESP_V 0x1UL
2241	u8 event;
2242	#define CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS 0x8aUL
2243	#define CREQ_MAP_TC_TO_COS_RESP_EVENT_LAST CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS
2244	u8 reserved48[6];
2245	};
2246
2247	/* cmdq_query_roce_cc (size:128b/16B) */
2248	struct cmdq_query_roce_cc {
2249	u8 opcode;
2250	#define CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC 0x8dUL
2251	#define CMDQ_QUERY_ROCE_CC_OPCODE_LAST CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC
2252	u8 cmd_size;
2253	__le16 flags;
2254	__le16 cookie;
2255	u8 resp_size;
2256	u8 reserved8;
2257	__le64 resp_addr;
2258	};
2259
2260	/* creq_query_roce_cc_resp (size:128b/16B) */
2261	struct creq_query_roce_cc_resp {
2262	u8 type;
2263	#define CREQ_QUERY_ROCE_CC_RESP_TYPE_MASK 0x3fUL
2264	#define CREQ_QUERY_ROCE_CC_RESP_TYPE_SFT 0
2265	#define CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT 0x38UL
2266	#define CREQ_QUERY_ROCE_CC_RESP_TYPE_LAST CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT
2267	u8 status;
2268	__le16 cookie;
2269	__le32 size;
2270	u8 v;
2271	#define CREQ_QUERY_ROCE_CC_RESP_V 0x1UL
2272	u8 event;
2273	#define CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC 0x8dUL
2274	#define CREQ_QUERY_ROCE_CC_RESP_EVENT_LAST CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC
2275	u8 reserved48[6];
2276	};
2277
2278	/* creq_query_roce_cc_resp_sb (size:256b/32B) */
2279	struct creq_query_roce_cc_resp_sb {
2280	u8 opcode;
2281	#define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC 0x8dUL
2282	#define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_LAST \
2283	CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC
2284	u8 status;
2285	__le16 cookie;
2286	__le16 flags;
2287	u8 resp_size;
2288	u8 reserved8;
2289	u8 enable_cc;
2290	#define CREQ_QUERY_ROCE_CC_RESP_SB_ENABLE_CC 0x1UL
2291	#define CREQ_QUERY_ROCE_CC_RESP_SB_UNUSED7_MASK 0xfeUL
2292	#define CREQ_QUERY_ROCE_CC_RESP_SB_UNUSED7_SFT 1
2293	u8 tos_dscp_tos_ecn;
2294	#define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_MASK 0x3UL
2295	#define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_SFT 0
2296	#define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_MASK 0xfcUL
2297	#define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_SFT 2
2298	u8 g;
2299	u8 num_phases_per_state;
2300	__le16 init_cr;
2301	__le16 init_tr;
2302	u8 alt_vlan_pcp;
2303	#define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_MASK 0x7UL
2304	#define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_SFT 0
2305	#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_MASK 0xf8UL
2306	#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_SFT 3
2307	u8 alt_tos_dscp;
2308	#define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_MASK 0x3fUL
2309	#define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_SFT 0
2310	#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_MASK 0xc0UL
2311	#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_SFT 6
2312	u8 cc_mode;
2313	#define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_DCTCP 0x0UL
2314	#define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_PROBABILISTIC 0x1UL
2315	#define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_LAST \
2316	CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_PROBABILISTIC
2317	u8 tx_queue;
2318	__le16 rtt;
2319	#define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_MASK 0x3fffUL
2320	#define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_SFT 0
2321	#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_MASK 0xc000UL
2322	#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_SFT 14
2323	__le16 tcp_cp;
2324	#define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_MASK 0x3ffUL
2325	#define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_SFT 0
2326	#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_MASK 0xfc00UL
2327	#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_SFT 10
2328	__le16 inactivity_th;
2329	u8 pkts_per_phase;
2330	u8 time_per_phase;
2331	__le32 reserved32;
2332	};
2333
2334	/* creq_query_roce_cc_resp_sb_tlv (size:384b/48B) */
2335	struct creq_query_roce_cc_resp_sb_tlv {
2336	__le16 cmd_discr;
2337	u8 reserved_8b;
2338	u8 tlv_flags;
2339	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL
2340	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL
2341	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL
2342	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL
2343	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
2344	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
2345	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST \
2346	CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES
2347	__le16 tlv_type;
2348	__le16 length;
2349	u8 total_size;
2350	u8 reserved56[7];
2351	u8 opcode;
2352	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_QUERY_ROCE_CC 0x8dUL
2353	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_LAST \
2354	CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_QUERY_ROCE_CC
2355	u8 status;
2356	__le16 cookie;
2357	__le16 flags;
2358	u8 resp_size;
2359	u8 reserved8;
2360	u8 enable_cc;
2361	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ENABLE_CC 0x1UL
2362	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_UNUSED7_MASK 0xfeUL
2363	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_UNUSED7_SFT 1
2364	u8 tos_dscp_tos_ecn;
2365	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_MASK 0x3UL
2366	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_SFT 0
2367	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_DSCP_MASK 0xfcUL
2368	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_DSCP_SFT 2
2369	u8 g;
2370	u8 num_phases_per_state;
2371	__le16 init_cr;
2372	__le16 init_tr;
2373	u8 alt_vlan_pcp;
2374	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_MASK 0x7UL
2375	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_SFT 0
2376	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD1_MASK 0xf8UL
2377	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD1_SFT 3
2378	u8 alt_tos_dscp;
2379	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_MASK 0x3fUL
2380	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_SFT 0
2381	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD4_MASK 0xc0UL
2382	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD4_SFT 6
2383	u8 cc_mode;
2384	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_DCTCP 0x0UL
2385	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_PROBABILISTIC 0x1UL
2386	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_LAST\
2387	CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_PROBABILISTIC
2388	u8 tx_queue;
2389	__le16 rtt;
2390	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_MASK 0x3fffUL
2391	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_SFT 0
2392	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD5_MASK 0xc000UL
2393	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD5_SFT 14
2394	__le16 tcp_cp;
2395	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_MASK 0x3ffUL
2396	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_SFT 0
2397	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD6_MASK 0xfc00UL
2398	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD6_SFT 10
2399	__le16 inactivity_th;
2400	u8 pkts_per_phase;
2401	u8 time_per_phase;
2402	__le32 reserved32;
2403	};
2404
2405	/* creq_query_roce_cc_gen1_resp_sb_tlv (size:704b/88B) */
2406	struct creq_query_roce_cc_gen1_resp_sb_tlv {
2407	__le16 cmd_discr;
2408	u8 reserved_8b;
2409	u8 tlv_flags;
2410	#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL
2411	#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL
2412	#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL
2413	#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL
2414	#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
2415	#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
2416	#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST \
2417	CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES
2418	__le16 tlv_type;
2419	__le16 length;
2420	__le64 reserved64;
2421	__le16 inactivity_th_hi;
2422	__le16 min_time_between_cnps;
2423	__le16 init_cp;
2424	u8 tr_update_mode;
2425	u8 tr_update_cycles;
2426	u8 fr_num_rtts;
2427	u8 ai_rate_increase;
2428	__le16 reduction_relax_rtts_th;
2429	__le16 additional_relax_cr_th;
2430	__le16 cr_min_th;
2431	u8 bw_avg_weight;
2432	u8 actual_cr_factor;
2433	__le16 max_cp_cr_th;
2434	u8 cp_bias_en;
2435	u8 cp_bias;
2436	u8 cnp_ecn;
2437	#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_NOT_ECT 0x0UL
2438	#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_1 0x1UL
2439	#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_0 0x2UL
2440	#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_LAST \
2441	CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_0
2442	u8 rtt_jitter_en;
2443	__le16 link_bytes_per_usec;
2444	__le16 reset_cc_cr_th;
2445	u8 cr_width;
2446	u8 quota_period_min;
2447	u8 quota_period_max;
2448	u8 quota_period_abs_max;
2449	__le16 tr_lower_bound;
2450	u8 cr_prob_factor;
2451	u8 tr_prob_factor;
2452	__le16 fairness_cr_th;
2453	u8 red_div;
2454	u8 cnp_ratio_th;
2455	__le16 exp_ai_rtts;
2456	u8 exp_ai_cr_cp_ratio;
2457	u8 use_rate_table;
2458	__le16 cp_exp_update_th;
2459	__le16 high_exp_ai_rtts_th1;
2460	__le16 high_exp_ai_rtts_th2;
2461	__le16 actual_cr_cong_free_rtts_th;
2462	__le16 severe_cong_cr_th1;
2463	__le16 severe_cong_cr_th2;
2464	__le32 link64B_per_rtt;
2465	u8 cc_ack_bytes;
2466	u8 reduce_init_en;
2467	__le16 reduce_init_cong_free_rtts_th;
2468	u8 random_no_red_en;
2469	u8 actual_cr_shift_correction_en;
2470	u8 quota_period_adjust_en;
2471	u8 reserved[5];
2472	};
2473
2474	/* cmdq_modify_roce_cc (size:448b/56B) */
2475	struct cmdq_modify_roce_cc {
2476	u8 opcode;
2477	#define CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC 0x8cUL
2478	#define CMDQ_MODIFY_ROCE_CC_OPCODE_LAST CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC
2479	u8 cmd_size;
2480	__le16 flags;
2481	__le16 cookie;
2482	u8 resp_size;
2483	u8 reserved8;
2484	__le64 resp_addr;
2485	__le32 modify_mask;
2486	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC 0x1UL
2487	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_G 0x2UL
2488	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_NUMPHASEPERSTATE 0x4UL
2489	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_CR 0x8UL
2490	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_TR 0x10UL
2491	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN 0x20UL
2492	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_DSCP 0x40UL
2493	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_VLAN_PCP 0x80UL
2494	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_TOS_DSCP 0x100UL
2495	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_RTT 0x200UL
2496	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_CC_MODE 0x400UL
2497	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TCP_CP 0x800UL
2498	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TX_QUEUE 0x1000UL
2499	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INACTIVITY_CP 0x2000UL
2500	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TIME_PER_PHASE 0x4000UL
2501	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_PKTS_PER_PHASE 0x8000UL
2502	u8 enable_cc;
2503	#define CMDQ_MODIFY_ROCE_CC_ENABLE_CC 0x1UL
2504	#define CMDQ_MODIFY_ROCE_CC_RSVD1_MASK 0xfeUL
2505	#define CMDQ_MODIFY_ROCE_CC_RSVD1_SFT 1
2506	u8 g;
2507	u8 num_phases_per_state;
2508	u8 pkts_per_phase;
2509	__le16 init_cr;
2510	__le16 init_tr;
2511	u8 tos_dscp_tos_ecn;
2512	#define CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK 0x3UL
2513	#define CMDQ_MODIFY_ROCE_CC_TOS_ECN_SFT 0
2514	#define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_MASK 0xfcUL
2515	#define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_SFT 2
2516	u8 alt_vlan_pcp;
2517	#define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_MASK 0x7UL
2518	#define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_SFT 0
2519	#define CMDQ_MODIFY_ROCE_CC_RSVD3_MASK 0xf8UL
2520	#define CMDQ_MODIFY_ROCE_CC_RSVD3_SFT 3
2521	__le16 alt_tos_dscp;
2522	#define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_MASK 0x3fUL
2523	#define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_SFT 0
2524	#define CMDQ_MODIFY_ROCE_CC_RSVD4_MASK 0xffc0UL
2525	#define CMDQ_MODIFY_ROCE_CC_RSVD4_SFT 6
2526	__le16 rtt;
2527	#define CMDQ_MODIFY_ROCE_CC_RTT_MASK 0x3fffUL
2528	#define CMDQ_MODIFY_ROCE_CC_RTT_SFT 0
2529	#define CMDQ_MODIFY_ROCE_CC_RSVD5_MASK 0xc000UL
2530	#define CMDQ_MODIFY_ROCE_CC_RSVD5_SFT 14
2531	__le16 tcp_cp;
2532	#define CMDQ_MODIFY_ROCE_CC_TCP_CP_MASK 0x3ffUL
2533	#define CMDQ_MODIFY_ROCE_CC_TCP_CP_SFT 0
2534	#define CMDQ_MODIFY_ROCE_CC_RSVD6_MASK 0xfc00UL
2535	#define CMDQ_MODIFY_ROCE_CC_RSVD6_SFT 10
2536	u8 cc_mode;
2537	#define CMDQ_MODIFY_ROCE_CC_CC_MODE_DCTCP_CC_MODE 0x0UL
2538	#define CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE 0x1UL
2539	#define CMDQ_MODIFY_ROCE_CC_CC_MODE_LAST CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE
2540	u8 tx_queue;
2541	__le16 inactivity_th;
2542	u8 time_per_phase;
2543	u8 reserved8_1;
2544	__le16 reserved16;
2545	__le32 reserved32;
2546	__le64 reserved64;
2547	};
2548
2549	/* cmdq_modify_roce_cc_tlv (size:640b/80B) */
2550	struct cmdq_modify_roce_cc_tlv {
2551	__le16 cmd_discr;
2552	u8 reserved_8b;
2553	u8 tlv_flags;
2554	#define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE 0x1UL
2555	#define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_LAST 0x0UL
2556	#define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL
2557	#define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED 0x2UL
2558	#define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
2559	#define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
2560	#define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_LAST \
2561	CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_YES
2562	__le16 tlv_type;
2563	__le16 length;
2564	u8 total_size;
2565	u8 reserved56[7];
2566	u8 opcode;
2567	#define CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_MODIFY_ROCE_CC 0x8cUL
2568	#define CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_LAST CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_MODIFY_ROCE_CC
2569	u8 cmd_size;
2570	__le16 flags;
2571	__le16 cookie;
2572	u8 resp_size;
2573	u8 reserved8;
2574	__le64 resp_addr;
2575	__le32 modify_mask;
2576	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ENABLE_CC 0x1UL
2577	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_G 0x2UL
2578	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_NUMPHASEPERSTATE 0x4UL
2579	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_CR 0x8UL
2580	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_TR 0x10UL
2581	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_ECN 0x20UL
2582	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_DSCP 0x40UL
2583	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_VLAN_PCP 0x80UL
2584	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_TOS_DSCP 0x100UL
2585	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_RTT 0x200UL
2586	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_CC_MODE 0x400UL
2587	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TCP_CP 0x800UL
2588	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TX_QUEUE 0x1000UL
2589	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INACTIVITY_CP 0x2000UL
2590	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TIME_PER_PHASE 0x4000UL
2591	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_PKTS_PER_PHASE 0x8000UL
2592	u8 enable_cc;
2593	#define CMDQ_MODIFY_ROCE_CC_TLV_ENABLE_CC 0x1UL
2594	#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD1_MASK 0xfeUL
2595	#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD1_SFT 1
2596	u8 g;
2597	u8 num_phases_per_state;
2598	u8 pkts_per_phase;
2599	__le16 init_cr;
2600	__le16 init_tr;
2601	u8 tos_dscp_tos_ecn;
2602	#define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_MASK 0x3UL
2603	#define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_SFT 0
2604	#define CMDQ_MODIFY_ROCE_CC_TLV_TOS_DSCP_MASK 0xfcUL
2605	#define CMDQ_MODIFY_ROCE_CC_TLV_TOS_DSCP_SFT 2
2606	u8 alt_vlan_pcp;
2607	#define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_MASK 0x7UL
2608	#define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_SFT 0
2609	#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD3_MASK 0xf8UL
2610	#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD3_SFT 3
2611	__le16 alt_tos_dscp;
2612	#define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_MASK 0x3fUL
2613	#define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_SFT 0
2614	#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD4_MASK 0xffc0UL
2615	#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD4_SFT 6
2616	__le16 rtt;
2617	#define CMDQ_MODIFY_ROCE_CC_TLV_RTT_MASK 0x3fffUL
2618	#define CMDQ_MODIFY_ROCE_CC_TLV_RTT_SFT 0
2619	#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD5_MASK 0xc000UL
2620	#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD5_SFT 14
2621	__le16 tcp_cp;
2622	#define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_MASK 0x3ffUL
2623	#define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_SFT 0
2624	#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD6_MASK 0xfc00UL
2625	#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD6_SFT 10
2626	u8 cc_mode;
2627	#define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_DCTCP_CC_MODE 0x0UL
2628	#define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_PROBABILISTIC_CC_MODE 0x1UL
2629	#define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_LAST\
2630	CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_PROBABILISTIC_CC_MODE
2631	u8 tx_queue;
2632	__le16 inactivity_th;
2633	u8 time_per_phase;
2634	u8 reserved8_1;
2635	__le16 reserved16;
2636	__le32 reserved32;
2637	__le64 reserved64;
2638	__le64 reservedtlvpad;
2639	};
2640
2641	/* cmdq_modify_roce_cc_gen1_tlv (size:768b/96B) */
2642	struct cmdq_modify_roce_cc_gen1_tlv {
2643	__le16 cmd_discr;
2644	u8 reserved_8b;
2645	u8 tlv_flags;
2646	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE 0x1UL
2647	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_LAST 0x0UL
2648	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL
2649	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED 0x2UL
2650	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
2651	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
2652	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_LAST\
2653	CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_YES
2654	__le16 tlv_type;
2655	__le16 length;
2656	__le64 reserved64;
2657	__le64 modify_mask;
2658	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MIN_TIME_BETWEEN_CNPS 0x1UL
2659	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_INIT_CP 0x2UL
2660	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_MODE 0x4UL
2661	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_CYCLES 0x8UL
2662	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FR_NUM_RTTS 0x10UL
2663	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_AI_RATE_INCREASE 0x20UL
2664	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCTION_RELAX_RTTS_TH 0x40UL
2665	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ADDITIONAL_RELAX_CR_TH 0x80UL
2666	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_MIN_TH 0x100UL
2667	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_BW_AVG_WEIGHT 0x200UL
2668	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_FACTOR 0x400UL
2669	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MAX_CP_CR_TH 0x800UL
2670	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS_EN 0x1000UL
2671	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS 0x2000UL
2672	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_ECN 0x4000UL
2673	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RTT_JITTER_EN 0x8000UL
2674	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK_BYTES_PER_USEC 0x10000UL
2675	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RESET_CC_CR_TH 0x20000UL
2676	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_WIDTH 0x40000UL
2677	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MIN 0x80000UL
2678	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MAX 0x100000UL
2679	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ABS_MAX 0x200000UL
2680	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_LOWER_BOUND 0x400000UL
2681	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_PROB_FACTOR 0x800000UL
2682	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_PROB_FACTOR 0x1000000UL
2683	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FAIRNESS_CR_TH 0x2000000UL
2684	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RED_DIV 0x4000000UL
2685	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_RATIO_TH 0x8000000UL
2686	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_RTTS 0x10000000UL
2687	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_CR_CP_RATIO 0x20000000UL
2688	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_EXP_UPDATE_TH 0x40000000UL
2689	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH1 0x80000000UL
2690	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH2 0x100000000ULL
2691	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_USE_RATE_TABLE 0x200000000ULL
2692	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK64B_PER_RTT 0x400000000ULL
2693	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_CONG_FREE_RTTS_TH 0x800000000ULL
2694	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH1 0x1000000000ULL
2695	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH2 0x2000000000ULL
2696	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CC_ACK_BYTES 0x4000000000ULL
2697	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_EN 0x8000000000ULL
2698	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_CONG_FREE_RTTS_TH \
2699	0x10000000000ULL
2700	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RANDOM_NO_RED_EN 0x20000000000ULL
2701	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_SHIFT_CORRECTION_EN \
2702	0x40000000000ULL
2703	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ADJUST_EN 0x80000000000ULL
2704	__le16 inactivity_th_hi;
2705	__le16 min_time_between_cnps;
2706	__le16 init_cp;
2707	u8 tr_update_mode;
2708	u8 tr_update_cycles;
2709	u8 fr_num_rtts;
2710	u8 ai_rate_increase;
2711	__le16 reduction_relax_rtts_th;
2712	__le16 additional_relax_cr_th;
2713	__le16 cr_min_th;
2714	u8 bw_avg_weight;
2715	u8 actual_cr_factor;
2716	__le16 max_cp_cr_th;
2717	u8 cp_bias_en;
2718	u8 cp_bias;
2719	u8 cnp_ecn;
2720	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_NOT_ECT 0x0UL
2721	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_1 0x1UL
2722	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_0 0x2UL
2723	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_LAST CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_0
2724	u8 rtt_jitter_en;
2725	__le16 link_bytes_per_usec;
2726	__le16 reset_cc_cr_th;
2727	u8 cr_width;
2728	u8 quota_period_min;
2729	u8 quota_period_max;
2730	u8 quota_period_abs_max;
2731	__le16 tr_lower_bound;
2732	u8 cr_prob_factor;
2733	u8 tr_prob_factor;
2734	__le16 fairness_cr_th;
2735	u8 red_div;
2736	u8 cnp_ratio_th;
2737	__le16 exp_ai_rtts;
2738	u8 exp_ai_cr_cp_ratio;
2739	u8 use_rate_table;
2740	__le16 cp_exp_update_th;
2741	__le16 high_exp_ai_rtts_th1;
2742	__le16 high_exp_ai_rtts_th2;
2743	__le16 actual_cr_cong_free_rtts_th;
2744	__le16 severe_cong_cr_th1;
2745	__le16 severe_cong_cr_th2;
2746	__le32 link64B_per_rtt;
2747	u8 cc_ack_bytes;
2748	u8 reduce_init_en;
2749	__le16 reduce_init_cong_free_rtts_th;
2750	u8 random_no_red_en;
2751	u8 actual_cr_shift_correction_en;
2752	u8 quota_period_adjust_en;
2753	u8 reserved[5];
2754	};
2755
2756	/* creq_modify_roce_cc_resp (size:128b/16B) */
2757	struct creq_modify_roce_cc_resp {
2758	u8 type;
2759	#define CREQ_MODIFY_ROCE_CC_RESP_TYPE_MASK 0x3fUL
2760	#define CREQ_MODIFY_ROCE_CC_RESP_TYPE_SFT 0
2761	#define CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT 0x38UL
2762	#define CREQ_MODIFY_ROCE_CC_RESP_TYPE_LAST CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT
2763	u8 status;
2764	__le16 cookie;
2765	__le32 reserved32;
2766	u8 v;
2767	#define CREQ_MODIFY_ROCE_CC_RESP_V 0x1UL
2768	u8 event;
2769	#define CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC 0x8cUL
2770	#define CREQ_MODIFY_ROCE_CC_RESP_EVENT_LAST CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC
2771	u8 reserved48[6];
2772	};
2773
2774	/* cmdq_set_link_aggr_mode_cc (size:320b/40B) */
2775	struct cmdq_set_link_aggr_mode_cc {
2776	u8 opcode;
2777	#define CMDQ_SET_LINK_AGGR_MODE_OPCODE_SET_LINK_AGGR_MODE 0x8fUL
2778	#define CMDQ_SET_LINK_AGGR_MODE_OPCODE_LAST \
2779	CMDQ_SET_LINK_AGGR_MODE_OPCODE_SET_LINK_AGGR_MODE
2780	u8 cmd_size;
2781	__le16 flags;
2782	__le16 cookie;
2783	u8 resp_size;
2784	u8 reserved8;
2785	__le64 resp_addr;
2786	__le32 modify_mask;
2787	#define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_EN 0x1UL
2788	#define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_ACTIVE_PORT_MAP 0x2UL
2789	#define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_MEMBER_PORT_MAP 0x4UL
2790	#define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_MODE 0x8UL
2791	#define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_STAT_CTX_ID 0x10UL
2792	u8 aggr_enable;
2793	#define CMDQ_SET_LINK_AGGR_MODE_AGGR_ENABLE 0x1UL
2794	#define CMDQ_SET_LINK_AGGR_MODE_RSVD1_MASK 0xfeUL
2795	#define CMDQ_SET_LINK_AGGR_MODE_RSVD1_SFT 1
2796	u8 active_port_map;
2797	#define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_MASK 0xfUL
2798	#define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_SFT 0
2799	#define CMDQ_SET_LINK_AGGR_MODE_RSVD2_MASK 0xf0UL
2800	#define CMDQ_SET_LINK_AGGR_MODE_RSVD2_SFT 4
2801	u8 member_port_map;
2802	u8 link_aggr_mode;
2803	#define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_ACTIVE 0x1UL
2804	#define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_BACKUP 0x2UL
2805	#define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_BALANCE_XOR 0x3UL
2806	#define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_802_3_AD 0x4UL
2807	#define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_LAST CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_802_3_AD
2808	__le16 stat_ctx_id[4];
2809	__le64 rsvd1;
2810	};
2811
2812	/* creq_set_link_aggr_mode_resources_resp (size:128b/16B) */
2813	struct creq_set_link_aggr_mode_resources_resp {
2814	u8 type;
2815	#define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_MASK 0x3fUL
2816	#define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_SFT 0
2817	#define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_QP_EVENT 0x38UL
2818	#define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_LAST CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_QP_EVENT
2819	u8 status;
2820	__le16 cookie;
2821	__le32 reserved32;
2822	u8 v;
2823	#define CREQ_SET_LINK_AGGR_MODE_RESP_V 0x1UL
2824	u8 event;
2825	#define CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_SET_LINK_AGGR_MODE 0x8fUL
2826	#define CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_LAST\
2827	CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_SET_LINK_AGGR_MODE
2828	u8 reserved48[6];
2829	};
2830
2831	/* creq_func_event (size:128b/16B) */
2832	struct creq_func_event {
2833	u8 type;
2834	#define CREQ_FUNC_EVENT_TYPE_MASK 0x3fUL
2835	#define CREQ_FUNC_EVENT_TYPE_SFT 0
2836	#define CREQ_FUNC_EVENT_TYPE_FUNC_EVENT 0x3aUL
2837	#define CREQ_FUNC_EVENT_TYPE_LAST CREQ_FUNC_EVENT_TYPE_FUNC_EVENT
2838	u8 reserved56[7];
2839	u8 v;
2840	#define CREQ_FUNC_EVENT_V 0x1UL
2841	u8 event;
2842	#define CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR 0x1UL
2843	#define CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR 0x2UL
2844	#define CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR 0x3UL
2845	#define CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR 0x4UL
2846	#define CREQ_FUNC_EVENT_EVENT_CQ_ERROR 0x5UL
2847	#define CREQ_FUNC_EVENT_EVENT_TQM_ERROR 0x6UL
2848	#define CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR 0x7UL
2849	#define CREQ_FUNC_EVENT_EVENT_CFCS_ERROR 0x8UL
2850	#define CREQ_FUNC_EVENT_EVENT_CFCC_ERROR 0x9UL
2851	#define CREQ_FUNC_EVENT_EVENT_CFCM_ERROR 0xaUL
2852	#define CREQ_FUNC_EVENT_EVENT_TIM_ERROR 0xbUL
2853	#define CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST 0x80UL
2854	#define CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED 0x81UL
2855	#define CREQ_FUNC_EVENT_EVENT_LAST CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED
2856	u8 reserved48[6];
2857	};
2858
2859	/* creq_qp_event (size:128b/16B) */
2860	struct creq_qp_event {
2861	u8 type;
2862	#define CREQ_QP_EVENT_TYPE_MASK 0x3fUL
2863	#define CREQ_QP_EVENT_TYPE_SFT 0
2864	#define CREQ_QP_EVENT_TYPE_QP_EVENT 0x38UL
2865	#define CREQ_QP_EVENT_TYPE_LAST CREQ_QP_EVENT_TYPE_QP_EVENT
2866	u8 status;
2867	#define CREQ_QP_EVENT_STATUS_SUCCESS 0x0UL
2868	#define CREQ_QP_EVENT_STATUS_FAIL 0x1UL
2869	#define CREQ_QP_EVENT_STATUS_RESOURCES 0x2UL
2870	#define CREQ_QP_EVENT_STATUS_INVALID_CMD 0x3UL
2871	#define CREQ_QP_EVENT_STATUS_NOT_IMPLEMENTED 0x4UL
2872	#define CREQ_QP_EVENT_STATUS_INVALID_PARAMETER 0x5UL
2873	#define CREQ_QP_EVENT_STATUS_HARDWARE_ERROR 0x6UL
2874	#define CREQ_QP_EVENT_STATUS_INTERNAL_ERROR 0x7UL
2875	#define CREQ_QP_EVENT_STATUS_LAST CREQ_QP_EVENT_STATUS_INTERNAL_ERROR
2876	__le16 cookie;
2877	__le32 reserved32;
2878	u8 v;
2879	#define CREQ_QP_EVENT_V 0x1UL
2880	u8 event;
2881	#define CREQ_QP_EVENT_EVENT_CREATE_QP 0x1UL
2882	#define CREQ_QP_EVENT_EVENT_DESTROY_QP 0x2UL
2883	#define CREQ_QP_EVENT_EVENT_MODIFY_QP 0x3UL
2884	#define CREQ_QP_EVENT_EVENT_QUERY_QP 0x4UL
2885	#define CREQ_QP_EVENT_EVENT_CREATE_SRQ 0x5UL
2886	#define CREQ_QP_EVENT_EVENT_DESTROY_SRQ 0x6UL
2887	#define CREQ_QP_EVENT_EVENT_QUERY_SRQ 0x8UL
2888	#define CREQ_QP_EVENT_EVENT_CREATE_CQ 0x9UL
2889	#define CREQ_QP_EVENT_EVENT_DESTROY_CQ 0xaUL
2890	#define CREQ_QP_EVENT_EVENT_RESIZE_CQ 0xcUL
2891	#define CREQ_QP_EVENT_EVENT_ALLOCATE_MRW 0xdUL
2892	#define CREQ_QP_EVENT_EVENT_DEALLOCATE_KEY 0xeUL
2893	#define CREQ_QP_EVENT_EVENT_REGISTER_MR 0xfUL
2894	#define CREQ_QP_EVENT_EVENT_DEREGISTER_MR 0x10UL
2895	#define CREQ_QP_EVENT_EVENT_ADD_GID 0x11UL
2896	#define CREQ_QP_EVENT_EVENT_DELETE_GID 0x12UL
2897	#define CREQ_QP_EVENT_EVENT_MODIFY_GID 0x17UL
2898	#define CREQ_QP_EVENT_EVENT_QUERY_GID 0x18UL
2899	#define CREQ_QP_EVENT_EVENT_CREATE_QP1 0x13UL
2900	#define CREQ_QP_EVENT_EVENT_DESTROY_QP1 0x14UL
2901	#define CREQ_QP_EVENT_EVENT_CREATE_AH 0x15UL
2902	#define CREQ_QP_EVENT_EVENT_DESTROY_AH 0x16UL
2903	#define CREQ_QP_EVENT_EVENT_INITIALIZE_FW 0x80UL
2904	#define CREQ_QP_EVENT_EVENT_DEINITIALIZE_FW 0x81UL
2905	#define CREQ_QP_EVENT_EVENT_STOP_FUNC 0x82UL
2906	#define CREQ_QP_EVENT_EVENT_QUERY_FUNC 0x83UL
2907	#define CREQ_QP_EVENT_EVENT_SET_FUNC_RESOURCES 0x84UL
2908	#define CREQ_QP_EVENT_EVENT_READ_CONTEXT 0x85UL
2909	#define CREQ_QP_EVENT_EVENT_MAP_TC_TO_COS 0x8aUL
2910	#define CREQ_QP_EVENT_EVENT_QUERY_VERSION 0x8bUL
2911	#define CREQ_QP_EVENT_EVENT_MODIFY_CC 0x8cUL
2912	#define CREQ_QP_EVENT_EVENT_QUERY_CC 0x8dUL
2913	#define CREQ_QP_EVENT_EVENT_QUERY_ROCE_STATS 0x8eUL
2914	#define CREQ_QP_EVENT_EVENT_SET_LINK_AGGR_MODE 0x8fUL
2915	#define CREQ_QP_EVENT_EVENT_QUERY_QP_EXTEND 0x91UL
2916	#define CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION 0xc0UL
2917	#define CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION 0xc1UL
2918	#define CREQ_QP_EVENT_EVENT_LAST CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION
2919	u8 reserved48[6];
2920	};
2921
2922	/* creq_qp_error_notification (size:128b/16B) */
2923	struct creq_qp_error_notification {
2924	u8 type;
2925	#define CREQ_QP_ERROR_NOTIFICATION_TYPE_MASK 0x3fUL
2926	#define CREQ_QP_ERROR_NOTIFICATION_TYPE_SFT 0
2927	#define CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT 0x38UL
2928	#define CREQ_QP_ERROR_NOTIFICATION_TYPE_LAST CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT
2929	u8 status;
2930	u8 req_slow_path_state;
2931	u8 req_err_state_reason;
2932	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_NO_ERROR 0X0UL
2933	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_OPCODE_ERROR 0X1UL
2934	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TIMEOUT_RETRY_LIMIT 0X2UL
2935	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RNR_TIMEOUT_RETRY_LIMIT 0X3UL
2936	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_1 0X4UL
2937	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_2 0X5UL
2938	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_3 0X6UL
2939	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_4 0X7UL
2940	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_MEMORY_ERROR 0X8UL
2941	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_MEMORY_ERROR 0X9UL
2942	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_READ_RESP_LENGTH 0XAUL
2943	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_READ_RESP 0XBUL
2944	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_BIND 0XCUL
2945	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_FAST_REG 0XDUL
2946	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_INVALIDATE 0XEUL
2947	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CMP_ERROR 0XFUL
2948	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETRAN_LOCAL_ERROR 0X10UL
2949	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_WQE_FORMAT_ERROR 0X11UL
2950	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ORRQ_FORMAT_ERROR 0X12UL
2951	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_AVID_ERROR 0X13UL
2952	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_AV_DOMAIN_ERROR 0X14UL
2953	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CQ_LOAD_ERROR 0X15UL
2954	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SERV_TYPE_ERROR 0X16UL
2955	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_OP_ERROR 0X17UL
2956	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_PCI_ERROR 0X18UL
2957	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_PCI_ERROR 0X19UL
2958	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PROD_WQE_MSMTCH_ERROR 0X1AUL
2959	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PSN_RANGE_CHECK_ERROR 0X1BUL
2960	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETX_SETUP_ERROR 0X1CUL
2961	__le32 xid;
2962	u8 v;
2963	#define CREQ_QP_ERROR_NOTIFICATION_V 0x1UL
2964	u8 event;
2965	#define CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION 0xc0UL
2966	#define CREQ_QP_ERROR_NOTIFICATION_EVENT_LAST \
2967	CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION
2968	u8 res_slow_path_state;
2969	u8 res_err_state_reason;
2970	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_NO_ERROR 0x0UL
2971	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEED_MAX 0x1UL
2972	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PAYLOAD_LENGTH_MISMATCH 0x2UL
2973	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEEDS_WQE 0x3UL
2974	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_OPCODE_ERROR 0x4UL
2975	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_SEQ_ERROR_RETRY_LIMIT 0x5UL
2976	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_INVALID_R_KEY 0x6UL
2977	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_DOMAIN_ERROR 0x7UL
2978	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_NO_PERMISSION 0x8UL
2979	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_RANGE_ERROR 0x9UL
2980	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_INVALID_R_KEY 0xaUL
2981	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_DOMAIN_ERROR 0xbUL
2982	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_NO_PERMISSION 0xcUL
2983	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_RANGE_ERROR 0xdUL
2984	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_OFLOW 0xeUL
2985	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNSUPPORTED_OPCODE 0xfUL
2986	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNALIGN_ATOMIC 0x10UL
2987	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_REM_INVALIDATE 0x11UL
2988	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_MEMORY_ERROR 0x12UL
2989	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_ERROR 0x13UL
2990	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CMP_ERROR 0x14UL
2991	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_INVALID_DUP_RKEY 0x15UL
2992	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_WQE_FORMAT_ERROR 0x16UL
2993	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_FORMAT_ERROR 0x17UL
2994	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CQ_LOAD_ERROR 0x18UL
2995	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_LOAD_ERROR 0x19UL
2996	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_PCI_ERROR 0x1bUL
2997	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_PCI_ERROR 0x1cUL
2998	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_NOT_FOUND 0x1dUL
2999	__le16 sq_cons_idx;
3000	__le16 rq_cons_idx;
3001	};
3002
3003	/* creq_cq_error_notification (size:128b/16B) */
3004	struct creq_cq_error_notification {
3005	u8 type;
3006	#define CREQ_CQ_ERROR_NOTIFICATION_TYPE_MASK 0x3fUL
3007	#define CREQ_CQ_ERROR_NOTIFICATION_TYPE_SFT 0
3008	#define CREQ_CQ_ERROR_NOTIFICATION_TYPE_CQ_EVENT 0x38UL
3009	#define CREQ_CQ_ERROR_NOTIFICATION_TYPE_LAST CREQ_CQ_ERROR_NOTIFICATION_TYPE_CQ_EVENT
3010	u8 status;
3011	u8 cq_err_reason;
3012	#define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_INVALID_ERROR 0x1UL
3013	#define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_OVERFLOW_ERROR 0x2UL
3014	#define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_LOAD_ERROR 0x3UL
3015	#define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_INVALID_ERROR 0x4UL
3016	#define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_OVERFLOW_ERROR 0x5UL
3017	#define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR 0x6UL
3018	#define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_LAST \
3019	CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR
3020	u8 reserved8;
3021	__le32 xid;
3022	u8 v;
3023	#define CREQ_CQ_ERROR_NOTIFICATION_V 0x1UL
3024	u8 event;
3025	#define CREQ_CQ_ERROR_NOTIFICATION_EVENT_CQ_ERROR_NOTIFICATION 0xc1UL
3026	#define CREQ_CQ_ERROR_NOTIFICATION_EVENT_LAST \
3027	CREQ_CQ_ERROR_NOTIFICATION_EVENT_CQ_ERROR_NOTIFICATION
3028	u8 reserved48[6];
3029	};
3030
3031	/* sq_base (size:64b/8B) */
3032	struct sq_base {
3033	u8 wqe_type;
3034	#define SQ_BASE_WQE_TYPE_SEND 0x0UL
3035	#define SQ_BASE_WQE_TYPE_SEND_W_IMMEAD 0x1UL
3036	#define SQ_BASE_WQE_TYPE_SEND_W_INVALID 0x2UL
3037	#define SQ_BASE_WQE_TYPE_WRITE_WQE 0x4UL
3038	#define SQ_BASE_WQE_TYPE_WRITE_W_IMMEAD 0x5UL
3039	#define SQ_BASE_WQE_TYPE_READ_WQE 0x6UL
3040	#define SQ_BASE_WQE_TYPE_ATOMIC_CS 0x8UL
3041	#define SQ_BASE_WQE_TYPE_ATOMIC_FA 0xbUL
3042	#define SQ_BASE_WQE_TYPE_LOCAL_INVALID 0xcUL
3043	#define SQ_BASE_WQE_TYPE_FR_PMR 0xdUL
3044	#define SQ_BASE_WQE_TYPE_BIND 0xeUL
3045	#define SQ_BASE_WQE_TYPE_FR_PPMR 0xfUL
3046	#define SQ_BASE_WQE_TYPE_LAST SQ_BASE_WQE_TYPE_FR_PPMR
3047	u8 unused_0[7];
3048	};
3049
3050	/* sq_sge (size:128b/16B) */
3051	struct sq_sge {
3052	__le64 va_or_pa;
3053	__le32 l_key;
3054	__le32 size;
3055	};
3056
3057	/* sq_psn_search (size:64b/8B) */
3058	struct sq_psn_search {
3059	__le32 opcode_start_psn;
3060	#define SQ_PSN_SEARCH_START_PSN_MASK 0xffffffUL
3061	#define SQ_PSN_SEARCH_START_PSN_SFT 0
3062	#define SQ_PSN_SEARCH_OPCODE_MASK 0xff000000UL
3063	#define SQ_PSN_SEARCH_OPCODE_SFT 24
3064	__le32 flags_next_psn;
3065	#define SQ_PSN_SEARCH_NEXT_PSN_MASK 0xffffffUL
3066	#define SQ_PSN_SEARCH_NEXT_PSN_SFT 0
3067	#define SQ_PSN_SEARCH_FLAGS_MASK 0xff000000UL
3068	#define SQ_PSN_SEARCH_FLAGS_SFT 24
3069	};
3070
3071	/* sq_psn_search_ext (size:128b/16B) */
3072	struct sq_psn_search_ext {
3073	__le32 opcode_start_psn;
3074	#define SQ_PSN_SEARCH_EXT_START_PSN_MASK 0xffffffUL
3075	#define SQ_PSN_SEARCH_EXT_START_PSN_SFT 0
3076	#define SQ_PSN_SEARCH_EXT_OPCODE_MASK 0xff000000UL
3077	#define SQ_PSN_SEARCH_EXT_OPCODE_SFT 24
3078	__le32 flags_next_psn;
3079	#define SQ_PSN_SEARCH_EXT_NEXT_PSN_MASK 0xffffffUL
3080	#define SQ_PSN_SEARCH_EXT_NEXT_PSN_SFT 0
3081	#define SQ_PSN_SEARCH_EXT_FLAGS_MASK 0xff000000UL
3082	#define SQ_PSN_SEARCH_EXT_FLAGS_SFT 24
3083	__le16 start_slot_idx;
3084	__le16 reserved16;
3085	__le32 reserved32;
3086	};
3087
3088	/* sq_msn_search (size:64b/8B) */
3089	struct sq_msn_search {
3090	__le64 start_idx_next_psn_start_psn;
3091	#define SQ_MSN_SEARCH_START_PSN_MASK 0xffffffUL
3092	#define SQ_MSN_SEARCH_START_PSN_SFT 0
3093	#define SQ_MSN_SEARCH_NEXT_PSN_MASK 0xffffff000000ULL
3094	#define SQ_MSN_SEARCH_NEXT_PSN_SFT 24
3095	#define SQ_MSN_SEARCH_START_IDX_MASK 0xffff000000000000ULL
3096	#define SQ_MSN_SEARCH_START_IDX_SFT 48
3097	};
3098
3099	/* sq_send (size:1024b/128B) */
3100	struct sq_send {
3101	u8 wqe_type;
3102	#define SQ_SEND_WQE_TYPE_SEND 0x0UL
3103	#define SQ_SEND_WQE_TYPE_SEND_W_IMMEAD 0x1UL
3104	#define SQ_SEND_WQE_TYPE_SEND_W_INVALID 0x2UL
3105	#define SQ_SEND_WQE_TYPE_LAST SQ_SEND_WQE_TYPE_SEND_W_INVALID
3106	u8 flags;
3107	#define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3108	#define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3109	#define SQ_SEND_FLAGS_SIGNAL_COMP 0x1UL
3110	#define SQ_SEND_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3111	#define SQ_SEND_FLAGS_UC_FENCE 0x4UL
3112	#define SQ_SEND_FLAGS_SE 0x8UL
3113	#define SQ_SEND_FLAGS_INLINE 0x10UL
3114	#define SQ_SEND_FLAGS_WQE_TS_EN 0x20UL
3115	#define SQ_SEND_FLAGS_DEBUG_TRACE 0x40UL
3116	u8 wqe_size;
3117	u8 reserved8_1;
3118	__le32 inv_key_or_imm_data;
3119	__le32 length;
3120	__le32 q_key;
3121	__le32 dst_qp;
3122	#define SQ_SEND_DST_QP_MASK 0xffffffUL
3123	#define SQ_SEND_DST_QP_SFT 0
3124	__le32 avid;
3125	#define SQ_SEND_AVID_MASK 0xfffffUL
3126	#define SQ_SEND_AVID_SFT 0
3127	__le32 reserved32;
3128	__le32 timestamp;
3129	#define SQ_SEND_TIMESTAMP_MASK 0xffffffUL
3130	#define SQ_SEND_TIMESTAMP_SFT 0
3131	__le32 data[24];
3132	};
3133
3134	/* sq_send_hdr (size:256b/32B) */
3135	struct sq_send_hdr {
3136	u8 wqe_type;
3137	#define SQ_SEND_HDR_WQE_TYPE_SEND 0x0UL
3138	#define SQ_SEND_HDR_WQE_TYPE_SEND_W_IMMEAD 0x1UL
3139	#define SQ_SEND_HDR_WQE_TYPE_SEND_W_INVALID 0x2UL
3140	#define SQ_SEND_HDR_WQE_TYPE_LAST SQ_SEND_HDR_WQE_TYPE_SEND_W_INVALID
3141	u8 flags;
3142	#define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3143	#define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3144	#define SQ_SEND_HDR_FLAGS_SIGNAL_COMP 0x1UL
3145	#define SQ_SEND_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3146	#define SQ_SEND_HDR_FLAGS_UC_FENCE 0x4UL
3147	#define SQ_SEND_HDR_FLAGS_SE 0x8UL
3148	#define SQ_SEND_HDR_FLAGS_INLINE 0x10UL
3149	#define SQ_SEND_HDR_FLAGS_WQE_TS_EN 0x20UL
3150	#define SQ_SEND_HDR_FLAGS_DEBUG_TRACE 0x40UL
3151	u8 wqe_size;
3152	u8 reserved8_1;
3153	__le32 inv_key_or_imm_data;
3154	__le32 length;
3155	__le32 q_key;
3156	__le32 dst_qp;
3157	#define SQ_SEND_HDR_DST_QP_MASK 0xffffffUL
3158	#define SQ_SEND_HDR_DST_QP_SFT 0
3159	__le32 avid;
3160	#define SQ_SEND_HDR_AVID_MASK 0xfffffUL
3161	#define SQ_SEND_HDR_AVID_SFT 0
3162	__le32 reserved32;
3163	__le32 timestamp;
3164	#define SQ_SEND_HDR_TIMESTAMP_MASK 0xffffffUL
3165	#define SQ_SEND_HDR_TIMESTAMP_SFT 0
3166	};
3167
3168	/* sq_send_raweth_qp1 (size:1024b/128B) */
3169	struct sq_send_raweth_qp1 {
3170	u8 wqe_type;
3171	#define SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND 0x0UL
3172	#define SQ_SEND_RAWETH_QP1_WQE_TYPE_LAST SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND
3173	u8 flags;
3174	#define SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK \
3175	0xffUL
3176	#define SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT \
3177	0
3178	#define SQ_SEND_RAWETH_QP1_FLAGS_SIGNAL_COMP 0x1UL
3179	#define SQ_SEND_RAWETH_QP1_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3180	#define SQ_SEND_RAWETH_QP1_FLAGS_UC_FENCE 0x4UL
3181	#define SQ_SEND_RAWETH_QP1_FLAGS_SE 0x8UL
3182	#define SQ_SEND_RAWETH_QP1_FLAGS_INLINE 0x10UL
3183	#define SQ_SEND_RAWETH_QP1_FLAGS_WQE_TS_EN 0x20UL
3184	#define SQ_SEND_RAWETH_QP1_FLAGS_DEBUG_TRACE 0x40UL
3185	u8 wqe_size;
3186	u8 reserved8;
3187	__le16 lflags;
3188	#define SQ_SEND_RAWETH_QP1_LFLAGS_TCP_UDP_CHKSUM 0x1UL
3189	#define SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM 0x2UL
3190	#define SQ_SEND_RAWETH_QP1_LFLAGS_NOCRC 0x4UL
3191	#define SQ_SEND_RAWETH_QP1_LFLAGS_STAMP 0x8UL
3192	#define SQ_SEND_RAWETH_QP1_LFLAGS_T_IP_CHKSUM 0x10UL
3193	#define SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC 0x100UL
3194	#define SQ_SEND_RAWETH_QP1_LFLAGS_FCOE_CRC 0x200UL
3195	__le16 cfa_action;
3196	__le32 length;
3197	__le32 reserved32_1;
3198	__le32 cfa_meta;
3199	#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_MASK 0xfffUL
3200	#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_SFT 0
3201	#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_DE 0x1000UL
3202	#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_MASK 0xe000UL
3203	#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_SFT 13
3204	#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_MASK 0x70000UL
3205	#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_SFT 16
3206	#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID88A8 (0x0UL << 16)
3207	#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID8100 (0x1UL << 16)
3208	#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9100 (0x2UL << 16)
3209	#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9200 (0x3UL << 16)
3210	#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9300 (0x4UL << 16)
3211	#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG (0x5UL << 16)
3212	#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_LAST\
3213	SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG
3214	#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_MASK 0xff80000UL
3215	#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_SFT 19
3216	#define SQ_SEND_RAWETH_QP1_CFA_META_KEY_MASK 0xf0000000UL
3217	#define SQ_SEND_RAWETH_QP1_CFA_META_KEY_SFT 28
3218	#define SQ_SEND_RAWETH_QP1_CFA_META_KEY_NONE (0x0UL << 28)
3219	#define SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG (0x1UL << 28)
3220	#define SQ_SEND_RAWETH_QP1_CFA_META_KEY_LAST SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG
3221	__le32 reserved32_2;
3222	__le32 reserved32_3;
3223	__le32 timestamp;
3224	#define SQ_SEND_RAWETH_QP1_TIMESTAMP_MASK 0xffffffUL
3225	#define SQ_SEND_RAWETH_QP1_TIMESTAMP_SFT 0
3226	__le32 data[24];
3227	};
3228
3229	/* sq_send_raweth_qp1_hdr (size:256b/32B) */
3230	struct sq_send_raweth_qp1_hdr {
3231	u8 wqe_type;
3232	#define SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_SEND 0x0UL
3233	#define SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_LAST SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_SEND
3234	u8 flags;
3235	#define \
3236	SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3237	#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT\
3238	0
3239	#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SIGNAL_COMP 0x1UL
3240	#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3241	#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_UC_FENCE 0x4UL
3242	#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SE 0x8UL
3243	#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE 0x10UL
3244	#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_WQE_TS_EN 0x20UL
3245	#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_DEBUG_TRACE 0x40UL
3246	u8 wqe_size;
3247	u8 reserved8;
3248	__le16 lflags;
3249	#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_TCP_UDP_CHKSUM 0x1UL
3250	#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_IP_CHKSUM 0x2UL
3251	#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_NOCRC 0x4UL
3252	#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_STAMP 0x8UL
3253	#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_T_IP_CHKSUM 0x10UL
3254	#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_ROCE_CRC 0x100UL
3255	#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_FCOE_CRC 0x200UL
3256	__le16 cfa_action;
3257	__le32 length;
3258	__le32 reserved32_1;
3259	__le32 cfa_meta;
3260	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_MASK 0xfffUL
3261	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_SFT 0
3262	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_DE 0x1000UL
3263	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_PRI_MASK 0xe000UL
3264	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_PRI_SFT 13
3265	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_MASK 0x70000UL
3266	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_SFT 16
3267	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID88A8 (0x0UL << 16)
3268	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID8100 (0x1UL << 16)
3269	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9100 (0x2UL << 16)
3270	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9200 (0x3UL << 16)
3271	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9300 (0x4UL << 16)
3272	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPIDCFG (0x5UL << 16)
3273	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_LAST\
3274	SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPIDCFG
3275	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_RESERVED_MASK 0xff80000UL
3276	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_RESERVED_SFT 19
3277	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_MASK 0xf0000000UL
3278	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_SFT 28
3279	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_NONE (0x0UL << 28)
3280	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_VLAN_TAG (0x1UL << 28)
3281	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_LAST\
3282	SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_VLAN_TAG
3283	__le32 reserved32_2;
3284	__le32 reserved32_3;
3285	__le32 timestamp;
3286	#define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_MASK 0xffffffUL
3287	#define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_SFT 0
3288	};
3289
3290	/* sq_rdma (size:1024b/128B) */
3291	struct sq_rdma {
3292	u8 wqe_type;
3293	#define SQ_RDMA_WQE_TYPE_WRITE_WQE 0x4UL
3294	#define SQ_RDMA_WQE_TYPE_WRITE_W_IMMEAD 0x5UL
3295	#define SQ_RDMA_WQE_TYPE_READ_WQE 0x6UL
3296	#define SQ_RDMA_WQE_TYPE_LAST SQ_RDMA_WQE_TYPE_READ_WQE
3297	u8 flags;
3298	#define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3299	#define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3300	#define SQ_RDMA_FLAGS_SIGNAL_COMP 0x1UL
3301	#define SQ_RDMA_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3302	#define SQ_RDMA_FLAGS_UC_FENCE 0x4UL
3303	#define SQ_RDMA_FLAGS_SE 0x8UL
3304	#define SQ_RDMA_FLAGS_INLINE 0x10UL
3305	#define SQ_RDMA_FLAGS_WQE_TS_EN 0x20UL
3306	#define SQ_RDMA_FLAGS_DEBUG_TRACE 0x40UL
3307	u8 wqe_size;
3308	u8 reserved8;
3309	__le32 imm_data;
3310	__le32 length;
3311	__le32 reserved32_1;
3312	__le64 remote_va;
3313	__le32 remote_key;
3314	__le32 timestamp;
3315	#define SQ_RDMA_TIMESTAMP_MASK 0xffffffUL
3316	#define SQ_RDMA_TIMESTAMP_SFT 0
3317	__le32 data[24];
3318	};
3319
3320	/* sq_rdma_hdr (size:256b/32B) */
3321	struct sq_rdma_hdr {
3322	u8 wqe_type;
3323	#define SQ_RDMA_HDR_WQE_TYPE_WRITE_WQE 0x4UL
3324	#define SQ_RDMA_HDR_WQE_TYPE_WRITE_W_IMMEAD 0x5UL
3325	#define SQ_RDMA_HDR_WQE_TYPE_READ_WQE 0x6UL
3326	#define SQ_RDMA_HDR_WQE_TYPE_LAST SQ_RDMA_HDR_WQE_TYPE_READ_WQE
3327	u8 flags;
3328	#define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3329	#define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3330	#define SQ_RDMA_HDR_FLAGS_SIGNAL_COMP 0x1UL
3331	#define SQ_RDMA_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3332	#define SQ_RDMA_HDR_FLAGS_UC_FENCE 0x4UL
3333	#define SQ_RDMA_HDR_FLAGS_SE 0x8UL
3334	#define SQ_RDMA_HDR_FLAGS_INLINE 0x10UL
3335	#define SQ_RDMA_HDR_FLAGS_WQE_TS_EN 0x20UL
3336	#define SQ_RDMA_HDR_FLAGS_DEBUG_TRACE 0x40UL
3337	u8 wqe_size;
3338	u8 reserved8;
3339	__le32 imm_data;
3340	__le32 length;
3341	__le32 reserved32_1;
3342	__le64 remote_va;
3343	__le32 remote_key;
3344	__le32 timestamp;
3345	#define SQ_RDMA_HDR_TIMESTAMP_MASK 0xffffffUL
3346	#define SQ_RDMA_HDR_TIMESTAMP_SFT 0
3347	};
3348
3349	/* sq_atomic (size:1024b/128B) */
3350	struct sq_atomic {
3351	u8 wqe_type;
3352	#define SQ_ATOMIC_WQE_TYPE_ATOMIC_CS 0x8UL
3353	#define SQ_ATOMIC_WQE_TYPE_ATOMIC_FA 0xbUL
3354	#define SQ_ATOMIC_WQE_TYPE_LAST SQ_ATOMIC_WQE_TYPE_ATOMIC_FA
3355	u8 flags;
3356	#define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3357	#define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3358	#define SQ_ATOMIC_FLAGS_SIGNAL_COMP 0x1UL
3359	#define SQ_ATOMIC_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3360	#define SQ_ATOMIC_FLAGS_UC_FENCE 0x4UL
3361	#define SQ_ATOMIC_FLAGS_SE 0x8UL
3362	#define SQ_ATOMIC_FLAGS_INLINE 0x10UL
3363	#define SQ_ATOMIC_FLAGS_WQE_TS_EN 0x20UL
3364	#define SQ_ATOMIC_FLAGS_DEBUG_TRACE 0x40UL
3365	__le16 reserved16;
3366	__le32 remote_key;
3367	__le64 remote_va;
3368	__le64 swap_data;
3369	__le64 cmp_data;
3370	__le32 data[24];
3371	};
3372
3373	/* sq_atomic_hdr (size:256b/32B) */
3374	struct sq_atomic_hdr {
3375	u8 wqe_type;
3376	#define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_CS 0x8UL
3377	#define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_FA 0xbUL
3378	#define SQ_ATOMIC_HDR_WQE_TYPE_LAST SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_FA
3379	u8 flags;
3380	#define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3381	#define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3382	#define SQ_ATOMIC_HDR_FLAGS_SIGNAL_COMP 0x1UL
3383	#define SQ_ATOMIC_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3384	#define SQ_ATOMIC_HDR_FLAGS_UC_FENCE 0x4UL
3385	#define SQ_ATOMIC_HDR_FLAGS_SE 0x8UL
3386	#define SQ_ATOMIC_HDR_FLAGS_INLINE 0x10UL
3387	#define SQ_ATOMIC_HDR_FLAGS_WQE_TS_EN 0x20UL
3388	#define SQ_ATOMIC_HDR_FLAGS_DEBUG_TRACE 0x40UL
3389	__le16 reserved16;
3390	__le32 remote_key;
3391	__le64 remote_va;
3392	__le64 swap_data;
3393	__le64 cmp_data;
3394	};
3395
3396	/* sq_localinvalidate (size:1024b/128B) */
3397	struct sq_localinvalidate {
3398	u8 wqe_type;
3399	#define SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID 0xcUL
3400	#define SQ_LOCALINVALIDATE_WQE_TYPE_LAST SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID
3401	u8 flags;
3402	#define SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK\
3403	0xffUL
3404	#define SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT\
3405	0
3406	#define SQ_LOCALINVALIDATE_FLAGS_SIGNAL_COMP 0x1UL
3407	#define SQ_LOCALINVALIDATE_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3408	#define SQ_LOCALINVALIDATE_FLAGS_UC_FENCE 0x4UL
3409	#define SQ_LOCALINVALIDATE_FLAGS_SE 0x8UL
3410	#define SQ_LOCALINVALIDATE_FLAGS_INLINE 0x10UL
3411	#define SQ_LOCALINVALIDATE_FLAGS_WQE_TS_EN 0x20UL
3412	#define SQ_LOCALINVALIDATE_FLAGS_DEBUG_TRACE 0x40UL
3413	__le16 reserved16;
3414	__le32 inv_l_key;
3415	__le64 reserved64;
3416	u8 reserved128[16];
3417	__le32 data[24];
3418	};
3419
3420	/* sq_localinvalidate_hdr (size:256b/32B) */
3421	struct sq_localinvalidate_hdr {
3422	u8 wqe_type;
3423	#define SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LOCAL_INVALID 0xcUL
3424	#define SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LAST SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LOCAL_INVALID
3425	u8 flags;
3426	#define \
3427	SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3428	#define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT\
3429	0
3430	#define SQ_LOCALINVALIDATE_HDR_FLAGS_SIGNAL_COMP 0x1UL
3431	#define SQ_LOCALINVALIDATE_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3432	#define SQ_LOCALINVALIDATE_HDR_FLAGS_UC_FENCE 0x4UL
3433	#define SQ_LOCALINVALIDATE_HDR_FLAGS_SE 0x8UL
3434	#define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE 0x10UL
3435	#define SQ_LOCALINVALIDATE_HDR_FLAGS_WQE_TS_EN 0x20UL
3436	#define SQ_LOCALINVALIDATE_HDR_FLAGS_DEBUG_TRACE 0x40UL
3437	__le16 reserved16;
3438	__le32 inv_l_key;
3439	__le64 reserved64;
3440	u8 reserved128[16];
3441	};
3442
3443	/* sq_fr_pmr (size:1024b/128B) */
3444	struct sq_fr_pmr {
3445	u8 wqe_type;
3446	#define SQ_FR_PMR_WQE_TYPE_FR_PMR 0xdUL
3447	#define SQ_FR_PMR_WQE_TYPE_LAST SQ_FR_PMR_WQE_TYPE_FR_PMR
3448	u8 flags;
3449	#define SQ_FR_PMR_FLAGS_SIGNAL_COMP 0x1UL
3450	#define SQ_FR_PMR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3451	#define SQ_FR_PMR_FLAGS_UC_FENCE 0x4UL
3452	#define SQ_FR_PMR_FLAGS_SE 0x8UL
3453	#define SQ_FR_PMR_FLAGS_INLINE 0x10UL
3454	#define SQ_FR_PMR_FLAGS_WQE_TS_EN 0x20UL
3455	#define SQ_FR_PMR_FLAGS_DEBUG_TRACE 0x40UL
3456	u8 access_cntl;
3457	#define SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE 0x1UL
3458	#define SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ 0x2UL
3459	#define SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE 0x4UL
3460	#define SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL
3461	#define SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND 0x10UL
3462	u8 zero_based_page_size_log;
3463	#define SQ_FR_PMR_PAGE_SIZE_LOG_MASK 0x1fUL
3464	#define SQ_FR_PMR_PAGE_SIZE_LOG_SFT 0
3465	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4K 0x0UL
3466	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8K 0x1UL
3467	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16K 0x2UL
3468	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32K 0x3UL
3469	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64K 0x4UL
3470	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128K 0x5UL
3471	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256K 0x6UL
3472	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512K 0x7UL
3473	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1M 0x8UL
3474	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2M 0x9UL
3475	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4M 0xaUL
3476	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8M 0xbUL
3477	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16M 0xcUL
3478	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32M 0xdUL
3479	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64M 0xeUL
3480	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128M 0xfUL
3481	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256M 0x10UL
3482	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512M 0x11UL
3483	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1G 0x12UL
3484	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2G 0x13UL
3485	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4G 0x14UL
3486	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8G 0x15UL
3487	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16G 0x16UL
3488	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32G 0x17UL
3489	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64G 0x18UL
3490	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128G 0x19UL
3491	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL
3492	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL
3493	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL
3494	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL
3495	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL
3496	#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL
3497	#define SQ_FR_PMR_PAGE_SIZE_LOG_LAST SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8T
3498	#define SQ_FR_PMR_ZERO_BASED 0x20UL
3499	__le32 l_key;
3500	u8 length[5];
3501	u8 reserved8_1;
3502	u8 reserved8_2;
3503	u8 numlevels_pbl_page_size_log;
3504	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_MASK 0x1fUL
3505	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_SFT 0
3506	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4K 0x0UL
3507	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8K 0x1UL
3508	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16K 0x2UL
3509	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32K 0x3UL
3510	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64K 0x4UL
3511	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128K 0x5UL
3512	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256K 0x6UL
3513	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512K 0x7UL
3514	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1M 0x8UL
3515	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2M 0x9UL
3516	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4M 0xaUL
3517	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8M 0xbUL
3518	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16M 0xcUL
3519	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32M 0xdUL
3520	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64M 0xeUL
3521	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128M 0xfUL
3522	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256M 0x10UL
3523	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512M 0x11UL
3524	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1G 0x12UL
3525	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2G 0x13UL
3526	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4G 0x14UL
3527	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8G 0x15UL
3528	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16G 0x16UL
3529	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32G 0x17UL
3530	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64G 0x18UL
3531	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128G 0x19UL
3532	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL
3533	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL
3534	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL
3535	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL
3536	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL
3537	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL
3538	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8T
3539	#define SQ_FR_PMR_NUMLEVELS_MASK 0xc0UL
3540	#define SQ_FR_PMR_NUMLEVELS_SFT 6
3541	#define SQ_FR_PMR_NUMLEVELS_PHYSICAL (0x0UL << 6)
3542	#define SQ_FR_PMR_NUMLEVELS_LAYER1 (0x1UL << 6)
3543	#define SQ_FR_PMR_NUMLEVELS_LAYER2 (0x2UL << 6)
3544	#define SQ_FR_PMR_NUMLEVELS_LAST SQ_FR_PMR_NUMLEVELS_LAYER2
3545	__le64 pblptr;
3546	__le64 va;
3547	__le32 data[24];
3548	};
3549
3550	/* sq_fr_pmr_hdr (size:256b/32B) */
3551	struct sq_fr_pmr_hdr {
3552	u8 wqe_type;
3553	#define SQ_FR_PMR_HDR_WQE_TYPE_FR_PMR 0xdUL
3554	#define SQ_FR_PMR_HDR_WQE_TYPE_LAST SQ_FR_PMR_HDR_WQE_TYPE_FR_PMR
3555	u8 flags;
3556	#define SQ_FR_PMR_HDR_FLAGS_SIGNAL_COMP 0x1UL
3557	#define SQ_FR_PMR_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3558	#define SQ_FR_PMR_HDR_FLAGS_UC_FENCE 0x4UL
3559	#define SQ_FR_PMR_HDR_FLAGS_SE 0x8UL
3560	#define SQ_FR_PMR_HDR_FLAGS_INLINE 0x10UL
3561	#define SQ_FR_PMR_HDR_FLAGS_WQE_TS_EN 0x20UL
3562	#define SQ_FR_PMR_HDR_FLAGS_DEBUG_TRACE 0x40UL
3563	u8 access_cntl;
3564	#define SQ_FR_PMR_HDR_ACCESS_CNTL_LOCAL_WRITE 0x1UL
3565	#define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_READ 0x2UL
3566	#define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_WRITE 0x4UL
3567	#define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL
3568	#define SQ_FR_PMR_HDR_ACCESS_CNTL_WINDOW_BIND 0x10UL
3569	u8 zero_based_page_size_log;
3570	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_MASK 0x1fUL
3571	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_SFT 0
3572	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4K 0x0UL
3573	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8K 0x1UL
3574	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16K 0x2UL
3575	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32K 0x3UL
3576	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64K 0x4UL
3577	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128K 0x5UL
3578	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256K 0x6UL
3579	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512K 0x7UL
3580	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1M 0x8UL
3581	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2M 0x9UL
3582	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4M 0xaUL
3583	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8M 0xbUL
3584	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16M 0xcUL
3585	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32M 0xdUL
3586	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64M 0xeUL
3587	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128M 0xfUL
3588	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256M 0x10UL
3589	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512M 0x11UL
3590	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1G 0x12UL
3591	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2G 0x13UL
3592	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4G 0x14UL
3593	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8G 0x15UL
3594	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16G 0x16UL
3595	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32G 0x17UL
3596	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64G 0x18UL
3597	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128G 0x19UL
3598	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL
3599	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL
3600	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL
3601	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL
3602	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL
3603	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL
3604	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8T
3605	#define SQ_FR_PMR_HDR_ZERO_BASED 0x20UL
3606	__le32 l_key;
3607	u8 length[5];
3608	u8 reserved8_1;
3609	u8 reserved8_2;
3610	u8 numlevels_pbl_page_size_log;
3611	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_MASK 0x1fUL
3612	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_SFT 0
3613	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4K 0x0UL
3614	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8K 0x1UL
3615	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16K 0x2UL
3616	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32K 0x3UL
3617	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64K 0x4UL
3618	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128K 0x5UL
3619	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256K 0x6UL
3620	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512K 0x7UL
3621	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1M 0x8UL
3622	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2M 0x9UL
3623	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4M 0xaUL
3624	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8M 0xbUL
3625	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16M 0xcUL
3626	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32M 0xdUL
3627	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64M 0xeUL
3628	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128M 0xfUL
3629	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256M 0x10UL
3630	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512M 0x11UL
3631	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1G 0x12UL
3632	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2G 0x13UL
3633	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4G 0x14UL
3634	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8G 0x15UL
3635	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16G 0x16UL
3636	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32G 0x17UL
3637	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64G 0x18UL
3638	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128G 0x19UL
3639	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL
3640	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL
3641	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL
3642	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL
3643	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL
3644	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL
3645	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T
3646	#define SQ_FR_PMR_HDR_NUMLEVELS_MASK 0xc0UL
3647	#define SQ_FR_PMR_HDR_NUMLEVELS_SFT 6
3648	#define SQ_FR_PMR_HDR_NUMLEVELS_PHYSICAL (0x0UL << 6)
3649	#define SQ_FR_PMR_HDR_NUMLEVELS_LAYER1 (0x1UL << 6)
3650	#define SQ_FR_PMR_HDR_NUMLEVELS_LAYER2 (0x2UL << 6)
3651	#define SQ_FR_PMR_HDR_NUMLEVELS_LAST SQ_FR_PMR_HDR_NUMLEVELS_LAYER2
3652	__le64 pblptr;
3653	__le64 va;
3654	};
3655
3656	/* sq_bind (size:1024b/128B) */
3657	struct sq_bind {
3658	u8 wqe_type;
3659	#define SQ_BIND_WQE_TYPE_BIND 0xeUL
3660	#define SQ_BIND_WQE_TYPE_LAST SQ_BIND_WQE_TYPE_BIND
3661	u8 flags;
3662	#define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3663	#define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3664	#define SQ_BIND_FLAGS_SIGNAL_COMP 0x1UL
3665	#define SQ_BIND_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3666	#define SQ_BIND_FLAGS_UC_FENCE 0x4UL
3667	#define SQ_BIND_FLAGS_SE 0x8UL
3668	#define SQ_BIND_FLAGS_INLINE 0x10UL
3669	#define SQ_BIND_FLAGS_WQE_TS_EN 0x20UL
3670	#define SQ_BIND_FLAGS_DEBUG_TRACE 0x40UL
3671	u8 access_cntl;
3672	#define \
3673	SQ_BIND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK\
3674	0xffUL
3675	#define \
3676	SQ_BIND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_SFT 0
3677	#define SQ_BIND_ACCESS_CNTL_LOCAL_WRITE 0x1UL
3678	#define SQ_BIND_ACCESS_CNTL_REMOTE_READ 0x2UL
3679	#define SQ_BIND_ACCESS_CNTL_REMOTE_WRITE 0x4UL
3680	#define SQ_BIND_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL
3681	#define SQ_BIND_ACCESS_CNTL_WINDOW_BIND 0x10UL
3682	u8 reserved8_1;
3683	u8 mw_type_zero_based;
3684	#define SQ_BIND_ZERO_BASED 0x1UL
3685	#define SQ_BIND_MW_TYPE 0x2UL
3686	#define SQ_BIND_MW_TYPE_TYPE1 (0x0UL << 1)
3687	#define SQ_BIND_MW_TYPE_TYPE2 (0x1UL << 1)
3688	#define SQ_BIND_MW_TYPE_LAST SQ_BIND_MW_TYPE_TYPE2
3689	u8 reserved8_2;
3690	__le16 reserved16;
3691	__le32 parent_l_key;
3692	__le32 l_key;
3693	__le64 va;
3694	u8 length[5];
3695	u8 reserved24[3];
3696	__le32 data[24];
3697	};
3698
3699	/* sq_bind_hdr (size:256b/32B) */
3700	struct sq_bind_hdr {
3701	u8 wqe_type;
3702	#define SQ_BIND_HDR_WQE_TYPE_BIND 0xeUL
3703	#define SQ_BIND_HDR_WQE_TYPE_LAST SQ_BIND_HDR_WQE_TYPE_BIND
3704	u8 flags;
3705	#define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3706	#define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3707	#define SQ_BIND_HDR_FLAGS_SIGNAL_COMP 0x1UL
3708	#define SQ_BIND_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3709	#define SQ_BIND_HDR_FLAGS_UC_FENCE 0x4UL
3710	#define SQ_BIND_HDR_FLAGS_SE 0x8UL
3711	#define SQ_BIND_HDR_FLAGS_INLINE 0x10UL
3712	#define SQ_BIND_HDR_FLAGS_WQE_TS_EN 0x20UL
3713	#define SQ_BIND_HDR_FLAGS_DEBUG_TRACE 0x40UL
3714	u8 access_cntl;
3715	#define \
3716	SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK\
3717	0xffUL
3718	#define \
3719	SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_SFT \
3720	0
3721	#define SQ_BIND_HDR_ACCESS_CNTL_LOCAL_WRITE 0x1UL
3722	#define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_READ 0x2UL
3723	#define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_WRITE 0x4UL
3724	#define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL
3725	#define SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND 0x10UL
3726	u8 reserved8_1;
3727	u8 mw_type_zero_based;
3728	#define SQ_BIND_HDR_ZERO_BASED 0x1UL
3729	#define SQ_BIND_HDR_MW_TYPE 0x2UL
3730	#define SQ_BIND_HDR_MW_TYPE_TYPE1 (0x0UL << 1)
3731	#define SQ_BIND_HDR_MW_TYPE_TYPE2 (0x1UL << 1)
3732	#define SQ_BIND_HDR_MW_TYPE_LAST SQ_BIND_HDR_MW_TYPE_TYPE2
3733	u8 reserved8_2;
3734	__le16 reserved16;
3735	__le32 parent_l_key;
3736	__le32 l_key;
3737	__le64 va;
3738	u8 length[5];
3739	u8 reserved24[3];
3740	};
3741
3742	/* rq_wqe (size:1024b/128B) */
3743	struct rq_wqe {
3744	u8 wqe_type;
3745	#define RQ_WQE_WQE_TYPE_RCV 0x80UL
3746	#define RQ_WQE_WQE_TYPE_LAST RQ_WQE_WQE_TYPE_RCV
3747	u8 flags;
3748	u8 wqe_size;
3749	u8 reserved8;
3750	__le32 reserved32;
3751	__le32 wr_id[2];
3752	#define RQ_WQE_WR_ID_MASK 0xfffffUL
3753	#define RQ_WQE_WR_ID_SFT 0
3754	u8 reserved128[16];
3755	__le32 data[24];
3756	};
3757
3758	/* rq_wqe_hdr (size:256b/32B) */
3759	struct rq_wqe_hdr {
3760	u8 wqe_type;
3761	#define RQ_WQE_HDR_WQE_TYPE_RCV 0x80UL
3762	#define RQ_WQE_HDR_WQE_TYPE_LAST RQ_WQE_HDR_WQE_TYPE_RCV
3763	u8 flags;
3764	u8 wqe_size;
3765	u8 reserved8;
3766	__le32 reserved32;
3767	__le32 wr_id[2];
3768	#define RQ_WQE_HDR_WR_ID_MASK 0xfffffUL
3769	#define RQ_WQE_HDR_WR_ID_SFT 0
3770	u8 reserved128[16];
3771	};
3772
3773	/* cq_base (size:256b/32B) */
3774	struct cq_base {
3775	__le64 reserved64_1;
3776	__le64 reserved64_2;
3777	__le64 reserved64_3;
3778	u8 cqe_type_toggle;
3779	#define CQ_BASE_TOGGLE 0x1UL
3780	#define CQ_BASE_CQE_TYPE_MASK 0x1eUL
3781	#define CQ_BASE_CQE_TYPE_SFT 1
3782	#define CQ_BASE_CQE_TYPE_REQ (0x0UL << 1)
3783	#define CQ_BASE_CQE_TYPE_RES_RC (0x1UL << 1)
3784	#define CQ_BASE_CQE_TYPE_RES_UD (0x2UL << 1)
3785	#define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1)
3786	#define CQ_BASE_CQE_TYPE_RES_UD_CFA (0x4UL << 1)
3787	#define CQ_BASE_CQE_TYPE_REQ_V3 (0x8UL << 1)
3788	#define CQ_BASE_CQE_TYPE_RES_RC_V3 (0x9UL << 1)
3789	#define CQ_BASE_CQE_TYPE_RES_UD_V3 (0xaUL << 1)
3790	#define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1_V3 (0xbUL << 1)
3791	#define CQ_BASE_CQE_TYPE_RES_UD_CFA_V3 (0xcUL << 1)
3792	#define CQ_BASE_CQE_TYPE_NO_OP (0xdUL << 1)
3793	#define CQ_BASE_CQE_TYPE_TERMINAL (0xeUL << 1)
3794	#define CQ_BASE_CQE_TYPE_CUT_OFF (0xfUL << 1)
3795	#define CQ_BASE_CQE_TYPE_LAST CQ_BASE_CQE_TYPE_CUT_OFF
3796	u8 status;
3797	#define CQ_BASE_STATUS_OK 0x0UL
3798	#define CQ_BASE_STATUS_BAD_RESPONSE_ERR 0x1UL
3799	#define CQ_BASE_STATUS_LOCAL_LENGTH_ERR 0x2UL
3800	#define CQ_BASE_STATUS_HW_LOCAL_LENGTH_ERR 0x3UL
3801	#define CQ_BASE_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
3802	#define CQ_BASE_STATUS_LOCAL_PROTECTION_ERR 0x5UL
3803	#define CQ_BASE_STATUS_LOCAL_ACCESS_ERROR 0x6UL
3804	#define CQ_BASE_STATUS_MEMORY_MGT_OPERATION_ERR 0x7UL
3805	#define CQ_BASE_STATUS_REMOTE_INVALID_REQUEST_ERR 0x8UL
3806	#define CQ_BASE_STATUS_REMOTE_ACCESS_ERR 0x9UL
3807	#define CQ_BASE_STATUS_REMOTE_OPERATION_ERR 0xaUL
3808	#define CQ_BASE_STATUS_RNR_NAK_RETRY_CNT_ERR 0xbUL
3809	#define CQ_BASE_STATUS_TRANSPORT_RETRY_CNT_ERR 0xcUL
3810	#define CQ_BASE_STATUS_WORK_REQUEST_FLUSHED_ERR 0xdUL
3811	#define CQ_BASE_STATUS_HW_FLUSH_ERR 0xeUL
3812	#define CQ_BASE_STATUS_OVERFLOW_ERR 0xfUL
3813	#define CQ_BASE_STATUS_LAST CQ_BASE_STATUS_OVERFLOW_ERR
3814	__le16 reserved16;
3815	__le32 opaque;
3816	};
3817
3818	/* cq_req (size:256b/32B) */
3819	struct cq_req {
3820	__le64 qp_handle;
3821	__le16 sq_cons_idx;
3822	__le16 reserved16_1;
3823	__le32 reserved32_2;
3824	__le64 reserved64;
3825	u8 cqe_type_toggle;
3826	#define CQ_REQ_TOGGLE 0x1UL
3827	#define CQ_REQ_CQE_TYPE_MASK 0x1eUL
3828	#define CQ_REQ_CQE_TYPE_SFT 1
3829	#define CQ_REQ_CQE_TYPE_REQ (0x0UL << 1)
3830	#define CQ_REQ_CQE_TYPE_LAST CQ_REQ_CQE_TYPE_REQ
3831	#define CQ_REQ_PUSH 0x20UL
3832	u8 status;
3833	#define CQ_REQ_STATUS_OK 0x0UL
3834	#define CQ_REQ_STATUS_BAD_RESPONSE_ERR 0x1UL
3835	#define CQ_REQ_STATUS_LOCAL_LENGTH_ERR 0x2UL
3836	#define CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR 0x3UL
3837	#define CQ_REQ_STATUS_LOCAL_PROTECTION_ERR 0x4UL
3838	#define CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
3839	#define CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR 0x6UL
3840	#define CQ_REQ_STATUS_REMOTE_ACCESS_ERR 0x7UL
3841	#define CQ_REQ_STATUS_REMOTE_OPERATION_ERR 0x8UL
3842	#define CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR 0x9UL
3843	#define CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR 0xaUL
3844	#define CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR 0xbUL
3845	#define CQ_REQ_STATUS_LAST CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR
3846	__le16 reserved16_2;
3847	__le32 reserved32_1;
3848	};
3849
3850	/* cq_res_rc (size:256b/32B) */
3851	struct cq_res_rc {
3852	__le32 length;
3853	__le32 imm_data_or_inv_r_key;
3854	__le64 qp_handle;
3855	__le64 mr_handle;
3856	u8 cqe_type_toggle;
3857	#define CQ_RES_RC_TOGGLE 0x1UL
3858	#define CQ_RES_RC_CQE_TYPE_MASK 0x1eUL
3859	#define CQ_RES_RC_CQE_TYPE_SFT 1
3860	#define CQ_RES_RC_CQE_TYPE_RES_RC (0x1UL << 1)
3861	#define CQ_RES_RC_CQE_TYPE_LAST CQ_RES_RC_CQE_TYPE_RES_RC
3862	u8 status;
3863	#define CQ_RES_RC_STATUS_OK 0x0UL
3864	#define CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR 0x1UL
3865	#define CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR 0x2UL
3866	#define CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR 0x3UL
3867	#define CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
3868	#define CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
3869	#define CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR 0x6UL
3870	#define CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
3871	#define CQ_RES_RC_STATUS_HW_FLUSH_ERR 0x8UL
3872	#define CQ_RES_RC_STATUS_LAST CQ_RES_RC_STATUS_HW_FLUSH_ERR
3873	__le16 flags;
3874	#define CQ_RES_RC_FLAGS_SRQ 0x1UL
3875	#define CQ_RES_RC_FLAGS_SRQ_RQ 0x0UL
3876	#define CQ_RES_RC_FLAGS_SRQ_SRQ 0x1UL
3877	#define CQ_RES_RC_FLAGS_SRQ_LAST CQ_RES_RC_FLAGS_SRQ_SRQ
3878	#define CQ_RES_RC_FLAGS_IMM 0x2UL
3879	#define CQ_RES_RC_FLAGS_INV 0x4UL
3880	#define CQ_RES_RC_FLAGS_RDMA 0x8UL
3881	#define CQ_RES_RC_FLAGS_RDMA_SEND (0x0UL << 3)
3882	#define CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE (0x1UL << 3)
3883	#define CQ_RES_RC_FLAGS_RDMA_LAST CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE
3884	__le32 srq_or_rq_wr_id;
3885	#define CQ_RES_RC_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
3886	#define CQ_RES_RC_SRQ_OR_RQ_WR_ID_SFT 0
3887	};
3888
3889	/* cq_res_ud (size:256b/32B) */
3890	struct cq_res_ud {
3891	__le16 length;
3892	#define CQ_RES_UD_LENGTH_MASK 0x3fffUL
3893	#define CQ_RES_UD_LENGTH_SFT 0
3894	__le16 cfa_metadata;
3895	#define CQ_RES_UD_CFA_METADATA_VID_MASK 0xfffUL
3896	#define CQ_RES_UD_CFA_METADATA_VID_SFT 0
3897	#define CQ_RES_UD_CFA_METADATA_DE 0x1000UL
3898	#define CQ_RES_UD_CFA_METADATA_PRI_MASK 0xe000UL
3899	#define CQ_RES_UD_CFA_METADATA_PRI_SFT 13
3900	__le32 imm_data;
3901	__le64 qp_handle;
3902	__le16 src_mac[3];
3903	__le16 src_qp_low;
3904	u8 cqe_type_toggle;
3905	#define CQ_RES_UD_TOGGLE 0x1UL
3906	#define CQ_RES_UD_CQE_TYPE_MASK 0x1eUL
3907	#define CQ_RES_UD_CQE_TYPE_SFT 1
3908	#define CQ_RES_UD_CQE_TYPE_RES_UD (0x2UL << 1)
3909	#define CQ_RES_UD_CQE_TYPE_LAST CQ_RES_UD_CQE_TYPE_RES_UD
3910	u8 status;
3911	#define CQ_RES_UD_STATUS_OK 0x0UL
3912	#define CQ_RES_UD_STATUS_LOCAL_ACCESS_ERROR 0x1UL
3913	#define CQ_RES_UD_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL
3914	#define CQ_RES_UD_STATUS_LOCAL_PROTECTION_ERR 0x3UL
3915	#define CQ_RES_UD_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
3916	#define CQ_RES_UD_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
3917	#define CQ_RES_UD_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
3918	#define CQ_RES_UD_STATUS_HW_FLUSH_ERR 0x8UL
3919	#define CQ_RES_UD_STATUS_LAST CQ_RES_UD_STATUS_HW_FLUSH_ERR
3920	__le16 flags;
3921	#define CQ_RES_UD_FLAGS_SRQ 0x1UL
3922	#define CQ_RES_UD_FLAGS_SRQ_RQ 0x0UL
3923	#define CQ_RES_UD_FLAGS_SRQ_SRQ 0x1UL
3924	#define CQ_RES_UD_FLAGS_SRQ_LAST CQ_RES_UD_FLAGS_SRQ_SRQ
3925	#define CQ_RES_UD_FLAGS_IMM 0x2UL
3926	#define CQ_RES_UD_FLAGS_UNUSED_MASK 0xcUL
3927	#define CQ_RES_UD_FLAGS_UNUSED_SFT 2
3928	#define CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK 0x30UL
3929	#define CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT 4
3930	#define CQ_RES_UD_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4)
3931	#define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4)
3932	#define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4)
3933	#define CQ_RES_UD_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6
3934	#define CQ_RES_UD_FLAGS_META_FORMAT_MASK 0x3c0UL
3935	#define CQ_RES_UD_FLAGS_META_FORMAT_SFT 6
3936	#define CQ_RES_UD_FLAGS_META_FORMAT_NONE (0x0UL << 6)
3937	#define CQ_RES_UD_FLAGS_META_FORMAT_VLAN (0x1UL << 6)
3938	#define CQ_RES_UD_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6)
3939	#define CQ_RES_UD_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6)
3940	#define CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6)
3941	#define CQ_RES_UD_FLAGS_META_FORMAT_LAST CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET
3942	#define CQ_RES_UD_FLAGS_EXT_META_FORMAT_MASK 0xc00UL
3943	#define CQ_RES_UD_FLAGS_EXT_META_FORMAT_SFT 10
3944	__le32 src_qp_high_srq_or_rq_wr_id;
3945	#define CQ_RES_UD_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
3946	#define CQ_RES_UD_SRQ_OR_RQ_WR_ID_SFT 0
3947	#define CQ_RES_UD_SRC_QP_HIGH_MASK 0xff000000UL
3948	#define CQ_RES_UD_SRC_QP_HIGH_SFT 24
3949	};
3950
3951	/* cq_res_ud_v2 (size:256b/32B) */
3952	struct cq_res_ud_v2 {
3953	__le16 length;
3954	#define CQ_RES_UD_V2_LENGTH_MASK 0x3fffUL
3955	#define CQ_RES_UD_V2_LENGTH_SFT 0
3956	__le16 cfa_metadata0;
3957	#define CQ_RES_UD_V2_CFA_METADATA0_VID_MASK 0xfffUL
3958	#define CQ_RES_UD_V2_CFA_METADATA0_VID_SFT 0
3959	#define CQ_RES_UD_V2_CFA_METADATA0_DE 0x1000UL
3960	#define CQ_RES_UD_V2_CFA_METADATA0_PRI_MASK 0xe000UL
3961	#define CQ_RES_UD_V2_CFA_METADATA0_PRI_SFT 13
3962	__le32 imm_data;
3963	__le64 qp_handle;
3964	__le16 src_mac[3];
3965	__le16 src_qp_low;
3966	u8 cqe_type_toggle;
3967	#define CQ_RES_UD_V2_TOGGLE 0x1UL
3968	#define CQ_RES_UD_V2_CQE_TYPE_MASK 0x1eUL
3969	#define CQ_RES_UD_V2_CQE_TYPE_SFT 1
3970	#define CQ_RES_UD_V2_CQE_TYPE_RES_UD (0x2UL << 1)
3971	#define CQ_RES_UD_V2_CQE_TYPE_LAST CQ_RES_UD_V2_CQE_TYPE_RES_UD
3972	u8 status;
3973	#define CQ_RES_UD_V2_STATUS_OK 0x0UL
3974	#define CQ_RES_UD_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL
3975	#define CQ_RES_UD_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL
3976	#define CQ_RES_UD_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL
3977	#define CQ_RES_UD_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
3978	#define CQ_RES_UD_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
3979	#define CQ_RES_UD_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
3980	#define CQ_RES_UD_V2_STATUS_HW_FLUSH_ERR 0x8UL
3981	#define CQ_RES_UD_V2_STATUS_LAST CQ_RES_UD_V2_STATUS_HW_FLUSH_ERR
3982	__le16 flags;
3983	#define CQ_RES_UD_V2_FLAGS_SRQ 0x1UL
3984	#define CQ_RES_UD_V2_FLAGS_SRQ_RQ 0x0UL
3985	#define CQ_RES_UD_V2_FLAGS_SRQ_SRQ 0x1UL
3986	#define CQ_RES_UD_V2_FLAGS_SRQ_LAST CQ_RES_UD_V2_FLAGS_SRQ_SRQ
3987	#define CQ_RES_UD_V2_FLAGS_IMM 0x2UL
3988	#define CQ_RES_UD_V2_FLAGS_UNUSED_MASK 0xcUL
3989	#define CQ_RES_UD_V2_FLAGS_UNUSED_SFT 2
3990	#define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_MASK 0x30UL
3991	#define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_SFT 4
3992	#define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4)
3993	#define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4)
3994	#define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4)
3995	#define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV6
3996	#define CQ_RES_UD_V2_FLAGS_META_FORMAT_MASK 0x3c0UL
3997	#define CQ_RES_UD_V2_FLAGS_META_FORMAT_SFT 6
3998	#define CQ_RES_UD_V2_FLAGS_META_FORMAT_NONE (0x0UL << 6)
3999	#define CQ_RES_UD_V2_FLAGS_META_FORMAT_ACT_REC_PTR (0x1UL << 6)
4000	#define CQ_RES_UD_V2_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6)
4001	#define CQ_RES_UD_V2_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6)
4002	#define CQ_RES_UD_V2_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6)
4003	#define CQ_RES_UD_V2_FLAGS_META_FORMAT_LAST CQ_RES_UD_V2_FLAGS_META_FORMAT_HDR_OFFSET
4004	__le32 src_qp_high_srq_or_rq_wr_id;
4005	#define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
4006	#define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_SFT 0
4007	#define CQ_RES_UD_V2_CFA_METADATA1_MASK 0xf00000UL
4008	#define CQ_RES_UD_V2_CFA_METADATA1_SFT 20
4009	#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL
4010	#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_SFT 20
4011	#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20)
4012	#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20)
4013	#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20)
4014	#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20)
4015	#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20)
4016	#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20)
4017	#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_LAST CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPIDCFG
4018	#define CQ_RES_UD_V2_CFA_METADATA1_VALID 0x800000UL
4019	#define CQ_RES_UD_V2_SRC_QP_HIGH_MASK 0xff000000UL
4020	#define CQ_RES_UD_V2_SRC_QP_HIGH_SFT 24
4021	};
4022
4023	/* cq_res_ud_cfa (size:256b/32B) */
4024	struct cq_res_ud_cfa {
4025	__le16 length;
4026	#define CQ_RES_UD_CFA_LENGTH_MASK 0x3fffUL
4027	#define CQ_RES_UD_CFA_LENGTH_SFT 0
4028	__le16 cfa_code;
4029	__le32 imm_data;
4030	__le32 qid;
4031	#define CQ_RES_UD_CFA_QID_MASK 0xfffffUL
4032	#define CQ_RES_UD_CFA_QID_SFT 0
4033	__le32 cfa_metadata;
4034	#define CQ_RES_UD_CFA_CFA_METADATA_VID_MASK 0xfffUL
4035	#define CQ_RES_UD_CFA_CFA_METADATA_VID_SFT 0
4036	#define CQ_RES_UD_CFA_CFA_METADATA_DE 0x1000UL
4037	#define CQ_RES_UD_CFA_CFA_METADATA_PRI_MASK 0xe000UL
4038	#define CQ_RES_UD_CFA_CFA_METADATA_PRI_SFT 13
4039	#define CQ_RES_UD_CFA_CFA_METADATA_TPID_MASK 0xffff0000UL
4040	#define CQ_RES_UD_CFA_CFA_METADATA_TPID_SFT 16
4041	__le16 src_mac[3];
4042	__le16 src_qp_low;
4043	u8 cqe_type_toggle;
4044	#define CQ_RES_UD_CFA_TOGGLE 0x1UL
4045	#define CQ_RES_UD_CFA_CQE_TYPE_MASK 0x1eUL
4046	#define CQ_RES_UD_CFA_CQE_TYPE_SFT 1
4047	#define CQ_RES_UD_CFA_CQE_TYPE_RES_UD_CFA (0x4UL << 1)
4048	#define CQ_RES_UD_CFA_CQE_TYPE_LAST CQ_RES_UD_CFA_CQE_TYPE_RES_UD_CFA
4049	u8 status;
4050	#define CQ_RES_UD_CFA_STATUS_OK 0x0UL
4051	#define CQ_RES_UD_CFA_STATUS_LOCAL_ACCESS_ERROR 0x1UL
4052	#define CQ_RES_UD_CFA_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL
4053	#define CQ_RES_UD_CFA_STATUS_LOCAL_PROTECTION_ERR 0x3UL
4054	#define CQ_RES_UD_CFA_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
4055	#define CQ_RES_UD_CFA_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
4056	#define CQ_RES_UD_CFA_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
4057	#define CQ_RES_UD_CFA_STATUS_HW_FLUSH_ERR 0x8UL
4058	#define CQ_RES_UD_CFA_STATUS_LAST CQ_RES_UD_CFA_STATUS_HW_FLUSH_ERR
4059	__le16 flags;
4060	#define CQ_RES_UD_CFA_FLAGS_SRQ 0x1UL
4061	#define CQ_RES_UD_CFA_FLAGS_SRQ_RQ 0x0UL
4062	#define CQ_RES_UD_CFA_FLAGS_SRQ_SRQ 0x1UL
4063	#define CQ_RES_UD_CFA_FLAGS_SRQ_LAST CQ_RES_UD_CFA_FLAGS_SRQ_SRQ
4064	#define CQ_RES_UD_CFA_FLAGS_IMM 0x2UL
4065	#define CQ_RES_UD_CFA_FLAGS_UNUSED_MASK 0xcUL
4066	#define CQ_RES_UD_CFA_FLAGS_UNUSED_SFT 2
4067	#define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_MASK 0x30UL
4068	#define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_SFT 4
4069	#define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4)
4070	#define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4)
4071	#define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4)
4072	#define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV6
4073	#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_MASK 0x3c0UL
4074	#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_SFT 6
4075	#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_NONE (0x0UL << 6)
4076	#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_VLAN (0x1UL << 6)
4077	#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6)
4078	#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6)
4079	#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6)
4080	#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_LAST CQ_RES_UD_CFA_FLAGS_META_FORMAT_HDR_OFFSET
4081	#define CQ_RES_UD_CFA_FLAGS_EXT_META_FORMAT_MASK 0xc00UL
4082	#define CQ_RES_UD_CFA_FLAGS_EXT_META_FORMAT_SFT 10
4083	__le32 src_qp_high_srq_or_rq_wr_id;
4084	#define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
4085	#define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_SFT 0
4086	#define CQ_RES_UD_CFA_SRC_QP_HIGH_MASK 0xff000000UL
4087	#define CQ_RES_UD_CFA_SRC_QP_HIGH_SFT 24
4088	};
4089
4090	/* cq_res_ud_cfa_v2 (size:256b/32B) */
4091	struct cq_res_ud_cfa_v2 {
4092	__le16 length;
4093	#define CQ_RES_UD_CFA_V2_LENGTH_MASK 0x3fffUL
4094	#define CQ_RES_UD_CFA_V2_LENGTH_SFT 0
4095	__le16 cfa_metadata0;
4096	#define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_MASK 0xfffUL
4097	#define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_SFT 0
4098	#define CQ_RES_UD_CFA_V2_CFA_METADATA0_DE 0x1000UL
4099	#define CQ_RES_UD_CFA_V2_CFA_METADATA0_PRI_MASK 0xe000UL
4100	#define CQ_RES_UD_CFA_V2_CFA_METADATA0_PRI_SFT 13
4101	__le32 imm_data;
4102	__le32 qid;
4103	#define CQ_RES_UD_CFA_V2_QID_MASK 0xfffffUL
4104	#define CQ_RES_UD_CFA_V2_QID_SFT 0
4105	__le32 cfa_metadata2;
4106	__le16 src_mac[3];
4107	__le16 src_qp_low;
4108	u8 cqe_type_toggle;
4109	#define CQ_RES_UD_CFA_V2_TOGGLE 0x1UL
4110	#define CQ_RES_UD_CFA_V2_CQE_TYPE_MASK 0x1eUL
4111	#define CQ_RES_UD_CFA_V2_CQE_TYPE_SFT 1
4112	#define CQ_RES_UD_CFA_V2_CQE_TYPE_RES_UD_CFA (0x4UL << 1)
4113	#define CQ_RES_UD_CFA_V2_CQE_TYPE_LAST CQ_RES_UD_CFA_V2_CQE_TYPE_RES_UD_CFA
4114	u8 status;
4115	#define CQ_RES_UD_CFA_V2_STATUS_OK 0x0UL
4116	#define CQ_RES_UD_CFA_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL
4117	#define CQ_RES_UD_CFA_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL
4118	#define CQ_RES_UD_CFA_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL
4119	#define CQ_RES_UD_CFA_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
4120	#define CQ_RES_UD_CFA_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
4121	#define CQ_RES_UD_CFA_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
4122	#define CQ_RES_UD_CFA_V2_STATUS_HW_FLUSH_ERR 0x8UL
4123	#define CQ_RES_UD_CFA_V2_STATUS_LAST CQ_RES_UD_CFA_V2_STATUS_HW_FLUSH_ERR
4124	__le16 flags;
4125	#define CQ_RES_UD_CFA_V2_FLAGS_SRQ 0x1UL
4126	#define CQ_RES_UD_CFA_V2_FLAGS_SRQ_RQ 0x0UL
4127	#define CQ_RES_UD_CFA_V2_FLAGS_SRQ_SRQ 0x1UL
4128	#define CQ_RES_UD_CFA_V2_FLAGS_SRQ_LAST CQ_RES_UD_CFA_V2_FLAGS_SRQ_SRQ
4129	#define CQ_RES_UD_CFA_V2_FLAGS_IMM 0x2UL
4130	#define CQ_RES_UD_CFA_V2_FLAGS_UNUSED_MASK 0xcUL
4131	#define CQ_RES_UD_CFA_V2_FLAGS_UNUSED_SFT 2
4132	#define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_MASK 0x30UL
4133	#define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_SFT 4
4134	#define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4)
4135	#define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4)
4136	#define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4)
4137	#define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV6
4138	#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_MASK 0x3c0UL
4139	#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_SFT 6
4140	#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_NONE (0x0UL << 6)
4141	#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_ACT_REC_PTR (0x1UL << 6)
4142	#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6)
4143	#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6)
4144	#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6)
4145	#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_LAST \
4146	CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_HDR_OFFSET
4147	__le32 src_qp_high_srq_or_rq_wr_id;
4148	#define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
4149	#define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_SFT 0
4150	#define CQ_RES_UD_CFA_V2_CFA_METADATA1_MASK 0xf00000UL
4151	#define CQ_RES_UD_CFA_V2_CFA_METADATA1_SFT 20
4152	#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL
4153	#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_SFT 20
4154	#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20)
4155	#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20)
4156	#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20)
4157	#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20)
4158	#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20)
4159	#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20)
4160	#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_LAST \
4161	CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPIDCFG
4162	#define CQ_RES_UD_CFA_V2_CFA_METADATA1_VALID 0x800000UL
4163	#define CQ_RES_UD_CFA_V2_SRC_QP_HIGH_MASK 0xff000000UL
4164	#define CQ_RES_UD_CFA_V2_SRC_QP_HIGH_SFT 24
4165	};
4166
4167	/* cq_res_raweth_qp1 (size:256b/32B) */
4168	struct cq_res_raweth_qp1 {
4169	__le16 length;
4170	#define CQ_RES_RAWETH_QP1_LENGTH_MASK 0x3fffUL
4171	#define CQ_RES_RAWETH_QP1_LENGTH_SFT 0
4172	__le16 raweth_qp1_flags;
4173	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_MASK 0x3ffUL
4174	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_SFT 0
4175	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ERROR 0x1UL
4176	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_MASK 0x3c0UL
4177	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_SFT 6
4178	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (0x0UL << 6)
4179	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_IP (0x1UL << 6)
4180	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_TCP (0x2UL << 6)
4181	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_UDP (0x3UL << 6)
4182	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_FCOE (0x4UL << 6)
4183	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE (0x5UL << 6)
4184	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ICMP (0x7UL << 6)
4185	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (0x8UL << 6)
4186	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (0x9UL << 6)
4187	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_LAST \
4188	CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP
4189	__le16 raweth_qp1_errors;
4190	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_IP_CS_ERROR 0x10UL
4191	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_L4_CS_ERROR 0x20UL
4192	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_IP_CS_ERROR 0x40UL
4193	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_L4_CS_ERROR 0x80UL
4194	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_CRC_ERROR 0x100UL
4195	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK 0xe00UL
4196	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9
4197	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (0x0UL << 9)
4198	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1UL << 9)
4199	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2UL << 9)
4200	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3UL << 9)
4201	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4UL << 9)
4202	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5UL << 9)
4203	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6UL << 9)
4204	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST \
4205	CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
4206	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_MASK 0xf000UL
4207	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12
4208	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (0x0UL << 12)
4209	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1UL << 12)
4210	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2UL << 12)
4211	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3UL << 12)
4212	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4UL << 12)
4213	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5UL << 12)
4214	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6UL << 12)
4215	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7UL << 12)
4216	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8UL << 12)
4217	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_LAST \
4218	CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
4219	__le16 raweth_qp1_cfa_code;
4220	__le64 qp_handle;
4221	__le32 raweth_qp1_flags2;
4222	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC 0x1UL
4223	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC 0x2UL
4224	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_IP_CS_CALC 0x4UL
4225	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_L4_CS_CALC 0x8UL
4226	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_MASK 0xf0UL
4227	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4
4228	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (0x0UL << 4)
4229	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN (0x1UL << 4)
4230	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (0x2UL << 4)
4231	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (0x3UL << 4)
4232	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (0x4UL << 4)
4233	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_LAST \
4234	CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET
4235	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE 0x100UL
4236	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC 0x200UL
4237	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_MASK 0xc00UL
4238	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_SFT 10
4239	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK 0xffff0000UL
4240	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_SFT 16
4241	__le32 raweth_qp1_metadata;
4242	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_MASK 0xffffUL
4243	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_SFT 0
4244	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK 0xfffUL
4245	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_SFT 0
4246	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_DE 0x1000UL
4247	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK 0xe000UL
4248	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT 13
4249	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK 0xffff0000UL
4250	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT 16
4251	u8 cqe_type_toggle;
4252	#define CQ_RES_RAWETH_QP1_TOGGLE 0x1UL
4253	#define CQ_RES_RAWETH_QP1_CQE_TYPE_MASK 0x1eUL
4254	#define CQ_RES_RAWETH_QP1_CQE_TYPE_SFT 1
4255	#define CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1)
4256	#define CQ_RES_RAWETH_QP1_CQE_TYPE_LAST CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1
4257	u8 status;
4258	#define CQ_RES_RAWETH_QP1_STATUS_OK 0x0UL
4259	#define CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR 0x1UL
4260	#define CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL
4261	#define CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR 0x3UL
4262	#define CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
4263	#define CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
4264	#define CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
4265	#define CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR 0x8UL
4266	#define CQ_RES_RAWETH_QP1_STATUS_LAST CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR
4267	__le16 flags;
4268	#define CQ_RES_RAWETH_QP1_FLAGS_SRQ 0x1UL
4269	#define CQ_RES_RAWETH_QP1_FLAGS_SRQ_RQ 0x0UL
4270	#define CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ 0x1UL
4271	#define CQ_RES_RAWETH_QP1_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ
4272	__le32 raweth_qp1_payload_offset_srq_or_rq_wr_id;
4273	#define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
4274	#define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_SFT 0
4275	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_MASK 0xff000000UL
4276	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24
4277	};
4278
4279	/* cq_res_raweth_qp1_v2 (size:256b/32B) */
4280	struct cq_res_raweth_qp1_v2 {
4281	__le16 length;
4282	#define CQ_RES_RAWETH_QP1_V2_LENGTH_MASK 0x3fffUL
4283	#define CQ_RES_RAWETH_QP1_V2_LENGTH_SFT 0
4284	__le16 raweth_qp1_flags;
4285	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_MASK 0x3ffUL
4286	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_SFT 0
4287	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ERROR 0x1UL
4288	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_MASK 0x3c0UL
4289	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_SFT 6
4290	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (0x0UL << 6)
4291	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_IP (0x1UL << 6)
4292	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_TCP (0x2UL << 6)
4293	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_UDP (0x3UL << 6)
4294	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_FCOE (0x4UL << 6)
4295	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ROCE (0x5UL << 6)
4296	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ICMP (0x7UL << 6)
4297	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (0x8UL << 6)
4298	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (0x9UL << 6)
4299	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_LAST \
4300	CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP
4301	__le16 raweth_qp1_errors;
4302	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_IP_CS_ERROR 0x10UL
4303	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_L4_CS_ERROR 0x20UL
4304	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_IP_CS_ERROR 0x40UL
4305	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_L4_CS_ERROR 0x80UL
4306	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_CRC_ERROR 0x100UL
4307	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK 0xe00UL
4308	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9
4309	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (0x0UL << 9)
4310	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1UL << 9)
4311	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2UL << 9)
4312	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3UL << 9)
4313	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4UL << 9)
4314	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5UL << 9)
4315	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6UL << 9)
4316	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST \
4317	CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
4318	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_MASK 0xf000UL
4319	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12
4320	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (0x0UL << 12)
4321	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1UL << 12)
4322	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2UL << 12)
4323	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3UL << 12)
4324	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4UL << 12)
4325	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5UL << 12)
4326	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6UL << 12)
4327	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
4328	(0x7UL << 12)
4329	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
4330	(0x8UL << 12)
4331	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_LAST \
4332	CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
4333	__le16 cfa_metadata0;
4334	#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_MASK 0xfffUL
4335	#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_SFT 0
4336	#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_DE 0x1000UL
4337	#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_PRI_MASK 0xe000UL
4338	#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_PRI_SFT 13
4339	__le64 qp_handle;
4340	__le32 raweth_qp1_flags2;
4341	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_ALL_OK_MODE 0x8UL
4342	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_MASK 0xf0UL
4343	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4
4344	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (0x0UL << 4)
4345	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_ACT_REC_PTR (0x1UL << 4)
4346	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (0x2UL << 4)
4347	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (0x3UL << 4)
4348	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (0x4UL << 4)
4349	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_LAST \
4350	CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET
4351	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_IP_TYPE 0x100UL
4352	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC 0x200UL
4353	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_OK_MASK 0xfc00UL
4354	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_OK_SFT 10
4355	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK 0xffff0000UL
4356	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_SFT 16
4357	__le32 cfa_metadata2;
4358	u8 cqe_type_toggle;
4359	#define CQ_RES_RAWETH_QP1_V2_TOGGLE 0x1UL
4360	#define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_MASK 0x1eUL
4361	#define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_SFT 1
4362	#define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1)
4363	#define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_LAST CQ_RES_RAWETH_QP1_V2_CQE_TYPE_RES_RAWETH_QP1
4364	u8 status;
4365	#define CQ_RES_RAWETH_QP1_V2_STATUS_OK 0x0UL
4366	#define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL
4367	#define CQ_RES_RAWETH_QP1_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL
4368	#define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL
4369	#define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
4370	#define CQ_RES_RAWETH_QP1_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
4371	#define CQ_RES_RAWETH_QP1_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
4372	#define CQ_RES_RAWETH_QP1_V2_STATUS_HW_FLUSH_ERR 0x8UL
4373	#define CQ_RES_RAWETH_QP1_V2_STATUS_LAST CQ_RES_RAWETH_QP1_V2_STATUS_HW_FLUSH_ERR
4374	__le16 flags;
4375	#define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ 0x1UL
4376	#define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_RQ 0x0UL
4377	#define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_SRQ 0x1UL
4378	#define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_SRQ
4379	__le32 raweth_qp1_payload_offset_srq_or_rq_wr_id;
4380	#define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
4381	#define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_SFT 0
4382	#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_MASK 0xf00000UL
4383	#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_SFT 20
4384	#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL
4385	#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_SFT 20
4386	#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20)
4387	#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20)
4388	#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20)
4389	#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20)
4390	#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20)
4391	#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20)
4392	#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_LAST \
4393	CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPIDCFG
4394	#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_VALID 0x800000UL
4395	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_PAYLOAD_OFFSET_MASK 0xff000000UL
4396	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24
4397	};
4398
4399	/* cq_terminal (size:256b/32B) */
4400	struct cq_terminal {
4401	__le64 qp_handle;
4402	__le16 sq_cons_idx;
4403	__le16 rq_cons_idx;
4404	__le32 reserved32_1;
4405	__le64 reserved64_3;
4406	u8 cqe_type_toggle;
4407	#define CQ_TERMINAL_TOGGLE 0x1UL
4408	#define CQ_TERMINAL_CQE_TYPE_MASK 0x1eUL
4409	#define CQ_TERMINAL_CQE_TYPE_SFT 1
4410	#define CQ_TERMINAL_CQE_TYPE_TERMINAL (0xeUL << 1)
4411	#define CQ_TERMINAL_CQE_TYPE_LAST CQ_TERMINAL_CQE_TYPE_TERMINAL
4412	u8 status;
4413	#define CQ_TERMINAL_STATUS_OK 0x0UL
4414	#define CQ_TERMINAL_STATUS_LAST CQ_TERMINAL_STATUS_OK
4415	__le16 reserved16;
4416	__le32 reserved32_2;
4417	};
4418
4419	/* cq_cutoff (size:256b/32B) */
4420	struct cq_cutoff {
4421	__le64 reserved64_1;
4422	__le64 reserved64_2;
4423	__le64 reserved64_3;
4424	u8 cqe_type_toggle;
4425	#define CQ_CUTOFF_TOGGLE 0x1UL
4426	#define CQ_CUTOFF_CQE_TYPE_MASK 0x1eUL
4427	#define CQ_CUTOFF_CQE_TYPE_SFT 1
4428	#define CQ_CUTOFF_CQE_TYPE_CUT_OFF (0xfUL << 1)
4429	#define CQ_CUTOFF_CQE_TYPE_LAST CQ_CUTOFF_CQE_TYPE_CUT_OFF
4430	#define CQ_CUTOFF_RESIZE_TOGGLE_MASK 0x60UL
4431	#define CQ_CUTOFF_RESIZE_TOGGLE_SFT 5
4432	u8 status;
4433	#define CQ_CUTOFF_STATUS_OK 0x0UL
4434	#define CQ_CUTOFF_STATUS_LAST CQ_CUTOFF_STATUS_OK
4435	__le16 reserved16;
4436	__le32 reserved32;
4437	};
4438
4439	/* nq_base (size:128b/16B) */
4440	struct nq_base {
4441	__le16 info10_type;
4442	#define NQ_BASE_TYPE_MASK 0x3fUL
4443	#define NQ_BASE_TYPE_SFT 0
4444	#define NQ_BASE_TYPE_CQ_NOTIFICATION 0x30UL
4445	#define NQ_BASE_TYPE_SRQ_EVENT 0x32UL
4446	#define NQ_BASE_TYPE_DBQ_EVENT 0x34UL
4447	#define NQ_BASE_TYPE_QP_EVENT 0x38UL
4448	#define NQ_BASE_TYPE_FUNC_EVENT 0x3aUL
4449	#define NQ_BASE_TYPE_LAST NQ_BASE_TYPE_FUNC_EVENT
4450	#define NQ_BASE_INFO10_MASK 0xffc0UL
4451	#define NQ_BASE_INFO10_SFT 6
4452	__le16 info16;
4453	__le32 info32;
4454	__le32 info63_v[2];
4455	#define NQ_BASE_V 0x1UL
4456	#define NQ_BASE_INFO63_MASK 0xfffffffeUL
4457	#define NQ_BASE_INFO63_SFT 1
4458	};
4459
4460	/* nq_cn (size:128b/16B) */
4461	struct nq_cn {
4462	__le16 type;
4463	#define NQ_CN_TYPE_MASK 0x3fUL
4464	#define NQ_CN_TYPE_SFT 0
4465	#define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL
4466	#define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION
4467	#define NQ_CN_TOGGLE_MASK 0xc0UL
4468	#define NQ_CN_TOGGLE_SFT 6
4469	__le16 reserved16;
4470	__le32 cq_handle_low;
4471	__le32 v;
4472	#define NQ_CN_V 0x1UL
4473	__le32 cq_handle_high;
4474	};
4475
4476	/* nq_srq_event (size:128b/16B) */
4477	struct nq_srq_event {
4478	u8 type;
4479	#define NQ_SRQ_EVENT_TYPE_MASK 0x3fUL
4480	#define NQ_SRQ_EVENT_TYPE_SFT 0
4481	#define NQ_SRQ_EVENT_TYPE_SRQ_EVENT 0x32UL
4482	#define NQ_SRQ_EVENT_TYPE_LAST NQ_SRQ_EVENT_TYPE_SRQ_EVENT
4483	#define NQ_SRQ_EVENT_TOGGLE_MASK 0xc0UL
4484	#define NQ_SRQ_EVENT_TOGGLE_SFT 6
4485	u8 event;
4486	#define NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT 0x1UL
4487	#define NQ_SRQ_EVENT_EVENT_LAST NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT
4488	__le16 reserved16;
4489	__le32 srq_handle_low;
4490	__le32 v;
4491	#define NQ_SRQ_EVENT_V 0x1UL
4492	__le32 srq_handle_high;
4493	};
4494
4495	/* nq_dbq_event (size:128b/16B) */
4496	struct nq_dbq_event {
4497	u8 type;
4498	#define NQ_DBQ_EVENT_TYPE_MASK 0x3fUL
4499	#define NQ_DBQ_EVENT_TYPE_SFT 0
4500	#define NQ_DBQ_EVENT_TYPE_DBQ_EVENT 0x34UL
4501	#define NQ_DBQ_EVENT_TYPE_LAST NQ_DBQ_EVENT_TYPE_DBQ_EVENT
4502	u8 event;
4503	#define NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT 0x1UL
4504	#define NQ_DBQ_EVENT_EVENT_LAST NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT
4505	__le16 db_pfid;
4506	#define NQ_DBQ_EVENT_DB_PFID_MASK 0xfUL
4507	#define NQ_DBQ_EVENT_DB_PFID_SFT 0
4508	__le32 db_dpi;
4509	#define NQ_DBQ_EVENT_DB_DPI_MASK 0xfffffUL
4510	#define NQ_DBQ_EVENT_DB_DPI_SFT 0
4511	__le32 v;
4512	#define NQ_DBQ_EVENT_V 0x1UL
4513	__le32 db_type_db_xid;
4514	#define NQ_DBQ_EVENT_DB_XID_MASK 0xfffffUL
4515	#define NQ_DBQ_EVENT_DB_XID_SFT 0
4516	#define NQ_DBQ_EVENT_DB_TYPE_MASK 0xf0000000UL
4517	#define NQ_DBQ_EVENT_DB_TYPE_SFT 28
4518	};
4519
4520	/* xrrq_irrq (size:256b/32B) */
4521	struct xrrq_irrq {
4522	__le16 credits_type;
4523	#define XRRQ_IRRQ_TYPE 0x1UL
4524	#define XRRQ_IRRQ_TYPE_READ_REQ 0x0UL
4525	#define XRRQ_IRRQ_TYPE_ATOMIC_REQ 0x1UL
4526	#define XRRQ_IRRQ_TYPE_LAST XRRQ_IRRQ_TYPE_ATOMIC_REQ
4527	#define XRRQ_IRRQ_CREDITS_MASK 0xf800UL
4528	#define XRRQ_IRRQ_CREDITS_SFT 11
4529	__le16 reserved16;
4530	__le32 reserved32;
4531	__le32 psn;
4532	#define XRRQ_IRRQ_PSN_MASK 0xffffffUL
4533	#define XRRQ_IRRQ_PSN_SFT 0
4534	__le32 msn;
4535	#define XRRQ_IRRQ_MSN_MASK 0xffffffUL
4536	#define XRRQ_IRRQ_MSN_SFT 0
4537	__le64 va_or_atomic_result;
4538	__le32 rdma_r_key;
4539	__le32 length;
4540	};
4541
4542	/* xrrq_orrq (size:256b/32B) */
4543	struct xrrq_orrq {
4544	__le16 num_sges_type;
4545	#define XRRQ_ORRQ_TYPE 0x1UL
4546	#define XRRQ_ORRQ_TYPE_READ_REQ 0x0UL
4547	#define XRRQ_ORRQ_TYPE_ATOMIC_REQ 0x1UL
4548	#define XRRQ_ORRQ_TYPE_LAST XRRQ_ORRQ_TYPE_ATOMIC_REQ
4549	#define XRRQ_ORRQ_NUM_SGES_MASK 0xf800UL
4550	#define XRRQ_ORRQ_NUM_SGES_SFT 11
4551	__le16 reserved16;
4552	__le32 length;
4553	__le32 psn;
4554	#define XRRQ_ORRQ_PSN_MASK 0xffffffUL
4555	#define XRRQ_ORRQ_PSN_SFT 0
4556	__le32 end_psn;
4557	#define XRRQ_ORRQ_END_PSN_MASK 0xffffffUL
4558	#define XRRQ_ORRQ_END_PSN_SFT 0
4559	__le64 first_sge_phy_or_sing_sge_va;
4560	__le32 single_sge_l_key;
4561	__le32 single_sge_size;
4562	};
4563
4564	/* ptu_pte (size:64b/8B) */
4565	struct ptu_pte {
4566	__le32 page_next_to_last_last_valid[2];
4567	#define PTU_PTE_VALID 0x1UL
4568	#define PTU_PTE_LAST 0x2UL
4569	#define PTU_PTE_NEXT_TO_LAST 0x4UL
4570	#define PTU_PTE_UNUSED_MASK 0xff8UL
4571	#define PTU_PTE_UNUSED_SFT 3
4572	#define PTU_PTE_PAGE_MASK 0xfffff000UL
4573	#define PTU_PTE_PAGE_SFT 12
4574	};
4575
4576	/* ptu_pde (size:64b/8B) */
4577	struct ptu_pde {
4578	__le32 page_valid[2];
4579	#define PTU_PDE_VALID 0x1UL
4580	#define PTU_PDE_UNUSED_MASK 0xffeUL
4581	#define PTU_PDE_UNUSED_SFT 1
4582	#define PTU_PDE_PAGE_MASK 0xfffff000UL
4583	#define PTU_PDE_PAGE_SFT 12
4584	};
4585
4586	#endif /* ___BNXT_RE_HSI_H__ */
4587