1 | /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ |
2 | /* |
3 | * Copyright(c) 2015, 2016 Intel Corporation. |
4 | */ |
5 | |
6 | #ifndef __PLATFORM_H |
7 | #define __PLATFORM_H |
8 | |
9 | #define METADATA_TABLE_FIELD_START_SHIFT 0 |
10 | #define METADATA_TABLE_FIELD_START_LEN_BITS 15 |
11 | #define METADATA_TABLE_FIELD_LEN_SHIFT 16 |
12 | #define METADATA_TABLE_FIELD_LEN_LEN_BITS 16 |
13 | |
14 | /* Header structure */ |
15 | #define 0 |
16 | #define 6 |
17 | #define 16 |
18 | #define 12 |
19 | #define 28 |
20 | #define 4 |
21 | |
22 | enum platform_config_table_type_encoding { |
23 | PLATFORM_CONFIG_TABLE_RESERVED, |
24 | PLATFORM_CONFIG_SYSTEM_TABLE, |
25 | PLATFORM_CONFIG_PORT_TABLE, |
26 | PLATFORM_CONFIG_RX_PRESET_TABLE, |
27 | PLATFORM_CONFIG_TX_PRESET_TABLE, |
28 | PLATFORM_CONFIG_QSFP_ATTEN_TABLE, |
29 | PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE, |
30 | PLATFORM_CONFIG_TABLE_MAX |
31 | }; |
32 | |
33 | enum platform_config_system_table_fields { |
34 | SYSTEM_TABLE_RESERVED, |
35 | SYSTEM_TABLE_NODE_STRING, |
36 | SYSTEM_TABLE_SYSTEM_IMAGE_GUID, |
37 | SYSTEM_TABLE_NODE_GUID, |
38 | SYSTEM_TABLE_REVISION, |
39 | SYSTEM_TABLE_VENDOR_OUI, |
40 | SYSTEM_TABLE_META_VERSION, |
41 | SYSTEM_TABLE_DEVICE_ID, |
42 | SYSTEM_TABLE_PARTITION_ENFORCEMENT_CAP, |
43 | SYSTEM_TABLE_QSFP_POWER_CLASS_MAX, |
44 | SYSTEM_TABLE_QSFP_ATTENUATION_DEFAULT_12G, |
45 | SYSTEM_TABLE_QSFP_ATTENUATION_DEFAULT_25G, |
46 | SYSTEM_TABLE_VARIABLE_TABLE_ENTRIES_PER_PORT, |
47 | SYSTEM_TABLE_MAX |
48 | }; |
49 | |
50 | enum platform_config_port_table_fields { |
51 | PORT_TABLE_RESERVED, |
52 | PORT_TABLE_PORT_TYPE, |
53 | PORT_TABLE_LOCAL_ATTEN_12G, |
54 | PORT_TABLE_LOCAL_ATTEN_25G, |
55 | PORT_TABLE_LINK_SPEED_SUPPORTED, |
56 | PORT_TABLE_LINK_WIDTH_SUPPORTED, |
57 | PORT_TABLE_AUTO_LANE_SHEDDING_ENABLED, |
58 | PORT_TABLE_EXTERNAL_LOOPBACK_ALLOWED, |
59 | PORT_TABLE_VL_CAP, |
60 | PORT_TABLE_MTU_CAP, |
61 | PORT_TABLE_TX_LANE_ENABLE_MASK, |
62 | PORT_TABLE_LOCAL_MAX_TIMEOUT, |
63 | PORT_TABLE_REMOTE_ATTEN_12G, |
64 | PORT_TABLE_REMOTE_ATTEN_25G, |
65 | PORT_TABLE_TX_PRESET_IDX_ACTIVE_NO_EQ, |
66 | PORT_TABLE_TX_PRESET_IDX_ACTIVE_EQ, |
67 | PORT_TABLE_RX_PRESET_IDX, |
68 | PORT_TABLE_CABLE_REACH_CLASS, |
69 | PORT_TABLE_MAX |
70 | }; |
71 | |
72 | enum platform_config_rx_preset_table_fields { |
73 | RX_PRESET_TABLE_RESERVED, |
74 | RX_PRESET_TABLE_QSFP_RX_CDR_APPLY, |
75 | RX_PRESET_TABLE_QSFP_RX_EMP_APPLY, |
76 | RX_PRESET_TABLE_QSFP_RX_AMP_APPLY, |
77 | RX_PRESET_TABLE_QSFP_RX_CDR, |
78 | RX_PRESET_TABLE_QSFP_RX_EMP, |
79 | RX_PRESET_TABLE_QSFP_RX_AMP, |
80 | RX_PRESET_TABLE_MAX |
81 | }; |
82 | |
83 | enum platform_config_tx_preset_table_fields { |
84 | TX_PRESET_TABLE_RESERVED, |
85 | TX_PRESET_TABLE_PRECUR, |
86 | TX_PRESET_TABLE_ATTN, |
87 | TX_PRESET_TABLE_POSTCUR, |
88 | TX_PRESET_TABLE_QSFP_TX_CDR_APPLY, |
89 | TX_PRESET_TABLE_QSFP_TX_EQ_APPLY, |
90 | TX_PRESET_TABLE_QSFP_TX_CDR, |
91 | TX_PRESET_TABLE_QSFP_TX_EQ, |
92 | TX_PRESET_TABLE_MAX |
93 | }; |
94 | |
95 | enum platform_config_qsfp_attn_table_fields { |
96 | QSFP_ATTEN_TABLE_RESERVED, |
97 | QSFP_ATTEN_TABLE_TX_PRESET_IDX, |
98 | QSFP_ATTEN_TABLE_RX_PRESET_IDX, |
99 | QSFP_ATTEN_TABLE_MAX |
100 | }; |
101 | |
102 | enum platform_config_variable_settings_table_fields { |
103 | VARIABLE_SETTINGS_TABLE_RESERVED, |
104 | VARIABLE_SETTINGS_TABLE_TX_PRESET_IDX, |
105 | VARIABLE_SETTINGS_TABLE_RX_PRESET_IDX, |
106 | VARIABLE_SETTINGS_TABLE_MAX |
107 | }; |
108 | |
109 | struct platform_config { |
110 | size_t size; |
111 | const u8 *data; |
112 | }; |
113 | |
114 | struct platform_config_data { |
115 | u32 *table; |
116 | u32 *table_metadata; |
117 | u32 num_table; |
118 | }; |
119 | |
120 | /* |
121 | * This struct acts as a quick reference into the platform_data binary image |
122 | * and is populated by parse_platform_config(...) depending on the specific |
123 | * META_VERSION |
124 | */ |
125 | struct platform_config_cache { |
126 | u8 cache_valid; |
127 | struct platform_config_data config_tables[PLATFORM_CONFIG_TABLE_MAX]; |
128 | }; |
129 | |
130 | /* This section defines default values and encodings for the |
131 | * fields defined for each table above |
132 | */ |
133 | |
134 | /* |
135 | * ===================================================== |
136 | * System table encodings |
137 | * ===================================================== |
138 | */ |
139 | #define PLATFORM_CONFIG_MAGIC_NUM 0x3d4f5041 |
140 | #define PLATFORM_CONFIG_MAGIC_NUMBER_LEN 4 |
141 | |
142 | /* |
143 | * These power classes are the same as defined in SFF 8636 spec rev 2.4 |
144 | * describing byte 129 in table 6-16, except enumerated in a different order |
145 | */ |
146 | enum platform_config_qsfp_power_class_encoding { |
147 | QSFP_POWER_CLASS_1 = 1, |
148 | QSFP_POWER_CLASS_2, |
149 | QSFP_POWER_CLASS_3, |
150 | QSFP_POWER_CLASS_4, |
151 | QSFP_POWER_CLASS_5, |
152 | QSFP_POWER_CLASS_6, |
153 | QSFP_POWER_CLASS_7 |
154 | }; |
155 | |
156 | /* |
157 | * ==================================================== |
158 | * Port table encodings |
159 | * ==================================================== |
160 | */ |
161 | enum platform_config_port_type_encoding { |
162 | PORT_TYPE_UNKNOWN, |
163 | PORT_TYPE_DISCONNECTED, |
164 | PORT_TYPE_FIXED, |
165 | PORT_TYPE_VARIABLE, |
166 | PORT_TYPE_QSFP, |
167 | PORT_TYPE_MAX |
168 | }; |
169 | |
170 | enum platform_config_link_speed_supported_encoding { |
171 | LINK_SPEED_SUPP_12G = 1, |
172 | LINK_SPEED_SUPP_25G, |
173 | LINK_SPEED_SUPP_12G_25G, |
174 | LINK_SPEED_SUPP_MAX |
175 | }; |
176 | |
177 | /* |
178 | * This is a subset (not strict) of the link downgrades |
179 | * supported. The link downgrades supported are expected |
180 | * to be supplied to the driver by another entity such as |
181 | * the fabric manager |
182 | */ |
183 | enum platform_config_link_width_supported_encoding { |
184 | LINK_WIDTH_SUPP_1X = 1, |
185 | LINK_WIDTH_SUPP_2X, |
186 | LINK_WIDTH_SUPP_2X_1X, |
187 | LINK_WIDTH_SUPP_3X, |
188 | LINK_WIDTH_SUPP_3X_1X, |
189 | LINK_WIDTH_SUPP_3X_2X, |
190 | LINK_WIDTH_SUPP_3X_2X_1X, |
191 | LINK_WIDTH_SUPP_4X, |
192 | LINK_WIDTH_SUPP_4X_1X, |
193 | LINK_WIDTH_SUPP_4X_2X, |
194 | LINK_WIDTH_SUPP_4X_2X_1X, |
195 | LINK_WIDTH_SUPP_4X_3X, |
196 | LINK_WIDTH_SUPP_4X_3X_1X, |
197 | LINK_WIDTH_SUPP_4X_3X_2X, |
198 | LINK_WIDTH_SUPP_4X_3X_2X_1X, |
199 | LINK_WIDTH_SUPP_MAX |
200 | }; |
201 | |
202 | enum platform_config_virtual_lane_capability_encoding { |
203 | VL_CAP_VL0 = 1, |
204 | VL_CAP_VL0_1, |
205 | VL_CAP_VL0_2, |
206 | VL_CAP_VL0_3, |
207 | VL_CAP_VL0_4, |
208 | VL_CAP_VL0_5, |
209 | VL_CAP_VL0_6, |
210 | VL_CAP_VL0_7, |
211 | VL_CAP_VL0_8, |
212 | VL_CAP_VL0_9, |
213 | VL_CAP_VL0_10, |
214 | VL_CAP_VL0_11, |
215 | VL_CAP_VL0_12, |
216 | VL_CAP_VL0_13, |
217 | VL_CAP_VL0_14, |
218 | VL_CAP_MAX |
219 | }; |
220 | |
221 | /* Max MTU */ |
222 | enum platform_config_mtu_capability_encoding { |
223 | MTU_CAP_256 = 1, |
224 | MTU_CAP_512 = 2, |
225 | MTU_CAP_1024 = 3, |
226 | MTU_CAP_2048 = 4, |
227 | MTU_CAP_4096 = 5, |
228 | MTU_CAP_8192 = 6, |
229 | MTU_CAP_10240 = 7 |
230 | }; |
231 | |
232 | enum platform_config_local_max_timeout_encoding { |
233 | LOCAL_MAX_TIMEOUT_10_MS = 1, |
234 | LOCAL_MAX_TIMEOUT_100_MS, |
235 | LOCAL_MAX_TIMEOUT_1_S, |
236 | LOCAL_MAX_TIMEOUT_10_S, |
237 | LOCAL_MAX_TIMEOUT_100_S, |
238 | LOCAL_MAX_TIMEOUT_1000_S |
239 | }; |
240 | |
241 | enum link_tuning_encoding { |
242 | OPA_PASSIVE_TUNING, |
243 | OPA_ACTIVE_TUNING, |
244 | OPA_UNKNOWN_TUNING |
245 | }; |
246 | |
247 | /* |
248 | * Shifts and masks for the link SI tuning values stuffed into the ASIC scratch |
249 | * registers for integrated platforms |
250 | */ |
251 | #define PORT0_PORT_TYPE_SHIFT 0 |
252 | #define PORT0_LOCAL_ATTEN_SHIFT 4 |
253 | #define PORT0_REMOTE_ATTEN_SHIFT 10 |
254 | #define PORT0_DEFAULT_ATTEN_SHIFT 32 |
255 | |
256 | #define PORT1_PORT_TYPE_SHIFT 16 |
257 | #define PORT1_LOCAL_ATTEN_SHIFT 20 |
258 | #define PORT1_REMOTE_ATTEN_SHIFT 26 |
259 | #define PORT1_DEFAULT_ATTEN_SHIFT 40 |
260 | |
261 | #define PORT0_PORT_TYPE_MASK 0xFUL |
262 | #define PORT0_LOCAL_ATTEN_MASK 0x3FUL |
263 | #define PORT0_REMOTE_ATTEN_MASK 0x3FUL |
264 | #define PORT0_DEFAULT_ATTEN_MASK 0xFFUL |
265 | |
266 | #define PORT1_PORT_TYPE_MASK 0xFUL |
267 | #define PORT1_LOCAL_ATTEN_MASK 0x3FUL |
268 | #define PORT1_REMOTE_ATTEN_MASK 0x3FUL |
269 | #define PORT1_DEFAULT_ATTEN_MASK 0xFFUL |
270 | |
271 | #define PORT0_PORT_TYPE_SMASK (PORT0_PORT_TYPE_MASK << \ |
272 | PORT0_PORT_TYPE_SHIFT) |
273 | #define PORT0_LOCAL_ATTEN_SMASK (PORT0_LOCAL_ATTEN_MASK << \ |
274 | PORT0_LOCAL_ATTEN_SHIFT) |
275 | #define PORT0_REMOTE_ATTEN_SMASK (PORT0_REMOTE_ATTEN_MASK << \ |
276 | PORT0_REMOTE_ATTEN_SHIFT) |
277 | #define PORT0_DEFAULT_ATTEN_SMASK (PORT0_DEFAULT_ATTEN_MASK << \ |
278 | PORT0_DEFAULT_ATTEN_SHIFT) |
279 | |
280 | #define PORT1_PORT_TYPE_SMASK (PORT1_PORT_TYPE_MASK << \ |
281 | PORT1_PORT_TYPE_SHIFT) |
282 | #define PORT1_LOCAL_ATTEN_SMASK (PORT1_LOCAL_ATTEN_MASK << \ |
283 | PORT1_LOCAL_ATTEN_SHIFT) |
284 | #define PORT1_REMOTE_ATTEN_SMASK (PORT1_REMOTE_ATTEN_MASK << \ |
285 | PORT1_REMOTE_ATTEN_SHIFT) |
286 | #define PORT1_DEFAULT_ATTEN_SMASK (PORT1_DEFAULT_ATTEN_MASK << \ |
287 | PORT1_DEFAULT_ATTEN_SHIFT) |
288 | |
289 | #define QSFP_MAX_POWER_SHIFT 0 |
290 | #define TX_NO_EQ_SHIFT 4 |
291 | #define TX_EQ_SHIFT 25 |
292 | #define RX_SHIFT 46 |
293 | |
294 | #define QSFP_MAX_POWER_MASK 0xFUL |
295 | #define TX_NO_EQ_MASK 0x1FFFFFUL |
296 | #define TX_EQ_MASK 0x1FFFFFUL |
297 | #define RX_MASK 0xFFFFUL |
298 | |
299 | #define QSFP_MAX_POWER_SMASK (QSFP_MAX_POWER_MASK << \ |
300 | QSFP_MAX_POWER_SHIFT) |
301 | #define TX_NO_EQ_SMASK (TX_NO_EQ_MASK << TX_NO_EQ_SHIFT) |
302 | #define TX_EQ_SMASK (TX_EQ_MASK << TX_EQ_SHIFT) |
303 | #define RX_SMASK (RX_MASK << RX_SHIFT) |
304 | |
305 | #define TX_PRECUR_SHIFT 0 |
306 | #define TX_ATTN_SHIFT 4 |
307 | #define QSFP_TX_CDR_APPLY_SHIFT 9 |
308 | #define QSFP_TX_EQ_APPLY_SHIFT 10 |
309 | #define QSFP_TX_CDR_SHIFT 11 |
310 | #define QSFP_TX_EQ_SHIFT 12 |
311 | #define TX_POSTCUR_SHIFT 16 |
312 | |
313 | #define TX_PRECUR_MASK 0xFUL |
314 | #define TX_ATTN_MASK 0x1FUL |
315 | #define QSFP_TX_CDR_APPLY_MASK 0x1UL |
316 | #define QSFP_TX_EQ_APPLY_MASK 0x1UL |
317 | #define QSFP_TX_CDR_MASK 0x1UL |
318 | #define QSFP_TX_EQ_MASK 0xFUL |
319 | #define TX_POSTCUR_MASK 0x1FUL |
320 | |
321 | #define TX_PRECUR_SMASK (TX_PRECUR_MASK << TX_PRECUR_SHIFT) |
322 | #define TX_ATTN_SMASK (TX_ATTN_MASK << TX_ATTN_SHIFT) |
323 | #define QSFP_TX_CDR_APPLY_SMASK (QSFP_TX_CDR_APPLY_MASK << \ |
324 | QSFP_TX_CDR_APPLY_SHIFT) |
325 | #define QSFP_TX_EQ_APPLY_SMASK (QSFP_TX_EQ_APPLY_MASK << \ |
326 | QSFP_TX_EQ_APPLY_SHIFT) |
327 | #define QSFP_TX_CDR_SMASK (QSFP_TX_CDR_MASK << QSFP_TX_CDR_SHIFT) |
328 | #define QSFP_TX_EQ_SMASK (QSFP_TX_EQ_MASK << QSFP_TX_EQ_SHIFT) |
329 | #define TX_POSTCUR_SMASK (TX_POSTCUR_MASK << TX_POSTCUR_SHIFT) |
330 | |
331 | #define QSFP_RX_CDR_APPLY_SHIFT 0 |
332 | #define QSFP_RX_EMP_APPLY_SHIFT 1 |
333 | #define QSFP_RX_AMP_APPLY_SHIFT 2 |
334 | #define QSFP_RX_CDR_SHIFT 3 |
335 | #define QSFP_RX_EMP_SHIFT 4 |
336 | #define QSFP_RX_AMP_SHIFT 8 |
337 | |
338 | #define QSFP_RX_CDR_APPLY_MASK 0x1UL |
339 | #define QSFP_RX_EMP_APPLY_MASK 0x1UL |
340 | #define QSFP_RX_AMP_APPLY_MASK 0x1UL |
341 | #define QSFP_RX_CDR_MASK 0x1UL |
342 | #define QSFP_RX_EMP_MASK 0xFUL |
343 | #define QSFP_RX_AMP_MASK 0x3UL |
344 | |
345 | #define QSFP_RX_CDR_APPLY_SMASK (QSFP_RX_CDR_APPLY_MASK << \ |
346 | QSFP_RX_CDR_APPLY_SHIFT) |
347 | #define QSFP_RX_EMP_APPLY_SMASK (QSFP_RX_EMP_APPLY_MASK << \ |
348 | QSFP_RX_EMP_APPLY_SHIFT) |
349 | #define QSFP_RX_AMP_APPLY_SMASK (QSFP_RX_AMP_APPLY_MASK << \ |
350 | QSFP_RX_AMP_APPLY_SHIFT) |
351 | #define QSFP_RX_CDR_SMASK (QSFP_RX_CDR_MASK << QSFP_RX_CDR_SHIFT) |
352 | #define QSFP_RX_EMP_SMASK (QSFP_RX_EMP_MASK << QSFP_RX_EMP_SHIFT) |
353 | #define QSFP_RX_AMP_SMASK (QSFP_RX_AMP_MASK << QSFP_RX_AMP_SHIFT) |
354 | |
355 | #define BITMAP_VERSION 1 |
356 | #define BITMAP_VERSION_SHIFT 44 |
357 | #define BITMAP_VERSION_MASK 0xFUL |
358 | #define BITMAP_VERSION_SMASK (BITMAP_VERSION_MASK << \ |
359 | BITMAP_VERSION_SHIFT) |
360 | #define CHECKSUM_SHIFT 48 |
361 | #define CHECKSUM_MASK 0xFFFFUL |
362 | #define CHECKSUM_SMASK (CHECKSUM_MASK << CHECKSUM_SHIFT) |
363 | |
364 | /* platform.c */ |
365 | void get_platform_config(struct hfi1_devdata *dd); |
366 | void free_platform_config(struct hfi1_devdata *dd); |
367 | void get_port_type(struct hfi1_pportdata *ppd); |
368 | int set_qsfp_tx(struct hfi1_pportdata *ppd, int on); |
369 | void tune_serdes(struct hfi1_pportdata *ppd); |
370 | |
371 | #endif /*__PLATFORM_H*/ |
372 | |