1	// SPDX-License-Identifier: GPL-2.0-or-later
2	/*
3	* Azoteq IQS7222A/B/C/D Capacitive Touch Controller
4	*
5	* Copyright (C) 2022 Jeff LaBundy <jeff@labundy.com>
6	*/
7
8	#include <linux/bits.h>
9	#include <linux/delay.h>
10	#include <linux/device.h>
11	#include <linux/err.h>
12	#include <linux/gpio/consumer.h>
13	#include <linux/i2c.h>
14	#include <linux/input.h>
15	#include <linux/input/touchscreen.h>
16	#include <linux/interrupt.h>
17	#include <linux/kernel.h>
18	#include <linux/ktime.h>
19	#include <linux/mod_devicetable.h>
20	#include <linux/module.h>
21	#include <linux/property.h>
22	#include <linux/slab.h>
23	#include <asm/unaligned.h>
24
25	#define IQS7222_PROD_NUM 0x00
26	#define IQS7222_PROD_NUM_A 840
27	#define IQS7222_PROD_NUM_B 698
28	#define IQS7222_PROD_NUM_C 863
29	#define IQS7222_PROD_NUM_D 1046
30
31	#define IQS7222_SYS_STATUS 0x10
32	#define IQS7222_SYS_STATUS_RESET BIT(3)
33	#define IQS7222_SYS_STATUS_ATI_ERROR BIT(1)
34	#define IQS7222_SYS_STATUS_ATI_ACTIVE BIT(0)
35
36	#define IQS7222_CHAN_SETUP_0_REF_MODE_MASK GENMASK(15, 14)
37	#define IQS7222_CHAN_SETUP_0_REF_MODE_FOLLOW BIT(15)
38	#define IQS7222_CHAN_SETUP_0_REF_MODE_REF BIT(14)
39	#define IQS7222_CHAN_SETUP_0_CHAN_EN BIT(8)
40
41	#define IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK GENMASK(2, 0)
42	#define IQS7222_SLDR_SETUP_2_RES_MASK GENMASK(15, 8)
43	#define IQS7222_SLDR_SETUP_2_RES_SHIFT 8
44	#define IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK GENMASK(7, 0)
45
46	#define IQS7222_GPIO_SETUP_0_GPIO_EN BIT(0)
47
48	#define IQS7222_SYS_SETUP 0xD0
49	#define IQS7222_SYS_SETUP_INTF_MODE_MASK GENMASK(7, 6)
50	#define IQS7222_SYS_SETUP_INTF_MODE_TOUCH BIT(7)
51	#define IQS7222_SYS_SETUP_INTF_MODE_EVENT BIT(6)
52	#define IQS7222_SYS_SETUP_PWR_MODE_MASK GENMASK(5, 4)
53	#define IQS7222_SYS_SETUP_PWR_MODE_AUTO IQS7222_SYS_SETUP_PWR_MODE_MASK
54	#define IQS7222_SYS_SETUP_REDO_ATI BIT(2)
55	#define IQS7222_SYS_SETUP_ACK_RESET BIT(0)
56
57	#define IQS7222_EVENT_MASK_ATI BIT(12)
58	#define IQS7222_EVENT_MASK_SLDR BIT(10)
59	#define IQS7222_EVENT_MASK_TPAD IQS7222_EVENT_MASK_SLDR
60	#define IQS7222_EVENT_MASK_TOUCH BIT(1)
61	#define IQS7222_EVENT_MASK_PROX BIT(0)
62
63	#define IQS7222_COMMS_HOLD BIT(0)
64	#define IQS7222_COMMS_ERROR 0xEEEE
65	#define IQS7222_COMMS_RETRY_MS 50
66	#define IQS7222_COMMS_TIMEOUT_MS 100
67	#define IQS7222_RESET_TIMEOUT_MS 250
68	#define IQS7222_ATI_TIMEOUT_MS 2000
69
70	#define IQS7222_MAX_COLS_STAT 8
71	#define IQS7222_MAX_COLS_CYCLE 3
72	#define IQS7222_MAX_COLS_GLBL 3
73	#define IQS7222_MAX_COLS_BTN 3
74	#define IQS7222_MAX_COLS_CHAN 6
75	#define IQS7222_MAX_COLS_FILT 2
76	#define IQS7222_MAX_COLS_SLDR 11
77	#define IQS7222_MAX_COLS_TPAD 24
78	#define IQS7222_MAX_COLS_GPIO 3
79	#define IQS7222_MAX_COLS_SYS 13
80
81	#define IQS7222_MAX_CHAN 20
82	#define IQS7222_MAX_SLDR 2
83
84	#define IQS7222_NUM_RETRIES 5
85	#define IQS7222_REG_OFFSET 0x100
86
87	enum iqs7222_reg_key_id {
88	IQS7222_REG_KEY_NONE,
89	IQS7222_REG_KEY_PROX,
90	IQS7222_REG_KEY_TOUCH,
91	IQS7222_REG_KEY_DEBOUNCE,
92	IQS7222_REG_KEY_TAP,
93	IQS7222_REG_KEY_TAP_LEGACY,
94	IQS7222_REG_KEY_AXIAL,
95	IQS7222_REG_KEY_AXIAL_LEGACY,
96	IQS7222_REG_KEY_WHEEL,
97	IQS7222_REG_KEY_NO_WHEEL,
98	IQS7222_REG_KEY_RESERVED
99	};
100
101	enum iqs7222_reg_grp_id {
102	IQS7222_REG_GRP_STAT,
103	IQS7222_REG_GRP_FILT,
104	IQS7222_REG_GRP_CYCLE,
105	IQS7222_REG_GRP_GLBL,
106	IQS7222_REG_GRP_BTN,
107	IQS7222_REG_GRP_CHAN,
108	IQS7222_REG_GRP_SLDR,
109	IQS7222_REG_GRP_TPAD,
110	IQS7222_REG_GRP_GPIO,
111	IQS7222_REG_GRP_SYS,
112	IQS7222_NUM_REG_GRPS
113	};
114
115	static const char * const iqs7222_reg_grp_names[IQS7222_NUM_REG_GRPS] = {
116	[IQS7222_REG_GRP_CYCLE] = "cycle-%d",
117	[IQS7222_REG_GRP_CHAN] = "channel-%d",
118	[IQS7222_REG_GRP_SLDR] = "slider-%d",
119	[IQS7222_REG_GRP_TPAD] = "trackpad",
120	[IQS7222_REG_GRP_GPIO] = "gpio-%d",
121	};
122
123	static const unsigned int iqs7222_max_cols[IQS7222_NUM_REG_GRPS] = {
124	[IQS7222_REG_GRP_STAT] = IQS7222_MAX_COLS_STAT,
125	[IQS7222_REG_GRP_CYCLE] = IQS7222_MAX_COLS_CYCLE,
126	[IQS7222_REG_GRP_GLBL] = IQS7222_MAX_COLS_GLBL,
127	[IQS7222_REG_GRP_BTN] = IQS7222_MAX_COLS_BTN,
128	[IQS7222_REG_GRP_CHAN] = IQS7222_MAX_COLS_CHAN,
129	[IQS7222_REG_GRP_FILT] = IQS7222_MAX_COLS_FILT,
130	[IQS7222_REG_GRP_SLDR] = IQS7222_MAX_COLS_SLDR,
131	[IQS7222_REG_GRP_TPAD] = IQS7222_MAX_COLS_TPAD,
132	[IQS7222_REG_GRP_GPIO] = IQS7222_MAX_COLS_GPIO,
133	[IQS7222_REG_GRP_SYS] = IQS7222_MAX_COLS_SYS,
134	};
135
136	static const unsigned int iqs7222_gpio_links[] = { 2, 5, 6, };
137
138	struct iqs7222_event_desc {
139	const char *name;
140	u16 link;
141	u16 mask;
142	u16 val;
143	u16 strict;
144	u16 enable;
145	enum iqs7222_reg_key_id reg_key;
146	};
147
148	static const struct iqs7222_event_desc iqs7222_kp_events[] = {
149	{
150	.name = "event-prox",
151	.enable = IQS7222_EVENT_MASK_PROX,
152	.reg_key = IQS7222_REG_KEY_PROX,
153	},
154	{
155	.name = "event-touch",
156	.enable = IQS7222_EVENT_MASK_TOUCH,
157	.reg_key = IQS7222_REG_KEY_TOUCH,
158	},
159	};
160
161	static const struct iqs7222_event_desc iqs7222_sl_events[] = {
162	{ .name = "event-press", },
163	{
164	.name = "event-tap",
165	.mask = BIT(0),
166	.val = BIT(0),
167	.enable = BIT(0),
168	.reg_key = IQS7222_REG_KEY_TAP,
169	},
170	{
171	.name = "event-swipe-pos",
172	.mask = BIT(5) | BIT(1),
173	.val = BIT(1),
174	.enable = BIT(1),
175	.reg_key = IQS7222_REG_KEY_AXIAL,
176	},
177	{
178	.name = "event-swipe-neg",
179	.mask = BIT(5) | BIT(1),
180	.val = BIT(5) | BIT(1),
181	.enable = BIT(1),
182	.reg_key = IQS7222_REG_KEY_AXIAL,
183	},
184	{
185	.name = "event-flick-pos",
186	.mask = BIT(5) | BIT(2),
187	.val = BIT(2),
188	.enable = BIT(2),
189	.reg_key = IQS7222_REG_KEY_AXIAL,
190	},
191	{
192	.name = "event-flick-neg",
193	.mask = BIT(5) | BIT(2),
194	.val = BIT(5) | BIT(2),
195	.enable = BIT(2),
196	.reg_key = IQS7222_REG_KEY_AXIAL,
197	},
198	};
199
200	static const struct iqs7222_event_desc iqs7222_tp_events[] = {
201	{
202	.name = "event-press",
203	.link = BIT(7),
204	},
205	{
206	.name = "event-tap",
207	.link = BIT(0),
208	.mask = BIT(0),
209	.val = BIT(0),
210	.enable = BIT(0),
211	.reg_key = IQS7222_REG_KEY_TAP,
212	},
213	{
214	.name = "event-swipe-x-pos",
215	.link = BIT(2),
216	.mask = BIT(2) | BIT(1),
217	.val = BIT(2),
218	.strict = BIT(4),
219	.enable = BIT(1),
220	.reg_key = IQS7222_REG_KEY_AXIAL,
221	},
222	{
223	.name = "event-swipe-y-pos",
224	.link = BIT(3),
225	.mask = BIT(3) | BIT(1),
226	.val = BIT(3),
227	.strict = BIT(3),
228	.enable = BIT(1),
229	.reg_key = IQS7222_REG_KEY_AXIAL,
230	},
231	{
232	.name = "event-swipe-x-neg",
233	.link = BIT(4),
234	.mask = BIT(4) | BIT(1),
235	.val = BIT(4),
236	.strict = BIT(4),
237	.enable = BIT(1),
238	.reg_key = IQS7222_REG_KEY_AXIAL,
239	},
240	{
241	.name = "event-swipe-y-neg",
242	.link = BIT(5),
243	.mask = BIT(5) | BIT(1),
244	.val = BIT(5),
245	.strict = BIT(3),
246	.enable = BIT(1),
247	.reg_key = IQS7222_REG_KEY_AXIAL,
248	},
249	{
250	.name = "event-flick-x-pos",
251	.link = BIT(2),
252	.mask = BIT(2) | BIT(1),
253	.val = BIT(2) | BIT(1),
254	.strict = BIT(4),
255	.enable = BIT(2),
256	.reg_key = IQS7222_REG_KEY_AXIAL,
257	},
258	{
259	.name = "event-flick-y-pos",
260	.link = BIT(3),
261	.mask = BIT(3) | BIT(1),
262	.val = BIT(3) | BIT(1),
263	.strict = BIT(3),
264	.enable = BIT(2),
265	.reg_key = IQS7222_REG_KEY_AXIAL,
266	},
267	{
268	.name = "event-flick-x-neg",
269	.link = BIT(4),
270	.mask = BIT(4) | BIT(1),
271	.val = BIT(4) | BIT(1),
272	.strict = BIT(4),
273	.enable = BIT(2),
274	.reg_key = IQS7222_REG_KEY_AXIAL,
275	},
276	{
277	.name = "event-flick-y-neg",
278	.link = BIT(5),
279	.mask = BIT(5) | BIT(1),
280	.val = BIT(5) | BIT(1),
281	.strict = BIT(3),
282	.enable = BIT(2),
283	.reg_key = IQS7222_REG_KEY_AXIAL,
284	},
285	};
286
287	struct iqs7222_reg_grp_desc {
288	u16 base;
289	int num_row;
290	int num_col;
291	};
292
293	struct iqs7222_dev_desc {
294	u16 prod_num;
295	u16 fw_major;
296	u16 fw_minor;
297	u16 sldr_res;
298	u16 touch_link;
299	u16 wheel_enable;
300	int allow_offset;
301	int event_offset;
302	int comms_offset;
303	bool legacy_gesture;
304	struct iqs7222_reg_grp_desc reg_grps[IQS7222_NUM_REG_GRPS];
305	};
306
307	static const struct iqs7222_dev_desc iqs7222_devs[] = {
308	{
309	.prod_num = IQS7222_PROD_NUM_A,
310	.fw_major = 1,
311	.fw_minor = 13,
312	.sldr_res = U8_MAX * 16,
313	.touch_link = 1768,
314	.allow_offset = 9,
315	.event_offset = 10,
316	.comms_offset = 12,
317	.reg_grps = {
318	[IQS7222_REG_GRP_STAT] = {
319	.base = IQS7222_SYS_STATUS,
320	.num_row = 1,
321	.num_col = 8,
322	},
323	[IQS7222_REG_GRP_CYCLE] = {
324	.base = 0x8000,
325	.num_row = 7,
326	.num_col = 3,
327	},
328	[IQS7222_REG_GRP_GLBL] = {
329	.base = 0x8700,
330	.num_row = 1,
331	.num_col = 3,
332	},
333	[IQS7222_REG_GRP_BTN] = {
334	.base = 0x9000,
335	.num_row = 12,
336	.num_col = 3,
337	},
338	[IQS7222_REG_GRP_CHAN] = {
339	.base = 0xA000,
340	.num_row = 12,
341	.num_col = 6,
342	},
343	[IQS7222_REG_GRP_FILT] = {
344	.base = 0xAC00,
345	.num_row = 1,
346	.num_col = 2,
347	},
348	[IQS7222_REG_GRP_SLDR] = {
349	.base = 0xB000,
350	.num_row = 2,
351	.num_col = 11,
352	},
353	[IQS7222_REG_GRP_GPIO] = {
354	.base = 0xC000,
355	.num_row = 1,
356	.num_col = 3,
357	},
358	[IQS7222_REG_GRP_SYS] = {
359	.base = IQS7222_SYS_SETUP,
360	.num_row = 1,
361	.num_col = 13,
362	},
363	},
364	},
365	{
366	.prod_num = IQS7222_PROD_NUM_A,
367	.fw_major = 1,
368	.fw_minor = 12,
369	.sldr_res = U8_MAX * 16,
370	.touch_link = 1768,
371	.allow_offset = 9,
372	.event_offset = 10,
373	.comms_offset = 12,
374	.legacy_gesture = true,
375	.reg_grps = {
376	[IQS7222_REG_GRP_STAT] = {
377	.base = IQS7222_SYS_STATUS,
378	.num_row = 1,
379	.num_col = 8,
380	},
381	[IQS7222_REG_GRP_CYCLE] = {
382	.base = 0x8000,
383	.num_row = 7,
384	.num_col = 3,
385	},
386	[IQS7222_REG_GRP_GLBL] = {
387	.base = 0x8700,
388	.num_row = 1,
389	.num_col = 3,
390	},
391	[IQS7222_REG_GRP_BTN] = {
392	.base = 0x9000,
393	.num_row = 12,
394	.num_col = 3,
395	},
396	[IQS7222_REG_GRP_CHAN] = {
397	.base = 0xA000,
398	.num_row = 12,
399	.num_col = 6,
400	},
401	[IQS7222_REG_GRP_FILT] = {
402	.base = 0xAC00,
403	.num_row = 1,
404	.num_col = 2,
405	},
406	[IQS7222_REG_GRP_SLDR] = {
407	.base = 0xB000,
408	.num_row = 2,
409	.num_col = 11,
410	},
411	[IQS7222_REG_GRP_GPIO] = {
412	.base = 0xC000,
413	.num_row = 1,
414	.num_col = 3,
415	},
416	[IQS7222_REG_GRP_SYS] = {
417	.base = IQS7222_SYS_SETUP,
418	.num_row = 1,
419	.num_col = 13,
420	},
421	},
422	},
423	{
424	.prod_num = IQS7222_PROD_NUM_B,
425	.fw_major = 1,
426	.fw_minor = 43,
427	.event_offset = 10,
428	.comms_offset = 11,
429	.reg_grps = {
430	[IQS7222_REG_GRP_STAT] = {
431	.base = IQS7222_SYS_STATUS,
432	.num_row = 1,
433	.num_col = 6,
434	},
435	[IQS7222_REG_GRP_CYCLE] = {
436	.base = 0x8000,
437	.num_row = 10,
438	.num_col = 2,
439	},
440	[IQS7222_REG_GRP_GLBL] = {
441	.base = 0x8A00,
442	.num_row = 1,
443	.num_col = 3,
444	},
445	[IQS7222_REG_GRP_BTN] = {
446	.base = 0x9000,
447	.num_row = 20,
448	.num_col = 2,
449	},
450	[IQS7222_REG_GRP_CHAN] = {
451	.base = 0xB000,
452	.num_row = 20,
453	.num_col = 4,
454	},
455	[IQS7222_REG_GRP_FILT] = {
456	.base = 0xC400,
457	.num_row = 1,
458	.num_col = 2,
459	},
460	[IQS7222_REG_GRP_SYS] = {
461	.base = IQS7222_SYS_SETUP,
462	.num_row = 1,
463	.num_col = 13,
464	},
465	},
466	},
467	{
468	.prod_num = IQS7222_PROD_NUM_B,
469	.fw_major = 1,
470	.fw_minor = 27,
471	.reg_grps = {
472	[IQS7222_REG_GRP_STAT] = {
473	.base = IQS7222_SYS_STATUS,
474	.num_row = 1,
475	.num_col = 6,
476	},
477	[IQS7222_REG_GRP_CYCLE] = {
478	.base = 0x8000,
479	.num_row = 10,
480	.num_col = 2,
481	},
482	[IQS7222_REG_GRP_GLBL] = {
483	.base = 0x8A00,
484	.num_row = 1,
485	.num_col = 3,
486	},
487	[IQS7222_REG_GRP_BTN] = {
488	.base = 0x9000,
489	.num_row = 20,
490	.num_col = 2,
491	},
492	[IQS7222_REG_GRP_CHAN] = {
493	.base = 0xB000,
494	.num_row = 20,
495	.num_col = 4,
496	},
497	[IQS7222_REG_GRP_FILT] = {
498	.base = 0xC400,
499	.num_row = 1,
500	.num_col = 2,
501	},
502	[IQS7222_REG_GRP_SYS] = {
503	.base = IQS7222_SYS_SETUP,
504	.num_row = 1,
505	.num_col = 10,
506	},
507	},
508	},
509	{
510	.prod_num = IQS7222_PROD_NUM_C,
511	.fw_major = 2,
512	.fw_minor = 6,
513	.sldr_res = U16_MAX,
514	.touch_link = 1686,
515	.wheel_enable = BIT(3),
516	.event_offset = 9,
517	.comms_offset = 10,
518	.reg_grps = {
519	[IQS7222_REG_GRP_STAT] = {
520	.base = IQS7222_SYS_STATUS,
521	.num_row = 1,
522	.num_col = 6,
523	},
524	[IQS7222_REG_GRP_CYCLE] = {
525	.base = 0x8000,
526	.num_row = 5,
527	.num_col = 3,
528	},
529	[IQS7222_REG_GRP_GLBL] = {
530	.base = 0x8500,
531	.num_row = 1,
532	.num_col = 3,
533	},
534	[IQS7222_REG_GRP_BTN] = {
535	.base = 0x9000,
536	.num_row = 10,
537	.num_col = 3,
538	},
539	[IQS7222_REG_GRP_CHAN] = {
540	.base = 0xA000,
541	.num_row = 10,
542	.num_col = 6,
543	},
544	[IQS7222_REG_GRP_FILT] = {
545	.base = 0xAA00,
546	.num_row = 1,
547	.num_col = 2,
548	},
549	[IQS7222_REG_GRP_SLDR] = {
550	.base = 0xB000,
551	.num_row = 2,
552	.num_col = 10,
553	},
554	[IQS7222_REG_GRP_GPIO] = {
555	.base = 0xC000,
556	.num_row = 3,
557	.num_col = 3,
558	},
559	[IQS7222_REG_GRP_SYS] = {
560	.base = IQS7222_SYS_SETUP,
561	.num_row = 1,
562	.num_col = 12,
563	},
564	},
565	},
566	{
567	.prod_num = IQS7222_PROD_NUM_C,
568	.fw_major = 1,
569	.fw_minor = 13,
570	.sldr_res = U16_MAX,
571	.touch_link = 1674,
572	.wheel_enable = BIT(3),
573	.event_offset = 9,
574	.comms_offset = 10,
575	.reg_grps = {
576	[IQS7222_REG_GRP_STAT] = {
577	.base = IQS7222_SYS_STATUS,
578	.num_row = 1,
579	.num_col = 6,
580	},
581	[IQS7222_REG_GRP_CYCLE] = {
582	.base = 0x8000,
583	.num_row = 5,
584	.num_col = 3,
585	},
586	[IQS7222_REG_GRP_GLBL] = {
587	.base = 0x8500,
588	.num_row = 1,
589	.num_col = 3,
590	},
591	[IQS7222_REG_GRP_BTN] = {
592	.base = 0x9000,
593	.num_row = 10,
594	.num_col = 3,
595	},
596	[IQS7222_REG_GRP_CHAN] = {
597	.base = 0xA000,
598	.num_row = 10,
599	.num_col = 6,
600	},
601	[IQS7222_REG_GRP_FILT] = {
602	.base = 0xAA00,
603	.num_row = 1,
604	.num_col = 2,
605	},
606	[IQS7222_REG_GRP_SLDR] = {
607	.base = 0xB000,
608	.num_row = 2,
609	.num_col = 10,
610	},
611	[IQS7222_REG_GRP_GPIO] = {
612	.base = 0xC000,
613	.num_row = 1,
614	.num_col = 3,
615	},
616	[IQS7222_REG_GRP_SYS] = {
617	.base = IQS7222_SYS_SETUP,
618	.num_row = 1,
619	.num_col = 11,
620	},
621	},
622	},
623	{
624	.prod_num = IQS7222_PROD_NUM_D,
625	.fw_major = 1,
626	.fw_minor = 2,
627	.touch_link = 1770,
628	.allow_offset = 9,
629	.event_offset = 10,
630	.comms_offset = 11,
631	.reg_grps = {
632	[IQS7222_REG_GRP_STAT] = {
633	.base = IQS7222_SYS_STATUS,
634	.num_row = 1,
635	.num_col = 7,
636	},
637	[IQS7222_REG_GRP_CYCLE] = {
638	.base = 0x8000,
639	.num_row = 7,
640	.num_col = 2,
641	},
642	[IQS7222_REG_GRP_GLBL] = {
643	.base = 0x8700,
644	.num_row = 1,
645	.num_col = 3,
646	},
647	[IQS7222_REG_GRP_BTN] = {
648	.base = 0x9000,
649	.num_row = 14,
650	.num_col = 3,
651	},
652	[IQS7222_REG_GRP_CHAN] = {
653	.base = 0xA000,
654	.num_row = 14,
655	.num_col = 4,
656	},
657	[IQS7222_REG_GRP_FILT] = {
658	.base = 0xAE00,
659	.num_row = 1,
660	.num_col = 2,
661	},
662	[IQS7222_REG_GRP_TPAD] = {
663	.base = 0xB000,
664	.num_row = 1,
665	.num_col = 24,
666	},
667	[IQS7222_REG_GRP_GPIO] = {
668	.base = 0xC000,
669	.num_row = 3,
670	.num_col = 3,
671	},
672	[IQS7222_REG_GRP_SYS] = {
673	.base = IQS7222_SYS_SETUP,
674	.num_row = 1,
675	.num_col = 12,
676	},
677	},
678	},
679	{
680	.prod_num = IQS7222_PROD_NUM_D,
681	.fw_major = 1,
682	.fw_minor = 1,
683	.touch_link = 1774,
684	.allow_offset = 9,
685	.event_offset = 10,
686	.comms_offset = 11,
687	.reg_grps = {
688	[IQS7222_REG_GRP_STAT] = {
689	.base = IQS7222_SYS_STATUS,
690	.num_row = 1,
691	.num_col = 7,
692	},
693	[IQS7222_REG_GRP_CYCLE] = {
694	.base = 0x8000,
695	.num_row = 7,
696	.num_col = 2,
697	},
698	[IQS7222_REG_GRP_GLBL] = {
699	.base = 0x8700,
700	.num_row = 1,
701	.num_col = 3,
702	},
703	[IQS7222_REG_GRP_BTN] = {
704	.base = 0x9000,
705	.num_row = 14,
706	.num_col = 3,
707	},
708	[IQS7222_REG_GRP_CHAN] = {
709	.base = 0xA000,
710	.num_row = 14,
711	.num_col = 4,
712	},
713	[IQS7222_REG_GRP_FILT] = {
714	.base = 0xAE00,
715	.num_row = 1,
716	.num_col = 2,
717	},
718	[IQS7222_REG_GRP_TPAD] = {
719	.base = 0xB000,
720	.num_row = 1,
721	.num_col = 24,
722	},
723	[IQS7222_REG_GRP_GPIO] = {
724	.base = 0xC000,
725	.num_row = 3,
726	.num_col = 3,
727	},
728	[IQS7222_REG_GRP_SYS] = {
729	.base = IQS7222_SYS_SETUP,
730	.num_row = 1,
731	.num_col = 12,
732	},
733	},
734	},
735	{
736	.prod_num = IQS7222_PROD_NUM_D,
737	.fw_major = 0,
738	.fw_minor = 37,
739	.touch_link = 1770,
740	.allow_offset = 9,
741	.event_offset = 10,
742	.comms_offset = 11,
743	.reg_grps = {
744	[IQS7222_REG_GRP_STAT] = {
745	.base = IQS7222_SYS_STATUS,
746	.num_row = 1,
747	.num_col = 7,
748	},
749	[IQS7222_REG_GRP_CYCLE] = {
750	.base = 0x8000,
751	.num_row = 7,
752	.num_col = 2,
753	},
754	[IQS7222_REG_GRP_GLBL] = {
755	.base = 0x8700,
756	.num_row = 1,
757	.num_col = 3,
758	},
759	[IQS7222_REG_GRP_BTN] = {
760	.base = 0x9000,
761	.num_row = 14,
762	.num_col = 3,
763	},
764	[IQS7222_REG_GRP_CHAN] = {
765	.base = 0xA000,
766	.num_row = 14,
767	.num_col = 4,
768	},
769	[IQS7222_REG_GRP_FILT] = {
770	.base = 0xAE00,
771	.num_row = 1,
772	.num_col = 2,
773	},
774	[IQS7222_REG_GRP_TPAD] = {
775	.base = 0xB000,
776	.num_row = 1,
777	.num_col = 24,
778	},
779	[IQS7222_REG_GRP_GPIO] = {
780	.base = 0xC000,
781	.num_row = 3,
782	.num_col = 3,
783	},
784	[IQS7222_REG_GRP_SYS] = {
785	.base = IQS7222_SYS_SETUP,
786	.num_row = 1,
787	.num_col = 12,
788	},
789	},
790	},
791	};
792
793	struct iqs7222_prop_desc {
794	const char *name;
795	enum iqs7222_reg_grp_id reg_grp;
796	enum iqs7222_reg_key_id reg_key;
797	int reg_offset;
798	int reg_shift;
799	int reg_width;
800	int val_pitch;
801	int val_min;
802	int val_max;
803	bool invert;
804	const char *label;
805	};
806
807	static const struct iqs7222_prop_desc iqs7222_props[] = {
808	{
809	.name = "azoteq,conv-period",
810	.reg_grp = IQS7222_REG_GRP_CYCLE,
811	.reg_offset = 0,
812	.reg_shift = 8,
813	.reg_width = 8,
814	.label = "conversion period",
815	},
816	{
817	.name = "azoteq,conv-frac",
818	.reg_grp = IQS7222_REG_GRP_CYCLE,
819	.reg_offset = 0,
820	.reg_shift = 0,
821	.reg_width = 8,
822	.label = "conversion frequency fractional divider",
823	},
824	{
825	.name = "azoteq,rx-float-inactive",
826	.reg_grp = IQS7222_REG_GRP_CYCLE,
827	.reg_offset = 1,
828	.reg_shift = 6,
829	.reg_width = 1,
830	.invert = true,
831	},
832	{
833	.name = "azoteq,dead-time-enable",
834	.reg_grp = IQS7222_REG_GRP_CYCLE,
835	.reg_offset = 1,
836	.reg_shift = 5,
837	.reg_width = 1,
838	},
839	{
840	.name = "azoteq,tx-freq-fosc",
841	.reg_grp = IQS7222_REG_GRP_CYCLE,
842	.reg_offset = 1,
843	.reg_shift = 4,
844	.reg_width = 1,
845	},
846	{
847	.name = "azoteq,vbias-enable",
848	.reg_grp = IQS7222_REG_GRP_CYCLE,
849	.reg_offset = 1,
850	.reg_shift = 3,
851	.reg_width = 1,
852	},
853	{
854	.name = "azoteq,sense-mode",
855	.reg_grp = IQS7222_REG_GRP_CYCLE,
856	.reg_offset = 1,
857	.reg_shift = 0,
858	.reg_width = 3,
859	.val_max = 3,
860	.label = "sensing mode",
861	},
862	{
863	.name = "azoteq,iref-enable",
864	.reg_grp = IQS7222_REG_GRP_CYCLE,
865	.reg_offset = 2,
866	.reg_shift = 10,
867	.reg_width = 1,
868	},
869	{
870	.name = "azoteq,iref-level",
871	.reg_grp = IQS7222_REG_GRP_CYCLE,
872	.reg_offset = 2,
873	.reg_shift = 4,
874	.reg_width = 4,
875	.label = "current reference level",
876	},
877	{
878	.name = "azoteq,iref-trim",
879	.reg_grp = IQS7222_REG_GRP_CYCLE,
880	.reg_offset = 2,
881	.reg_shift = 0,
882	.reg_width = 4,
883	.label = "current reference trim",
884	},
885	{
886	.name = "azoteq,max-counts",
887	.reg_grp = IQS7222_REG_GRP_GLBL,
888	.reg_offset = 0,
889	.reg_shift = 13,
890	.reg_width = 2,
891	.label = "maximum counts",
892	},
893	{
894	.name = "azoteq,auto-mode",
895	.reg_grp = IQS7222_REG_GRP_GLBL,
896	.reg_offset = 0,
897	.reg_shift = 2,
898	.reg_width = 2,
899	.label = "number of conversions",
900	},
901	{
902	.name = "azoteq,ati-frac-div-fine",
903	.reg_grp = IQS7222_REG_GRP_GLBL,
904	.reg_offset = 1,
905	.reg_shift = 9,
906	.reg_width = 5,
907	.label = "ATI fine fractional divider",
908	},
909	{
910	.name = "azoteq,ati-frac-div-coarse",
911	.reg_grp = IQS7222_REG_GRP_GLBL,
912	.reg_offset = 1,
913	.reg_shift = 0,
914	.reg_width = 5,
915	.label = "ATI coarse fractional divider",
916	},
917	{
918	.name = "azoteq,ati-comp-select",
919	.reg_grp = IQS7222_REG_GRP_GLBL,
920	.reg_offset = 2,
921	.reg_shift = 0,
922	.reg_width = 10,
923	.label = "ATI compensation selection",
924	},
925	{
926	.name = "azoteq,ati-band",
927	.reg_grp = IQS7222_REG_GRP_CHAN,
928	.reg_offset = 0,
929	.reg_shift = 12,
930	.reg_width = 2,
931	.label = "ATI band",
932	},
933	{
934	.name = "azoteq,global-halt",
935	.reg_grp = IQS7222_REG_GRP_CHAN,
936	.reg_offset = 0,
937	.reg_shift = 11,
938	.reg_width = 1,
939	},
940	{
941	.name = "azoteq,invert-enable",
942	.reg_grp = IQS7222_REG_GRP_CHAN,
943	.reg_offset = 0,
944	.reg_shift = 10,
945	.reg_width = 1,
946	},
947	{
948	.name = "azoteq,dual-direction",
949	.reg_grp = IQS7222_REG_GRP_CHAN,
950	.reg_offset = 0,
951	.reg_shift = 9,
952	.reg_width = 1,
953	},
954	{
955	.name = "azoteq,samp-cap-double",
956	.reg_grp = IQS7222_REG_GRP_CHAN,
957	.reg_offset = 0,
958	.reg_shift = 3,
959	.reg_width = 1,
960	},
961	{
962	.name = "azoteq,vref-half",
963	.reg_grp = IQS7222_REG_GRP_CHAN,
964	.reg_offset = 0,
965	.reg_shift = 2,
966	.reg_width = 1,
967	},
968	{
969	.name = "azoteq,proj-bias",
970	.reg_grp = IQS7222_REG_GRP_CHAN,
971	.reg_offset = 0,
972	.reg_shift = 0,
973	.reg_width = 2,
974	.label = "projected bias current",
975	},
976	{
977	.name = "azoteq,ati-target",
978	.reg_grp = IQS7222_REG_GRP_CHAN,
979	.reg_offset = 1,
980	.reg_shift = 8,
981	.reg_width = 8,
982	.val_pitch = 8,
983	.label = "ATI target",
984	},
985	{
986	.name = "azoteq,ati-base",
987	.reg_grp = IQS7222_REG_GRP_CHAN,
988	.reg_offset = 1,
989	.reg_shift = 3,
990	.reg_width = 5,
991	.val_pitch = 16,
992	.label = "ATI base",
993	},
994	{
995	.name = "azoteq,ati-mode",
996	.reg_grp = IQS7222_REG_GRP_CHAN,
997	.reg_offset = 1,
998	.reg_shift = 0,
999	.reg_width = 3,
1000	.val_max = 5,
1001	.label = "ATI mode",
1002	},
1003	{
1004	.name = "azoteq,ati-frac-div-fine",
1005	.reg_grp = IQS7222_REG_GRP_CHAN,
1006	.reg_offset = 2,
1007	.reg_shift = 9,
1008	.reg_width = 5,
1009	.label = "ATI fine fractional divider",
1010	},
1011	{
1012	.name = "azoteq,ati-frac-mult-coarse",
1013	.reg_grp = IQS7222_REG_GRP_CHAN,
1014	.reg_offset = 2,
1015	.reg_shift = 5,
1016	.reg_width = 4,
1017	.label = "ATI coarse fractional multiplier",
1018	},
1019	{
1020	.name = "azoteq,ati-frac-div-coarse",
1021	.reg_grp = IQS7222_REG_GRP_CHAN,
1022	.reg_offset = 2,
1023	.reg_shift = 0,
1024	.reg_width = 5,
1025	.label = "ATI coarse fractional divider",
1026	},
1027	{
1028	.name = "azoteq,ati-comp-div",
1029	.reg_grp = IQS7222_REG_GRP_CHAN,
1030	.reg_offset = 3,
1031	.reg_shift = 11,
1032	.reg_width = 5,
1033	.label = "ATI compensation divider",
1034	},
1035	{
1036	.name = "azoteq,ati-comp-select",
1037	.reg_grp = IQS7222_REG_GRP_CHAN,
1038	.reg_offset = 3,
1039	.reg_shift = 0,
1040	.reg_width = 10,
1041	.label = "ATI compensation selection",
1042	},
1043	{
1044	.name = "azoteq,debounce-exit",
1045	.reg_grp = IQS7222_REG_GRP_BTN,
1046	.reg_key = IQS7222_REG_KEY_DEBOUNCE,
1047	.reg_offset = 0,
1048	.reg_shift = 12,
1049	.reg_width = 4,
1050	.label = "debounce exit factor",
1051	},
1052	{
1053	.name = "azoteq,debounce-enter",
1054	.reg_grp = IQS7222_REG_GRP_BTN,
1055	.reg_key = IQS7222_REG_KEY_DEBOUNCE,
1056	.reg_offset = 0,
1057	.reg_shift = 8,
1058	.reg_width = 4,
1059	.label = "debounce entrance factor",
1060	},
1061	{
1062	.name = "azoteq,thresh",
1063	.reg_grp = IQS7222_REG_GRP_BTN,
1064	.reg_key = IQS7222_REG_KEY_PROX,
1065	.reg_offset = 0,
1066	.reg_shift = 0,
1067	.reg_width = 8,
1068	.val_max = 127,
1069	.label = "threshold",
1070	},
1071	{
1072	.name = "azoteq,thresh",
1073	.reg_grp = IQS7222_REG_GRP_BTN,
1074	.reg_key = IQS7222_REG_KEY_TOUCH,
1075	.reg_offset = 1,
1076	.reg_shift = 0,
1077	.reg_width = 8,
1078	.label = "threshold",
1079	},
1080	{
1081	.name = "azoteq,hyst",
1082	.reg_grp = IQS7222_REG_GRP_BTN,
1083	.reg_key = IQS7222_REG_KEY_TOUCH,
1084	.reg_offset = 1,
1085	.reg_shift = 8,
1086	.reg_width = 8,
1087	.label = "hysteresis",
1088	},
1089	{
1090	.name = "azoteq,lta-beta-lp",
1091	.reg_grp = IQS7222_REG_GRP_FILT,
1092	.reg_offset = 0,
1093	.reg_shift = 12,
1094	.reg_width = 4,
1095	.label = "low-power mode long-term average beta",
1096	},
1097	{
1098	.name = "azoteq,lta-beta-np",
1099	.reg_grp = IQS7222_REG_GRP_FILT,
1100	.reg_offset = 0,
1101	.reg_shift = 8,
1102	.reg_width = 4,
1103	.label = "normal-power mode long-term average beta",
1104	},
1105	{
1106	.name = "azoteq,counts-beta-lp",
1107	.reg_grp = IQS7222_REG_GRP_FILT,
1108	.reg_offset = 0,
1109	.reg_shift = 4,
1110	.reg_width = 4,
1111	.label = "low-power mode counts beta",
1112	},
1113	{
1114	.name = "azoteq,counts-beta-np",
1115	.reg_grp = IQS7222_REG_GRP_FILT,
1116	.reg_offset = 0,
1117	.reg_shift = 0,
1118	.reg_width = 4,
1119	.label = "normal-power mode counts beta",
1120	},
1121	{
1122	.name = "azoteq,lta-fast-beta-lp",
1123	.reg_grp = IQS7222_REG_GRP_FILT,
1124	.reg_offset = 1,
1125	.reg_shift = 4,
1126	.reg_width = 4,
1127	.label = "low-power mode long-term average fast beta",
1128	},
1129	{
1130	.name = "azoteq,lta-fast-beta-np",
1131	.reg_grp = IQS7222_REG_GRP_FILT,
1132	.reg_offset = 1,
1133	.reg_shift = 0,
1134	.reg_width = 4,
1135	.label = "normal-power mode long-term average fast beta",
1136	},
1137	{
1138	.name = "azoteq,lower-cal",
1139	.reg_grp = IQS7222_REG_GRP_SLDR,
1140	.reg_offset = 0,
1141	.reg_shift = 8,
1142	.reg_width = 8,
1143	.label = "lower calibration",
1144	},
1145	{
1146	.name = "azoteq,static-beta",
1147	.reg_grp = IQS7222_REG_GRP_SLDR,
1148	.reg_key = IQS7222_REG_KEY_NO_WHEEL,
1149	.reg_offset = 0,
1150	.reg_shift = 6,
1151	.reg_width = 1,
1152	},
1153	{
1154	.name = "azoteq,bottom-beta",
1155	.reg_grp = IQS7222_REG_GRP_SLDR,
1156	.reg_key = IQS7222_REG_KEY_NO_WHEEL,
1157	.reg_offset = 0,
1158	.reg_shift = 3,
1159	.reg_width = 3,
1160	.label = "bottom beta",
1161	},
1162	{
1163	.name = "azoteq,static-beta",
1164	.reg_grp = IQS7222_REG_GRP_SLDR,
1165	.reg_key = IQS7222_REG_KEY_WHEEL,
1166	.reg_offset = 0,
1167	.reg_shift = 7,
1168	.reg_width = 1,
1169	},
1170	{
1171	.name = "azoteq,bottom-beta",
1172	.reg_grp = IQS7222_REG_GRP_SLDR,
1173	.reg_key = IQS7222_REG_KEY_WHEEL,
1174	.reg_offset = 0,
1175	.reg_shift = 4,
1176	.reg_width = 3,
1177	.label = "bottom beta",
1178	},
1179	{
1180	.name = "azoteq,bottom-speed",
1181	.reg_grp = IQS7222_REG_GRP_SLDR,
1182	.reg_offset = 1,
1183	.reg_shift = 8,
1184	.reg_width = 8,
1185	.label = "bottom speed",
1186	},
1187	{
1188	.name = "azoteq,upper-cal",
1189	.reg_grp = IQS7222_REG_GRP_SLDR,
1190	.reg_offset = 1,
1191	.reg_shift = 0,
1192	.reg_width = 8,
1193	.label = "upper calibration",
1194	},
1195	{
1196	.name = "azoteq,gesture-max-ms",
1197	.reg_grp = IQS7222_REG_GRP_SLDR,
1198	.reg_key = IQS7222_REG_KEY_TAP,
1199	.reg_offset = 9,
1200	.reg_shift = 8,
1201	.reg_width = 8,
1202	.val_pitch = 16,
1203	.label = "maximum gesture time",
1204	},
1205	{
1206	.name = "azoteq,gesture-max-ms",
1207	.reg_grp = IQS7222_REG_GRP_SLDR,
1208	.reg_key = IQS7222_REG_KEY_TAP_LEGACY,
1209	.reg_offset = 9,
1210	.reg_shift = 8,
1211	.reg_width = 8,
1212	.val_pitch = 4,
1213	.label = "maximum gesture time",
1214	},
1215	{
1216	.name = "azoteq,gesture-min-ms",
1217	.reg_grp = IQS7222_REG_GRP_SLDR,
1218	.reg_key = IQS7222_REG_KEY_TAP,
1219	.reg_offset = 9,
1220	.reg_shift = 3,
1221	.reg_width = 5,
1222	.val_pitch = 16,
1223	.label = "minimum gesture time",
1224	},
1225	{
1226	.name = "azoteq,gesture-min-ms",
1227	.reg_grp = IQS7222_REG_GRP_SLDR,
1228	.reg_key = IQS7222_REG_KEY_TAP_LEGACY,
1229	.reg_offset = 9,
1230	.reg_shift = 3,
1231	.reg_width = 5,
1232	.val_pitch = 4,
1233	.label = "minimum gesture time",
1234	},
1235	{
1236	.name = "azoteq,gesture-dist",
1237	.reg_grp = IQS7222_REG_GRP_SLDR,
1238	.reg_key = IQS7222_REG_KEY_AXIAL,
1239	.reg_offset = 10,
1240	.reg_shift = 8,
1241	.reg_width = 8,
1242	.val_pitch = 16,
1243	.label = "gesture distance",
1244	},
1245	{
1246	.name = "azoteq,gesture-dist",
1247	.reg_grp = IQS7222_REG_GRP_SLDR,
1248	.reg_key = IQS7222_REG_KEY_AXIAL_LEGACY,
1249	.reg_offset = 10,
1250	.reg_shift = 8,
1251	.reg_width = 8,
1252	.val_pitch = 16,
1253	.label = "gesture distance",
1254	},
1255	{
1256	.name = "azoteq,gesture-max-ms",
1257	.reg_grp = IQS7222_REG_GRP_SLDR,
1258	.reg_key = IQS7222_REG_KEY_AXIAL,
1259	.reg_offset = 10,
1260	.reg_shift = 0,
1261	.reg_width = 8,
1262	.val_pitch = 16,
1263	.label = "maximum gesture time",
1264	},
1265	{
1266	.name = "azoteq,gesture-max-ms",
1267	.reg_grp = IQS7222_REG_GRP_SLDR,
1268	.reg_key = IQS7222_REG_KEY_AXIAL_LEGACY,
1269	.reg_offset = 10,
1270	.reg_shift = 0,
1271	.reg_width = 8,
1272	.val_pitch = 4,
1273	.label = "maximum gesture time",
1274	},
1275	{
1276	.name = "azoteq,num-rows",
1277	.reg_grp = IQS7222_REG_GRP_TPAD,
1278	.reg_offset = 0,
1279	.reg_shift = 4,
1280	.reg_width = 4,
1281	.val_min = 1,
1282	.val_max = 12,
1283	.label = "number of rows",
1284	},
1285	{
1286	.name = "azoteq,num-cols",
1287	.reg_grp = IQS7222_REG_GRP_TPAD,
1288	.reg_offset = 0,
1289	.reg_shift = 0,
1290	.reg_width = 4,
1291	.val_min = 1,
1292	.val_max = 12,
1293	.label = "number of columns",
1294	},
1295	{
1296	.name = "azoteq,lower-cal-y",
1297	.reg_grp = IQS7222_REG_GRP_TPAD,
1298	.reg_offset = 1,
1299	.reg_shift = 8,
1300	.reg_width = 8,
1301	.label = "lower vertical calibration",
1302	},
1303	{
1304	.name = "azoteq,lower-cal-x",
1305	.reg_grp = IQS7222_REG_GRP_TPAD,
1306	.reg_offset = 1,
1307	.reg_shift = 0,
1308	.reg_width = 8,
1309	.label = "lower horizontal calibration",
1310	},
1311	{
1312	.name = "azoteq,upper-cal-y",
1313	.reg_grp = IQS7222_REG_GRP_TPAD,
1314	.reg_offset = 2,
1315	.reg_shift = 8,
1316	.reg_width = 8,
1317	.label = "upper vertical calibration",
1318	},
1319	{
1320	.name = "azoteq,upper-cal-x",
1321	.reg_grp = IQS7222_REG_GRP_TPAD,
1322	.reg_offset = 2,
1323	.reg_shift = 0,
1324	.reg_width = 8,
1325	.label = "upper horizontal calibration",
1326	},
1327	{
1328	.name = "azoteq,top-speed",
1329	.reg_grp = IQS7222_REG_GRP_TPAD,
1330	.reg_offset = 3,
1331	.reg_shift = 8,
1332	.reg_width = 8,
1333	.val_pitch = 4,
1334	.label = "top speed",
1335	},
1336	{
1337	.name = "azoteq,bottom-speed",
1338	.reg_grp = IQS7222_REG_GRP_TPAD,
1339	.reg_offset = 3,
1340	.reg_shift = 0,
1341	.reg_width = 8,
1342	.label = "bottom speed",
1343	},
1344	{
1345	.name = "azoteq,gesture-min-ms",
1346	.reg_grp = IQS7222_REG_GRP_TPAD,
1347	.reg_key = IQS7222_REG_KEY_TAP,
1348	.reg_offset = 20,
1349	.reg_shift = 8,
1350	.reg_width = 8,
1351	.val_pitch = 16,
1352	.label = "minimum gesture time",
1353	},
1354	{
1355	.name = "azoteq,gesture-max-ms",
1356	.reg_grp = IQS7222_REG_GRP_TPAD,
1357	.reg_key = IQS7222_REG_KEY_AXIAL,
1358	.reg_offset = 21,
1359	.reg_shift = 8,
1360	.reg_width = 8,
1361	.val_pitch = 16,
1362	.label = "maximum gesture time",
1363	},
1364	{
1365	.name = "azoteq,gesture-max-ms",
1366	.reg_grp = IQS7222_REG_GRP_TPAD,
1367	.reg_key = IQS7222_REG_KEY_TAP,
1368	.reg_offset = 21,
1369	.reg_shift = 0,
1370	.reg_width = 8,
1371	.val_pitch = 16,
1372	.label = "maximum gesture time",
1373	},
1374	{
1375	.name = "azoteq,gesture-dist",
1376	.reg_grp = IQS7222_REG_GRP_TPAD,
1377	.reg_key = IQS7222_REG_KEY_TAP,
1378	.reg_offset = 22,
1379	.reg_shift = 0,
1380	.reg_width = 16,
1381	.label = "gesture distance",
1382	},
1383	{
1384	.name = "azoteq,gesture-dist",
1385	.reg_grp = IQS7222_REG_GRP_TPAD,
1386	.reg_key = IQS7222_REG_KEY_AXIAL,
1387	.reg_offset = 23,
1388	.reg_shift = 0,
1389	.reg_width = 16,
1390	.label = "gesture distance",
1391	},
1392	{
1393	.name = "drive-open-drain",
1394	.reg_grp = IQS7222_REG_GRP_GPIO,
1395	.reg_offset = 0,
1396	.reg_shift = 1,
1397	.reg_width = 1,
1398	},
1399	{
1400	.name = "azoteq,timeout-ati-ms",
1401	.reg_grp = IQS7222_REG_GRP_SYS,
1402	.reg_offset = 1,
1403	.reg_shift = 0,
1404	.reg_width = 16,
1405	.val_pitch = 500,
1406	.label = "ATI error timeout",
1407	},
1408	{
1409	.name = "azoteq,rate-ati-ms",
1410	.reg_grp = IQS7222_REG_GRP_SYS,
1411	.reg_offset = 2,
1412	.reg_shift = 0,
1413	.reg_width = 16,
1414	.label = "ATI report rate",
1415	},
1416	{
1417	.name = "azoteq,timeout-np-ms",
1418	.reg_grp = IQS7222_REG_GRP_SYS,
1419	.reg_offset = 3,
1420	.reg_shift = 0,
1421	.reg_width = 16,
1422	.label = "normal-power mode timeout",
1423	},
1424	{
1425	.name = "azoteq,rate-np-ms",
1426	.reg_grp = IQS7222_REG_GRP_SYS,
1427	.reg_offset = 4,
1428	.reg_shift = 0,
1429	.reg_width = 16,
1430	.val_max = 3000,
1431	.label = "normal-power mode report rate",
1432	},
1433	{
1434	.name = "azoteq,timeout-lp-ms",
1435	.reg_grp = IQS7222_REG_GRP_SYS,
1436	.reg_offset = 5,
1437	.reg_shift = 0,
1438	.reg_width = 16,
1439	.label = "low-power mode timeout",
1440	},
1441	{
1442	.name = "azoteq,rate-lp-ms",
1443	.reg_grp = IQS7222_REG_GRP_SYS,
1444	.reg_offset = 6,
1445	.reg_shift = 0,
1446	.reg_width = 16,
1447	.val_max = 3000,
1448	.label = "low-power mode report rate",
1449	},
1450	{
1451	.name = "azoteq,timeout-ulp-ms",
1452	.reg_grp = IQS7222_REG_GRP_SYS,
1453	.reg_offset = 7,
1454	.reg_shift = 0,
1455	.reg_width = 16,
1456	.label = "ultra-low-power mode timeout",
1457	},
1458	{
1459	.name = "azoteq,rate-ulp-ms",
1460	.reg_grp = IQS7222_REG_GRP_SYS,
1461	.reg_offset = 8,
1462	.reg_shift = 0,
1463	.reg_width = 16,
1464	.val_max = 3000,
1465	.label = "ultra-low-power mode report rate",
1466	},
1467	};
1468
1469	struct iqs7222_private {
1470	const struct iqs7222_dev_desc *dev_desc;
1471	struct gpio_desc *reset_gpio;
1472	struct gpio_desc *irq_gpio;
1473	struct i2c_client *client;
1474	struct input_dev *keypad;
1475	struct touchscreen_properties prop;
1476	unsigned int kp_type[IQS7222_MAX_CHAN][ARRAY_SIZE(iqs7222_kp_events)];
1477	unsigned int kp_code[IQS7222_MAX_CHAN][ARRAY_SIZE(iqs7222_kp_events)];
1478	unsigned int sl_code[IQS7222_MAX_SLDR][ARRAY_SIZE(iqs7222_sl_events)];
1479	unsigned int sl_axis[IQS7222_MAX_SLDR];
1480	unsigned int tp_code[ARRAY_SIZE(iqs7222_tp_events)];
1481	u16 cycle_setup[IQS7222_MAX_CHAN / 2][IQS7222_MAX_COLS_CYCLE];
1482	u16 glbl_setup[IQS7222_MAX_COLS_GLBL];
1483	u16 btn_setup[IQS7222_MAX_CHAN][IQS7222_MAX_COLS_BTN];
1484	u16 chan_setup[IQS7222_MAX_CHAN][IQS7222_MAX_COLS_CHAN];
1485	u16 filt_setup[IQS7222_MAX_COLS_FILT];
1486	u16 sldr_setup[IQS7222_MAX_SLDR][IQS7222_MAX_COLS_SLDR];
1487	u16 tpad_setup[IQS7222_MAX_COLS_TPAD];
1488	u16 gpio_setup[ARRAY_SIZE(iqs7222_gpio_links)][IQS7222_MAX_COLS_GPIO];
1489	u16 sys_setup[IQS7222_MAX_COLS_SYS];
1490	};
1491
1492	static u16 *iqs7222_setup(struct iqs7222_private *iqs7222,
1493	enum iqs7222_reg_grp_id reg_grp, int row)
1494	{
1495	switch (reg_grp) {
1496	case IQS7222_REG_GRP_CYCLE:
1497	return iqs7222->cycle_setup[row];
1498
1499	case IQS7222_REG_GRP_GLBL:
1500	return iqs7222->glbl_setup;
1501
1502	case IQS7222_REG_GRP_BTN:
1503	return iqs7222->btn_setup[row];
1504
1505	case IQS7222_REG_GRP_CHAN:
1506	return iqs7222->chan_setup[row];
1507
1508	case IQS7222_REG_GRP_FILT:
1509	return iqs7222->filt_setup;
1510
1511	case IQS7222_REG_GRP_SLDR:
1512	return iqs7222->sldr_setup[row];
1513
1514	case IQS7222_REG_GRP_TPAD:
1515	return iqs7222->tpad_setup;
1516
1517	case IQS7222_REG_GRP_GPIO:
1518	return iqs7222->gpio_setup[row];
1519
1520	case IQS7222_REG_GRP_SYS:
1521	return iqs7222->sys_setup;
1522
1523	default:
1524	return NULL;
1525	}
1526	}
1527
1528	static int iqs7222_irq_poll(struct iqs7222_private *iqs7222, u16 timeout_ms)
1529	{
1530	ktime_t irq_timeout = ktime_add_ms(kt: ktime_get(), msec: timeout_ms);
1531	int ret;
1532
1533	do {
1534	usleep_range(min: 1000, max: 1100);
1535
1536	ret = gpiod_get_value_cansleep(desc: iqs7222->irq_gpio);
1537	if (ret < 0)
1538	return ret;
1539	else if (ret > 0)
1540	return 0;
1541	} while (ktime_compare(cmp1: ktime_get(), cmp2: irq_timeout) < 0);
1542
1543	return -EBUSY;
1544	}
1545
1546	static int iqs7222_hard_reset(struct iqs7222_private *iqs7222)
1547	{
1548	struct i2c_client *client = iqs7222->client;
1549	int error;
1550
1551	if (!iqs7222->reset_gpio)
1552	return 0;
1553
1554	gpiod_set_value_cansleep(desc: iqs7222->reset_gpio, value: 1);
1555	usleep_range(min: 1000, max: 1100);
1556
1557	gpiod_set_value_cansleep(desc: iqs7222->reset_gpio, value: 0);
1558
1559	error = iqs7222_irq_poll(iqs7222, IQS7222_RESET_TIMEOUT_MS);
1560	if (error)
1561	dev_err(&client->dev, "Failed to reset device: %d\n", error);
1562
1563	return error;
1564	}
1565
1566	static int iqs7222_force_comms(struct iqs7222_private *iqs7222)
1567	{
1568	u8 msg_buf[] = { 0xFF, };
1569	int ret;
1570
1571	/*
1572	* The device cannot communicate until it asserts its interrupt (RDY)
1573	* pin. Attempts to do so while RDY is deasserted return an ACK; how-
1574	* ever all write data is ignored, and all read data returns 0xEE.
1575	*
1576	* Unsolicited communication must be preceded by a special force com-
1577	* munication command, after which the device eventually asserts its
1578	* RDY pin and agrees to communicate.
1579	*
1580	* Regardless of whether communication is forced or the result of an
1581	* interrupt, the device automatically deasserts its RDY pin once it
1582	* detects an I2C stop condition, or a timeout expires.
1583	*/
1584	ret = gpiod_get_value_cansleep(desc: iqs7222->irq_gpio);
1585	if (ret < 0)
1586	return ret;
1587	else if (ret > 0)
1588	return 0;
1589
1590	ret = i2c_master_send(client: iqs7222->client, buf: msg_buf, count: sizeof(msg_buf));
1591	if (ret < (int)sizeof(msg_buf)) {
1592	if (ret >= 0)
1593	ret = -EIO;
1594
1595	/*
1596	* The datasheet states that the host must wait to retry any
1597	* failed attempt to communicate over I2C.
1598	*/
1599	msleep(IQS7222_COMMS_RETRY_MS);
1600	return ret;
1601	}
1602
1603	return iqs7222_irq_poll(iqs7222, IQS7222_COMMS_TIMEOUT_MS);
1604	}
1605
1606	static int iqs7222_read_burst(struct iqs7222_private *iqs7222,
1607	u16 reg, void *val, u16 num_val)
1608	{
1609	u8 reg_buf[sizeof(__be16)];
1610	int ret, i;
1611	struct i2c_client *client = iqs7222->client;
1612	struct i2c_msg msg[] = {
1613	{
1614	.addr = client->addr,
1615	.flags = 0,
1616	.len = reg > U8_MAX ? sizeof(reg) : sizeof(u8),
1617	.buf = reg_buf,
1618	},
1619	{
1620	.addr = client->addr,
1621	.flags = I2C_M_RD,
1622	.len = num_val * sizeof(__le16),
1623	.buf = (u8 *)val,
1624	},
1625	};
1626
1627	if (reg > U8_MAX)
1628	put_unaligned_be16(val: reg, p: reg_buf);
1629	else
1630	*reg_buf = (u8)reg;
1631
1632	/*
1633	* The following loop protects against an edge case in which the RDY
1634	* pin is automatically deasserted just as the read is initiated. In
1635	* that case, the read must be retried using forced communication.
1636	*/
1637	for (i = 0; i < IQS7222_NUM_RETRIES; i++) {
1638	ret = iqs7222_force_comms(iqs7222);
1639	if (ret < 0)
1640	continue;
1641
1642	ret = i2c_transfer(adap: client->adapter, msgs: msg, ARRAY_SIZE(msg));
1643	if (ret < (int)ARRAY_SIZE(msg)) {
1644	if (ret >= 0)
1645	ret = -EIO;
1646
1647	msleep(IQS7222_COMMS_RETRY_MS);
1648	continue;
1649	}
1650
1651	if (get_unaligned_le16(p: msg[1].buf) == IQS7222_COMMS_ERROR) {
1652	ret = -ENODATA;
1653	continue;
1654	}
1655
1656	ret = 0;
1657	break;
1658	}
1659
1660	/*
1661	* The following delay ensures the device has deasserted the RDY pin
1662	* following the I2C stop condition.
1663	*/
1664	usleep_range(min: 50, max: 100);
1665
1666	if (ret < 0)
1667	dev_err(&client->dev,
1668	"Failed to read from address 0x%04X: %d\n", reg, ret);
1669
1670	return ret;
1671	}
1672
1673	static int iqs7222_read_word(struct iqs7222_private *iqs7222, u16 reg, u16 *val)
1674	{
1675	__le16 val_buf;
1676	int error;
1677
1678	error = iqs7222_read_burst(iqs7222, reg, val: &val_buf, num_val: 1);
1679	if (error)
1680	return error;
1681
1682	*val = le16_to_cpu(val_buf);
1683
1684	return 0;
1685	}
1686
1687	static int iqs7222_write_burst(struct iqs7222_private *iqs7222,
1688	u16 reg, const void *val, u16 num_val)
1689	{
1690	int reg_len = reg > U8_MAX ? sizeof(reg) : sizeof(u8);
1691	int val_len = num_val * sizeof(__le16);
1692	int msg_len = reg_len + val_len;
1693	int ret, i;
1694	struct i2c_client *client = iqs7222->client;
1695	u8 *msg_buf;
1696
1697	msg_buf = kzalloc(size: msg_len, GFP_KERNEL);
1698	if (!msg_buf)
1699	return -ENOMEM;
1700
1701	if (reg > U8_MAX)
1702	put_unaligned_be16(val: reg, p: msg_buf);
1703	else
1704	*msg_buf = (u8)reg;
1705
1706	memcpy(msg_buf + reg_len, val, val_len);
1707
1708	/*
1709	* The following loop protects against an edge case in which the RDY
1710	* pin is automatically asserted just before the force communication
1711	* command is sent.
1712	*
1713	* In that case, the subsequent I2C stop condition tricks the device
1714	* into preemptively deasserting the RDY pin and the command must be
1715	* sent again.
1716	*/
1717	for (i = 0; i < IQS7222_NUM_RETRIES; i++) {
1718	ret = iqs7222_force_comms(iqs7222);
1719	if (ret < 0)
1720	continue;
1721
1722	ret = i2c_master_send(client, buf: msg_buf, count: msg_len);
1723	if (ret < msg_len) {
1724	if (ret >= 0)
1725	ret = -EIO;
1726
1727	msleep(IQS7222_COMMS_RETRY_MS);
1728	continue;
1729	}
1730
1731	ret = 0;
1732	break;
1733	}
1734
1735	kfree(objp: msg_buf);
1736
1737	usleep_range(min: 50, max: 100);
1738
1739	if (ret < 0)
1740	dev_err(&client->dev,
1741	"Failed to write to address 0x%04X: %d\n", reg, ret);
1742
1743	return ret;
1744	}
1745
1746	static int iqs7222_write_word(struct iqs7222_private *iqs7222, u16 reg, u16 val)
1747	{
1748	__le16 val_buf = cpu_to_le16(val);
1749
1750	return iqs7222_write_burst(iqs7222, reg, val: &val_buf, num_val: 1);
1751	}
1752
1753	static int iqs7222_ati_trigger(struct iqs7222_private *iqs7222)
1754	{
1755	struct i2c_client *client = iqs7222->client;
1756	ktime_t ati_timeout;
1757	u16 sys_status = 0;
1758	u16 sys_setup;
1759	int error, i;
1760
1761	/*
1762	* The reserved fields of the system setup register may have changed
1763	* as a result of other registers having been written. As such, read
1764	* the register's latest value to avoid unexpected behavior when the
1765	* register is written in the loop that follows.
1766	*/
1767	error = iqs7222_read_word(iqs7222, IQS7222_SYS_SETUP, val: &sys_setup);
1768	if (error)
1769	return error;
1770
1771	for (i = 0; i < IQS7222_NUM_RETRIES; i++) {
1772	/*
1773	* Trigger ATI from streaming and normal-power modes so that
1774	* the RDY pin continues to be asserted during ATI.
1775	*/
1776	error = iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP,
1777	val: sys_setup |
1778	IQS7222_SYS_SETUP_REDO_ATI);
1779	if (error)
1780	return error;
1781
1782	ati_timeout = ktime_add_ms(kt: ktime_get(), IQS7222_ATI_TIMEOUT_MS);
1783
1784	do {
1785	error = iqs7222_irq_poll(iqs7222,
1786	IQS7222_COMMS_TIMEOUT_MS);
1787	if (error)
1788	continue;
1789
1790	error = iqs7222_read_word(iqs7222, IQS7222_SYS_STATUS,
1791	val: &sys_status);
1792	if (error)
1793	return error;
1794
1795	if (sys_status & IQS7222_SYS_STATUS_RESET)
1796	return 0;
1797
1798	if (sys_status & IQS7222_SYS_STATUS_ATI_ERROR)
1799	break;
1800
1801	if (sys_status & IQS7222_SYS_STATUS_ATI_ACTIVE)
1802	continue;
1803
1804	/*
1805	* Use stream-in-touch mode if either slider reports
1806	* absolute position.
1807	*/
1808	sys_setup |= test_bit(EV_ABS, iqs7222->keypad->evbit)
1809	? IQS7222_SYS_SETUP_INTF_MODE_TOUCH
1810	: IQS7222_SYS_SETUP_INTF_MODE_EVENT;
1811	sys_setup |= IQS7222_SYS_SETUP_PWR_MODE_AUTO;
1812
1813	return iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP,
1814	val: sys_setup);
1815	} while (ktime_compare(cmp1: ktime_get(), cmp2: ati_timeout) < 0);
1816
1817	dev_err(&client->dev,
1818	"ATI attempt %d of %d failed with status 0x%02X, %s\n",
1819	i + 1, IQS7222_NUM_RETRIES, (u8)sys_status,
1820	i + 1 < IQS7222_NUM_RETRIES ? "retrying" : "stopping");
1821	}
1822
1823	return -ETIMEDOUT;
1824	}
1825
1826	static int iqs7222_dev_init(struct iqs7222_private *iqs7222, int dir)
1827	{
1828	const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
1829	int comms_offset = dev_desc->comms_offset;
1830	int error, i, j, k;
1831
1832	/*
1833	* Acknowledge reset before writing any registers in case the device
1834	* suffers a spurious reset during initialization. Because this step
1835	* may change the reserved fields of the second filter beta register,
1836	* its cache must be updated.
1837	*
1838	* Writing the second filter beta register, in turn, may clobber the
1839	* system status register. As such, the filter beta register pair is
1840	* written first to protect against this hazard.
1841	*/
1842	if (dir == WRITE) {
1843	u16 reg = dev_desc->reg_grps[IQS7222_REG_GRP_FILT].base + 1;
1844	u16 filt_setup;
1845
1846	error = iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP,
1847	val: iqs7222->sys_setup[0] |
1848	IQS7222_SYS_SETUP_ACK_RESET);
1849	if (error)
1850	return error;
1851
1852	error = iqs7222_read_word(iqs7222, reg, val: &filt_setup);
1853	if (error)
1854	return error;
1855
1856	iqs7222->filt_setup[1] &= GENMASK(7, 0);
1857	iqs7222->filt_setup[1] |= (filt_setup & ~GENMASK(7, 0));
1858	}
1859
1860	/*
1861	* Take advantage of the stop-bit disable function, if available, to
1862	* save the trouble of having to reopen a communication window after
1863	* each burst read or write.
1864	*/
1865	if (comms_offset) {
1866	u16 comms_setup;
1867
1868	error = iqs7222_read_word(iqs7222,
1869	IQS7222_SYS_SETUP + comms_offset,
1870	val: &comms_setup);
1871	if (error)
1872	return error;
1873
1874	error = iqs7222_write_word(iqs7222,
1875	IQS7222_SYS_SETUP + comms_offset,
1876	val: comms_setup | IQS7222_COMMS_HOLD);
1877	if (error)
1878	return error;
1879	}
1880
1881	for (i = 0; i < IQS7222_NUM_REG_GRPS; i++) {
1882	int num_row = dev_desc->reg_grps[i].num_row;
1883	int num_col = dev_desc->reg_grps[i].num_col;
1884	u16 reg = dev_desc->reg_grps[i].base;
1885	__le16 *val_buf;
1886	u16 *val;
1887
1888	if (!num_col)
1889	continue;
1890
1891	val = iqs7222_setup(iqs7222, reg_grp: i, row: 0);
1892	if (!val)
1893	continue;
1894
1895	val_buf = kcalloc(n: num_col, size: sizeof(__le16), GFP_KERNEL);
1896	if (!val_buf)
1897	return -ENOMEM;
1898
1899	for (j = 0; j < num_row; j++) {
1900	switch (dir) {
1901	case READ:
1902	error = iqs7222_read_burst(iqs7222, reg,
1903	val: val_buf, num_val: num_col);
1904	for (k = 0; k < num_col; k++)
1905	val[k] = le16_to_cpu(val_buf[k]);
1906	break;
1907
1908	case WRITE:
1909	for (k = 0; k < num_col; k++)
1910	val_buf[k] = cpu_to_le16(val[k]);
1911	error = iqs7222_write_burst(iqs7222, reg,
1912	val: val_buf, num_val: num_col);
1913	break;
1914
1915	default:
1916	error = -EINVAL;
1917	}
1918
1919	if (error)
1920	break;
1921
1922	reg += IQS7222_REG_OFFSET;
1923	val += iqs7222_max_cols[i];
1924	}
1925
1926	kfree(objp: val_buf);
1927
1928	if (error)
1929	return error;
1930	}
1931
1932	if (comms_offset) {
1933	u16 comms_setup;
1934
1935	error = iqs7222_read_word(iqs7222,
1936	IQS7222_SYS_SETUP + comms_offset,
1937	val: &comms_setup);
1938	if (error)
1939	return error;
1940
1941	error = iqs7222_write_word(iqs7222,
1942	IQS7222_SYS_SETUP + comms_offset,
1943	val: comms_setup & ~IQS7222_COMMS_HOLD);
1944	if (error)
1945	return error;
1946	}
1947
1948	if (dir == READ) {
1949	iqs7222->sys_setup[0] &= ~IQS7222_SYS_SETUP_INTF_MODE_MASK;
1950	iqs7222->sys_setup[0] &= ~IQS7222_SYS_SETUP_PWR_MODE_MASK;
1951	return 0;
1952	}
1953
1954	return iqs7222_ati_trigger(iqs7222);
1955	}
1956
1957	static int iqs7222_dev_info(struct iqs7222_private *iqs7222)
1958	{
1959	struct i2c_client *client = iqs7222->client;
1960	bool prod_num_valid = false;
1961	__le16 dev_id[3];
1962	int error, i;
1963
1964	error = iqs7222_read_burst(iqs7222, IQS7222_PROD_NUM, val: dev_id,
1965	ARRAY_SIZE(dev_id));
1966	if (error)
1967	return error;
1968
1969	for (i = 0; i < ARRAY_SIZE(iqs7222_devs); i++) {
1970	if (le16_to_cpu(dev_id[0]) != iqs7222_devs[i].prod_num)
1971	continue;
1972
1973	prod_num_valid = true;
1974
1975	if (le16_to_cpu(dev_id[1]) < iqs7222_devs[i].fw_major)
1976	continue;
1977
1978	if (le16_to_cpu(dev_id[2]) < iqs7222_devs[i].fw_minor)
1979	continue;
1980
1981	iqs7222->dev_desc = &iqs7222_devs[i];
1982	return 0;
1983	}
1984
1985	if (prod_num_valid)
1986	dev_err(&client->dev, "Unsupported firmware revision: %u.%u\n",
1987	le16_to_cpu(dev_id[1]), le16_to_cpu(dev_id[2]));
1988	else
1989	dev_err(&client->dev, "Unrecognized product number: %u\n",
1990	le16_to_cpu(dev_id[0]));
1991
1992	return -EINVAL;
1993	}
1994
1995	static int iqs7222_gpio_select(struct iqs7222_private *iqs7222,
1996	struct fwnode_handle *child_node,
1997	int child_enable, u16 child_link)
1998	{
1999	const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2000	struct i2c_client *client = iqs7222->client;
2001	int num_gpio = dev_desc->reg_grps[IQS7222_REG_GRP_GPIO].num_row;
2002	int error, count, i;
2003	unsigned int gpio_sel[ARRAY_SIZE(iqs7222_gpio_links)];
2004
2005	if (!num_gpio)
2006	return 0;
2007
2008	if (!fwnode_property_present(fwnode: child_node, propname: "azoteq,gpio-select"))
2009	return 0;
2010
2011	count = fwnode_property_count_u32(fwnode: child_node, propname: "azoteq,gpio-select");
2012	if (count > num_gpio) {
2013	dev_err(&client->dev, "Invalid number of %s GPIOs\n",
2014	fwnode_get_name(child_node));
2015	return -EINVAL;
2016	} else if (count < 0) {
2017	dev_err(&client->dev, "Failed to count %s GPIOs: %d\n",
2018	fwnode_get_name(child_node), count);
2019	return count;
2020	}
2021
2022	error = fwnode_property_read_u32_array(fwnode: child_node,
2023	propname: "azoteq,gpio-select",
2024	val: gpio_sel, nval: count);
2025	if (error) {
2026	dev_err(&client->dev, "Failed to read %s GPIOs: %d\n",
2027	fwnode_get_name(child_node), error);
2028	return error;
2029	}
2030
2031	for (i = 0; i < count; i++) {
2032	u16 *gpio_setup;
2033
2034	if (gpio_sel[i] >= num_gpio) {
2035	dev_err(&client->dev, "Invalid %s GPIO: %u\n",
2036	fwnode_get_name(child_node), gpio_sel[i]);
2037	return -EINVAL;
2038	}
2039
2040	gpio_setup = iqs7222->gpio_setup[gpio_sel[i]];
2041
2042	if (gpio_setup[2] && child_link != gpio_setup[2]) {
2043	dev_err(&client->dev,
2044	"Conflicting GPIO %u event types\n",
2045	gpio_sel[i]);
2046	return -EINVAL;
2047	}
2048
2049	gpio_setup[0] |= IQS7222_GPIO_SETUP_0_GPIO_EN;
2050	gpio_setup[1] |= child_enable;
2051	gpio_setup[2] = child_link;
2052	}
2053
2054	return 0;
2055	}
2056
2057	static int iqs7222_parse_props(struct iqs7222_private *iqs7222,
2058	struct fwnode_handle *reg_grp_node,
2059	int reg_grp_index,
2060	enum iqs7222_reg_grp_id reg_grp,
2061	enum iqs7222_reg_key_id reg_key)
2062	{
2063	u16 *setup = iqs7222_setup(iqs7222, reg_grp, row: reg_grp_index);
2064	struct i2c_client *client = iqs7222->client;
2065	int i;
2066
2067	if (!setup)
2068	return 0;
2069
2070	for (i = 0; i < ARRAY_SIZE(iqs7222_props); i++) {
2071	const char *name = iqs7222_props[i].name;
2072	int reg_offset = iqs7222_props[i].reg_offset;
2073	int reg_shift = iqs7222_props[i].reg_shift;
2074	int reg_width = iqs7222_props[i].reg_width;
2075	int val_pitch = iqs7222_props[i].val_pitch ? : 1;
2076	int val_min = iqs7222_props[i].val_min;
2077	int val_max = iqs7222_props[i].val_max;
2078	bool invert = iqs7222_props[i].invert;
2079	const char *label = iqs7222_props[i].label ? : name;
2080	unsigned int val;
2081	int error;
2082
2083	if (iqs7222_props[i].reg_grp != reg_grp ||
2084	iqs7222_props[i].reg_key != reg_key)
2085	continue;
2086
2087	/*
2088	* Boolean register fields are one bit wide; they are forcibly
2089	* reset to provide a means to undo changes by a bootloader if
2090	* necessary.
2091	*
2092	* Scalar fields, on the other hand, are left untouched unless
2093	* their corresponding properties are present.
2094	*/
2095	if (reg_width == 1) {
2096	if (invert)
2097	setup[reg_offset] |= BIT(reg_shift);
2098	else
2099	setup[reg_offset] &= ~BIT(reg_shift);
2100	}
2101
2102	if (!fwnode_property_present(fwnode: reg_grp_node, propname: name))
2103	continue;
2104
2105	if (reg_width == 1) {
2106	if (invert)
2107	setup[reg_offset] &= ~BIT(reg_shift);
2108	else
2109	setup[reg_offset] |= BIT(reg_shift);
2110
2111	continue;
2112	}
2113
2114	error = fwnode_property_read_u32(fwnode: reg_grp_node, propname: name, val: &val);
2115	if (error) {
2116	dev_err(&client->dev, "Failed to read %s %s: %d\n",
2117	fwnode_get_name(reg_grp_node), label, error);
2118	return error;
2119	}
2120
2121	if (!val_max)
2122	val_max = GENMASK(reg_width - 1, 0) * val_pitch;
2123
2124	if (val < val_min || val > val_max) {
2125	dev_err(&client->dev, "Invalid %s %s: %u\n",
2126	fwnode_get_name(reg_grp_node), label, val);
2127	return -EINVAL;
2128	}
2129
2130	setup[reg_offset] &= ~GENMASK(reg_shift + reg_width - 1,
2131	reg_shift);
2132	setup[reg_offset] |= (val / val_pitch << reg_shift);
2133	}
2134
2135	return 0;
2136	}
2137
2138	static int iqs7222_parse_event(struct iqs7222_private *iqs7222,
2139	struct fwnode_handle *event_node,
2140	int reg_grp_index,
2141	enum iqs7222_reg_grp_id reg_grp,
2142	enum iqs7222_reg_key_id reg_key,
2143	u16 event_enable, u16 event_link,
2144	unsigned int *event_type,
2145	unsigned int *event_code)
2146	{
2147	struct i2c_client *client = iqs7222->client;
2148	int error;
2149
2150	error = iqs7222_parse_props(iqs7222, reg_grp_node: event_node, reg_grp_index,
2151	reg_grp, reg_key);
2152	if (error)
2153	return error;
2154
2155	error = iqs7222_gpio_select(iqs7222, child_node: event_node, child_enable: event_enable,
2156	child_link: event_link);
2157	if (error)
2158	return error;
2159
2160	error = fwnode_property_read_u32(fwnode: event_node, propname: "linux,code", val: event_code);
2161	if (error == -EINVAL) {
2162	return 0;
2163	} else if (error) {
2164	dev_err(&client->dev, "Failed to read %s code: %d\n",
2165	fwnode_get_name(event_node), error);
2166	return error;
2167	}
2168
2169	if (!event_type) {
2170	input_set_capability(dev: iqs7222->keypad, EV_KEY, code: *event_code);
2171	return 0;
2172	}
2173
2174	error = fwnode_property_read_u32(fwnode: event_node, propname: "linux,input-type",
2175	val: event_type);
2176	if (error == -EINVAL) {
2177	*event_type = EV_KEY;
2178	} else if (error) {
2179	dev_err(&client->dev, "Failed to read %s input type: %d\n",
2180	fwnode_get_name(event_node), error);
2181	return error;
2182	} else if (*event_type != EV_KEY && *event_type != EV_SW) {
2183	dev_err(&client->dev, "Invalid %s input type: %d\n",
2184	fwnode_get_name(event_node), *event_type);
2185	return -EINVAL;
2186	}
2187
2188	input_set_capability(dev: iqs7222->keypad, type: *event_type, code: *event_code);
2189
2190	return 0;
2191	}
2192
2193	static int iqs7222_parse_cycle(struct iqs7222_private *iqs7222,
2194	struct fwnode_handle *cycle_node, int cycle_index)
2195	{
2196	u16 *cycle_setup = iqs7222->cycle_setup[cycle_index];
2197	struct i2c_client *client = iqs7222->client;
2198	unsigned int pins[9];
2199	int error, count, i;
2200
2201	/*
2202	* Each channel shares a cycle with one other channel; the mapping of
2203	* channels to cycles is fixed. Properties defined for a cycle impact
2204	* both channels tied to the cycle.
2205	*
2206	* Unlike channels which are restricted to a select range of CRx pins
2207	* based on channel number, any cycle can claim any of the device's 9
2208	* CTx pins (CTx0-8).
2209	*/
2210	if (!fwnode_property_present(fwnode: cycle_node, propname: "azoteq,tx-enable"))
2211	return 0;
2212
2213	count = fwnode_property_count_u32(fwnode: cycle_node, propname: "azoteq,tx-enable");
2214	if (count < 0) {
2215	dev_err(&client->dev, "Failed to count %s CTx pins: %d\n",
2216	fwnode_get_name(cycle_node), count);
2217	return count;
2218	} else if (count > ARRAY_SIZE(pins)) {
2219	dev_err(&client->dev, "Invalid number of %s CTx pins\n",
2220	fwnode_get_name(cycle_node));
2221	return -EINVAL;
2222	}
2223
2224	error = fwnode_property_read_u32_array(fwnode: cycle_node, propname: "azoteq,tx-enable",
2225	val: pins, nval: count);
2226	if (error) {
2227	dev_err(&client->dev, "Failed to read %s CTx pins: %d\n",
2228	fwnode_get_name(cycle_node), error);
2229	return error;
2230	}
2231
2232	cycle_setup[1] &= ~GENMASK(7 + ARRAY_SIZE(pins) - 1, 7);
2233
2234	for (i = 0; i < count; i++) {
2235	if (pins[i] > 8) {
2236	dev_err(&client->dev, "Invalid %s CTx pin: %u\n",
2237	fwnode_get_name(cycle_node), pins[i]);
2238	return -EINVAL;
2239	}
2240
2241	cycle_setup[1] |= BIT(pins[i] + 7);
2242	}
2243
2244	return 0;
2245	}
2246
2247	static int iqs7222_parse_chan(struct iqs7222_private *iqs7222,
2248	struct fwnode_handle *chan_node, int chan_index)
2249	{
2250	const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2251	struct i2c_client *client = iqs7222->client;
2252	int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row;
2253	int ext_chan = rounddown(num_chan, 10);
2254	int error, i;
2255	u16 *chan_setup = iqs7222->chan_setup[chan_index];
2256	u16 *sys_setup = iqs7222->sys_setup;
2257	unsigned int val;
2258
2259	if (dev_desc->allow_offset &&
2260	fwnode_property_present(fwnode: chan_node, propname: "azoteq,ulp-allow"))
2261	sys_setup[dev_desc->allow_offset] &= ~BIT(chan_index);
2262
2263	chan_setup[0] |= IQS7222_CHAN_SETUP_0_CHAN_EN;
2264
2265	/*
2266	* The reference channel function allows for differential measurements
2267	* and is only available in the case of IQS7222A or IQS7222C.
2268	*/
2269	if (dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_col > 4 &&
2270	fwnode_property_present(fwnode: chan_node, propname: "azoteq,ref-select")) {
2271	u16 *ref_setup;
2272
2273	error = fwnode_property_read_u32(fwnode: chan_node, propname: "azoteq,ref-select",
2274	val: &val);
2275	if (error) {
2276	dev_err(&client->dev,
2277	"Failed to read %s reference channel: %d\n",
2278	fwnode_get_name(chan_node), error);
2279	return error;
2280	}
2281
2282	if (val >= ext_chan) {
2283	dev_err(&client->dev,
2284	"Invalid %s reference channel: %u\n",
2285	fwnode_get_name(chan_node), val);
2286	return -EINVAL;
2287	}
2288
2289	ref_setup = iqs7222->chan_setup[val];
2290
2291	/*
2292	* Configure the current channel as a follower of the selected
2293	* reference channel.
2294	*/
2295	chan_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_FOLLOW;
2296	chan_setup[4] = val * 42 + 1048;
2297
2298	error = fwnode_property_read_u32(fwnode: chan_node, propname: "azoteq,ref-weight",
2299	val: &val);
2300	if (!error) {
2301	if (val > U16_MAX) {
2302	dev_err(&client->dev,
2303	"Invalid %s reference weight: %u\n",
2304	fwnode_get_name(chan_node), val);
2305	return -EINVAL;
2306	}
2307
2308	chan_setup[5] = val;
2309	} else if (error != -EINVAL) {
2310	dev_err(&client->dev,
2311	"Failed to read %s reference weight: %d\n",
2312	fwnode_get_name(chan_node), error);
2313	return error;
2314	}
2315
2316	/*
2317	* Configure the selected channel as a reference channel which
2318	* serves the current channel.
2319	*/
2320	ref_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_REF;
2321	ref_setup[5] |= BIT(chan_index);
2322
2323	ref_setup[4] = dev_desc->touch_link;
2324	if (fwnode_property_present(fwnode: chan_node, propname: "azoteq,use-prox"))
2325	ref_setup[4] -= 2;
2326	} else if (dev_desc->reg_grps[IQS7222_REG_GRP_TPAD].num_row &&
2327	fwnode_property_present(fwnode: chan_node,
2328	propname: "azoteq,counts-filt-enable")) {
2329	/*
2330	* In the case of IQS7222D, however, the reference mode field
2331	* is partially repurposed as a counts filter enable control.
2332	*/
2333	chan_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_REF;
2334	}
2335
2336	if (fwnode_property_present(fwnode: chan_node, propname: "azoteq,rx-enable")) {
2337	/*
2338	* Each channel can claim up to 4 CRx pins. The first half of
2339	* the channels can use CRx0-3, while the second half can use
2340	* CRx4-7.
2341	*/
2342	unsigned int pins[4];
2343	int count;
2344
2345	count = fwnode_property_count_u32(fwnode: chan_node,
2346	propname: "azoteq,rx-enable");
2347	if (count < 0) {
2348	dev_err(&client->dev,
2349	"Failed to count %s CRx pins: %d\n",
2350	fwnode_get_name(chan_node), count);
2351	return count;
2352	} else if (count > ARRAY_SIZE(pins)) {
2353	dev_err(&client->dev,
2354	"Invalid number of %s CRx pins\n",
2355	fwnode_get_name(chan_node));
2356	return -EINVAL;
2357	}
2358
2359	error = fwnode_property_read_u32_array(fwnode: chan_node,
2360	propname: "azoteq,rx-enable",
2361	val: pins, nval: count);
2362	if (error) {
2363	dev_err(&client->dev,
2364	"Failed to read %s CRx pins: %d\n",
2365	fwnode_get_name(chan_node), error);
2366	return error;
2367	}
2368
2369	chan_setup[0] &= ~GENMASK(4 + ARRAY_SIZE(pins) - 1, 4);
2370
2371	for (i = 0; i < count; i++) {
2372	int min_crx = chan_index < ext_chan / 2 ? 0 : 4;
2373
2374	if (pins[i] < min_crx || pins[i] > min_crx + 3) {
2375	dev_err(&client->dev,
2376	"Invalid %s CRx pin: %u\n",
2377	fwnode_get_name(chan_node), pins[i]);
2378	return -EINVAL;
2379	}
2380
2381	chan_setup[0] |= BIT(pins[i] + 4 - min_crx);
2382	}
2383	}
2384
2385	for (i = 0; i < ARRAY_SIZE(iqs7222_kp_events); i++) {
2386	const char *event_name = iqs7222_kp_events[i].name;
2387	u16 event_enable = iqs7222_kp_events[i].enable;
2388	struct fwnode_handle *event_node;
2389
2390	event_node = fwnode_get_named_child_node(fwnode: chan_node, childname: event_name);
2391	if (!event_node)
2392	continue;
2393
2394	error = fwnode_property_read_u32(fwnode: event_node,
2395	propname: "azoteq,timeout-press-ms",
2396	val: &val);
2397	if (!error) {
2398	/*
2399	* The IQS7222B employs a global pair of press timeout
2400	* registers as opposed to channel-specific registers.
2401	*/
2402	u16 *setup = dev_desc->reg_grps
2403	[IQS7222_REG_GRP_BTN].num_col > 2 ?
2404	&iqs7222->btn_setup[chan_index][2] :
2405	&sys_setup[9];
2406
2407	if (val > U8_MAX * 500) {
2408	dev_err(&client->dev,
2409	"Invalid %s press timeout: %u\n",
2410	fwnode_get_name(event_node), val);
2411	fwnode_handle_put(fwnode: event_node);
2412	return -EINVAL;
2413	}
2414
2415	*setup &= ~(U8_MAX << i * 8);
2416	*setup |= (val / 500 << i * 8);
2417	} else if (error != -EINVAL) {
2418	dev_err(&client->dev,
2419	"Failed to read %s press timeout: %d\n",
2420	fwnode_get_name(event_node), error);
2421	fwnode_handle_put(fwnode: event_node);
2422	return error;
2423	}
2424
2425	error = iqs7222_parse_event(iqs7222, event_node, reg_grp_index: chan_index,
2426	reg_grp: IQS7222_REG_GRP_BTN,
2427	reg_key: iqs7222_kp_events[i].reg_key,
2428	BIT(chan_index),
2429	event_link: dev_desc->touch_link - (i ? 0 : 2),
2430	event_type: &iqs7222->kp_type[chan_index][i],
2431	event_code: &iqs7222->kp_code[chan_index][i]);
2432	fwnode_handle_put(fwnode: event_node);
2433	if (error)
2434	return error;
2435
2436	if (!dev_desc->event_offset)
2437	continue;
2438
2439	sys_setup[dev_desc->event_offset] |= event_enable;
2440	}
2441
2442	/*
2443	* The following call handles a special pair of properties that apply
2444	* to a channel node, but reside within the button (event) group.
2445	*/
2446	return iqs7222_parse_props(iqs7222, reg_grp_node: chan_node, reg_grp_index: chan_index,
2447	reg_grp: IQS7222_REG_GRP_BTN,
2448	reg_key: IQS7222_REG_KEY_DEBOUNCE);
2449	}
2450
2451	static int iqs7222_parse_sldr(struct iqs7222_private *iqs7222,
2452	struct fwnode_handle *sldr_node, int sldr_index)
2453	{
2454	const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2455	struct i2c_client *client = iqs7222->client;
2456	int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row;
2457	int ext_chan = rounddown(num_chan, 10);
2458	int count, error, reg_offset, i;
2459	u16 *event_mask = &iqs7222->sys_setup[dev_desc->event_offset];
2460	u16 *sldr_setup = iqs7222->sldr_setup[sldr_index];
2461	unsigned int chan_sel[4], val;
2462
2463	/*
2464	* Each slider can be spread across 3 to 4 channels. It is possible to
2465	* select only 2 channels, but doing so prevents the slider from using
2466	* the specified resolution.
2467	*/
2468	count = fwnode_property_count_u32(fwnode: sldr_node, propname: "azoteq,channel-select");
2469	if (count < 0) {
2470	dev_err(&client->dev, "Failed to count %s channels: %d\n",
2471	fwnode_get_name(sldr_node), count);
2472	return count;
2473	} else if (count < 3 || count > ARRAY_SIZE(chan_sel)) {
2474	dev_err(&client->dev, "Invalid number of %s channels\n",
2475	fwnode_get_name(sldr_node));
2476	return -EINVAL;
2477	}
2478
2479	error = fwnode_property_read_u32_array(fwnode: sldr_node,
2480	propname: "azoteq,channel-select",
2481	val: chan_sel, nval: count);
2482	if (error) {
2483	dev_err(&client->dev, "Failed to read %s channels: %d\n",
2484	fwnode_get_name(sldr_node), error);
2485	return error;
2486	}
2487
2488	/*
2489	* Resolution and top speed, if small enough, are packed into a single
2490	* register. Otherwise, each occupies its own register and the rest of
2491	* the slider-related register addresses are offset by one.
2492	*/
2493	reg_offset = dev_desc->sldr_res < U16_MAX ? 0 : 1;
2494
2495	sldr_setup[0] |= count;
2496	sldr_setup[3 + reg_offset] &= ~GENMASK(ext_chan - 1, 0);
2497
2498	for (i = 0; i < ARRAY_SIZE(chan_sel); i++) {
2499	sldr_setup[5 + reg_offset + i] = 0;
2500	if (i >= count)
2501	continue;
2502
2503	if (chan_sel[i] >= ext_chan) {
2504	dev_err(&client->dev, "Invalid %s channel: %u\n",
2505	fwnode_get_name(sldr_node), chan_sel[i]);
2506	return -EINVAL;
2507	}
2508
2509	/*
2510	* The following fields indicate which channels participate in
2511	* the slider, as well as each channel's relative placement.
2512	*/
2513	sldr_setup[3 + reg_offset] |= BIT(chan_sel[i]);
2514	sldr_setup[5 + reg_offset + i] = chan_sel[i] * 42 + 1080;
2515	}
2516
2517	sldr_setup[4 + reg_offset] = dev_desc->touch_link;
2518	if (fwnode_property_present(fwnode: sldr_node, propname: "azoteq,use-prox"))
2519	sldr_setup[4 + reg_offset] -= 2;
2520
2521	error = fwnode_property_read_u32(fwnode: sldr_node, propname: "azoteq,slider-size", val: &val);
2522	if (!error) {
2523	if (val > dev_desc->sldr_res) {
2524	dev_err(&client->dev, "Invalid %s size: %u\n",
2525	fwnode_get_name(sldr_node), val);
2526	return -EINVAL;
2527	}
2528
2529	if (reg_offset) {
2530	sldr_setup[3] = val;
2531	} else {
2532	sldr_setup[2] &= ~IQS7222_SLDR_SETUP_2_RES_MASK;
2533	sldr_setup[2] |= (val / 16 <<
2534	IQS7222_SLDR_SETUP_2_RES_SHIFT);
2535	}
2536	} else if (error != -EINVAL) {
2537	dev_err(&client->dev, "Failed to read %s size: %d\n",
2538	fwnode_get_name(sldr_node), error);
2539	return error;
2540	}
2541
2542	if (!(reg_offset ? sldr_setup[3]
2543	: sldr_setup[2] & IQS7222_SLDR_SETUP_2_RES_MASK)) {
2544	dev_err(&client->dev, "Undefined %s size\n",
2545	fwnode_get_name(sldr_node));
2546	return -EINVAL;
2547	}
2548
2549	error = fwnode_property_read_u32(fwnode: sldr_node, propname: "azoteq,top-speed", val: &val);
2550	if (!error) {
2551	if (val > (reg_offset ? U16_MAX : U8_MAX * 4)) {
2552	dev_err(&client->dev, "Invalid %s top speed: %u\n",
2553	fwnode_get_name(sldr_node), val);
2554	return -EINVAL;
2555	}
2556
2557	if (reg_offset) {
2558	sldr_setup[2] = val;
2559	} else {
2560	sldr_setup[2] &= ~IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK;
2561	sldr_setup[2] |= (val / 4);
2562	}
2563	} else if (error != -EINVAL) {
2564	dev_err(&client->dev, "Failed to read %s top speed: %d\n",
2565	fwnode_get_name(sldr_node), error);
2566	return error;
2567	}
2568
2569	error = fwnode_property_read_u32(fwnode: sldr_node, propname: "linux,axis", val: &val);
2570	if (!error) {
2571	u16 sldr_max = sldr_setup[3] - 1;
2572
2573	if (!reg_offset) {
2574	sldr_max = sldr_setup[2];
2575
2576	sldr_max &= IQS7222_SLDR_SETUP_2_RES_MASK;
2577	sldr_max >>= IQS7222_SLDR_SETUP_2_RES_SHIFT;
2578
2579	sldr_max = sldr_max * 16 - 1;
2580	}
2581
2582	input_set_abs_params(dev: iqs7222->keypad, axis: val, min: 0, max: sldr_max, fuzz: 0, flat: 0);
2583	iqs7222->sl_axis[sldr_index] = val;
2584	} else if (error != -EINVAL) {
2585	dev_err(&client->dev, "Failed to read %s axis: %d\n",
2586	fwnode_get_name(sldr_node), error);
2587	return error;
2588	}
2589
2590	if (dev_desc->wheel_enable) {
2591	sldr_setup[0] &= ~dev_desc->wheel_enable;
2592	if (iqs7222->sl_axis[sldr_index] == ABS_WHEEL)
2593	sldr_setup[0] |= dev_desc->wheel_enable;
2594	}
2595
2596	/*
2597	* The absence of a register offset makes it safe to assume the device
2598	* supports gestures, each of which is first disabled until explicitly
2599	* enabled.
2600	*/
2601	if (!reg_offset)
2602	for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++)
2603	sldr_setup[9] &= ~iqs7222_sl_events[i].enable;
2604
2605	for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++) {
2606	const char *event_name = iqs7222_sl_events[i].name;
2607	struct fwnode_handle *event_node;
2608	enum iqs7222_reg_key_id reg_key;
2609
2610	event_node = fwnode_get_named_child_node(fwnode: sldr_node, childname: event_name);
2611	if (!event_node)
2612	continue;
2613
2614	/*
2615	* Depending on the device, gestures are either offered using
2616	* one of two timing resolutions, or are not supported at all.
2617	*/
2618	if (reg_offset)
2619	reg_key = IQS7222_REG_KEY_RESERVED;
2620	else if (dev_desc->legacy_gesture &&
2621	iqs7222_sl_events[i].reg_key == IQS7222_REG_KEY_TAP)
2622	reg_key = IQS7222_REG_KEY_TAP_LEGACY;
2623	else if (dev_desc->legacy_gesture &&
2624	iqs7222_sl_events[i].reg_key == IQS7222_REG_KEY_AXIAL)
2625	reg_key = IQS7222_REG_KEY_AXIAL_LEGACY;
2626	else
2627	reg_key = iqs7222_sl_events[i].reg_key;
2628
2629	/*
2630	* The press/release event does not expose a direct GPIO link,
2631	* but one can be emulated by tying each of the participating
2632	* channels to the same GPIO.
2633	*/
2634	error = iqs7222_parse_event(iqs7222, event_node, reg_grp_index: sldr_index,
2635	reg_grp: IQS7222_REG_GRP_SLDR, reg_key,
2636	event_enable: i ? iqs7222_sl_events[i].enable
2637	: sldr_setup[3 + reg_offset],
2638	event_link: i ? 1568 + sldr_index * 30
2639	: sldr_setup[4 + reg_offset],
2640	NULL,
2641	event_code: &iqs7222->sl_code[sldr_index][i]);
2642	fwnode_handle_put(fwnode: event_node);
2643	if (error)
2644	return error;
2645
2646	if (!reg_offset)
2647	sldr_setup[9] |= iqs7222_sl_events[i].enable;
2648
2649	if (!dev_desc->event_offset)
2650	continue;
2651
2652	/*
2653	* The press/release event is determined based on whether the
2654	* coordinate field reports 0xFFFF and solely relies on touch
2655	* or proximity interrupts to be unmasked.
2656	*/
2657	if (i && !reg_offset)
2658	*event_mask |= (IQS7222_EVENT_MASK_SLDR << sldr_index);
2659	else if (sldr_setup[4 + reg_offset] == dev_desc->touch_link)
2660	*event_mask |= IQS7222_EVENT_MASK_TOUCH;
2661	else
2662	*event_mask |= IQS7222_EVENT_MASK_PROX;
2663	}
2664
2665	/*
2666	* The following call handles a special pair of properties that shift
2667	* to make room for a wheel enable control in the case of IQS7222C.
2668	*/
2669	return iqs7222_parse_props(iqs7222, reg_grp_node: sldr_node, reg_grp_index: sldr_index,
2670	reg_grp: IQS7222_REG_GRP_SLDR,
2671	reg_key: dev_desc->wheel_enable ?
2672	IQS7222_REG_KEY_WHEEL :
2673	IQS7222_REG_KEY_NO_WHEEL);
2674	}
2675
2676	static int iqs7222_parse_tpad(struct iqs7222_private *iqs7222,
2677	struct fwnode_handle *tpad_node, int tpad_index)
2678	{
2679	const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2680	struct touchscreen_properties *prop = &iqs7222->prop;
2681	struct i2c_client *client = iqs7222->client;
2682	int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row;
2683	int count, error, i;
2684	u16 *event_mask = &iqs7222->sys_setup[dev_desc->event_offset];
2685	u16 *tpad_setup = iqs7222->tpad_setup;
2686	unsigned int chan_sel[12];
2687
2688	error = iqs7222_parse_props(iqs7222, reg_grp_node: tpad_node, reg_grp_index: tpad_index,
2689	reg_grp: IQS7222_REG_GRP_TPAD,
2690	reg_key: IQS7222_REG_KEY_NONE);
2691	if (error)
2692	return error;
2693
2694	count = fwnode_property_count_u32(fwnode: tpad_node, propname: "azoteq,channel-select");
2695	if (count < 0) {
2696	dev_err(&client->dev, "Failed to count %s channels: %d\n",
2697	fwnode_get_name(tpad_node), count);
2698	return count;
2699	} else if (!count || count > ARRAY_SIZE(chan_sel)) {
2700	dev_err(&client->dev, "Invalid number of %s channels\n",
2701	fwnode_get_name(tpad_node));
2702	return -EINVAL;
2703	}
2704
2705	error = fwnode_property_read_u32_array(fwnode: tpad_node,
2706	propname: "azoteq,channel-select",
2707	val: chan_sel, nval: count);
2708	if (error) {
2709	dev_err(&client->dev, "Failed to read %s channels: %d\n",
2710	fwnode_get_name(tpad_node), error);
2711	return error;
2712	}
2713
2714	tpad_setup[6] &= ~GENMASK(num_chan - 1, 0);
2715
2716	for (i = 0; i < ARRAY_SIZE(chan_sel); i++) {
2717	tpad_setup[8 + i] = 0;
2718	if (i >= count || chan_sel[i] == U8_MAX)
2719	continue;
2720
2721	if (chan_sel[i] >= num_chan) {
2722	dev_err(&client->dev, "Invalid %s channel: %u\n",
2723	fwnode_get_name(tpad_node), chan_sel[i]);
2724	return -EINVAL;
2725	}
2726
2727	/*
2728	* The following fields indicate which channels participate in
2729	* the trackpad, as well as each channel's relative placement.
2730	*/
2731	tpad_setup[6] |= BIT(chan_sel[i]);
2732	tpad_setup[8 + i] = chan_sel[i] * 34 + 1072;
2733	}
2734
2735	tpad_setup[7] = dev_desc->touch_link;
2736	if (fwnode_property_present(fwnode: tpad_node, propname: "azoteq,use-prox"))
2737	tpad_setup[7] -= 2;
2738
2739	for (i = 0; i < ARRAY_SIZE(iqs7222_tp_events); i++)
2740	tpad_setup[20] &= ~(iqs7222_tp_events[i].strict |
2741	iqs7222_tp_events[i].enable);
2742
2743	for (i = 0; i < ARRAY_SIZE(iqs7222_tp_events); i++) {
2744	const char *event_name = iqs7222_tp_events[i].name;
2745	struct fwnode_handle *event_node;
2746
2747	event_node = fwnode_get_named_child_node(fwnode: tpad_node, childname: event_name);
2748	if (!event_node)
2749	continue;
2750
2751	if (fwnode_property_present(fwnode: event_node,
2752	propname: "azoteq,gesture-angle-tighten"))
2753	tpad_setup[20] |= iqs7222_tp_events[i].strict;
2754
2755	tpad_setup[20] |= iqs7222_tp_events[i].enable;
2756
2757	error = iqs7222_parse_event(iqs7222, event_node, reg_grp_index: tpad_index,
2758	reg_grp: IQS7222_REG_GRP_TPAD,
2759	reg_key: iqs7222_tp_events[i].reg_key,
2760	event_enable: iqs7222_tp_events[i].link, event_link: 1566,
2761	NULL,
2762	event_code: &iqs7222->tp_code[i]);
2763	fwnode_handle_put(fwnode: event_node);
2764	if (error)
2765	return error;
2766
2767	if (!dev_desc->event_offset)
2768	continue;
2769
2770	/*
2771	* The press/release event is determined based on whether the
2772	* coordinate fields report 0xFFFF and solely relies on touch
2773	* or proximity interrupts to be unmasked.
2774	*/
2775	if (i)
2776	*event_mask |= IQS7222_EVENT_MASK_TPAD;
2777	else if (tpad_setup[7] == dev_desc->touch_link)
2778	*event_mask |= IQS7222_EVENT_MASK_TOUCH;
2779	else
2780	*event_mask |= IQS7222_EVENT_MASK_PROX;
2781	}
2782
2783	if (!iqs7222->tp_code[0])
2784	return 0;
2785
2786	input_set_abs_params(dev: iqs7222->keypad, ABS_X,
2787	min: 0, max: (tpad_setup[4] ? : 1) - 1, fuzz: 0, flat: 0);
2788
2789	input_set_abs_params(dev: iqs7222->keypad, ABS_Y,
2790	min: 0, max: (tpad_setup[5] ? : 1) - 1, fuzz: 0, flat: 0);
2791
2792	touchscreen_parse_properties(input: iqs7222->keypad, multitouch: false, prop);
2793
2794	if (prop->max_x >= U16_MAX || prop->max_y >= U16_MAX) {
2795	dev_err(&client->dev, "Invalid trackpad size: %u*%u\n",
2796	prop->max_x, prop->max_y);
2797	return -EINVAL;
2798	}
2799
2800	tpad_setup[4] = prop->max_x + 1;
2801	tpad_setup[5] = prop->max_y + 1;
2802
2803	return 0;
2804	}
2805
2806	static int (*iqs7222_parse_extra[IQS7222_NUM_REG_GRPS])
2807	(struct iqs7222_private *iqs7222,
2808	struct fwnode_handle *reg_grp_node,
2809	int reg_grp_index) = {
2810	[IQS7222_REG_GRP_CYCLE] = iqs7222_parse_cycle,
2811	[IQS7222_REG_GRP_CHAN] = iqs7222_parse_chan,
2812	[IQS7222_REG_GRP_SLDR] = iqs7222_parse_sldr,
2813	[IQS7222_REG_GRP_TPAD] = iqs7222_parse_tpad,
2814	};
2815
2816	static int iqs7222_parse_reg_grp(struct iqs7222_private *iqs7222,
2817	enum iqs7222_reg_grp_id reg_grp,
2818	int reg_grp_index)
2819	{
2820	struct i2c_client *client = iqs7222->client;
2821	struct fwnode_handle *reg_grp_node;
2822	int error;
2823
2824	if (iqs7222_reg_grp_names[reg_grp]) {
2825	char reg_grp_name[16];
2826
2827	snprintf(buf: reg_grp_name, size: sizeof(reg_grp_name),
2828	fmt: iqs7222_reg_grp_names[reg_grp], reg_grp_index);
2829
2830	reg_grp_node = device_get_named_child_node(dev: &client->dev,
2831	childname: reg_grp_name);
2832	} else {
2833	reg_grp_node = fwnode_handle_get(dev_fwnode(&client->dev));
2834	}
2835
2836	if (!reg_grp_node)
2837	return 0;
2838
2839	error = iqs7222_parse_props(iqs7222, reg_grp_node, reg_grp_index,
2840	reg_grp, reg_key: IQS7222_REG_KEY_NONE);
2841
2842	if (!error && iqs7222_parse_extra[reg_grp])
2843	error = iqs7222_parse_extra[reg_grp](iqs7222, reg_grp_node,
2844	reg_grp_index);
2845
2846	fwnode_handle_put(fwnode: reg_grp_node);
2847
2848	return error;
2849	}
2850
2851	static int iqs7222_parse_all(struct iqs7222_private *iqs7222)
2852	{
2853	const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2854	const struct iqs7222_reg_grp_desc *reg_grps = dev_desc->reg_grps;
2855	u16 *sys_setup = iqs7222->sys_setup;
2856	int error, i, j;
2857
2858	if (dev_desc->allow_offset)
2859	sys_setup[dev_desc->allow_offset] = U16_MAX;
2860
2861	if (dev_desc->event_offset)
2862	sys_setup[dev_desc->event_offset] = IQS7222_EVENT_MASK_ATI;
2863
2864	for (i = 0; i < reg_grps[IQS7222_REG_GRP_GPIO].num_row; i++) {
2865	u16 *gpio_setup = iqs7222->gpio_setup[i];
2866
2867	gpio_setup[0] &= ~IQS7222_GPIO_SETUP_0_GPIO_EN;
2868	gpio_setup[1] = 0;
2869	gpio_setup[2] = 0;
2870
2871	if (reg_grps[IQS7222_REG_GRP_GPIO].num_row == 1)
2872	continue;
2873
2874	/*
2875	* The IQS7222C and IQS7222D expose multiple GPIO and must be
2876	* informed as to which GPIO this group represents.
2877	*/
2878	for (j = 0; j < ARRAY_SIZE(iqs7222_gpio_links); j++)
2879	gpio_setup[0] &= ~BIT(iqs7222_gpio_links[j]);
2880
2881	gpio_setup[0] |= BIT(iqs7222_gpio_links[i]);
2882	}
2883
2884	for (i = 0; i < reg_grps[IQS7222_REG_GRP_CHAN].num_row; i++) {
2885	u16 *chan_setup = iqs7222->chan_setup[i];
2886
2887	chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_REF_MODE_MASK;
2888	chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_CHAN_EN;
2889
2890	chan_setup[5] = 0;
2891	}
2892
2893	for (i = 0; i < reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) {
2894	u16 *sldr_setup = iqs7222->sldr_setup[i];
2895
2896	sldr_setup[0] &= ~IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK;
2897	}
2898
2899	for (i = 0; i < IQS7222_NUM_REG_GRPS; i++) {
2900	for (j = 0; j < reg_grps[i].num_row; j++) {
2901	error = iqs7222_parse_reg_grp(iqs7222, reg_grp: i, reg_grp_index: j);
2902	if (error)
2903	return error;
2904	}
2905	}
2906
2907	return 0;
2908	}
2909
2910	static int iqs7222_report(struct iqs7222_private *iqs7222)
2911	{
2912	const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2913	struct i2c_client *client = iqs7222->client;
2914	int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row;
2915	int num_stat = dev_desc->reg_grps[IQS7222_REG_GRP_STAT].num_col;
2916	int error, i, j;
2917	__le16 status[IQS7222_MAX_COLS_STAT];
2918
2919	error = iqs7222_read_burst(iqs7222, IQS7222_SYS_STATUS, val: status,
2920	num_val: num_stat);
2921	if (error)
2922	return error;
2923
2924	if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_RESET) {
2925	dev_err(&client->dev, "Unexpected device reset\n");
2926	return iqs7222_dev_init(iqs7222, WRITE);
2927	}
2928
2929	if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ERROR) {
2930	dev_err(&client->dev, "Unexpected ATI error\n");
2931	return iqs7222_ati_trigger(iqs7222);
2932	}
2933
2934	if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ACTIVE)
2935	return 0;
2936
2937	for (i = 0; i < num_chan; i++) {
2938	u16 *chan_setup = iqs7222->chan_setup[i];
2939
2940	if (!(chan_setup[0] & IQS7222_CHAN_SETUP_0_CHAN_EN))
2941	continue;
2942
2943	for (j = 0; j < ARRAY_SIZE(iqs7222_kp_events); j++) {
2944	/*
2945	* Proximity state begins at offset 2 and spills into
2946	* offset 3 for devices with more than 16 channels.
2947	*
2948	* Touch state begins at the first offset immediately
2949	* following proximity state.
2950	*/
2951	int k = 2 + j * (num_chan > 16 ? 2 : 1);
2952	u16 state = le16_to_cpu(status[k + i / 16]);
2953
2954	if (!iqs7222->kp_type[i][j])
2955	continue;
2956
2957	input_event(dev: iqs7222->keypad,
2958	type: iqs7222->kp_type[i][j],
2959	code: iqs7222->kp_code[i][j],
2960	value: !!(state & BIT(i % 16)));
2961	}
2962	}
2963
2964	for (i = 0; i < dev_desc->reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) {
2965	u16 *sldr_setup = iqs7222->sldr_setup[i];
2966	u16 sldr_pos = le16_to_cpu(status[4 + i]);
2967	u16 state = le16_to_cpu(status[6 + i]);
2968
2969	if (!(sldr_setup[0] & IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK))
2970	continue;
2971
2972	if (sldr_pos < dev_desc->sldr_res)
2973	input_report_abs(dev: iqs7222->keypad, code: iqs7222->sl_axis[i],
2974	value: sldr_pos);
2975
2976	input_report_key(dev: iqs7222->keypad, code: iqs7222->sl_code[i][0],
2977	value: sldr_pos < dev_desc->sldr_res);
2978
2979	/*
2980	* A maximum resolution indicates the device does not support
2981	* gestures, in which case the remaining fields are ignored.
2982	*/
2983	if (dev_desc->sldr_res == U16_MAX)
2984	continue;
2985
2986	if (!(le16_to_cpu(status[1]) & IQS7222_EVENT_MASK_SLDR << i))
2987	continue;
2988
2989	/*
2990	* Skip the press/release event, as it does not have separate
2991	* status fields and is handled separately.
2992	*/
2993	for (j = 1; j < ARRAY_SIZE(iqs7222_sl_events); j++) {
2994	u16 mask = iqs7222_sl_events[j].mask;
2995	u16 val = iqs7222_sl_events[j].val;
2996
2997	input_report_key(dev: iqs7222->keypad,
2998	code: iqs7222->sl_code[i][j],
2999	value: (state & mask) == val);
3000	}
3001
3002	input_sync(dev: iqs7222->keypad);
3003
3004	for (j = 1; j < ARRAY_SIZE(iqs7222_sl_events); j++)
3005	input_report_key(dev: iqs7222->keypad,
3006	code: iqs7222->sl_code[i][j], value: 0);
3007	}
3008
3009	for (i = 0; i < dev_desc->reg_grps[IQS7222_REG_GRP_TPAD].num_row; i++) {
3010	u16 tpad_pos_x = le16_to_cpu(status[4]);
3011	u16 tpad_pos_y = le16_to_cpu(status[5]);
3012	u16 state = le16_to_cpu(status[6]);
3013
3014	input_report_key(dev: iqs7222->keypad, code: iqs7222->tp_code[0],
3015	value: tpad_pos_x < U16_MAX);
3016
3017	if (tpad_pos_x < U16_MAX)
3018	touchscreen_report_pos(input: iqs7222->keypad, prop: &iqs7222->prop,
3019	x: tpad_pos_x, y: tpad_pos_y, multitouch: false);
3020
3021	if (!(le16_to_cpu(status[1]) & IQS7222_EVENT_MASK_TPAD))
3022	continue;
3023
3024	/*
3025	* Skip the press/release event, as it does not have separate
3026	* status fields and is handled separately.
3027	*/
3028	for (j = 1; j < ARRAY_SIZE(iqs7222_tp_events); j++) {
3029	u16 mask = iqs7222_tp_events[j].mask;
3030	u16 val = iqs7222_tp_events[j].val;
3031
3032	input_report_key(dev: iqs7222->keypad,
3033	code: iqs7222->tp_code[j],
3034	value: (state & mask) == val);
3035	}
3036
3037	input_sync(dev: iqs7222->keypad);
3038
3039	for (j = 1; j < ARRAY_SIZE(iqs7222_tp_events); j++)
3040	input_report_key(dev: iqs7222->keypad,
3041	code: iqs7222->tp_code[j], value: 0);
3042	}
3043
3044	input_sync(dev: iqs7222->keypad);
3045
3046	return 0;
3047	}
3048
3049	static irqreturn_t iqs7222_irq(int irq, void *context)
3050	{
3051	struct iqs7222_private *iqs7222 = context;
3052
3053	return iqs7222_report(iqs7222) ? IRQ_NONE : IRQ_HANDLED;
3054	}
3055
3056	static int iqs7222_probe(struct i2c_client *client)
3057	{
3058	struct iqs7222_private *iqs7222;
3059	unsigned long irq_flags;
3060	int error, irq;
3061
3062	iqs7222 = devm_kzalloc(dev: &client->dev, size: sizeof(*iqs7222), GFP_KERNEL);
3063	if (!iqs7222)
3064	return -ENOMEM;
3065
3066	i2c_set_clientdata(client, data: iqs7222);
3067	iqs7222->client = client;
3068
3069	iqs7222->keypad = devm_input_allocate_device(&client->dev);
3070	if (!iqs7222->keypad)
3071	return -ENOMEM;
3072
3073	iqs7222->keypad->name = client->name;
3074	iqs7222->keypad->id.bustype = BUS_I2C;
3075
3076	/*
3077	* The RDY pin behaves as an interrupt, but must also be polled ahead
3078	* of unsolicited I2C communication. As such, it is first opened as a
3079	* GPIO and then passed to gpiod_to_irq() to register the interrupt.
3080	*/
3081	iqs7222->irq_gpio = devm_gpiod_get(dev: &client->dev, con_id: "irq", flags: GPIOD_IN);
3082	if (IS_ERR(ptr: iqs7222->irq_gpio)) {
3083	error = PTR_ERR(ptr: iqs7222->irq_gpio);
3084	dev_err(&client->dev, "Failed to request IRQ GPIO: %d\n",
3085	error);
3086	return error;
3087	}
3088
3089	iqs7222->reset_gpio = devm_gpiod_get_optional(dev: &client->dev, con_id: "reset",
3090	flags: GPIOD_OUT_HIGH);
3091	if (IS_ERR(ptr: iqs7222->reset_gpio)) {
3092	error = PTR_ERR(ptr: iqs7222->reset_gpio);
3093	dev_err(&client->dev, "Failed to request reset GPIO: %d\n",
3094	error);
3095	return error;
3096	}
3097
3098	error = iqs7222_hard_reset(iqs7222);
3099	if (error)
3100	return error;
3101
3102	error = iqs7222_dev_info(iqs7222);
3103	if (error)
3104	return error;
3105
3106	error = iqs7222_dev_init(iqs7222, READ);
3107	if (error)
3108	return error;
3109
3110	error = iqs7222_parse_all(iqs7222);
3111	if (error)
3112	return error;
3113
3114	error = iqs7222_dev_init(iqs7222, WRITE);
3115	if (error)
3116	return error;
3117
3118	error = iqs7222_report(iqs7222);
3119	if (error)
3120	return error;
3121
3122	error = input_register_device(iqs7222->keypad);
3123	if (error) {
3124	dev_err(&client->dev, "Failed to register device: %d\n", error);
3125	return error;
3126	}
3127
3128	irq = gpiod_to_irq(desc: iqs7222->irq_gpio);
3129	if (irq < 0)
3130	return irq;
3131
3132	irq_flags = gpiod_is_active_low(desc: iqs7222->irq_gpio) ? IRQF_TRIGGER_LOW
3133	: IRQF_TRIGGER_HIGH;
3134	irq_flags |= IRQF_ONESHOT;
3135
3136	error = devm_request_threaded_irq(dev: &client->dev, irq, NULL, thread_fn: iqs7222_irq,
3137	irqflags: irq_flags, devname: client->name, dev_id: iqs7222);
3138	if (error)
3139	dev_err(&client->dev, "Failed to request IRQ: %d\n", error);
3140
3141	return error;
3142	}
3143
3144	static const struct of_device_id iqs7222_of_match[] = {
3145	{ .compatible = "azoteq,iqs7222a" },
3146	{ .compatible = "azoteq,iqs7222b" },
3147	{ .compatible = "azoteq,iqs7222c" },
3148	{ .compatible = "azoteq,iqs7222d" },
3149	{ }
3150	};
3151	MODULE_DEVICE_TABLE(of, iqs7222_of_match);
3152
3153	static struct i2c_driver iqs7222_i2c_driver = {
3154	.driver = {
3155	.name = "iqs7222",
3156	.of_match_table = iqs7222_of_match,
3157	},
3158	.probe = iqs7222_probe,
3159	};
3160	module_i2c_driver(iqs7222_i2c_driver);
3161
3162	MODULE_AUTHOR("Jeff LaBundy <jeff@labundy.com>");
3163	MODULE_DESCRIPTION("Azoteq IQS7222A/B/C/D Capacitive Touch Controller");
3164	MODULE_LICENSE("GPL");
3165