1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 *
5 */
6
7#include <linux/device.h>
8#include <linux/interconnect.h>
9#include <linux/interconnect-provider.h>
10#include <linux/mod_devicetable.h>
11#include <linux/module.h>
12#include <linux/platform_device.h>
13#include <dt-bindings/interconnect/qcom,sc7180.h>
14
15#include "bcm-voter.h"
16#include "icc-rpmh.h"
17#include "sc7180.h"
18
19static struct qcom_icc_node qhm_a1noc_cfg = {
20 .name = "qhm_a1noc_cfg",
21 .id = SC7180_MASTER_A1NOC_CFG,
22 .channels = 1,
23 .buswidth = 4,
24 .num_links = 1,
25 .links = { SC7180_SLAVE_SERVICE_A1NOC },
26};
27
28static struct qcom_icc_node qhm_qspi = {
29 .name = "qhm_qspi",
30 .id = SC7180_MASTER_QSPI,
31 .channels = 1,
32 .buswidth = 4,
33 .num_links = 1,
34 .links = { SC7180_SLAVE_A1NOC_SNOC },
35};
36
37static struct qcom_icc_node qhm_qup_0 = {
38 .name = "qhm_qup_0",
39 .id = SC7180_MASTER_QUP_0,
40 .channels = 1,
41 .buswidth = 4,
42 .num_links = 1,
43 .links = { SC7180_SLAVE_A1NOC_SNOC },
44};
45
46static struct qcom_icc_node xm_sdc2 = {
47 .name = "xm_sdc2",
48 .id = SC7180_MASTER_SDCC_2,
49 .channels = 1,
50 .buswidth = 8,
51 .num_links = 1,
52 .links = { SC7180_SLAVE_A1NOC_SNOC },
53};
54
55static struct qcom_icc_node xm_emmc = {
56 .name = "xm_emmc",
57 .id = SC7180_MASTER_EMMC,
58 .channels = 1,
59 .buswidth = 8,
60 .num_links = 1,
61 .links = { SC7180_SLAVE_A1NOC_SNOC },
62};
63
64static struct qcom_icc_node xm_ufs_mem = {
65 .name = "xm_ufs_mem",
66 .id = SC7180_MASTER_UFS_MEM,
67 .channels = 1,
68 .buswidth = 8,
69 .num_links = 1,
70 .links = { SC7180_SLAVE_A1NOC_SNOC },
71};
72
73static struct qcom_icc_node qhm_a2noc_cfg = {
74 .name = "qhm_a2noc_cfg",
75 .id = SC7180_MASTER_A2NOC_CFG,
76 .channels = 1,
77 .buswidth = 4,
78 .num_links = 1,
79 .links = { SC7180_SLAVE_SERVICE_A2NOC },
80};
81
82static struct qcom_icc_node qhm_qdss_bam = {
83 .name = "qhm_qdss_bam",
84 .id = SC7180_MASTER_QDSS_BAM,
85 .channels = 1,
86 .buswidth = 4,
87 .num_links = 1,
88 .links = { SC7180_SLAVE_A2NOC_SNOC },
89};
90
91static struct qcom_icc_node qhm_qup_1 = {
92 .name = "qhm_qup_1",
93 .id = SC7180_MASTER_QUP_1,
94 .channels = 1,
95 .buswidth = 4,
96 .num_links = 1,
97 .links = { SC7180_SLAVE_A2NOC_SNOC },
98};
99
100static struct qcom_icc_node qxm_crypto = {
101 .name = "qxm_crypto",
102 .id = SC7180_MASTER_CRYPTO,
103 .channels = 1,
104 .buswidth = 8,
105 .num_links = 1,
106 .links = { SC7180_SLAVE_A2NOC_SNOC },
107};
108
109static struct qcom_icc_node qxm_ipa = {
110 .name = "qxm_ipa",
111 .id = SC7180_MASTER_IPA,
112 .channels = 1,
113 .buswidth = 8,
114 .num_links = 1,
115 .links = { SC7180_SLAVE_A2NOC_SNOC },
116};
117
118static struct qcom_icc_node xm_qdss_etr = {
119 .name = "xm_qdss_etr",
120 .id = SC7180_MASTER_QDSS_ETR,
121 .channels = 1,
122 .buswidth = 8,
123 .num_links = 1,
124 .links = { SC7180_SLAVE_A2NOC_SNOC },
125};
126
127static struct qcom_icc_node qhm_usb3 = {
128 .name = "qhm_usb3",
129 .id = SC7180_MASTER_USB3,
130 .channels = 1,
131 .buswidth = 8,
132 .num_links = 1,
133 .links = { SC7180_SLAVE_A2NOC_SNOC },
134};
135
136static struct qcom_icc_node qxm_camnoc_hf0_uncomp = {
137 .name = "qxm_camnoc_hf0_uncomp",
138 .id = SC7180_MASTER_CAMNOC_HF0_UNCOMP,
139 .channels = 1,
140 .buswidth = 32,
141 .num_links = 1,
142 .links = { SC7180_SLAVE_CAMNOC_UNCOMP },
143};
144
145static struct qcom_icc_node qxm_camnoc_hf1_uncomp = {
146 .name = "qxm_camnoc_hf1_uncomp",
147 .id = SC7180_MASTER_CAMNOC_HF1_UNCOMP,
148 .channels = 1,
149 .buswidth = 32,
150 .num_links = 1,
151 .links = { SC7180_SLAVE_CAMNOC_UNCOMP },
152};
153
154static struct qcom_icc_node qxm_camnoc_sf_uncomp = {
155 .name = "qxm_camnoc_sf_uncomp",
156 .id = SC7180_MASTER_CAMNOC_SF_UNCOMP,
157 .channels = 1,
158 .buswidth = 32,
159 .num_links = 1,
160 .links = { SC7180_SLAVE_CAMNOC_UNCOMP },
161};
162
163static struct qcom_icc_node qnm_npu = {
164 .name = "qnm_npu",
165 .id = SC7180_MASTER_NPU,
166 .channels = 2,
167 .buswidth = 32,
168 .num_links = 1,
169 .links = { SC7180_SLAVE_CDSP_GEM_NOC },
170};
171
172static struct qcom_icc_node qxm_npu_dsp = {
173 .name = "qxm_npu_dsp",
174 .id = SC7180_MASTER_NPU_PROC,
175 .channels = 1,
176 .buswidth = 8,
177 .num_links = 1,
178 .links = { SC7180_SLAVE_CDSP_GEM_NOC },
179};
180
181static struct qcom_icc_node qnm_snoc = {
182 .name = "qnm_snoc",
183 .id = SC7180_MASTER_SNOC_CNOC,
184 .channels = 1,
185 .buswidth = 8,
186 .num_links = 51,
187 .links = { SC7180_SLAVE_A1NOC_CFG,
188 SC7180_SLAVE_A2NOC_CFG,
189 SC7180_SLAVE_AHB2PHY_SOUTH,
190 SC7180_SLAVE_AHB2PHY_CENTER,
191 SC7180_SLAVE_AOP,
192 SC7180_SLAVE_AOSS,
193 SC7180_SLAVE_BOOT_ROM,
194 SC7180_SLAVE_CAMERA_CFG,
195 SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG,
196 SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG,
197 SC7180_SLAVE_CLK_CTL,
198 SC7180_SLAVE_RBCPR_CX_CFG,
199 SC7180_SLAVE_RBCPR_MX_CFG,
200 SC7180_SLAVE_CRYPTO_0_CFG,
201 SC7180_SLAVE_DCC_CFG,
202 SC7180_SLAVE_CNOC_DDRSS,
203 SC7180_SLAVE_DISPLAY_CFG,
204 SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG,
205 SC7180_SLAVE_DISPLAY_THROTTLE_CFG,
206 SC7180_SLAVE_EMMC_CFG,
207 SC7180_SLAVE_GLM,
208 SC7180_SLAVE_GFX3D_CFG,
209 SC7180_SLAVE_IMEM_CFG,
210 SC7180_SLAVE_IPA_CFG,
211 SC7180_SLAVE_CNOC_MNOC_CFG,
212 SC7180_SLAVE_CNOC_MSS,
213 SC7180_SLAVE_NPU_CFG,
214 SC7180_SLAVE_NPU_DMA_BWMON_CFG,
215 SC7180_SLAVE_NPU_PROC_BWMON_CFG,
216 SC7180_SLAVE_PDM,
217 SC7180_SLAVE_PIMEM_CFG,
218 SC7180_SLAVE_PRNG,
219 SC7180_SLAVE_QDSS_CFG,
220 SC7180_SLAVE_QM_CFG,
221 SC7180_SLAVE_QM_MPU_CFG,
222 SC7180_SLAVE_QSPI_0,
223 SC7180_SLAVE_QUP_0,
224 SC7180_SLAVE_QUP_1,
225 SC7180_SLAVE_SDCC_2,
226 SC7180_SLAVE_SECURITY,
227 SC7180_SLAVE_SNOC_CFG,
228 SC7180_SLAVE_TCSR,
229 SC7180_SLAVE_TLMM_WEST,
230 SC7180_SLAVE_TLMM_NORTH,
231 SC7180_SLAVE_TLMM_SOUTH,
232 SC7180_SLAVE_UFS_MEM_CFG,
233 SC7180_SLAVE_USB3,
234 SC7180_SLAVE_VENUS_CFG,
235 SC7180_SLAVE_VENUS_THROTTLE_CFG,
236 SC7180_SLAVE_VSENSE_CTRL_CFG,
237 SC7180_SLAVE_SERVICE_CNOC
238 },
239};
240
241static struct qcom_icc_node xm_qdss_dap = {
242 .name = "xm_qdss_dap",
243 .id = SC7180_MASTER_QDSS_DAP,
244 .channels = 1,
245 .buswidth = 8,
246 .num_links = 51,
247 .links = { SC7180_SLAVE_A1NOC_CFG,
248 SC7180_SLAVE_A2NOC_CFG,
249 SC7180_SLAVE_AHB2PHY_SOUTH,
250 SC7180_SLAVE_AHB2PHY_CENTER,
251 SC7180_SLAVE_AOP,
252 SC7180_SLAVE_AOSS,
253 SC7180_SLAVE_BOOT_ROM,
254 SC7180_SLAVE_CAMERA_CFG,
255 SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG,
256 SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG,
257 SC7180_SLAVE_CLK_CTL,
258 SC7180_SLAVE_RBCPR_CX_CFG,
259 SC7180_SLAVE_RBCPR_MX_CFG,
260 SC7180_SLAVE_CRYPTO_0_CFG,
261 SC7180_SLAVE_DCC_CFG,
262 SC7180_SLAVE_CNOC_DDRSS,
263 SC7180_SLAVE_DISPLAY_CFG,
264 SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG,
265 SC7180_SLAVE_DISPLAY_THROTTLE_CFG,
266 SC7180_SLAVE_EMMC_CFG,
267 SC7180_SLAVE_GLM,
268 SC7180_SLAVE_GFX3D_CFG,
269 SC7180_SLAVE_IMEM_CFG,
270 SC7180_SLAVE_IPA_CFG,
271 SC7180_SLAVE_CNOC_MNOC_CFG,
272 SC7180_SLAVE_CNOC_MSS,
273 SC7180_SLAVE_NPU_CFG,
274 SC7180_SLAVE_NPU_DMA_BWMON_CFG,
275 SC7180_SLAVE_NPU_PROC_BWMON_CFG,
276 SC7180_SLAVE_PDM,
277 SC7180_SLAVE_PIMEM_CFG,
278 SC7180_SLAVE_PRNG,
279 SC7180_SLAVE_QDSS_CFG,
280 SC7180_SLAVE_QM_CFG,
281 SC7180_SLAVE_QM_MPU_CFG,
282 SC7180_SLAVE_QSPI_0,
283 SC7180_SLAVE_QUP_0,
284 SC7180_SLAVE_QUP_1,
285 SC7180_SLAVE_SDCC_2,
286 SC7180_SLAVE_SECURITY,
287 SC7180_SLAVE_SNOC_CFG,
288 SC7180_SLAVE_TCSR,
289 SC7180_SLAVE_TLMM_WEST,
290 SC7180_SLAVE_TLMM_NORTH,
291 SC7180_SLAVE_TLMM_SOUTH,
292 SC7180_SLAVE_UFS_MEM_CFG,
293 SC7180_SLAVE_USB3,
294 SC7180_SLAVE_VENUS_CFG,
295 SC7180_SLAVE_VENUS_THROTTLE_CFG,
296 SC7180_SLAVE_VSENSE_CTRL_CFG,
297 SC7180_SLAVE_SERVICE_CNOC
298 },
299};
300
301static struct qcom_icc_node qhm_cnoc_dc_noc = {
302 .name = "qhm_cnoc_dc_noc",
303 .id = SC7180_MASTER_CNOC_DC_NOC,
304 .channels = 1,
305 .buswidth = 4,
306 .num_links = 2,
307 .links = { SC7180_SLAVE_GEM_NOC_CFG,
308 SC7180_SLAVE_LLCC_CFG
309 },
310};
311
312static struct qcom_icc_node acm_apps0 = {
313 .name = "acm_apps0",
314 .id = SC7180_MASTER_APPSS_PROC,
315 .channels = 1,
316 .buswidth = 16,
317 .num_links = 2,
318 .links = { SC7180_SLAVE_GEM_NOC_SNOC,
319 SC7180_SLAVE_LLCC
320 },
321};
322
323static struct qcom_icc_node acm_sys_tcu = {
324 .name = "acm_sys_tcu",
325 .id = SC7180_MASTER_SYS_TCU,
326 .channels = 1,
327 .buswidth = 8,
328 .num_links = 2,
329 .links = { SC7180_SLAVE_GEM_NOC_SNOC,
330 SC7180_SLAVE_LLCC
331 },
332};
333
334static struct qcom_icc_node qhm_gemnoc_cfg = {
335 .name = "qhm_gemnoc_cfg",
336 .id = SC7180_MASTER_GEM_NOC_CFG,
337 .channels = 1,
338 .buswidth = 4,
339 .num_links = 2,
340 .links = { SC7180_SLAVE_MSS_PROC_MS_MPU_CFG,
341 SC7180_SLAVE_SERVICE_GEM_NOC
342 },
343};
344
345static struct qcom_icc_node qnm_cmpnoc = {
346 .name = "qnm_cmpnoc",
347 .id = SC7180_MASTER_COMPUTE_NOC,
348 .channels = 1,
349 .buswidth = 32,
350 .num_links = 2,
351 .links = { SC7180_SLAVE_GEM_NOC_SNOC,
352 SC7180_SLAVE_LLCC
353 },
354};
355
356static struct qcom_icc_node qnm_mnoc_hf = {
357 .name = "qnm_mnoc_hf",
358 .id = SC7180_MASTER_MNOC_HF_MEM_NOC,
359 .channels = 1,
360 .buswidth = 32,
361 .num_links = 1,
362 .links = { SC7180_SLAVE_LLCC },
363};
364
365static struct qcom_icc_node qnm_mnoc_sf = {
366 .name = "qnm_mnoc_sf",
367 .id = SC7180_MASTER_MNOC_SF_MEM_NOC,
368 .channels = 1,
369 .buswidth = 32,
370 .num_links = 2,
371 .links = { SC7180_SLAVE_GEM_NOC_SNOC,
372 SC7180_SLAVE_LLCC
373 },
374};
375
376static struct qcom_icc_node qnm_snoc_gc = {
377 .name = "qnm_snoc_gc",
378 .id = SC7180_MASTER_SNOC_GC_MEM_NOC,
379 .channels = 1,
380 .buswidth = 8,
381 .num_links = 1,
382 .links = { SC7180_SLAVE_LLCC },
383};
384
385static struct qcom_icc_node qnm_snoc_sf = {
386 .name = "qnm_snoc_sf",
387 .id = SC7180_MASTER_SNOC_SF_MEM_NOC,
388 .channels = 1,
389 .buswidth = 16,
390 .num_links = 1,
391 .links = { SC7180_SLAVE_LLCC },
392};
393
394static struct qcom_icc_node qxm_gpu = {
395 .name = "qxm_gpu",
396 .id = SC7180_MASTER_GFX3D,
397 .channels = 2,
398 .buswidth = 32,
399 .num_links = 2,
400 .links = { SC7180_SLAVE_GEM_NOC_SNOC,
401 SC7180_SLAVE_LLCC
402 },
403};
404
405static struct qcom_icc_node llcc_mc = {
406 .name = "llcc_mc",
407 .id = SC7180_MASTER_LLCC,
408 .channels = 2,
409 .buswidth = 4,
410 .num_links = 1,
411 .links = { SC7180_SLAVE_EBI1 },
412};
413
414static struct qcom_icc_node qhm_mnoc_cfg = {
415 .name = "qhm_mnoc_cfg",
416 .id = SC7180_MASTER_CNOC_MNOC_CFG,
417 .channels = 1,
418 .buswidth = 4,
419 .num_links = 1,
420 .links = { SC7180_SLAVE_SERVICE_MNOC },
421};
422
423static struct qcom_icc_node qxm_camnoc_hf0 = {
424 .name = "qxm_camnoc_hf0",
425 .id = SC7180_MASTER_CAMNOC_HF0,
426 .channels = 2,
427 .buswidth = 32,
428 .num_links = 1,
429 .links = { SC7180_SLAVE_MNOC_HF_MEM_NOC },
430};
431
432static struct qcom_icc_node qxm_camnoc_hf1 = {
433 .name = "qxm_camnoc_hf1",
434 .id = SC7180_MASTER_CAMNOC_HF1,
435 .channels = 2,
436 .buswidth = 32,
437 .num_links = 1,
438 .links = { SC7180_SLAVE_MNOC_HF_MEM_NOC },
439};
440
441static struct qcom_icc_node qxm_camnoc_sf = {
442 .name = "qxm_camnoc_sf",
443 .id = SC7180_MASTER_CAMNOC_SF,
444 .channels = 1,
445 .buswidth = 32,
446 .num_links = 1,
447 .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC },
448};
449
450static struct qcom_icc_node qxm_mdp0 = {
451 .name = "qxm_mdp0",
452 .id = SC7180_MASTER_MDP0,
453 .channels = 1,
454 .buswidth = 32,
455 .num_links = 1,
456 .links = { SC7180_SLAVE_MNOC_HF_MEM_NOC },
457};
458
459static struct qcom_icc_node qxm_rot = {
460 .name = "qxm_rot",
461 .id = SC7180_MASTER_ROTATOR,
462 .channels = 1,
463 .buswidth = 16,
464 .num_links = 1,
465 .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC },
466};
467
468static struct qcom_icc_node qxm_venus0 = {
469 .name = "qxm_venus0",
470 .id = SC7180_MASTER_VIDEO_P0,
471 .channels = 1,
472 .buswidth = 32,
473 .num_links = 1,
474 .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC },
475};
476
477static struct qcom_icc_node qxm_venus_arm9 = {
478 .name = "qxm_venus_arm9",
479 .id = SC7180_MASTER_VIDEO_PROC,
480 .channels = 1,
481 .buswidth = 8,
482 .num_links = 1,
483 .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC },
484};
485
486static struct qcom_icc_node amm_npu_sys = {
487 .name = "amm_npu_sys",
488 .id = SC7180_MASTER_NPU_SYS,
489 .channels = 2,
490 .buswidth = 32,
491 .num_links = 1,
492 .links = { SC7180_SLAVE_NPU_COMPUTE_NOC },
493};
494
495static struct qcom_icc_node qhm_npu_cfg = {
496 .name = "qhm_npu_cfg",
497 .id = SC7180_MASTER_NPU_NOC_CFG,
498 .channels = 1,
499 .buswidth = 4,
500 .num_links = 8,
501 .links = { SC7180_SLAVE_NPU_CAL_DP0,
502 SC7180_SLAVE_NPU_CP,
503 SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG,
504 SC7180_SLAVE_NPU_DPM,
505 SC7180_SLAVE_ISENSE_CFG,
506 SC7180_SLAVE_NPU_LLM_CFG,
507 SC7180_SLAVE_NPU_TCM,
508 SC7180_SLAVE_SERVICE_NPU_NOC
509 },
510};
511
512static struct qcom_icc_node qup_core_master_1 = {
513 .name = "qup_core_master_1",
514 .id = SC7180_MASTER_QUP_CORE_0,
515 .channels = 1,
516 .buswidth = 4,
517 .num_links = 1,
518 .links = { SC7180_SLAVE_QUP_CORE_0 },
519};
520
521static struct qcom_icc_node qup_core_master_2 = {
522 .name = "qup_core_master_2",
523 .id = SC7180_MASTER_QUP_CORE_1,
524 .channels = 1,
525 .buswidth = 4,
526 .num_links = 1,
527 .links = { SC7180_SLAVE_QUP_CORE_1 },
528};
529
530static struct qcom_icc_node qhm_snoc_cfg = {
531 .name = "qhm_snoc_cfg",
532 .id = SC7180_MASTER_SNOC_CFG,
533 .channels = 1,
534 .buswidth = 4,
535 .num_links = 1,
536 .links = { SC7180_SLAVE_SERVICE_SNOC },
537};
538
539static struct qcom_icc_node qnm_aggre1_noc = {
540 .name = "qnm_aggre1_noc",
541 .id = SC7180_MASTER_A1NOC_SNOC,
542 .channels = 1,
543 .buswidth = 16,
544 .num_links = 6,
545 .links = { SC7180_SLAVE_APPSS,
546 SC7180_SLAVE_SNOC_CNOC,
547 SC7180_SLAVE_SNOC_GEM_NOC_SF,
548 SC7180_SLAVE_IMEM,
549 SC7180_SLAVE_PIMEM,
550 SC7180_SLAVE_QDSS_STM
551 },
552};
553
554static struct qcom_icc_node qnm_aggre2_noc = {
555 .name = "qnm_aggre2_noc",
556 .id = SC7180_MASTER_A2NOC_SNOC,
557 .channels = 1,
558 .buswidth = 16,
559 .num_links = 7,
560 .links = { SC7180_SLAVE_APPSS,
561 SC7180_SLAVE_SNOC_CNOC,
562 SC7180_SLAVE_SNOC_GEM_NOC_SF,
563 SC7180_SLAVE_IMEM,
564 SC7180_SLAVE_PIMEM,
565 SC7180_SLAVE_QDSS_STM,
566 SC7180_SLAVE_TCU
567 },
568};
569
570static struct qcom_icc_node qnm_gemnoc = {
571 .name = "qnm_gemnoc",
572 .id = SC7180_MASTER_GEM_NOC_SNOC,
573 .channels = 1,
574 .buswidth = 8,
575 .num_links = 6,
576 .links = { SC7180_SLAVE_APPSS,
577 SC7180_SLAVE_SNOC_CNOC,
578 SC7180_SLAVE_IMEM,
579 SC7180_SLAVE_PIMEM,
580 SC7180_SLAVE_QDSS_STM,
581 SC7180_SLAVE_TCU
582 },
583};
584
585static struct qcom_icc_node qxm_pimem = {
586 .name = "qxm_pimem",
587 .id = SC7180_MASTER_PIMEM,
588 .channels = 1,
589 .buswidth = 8,
590 .num_links = 2,
591 .links = { SC7180_SLAVE_SNOC_GEM_NOC_GC,
592 SC7180_SLAVE_IMEM
593 },
594};
595
596static struct qcom_icc_node qns_a1noc_snoc = {
597 .name = "qns_a1noc_snoc",
598 .id = SC7180_SLAVE_A1NOC_SNOC,
599 .channels = 1,
600 .buswidth = 16,
601 .num_links = 1,
602 .links = { SC7180_MASTER_A1NOC_SNOC },
603};
604
605static struct qcom_icc_node srvc_aggre1_noc = {
606 .name = "srvc_aggre1_noc",
607 .id = SC7180_SLAVE_SERVICE_A1NOC,
608 .channels = 1,
609 .buswidth = 4,
610};
611
612static struct qcom_icc_node qns_a2noc_snoc = {
613 .name = "qns_a2noc_snoc",
614 .id = SC7180_SLAVE_A2NOC_SNOC,
615 .channels = 1,
616 .buswidth = 16,
617 .num_links = 1,
618 .links = { SC7180_MASTER_A2NOC_SNOC },
619};
620
621static struct qcom_icc_node srvc_aggre2_noc = {
622 .name = "srvc_aggre2_noc",
623 .id = SC7180_SLAVE_SERVICE_A2NOC,
624 .channels = 1,
625 .buswidth = 4,
626};
627
628static struct qcom_icc_node qns_camnoc_uncomp = {
629 .name = "qns_camnoc_uncomp",
630 .id = SC7180_SLAVE_CAMNOC_UNCOMP,
631 .channels = 1,
632 .buswidth = 32,
633};
634
635static struct qcom_icc_node qns_cdsp_gemnoc = {
636 .name = "qns_cdsp_gemnoc",
637 .id = SC7180_SLAVE_CDSP_GEM_NOC,
638 .channels = 1,
639 .buswidth = 32,
640 .num_links = 1,
641 .links = { SC7180_MASTER_COMPUTE_NOC },
642};
643
644static struct qcom_icc_node qhs_a1_noc_cfg = {
645 .name = "qhs_a1_noc_cfg",
646 .id = SC7180_SLAVE_A1NOC_CFG,
647 .channels = 1,
648 .buswidth = 4,
649 .num_links = 1,
650 .links = { SC7180_MASTER_A1NOC_CFG },
651};
652
653static struct qcom_icc_node qhs_a2_noc_cfg = {
654 .name = "qhs_a2_noc_cfg",
655 .id = SC7180_SLAVE_A2NOC_CFG,
656 .channels = 1,
657 .buswidth = 4,
658 .num_links = 1,
659 .links = { SC7180_MASTER_A2NOC_CFG },
660};
661
662static struct qcom_icc_node qhs_ahb2phy0 = {
663 .name = "qhs_ahb2phy0",
664 .id = SC7180_SLAVE_AHB2PHY_SOUTH,
665 .channels = 1,
666 .buswidth = 4,
667};
668
669static struct qcom_icc_node qhs_ahb2phy2 = {
670 .name = "qhs_ahb2phy2",
671 .id = SC7180_SLAVE_AHB2PHY_CENTER,
672 .channels = 1,
673 .buswidth = 4,
674};
675
676static struct qcom_icc_node qhs_aop = {
677 .name = "qhs_aop",
678 .id = SC7180_SLAVE_AOP,
679 .channels = 1,
680 .buswidth = 4,
681};
682
683static struct qcom_icc_node qhs_aoss = {
684 .name = "qhs_aoss",
685 .id = SC7180_SLAVE_AOSS,
686 .channels = 1,
687 .buswidth = 4,
688};
689
690static struct qcom_icc_node qhs_boot_rom = {
691 .name = "qhs_boot_rom",
692 .id = SC7180_SLAVE_BOOT_ROM,
693 .channels = 1,
694 .buswidth = 4,
695};
696
697static struct qcom_icc_node qhs_camera_cfg = {
698 .name = "qhs_camera_cfg",
699 .id = SC7180_SLAVE_CAMERA_CFG,
700 .channels = 1,
701 .buswidth = 4,
702};
703
704static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = {
705 .name = "qhs_camera_nrt_throttle_cfg",
706 .id = SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG,
707 .channels = 1,
708 .buswidth = 4,
709};
710
711static struct qcom_icc_node qhs_camera_rt_throttle_cfg = {
712 .name = "qhs_camera_rt_throttle_cfg",
713 .id = SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG,
714 .channels = 1,
715 .buswidth = 4,
716};
717
718static struct qcom_icc_node qhs_clk_ctl = {
719 .name = "qhs_clk_ctl",
720 .id = SC7180_SLAVE_CLK_CTL,
721 .channels = 1,
722 .buswidth = 4,
723};
724
725static struct qcom_icc_node qhs_cpr_cx = {
726 .name = "qhs_cpr_cx",
727 .id = SC7180_SLAVE_RBCPR_CX_CFG,
728 .channels = 1,
729 .buswidth = 4,
730};
731
732static struct qcom_icc_node qhs_cpr_mx = {
733 .name = "qhs_cpr_mx",
734 .id = SC7180_SLAVE_RBCPR_MX_CFG,
735 .channels = 1,
736 .buswidth = 4,
737};
738
739static struct qcom_icc_node qhs_crypto0_cfg = {
740 .name = "qhs_crypto0_cfg",
741 .id = SC7180_SLAVE_CRYPTO_0_CFG,
742 .channels = 1,
743 .buswidth = 4,
744};
745
746static struct qcom_icc_node qhs_dcc_cfg = {
747 .name = "qhs_dcc_cfg",
748 .id = SC7180_SLAVE_DCC_CFG,
749 .channels = 1,
750 .buswidth = 4,
751};
752
753static struct qcom_icc_node qhs_ddrss_cfg = {
754 .name = "qhs_ddrss_cfg",
755 .id = SC7180_SLAVE_CNOC_DDRSS,
756 .channels = 1,
757 .buswidth = 4,
758 .num_links = 1,
759 .links = { SC7180_MASTER_CNOC_DC_NOC },
760};
761
762static struct qcom_icc_node qhs_display_cfg = {
763 .name = "qhs_display_cfg",
764 .id = SC7180_SLAVE_DISPLAY_CFG,
765 .channels = 1,
766 .buswidth = 4,
767};
768
769static struct qcom_icc_node qhs_display_rt_throttle_cfg = {
770 .name = "qhs_display_rt_throttle_cfg",
771 .id = SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG,
772 .channels = 1,
773 .buswidth = 4,
774};
775
776static struct qcom_icc_node qhs_display_throttle_cfg = {
777 .name = "qhs_display_throttle_cfg",
778 .id = SC7180_SLAVE_DISPLAY_THROTTLE_CFG,
779 .channels = 1,
780 .buswidth = 4,
781};
782
783static struct qcom_icc_node qhs_emmc_cfg = {
784 .name = "qhs_emmc_cfg",
785 .id = SC7180_SLAVE_EMMC_CFG,
786 .channels = 1,
787 .buswidth = 4,
788};
789
790static struct qcom_icc_node qhs_glm = {
791 .name = "qhs_glm",
792 .id = SC7180_SLAVE_GLM,
793 .channels = 1,
794 .buswidth = 4,
795};
796
797static struct qcom_icc_node qhs_gpuss_cfg = {
798 .name = "qhs_gpuss_cfg",
799 .id = SC7180_SLAVE_GFX3D_CFG,
800 .channels = 1,
801 .buswidth = 8,
802};
803
804static struct qcom_icc_node qhs_imem_cfg = {
805 .name = "qhs_imem_cfg",
806 .id = SC7180_SLAVE_IMEM_CFG,
807 .channels = 1,
808 .buswidth = 4,
809};
810
811static struct qcom_icc_node qhs_ipa = {
812 .name = "qhs_ipa",
813 .id = SC7180_SLAVE_IPA_CFG,
814 .channels = 1,
815 .buswidth = 4,
816};
817
818static struct qcom_icc_node qhs_mnoc_cfg = {
819 .name = "qhs_mnoc_cfg",
820 .id = SC7180_SLAVE_CNOC_MNOC_CFG,
821 .channels = 1,
822 .buswidth = 4,
823 .num_links = 1,
824 .links = { SC7180_MASTER_CNOC_MNOC_CFG },
825};
826
827static struct qcom_icc_node qhs_mss_cfg = {
828 .name = "qhs_mss_cfg",
829 .id = SC7180_SLAVE_CNOC_MSS,
830 .channels = 1,
831 .buswidth = 4,
832};
833
834static struct qcom_icc_node qhs_npu_cfg = {
835 .name = "qhs_npu_cfg",
836 .id = SC7180_SLAVE_NPU_CFG,
837 .channels = 1,
838 .buswidth = 4,
839 .num_links = 1,
840 .links = { SC7180_MASTER_NPU_NOC_CFG },
841};
842
843static struct qcom_icc_node qhs_npu_dma_throttle_cfg = {
844 .name = "qhs_npu_dma_throttle_cfg",
845 .id = SC7180_SLAVE_NPU_DMA_BWMON_CFG,
846 .channels = 1,
847 .buswidth = 4,
848};
849
850static struct qcom_icc_node qhs_npu_dsp_throttle_cfg = {
851 .name = "qhs_npu_dsp_throttle_cfg",
852 .id = SC7180_SLAVE_NPU_PROC_BWMON_CFG,
853 .channels = 1,
854 .buswidth = 4,
855};
856
857static struct qcom_icc_node qhs_pdm = {
858 .name = "qhs_pdm",
859 .id = SC7180_SLAVE_PDM,
860 .channels = 1,
861 .buswidth = 4,
862};
863
864static struct qcom_icc_node qhs_pimem_cfg = {
865 .name = "qhs_pimem_cfg",
866 .id = SC7180_SLAVE_PIMEM_CFG,
867 .channels = 1,
868 .buswidth = 4,
869};
870
871static struct qcom_icc_node qhs_prng = {
872 .name = "qhs_prng",
873 .id = SC7180_SLAVE_PRNG,
874 .channels = 1,
875 .buswidth = 4,
876};
877
878static struct qcom_icc_node qhs_qdss_cfg = {
879 .name = "qhs_qdss_cfg",
880 .id = SC7180_SLAVE_QDSS_CFG,
881 .channels = 1,
882 .buswidth = 4,
883};
884
885static struct qcom_icc_node qhs_qm_cfg = {
886 .name = "qhs_qm_cfg",
887 .id = SC7180_SLAVE_QM_CFG,
888 .channels = 1,
889 .buswidth = 4,
890};
891
892static struct qcom_icc_node qhs_qm_mpu_cfg = {
893 .name = "qhs_qm_mpu_cfg",
894 .id = SC7180_SLAVE_QM_MPU_CFG,
895 .channels = 1,
896 .buswidth = 4,
897};
898
899static struct qcom_icc_node qhs_qspi = {
900 .name = "qhs_qspi",
901 .id = SC7180_SLAVE_QSPI_0,
902 .channels = 1,
903 .buswidth = 4,
904};
905
906static struct qcom_icc_node qhs_qup0 = {
907 .name = "qhs_qup0",
908 .id = SC7180_SLAVE_QUP_0,
909 .channels = 1,
910 .buswidth = 4,
911};
912
913static struct qcom_icc_node qhs_qup1 = {
914 .name = "qhs_qup1",
915 .id = SC7180_SLAVE_QUP_1,
916 .channels = 1,
917 .buswidth = 4,
918};
919
920static struct qcom_icc_node qhs_sdc2 = {
921 .name = "qhs_sdc2",
922 .id = SC7180_SLAVE_SDCC_2,
923 .channels = 1,
924 .buswidth = 4,
925};
926
927static struct qcom_icc_node qhs_security = {
928 .name = "qhs_security",
929 .id = SC7180_SLAVE_SECURITY,
930 .channels = 1,
931 .buswidth = 4,
932};
933
934static struct qcom_icc_node qhs_snoc_cfg = {
935 .name = "qhs_snoc_cfg",
936 .id = SC7180_SLAVE_SNOC_CFG,
937 .channels = 1,
938 .buswidth = 4,
939 .num_links = 1,
940 .links = { SC7180_MASTER_SNOC_CFG },
941};
942
943static struct qcom_icc_node qhs_tcsr = {
944 .name = "qhs_tcsr",
945 .id = SC7180_SLAVE_TCSR,
946 .channels = 1,
947 .buswidth = 4,
948};
949
950static struct qcom_icc_node qhs_tlmm_1 = {
951 .name = "qhs_tlmm_1",
952 .id = SC7180_SLAVE_TLMM_WEST,
953 .channels = 1,
954 .buswidth = 4,
955};
956
957static struct qcom_icc_node qhs_tlmm_2 = {
958 .name = "qhs_tlmm_2",
959 .id = SC7180_SLAVE_TLMM_NORTH,
960 .channels = 1,
961 .buswidth = 4,
962};
963
964static struct qcom_icc_node qhs_tlmm_3 = {
965 .name = "qhs_tlmm_3",
966 .id = SC7180_SLAVE_TLMM_SOUTH,
967 .channels = 1,
968 .buswidth = 4,
969};
970
971static struct qcom_icc_node qhs_ufs_mem_cfg = {
972 .name = "qhs_ufs_mem_cfg",
973 .id = SC7180_SLAVE_UFS_MEM_CFG,
974 .channels = 1,
975 .buswidth = 4,
976};
977
978static struct qcom_icc_node qhs_usb3 = {
979 .name = "qhs_usb3",
980 .id = SC7180_SLAVE_USB3,
981 .channels = 1,
982 .buswidth = 4,
983};
984
985static struct qcom_icc_node qhs_venus_cfg = {
986 .name = "qhs_venus_cfg",
987 .id = SC7180_SLAVE_VENUS_CFG,
988 .channels = 1,
989 .buswidth = 4,
990};
991
992static struct qcom_icc_node qhs_venus_throttle_cfg = {
993 .name = "qhs_venus_throttle_cfg",
994 .id = SC7180_SLAVE_VENUS_THROTTLE_CFG,
995 .channels = 1,
996 .buswidth = 4,
997};
998
999static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1000 .name = "qhs_vsense_ctrl_cfg",
1001 .id = SC7180_SLAVE_VSENSE_CTRL_CFG,
1002 .channels = 1,
1003 .buswidth = 4,
1004};
1005
1006static struct qcom_icc_node srvc_cnoc = {
1007 .name = "srvc_cnoc",
1008 .id = SC7180_SLAVE_SERVICE_CNOC,
1009 .channels = 1,
1010 .buswidth = 4,
1011};
1012
1013static struct qcom_icc_node qhs_gemnoc = {
1014 .name = "qhs_gemnoc",
1015 .id = SC7180_SLAVE_GEM_NOC_CFG,
1016 .channels = 1,
1017 .buswidth = 4,
1018 .num_links = 1,
1019 .links = { SC7180_MASTER_GEM_NOC_CFG },
1020};
1021
1022static struct qcom_icc_node qhs_llcc = {
1023 .name = "qhs_llcc",
1024 .id = SC7180_SLAVE_LLCC_CFG,
1025 .channels = 1,
1026 .buswidth = 4,
1027};
1028
1029static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
1030 .name = "qhs_mdsp_ms_mpu_cfg",
1031 .id = SC7180_SLAVE_MSS_PROC_MS_MPU_CFG,
1032 .channels = 1,
1033 .buswidth = 4,
1034};
1035
1036static struct qcom_icc_node qns_gem_noc_snoc = {
1037 .name = "qns_gem_noc_snoc",
1038 .id = SC7180_SLAVE_GEM_NOC_SNOC,
1039 .channels = 1,
1040 .buswidth = 8,
1041 .num_links = 1,
1042 .links = { SC7180_MASTER_GEM_NOC_SNOC },
1043};
1044
1045static struct qcom_icc_node qns_llcc = {
1046 .name = "qns_llcc",
1047 .id = SC7180_SLAVE_LLCC,
1048 .channels = 1,
1049 .buswidth = 16,
1050 .num_links = 1,
1051 .links = { SC7180_MASTER_LLCC },
1052};
1053
1054static struct qcom_icc_node srvc_gemnoc = {
1055 .name = "srvc_gemnoc",
1056 .id = SC7180_SLAVE_SERVICE_GEM_NOC,
1057 .channels = 1,
1058 .buswidth = 4,
1059};
1060
1061static struct qcom_icc_node ebi = {
1062 .name = "ebi",
1063 .id = SC7180_SLAVE_EBI1,
1064 .channels = 2,
1065 .buswidth = 4,
1066};
1067
1068static struct qcom_icc_node qns_mem_noc_hf = {
1069 .name = "qns_mem_noc_hf",
1070 .id = SC7180_SLAVE_MNOC_HF_MEM_NOC,
1071 .channels = 1,
1072 .buswidth = 32,
1073 .num_links = 1,
1074 .links = { SC7180_MASTER_MNOC_HF_MEM_NOC },
1075};
1076
1077static struct qcom_icc_node qns_mem_noc_sf = {
1078 .name = "qns_mem_noc_sf",
1079 .id = SC7180_SLAVE_MNOC_SF_MEM_NOC,
1080 .channels = 1,
1081 .buswidth = 32,
1082 .num_links = 1,
1083 .links = { SC7180_MASTER_MNOC_SF_MEM_NOC },
1084};
1085
1086static struct qcom_icc_node srvc_mnoc = {
1087 .name = "srvc_mnoc",
1088 .id = SC7180_SLAVE_SERVICE_MNOC,
1089 .channels = 1,
1090 .buswidth = 4,
1091};
1092
1093static struct qcom_icc_node qhs_cal_dp0 = {
1094 .name = "qhs_cal_dp0",
1095 .id = SC7180_SLAVE_NPU_CAL_DP0,
1096 .channels = 1,
1097 .buswidth = 4,
1098};
1099
1100static struct qcom_icc_node qhs_cp = {
1101 .name = "qhs_cp",
1102 .id = SC7180_SLAVE_NPU_CP,
1103 .channels = 1,
1104 .buswidth = 4,
1105};
1106
1107static struct qcom_icc_node qhs_dma_bwmon = {
1108 .name = "qhs_dma_bwmon",
1109 .id = SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG,
1110 .channels = 1,
1111 .buswidth = 4,
1112};
1113
1114static struct qcom_icc_node qhs_dpm = {
1115 .name = "qhs_dpm",
1116 .id = SC7180_SLAVE_NPU_DPM,
1117 .channels = 1,
1118 .buswidth = 4,
1119};
1120
1121static struct qcom_icc_node qhs_isense = {
1122 .name = "qhs_isense",
1123 .id = SC7180_SLAVE_ISENSE_CFG,
1124 .channels = 1,
1125 .buswidth = 4,
1126};
1127
1128static struct qcom_icc_node qhs_llm = {
1129 .name = "qhs_llm",
1130 .id = SC7180_SLAVE_NPU_LLM_CFG,
1131 .channels = 1,
1132 .buswidth = 4,
1133};
1134
1135static struct qcom_icc_node qhs_tcm = {
1136 .name = "qhs_tcm",
1137 .id = SC7180_SLAVE_NPU_TCM,
1138 .channels = 1,
1139 .buswidth = 4,
1140};
1141
1142static struct qcom_icc_node qns_npu_sys = {
1143 .name = "qns_npu_sys",
1144 .id = SC7180_SLAVE_NPU_COMPUTE_NOC,
1145 .channels = 2,
1146 .buswidth = 32,
1147};
1148
1149static struct qcom_icc_node srvc_noc = {
1150 .name = "srvc_noc",
1151 .id = SC7180_SLAVE_SERVICE_NPU_NOC,
1152 .channels = 1,
1153 .buswidth = 4,
1154};
1155
1156static struct qcom_icc_node qup_core_slave_1 = {
1157 .name = "qup_core_slave_1",
1158 .id = SC7180_SLAVE_QUP_CORE_0,
1159 .channels = 1,
1160 .buswidth = 4,
1161};
1162
1163static struct qcom_icc_node qup_core_slave_2 = {
1164 .name = "qup_core_slave_2",
1165 .id = SC7180_SLAVE_QUP_CORE_1,
1166 .channels = 1,
1167 .buswidth = 4,
1168};
1169
1170static struct qcom_icc_node qhs_apss = {
1171 .name = "qhs_apss",
1172 .id = SC7180_SLAVE_APPSS,
1173 .channels = 1,
1174 .buswidth = 8,
1175};
1176
1177static struct qcom_icc_node qns_cnoc = {
1178 .name = "qns_cnoc",
1179 .id = SC7180_SLAVE_SNOC_CNOC,
1180 .channels = 1,
1181 .buswidth = 8,
1182 .num_links = 1,
1183 .links = { SC7180_MASTER_SNOC_CNOC },
1184};
1185
1186static struct qcom_icc_node qns_gemnoc_gc = {
1187 .name = "qns_gemnoc_gc",
1188 .id = SC7180_SLAVE_SNOC_GEM_NOC_GC,
1189 .channels = 1,
1190 .buswidth = 8,
1191 .num_links = 1,
1192 .links = { SC7180_MASTER_SNOC_GC_MEM_NOC },
1193};
1194
1195static struct qcom_icc_node qns_gemnoc_sf = {
1196 .name = "qns_gemnoc_sf",
1197 .id = SC7180_SLAVE_SNOC_GEM_NOC_SF,
1198 .channels = 1,
1199 .buswidth = 16,
1200 .num_links = 1,
1201 .links = { SC7180_MASTER_SNOC_SF_MEM_NOC },
1202};
1203
1204static struct qcom_icc_node qxs_imem = {
1205 .name = "qxs_imem",
1206 .id = SC7180_SLAVE_IMEM,
1207 .channels = 1,
1208 .buswidth = 8,
1209};
1210
1211static struct qcom_icc_node qxs_pimem = {
1212 .name = "qxs_pimem",
1213 .id = SC7180_SLAVE_PIMEM,
1214 .channels = 1,
1215 .buswidth = 8,
1216};
1217
1218static struct qcom_icc_node srvc_snoc = {
1219 .name = "srvc_snoc",
1220 .id = SC7180_SLAVE_SERVICE_SNOC,
1221 .channels = 1,
1222 .buswidth = 4,
1223};
1224
1225static struct qcom_icc_node xs_qdss_stm = {
1226 .name = "xs_qdss_stm",
1227 .id = SC7180_SLAVE_QDSS_STM,
1228 .channels = 1,
1229 .buswidth = 4,
1230};
1231
1232static struct qcom_icc_node xs_sys_tcu_cfg = {
1233 .name = "xs_sys_tcu_cfg",
1234 .id = SC7180_SLAVE_TCU,
1235 .channels = 1,
1236 .buswidth = 8,
1237};
1238
1239static struct qcom_icc_bcm bcm_acv = {
1240 .name = "ACV",
1241 .enable_mask = BIT(3),
1242 .keepalive = false,
1243 .num_nodes = 1,
1244 .nodes = { &ebi },
1245};
1246
1247static struct qcom_icc_bcm bcm_mc0 = {
1248 .name = "MC0",
1249 .keepalive = true,
1250 .num_nodes = 1,
1251 .nodes = { &ebi },
1252};
1253
1254static struct qcom_icc_bcm bcm_sh0 = {
1255 .name = "SH0",
1256 .keepalive = true,
1257 .num_nodes = 1,
1258 .nodes = { &qns_llcc },
1259};
1260
1261static struct qcom_icc_bcm bcm_mm0 = {
1262 .name = "MM0",
1263 .keepalive = false,
1264 .num_nodes = 1,
1265 .nodes = { &qns_mem_noc_hf },
1266};
1267
1268static struct qcom_icc_bcm bcm_ce0 = {
1269 .name = "CE0",
1270 .keepalive = false,
1271 .num_nodes = 1,
1272 .nodes = { &qxm_crypto },
1273};
1274
1275static struct qcom_icc_bcm bcm_cn0 = {
1276 .name = "CN0",
1277 .keepalive = true,
1278 .num_nodes = 48,
1279 .nodes = { &qnm_snoc,
1280 &xm_qdss_dap,
1281 &qhs_a1_noc_cfg,
1282 &qhs_a2_noc_cfg,
1283 &qhs_ahb2phy0,
1284 &qhs_aop,
1285 &qhs_aoss,
1286 &qhs_boot_rom,
1287 &qhs_camera_cfg,
1288 &qhs_camera_nrt_throttle_cfg,
1289 &qhs_camera_rt_throttle_cfg,
1290 &qhs_clk_ctl,
1291 &qhs_cpr_cx,
1292 &qhs_cpr_mx,
1293 &qhs_crypto0_cfg,
1294 &qhs_dcc_cfg,
1295 &qhs_ddrss_cfg,
1296 &qhs_display_cfg,
1297 &qhs_display_rt_throttle_cfg,
1298 &qhs_display_throttle_cfg,
1299 &qhs_glm,
1300 &qhs_gpuss_cfg,
1301 &qhs_imem_cfg,
1302 &qhs_ipa,
1303 &qhs_mnoc_cfg,
1304 &qhs_mss_cfg,
1305 &qhs_npu_cfg,
1306 &qhs_npu_dma_throttle_cfg,
1307 &qhs_npu_dsp_throttle_cfg,
1308 &qhs_pimem_cfg,
1309 &qhs_prng,
1310 &qhs_qdss_cfg,
1311 &qhs_qm_cfg,
1312 &qhs_qm_mpu_cfg,
1313 &qhs_qup0,
1314 &qhs_qup1,
1315 &qhs_security,
1316 &qhs_snoc_cfg,
1317 &qhs_tcsr,
1318 &qhs_tlmm_1,
1319 &qhs_tlmm_2,
1320 &qhs_tlmm_3,
1321 &qhs_ufs_mem_cfg,
1322 &qhs_usb3,
1323 &qhs_venus_cfg,
1324 &qhs_venus_throttle_cfg,
1325 &qhs_vsense_ctrl_cfg,
1326 &srvc_cnoc
1327 },
1328};
1329
1330static struct qcom_icc_bcm bcm_mm1 = {
1331 .name = "MM1",
1332 .keepalive = false,
1333 .num_nodes = 8,
1334 .nodes = { &qxm_camnoc_hf0_uncomp,
1335 &qxm_camnoc_hf1_uncomp,
1336 &qxm_camnoc_sf_uncomp,
1337 &qhm_mnoc_cfg,
1338 &qxm_mdp0,
1339 &qxm_rot,
1340 &qxm_venus0,
1341 &qxm_venus_arm9
1342 },
1343};
1344
1345static struct qcom_icc_bcm bcm_sh2 = {
1346 .name = "SH2",
1347 .keepalive = false,
1348 .num_nodes = 1,
1349 .nodes = { &acm_sys_tcu },
1350};
1351
1352static struct qcom_icc_bcm bcm_mm2 = {
1353 .name = "MM2",
1354 .keepalive = false,
1355 .num_nodes = 1,
1356 .nodes = { &qns_mem_noc_sf },
1357};
1358
1359static struct qcom_icc_bcm bcm_qup0 = {
1360 .name = "QUP0",
1361 .keepalive = false,
1362 .num_nodes = 2,
1363 .nodes = { &qup_core_master_1, &qup_core_master_2 },
1364};
1365
1366static struct qcom_icc_bcm bcm_sh3 = {
1367 .name = "SH3",
1368 .keepalive = false,
1369 .num_nodes = 1,
1370 .nodes = { &qnm_cmpnoc },
1371};
1372
1373static struct qcom_icc_bcm bcm_sh4 = {
1374 .name = "SH4",
1375 .keepalive = false,
1376 .num_nodes = 1,
1377 .nodes = { &acm_apps0 },
1378};
1379
1380static struct qcom_icc_bcm bcm_sn0 = {
1381 .name = "SN0",
1382 .keepalive = true,
1383 .num_nodes = 1,
1384 .nodes = { &qns_gemnoc_sf },
1385};
1386
1387static struct qcom_icc_bcm bcm_co0 = {
1388 .name = "CO0",
1389 .keepalive = false,
1390 .num_nodes = 1,
1391 .nodes = { &qns_cdsp_gemnoc },
1392};
1393
1394static struct qcom_icc_bcm bcm_sn1 = {
1395 .name = "SN1",
1396 .keepalive = false,
1397 .num_nodes = 1,
1398 .nodes = { &qxs_imem },
1399};
1400
1401static struct qcom_icc_bcm bcm_cn1 = {
1402 .name = "CN1",
1403 .keepalive = false,
1404 .num_nodes = 8,
1405 .nodes = { &qhm_qspi,
1406 &xm_sdc2,
1407 &xm_emmc,
1408 &qhs_ahb2phy2,
1409 &qhs_emmc_cfg,
1410 &qhs_pdm,
1411 &qhs_qspi,
1412 &qhs_sdc2
1413 },
1414};
1415
1416static struct qcom_icc_bcm bcm_sn2 = {
1417 .name = "SN2",
1418 .keepalive = false,
1419 .num_nodes = 2,
1420 .nodes = { &qxm_pimem, &qns_gemnoc_gc },
1421};
1422
1423static struct qcom_icc_bcm bcm_co2 = {
1424 .name = "CO2",
1425 .keepalive = false,
1426 .num_nodes = 1,
1427 .nodes = { &qnm_npu },
1428};
1429
1430static struct qcom_icc_bcm bcm_sn3 = {
1431 .name = "SN3",
1432 .keepalive = false,
1433 .num_nodes = 1,
1434 .nodes = { &qxs_pimem },
1435};
1436
1437static struct qcom_icc_bcm bcm_co3 = {
1438 .name = "CO3",
1439 .keepalive = false,
1440 .num_nodes = 1,
1441 .nodes = { &qxm_npu_dsp },
1442};
1443
1444static struct qcom_icc_bcm bcm_sn4 = {
1445 .name = "SN4",
1446 .keepalive = false,
1447 .num_nodes = 1,
1448 .nodes = { &xs_qdss_stm },
1449};
1450
1451static struct qcom_icc_bcm bcm_sn7 = {
1452 .name = "SN7",
1453 .keepalive = false,
1454 .num_nodes = 1,
1455 .nodes = { &qnm_aggre1_noc },
1456};
1457
1458static struct qcom_icc_bcm bcm_sn9 = {
1459 .name = "SN9",
1460 .keepalive = false,
1461 .num_nodes = 1,
1462 .nodes = { &qnm_aggre2_noc },
1463};
1464
1465static struct qcom_icc_bcm bcm_sn12 = {
1466 .name = "SN12",
1467 .keepalive = false,
1468 .num_nodes = 1,
1469 .nodes = { &qnm_gemnoc },
1470};
1471
1472static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1473 &bcm_cn1,
1474};
1475
1476static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1477 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
1478 [MASTER_QSPI] = &qhm_qspi,
1479 [MASTER_QUP_0] = &qhm_qup_0,
1480 [MASTER_SDCC_2] = &xm_sdc2,
1481 [MASTER_EMMC] = &xm_emmc,
1482 [MASTER_UFS_MEM] = &xm_ufs_mem,
1483 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1484 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
1485};
1486
1487static const struct qcom_icc_desc sc7180_aggre1_noc = {
1488 .nodes = aggre1_noc_nodes,
1489 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1490 .bcms = aggre1_noc_bcms,
1491 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1492};
1493
1494static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1495 &bcm_ce0,
1496};
1497
1498static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1499 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
1500 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
1501 [MASTER_QUP_1] = &qhm_qup_1,
1502 [MASTER_USB3] = &qhm_usb3,
1503 [MASTER_CRYPTO] = &qxm_crypto,
1504 [MASTER_IPA] = &qxm_ipa,
1505 [MASTER_QDSS_ETR] = &xm_qdss_etr,
1506 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1507 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
1508};
1509
1510static const struct qcom_icc_desc sc7180_aggre2_noc = {
1511 .nodes = aggre2_noc_nodes,
1512 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1513 .bcms = aggre2_noc_bcms,
1514 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1515};
1516
1517static struct qcom_icc_bcm * const camnoc_virt_bcms[] = {
1518 &bcm_mm1,
1519};
1520
1521static struct qcom_icc_node * const camnoc_virt_nodes[] = {
1522 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
1523 [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
1524 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
1525 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
1526};
1527
1528static const struct qcom_icc_desc sc7180_camnoc_virt = {
1529 .nodes = camnoc_virt_nodes,
1530 .num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
1531 .bcms = camnoc_virt_bcms,
1532 .num_bcms = ARRAY_SIZE(camnoc_virt_bcms),
1533};
1534
1535static struct qcom_icc_bcm * const compute_noc_bcms[] = {
1536 &bcm_co0,
1537 &bcm_co2,
1538 &bcm_co3,
1539};
1540
1541static struct qcom_icc_node * const compute_noc_nodes[] = {
1542 [MASTER_NPU] = &qnm_npu,
1543 [MASTER_NPU_PROC] = &qxm_npu_dsp,
1544 [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc,
1545};
1546
1547static const struct qcom_icc_desc sc7180_compute_noc = {
1548 .nodes = compute_noc_nodes,
1549 .num_nodes = ARRAY_SIZE(compute_noc_nodes),
1550 .bcms = compute_noc_bcms,
1551 .num_bcms = ARRAY_SIZE(compute_noc_bcms),
1552};
1553
1554static struct qcom_icc_bcm * const config_noc_bcms[] = {
1555 &bcm_cn0,
1556 &bcm_cn1,
1557};
1558
1559static struct qcom_icc_node * const config_noc_nodes[] = {
1560 [MASTER_SNOC_CNOC] = &qnm_snoc,
1561 [MASTER_QDSS_DAP] = &xm_qdss_dap,
1562 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
1563 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
1564 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1565 [SLAVE_AHB2PHY_CENTER] = &qhs_ahb2phy2,
1566 [SLAVE_AOP] = &qhs_aop,
1567 [SLAVE_AOSS] = &qhs_aoss,
1568 [SLAVE_BOOT_ROM] = &qhs_boot_rom,
1569 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1570 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg,
1571 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg,
1572 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1573 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1574 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
1575 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1576 [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
1577 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
1578 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1579 [SLAVE_DISPLAY_RT_THROTTLE_CFG] = &qhs_display_rt_throttle_cfg,
1580 [SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg,
1581 [SLAVE_EMMC_CFG] = &qhs_emmc_cfg,
1582 [SLAVE_GLM] = &qhs_glm,
1583 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1584 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1585 [SLAVE_IPA_CFG] = &qhs_ipa,
1586 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
1587 [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
1588 [SLAVE_NPU_CFG] = &qhs_npu_cfg,
1589 [SLAVE_NPU_DMA_BWMON_CFG] = &qhs_npu_dma_throttle_cfg,
1590 [SLAVE_NPU_PROC_BWMON_CFG] = &qhs_npu_dsp_throttle_cfg,
1591 [SLAVE_PDM] = &qhs_pdm,
1592 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1593 [SLAVE_PRNG] = &qhs_prng,
1594 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1595 [SLAVE_QM_CFG] = &qhs_qm_cfg,
1596 [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg,
1597 [SLAVE_QSPI_0] = &qhs_qspi,
1598 [SLAVE_QUP_0] = &qhs_qup0,
1599 [SLAVE_QUP_1] = &qhs_qup1,
1600 [SLAVE_SDCC_2] = &qhs_sdc2,
1601 [SLAVE_SECURITY] = &qhs_security,
1602 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
1603 [SLAVE_TCSR] = &qhs_tcsr,
1604 [SLAVE_TLMM_WEST] = &qhs_tlmm_1,
1605 [SLAVE_TLMM_NORTH] = &qhs_tlmm_2,
1606 [SLAVE_TLMM_SOUTH] = &qhs_tlmm_3,
1607 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1608 [SLAVE_USB3] = &qhs_usb3,
1609 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1610 [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg,
1611 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1612 [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
1613};
1614
1615static const struct qcom_icc_desc sc7180_config_noc = {
1616 .nodes = config_noc_nodes,
1617 .num_nodes = ARRAY_SIZE(config_noc_nodes),
1618 .bcms = config_noc_bcms,
1619 .num_bcms = ARRAY_SIZE(config_noc_bcms),
1620};
1621
1622static struct qcom_icc_node * const dc_noc_nodes[] = {
1623 [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
1624 [SLAVE_GEM_NOC_CFG] = &qhs_gemnoc,
1625 [SLAVE_LLCC_CFG] = &qhs_llcc,
1626};
1627
1628static const struct qcom_icc_desc sc7180_dc_noc = {
1629 .nodes = dc_noc_nodes,
1630 .num_nodes = ARRAY_SIZE(dc_noc_nodes),
1631};
1632
1633static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1634 &bcm_sh0,
1635 &bcm_sh2,
1636 &bcm_sh3,
1637 &bcm_sh4,
1638};
1639
1640static struct qcom_icc_node * const gem_noc_nodes[] = {
1641 [MASTER_APPSS_PROC] = &acm_apps0,
1642 [MASTER_SYS_TCU] = &acm_sys_tcu,
1643 [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
1644 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
1645 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1646 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1647 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1648 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1649 [MASTER_GFX3D] = &qxm_gpu,
1650 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
1651 [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
1652 [SLAVE_LLCC] = &qns_llcc,
1653 [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
1654};
1655
1656static const struct qcom_icc_desc sc7180_gem_noc = {
1657 .nodes = gem_noc_nodes,
1658 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
1659 .bcms = gem_noc_bcms,
1660 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
1661};
1662
1663static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1664 &bcm_acv,
1665 &bcm_mc0,
1666};
1667
1668static struct qcom_icc_node * const mc_virt_nodes[] = {
1669 [MASTER_LLCC] = &llcc_mc,
1670 [SLAVE_EBI1] = &ebi,
1671};
1672
1673static const struct qcom_icc_desc sc7180_mc_virt = {
1674 .nodes = mc_virt_nodes,
1675 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
1676 .bcms = mc_virt_bcms,
1677 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
1678};
1679
1680static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1681 &bcm_mm0,
1682 &bcm_mm1,
1683 &bcm_mm2,
1684};
1685
1686static struct qcom_icc_node * const mmss_noc_nodes[] = {
1687 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
1688 [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
1689 [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
1690 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
1691 [MASTER_MDP0] = &qxm_mdp0,
1692 [MASTER_ROTATOR] = &qxm_rot,
1693 [MASTER_VIDEO_P0] = &qxm_venus0,
1694 [MASTER_VIDEO_PROC] = &qxm_venus_arm9,
1695 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1696 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1697 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1698};
1699
1700static const struct qcom_icc_desc sc7180_mmss_noc = {
1701 .nodes = mmss_noc_nodes,
1702 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1703 .bcms = mmss_noc_bcms,
1704 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1705};
1706
1707static struct qcom_icc_node * const npu_noc_nodes[] = {
1708 [MASTER_NPU_SYS] = &amm_npu_sys,
1709 [MASTER_NPU_NOC_CFG] = &qhm_npu_cfg,
1710 [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0,
1711 [SLAVE_NPU_CP] = &qhs_cp,
1712 [SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon,
1713 [SLAVE_NPU_DPM] = &qhs_dpm,
1714 [SLAVE_ISENSE_CFG] = &qhs_isense,
1715 [SLAVE_NPU_LLM_CFG] = &qhs_llm,
1716 [SLAVE_NPU_TCM] = &qhs_tcm,
1717 [SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys,
1718 [SLAVE_SERVICE_NPU_NOC] = &srvc_noc,
1719};
1720
1721static const struct qcom_icc_desc sc7180_npu_noc = {
1722 .nodes = npu_noc_nodes,
1723 .num_nodes = ARRAY_SIZE(npu_noc_nodes),
1724};
1725
1726static struct qcom_icc_bcm * const qup_virt_bcms[] = {
1727 &bcm_qup0,
1728};
1729
1730static struct qcom_icc_node * const qup_virt_nodes[] = {
1731 [MASTER_QUP_CORE_0] = &qup_core_master_1,
1732 [MASTER_QUP_CORE_1] = &qup_core_master_2,
1733 [SLAVE_QUP_CORE_0] = &qup_core_slave_1,
1734 [SLAVE_QUP_CORE_1] = &qup_core_slave_2,
1735};
1736
1737static const struct qcom_icc_desc sc7180_qup_virt = {
1738 .nodes = qup_virt_nodes,
1739 .num_nodes = ARRAY_SIZE(qup_virt_nodes),
1740 .bcms = qup_virt_bcms,
1741 .num_bcms = ARRAY_SIZE(qup_virt_bcms),
1742};
1743
1744static struct qcom_icc_bcm * const system_noc_bcms[] = {
1745 &bcm_sn0,
1746 &bcm_sn1,
1747 &bcm_sn2,
1748 &bcm_sn3,
1749 &bcm_sn4,
1750 &bcm_sn7,
1751 &bcm_sn9,
1752 &bcm_sn12,
1753};
1754
1755static struct qcom_icc_node * const system_noc_nodes[] = {
1756 [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
1757 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
1758 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
1759 [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
1760 [MASTER_PIMEM] = &qxm_pimem,
1761 [SLAVE_APPSS] = &qhs_apss,
1762 [SLAVE_SNOC_CNOC] = &qns_cnoc,
1763 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
1764 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1765 [SLAVE_IMEM] = &qxs_imem,
1766 [SLAVE_PIMEM] = &qxs_pimem,
1767 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
1768 [SLAVE_QDSS_STM] = &xs_qdss_stm,
1769 [SLAVE_TCU] = &xs_sys_tcu_cfg,
1770};
1771
1772static const struct qcom_icc_desc sc7180_system_noc = {
1773 .nodes = system_noc_nodes,
1774 .num_nodes = ARRAY_SIZE(system_noc_nodes),
1775 .bcms = system_noc_bcms,
1776 .num_bcms = ARRAY_SIZE(system_noc_bcms),
1777};
1778
1779static const struct of_device_id qnoc_of_match[] = {
1780 { .compatible = "qcom,sc7180-aggre1-noc",
1781 .data = &sc7180_aggre1_noc},
1782 { .compatible = "qcom,sc7180-aggre2-noc",
1783 .data = &sc7180_aggre2_noc},
1784 { .compatible = "qcom,sc7180-camnoc-virt",
1785 .data = &sc7180_camnoc_virt},
1786 { .compatible = "qcom,sc7180-compute-noc",
1787 .data = &sc7180_compute_noc},
1788 { .compatible = "qcom,sc7180-config-noc",
1789 .data = &sc7180_config_noc},
1790 { .compatible = "qcom,sc7180-dc-noc",
1791 .data = &sc7180_dc_noc},
1792 { .compatible = "qcom,sc7180-gem-noc",
1793 .data = &sc7180_gem_noc},
1794 { .compatible = "qcom,sc7180-mc-virt",
1795 .data = &sc7180_mc_virt},
1796 { .compatible = "qcom,sc7180-mmss-noc",
1797 .data = &sc7180_mmss_noc},
1798 { .compatible = "qcom,sc7180-npu-noc",
1799 .data = &sc7180_npu_noc},
1800 { .compatible = "qcom,sc7180-qup-virt",
1801 .data = &sc7180_qup_virt},
1802 { .compatible = "qcom,sc7180-system-noc",
1803 .data = &sc7180_system_noc},
1804 { }
1805};
1806MODULE_DEVICE_TABLE(of, qnoc_of_match);
1807
1808static struct platform_driver qnoc_driver = {
1809 .probe = qcom_icc_rpmh_probe,
1810 .remove_new = qcom_icc_rpmh_remove,
1811 .driver = {
1812 .name = "qnoc-sc7180",
1813 .of_match_table = qnoc_of_match,
1814 .sync_state = icc_sync_state,
1815 },
1816};
1817module_platform_driver(qnoc_driver);
1818
1819MODULE_DESCRIPTION("Qualcomm SC7180 NoC driver");
1820MODULE_LICENSE("GPL v2");
1821

source code of linux/drivers/interconnect/qcom/sc7180.c