1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (c) 2021, The Linux Foundation. All rights reserved. |
4 | * |
5 | */ |
6 | |
7 | #include <linux/device.h> |
8 | #include <linux/interconnect.h> |
9 | #include <linux/interconnect-provider.h> |
10 | #include <linux/mod_devicetable.h> |
11 | #include <linux/module.h> |
12 | #include <linux/platform_device.h> |
13 | #include <dt-bindings/interconnect/qcom,sc7280.h> |
14 | |
15 | #include "bcm-voter.h" |
16 | #include "icc-rpmh.h" |
17 | #include "sc7280.h" |
18 | |
19 | static struct qcom_icc_node qhm_qspi = { |
20 | .name = "qhm_qspi" , |
21 | .id = SC7280_MASTER_QSPI_0, |
22 | .channels = 1, |
23 | .buswidth = 4, |
24 | .num_links = 1, |
25 | .links = { SC7280_SLAVE_A1NOC_SNOC }, |
26 | }; |
27 | |
28 | static struct qcom_icc_node qhm_qup0 = { |
29 | .name = "qhm_qup0" , |
30 | .id = SC7280_MASTER_QUP_0, |
31 | .channels = 1, |
32 | .buswidth = 4, |
33 | .num_links = 1, |
34 | .links = { SC7280_SLAVE_A1NOC_SNOC }, |
35 | }; |
36 | |
37 | static struct qcom_icc_node qhm_qup1 = { |
38 | .name = "qhm_qup1" , |
39 | .id = SC7280_MASTER_QUP_1, |
40 | .channels = 1, |
41 | .buswidth = 4, |
42 | .num_links = 1, |
43 | .links = { SC7280_SLAVE_A1NOC_SNOC }, |
44 | }; |
45 | |
46 | static struct qcom_icc_node qnm_a1noc_cfg = { |
47 | .name = "qnm_a1noc_cfg" , |
48 | .id = SC7280_MASTER_A1NOC_CFG, |
49 | .channels = 1, |
50 | .buswidth = 4, |
51 | .num_links = 1, |
52 | .links = { SC7280_SLAVE_SERVICE_A1NOC }, |
53 | }; |
54 | |
55 | static struct qcom_icc_node xm_sdc1 = { |
56 | .name = "xm_sdc1" , |
57 | .id = SC7280_MASTER_SDCC_1, |
58 | .channels = 1, |
59 | .buswidth = 8, |
60 | .num_links = 1, |
61 | .links = { SC7280_SLAVE_A1NOC_SNOC }, |
62 | }; |
63 | |
64 | static struct qcom_icc_node xm_sdc2 = { |
65 | .name = "xm_sdc2" , |
66 | .id = SC7280_MASTER_SDCC_2, |
67 | .channels = 1, |
68 | .buswidth = 8, |
69 | .num_links = 1, |
70 | .links = { SC7280_SLAVE_A1NOC_SNOC }, |
71 | }; |
72 | |
73 | static struct qcom_icc_node xm_sdc4 = { |
74 | .name = "xm_sdc4" , |
75 | .id = SC7280_MASTER_SDCC_4, |
76 | .channels = 1, |
77 | .buswidth = 8, |
78 | .num_links = 1, |
79 | .links = { SC7280_SLAVE_A1NOC_SNOC }, |
80 | }; |
81 | |
82 | static struct qcom_icc_node xm_ufs_mem = { |
83 | .name = "xm_ufs_mem" , |
84 | .id = SC7280_MASTER_UFS_MEM, |
85 | .channels = 1, |
86 | .buswidth = 8, |
87 | .num_links = 1, |
88 | .links = { SC7280_SLAVE_A1NOC_SNOC }, |
89 | }; |
90 | |
91 | static struct qcom_icc_node xm_usb2 = { |
92 | .name = "xm_usb2" , |
93 | .id = SC7280_MASTER_USB2, |
94 | .channels = 1, |
95 | .buswidth = 8, |
96 | .num_links = 1, |
97 | .links = { SC7280_SLAVE_A1NOC_SNOC }, |
98 | }; |
99 | |
100 | static struct qcom_icc_node xm_usb3_0 = { |
101 | .name = "xm_usb3_0" , |
102 | .id = SC7280_MASTER_USB3_0, |
103 | .channels = 1, |
104 | .buswidth = 8, |
105 | .num_links = 1, |
106 | .links = { SC7280_SLAVE_A1NOC_SNOC }, |
107 | }; |
108 | |
109 | static struct qcom_icc_node qhm_qdss_bam = { |
110 | .name = "qhm_qdss_bam" , |
111 | .id = SC7280_MASTER_QDSS_BAM, |
112 | .channels = 1, |
113 | .buswidth = 4, |
114 | .num_links = 1, |
115 | .links = { SC7280_SLAVE_A2NOC_SNOC }, |
116 | }; |
117 | |
118 | static struct qcom_icc_node qnm_a2noc_cfg = { |
119 | .name = "qnm_a2noc_cfg" , |
120 | .id = SC7280_MASTER_A2NOC_CFG, |
121 | .channels = 1, |
122 | .buswidth = 4, |
123 | .num_links = 1, |
124 | .links = { SC7280_SLAVE_SERVICE_A2NOC }, |
125 | }; |
126 | |
127 | static struct qcom_icc_node qnm_cnoc_datapath = { |
128 | .name = "qnm_cnoc_datapath" , |
129 | .id = SC7280_MASTER_CNOC_A2NOC, |
130 | .channels = 1, |
131 | .buswidth = 8, |
132 | .num_links = 1, |
133 | .links = { SC7280_SLAVE_A2NOC_SNOC }, |
134 | }; |
135 | |
136 | static struct qcom_icc_node qxm_crypto = { |
137 | .name = "qxm_crypto" , |
138 | .id = SC7280_MASTER_CRYPTO, |
139 | .channels = 1, |
140 | .buswidth = 8, |
141 | .num_links = 1, |
142 | .links = { SC7280_SLAVE_A2NOC_SNOC }, |
143 | }; |
144 | |
145 | static struct qcom_icc_node qxm_ipa = { |
146 | .name = "qxm_ipa" , |
147 | .id = SC7280_MASTER_IPA, |
148 | .channels = 1, |
149 | .buswidth = 8, |
150 | .num_links = 1, |
151 | .links = { SC7280_SLAVE_A2NOC_SNOC }, |
152 | }; |
153 | |
154 | static struct qcom_icc_node xm_pcie3_0 = { |
155 | .name = "xm_pcie3_0" , |
156 | .id = SC7280_MASTER_PCIE_0, |
157 | .channels = 1, |
158 | .buswidth = 8, |
159 | .num_links = 1, |
160 | .links = { SC7280_SLAVE_ANOC_PCIE_GEM_NOC }, |
161 | }; |
162 | |
163 | static struct qcom_icc_node xm_pcie3_1 = { |
164 | .name = "xm_pcie3_1" , |
165 | .id = SC7280_MASTER_PCIE_1, |
166 | .channels = 1, |
167 | .buswidth = 8, |
168 | .links = { SC7280_SLAVE_ANOC_PCIE_GEM_NOC }, |
169 | }; |
170 | |
171 | static struct qcom_icc_node xm_qdss_etr = { |
172 | .name = "xm_qdss_etr" , |
173 | .id = SC7280_MASTER_QDSS_ETR, |
174 | .channels = 1, |
175 | .buswidth = 8, |
176 | .num_links = 1, |
177 | .links = { SC7280_SLAVE_A2NOC_SNOC }, |
178 | }; |
179 | |
180 | static struct qcom_icc_node qup0_core_master = { |
181 | .name = "qup0_core_master" , |
182 | .id = SC7280_MASTER_QUP_CORE_0, |
183 | .channels = 1, |
184 | .buswidth = 4, |
185 | .num_links = 1, |
186 | .links = { SC7280_SLAVE_QUP_CORE_0 }, |
187 | }; |
188 | |
189 | static struct qcom_icc_node qup1_core_master = { |
190 | .name = "qup1_core_master" , |
191 | .id = SC7280_MASTER_QUP_CORE_1, |
192 | .channels = 1, |
193 | .buswidth = 4, |
194 | .num_links = 1, |
195 | .links = { SC7280_SLAVE_QUP_CORE_1 }, |
196 | }; |
197 | |
198 | static struct qcom_icc_node qnm_cnoc3_cnoc2 = { |
199 | .name = "qnm_cnoc3_cnoc2" , |
200 | .id = SC7280_MASTER_CNOC3_CNOC2, |
201 | .channels = 1, |
202 | .buswidth = 8, |
203 | .num_links = 44, |
204 | .links = { SC7280_SLAVE_AHB2PHY_SOUTH, SC7280_SLAVE_AHB2PHY_NORTH, |
205 | SC7280_SLAVE_CAMERA_CFG, SC7280_SLAVE_CLK_CTL, |
206 | SC7280_SLAVE_CDSP_CFG, SC7280_SLAVE_RBCPR_CX_CFG, |
207 | SC7280_SLAVE_RBCPR_MX_CFG, SC7280_SLAVE_CRYPTO_0_CFG, |
208 | SC7280_SLAVE_CX_RDPM, SC7280_SLAVE_DCC_CFG, |
209 | SC7280_SLAVE_DISPLAY_CFG, SC7280_SLAVE_GFX3D_CFG, |
210 | SC7280_SLAVE_HWKM, SC7280_SLAVE_IMEM_CFG, |
211 | SC7280_SLAVE_IPA_CFG, SC7280_SLAVE_IPC_ROUTER_CFG, |
212 | SC7280_SLAVE_LPASS, SC7280_SLAVE_CNOC_MSS, |
213 | SC7280_SLAVE_MX_RDPM, SC7280_SLAVE_PCIE_0_CFG, |
214 | SC7280_SLAVE_PCIE_1_CFG, SC7280_SLAVE_PDM, |
215 | SC7280_SLAVE_PIMEM_CFG, SC7280_SLAVE_PKA_WRAPPER_CFG, |
216 | SC7280_SLAVE_PMU_WRAPPER_CFG, SC7280_SLAVE_QDSS_CFG, |
217 | SC7280_SLAVE_QSPI_0, SC7280_SLAVE_QUP_0, |
218 | SC7280_SLAVE_QUP_1, SC7280_SLAVE_SDCC_1, |
219 | SC7280_SLAVE_SDCC_2, SC7280_SLAVE_SDCC_4, |
220 | SC7280_SLAVE_SECURITY, SC7280_SLAVE_TCSR, |
221 | SC7280_SLAVE_TLMM, SC7280_SLAVE_UFS_MEM_CFG, |
222 | SC7280_SLAVE_USB2, SC7280_SLAVE_USB3_0, |
223 | SC7280_SLAVE_VENUS_CFG, SC7280_SLAVE_VSENSE_CTRL_CFG, |
224 | SC7280_SLAVE_A1NOC_CFG, SC7280_SLAVE_A2NOC_CFG, |
225 | SC7280_SLAVE_CNOC_MNOC_CFG, SC7280_SLAVE_SNOC_CFG }, |
226 | }; |
227 | |
228 | static struct qcom_icc_node xm_qdss_dap = { |
229 | .name = "xm_qdss_dap" , |
230 | .id = SC7280_MASTER_QDSS_DAP, |
231 | .channels = 1, |
232 | .buswidth = 8, |
233 | .num_links = 45, |
234 | .links = { SC7280_SLAVE_AHB2PHY_SOUTH, SC7280_SLAVE_AHB2PHY_NORTH, |
235 | SC7280_SLAVE_CAMERA_CFG, SC7280_SLAVE_CLK_CTL, |
236 | SC7280_SLAVE_CDSP_CFG, SC7280_SLAVE_RBCPR_CX_CFG, |
237 | SC7280_SLAVE_RBCPR_MX_CFG, SC7280_SLAVE_CRYPTO_0_CFG, |
238 | SC7280_SLAVE_CX_RDPM, SC7280_SLAVE_DCC_CFG, |
239 | SC7280_SLAVE_DISPLAY_CFG, SC7280_SLAVE_GFX3D_CFG, |
240 | SC7280_SLAVE_HWKM, SC7280_SLAVE_IMEM_CFG, |
241 | SC7280_SLAVE_IPA_CFG, SC7280_SLAVE_IPC_ROUTER_CFG, |
242 | SC7280_SLAVE_LPASS, SC7280_SLAVE_CNOC_MSS, |
243 | SC7280_SLAVE_MX_RDPM, SC7280_SLAVE_PCIE_0_CFG, |
244 | SC7280_SLAVE_PCIE_1_CFG, SC7280_SLAVE_PDM, |
245 | SC7280_SLAVE_PIMEM_CFG, SC7280_SLAVE_PKA_WRAPPER_CFG, |
246 | SC7280_SLAVE_PMU_WRAPPER_CFG, SC7280_SLAVE_QDSS_CFG, |
247 | SC7280_SLAVE_QSPI_0, SC7280_SLAVE_QUP_0, |
248 | SC7280_SLAVE_QUP_1, SC7280_SLAVE_SDCC_1, |
249 | SC7280_SLAVE_SDCC_2, SC7280_SLAVE_SDCC_4, |
250 | SC7280_SLAVE_SECURITY, SC7280_SLAVE_TCSR, |
251 | SC7280_SLAVE_TLMM, SC7280_SLAVE_UFS_MEM_CFG, |
252 | SC7280_SLAVE_USB2, SC7280_SLAVE_USB3_0, |
253 | SC7280_SLAVE_VENUS_CFG, SC7280_SLAVE_VSENSE_CTRL_CFG, |
254 | SC7280_SLAVE_A1NOC_CFG, SC7280_SLAVE_A2NOC_CFG, |
255 | SC7280_SLAVE_CNOC2_CNOC3, SC7280_SLAVE_CNOC_MNOC_CFG, |
256 | SC7280_SLAVE_SNOC_CFG }, |
257 | }; |
258 | |
259 | static struct qcom_icc_node qnm_cnoc2_cnoc3 = { |
260 | .name = "qnm_cnoc2_cnoc3" , |
261 | .id = SC7280_MASTER_CNOC2_CNOC3, |
262 | .channels = 1, |
263 | .buswidth = 8, |
264 | .num_links = 9, |
265 | .links = { SC7280_SLAVE_AOSS, SC7280_SLAVE_APPSS, |
266 | SC7280_SLAVE_CNOC_A2NOC, SC7280_SLAVE_DDRSS_CFG, |
267 | SC7280_SLAVE_BOOT_IMEM, SC7280_SLAVE_IMEM, |
268 | SC7280_SLAVE_PIMEM, SC7280_SLAVE_QDSS_STM, |
269 | SC7280_SLAVE_TCU }, |
270 | }; |
271 | |
272 | static struct qcom_icc_node qnm_gemnoc_cnoc = { |
273 | .name = "qnm_gemnoc_cnoc" , |
274 | .id = SC7280_MASTER_GEM_NOC_CNOC, |
275 | .channels = 1, |
276 | .buswidth = 16, |
277 | .num_links = 9, |
278 | .links = { SC7280_SLAVE_AOSS, SC7280_SLAVE_APPSS, |
279 | SC7280_SLAVE_CNOC3_CNOC2, SC7280_SLAVE_DDRSS_CFG, |
280 | SC7280_SLAVE_BOOT_IMEM, SC7280_SLAVE_IMEM, |
281 | SC7280_SLAVE_PIMEM, SC7280_SLAVE_QDSS_STM, |
282 | SC7280_SLAVE_TCU }, |
283 | }; |
284 | |
285 | static struct qcom_icc_node qnm_gemnoc_pcie = { |
286 | .name = "qnm_gemnoc_pcie" , |
287 | .id = SC7280_MASTER_GEM_NOC_PCIE_SNOC, |
288 | .channels = 1, |
289 | .buswidth = 8, |
290 | .num_links = 2, |
291 | .links = { SC7280_SLAVE_PCIE_0, SC7280_SLAVE_PCIE_1 }, |
292 | }; |
293 | |
294 | static struct qcom_icc_node qnm_cnoc_dc_noc = { |
295 | .name = "qnm_cnoc_dc_noc" , |
296 | .id = SC7280_MASTER_CNOC_DC_NOC, |
297 | .channels = 1, |
298 | .buswidth = 4, |
299 | .num_links = 2, |
300 | .links = { SC7280_SLAVE_LLCC_CFG, SC7280_SLAVE_GEM_NOC_CFG }, |
301 | }; |
302 | |
303 | static struct qcom_icc_node alm_gpu_tcu = { |
304 | .name = "alm_gpu_tcu" , |
305 | .id = SC7280_MASTER_GPU_TCU, |
306 | .channels = 1, |
307 | .buswidth = 8, |
308 | .num_links = 2, |
309 | .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, |
310 | }; |
311 | |
312 | static struct qcom_icc_node alm_sys_tcu = { |
313 | .name = "alm_sys_tcu" , |
314 | .id = SC7280_MASTER_SYS_TCU, |
315 | .channels = 1, |
316 | .buswidth = 8, |
317 | .num_links = 2, |
318 | .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, |
319 | }; |
320 | |
321 | static struct qcom_icc_node chm_apps = { |
322 | .name = "chm_apps" , |
323 | .id = SC7280_MASTER_APPSS_PROC, |
324 | .channels = 1, |
325 | .buswidth = 32, |
326 | .num_links = 3, |
327 | .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC, |
328 | SC7280_SLAVE_MEM_NOC_PCIE_SNOC }, |
329 | }; |
330 | |
331 | static struct qcom_icc_node qnm_cmpnoc = { |
332 | .name = "qnm_cmpnoc" , |
333 | .id = SC7280_MASTER_COMPUTE_NOC, |
334 | .channels = 2, |
335 | .buswidth = 32, |
336 | .num_links = 2, |
337 | .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, |
338 | }; |
339 | |
340 | static struct qcom_icc_node qnm_gemnoc_cfg = { |
341 | .name = "qnm_gemnoc_cfg" , |
342 | .id = SC7280_MASTER_GEM_NOC_CFG, |
343 | .channels = 1, |
344 | .buswidth = 4, |
345 | .num_links = 5, |
346 | .links = { SC7280_SLAVE_MSS_PROC_MS_MPU_CFG, SC7280_SLAVE_MCDMA_MS_MPU_CFG, |
347 | SC7280_SLAVE_SERVICE_GEM_NOC_1, SC7280_SLAVE_SERVICE_GEM_NOC_2, |
348 | SC7280_SLAVE_SERVICE_GEM_NOC }, |
349 | }; |
350 | |
351 | static struct qcom_icc_node qnm_gpu = { |
352 | .name = "qnm_gpu" , |
353 | .id = SC7280_MASTER_GFX3D, |
354 | .channels = 2, |
355 | .buswidth = 32, |
356 | .num_links = 2, |
357 | .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, |
358 | }; |
359 | |
360 | static struct qcom_icc_node qnm_mnoc_hf = { |
361 | .name = "qnm_mnoc_hf" , |
362 | .id = SC7280_MASTER_MNOC_HF_MEM_NOC, |
363 | .channels = 2, |
364 | .buswidth = 32, |
365 | .num_links = 1, |
366 | .links = { SC7280_SLAVE_LLCC }, |
367 | }; |
368 | |
369 | static struct qcom_icc_node qnm_mnoc_sf = { |
370 | .name = "qnm_mnoc_sf" , |
371 | .id = SC7280_MASTER_MNOC_SF_MEM_NOC, |
372 | .channels = 1, |
373 | .buswidth = 32, |
374 | .num_links = 2, |
375 | .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, |
376 | }; |
377 | |
378 | static struct qcom_icc_node qnm_pcie = { |
379 | .name = "qnm_pcie" , |
380 | .id = SC7280_MASTER_ANOC_PCIE_GEM_NOC, |
381 | .channels = 1, |
382 | .buswidth = 16, |
383 | .num_links = 2, |
384 | .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, |
385 | }; |
386 | |
387 | static struct qcom_icc_node qnm_snoc_gc = { |
388 | .name = "qnm_snoc_gc" , |
389 | .id = SC7280_MASTER_SNOC_GC_MEM_NOC, |
390 | .channels = 1, |
391 | .buswidth = 8, |
392 | .num_links = 1, |
393 | .links = { SC7280_SLAVE_LLCC }, |
394 | }; |
395 | |
396 | static struct qcom_icc_node qnm_snoc_sf = { |
397 | .name = "qnm_snoc_sf" , |
398 | .id = SC7280_MASTER_SNOC_SF_MEM_NOC, |
399 | .channels = 1, |
400 | .buswidth = 16, |
401 | .num_links = 3, |
402 | .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC, |
403 | SC7280_SLAVE_MEM_NOC_PCIE_SNOC }, |
404 | }; |
405 | |
406 | static struct qcom_icc_node qhm_config_noc = { |
407 | .name = "qhm_config_noc" , |
408 | .id = SC7280_MASTER_CNOC_LPASS_AG_NOC, |
409 | .channels = 1, |
410 | .buswidth = 4, |
411 | .num_links = 6, |
412 | .links = { SC7280_SLAVE_LPASS_CORE_CFG, SC7280_SLAVE_LPASS_LPI_CFG, |
413 | SC7280_SLAVE_LPASS_MPU_CFG, SC7280_SLAVE_LPASS_TOP_CFG, |
414 | SC7280_SLAVE_SERVICES_LPASS_AML_NOC, SC7280_SLAVE_SERVICE_LPASS_AG_NOC }, |
415 | }; |
416 | |
417 | static struct qcom_icc_node llcc_mc = { |
418 | .name = "llcc_mc" , |
419 | .id = SC7280_MASTER_LLCC, |
420 | .channels = 2, |
421 | .buswidth = 4, |
422 | .num_links = 1, |
423 | .links = { SC7280_SLAVE_EBI1 }, |
424 | }; |
425 | |
426 | static struct qcom_icc_node qnm_mnoc_cfg = { |
427 | .name = "qnm_mnoc_cfg" , |
428 | .id = SC7280_MASTER_CNOC_MNOC_CFG, |
429 | .channels = 1, |
430 | .buswidth = 4, |
431 | .num_links = 1, |
432 | .links = { SC7280_SLAVE_SERVICE_MNOC }, |
433 | }; |
434 | |
435 | static struct qcom_icc_node qnm_video0 = { |
436 | .name = "qnm_video0" , |
437 | .id = SC7280_MASTER_VIDEO_P0, |
438 | .channels = 1, |
439 | .buswidth = 32, |
440 | .num_links = 1, |
441 | .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC }, |
442 | }; |
443 | |
444 | static struct qcom_icc_node qnm_video_cpu = { |
445 | .name = "qnm_video_cpu" , |
446 | .id = SC7280_MASTER_VIDEO_PROC, |
447 | .channels = 1, |
448 | .buswidth = 8, |
449 | .num_links = 1, |
450 | .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC }, |
451 | }; |
452 | |
453 | static struct qcom_icc_node qxm_camnoc_hf = { |
454 | .name = "qxm_camnoc_hf" , |
455 | .id = SC7280_MASTER_CAMNOC_HF, |
456 | .channels = 2, |
457 | .buswidth = 32, |
458 | .num_links = 1, |
459 | .links = { SC7280_SLAVE_MNOC_HF_MEM_NOC }, |
460 | }; |
461 | |
462 | static struct qcom_icc_node qxm_camnoc_icp = { |
463 | .name = "qxm_camnoc_icp" , |
464 | .id = SC7280_MASTER_CAMNOC_ICP, |
465 | .channels = 1, |
466 | .buswidth = 8, |
467 | .num_links = 1, |
468 | .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC }, |
469 | }; |
470 | |
471 | static struct qcom_icc_node qxm_camnoc_sf = { |
472 | .name = "qxm_camnoc_sf" , |
473 | .id = SC7280_MASTER_CAMNOC_SF, |
474 | .channels = 1, |
475 | .buswidth = 32, |
476 | .num_links = 1, |
477 | .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC }, |
478 | }; |
479 | |
480 | static struct qcom_icc_node qxm_mdp0 = { |
481 | .name = "qxm_mdp0" , |
482 | .id = SC7280_MASTER_MDP0, |
483 | .channels = 1, |
484 | .buswidth = 32, |
485 | .num_links = 1, |
486 | .links = { SC7280_SLAVE_MNOC_HF_MEM_NOC }, |
487 | }; |
488 | |
489 | static struct qcom_icc_node qhm_nsp_noc_config = { |
490 | .name = "qhm_nsp_noc_config" , |
491 | .id = SC7280_MASTER_CDSP_NOC_CFG, |
492 | .channels = 1, |
493 | .buswidth = 4, |
494 | .num_links = 1, |
495 | .links = { SC7280_SLAVE_SERVICE_NSP_NOC }, |
496 | }; |
497 | |
498 | static struct qcom_icc_node qxm_nsp = { |
499 | .name = "qxm_nsp" , |
500 | .id = SC7280_MASTER_CDSP_PROC, |
501 | .channels = 2, |
502 | .buswidth = 32, |
503 | .num_links = 1, |
504 | .links = { SC7280_SLAVE_CDSP_MEM_NOC }, |
505 | }; |
506 | |
507 | static struct qcom_icc_node qnm_aggre1_noc = { |
508 | .name = "qnm_aggre1_noc" , |
509 | .id = SC7280_MASTER_A1NOC_SNOC, |
510 | .channels = 1, |
511 | .buswidth = 16, |
512 | .num_links = 1, |
513 | .links = { SC7280_SLAVE_SNOC_GEM_NOC_SF }, |
514 | }; |
515 | |
516 | static struct qcom_icc_node qnm_aggre2_noc = { |
517 | .name = "qnm_aggre2_noc" , |
518 | .id = SC7280_MASTER_A2NOC_SNOC, |
519 | .channels = 1, |
520 | .buswidth = 16, |
521 | .num_links = 1, |
522 | .links = { SC7280_SLAVE_SNOC_GEM_NOC_SF }, |
523 | }; |
524 | |
525 | static struct qcom_icc_node qnm_snoc_cfg = { |
526 | .name = "qnm_snoc_cfg" , |
527 | .id = SC7280_MASTER_SNOC_CFG, |
528 | .channels = 1, |
529 | .buswidth = 4, |
530 | .num_links = 1, |
531 | .links = { SC7280_SLAVE_SERVICE_SNOC }, |
532 | }; |
533 | |
534 | static struct qcom_icc_node qxm_pimem = { |
535 | .name = "qxm_pimem" , |
536 | .id = SC7280_MASTER_PIMEM, |
537 | .channels = 1, |
538 | .buswidth = 8, |
539 | .num_links = 1, |
540 | .links = { SC7280_SLAVE_SNOC_GEM_NOC_GC }, |
541 | }; |
542 | |
543 | static struct qcom_icc_node xm_gic = { |
544 | .name = "xm_gic" , |
545 | .id = SC7280_MASTER_GIC, |
546 | .channels = 1, |
547 | .buswidth = 8, |
548 | .num_links = 1, |
549 | .links = { SC7280_SLAVE_SNOC_GEM_NOC_GC }, |
550 | }; |
551 | |
552 | static struct qcom_icc_node qns_a1noc_snoc = { |
553 | .name = "qns_a1noc_snoc" , |
554 | .id = SC7280_SLAVE_A1NOC_SNOC, |
555 | .channels = 1, |
556 | .buswidth = 16, |
557 | .num_links = 1, |
558 | .links = { SC7280_MASTER_A1NOC_SNOC }, |
559 | }; |
560 | |
561 | static struct qcom_icc_node srvc_aggre1_noc = { |
562 | .name = "srvc_aggre1_noc" , |
563 | .id = SC7280_SLAVE_SERVICE_A1NOC, |
564 | .channels = 1, |
565 | .buswidth = 4, |
566 | .num_links = 0, |
567 | }; |
568 | |
569 | static struct qcom_icc_node qns_a2noc_snoc = { |
570 | .name = "qns_a2noc_snoc" , |
571 | .id = SC7280_SLAVE_A2NOC_SNOC, |
572 | .channels = 1, |
573 | .buswidth = 16, |
574 | .num_links = 1, |
575 | .links = { SC7280_MASTER_A2NOC_SNOC }, |
576 | }; |
577 | |
578 | static struct qcom_icc_node qns_pcie_mem_noc = { |
579 | .name = "qns_pcie_mem_noc" , |
580 | .id = SC7280_SLAVE_ANOC_PCIE_GEM_NOC, |
581 | .channels = 1, |
582 | .buswidth = 16, |
583 | .num_links = 1, |
584 | .links = { SC7280_MASTER_ANOC_PCIE_GEM_NOC }, |
585 | }; |
586 | |
587 | static struct qcom_icc_node srvc_aggre2_noc = { |
588 | .name = "srvc_aggre2_noc" , |
589 | .id = SC7280_SLAVE_SERVICE_A2NOC, |
590 | .channels = 1, |
591 | .buswidth = 4, |
592 | .num_links = 0, |
593 | }; |
594 | |
595 | static struct qcom_icc_node qup0_core_slave = { |
596 | .name = "qup0_core_slave" , |
597 | .id = SC7280_SLAVE_QUP_CORE_0, |
598 | .channels = 1, |
599 | .buswidth = 4, |
600 | .num_links = 0, |
601 | }; |
602 | |
603 | static struct qcom_icc_node qup1_core_slave = { |
604 | .name = "qup1_core_slave" , |
605 | .id = SC7280_SLAVE_QUP_CORE_1, |
606 | .channels = 1, |
607 | .buswidth = 4, |
608 | .num_links = 0, |
609 | }; |
610 | |
611 | static struct qcom_icc_node qhs_ahb2phy0 = { |
612 | .name = "qhs_ahb2phy0" , |
613 | .id = SC7280_SLAVE_AHB2PHY_SOUTH, |
614 | .channels = 1, |
615 | .buswidth = 4, |
616 | .num_links = 0, |
617 | }; |
618 | |
619 | static struct qcom_icc_node qhs_ahb2phy1 = { |
620 | .name = "qhs_ahb2phy1" , |
621 | .id = SC7280_SLAVE_AHB2PHY_NORTH, |
622 | .channels = 1, |
623 | .buswidth = 4, |
624 | .num_links = 0, |
625 | }; |
626 | |
627 | static struct qcom_icc_node qhs_camera_cfg = { |
628 | .name = "qhs_camera_cfg" , |
629 | .id = SC7280_SLAVE_CAMERA_CFG, |
630 | .channels = 1, |
631 | .buswidth = 4, |
632 | .num_links = 0, |
633 | }; |
634 | |
635 | static struct qcom_icc_node qhs_clk_ctl = { |
636 | .name = "qhs_clk_ctl" , |
637 | .id = SC7280_SLAVE_CLK_CTL, |
638 | .channels = 1, |
639 | .buswidth = 4, |
640 | .num_links = 0, |
641 | }; |
642 | |
643 | static struct qcom_icc_node qhs_compute_cfg = { |
644 | .name = "qhs_compute_cfg" , |
645 | .id = SC7280_SLAVE_CDSP_CFG, |
646 | .channels = 1, |
647 | .buswidth = 4, |
648 | .num_links = 1, |
649 | .links = { SC7280_MASTER_CDSP_NOC_CFG }, |
650 | }; |
651 | |
652 | static struct qcom_icc_node qhs_cpr_cx = { |
653 | .name = "qhs_cpr_cx" , |
654 | .id = SC7280_SLAVE_RBCPR_CX_CFG, |
655 | .channels = 1, |
656 | .buswidth = 4, |
657 | .num_links = 0, |
658 | }; |
659 | |
660 | static struct qcom_icc_node qhs_cpr_mx = { |
661 | .name = "qhs_cpr_mx" , |
662 | .id = SC7280_SLAVE_RBCPR_MX_CFG, |
663 | .channels = 1, |
664 | .buswidth = 4, |
665 | .num_links = 0, |
666 | }; |
667 | |
668 | static struct qcom_icc_node qhs_crypto0_cfg = { |
669 | .name = "qhs_crypto0_cfg" , |
670 | .id = SC7280_SLAVE_CRYPTO_0_CFG, |
671 | .channels = 1, |
672 | .buswidth = 4, |
673 | .num_links = 0, |
674 | }; |
675 | |
676 | static struct qcom_icc_node qhs_cx_rdpm = { |
677 | .name = "qhs_cx_rdpm" , |
678 | .id = SC7280_SLAVE_CX_RDPM, |
679 | .channels = 1, |
680 | .buswidth = 4, |
681 | .num_links = 0, |
682 | }; |
683 | |
684 | static struct qcom_icc_node qhs_dcc_cfg = { |
685 | .name = "qhs_dcc_cfg" , |
686 | .id = SC7280_SLAVE_DCC_CFG, |
687 | .channels = 1, |
688 | .buswidth = 4, |
689 | .num_links = 0, |
690 | }; |
691 | |
692 | static struct qcom_icc_node qhs_display_cfg = { |
693 | .name = "qhs_display_cfg" , |
694 | .id = SC7280_SLAVE_DISPLAY_CFG, |
695 | .channels = 1, |
696 | .buswidth = 4, |
697 | .num_links = 0, |
698 | }; |
699 | |
700 | static struct qcom_icc_node qhs_gpuss_cfg = { |
701 | .name = "qhs_gpuss_cfg" , |
702 | .id = SC7280_SLAVE_GFX3D_CFG, |
703 | .channels = 1, |
704 | .buswidth = 8, |
705 | .num_links = 0, |
706 | }; |
707 | |
708 | static struct qcom_icc_node qhs_hwkm = { |
709 | .name = "qhs_hwkm" , |
710 | .id = SC7280_SLAVE_HWKM, |
711 | .channels = 1, |
712 | .buswidth = 4, |
713 | .num_links = 0, |
714 | }; |
715 | |
716 | static struct qcom_icc_node qhs_imem_cfg = { |
717 | .name = "qhs_imem_cfg" , |
718 | .id = SC7280_SLAVE_IMEM_CFG, |
719 | .channels = 1, |
720 | .buswidth = 4, |
721 | .num_links = 0, |
722 | }; |
723 | |
724 | static struct qcom_icc_node qhs_ipa = { |
725 | .name = "qhs_ipa" , |
726 | .id = SC7280_SLAVE_IPA_CFG, |
727 | .channels = 1, |
728 | .buswidth = 4, |
729 | .num_links = 0, |
730 | }; |
731 | |
732 | static struct qcom_icc_node qhs_ipc_router = { |
733 | .name = "qhs_ipc_router" , |
734 | .id = SC7280_SLAVE_IPC_ROUTER_CFG, |
735 | .channels = 1, |
736 | .buswidth = 4, |
737 | .num_links = 0, |
738 | }; |
739 | |
740 | static struct qcom_icc_node qhs_lpass_cfg = { |
741 | .name = "qhs_lpass_cfg" , |
742 | .id = SC7280_SLAVE_LPASS, |
743 | .channels = 1, |
744 | .buswidth = 4, |
745 | .num_links = 1, |
746 | .links = { SC7280_MASTER_CNOC_LPASS_AG_NOC }, |
747 | }; |
748 | |
749 | static struct qcom_icc_node qhs_mss_cfg = { |
750 | .name = "qhs_mss_cfg" , |
751 | .id = SC7280_SLAVE_CNOC_MSS, |
752 | .channels = 1, |
753 | .buswidth = 4, |
754 | .num_links = 0, |
755 | }; |
756 | |
757 | static struct qcom_icc_node qhs_mx_rdpm = { |
758 | .name = "qhs_mx_rdpm" , |
759 | .id = SC7280_SLAVE_MX_RDPM, |
760 | .channels = 1, |
761 | .buswidth = 4, |
762 | .num_links = 0, |
763 | }; |
764 | |
765 | static struct qcom_icc_node qhs_pcie0_cfg = { |
766 | .name = "qhs_pcie0_cfg" , |
767 | .id = SC7280_SLAVE_PCIE_0_CFG, |
768 | .channels = 1, |
769 | .buswidth = 4, |
770 | .num_links = 0, |
771 | }; |
772 | |
773 | static struct qcom_icc_node qhs_pcie1_cfg = { |
774 | .name = "qhs_pcie1_cfg" , |
775 | .id = SC7280_SLAVE_PCIE_1_CFG, |
776 | .channels = 1, |
777 | .buswidth = 4, |
778 | .num_links = 0, |
779 | }; |
780 | |
781 | static struct qcom_icc_node qhs_pdm = { |
782 | .name = "qhs_pdm" , |
783 | .id = SC7280_SLAVE_PDM, |
784 | .channels = 1, |
785 | .buswidth = 4, |
786 | .num_links = 0, |
787 | }; |
788 | |
789 | static struct qcom_icc_node qhs_pimem_cfg = { |
790 | .name = "qhs_pimem_cfg" , |
791 | .id = SC7280_SLAVE_PIMEM_CFG, |
792 | .channels = 1, |
793 | .buswidth = 4, |
794 | .num_links = 0, |
795 | }; |
796 | |
797 | static struct qcom_icc_node qhs_pka_wrapper_cfg = { |
798 | .name = "qhs_pka_wrapper_cfg" , |
799 | .id = SC7280_SLAVE_PKA_WRAPPER_CFG, |
800 | .channels = 1, |
801 | .buswidth = 4, |
802 | .num_links = 0, |
803 | }; |
804 | |
805 | static struct qcom_icc_node qhs_pmu_wrapper_cfg = { |
806 | .name = "qhs_pmu_wrapper_cfg" , |
807 | .id = SC7280_SLAVE_PMU_WRAPPER_CFG, |
808 | .channels = 1, |
809 | .buswidth = 4, |
810 | .num_links = 0, |
811 | }; |
812 | |
813 | static struct qcom_icc_node qhs_qdss_cfg = { |
814 | .name = "qhs_qdss_cfg" , |
815 | .id = SC7280_SLAVE_QDSS_CFG, |
816 | .channels = 1, |
817 | .buswidth = 4, |
818 | .num_links = 0, |
819 | }; |
820 | |
821 | static struct qcom_icc_node qhs_qspi = { |
822 | .name = "qhs_qspi" , |
823 | .id = SC7280_SLAVE_QSPI_0, |
824 | .channels = 1, |
825 | .buswidth = 4, |
826 | .num_links = 0, |
827 | }; |
828 | |
829 | static struct qcom_icc_node qhs_qup0 = { |
830 | .name = "qhs_qup0" , |
831 | .id = SC7280_SLAVE_QUP_0, |
832 | .channels = 1, |
833 | .buswidth = 4, |
834 | .num_links = 0, |
835 | }; |
836 | |
837 | static struct qcom_icc_node qhs_qup1 = { |
838 | .name = "qhs_qup1" , |
839 | .id = SC7280_SLAVE_QUP_1, |
840 | .channels = 1, |
841 | .buswidth = 4, |
842 | .num_links = 0, |
843 | }; |
844 | |
845 | static struct qcom_icc_node qhs_sdc1 = { |
846 | .name = "qhs_sdc1" , |
847 | .id = SC7280_SLAVE_SDCC_1, |
848 | .channels = 1, |
849 | .buswidth = 4, |
850 | .num_links = 0, |
851 | }; |
852 | |
853 | static struct qcom_icc_node qhs_sdc2 = { |
854 | .name = "qhs_sdc2" , |
855 | .id = SC7280_SLAVE_SDCC_2, |
856 | .channels = 1, |
857 | .buswidth = 4, |
858 | .num_links = 0, |
859 | }; |
860 | |
861 | static struct qcom_icc_node qhs_sdc4 = { |
862 | .name = "qhs_sdc4" , |
863 | .id = SC7280_SLAVE_SDCC_4, |
864 | .channels = 1, |
865 | .buswidth = 4, |
866 | .num_links = 0, |
867 | }; |
868 | |
869 | static struct qcom_icc_node qhs_security = { |
870 | .name = "qhs_security" , |
871 | .id = SC7280_SLAVE_SECURITY, |
872 | .channels = 1, |
873 | .buswidth = 4, |
874 | .num_links = 0, |
875 | }; |
876 | |
877 | static struct qcom_icc_node qhs_tcsr = { |
878 | .name = "qhs_tcsr" , |
879 | .id = SC7280_SLAVE_TCSR, |
880 | .channels = 1, |
881 | .buswidth = 4, |
882 | .num_links = 0, |
883 | }; |
884 | |
885 | static struct qcom_icc_node qhs_tlmm = { |
886 | .name = "qhs_tlmm" , |
887 | .id = SC7280_SLAVE_TLMM, |
888 | .channels = 1, |
889 | .buswidth = 4, |
890 | .num_links = 0, |
891 | }; |
892 | |
893 | static struct qcom_icc_node qhs_ufs_mem_cfg = { |
894 | .name = "qhs_ufs_mem_cfg" , |
895 | .id = SC7280_SLAVE_UFS_MEM_CFG, |
896 | .channels = 1, |
897 | .buswidth = 4, |
898 | .num_links = 0, |
899 | }; |
900 | |
901 | static struct qcom_icc_node qhs_usb2 = { |
902 | .name = "qhs_usb2" , |
903 | .id = SC7280_SLAVE_USB2, |
904 | .channels = 1, |
905 | .buswidth = 4, |
906 | .num_links = 0, |
907 | }; |
908 | |
909 | static struct qcom_icc_node qhs_usb3_0 = { |
910 | .name = "qhs_usb3_0" , |
911 | .id = SC7280_SLAVE_USB3_0, |
912 | .channels = 1, |
913 | .buswidth = 4, |
914 | .num_links = 0, |
915 | }; |
916 | |
917 | static struct qcom_icc_node qhs_venus_cfg = { |
918 | .name = "qhs_venus_cfg" , |
919 | .id = SC7280_SLAVE_VENUS_CFG, |
920 | .channels = 1, |
921 | .buswidth = 4, |
922 | .num_links = 0, |
923 | }; |
924 | |
925 | static struct qcom_icc_node qhs_vsense_ctrl_cfg = { |
926 | .name = "qhs_vsense_ctrl_cfg" , |
927 | .id = SC7280_SLAVE_VSENSE_CTRL_CFG, |
928 | .channels = 1, |
929 | .buswidth = 4, |
930 | .num_links = 0, |
931 | }; |
932 | |
933 | static struct qcom_icc_node qns_a1_noc_cfg = { |
934 | .name = "qns_a1_noc_cfg" , |
935 | .id = SC7280_SLAVE_A1NOC_CFG, |
936 | .channels = 1, |
937 | .buswidth = 4, |
938 | .num_links = 1, |
939 | .links = { SC7280_MASTER_A1NOC_CFG }, |
940 | }; |
941 | |
942 | static struct qcom_icc_node qns_a2_noc_cfg = { |
943 | .name = "qns_a2_noc_cfg" , |
944 | .id = SC7280_SLAVE_A2NOC_CFG, |
945 | .channels = 1, |
946 | .buswidth = 4, |
947 | .num_links = 1, |
948 | .links = { SC7280_MASTER_A2NOC_CFG }, |
949 | }; |
950 | |
951 | static struct qcom_icc_node qns_cnoc2_cnoc3 = { |
952 | .name = "qns_cnoc2_cnoc3" , |
953 | .id = SC7280_SLAVE_CNOC2_CNOC3, |
954 | .channels = 1, |
955 | .buswidth = 8, |
956 | .num_links = 1, |
957 | .links = { SC7280_MASTER_CNOC2_CNOC3 }, |
958 | }; |
959 | |
960 | static struct qcom_icc_node qns_mnoc_cfg = { |
961 | .name = "qns_mnoc_cfg" , |
962 | .id = SC7280_SLAVE_CNOC_MNOC_CFG, |
963 | .channels = 1, |
964 | .buswidth = 4, |
965 | .num_links = 1, |
966 | .links = { SC7280_MASTER_CNOC_MNOC_CFG }, |
967 | }; |
968 | |
969 | static struct qcom_icc_node qns_snoc_cfg = { |
970 | .name = "qns_snoc_cfg" , |
971 | .id = SC7280_SLAVE_SNOC_CFG, |
972 | .channels = 1, |
973 | .buswidth = 4, |
974 | .num_links = 1, |
975 | .links = { SC7280_MASTER_SNOC_CFG }, |
976 | }; |
977 | |
978 | static struct qcom_icc_node qhs_aoss = { |
979 | .name = "qhs_aoss" , |
980 | .id = SC7280_SLAVE_AOSS, |
981 | .channels = 1, |
982 | .buswidth = 4, |
983 | .num_links = 0, |
984 | }; |
985 | |
986 | static struct qcom_icc_node qhs_apss = { |
987 | .name = "qhs_apss" , |
988 | .id = SC7280_SLAVE_APPSS, |
989 | .channels = 1, |
990 | .buswidth = 8, |
991 | .num_links = 0, |
992 | }; |
993 | |
994 | static struct qcom_icc_node qns_cnoc3_cnoc2 = { |
995 | .name = "qns_cnoc3_cnoc2" , |
996 | .id = SC7280_SLAVE_CNOC3_CNOC2, |
997 | .channels = 1, |
998 | .buswidth = 8, |
999 | .num_links = 1, |
1000 | .links = { SC7280_MASTER_CNOC3_CNOC2 }, |
1001 | }; |
1002 | |
1003 | static struct qcom_icc_node qns_cnoc_a2noc = { |
1004 | .name = "qns_cnoc_a2noc" , |
1005 | .id = SC7280_SLAVE_CNOC_A2NOC, |
1006 | .channels = 1, |
1007 | .buswidth = 8, |
1008 | .num_links = 1, |
1009 | .links = { SC7280_MASTER_CNOC_A2NOC }, |
1010 | }; |
1011 | |
1012 | static struct qcom_icc_node = { |
1013 | .name = "qns_ddrss_cfg" , |
1014 | .id = SC7280_SLAVE_DDRSS_CFG, |
1015 | .channels = 1, |
1016 | .buswidth = 4, |
1017 | .num_links = 1, |
1018 | .links = { SC7280_MASTER_CNOC_DC_NOC }, |
1019 | }; |
1020 | |
1021 | static struct qcom_icc_node qxs_boot_imem = { |
1022 | .name = "qxs_boot_imem" , |
1023 | .id = SC7280_SLAVE_BOOT_IMEM, |
1024 | .channels = 1, |
1025 | .buswidth = 8, |
1026 | .num_links = 0, |
1027 | }; |
1028 | |
1029 | static struct qcom_icc_node qxs_imem = { |
1030 | .name = "qxs_imem" , |
1031 | .id = SC7280_SLAVE_IMEM, |
1032 | .channels = 1, |
1033 | .buswidth = 8, |
1034 | .num_links = 0, |
1035 | }; |
1036 | |
1037 | static struct qcom_icc_node qxs_pimem = { |
1038 | .name = "qxs_pimem" , |
1039 | .id = SC7280_SLAVE_PIMEM, |
1040 | .channels = 1, |
1041 | .buswidth = 8, |
1042 | .num_links = 0, |
1043 | }; |
1044 | |
1045 | static struct qcom_icc_node xs_pcie_0 = { |
1046 | .name = "xs_pcie_0" , |
1047 | .id = SC7280_SLAVE_PCIE_0, |
1048 | .channels = 1, |
1049 | .buswidth = 8, |
1050 | .num_links = 0, |
1051 | }; |
1052 | |
1053 | static struct qcom_icc_node xs_pcie_1 = { |
1054 | .name = "xs_pcie_1" , |
1055 | .id = SC7280_SLAVE_PCIE_1, |
1056 | .channels = 1, |
1057 | .buswidth = 8, |
1058 | .num_links = 0, |
1059 | }; |
1060 | |
1061 | static struct qcom_icc_node xs_qdss_stm = { |
1062 | .name = "xs_qdss_stm" , |
1063 | .id = SC7280_SLAVE_QDSS_STM, |
1064 | .channels = 1, |
1065 | .buswidth = 4, |
1066 | .num_links = 0, |
1067 | }; |
1068 | |
1069 | static struct qcom_icc_node xs_sys_tcu_cfg = { |
1070 | .name = "xs_sys_tcu_cfg" , |
1071 | .id = SC7280_SLAVE_TCU, |
1072 | .channels = 1, |
1073 | .buswidth = 8, |
1074 | .num_links = 0, |
1075 | }; |
1076 | |
1077 | static struct qcom_icc_node qhs_llcc = { |
1078 | .name = "qhs_llcc" , |
1079 | .id = SC7280_SLAVE_LLCC_CFG, |
1080 | .channels = 1, |
1081 | .buswidth = 4, |
1082 | .num_links = 0, |
1083 | }; |
1084 | |
1085 | static struct qcom_icc_node qns_gemnoc = { |
1086 | .name = "qns_gemnoc" , |
1087 | .id = SC7280_SLAVE_GEM_NOC_CFG, |
1088 | .channels = 1, |
1089 | .buswidth = 4, |
1090 | .num_links = 1, |
1091 | .links = { SC7280_MASTER_GEM_NOC_CFG }, |
1092 | }; |
1093 | |
1094 | static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { |
1095 | .name = "qhs_mdsp_ms_mpu_cfg" , |
1096 | .id = SC7280_SLAVE_MSS_PROC_MS_MPU_CFG, |
1097 | .channels = 1, |
1098 | .buswidth = 4, |
1099 | .num_links = 0, |
1100 | }; |
1101 | |
1102 | static struct qcom_icc_node qhs_modem_ms_mpu_cfg = { |
1103 | .name = "qhs_modem_ms_mpu_cfg" , |
1104 | .id = SC7280_SLAVE_MCDMA_MS_MPU_CFG, |
1105 | .channels = 1, |
1106 | .buswidth = 4, |
1107 | .num_links = 0, |
1108 | }; |
1109 | |
1110 | static struct qcom_icc_node qns_gem_noc_cnoc = { |
1111 | .name = "qns_gem_noc_cnoc" , |
1112 | .id = SC7280_SLAVE_GEM_NOC_CNOC, |
1113 | .channels = 1, |
1114 | .buswidth = 16, |
1115 | .num_links = 1, |
1116 | .links = { SC7280_MASTER_GEM_NOC_CNOC }, |
1117 | }; |
1118 | |
1119 | static struct qcom_icc_node qns_llcc = { |
1120 | .name = "qns_llcc" , |
1121 | .id = SC7280_SLAVE_LLCC, |
1122 | .channels = 2, |
1123 | .buswidth = 16, |
1124 | .num_links = 1, |
1125 | .links = { SC7280_MASTER_LLCC }, |
1126 | }; |
1127 | |
1128 | static struct qcom_icc_node qns_pcie = { |
1129 | .name = "qns_pcie" , |
1130 | .id = SC7280_SLAVE_MEM_NOC_PCIE_SNOC, |
1131 | .channels = 1, |
1132 | .buswidth = 8, |
1133 | .num_links = 1, |
1134 | .links = { SC7280_MASTER_GEM_NOC_PCIE_SNOC }, |
1135 | }; |
1136 | |
1137 | static struct qcom_icc_node srvc_even_gemnoc = { |
1138 | .name = "srvc_even_gemnoc" , |
1139 | .id = SC7280_SLAVE_SERVICE_GEM_NOC_1, |
1140 | .channels = 1, |
1141 | .buswidth = 4, |
1142 | .num_links = 0, |
1143 | }; |
1144 | |
1145 | static struct qcom_icc_node srvc_odd_gemnoc = { |
1146 | .name = "srvc_odd_gemnoc" , |
1147 | .id = SC7280_SLAVE_SERVICE_GEM_NOC_2, |
1148 | .channels = 1, |
1149 | .buswidth = 4, |
1150 | .num_links = 0, |
1151 | }; |
1152 | |
1153 | static struct qcom_icc_node srvc_sys_gemnoc = { |
1154 | .name = "srvc_sys_gemnoc" , |
1155 | .id = SC7280_SLAVE_SERVICE_GEM_NOC, |
1156 | .channels = 1, |
1157 | .buswidth = 4, |
1158 | .num_links = 0, |
1159 | }; |
1160 | |
1161 | static struct qcom_icc_node qhs_lpass_core = { |
1162 | .name = "qhs_lpass_core" , |
1163 | .id = SC7280_SLAVE_LPASS_CORE_CFG, |
1164 | .channels = 1, |
1165 | .buswidth = 4, |
1166 | .num_links = 0, |
1167 | }; |
1168 | |
1169 | static struct qcom_icc_node qhs_lpass_lpi = { |
1170 | .name = "qhs_lpass_lpi" , |
1171 | .id = SC7280_SLAVE_LPASS_LPI_CFG, |
1172 | .channels = 1, |
1173 | .buswidth = 4, |
1174 | .num_links = 0, |
1175 | }; |
1176 | |
1177 | static struct qcom_icc_node qhs_lpass_mpu = { |
1178 | .name = "qhs_lpass_mpu" , |
1179 | .id = SC7280_SLAVE_LPASS_MPU_CFG, |
1180 | .channels = 1, |
1181 | .buswidth = 4, |
1182 | .num_links = 0, |
1183 | }; |
1184 | |
1185 | static struct qcom_icc_node qhs_lpass_top = { |
1186 | .name = "qhs_lpass_top" , |
1187 | .id = SC7280_SLAVE_LPASS_TOP_CFG, |
1188 | .channels = 1, |
1189 | .buswidth = 4, |
1190 | .num_links = 0, |
1191 | }; |
1192 | |
1193 | static struct qcom_icc_node srvc_niu_aml_noc = { |
1194 | .name = "srvc_niu_aml_noc" , |
1195 | .id = SC7280_SLAVE_SERVICES_LPASS_AML_NOC, |
1196 | .channels = 1, |
1197 | .buswidth = 4, |
1198 | .num_links = 0, |
1199 | }; |
1200 | |
1201 | static struct qcom_icc_node srvc_niu_lpass_agnoc = { |
1202 | .name = "srvc_niu_lpass_agnoc" , |
1203 | .id = SC7280_SLAVE_SERVICE_LPASS_AG_NOC, |
1204 | .channels = 1, |
1205 | .buswidth = 4, |
1206 | .num_links = 0, |
1207 | }; |
1208 | |
1209 | static struct qcom_icc_node ebi = { |
1210 | .name = "ebi" , |
1211 | .id = SC7280_SLAVE_EBI1, |
1212 | .channels = 2, |
1213 | .buswidth = 4, |
1214 | .num_links = 0, |
1215 | }; |
1216 | |
1217 | static struct qcom_icc_node qns_mem_noc_hf = { |
1218 | .name = "qns_mem_noc_hf" , |
1219 | .id = SC7280_SLAVE_MNOC_HF_MEM_NOC, |
1220 | .channels = 2, |
1221 | .buswidth = 32, |
1222 | .num_links = 1, |
1223 | .links = { SC7280_MASTER_MNOC_HF_MEM_NOC }, |
1224 | }; |
1225 | |
1226 | static struct qcom_icc_node qns_mem_noc_sf = { |
1227 | .name = "qns_mem_noc_sf" , |
1228 | .id = SC7280_SLAVE_MNOC_SF_MEM_NOC, |
1229 | .channels = 1, |
1230 | .buswidth = 32, |
1231 | .num_links = 1, |
1232 | .links = { SC7280_MASTER_MNOC_SF_MEM_NOC }, |
1233 | }; |
1234 | |
1235 | static struct qcom_icc_node srvc_mnoc = { |
1236 | .name = "srvc_mnoc" , |
1237 | .id = SC7280_SLAVE_SERVICE_MNOC, |
1238 | .channels = 1, |
1239 | .buswidth = 4, |
1240 | .num_links = 0, |
1241 | }; |
1242 | |
1243 | static struct qcom_icc_node qns_nsp_gemnoc = { |
1244 | .name = "qns_nsp_gemnoc" , |
1245 | .id = SC7280_SLAVE_CDSP_MEM_NOC, |
1246 | .channels = 2, |
1247 | .buswidth = 32, |
1248 | .num_links = 1, |
1249 | .links = { SC7280_MASTER_COMPUTE_NOC }, |
1250 | }; |
1251 | |
1252 | static struct qcom_icc_node service_nsp_noc = { |
1253 | .name = "service_nsp_noc" , |
1254 | .id = SC7280_SLAVE_SERVICE_NSP_NOC, |
1255 | .channels = 1, |
1256 | .buswidth = 4, |
1257 | .num_links = 0, |
1258 | }; |
1259 | |
1260 | static struct qcom_icc_node qns_gemnoc_gc = { |
1261 | .name = "qns_gemnoc_gc" , |
1262 | .id = SC7280_SLAVE_SNOC_GEM_NOC_GC, |
1263 | .channels = 1, |
1264 | .buswidth = 8, |
1265 | .num_links = 1, |
1266 | .links = { SC7280_MASTER_SNOC_GC_MEM_NOC }, |
1267 | }; |
1268 | |
1269 | static struct qcom_icc_node qns_gemnoc_sf = { |
1270 | .name = "qns_gemnoc_sf" , |
1271 | .id = SC7280_SLAVE_SNOC_GEM_NOC_SF, |
1272 | .channels = 1, |
1273 | .buswidth = 16, |
1274 | .num_links = 1, |
1275 | .links = { SC7280_MASTER_SNOC_SF_MEM_NOC }, |
1276 | }; |
1277 | |
1278 | static struct qcom_icc_node srvc_snoc = { |
1279 | .name = "srvc_snoc" , |
1280 | .id = SC7280_SLAVE_SERVICE_SNOC, |
1281 | .channels = 1, |
1282 | .buswidth = 4, |
1283 | .num_links = 0, |
1284 | }; |
1285 | |
1286 | static struct qcom_icc_bcm bcm_acv = { |
1287 | .name = "ACV" , |
1288 | .enable_mask = BIT(3), |
1289 | .num_nodes = 1, |
1290 | .nodes = { &ebi }, |
1291 | }; |
1292 | |
1293 | static struct qcom_icc_bcm bcm_ce0 = { |
1294 | .name = "CE0" , |
1295 | .num_nodes = 1, |
1296 | .nodes = { &qxm_crypto }, |
1297 | }; |
1298 | |
1299 | static struct qcom_icc_bcm bcm_cn0 = { |
1300 | .name = "CN0" , |
1301 | .keepalive = true, |
1302 | .num_nodes = 2, |
1303 | .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie }, |
1304 | }; |
1305 | |
1306 | static struct qcom_icc_bcm bcm_cn1 = { |
1307 | .name = "CN1" , |
1308 | .num_nodes = 47, |
1309 | .nodes = { &qnm_cnoc3_cnoc2, &xm_qdss_dap, |
1310 | &qhs_ahb2phy0, &qhs_ahb2phy1, |
1311 | &qhs_camera_cfg, &qhs_clk_ctl, |
1312 | &qhs_compute_cfg, &qhs_cpr_cx, |
1313 | &qhs_cpr_mx, &qhs_crypto0_cfg, |
1314 | &qhs_cx_rdpm, &qhs_dcc_cfg, |
1315 | &qhs_display_cfg, &qhs_gpuss_cfg, |
1316 | &qhs_hwkm, &qhs_imem_cfg, |
1317 | &qhs_ipa, &qhs_ipc_router, |
1318 | &qhs_mss_cfg, &qhs_mx_rdpm, |
1319 | &qhs_pcie0_cfg, &qhs_pcie1_cfg, |
1320 | &qhs_pimem_cfg, &qhs_pka_wrapper_cfg, |
1321 | &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg, |
1322 | &qhs_qup0, &qhs_qup1, |
1323 | &qhs_security, &qhs_tcsr, |
1324 | &qhs_tlmm, &qhs_ufs_mem_cfg, &qhs_usb2, |
1325 | &qhs_usb3_0, &qhs_venus_cfg, |
1326 | &qhs_vsense_ctrl_cfg, &qns_a1_noc_cfg, |
1327 | &qns_a2_noc_cfg, &qns_cnoc2_cnoc3, |
1328 | &qns_mnoc_cfg, &qns_snoc_cfg, |
1329 | &qnm_cnoc2_cnoc3, &qhs_aoss, |
1330 | &qhs_apss, &qns_cnoc3_cnoc2, |
1331 | &qns_cnoc_a2noc, &qns_ddrss_cfg }, |
1332 | }; |
1333 | |
1334 | static struct qcom_icc_bcm bcm_cn2 = { |
1335 | .name = "CN2" , |
1336 | .num_nodes = 6, |
1337 | .nodes = { &qhs_lpass_cfg, &qhs_pdm, |
1338 | &qhs_qspi, &qhs_sdc1, |
1339 | &qhs_sdc2, &qhs_sdc4 }, |
1340 | }; |
1341 | |
1342 | static struct qcom_icc_bcm bcm_co0 = { |
1343 | .name = "CO0" , |
1344 | .num_nodes = 1, |
1345 | .nodes = { &qns_nsp_gemnoc }, |
1346 | }; |
1347 | |
1348 | static struct qcom_icc_bcm bcm_co3 = { |
1349 | .name = "CO3" , |
1350 | .num_nodes = 1, |
1351 | .nodes = { &qxm_nsp }, |
1352 | }; |
1353 | |
1354 | static struct qcom_icc_bcm bcm_mc0 = { |
1355 | .name = "MC0" , |
1356 | .keepalive = true, |
1357 | .num_nodes = 1, |
1358 | .nodes = { &ebi }, |
1359 | }; |
1360 | |
1361 | static struct qcom_icc_bcm bcm_mm0 = { |
1362 | .name = "MM0" , |
1363 | .keepalive = true, |
1364 | .num_nodes = 1, |
1365 | .nodes = { &qns_mem_noc_hf }, |
1366 | }; |
1367 | |
1368 | static struct qcom_icc_bcm bcm_mm1 = { |
1369 | .name = "MM1" , |
1370 | .num_nodes = 2, |
1371 | .nodes = { &qxm_camnoc_hf, &qxm_mdp0 }, |
1372 | }; |
1373 | |
1374 | static struct qcom_icc_bcm bcm_mm4 = { |
1375 | .name = "MM4" , |
1376 | .num_nodes = 1, |
1377 | .nodes = { &qns_mem_noc_sf }, |
1378 | }; |
1379 | |
1380 | static struct qcom_icc_bcm bcm_mm5 = { |
1381 | .name = "MM5" , |
1382 | .num_nodes = 3, |
1383 | .nodes = { &qnm_video0, &qxm_camnoc_icp, |
1384 | &qxm_camnoc_sf }, |
1385 | }; |
1386 | |
1387 | static struct qcom_icc_bcm bcm_qup0 = { |
1388 | .name = "QUP0" , |
1389 | .vote_scale = 1, |
1390 | .num_nodes = 1, |
1391 | .nodes = { &qup0_core_slave }, |
1392 | }; |
1393 | |
1394 | static struct qcom_icc_bcm bcm_qup1 = { |
1395 | .name = "QUP1" , |
1396 | .vote_scale = 1, |
1397 | .num_nodes = 1, |
1398 | .nodes = { &qup1_core_slave }, |
1399 | }; |
1400 | |
1401 | static struct qcom_icc_bcm bcm_sh0 = { |
1402 | .name = "SH0" , |
1403 | .keepalive = true, |
1404 | .num_nodes = 1, |
1405 | .nodes = { &qns_llcc }, |
1406 | }; |
1407 | |
1408 | static struct qcom_icc_bcm bcm_sh2 = { |
1409 | .name = "SH2" , |
1410 | .num_nodes = 2, |
1411 | .nodes = { &alm_gpu_tcu, &alm_sys_tcu }, |
1412 | }; |
1413 | |
1414 | static struct qcom_icc_bcm bcm_sh3 = { |
1415 | .name = "SH3" , |
1416 | .num_nodes = 1, |
1417 | .nodes = { &qnm_cmpnoc }, |
1418 | }; |
1419 | |
1420 | static struct qcom_icc_bcm bcm_sh4 = { |
1421 | .name = "SH4" , |
1422 | .num_nodes = 1, |
1423 | .nodes = { &chm_apps }, |
1424 | }; |
1425 | |
1426 | static struct qcom_icc_bcm bcm_sn0 = { |
1427 | .name = "SN0" , |
1428 | .keepalive = true, |
1429 | .num_nodes = 1, |
1430 | .nodes = { &qns_gemnoc_sf }, |
1431 | }; |
1432 | |
1433 | static struct qcom_icc_bcm bcm_sn2 = { |
1434 | .name = "SN2" , |
1435 | .num_nodes = 1, |
1436 | .nodes = { &qns_gemnoc_gc }, |
1437 | }; |
1438 | |
1439 | static struct qcom_icc_bcm bcm_sn3 = { |
1440 | .name = "SN3" , |
1441 | .num_nodes = 1, |
1442 | .nodes = { &qxs_pimem }, |
1443 | }; |
1444 | |
1445 | static struct qcom_icc_bcm bcm_sn4 = { |
1446 | .name = "SN4" , |
1447 | .num_nodes = 1, |
1448 | .nodes = { &xs_qdss_stm }, |
1449 | }; |
1450 | |
1451 | static struct qcom_icc_bcm bcm_sn5 = { |
1452 | .name = "SN5" , |
1453 | .num_nodes = 1, |
1454 | .nodes = { &xm_pcie3_0 }, |
1455 | }; |
1456 | |
1457 | static struct qcom_icc_bcm bcm_sn6 = { |
1458 | .name = "SN6" , |
1459 | .num_nodes = 1, |
1460 | .nodes = { &xm_pcie3_1 }, |
1461 | }; |
1462 | |
1463 | static struct qcom_icc_bcm bcm_sn7 = { |
1464 | .name = "SN7" , |
1465 | .num_nodes = 1, |
1466 | .nodes = { &qnm_aggre1_noc }, |
1467 | }; |
1468 | |
1469 | static struct qcom_icc_bcm bcm_sn8 = { |
1470 | .name = "SN8" , |
1471 | .num_nodes = 1, |
1472 | .nodes = { &qnm_aggre2_noc }, |
1473 | }; |
1474 | |
1475 | static struct qcom_icc_bcm bcm_sn14 = { |
1476 | .name = "SN14" , |
1477 | .num_nodes = 1, |
1478 | .nodes = { &qns_pcie_mem_noc }, |
1479 | }; |
1480 | |
1481 | static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { |
1482 | &bcm_sn5, |
1483 | &bcm_sn6, |
1484 | &bcm_sn14, |
1485 | }; |
1486 | |
1487 | static struct qcom_icc_node * const aggre1_noc_nodes[] = { |
1488 | [MASTER_QSPI_0] = &qhm_qspi, |
1489 | [MASTER_QUP_0] = &qhm_qup0, |
1490 | [MASTER_QUP_1] = &qhm_qup1, |
1491 | [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg, |
1492 | [MASTER_PCIE_0] = &xm_pcie3_0, |
1493 | [MASTER_PCIE_1] = &xm_pcie3_1, |
1494 | [MASTER_SDCC_1] = &xm_sdc1, |
1495 | [MASTER_SDCC_2] = &xm_sdc2, |
1496 | [MASTER_SDCC_4] = &xm_sdc4, |
1497 | [MASTER_UFS_MEM] = &xm_ufs_mem, |
1498 | [MASTER_USB2] = &xm_usb2, |
1499 | [MASTER_USB3_0] = &xm_usb3_0, |
1500 | [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, |
1501 | [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, |
1502 | [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, |
1503 | }; |
1504 | |
1505 | static const struct qcom_icc_desc sc7280_aggre1_noc = { |
1506 | .nodes = aggre1_noc_nodes, |
1507 | .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), |
1508 | .bcms = aggre1_noc_bcms, |
1509 | .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), |
1510 | }; |
1511 | |
1512 | static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { |
1513 | &bcm_ce0, |
1514 | }; |
1515 | |
1516 | static struct qcom_icc_node * const aggre2_noc_nodes[] = { |
1517 | [MASTER_QDSS_BAM] = &qhm_qdss_bam, |
1518 | [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg, |
1519 | [MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath, |
1520 | [MASTER_CRYPTO] = &qxm_crypto, |
1521 | [MASTER_IPA] = &qxm_ipa, |
1522 | [MASTER_QDSS_ETR] = &xm_qdss_etr, |
1523 | [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, |
1524 | [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, |
1525 | }; |
1526 | |
1527 | static const struct qcom_icc_desc sc7280_aggre2_noc = { |
1528 | .nodes = aggre2_noc_nodes, |
1529 | .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), |
1530 | .bcms = aggre2_noc_bcms, |
1531 | .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), |
1532 | }; |
1533 | |
1534 | static struct qcom_icc_bcm * const clk_virt_bcms[] = { |
1535 | &bcm_qup0, |
1536 | &bcm_qup1, |
1537 | }; |
1538 | |
1539 | static struct qcom_icc_node * const clk_virt_nodes[] = { |
1540 | [MASTER_QUP_CORE_0] = &qup0_core_master, |
1541 | [MASTER_QUP_CORE_1] = &qup1_core_master, |
1542 | [SLAVE_QUP_CORE_0] = &qup0_core_slave, |
1543 | [SLAVE_QUP_CORE_1] = &qup1_core_slave, |
1544 | }; |
1545 | |
1546 | static const struct qcom_icc_desc sc7280_clk_virt = { |
1547 | .nodes = clk_virt_nodes, |
1548 | .num_nodes = ARRAY_SIZE(clk_virt_nodes), |
1549 | .bcms = clk_virt_bcms, |
1550 | .num_bcms = ARRAY_SIZE(clk_virt_bcms), |
1551 | }; |
1552 | |
1553 | static struct qcom_icc_bcm * const cnoc2_bcms[] = { |
1554 | &bcm_cn1, |
1555 | &bcm_cn2, |
1556 | }; |
1557 | |
1558 | static struct qcom_icc_node * const cnoc2_nodes[] = { |
1559 | [MASTER_CNOC3_CNOC2] = &qnm_cnoc3_cnoc2, |
1560 | [MASTER_QDSS_DAP] = &xm_qdss_dap, |
1561 | [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, |
1562 | [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, |
1563 | [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, |
1564 | [SLAVE_CLK_CTL] = &qhs_clk_ctl, |
1565 | [SLAVE_CDSP_CFG] = &qhs_compute_cfg, |
1566 | [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, |
1567 | [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, |
1568 | [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, |
1569 | [SLAVE_CX_RDPM] = &qhs_cx_rdpm, |
1570 | [SLAVE_DCC_CFG] = &qhs_dcc_cfg, |
1571 | [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, |
1572 | [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, |
1573 | [SLAVE_HWKM] = &qhs_hwkm, |
1574 | [SLAVE_IMEM_CFG] = &qhs_imem_cfg, |
1575 | [SLAVE_IPA_CFG] = &qhs_ipa, |
1576 | [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, |
1577 | [SLAVE_LPASS] = &qhs_lpass_cfg, |
1578 | [SLAVE_CNOC_MSS] = &qhs_mss_cfg, |
1579 | [SLAVE_MX_RDPM] = &qhs_mx_rdpm, |
1580 | [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, |
1581 | [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, |
1582 | [SLAVE_PDM] = &qhs_pdm, |
1583 | [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, |
1584 | [SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg, |
1585 | [SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg, |
1586 | [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, |
1587 | [SLAVE_QSPI_0] = &qhs_qspi, |
1588 | [SLAVE_QUP_0] = &qhs_qup0, |
1589 | [SLAVE_QUP_1] = &qhs_qup1, |
1590 | [SLAVE_SDCC_1] = &qhs_sdc1, |
1591 | [SLAVE_SDCC_2] = &qhs_sdc2, |
1592 | [SLAVE_SDCC_4] = &qhs_sdc4, |
1593 | [SLAVE_SECURITY] = &qhs_security, |
1594 | [SLAVE_TCSR] = &qhs_tcsr, |
1595 | [SLAVE_TLMM] = &qhs_tlmm, |
1596 | [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, |
1597 | [SLAVE_USB2] = &qhs_usb2, |
1598 | [SLAVE_USB3_0] = &qhs_usb3_0, |
1599 | [SLAVE_VENUS_CFG] = &qhs_venus_cfg, |
1600 | [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, |
1601 | [SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg, |
1602 | [SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg, |
1603 | [SLAVE_CNOC2_CNOC3] = &qns_cnoc2_cnoc3, |
1604 | [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg, |
1605 | [SLAVE_SNOC_CFG] = &qns_snoc_cfg, |
1606 | }; |
1607 | |
1608 | static const struct qcom_icc_desc sc7280_cnoc2 = { |
1609 | .nodes = cnoc2_nodes, |
1610 | .num_nodes = ARRAY_SIZE(cnoc2_nodes), |
1611 | .bcms = cnoc2_bcms, |
1612 | .num_bcms = ARRAY_SIZE(cnoc2_bcms), |
1613 | }; |
1614 | |
1615 | static struct qcom_icc_bcm * const cnoc3_bcms[] = { |
1616 | &bcm_cn0, |
1617 | &bcm_cn1, |
1618 | &bcm_sn3, |
1619 | &bcm_sn4, |
1620 | }; |
1621 | |
1622 | static struct qcom_icc_node * const cnoc3_nodes[] = { |
1623 | [MASTER_CNOC2_CNOC3] = &qnm_cnoc2_cnoc3, |
1624 | [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, |
1625 | [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, |
1626 | [SLAVE_AOSS] = &qhs_aoss, |
1627 | [SLAVE_APPSS] = &qhs_apss, |
1628 | [SLAVE_CNOC3_CNOC2] = &qns_cnoc3_cnoc2, |
1629 | [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc, |
1630 | [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, |
1631 | [SLAVE_BOOT_IMEM] = &qxs_boot_imem, |
1632 | [SLAVE_IMEM] = &qxs_imem, |
1633 | [SLAVE_PIMEM] = &qxs_pimem, |
1634 | [SLAVE_PCIE_0] = &xs_pcie_0, |
1635 | [SLAVE_PCIE_1] = &xs_pcie_1, |
1636 | [SLAVE_QDSS_STM] = &xs_qdss_stm, |
1637 | [SLAVE_TCU] = &xs_sys_tcu_cfg, |
1638 | }; |
1639 | |
1640 | static const struct qcom_icc_desc sc7280_cnoc3 = { |
1641 | .nodes = cnoc3_nodes, |
1642 | .num_nodes = ARRAY_SIZE(cnoc3_nodes), |
1643 | .bcms = cnoc3_bcms, |
1644 | .num_bcms = ARRAY_SIZE(cnoc3_bcms), |
1645 | }; |
1646 | |
1647 | static struct qcom_icc_bcm * const dc_noc_bcms[] = { |
1648 | }; |
1649 | |
1650 | static struct qcom_icc_node * const dc_noc_nodes[] = { |
1651 | [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc, |
1652 | [SLAVE_LLCC_CFG] = &qhs_llcc, |
1653 | [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, |
1654 | }; |
1655 | |
1656 | static const struct qcom_icc_desc sc7280_dc_noc = { |
1657 | .nodes = dc_noc_nodes, |
1658 | .num_nodes = ARRAY_SIZE(dc_noc_nodes), |
1659 | .bcms = dc_noc_bcms, |
1660 | .num_bcms = ARRAY_SIZE(dc_noc_bcms), |
1661 | }; |
1662 | |
1663 | static struct qcom_icc_bcm * const gem_noc_bcms[] = { |
1664 | &bcm_sh0, |
1665 | &bcm_sh2, |
1666 | &bcm_sh3, |
1667 | &bcm_sh4, |
1668 | }; |
1669 | |
1670 | static struct qcom_icc_node * const gem_noc_nodes[] = { |
1671 | [MASTER_GPU_TCU] = &alm_gpu_tcu, |
1672 | [MASTER_SYS_TCU] = &alm_sys_tcu, |
1673 | [MASTER_APPSS_PROC] = &chm_apps, |
1674 | [MASTER_COMPUTE_NOC] = &qnm_cmpnoc, |
1675 | [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg, |
1676 | [MASTER_GFX3D] = &qnm_gpu, |
1677 | [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, |
1678 | [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, |
1679 | [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, |
1680 | [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, |
1681 | [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, |
1682 | [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, |
1683 | [SLAVE_MCDMA_MS_MPU_CFG] = &qhs_modem_ms_mpu_cfg, |
1684 | [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, |
1685 | [SLAVE_LLCC] = &qns_llcc, |
1686 | [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, |
1687 | [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc, |
1688 | [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc, |
1689 | [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc, |
1690 | }; |
1691 | |
1692 | static const struct qcom_icc_desc sc7280_gem_noc = { |
1693 | .nodes = gem_noc_nodes, |
1694 | .num_nodes = ARRAY_SIZE(gem_noc_nodes), |
1695 | .bcms = gem_noc_bcms, |
1696 | .num_bcms = ARRAY_SIZE(gem_noc_bcms), |
1697 | }; |
1698 | |
1699 | static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { |
1700 | }; |
1701 | |
1702 | static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { |
1703 | [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, |
1704 | [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, |
1705 | [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, |
1706 | [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu, |
1707 | [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top, |
1708 | [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc, |
1709 | [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, |
1710 | }; |
1711 | |
1712 | static const struct qcom_icc_desc sc7280_lpass_ag_noc = { |
1713 | .nodes = lpass_ag_noc_nodes, |
1714 | .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), |
1715 | .bcms = lpass_ag_noc_bcms, |
1716 | .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), |
1717 | }; |
1718 | |
1719 | static struct qcom_icc_bcm * const mc_virt_bcms[] = { |
1720 | &bcm_acv, |
1721 | &bcm_mc0, |
1722 | }; |
1723 | |
1724 | static struct qcom_icc_node * const mc_virt_nodes[] = { |
1725 | [MASTER_LLCC] = &llcc_mc, |
1726 | [SLAVE_EBI1] = &ebi, |
1727 | }; |
1728 | |
1729 | static const struct qcom_icc_desc sc7280_mc_virt = { |
1730 | .nodes = mc_virt_nodes, |
1731 | .num_nodes = ARRAY_SIZE(mc_virt_nodes), |
1732 | .bcms = mc_virt_bcms, |
1733 | .num_bcms = ARRAY_SIZE(mc_virt_bcms), |
1734 | }; |
1735 | |
1736 | static struct qcom_icc_bcm * const mmss_noc_bcms[] = { |
1737 | &bcm_mm0, |
1738 | &bcm_mm1, |
1739 | &bcm_mm4, |
1740 | &bcm_mm5, |
1741 | }; |
1742 | |
1743 | static struct qcom_icc_node * const mmss_noc_nodes[] = { |
1744 | [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg, |
1745 | [MASTER_VIDEO_P0] = &qnm_video0, |
1746 | [MASTER_VIDEO_PROC] = &qnm_video_cpu, |
1747 | [MASTER_CAMNOC_HF] = &qxm_camnoc_hf, |
1748 | [MASTER_CAMNOC_ICP] = &qxm_camnoc_icp, |
1749 | [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, |
1750 | [MASTER_MDP0] = &qxm_mdp0, |
1751 | [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, |
1752 | [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, |
1753 | [SLAVE_SERVICE_MNOC] = &srvc_mnoc, |
1754 | }; |
1755 | |
1756 | static const struct qcom_icc_desc sc7280_mmss_noc = { |
1757 | .nodes = mmss_noc_nodes, |
1758 | .num_nodes = ARRAY_SIZE(mmss_noc_nodes), |
1759 | .bcms = mmss_noc_bcms, |
1760 | .num_bcms = ARRAY_SIZE(mmss_noc_bcms), |
1761 | }; |
1762 | |
1763 | static struct qcom_icc_bcm * const nsp_noc_bcms[] = { |
1764 | &bcm_co0, |
1765 | &bcm_co3, |
1766 | }; |
1767 | |
1768 | static struct qcom_icc_node * const nsp_noc_nodes[] = { |
1769 | [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, |
1770 | [MASTER_CDSP_PROC] = &qxm_nsp, |
1771 | [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, |
1772 | [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, |
1773 | }; |
1774 | |
1775 | static const struct qcom_icc_desc sc7280_nsp_noc = { |
1776 | .nodes = nsp_noc_nodes, |
1777 | .num_nodes = ARRAY_SIZE(nsp_noc_nodes), |
1778 | .bcms = nsp_noc_bcms, |
1779 | .num_bcms = ARRAY_SIZE(nsp_noc_bcms), |
1780 | }; |
1781 | |
1782 | static struct qcom_icc_bcm * const system_noc_bcms[] = { |
1783 | &bcm_sn0, |
1784 | &bcm_sn2, |
1785 | &bcm_sn7, |
1786 | &bcm_sn8, |
1787 | }; |
1788 | |
1789 | static struct qcom_icc_node * const system_noc_nodes[] = { |
1790 | [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, |
1791 | [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, |
1792 | [MASTER_SNOC_CFG] = &qnm_snoc_cfg, |
1793 | [MASTER_PIMEM] = &qxm_pimem, |
1794 | [MASTER_GIC] = &xm_gic, |
1795 | [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, |
1796 | [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, |
1797 | [SLAVE_SERVICE_SNOC] = &srvc_snoc, |
1798 | }; |
1799 | |
1800 | static const struct qcom_icc_desc sc7280_system_noc = { |
1801 | .nodes = system_noc_nodes, |
1802 | .num_nodes = ARRAY_SIZE(system_noc_nodes), |
1803 | .bcms = system_noc_bcms, |
1804 | .num_bcms = ARRAY_SIZE(system_noc_bcms), |
1805 | }; |
1806 | |
1807 | static const struct of_device_id qnoc_of_match[] = { |
1808 | { .compatible = "qcom,sc7280-aggre1-noc" , |
1809 | .data = &sc7280_aggre1_noc}, |
1810 | { .compatible = "qcom,sc7280-aggre2-noc" , |
1811 | .data = &sc7280_aggre2_noc}, |
1812 | { .compatible = "qcom,sc7280-clk-virt" , |
1813 | .data = &sc7280_clk_virt}, |
1814 | { .compatible = "qcom,sc7280-cnoc2" , |
1815 | .data = &sc7280_cnoc2}, |
1816 | { .compatible = "qcom,sc7280-cnoc3" , |
1817 | .data = &sc7280_cnoc3}, |
1818 | { .compatible = "qcom,sc7280-dc-noc" , |
1819 | .data = &sc7280_dc_noc}, |
1820 | { .compatible = "qcom,sc7280-gem-noc" , |
1821 | .data = &sc7280_gem_noc}, |
1822 | { .compatible = "qcom,sc7280-lpass-ag-noc" , |
1823 | .data = &sc7280_lpass_ag_noc}, |
1824 | { .compatible = "qcom,sc7280-mc-virt" , |
1825 | .data = &sc7280_mc_virt}, |
1826 | { .compatible = "qcom,sc7280-mmss-noc" , |
1827 | .data = &sc7280_mmss_noc}, |
1828 | { .compatible = "qcom,sc7280-nsp-noc" , |
1829 | .data = &sc7280_nsp_noc}, |
1830 | { .compatible = "qcom,sc7280-system-noc" , |
1831 | .data = &sc7280_system_noc}, |
1832 | { } |
1833 | }; |
1834 | MODULE_DEVICE_TABLE(of, qnoc_of_match); |
1835 | |
1836 | static struct platform_driver qnoc_driver = { |
1837 | .probe = qcom_icc_rpmh_probe, |
1838 | .remove_new = qcom_icc_rpmh_remove, |
1839 | .driver = { |
1840 | .name = "qnoc-sc7280" , |
1841 | .of_match_table = qnoc_of_match, |
1842 | .sync_state = icc_sync_state, |
1843 | }, |
1844 | }; |
1845 | module_platform_driver(qnoc_driver); |
1846 | |
1847 | MODULE_DESCRIPTION("SC7280 NoC driver" ); |
1848 | MODULE_LICENSE("GPL v2" ); |
1849 | |