1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (c) 2020, The Linux Foundation. All rights reserved. |
4 | * Copyright (c) 2021, Linaro Ltd. |
5 | */ |
6 | |
7 | #include <linux/device.h> |
8 | #include <linux/interconnect-provider.h> |
9 | #include <linux/module.h> |
10 | #include <linux/mod_devicetable.h> |
11 | #include <linux/platform_device.h> |
12 | |
13 | #include <dt-bindings/interconnect/qcom,sc8180x.h> |
14 | |
15 | #include "bcm-voter.h" |
16 | #include "icc-rpmh.h" |
17 | #include "sc8180x.h" |
18 | |
19 | static struct qcom_icc_node mas_qhm_a1noc_cfg = { |
20 | .name = "mas_qhm_a1noc_cfg" , |
21 | .id = SC8180X_MASTER_A1NOC_CFG, |
22 | .channels = 1, |
23 | .buswidth = 4, |
24 | .num_links = 1, |
25 | .links = { SC8180X_SLAVE_SERVICE_A1NOC } |
26 | }; |
27 | |
28 | static struct qcom_icc_node mas_xm_ufs_card = { |
29 | .name = "mas_xm_ufs_card" , |
30 | .id = SC8180X_MASTER_UFS_CARD, |
31 | .channels = 1, |
32 | .buswidth = 8, |
33 | .num_links = 1, |
34 | .links = { SC8180X_A1NOC_SNOC_SLV } |
35 | }; |
36 | |
37 | static struct qcom_icc_node mas_xm_ufs_g4 = { |
38 | .name = "mas_xm_ufs_g4" , |
39 | .id = SC8180X_MASTER_UFS_GEN4, |
40 | .channels = 1, |
41 | .buswidth = 8, |
42 | .num_links = 1, |
43 | .links = { SC8180X_A1NOC_SNOC_SLV } |
44 | }; |
45 | |
46 | static struct qcom_icc_node mas_xm_ufs_mem = { |
47 | .name = "mas_xm_ufs_mem" , |
48 | .id = SC8180X_MASTER_UFS_MEM, |
49 | .channels = 1, |
50 | .buswidth = 8, |
51 | .num_links = 1, |
52 | .links = { SC8180X_A1NOC_SNOC_SLV } |
53 | }; |
54 | |
55 | static struct qcom_icc_node mas_xm_usb3_0 = { |
56 | .name = "mas_xm_usb3_0" , |
57 | .id = SC8180X_MASTER_USB3, |
58 | .channels = 1, |
59 | .buswidth = 8, |
60 | .num_links = 1, |
61 | .links = { SC8180X_A1NOC_SNOC_SLV } |
62 | }; |
63 | |
64 | static struct qcom_icc_node mas_xm_usb3_1 = { |
65 | .name = "mas_xm_usb3_1" , |
66 | .id = SC8180X_MASTER_USB3_1, |
67 | .channels = 1, |
68 | .buswidth = 8, |
69 | .num_links = 1, |
70 | .links = { SC8180X_A1NOC_SNOC_SLV } |
71 | }; |
72 | |
73 | static struct qcom_icc_node mas_xm_usb3_2 = { |
74 | .name = "mas_xm_usb3_2" , |
75 | .id = SC8180X_MASTER_USB3_2, |
76 | .channels = 1, |
77 | .buswidth = 16, |
78 | .num_links = 1, |
79 | .links = { SC8180X_A1NOC_SNOC_SLV } |
80 | }; |
81 | |
82 | static struct qcom_icc_node mas_qhm_a2noc_cfg = { |
83 | .name = "mas_qhm_a2noc_cfg" , |
84 | .id = SC8180X_MASTER_A2NOC_CFG, |
85 | .channels = 1, |
86 | .buswidth = 4, |
87 | .num_links = 1, |
88 | .links = { SC8180X_SLAVE_SERVICE_A2NOC } |
89 | }; |
90 | |
91 | static struct qcom_icc_node mas_qhm_qdss_bam = { |
92 | .name = "mas_qhm_qdss_bam" , |
93 | .id = SC8180X_MASTER_QDSS_BAM, |
94 | .channels = 1, |
95 | .buswidth = 4, |
96 | .num_links = 1, |
97 | .links = { SC8180X_A2NOC_SNOC_SLV } |
98 | }; |
99 | |
100 | static struct qcom_icc_node mas_qhm_qspi = { |
101 | .name = "mas_qhm_qspi" , |
102 | .id = SC8180X_MASTER_QSPI_0, |
103 | .channels = 1, |
104 | .buswidth = 4, |
105 | .num_links = 1, |
106 | .links = { SC8180X_A2NOC_SNOC_SLV } |
107 | }; |
108 | |
109 | static struct qcom_icc_node mas_qhm_qspi1 = { |
110 | .name = "mas_qhm_qspi1" , |
111 | .id = SC8180X_MASTER_QSPI_1, |
112 | .channels = 1, |
113 | .buswidth = 4, |
114 | .num_links = 1, |
115 | .links = { SC8180X_A2NOC_SNOC_SLV } |
116 | }; |
117 | |
118 | static struct qcom_icc_node mas_qhm_qup0 = { |
119 | .name = "mas_qhm_qup0" , |
120 | .id = SC8180X_MASTER_QUP_0, |
121 | .channels = 1, |
122 | .buswidth = 4, |
123 | .num_links = 1, |
124 | .links = { SC8180X_A2NOC_SNOC_SLV } |
125 | }; |
126 | |
127 | static struct qcom_icc_node mas_qhm_qup1 = { |
128 | .name = "mas_qhm_qup1" , |
129 | .id = SC8180X_MASTER_QUP_1, |
130 | .channels = 1, |
131 | .buswidth = 4, |
132 | .num_links = 1, |
133 | .links = { SC8180X_A2NOC_SNOC_SLV } |
134 | }; |
135 | |
136 | static struct qcom_icc_node mas_qhm_qup2 = { |
137 | .name = "mas_qhm_qup2" , |
138 | .id = SC8180X_MASTER_QUP_2, |
139 | .channels = 1, |
140 | .buswidth = 4, |
141 | .num_links = 1, |
142 | .links = { SC8180X_A2NOC_SNOC_SLV } |
143 | }; |
144 | |
145 | static struct qcom_icc_node = { |
146 | .name = "mas_qhm_sensorss_ahb" , |
147 | .id = SC8180X_MASTER_SENSORS_AHB, |
148 | .channels = 1, |
149 | .buswidth = 4, |
150 | .num_links = 1, |
151 | .links = { SC8180X_A2NOC_SNOC_SLV } |
152 | }; |
153 | |
154 | static struct qcom_icc_node mas_qxm_crypto = { |
155 | .name = "mas_qxm_crypto" , |
156 | .id = SC8180X_MASTER_CRYPTO_CORE_0, |
157 | .channels = 1, |
158 | .buswidth = 8, |
159 | .num_links = 1, |
160 | .links = { SC8180X_A2NOC_SNOC_SLV } |
161 | }; |
162 | |
163 | static struct qcom_icc_node mas_qxm_ipa = { |
164 | .name = "mas_qxm_ipa" , |
165 | .id = SC8180X_MASTER_IPA, |
166 | .channels = 1, |
167 | .buswidth = 8, |
168 | .num_links = 1, |
169 | .links = { SC8180X_A2NOC_SNOC_SLV } |
170 | }; |
171 | |
172 | static struct qcom_icc_node mas_xm_emac = { |
173 | .name = "mas_xm_emac" , |
174 | .id = SC8180X_MASTER_EMAC, |
175 | .channels = 1, |
176 | .buswidth = 8, |
177 | .num_links = 1, |
178 | .links = { SC8180X_A2NOC_SNOC_SLV } |
179 | }; |
180 | |
181 | static struct qcom_icc_node mas_xm_pcie3_0 = { |
182 | .name = "mas_xm_pcie3_0" , |
183 | .id = SC8180X_MASTER_PCIE, |
184 | .channels = 1, |
185 | .buswidth = 8, |
186 | .num_links = 1, |
187 | .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } |
188 | }; |
189 | |
190 | static struct qcom_icc_node mas_xm_pcie3_1 = { |
191 | .name = "mas_xm_pcie3_1" , |
192 | .id = SC8180X_MASTER_PCIE_1, |
193 | .channels = 1, |
194 | .buswidth = 16, |
195 | .num_links = 1, |
196 | .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } |
197 | }; |
198 | |
199 | static struct qcom_icc_node mas_xm_pcie3_2 = { |
200 | .name = "mas_xm_pcie3_2" , |
201 | .id = SC8180X_MASTER_PCIE_2, |
202 | .channels = 1, |
203 | .buswidth = 8, |
204 | .num_links = 1, |
205 | .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } |
206 | }; |
207 | |
208 | static struct qcom_icc_node mas_xm_pcie3_3 = { |
209 | .name = "mas_xm_pcie3_3" , |
210 | .id = SC8180X_MASTER_PCIE_3, |
211 | .channels = 1, |
212 | .buswidth = 16, |
213 | .num_links = 1, |
214 | .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } |
215 | }; |
216 | |
217 | static struct qcom_icc_node mas_xm_qdss_etr = { |
218 | .name = "mas_xm_qdss_etr" , |
219 | .id = SC8180X_MASTER_QDSS_ETR, |
220 | .channels = 1, |
221 | .buswidth = 8, |
222 | .num_links = 1, |
223 | .links = { SC8180X_A2NOC_SNOC_SLV } |
224 | }; |
225 | |
226 | static struct qcom_icc_node mas_xm_sdc2 = { |
227 | .name = "mas_xm_sdc2" , |
228 | .id = SC8180X_MASTER_SDCC_2, |
229 | .channels = 1, |
230 | .buswidth = 8, |
231 | .num_links = 1, |
232 | .links = { SC8180X_A2NOC_SNOC_SLV } |
233 | }; |
234 | |
235 | static struct qcom_icc_node mas_xm_sdc4 = { |
236 | .name = "mas_xm_sdc4" , |
237 | .id = SC8180X_MASTER_SDCC_4, |
238 | .channels = 1, |
239 | .buswidth = 8, |
240 | .num_links = 1, |
241 | .links = { SC8180X_A2NOC_SNOC_SLV } |
242 | }; |
243 | |
244 | static struct qcom_icc_node mas_qxm_camnoc_hf0_uncomp = { |
245 | .name = "mas_qxm_camnoc_hf0_uncomp" , |
246 | .id = SC8180X_MASTER_CAMNOC_HF0_UNCOMP, |
247 | .channels = 1, |
248 | .buswidth = 32, |
249 | .num_links = 1, |
250 | .links = { SC8180X_SLAVE_CAMNOC_UNCOMP } |
251 | }; |
252 | |
253 | static struct qcom_icc_node mas_qxm_camnoc_hf1_uncomp = { |
254 | .name = "mas_qxm_camnoc_hf1_uncomp" , |
255 | .id = SC8180X_MASTER_CAMNOC_HF1_UNCOMP, |
256 | .channels = 1, |
257 | .buswidth = 32, |
258 | .num_links = 1, |
259 | .links = { SC8180X_SLAVE_CAMNOC_UNCOMP } |
260 | }; |
261 | |
262 | static struct qcom_icc_node mas_qxm_camnoc_sf_uncomp = { |
263 | .name = "mas_qxm_camnoc_sf_uncomp" , |
264 | .id = SC8180X_MASTER_CAMNOC_SF_UNCOMP, |
265 | .channels = 1, |
266 | .buswidth = 32, |
267 | .num_links = 1, |
268 | .links = { SC8180X_SLAVE_CAMNOC_UNCOMP } |
269 | }; |
270 | |
271 | static struct qcom_icc_node mas_qnm_npu = { |
272 | .name = "mas_qnm_npu" , |
273 | .id = SC8180X_MASTER_NPU, |
274 | .channels = 1, |
275 | .buswidth = 32, |
276 | .num_links = 1, |
277 | .links = { SC8180X_SLAVE_CDSP_MEM_NOC } |
278 | }; |
279 | |
280 | static struct qcom_icc_node mas_qnm_snoc = { |
281 | .name = "mas_qnm_snoc" , |
282 | .id = SC8180X_SNOC_CNOC_MAS, |
283 | .channels = 1, |
284 | .buswidth = 8, |
285 | .num_links = 56, |
286 | .links = { SC8180X_SLAVE_TLMM_SOUTH, |
287 | SC8180X_SLAVE_CDSP_CFG, |
288 | SC8180X_SLAVE_SPSS_CFG, |
289 | SC8180X_SLAVE_CAMERA_CFG, |
290 | SC8180X_SLAVE_SDCC_4, |
291 | SC8180X_SLAVE_AHB2PHY_CENTER, |
292 | SC8180X_SLAVE_SDCC_2, |
293 | SC8180X_SLAVE_PCIE_2_CFG, |
294 | SC8180X_SLAVE_CNOC_MNOC_CFG, |
295 | SC8180X_SLAVE_EMAC_CFG, |
296 | SC8180X_SLAVE_QSPI_0, |
297 | SC8180X_SLAVE_QSPI_1, |
298 | SC8180X_SLAVE_TLMM_EAST, |
299 | SC8180X_SLAVE_SNOC_CFG, |
300 | SC8180X_SLAVE_AHB2PHY_EAST, |
301 | SC8180X_SLAVE_GLM, |
302 | SC8180X_SLAVE_PDM, |
303 | SC8180X_SLAVE_PCIE_1_CFG, |
304 | SC8180X_SLAVE_A2NOC_CFG, |
305 | SC8180X_SLAVE_QDSS_CFG, |
306 | SC8180X_SLAVE_DISPLAY_CFG, |
307 | SC8180X_SLAVE_TCSR, |
308 | SC8180X_SLAVE_UFS_MEM_0_CFG, |
309 | SC8180X_SLAVE_CNOC_DDRSS, |
310 | SC8180X_SLAVE_PCIE_0_CFG, |
311 | SC8180X_SLAVE_QUP_1, |
312 | SC8180X_SLAVE_QUP_2, |
313 | SC8180X_SLAVE_NPU_CFG, |
314 | SC8180X_SLAVE_CRYPTO_0_CFG, |
315 | SC8180X_SLAVE_GRAPHICS_3D_CFG, |
316 | SC8180X_SLAVE_VENUS_CFG, |
317 | SC8180X_SLAVE_TSIF, |
318 | SC8180X_SLAVE_IPA_CFG, |
319 | SC8180X_SLAVE_CLK_CTL, |
320 | SC8180X_SLAVE_SECURITY, |
321 | SC8180X_SLAVE_AOP, |
322 | SC8180X_SLAVE_AHB2PHY_WEST, |
323 | SC8180X_SLAVE_AHB2PHY_SOUTH, |
324 | SC8180X_SLAVE_SERVICE_CNOC, |
325 | SC8180X_SLAVE_UFS_CARD_CFG, |
326 | SC8180X_SLAVE_USB3_1, |
327 | SC8180X_SLAVE_USB3_2, |
328 | SC8180X_SLAVE_PCIE_3_CFG, |
329 | SC8180X_SLAVE_RBCPR_CX_CFG, |
330 | SC8180X_SLAVE_TLMM_WEST, |
331 | SC8180X_SLAVE_A1NOC_CFG, |
332 | SC8180X_SLAVE_AOSS, |
333 | SC8180X_SLAVE_PRNG, |
334 | SC8180X_SLAVE_VSENSE_CTRL_CFG, |
335 | SC8180X_SLAVE_QUP_0, |
336 | SC8180X_SLAVE_USB3, |
337 | SC8180X_SLAVE_RBCPR_MMCX_CFG, |
338 | SC8180X_SLAVE_PIMEM_CFG, |
339 | SC8180X_SLAVE_UFS_MEM_1_CFG, |
340 | SC8180X_SLAVE_RBCPR_MX_CFG, |
341 | SC8180X_SLAVE_IMEM_CFG } |
342 | }; |
343 | |
344 | static struct qcom_icc_node mas_qhm_cnoc_dc_noc = { |
345 | .name = "mas_qhm_cnoc_dc_noc" , |
346 | .id = SC8180X_MASTER_CNOC_DC_NOC, |
347 | .channels = 1, |
348 | .buswidth = 4, |
349 | .num_links = 2, |
350 | .links = { SC8180X_SLAVE_LLCC_CFG, |
351 | SC8180X_SLAVE_GEM_NOC_CFG } |
352 | }; |
353 | |
354 | static struct qcom_icc_node mas_acm_apps = { |
355 | .name = "mas_acm_apps" , |
356 | .id = SC8180X_MASTER_AMPSS_M0, |
357 | .channels = 4, |
358 | .buswidth = 64, |
359 | .num_links = 3, |
360 | .links = { SC8180X_SLAVE_ECC, |
361 | SC8180X_SLAVE_LLCC, |
362 | SC8180X_SLAVE_GEM_NOC_SNOC } |
363 | }; |
364 | |
365 | static struct qcom_icc_node mas_acm_gpu_tcu = { |
366 | .name = "mas_acm_gpu_tcu" , |
367 | .id = SC8180X_MASTER_GPU_TCU, |
368 | .channels = 1, |
369 | .buswidth = 8, |
370 | .num_links = 2, |
371 | .links = { SC8180X_SLAVE_LLCC, |
372 | SC8180X_SLAVE_GEM_NOC_SNOC } |
373 | }; |
374 | |
375 | static struct qcom_icc_node mas_acm_sys_tcu = { |
376 | .name = "mas_acm_sys_tcu" , |
377 | .id = SC8180X_MASTER_SYS_TCU, |
378 | .channels = 1, |
379 | .buswidth = 8, |
380 | .num_links = 2, |
381 | .links = { SC8180X_SLAVE_LLCC, |
382 | SC8180X_SLAVE_GEM_NOC_SNOC } |
383 | }; |
384 | |
385 | static struct qcom_icc_node mas_qhm_gemnoc_cfg = { |
386 | .name = "mas_qhm_gemnoc_cfg" , |
387 | .id = SC8180X_MASTER_GEM_NOC_CFG, |
388 | .channels = 1, |
389 | .buswidth = 4, |
390 | .num_links = 3, |
391 | .links = { SC8180X_SLAVE_SERVICE_GEM_NOC_1, |
392 | SC8180X_SLAVE_SERVICE_GEM_NOC, |
393 | SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG } |
394 | }; |
395 | |
396 | static struct qcom_icc_node mas_qnm_cmpnoc = { |
397 | .name = "mas_qnm_cmpnoc" , |
398 | .id = SC8180X_MASTER_COMPUTE_NOC, |
399 | .channels = 2, |
400 | .buswidth = 32, |
401 | .num_links = 3, |
402 | .links = { SC8180X_SLAVE_ECC, |
403 | SC8180X_SLAVE_LLCC, |
404 | SC8180X_SLAVE_GEM_NOC_SNOC } |
405 | }; |
406 | |
407 | static struct qcom_icc_node mas_qnm_gpu = { |
408 | .name = "mas_qnm_gpu" , |
409 | .id = SC8180X_MASTER_GRAPHICS_3D, |
410 | .channels = 4, |
411 | .buswidth = 32, |
412 | .num_links = 2, |
413 | .links = { SC8180X_SLAVE_LLCC, |
414 | SC8180X_SLAVE_GEM_NOC_SNOC } |
415 | }; |
416 | |
417 | static struct qcom_icc_node mas_qnm_mnoc_hf = { |
418 | .name = "mas_qnm_mnoc_hf" , |
419 | .id = SC8180X_MASTER_MNOC_HF_MEM_NOC, |
420 | .channels = 2, |
421 | .buswidth = 32, |
422 | .num_links = 1, |
423 | .links = { SC8180X_SLAVE_LLCC } |
424 | }; |
425 | |
426 | static struct qcom_icc_node mas_qnm_mnoc_sf = { |
427 | .name = "mas_qnm_mnoc_sf" , |
428 | .id = SC8180X_MASTER_MNOC_SF_MEM_NOC, |
429 | .channels = 1, |
430 | .buswidth = 32, |
431 | .num_links = 2, |
432 | .links = { SC8180X_SLAVE_LLCC, |
433 | SC8180X_SLAVE_GEM_NOC_SNOC } |
434 | }; |
435 | |
436 | static struct qcom_icc_node mas_qnm_pcie = { |
437 | .name = "mas_qnm_pcie" , |
438 | .id = SC8180X_MASTER_GEM_NOC_PCIE_SNOC, |
439 | .channels = 1, |
440 | .buswidth = 32, |
441 | .num_links = 2, |
442 | .links = { SC8180X_SLAVE_LLCC, |
443 | SC8180X_SLAVE_GEM_NOC_SNOC } |
444 | }; |
445 | |
446 | static struct qcom_icc_node mas_qnm_snoc_gc = { |
447 | .name = "mas_qnm_snoc_gc" , |
448 | .id = SC8180X_MASTER_SNOC_GC_MEM_NOC, |
449 | .channels = 1, |
450 | .buswidth = 8, |
451 | .num_links = 1, |
452 | .links = { SC8180X_SLAVE_LLCC } |
453 | }; |
454 | |
455 | static struct qcom_icc_node mas_qnm_snoc_sf = { |
456 | .name = "mas_qnm_snoc_sf" , |
457 | .id = SC8180X_MASTER_SNOC_SF_MEM_NOC, |
458 | .channels = 1, |
459 | .buswidth = 32, |
460 | .num_links = 1, |
461 | .links = { SC8180X_SLAVE_LLCC } |
462 | }; |
463 | |
464 | static struct qcom_icc_node mas_qxm_ecc = { |
465 | .name = "mas_qxm_ecc" , |
466 | .id = SC8180X_MASTER_ECC, |
467 | .channels = 2, |
468 | .buswidth = 32, |
469 | .num_links = 1, |
470 | .links = { SC8180X_SLAVE_LLCC } |
471 | }; |
472 | |
473 | static struct qcom_icc_node mas_llcc_mc = { |
474 | .name = "mas_llcc_mc" , |
475 | .id = SC8180X_MASTER_LLCC, |
476 | .channels = 8, |
477 | .buswidth = 4, |
478 | .num_links = 1, |
479 | .links = { SC8180X_SLAVE_EBI_CH0 } |
480 | }; |
481 | |
482 | static struct qcom_icc_node mas_qhm_mnoc_cfg = { |
483 | .name = "mas_qhm_mnoc_cfg" , |
484 | .id = SC8180X_MASTER_CNOC_MNOC_CFG, |
485 | .channels = 1, |
486 | .buswidth = 4, |
487 | .num_links = 1, |
488 | .links = { SC8180X_SLAVE_SERVICE_MNOC } |
489 | }; |
490 | |
491 | static struct qcom_icc_node mas_qxm_camnoc_hf0 = { |
492 | .name = "mas_qxm_camnoc_hf0" , |
493 | .id = SC8180X_MASTER_CAMNOC_HF0, |
494 | .channels = 1, |
495 | .buswidth = 32, |
496 | .num_links = 1, |
497 | .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC } |
498 | }; |
499 | |
500 | static struct qcom_icc_node mas_qxm_camnoc_hf1 = { |
501 | .name = "mas_qxm_camnoc_hf1" , |
502 | .id = SC8180X_MASTER_CAMNOC_HF1, |
503 | .channels = 1, |
504 | .buswidth = 32, |
505 | .num_links = 1, |
506 | .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC } |
507 | }; |
508 | |
509 | static struct qcom_icc_node mas_qxm_camnoc_sf = { |
510 | .name = "mas_qxm_camnoc_sf" , |
511 | .id = SC8180X_MASTER_CAMNOC_SF, |
512 | .channels = 1, |
513 | .buswidth = 32, |
514 | .num_links = 1, |
515 | .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } |
516 | }; |
517 | |
518 | static struct qcom_icc_node mas_qxm_mdp0 = { |
519 | .name = "mas_qxm_mdp0" , |
520 | .id = SC8180X_MASTER_MDP_PORT0, |
521 | .channels = 1, |
522 | .buswidth = 32, |
523 | .num_links = 1, |
524 | .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC } |
525 | }; |
526 | |
527 | static struct qcom_icc_node mas_qxm_mdp1 = { |
528 | .name = "mas_qxm_mdp1" , |
529 | .id = SC8180X_MASTER_MDP_PORT1, |
530 | .channels = 1, |
531 | .buswidth = 32, |
532 | .num_links = 1, |
533 | .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC } |
534 | }; |
535 | |
536 | static struct qcom_icc_node mas_qxm_rot = { |
537 | .name = "mas_qxm_rot" , |
538 | .id = SC8180X_MASTER_ROTATOR, |
539 | .channels = 1, |
540 | .buswidth = 32, |
541 | .num_links = 1, |
542 | .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } |
543 | }; |
544 | |
545 | static struct qcom_icc_node mas_qxm_venus0 = { |
546 | .name = "mas_qxm_venus0" , |
547 | .id = SC8180X_MASTER_VIDEO_P0, |
548 | .channels = 1, |
549 | .buswidth = 32, |
550 | .num_links = 1, |
551 | .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } |
552 | }; |
553 | |
554 | static struct qcom_icc_node mas_qxm_venus1 = { |
555 | .name = "mas_qxm_venus1" , |
556 | .id = SC8180X_MASTER_VIDEO_P1, |
557 | .channels = 1, |
558 | .buswidth = 32, |
559 | .num_links = 1, |
560 | .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } |
561 | }; |
562 | |
563 | static struct qcom_icc_node mas_qxm_venus_arm9 = { |
564 | .name = "mas_qxm_venus_arm9" , |
565 | .id = SC8180X_MASTER_VIDEO_PROC, |
566 | .channels = 1, |
567 | .buswidth = 8, |
568 | .num_links = 1, |
569 | .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } |
570 | }; |
571 | |
572 | static struct qcom_icc_node mas_qhm_snoc_cfg = { |
573 | .name = "mas_qhm_snoc_cfg" , |
574 | .id = SC8180X_MASTER_SNOC_CFG, |
575 | .channels = 1, |
576 | .buswidth = 4, |
577 | .num_links = 1, |
578 | .links = { SC8180X_SLAVE_SERVICE_SNOC } |
579 | }; |
580 | |
581 | static struct qcom_icc_node mas_qnm_aggre1_noc = { |
582 | .name = "mas_qnm_aggre1_noc" , |
583 | .id = SC8180X_A1NOC_SNOC_MAS, |
584 | .channels = 1, |
585 | .buswidth = 32, |
586 | .num_links = 6, |
587 | .links = { SC8180X_SLAVE_SNOC_GEM_NOC_SF, |
588 | SC8180X_SLAVE_PIMEM, |
589 | SC8180X_SLAVE_OCIMEM, |
590 | SC8180X_SLAVE_APPSS, |
591 | SC8180X_SNOC_CNOC_SLV, |
592 | SC8180X_SLAVE_QDSS_STM } |
593 | }; |
594 | |
595 | static struct qcom_icc_node mas_qnm_aggre2_noc = { |
596 | .name = "mas_qnm_aggre2_noc" , |
597 | .id = SC8180X_A2NOC_SNOC_MAS, |
598 | .channels = 1, |
599 | .buswidth = 16, |
600 | .num_links = 11, |
601 | .links = { SC8180X_SLAVE_SNOC_GEM_NOC_SF, |
602 | SC8180X_SLAVE_PIMEM, |
603 | SC8180X_SLAVE_PCIE_3, |
604 | SC8180X_SLAVE_OCIMEM, |
605 | SC8180X_SLAVE_APPSS, |
606 | SC8180X_SLAVE_PCIE_2, |
607 | SC8180X_SNOC_CNOC_SLV, |
608 | SC8180X_SLAVE_PCIE_0, |
609 | SC8180X_SLAVE_PCIE_1, |
610 | SC8180X_SLAVE_TCU, |
611 | SC8180X_SLAVE_QDSS_STM } |
612 | }; |
613 | |
614 | static struct qcom_icc_node mas_qnm_gemnoc = { |
615 | .name = "mas_qnm_gemnoc" , |
616 | .id = SC8180X_MASTER_GEM_NOC_SNOC, |
617 | .channels = 1, |
618 | .buswidth = 8, |
619 | .num_links = 6, |
620 | .links = { SC8180X_SLAVE_PIMEM, |
621 | SC8180X_SLAVE_OCIMEM, |
622 | SC8180X_SLAVE_APPSS, |
623 | SC8180X_SNOC_CNOC_SLV, |
624 | SC8180X_SLAVE_TCU, |
625 | SC8180X_SLAVE_QDSS_STM } |
626 | }; |
627 | |
628 | static struct qcom_icc_node mas_qxm_pimem = { |
629 | .name = "mas_qxm_pimem" , |
630 | .id = SC8180X_MASTER_PIMEM, |
631 | .channels = 1, |
632 | .buswidth = 8, |
633 | .num_links = 2, |
634 | .links = { SC8180X_SLAVE_SNOC_GEM_NOC_GC, |
635 | SC8180X_SLAVE_OCIMEM } |
636 | }; |
637 | |
638 | static struct qcom_icc_node mas_xm_gic = { |
639 | .name = "mas_xm_gic" , |
640 | .id = SC8180X_MASTER_GIC, |
641 | .channels = 1, |
642 | .buswidth = 8, |
643 | .num_links = 2, |
644 | .links = { SC8180X_SLAVE_SNOC_GEM_NOC_GC, |
645 | SC8180X_SLAVE_OCIMEM } |
646 | }; |
647 | |
648 | static struct qcom_icc_node mas_qup_core_0 = { |
649 | .name = "mas_qup_core_0" , |
650 | .id = SC8180X_MASTER_QUP_CORE_0, |
651 | .channels = 1, |
652 | .buswidth = 4, |
653 | .num_links = 1, |
654 | .links = { SC8180X_SLAVE_QUP_CORE_0 } |
655 | }; |
656 | |
657 | static struct qcom_icc_node mas_qup_core_1 = { |
658 | .name = "mas_qup_core_1" , |
659 | .id = SC8180X_MASTER_QUP_CORE_1, |
660 | .channels = 1, |
661 | .buswidth = 4, |
662 | .num_links = 1, |
663 | .links = { SC8180X_SLAVE_QUP_CORE_1 } |
664 | }; |
665 | |
666 | static struct qcom_icc_node mas_qup_core_2 = { |
667 | .name = "mas_qup_core_2" , |
668 | .id = SC8180X_MASTER_QUP_CORE_2, |
669 | .channels = 1, |
670 | .buswidth = 4, |
671 | .num_links = 1, |
672 | .links = { SC8180X_SLAVE_QUP_CORE_2 } |
673 | }; |
674 | |
675 | static struct qcom_icc_node slv_qns_a1noc_snoc = { |
676 | .name = "slv_qns_a1noc_snoc" , |
677 | .id = SC8180X_A1NOC_SNOC_SLV, |
678 | .channels = 1, |
679 | .buswidth = 32, |
680 | .num_links = 1, |
681 | .links = { SC8180X_A1NOC_SNOC_MAS } |
682 | }; |
683 | |
684 | static struct qcom_icc_node slv_srvc_aggre1_noc = { |
685 | .name = "slv_srvc_aggre1_noc" , |
686 | .id = SC8180X_SLAVE_SERVICE_A1NOC, |
687 | .channels = 1, |
688 | .buswidth = 4 |
689 | }; |
690 | |
691 | static struct qcom_icc_node slv_qns_a2noc_snoc = { |
692 | .name = "slv_qns_a2noc_snoc" , |
693 | .id = SC8180X_A2NOC_SNOC_SLV, |
694 | .channels = 1, |
695 | .buswidth = 16, |
696 | .num_links = 1, |
697 | .links = { SC8180X_A2NOC_SNOC_MAS } |
698 | }; |
699 | |
700 | static struct qcom_icc_node slv_qns_pcie_mem_noc = { |
701 | .name = "slv_qns_pcie_mem_noc" , |
702 | .id = SC8180X_SLAVE_ANOC_PCIE_GEM_NOC, |
703 | .channels = 1, |
704 | .buswidth = 32, |
705 | .num_links = 1, |
706 | .links = { SC8180X_MASTER_GEM_NOC_PCIE_SNOC } |
707 | }; |
708 | |
709 | static struct qcom_icc_node slv_srvc_aggre2_noc = { |
710 | .name = "slv_srvc_aggre2_noc" , |
711 | .id = SC8180X_SLAVE_SERVICE_A2NOC, |
712 | .channels = 1, |
713 | .buswidth = 4 |
714 | }; |
715 | |
716 | static struct qcom_icc_node slv_qns_camnoc_uncomp = { |
717 | .name = "slv_qns_camnoc_uncomp" , |
718 | .id = SC8180X_SLAVE_CAMNOC_UNCOMP, |
719 | .channels = 1, |
720 | .buswidth = 32 |
721 | }; |
722 | |
723 | static struct qcom_icc_node slv_qns_cdsp_mem_noc = { |
724 | .name = "slv_qns_cdsp_mem_noc" , |
725 | .id = SC8180X_SLAVE_CDSP_MEM_NOC, |
726 | .channels = 2, |
727 | .buswidth = 32, |
728 | .num_links = 1, |
729 | .links = { SC8180X_MASTER_COMPUTE_NOC } |
730 | }; |
731 | |
732 | static struct qcom_icc_node slv_qhs_a1_noc_cfg = { |
733 | .name = "slv_qhs_a1_noc_cfg" , |
734 | .id = SC8180X_SLAVE_A1NOC_CFG, |
735 | .channels = 1, |
736 | .buswidth = 4, |
737 | .num_links = 1, |
738 | .links = { SC8180X_MASTER_A1NOC_CFG } |
739 | }; |
740 | |
741 | static struct qcom_icc_node slv_qhs_a2_noc_cfg = { |
742 | .name = "slv_qhs_a2_noc_cfg" , |
743 | .id = SC8180X_SLAVE_A2NOC_CFG, |
744 | .channels = 1, |
745 | .buswidth = 4, |
746 | .num_links = 1, |
747 | .links = { SC8180X_MASTER_A2NOC_CFG } |
748 | }; |
749 | |
750 | static struct qcom_icc_node slv_qhs_ahb2phy_refgen_center = { |
751 | .name = "slv_qhs_ahb2phy_refgen_center" , |
752 | .id = SC8180X_SLAVE_AHB2PHY_CENTER, |
753 | .channels = 1, |
754 | .buswidth = 4 |
755 | }; |
756 | |
757 | static struct qcom_icc_node slv_qhs_ahb2phy_refgen_east = { |
758 | .name = "slv_qhs_ahb2phy_refgen_east" , |
759 | .id = SC8180X_SLAVE_AHB2PHY_EAST, |
760 | .channels = 1, |
761 | .buswidth = 4 |
762 | }; |
763 | |
764 | static struct qcom_icc_node slv_qhs_ahb2phy_refgen_west = { |
765 | .name = "slv_qhs_ahb2phy_refgen_west" , |
766 | .id = SC8180X_SLAVE_AHB2PHY_WEST, |
767 | .channels = 1, |
768 | .buswidth = 4 |
769 | }; |
770 | |
771 | static struct qcom_icc_node slv_qhs_ahb2phy_south = { |
772 | .name = "slv_qhs_ahb2phy_south" , |
773 | .id = SC8180X_SLAVE_AHB2PHY_SOUTH, |
774 | .channels = 1, |
775 | .buswidth = 4 |
776 | }; |
777 | |
778 | static struct qcom_icc_node slv_qhs_aop = { |
779 | .name = "slv_qhs_aop" , |
780 | .id = SC8180X_SLAVE_AOP, |
781 | .channels = 1, |
782 | .buswidth = 4 |
783 | }; |
784 | |
785 | static struct qcom_icc_node slv_qhs_aoss = { |
786 | .name = "slv_qhs_aoss" , |
787 | .id = SC8180X_SLAVE_AOSS, |
788 | .channels = 1, |
789 | .buswidth = 4 |
790 | }; |
791 | |
792 | static struct qcom_icc_node slv_qhs_camera_cfg = { |
793 | .name = "slv_qhs_camera_cfg" , |
794 | .id = SC8180X_SLAVE_CAMERA_CFG, |
795 | .channels = 1, |
796 | .buswidth = 4 |
797 | }; |
798 | |
799 | static struct qcom_icc_node slv_qhs_clk_ctl = { |
800 | .name = "slv_qhs_clk_ctl" , |
801 | .id = SC8180X_SLAVE_CLK_CTL, |
802 | .channels = 1, |
803 | .buswidth = 4 |
804 | }; |
805 | |
806 | static struct qcom_icc_node slv_qhs_compute_dsp = { |
807 | .name = "slv_qhs_compute_dsp" , |
808 | .id = SC8180X_SLAVE_CDSP_CFG, |
809 | .channels = 1, |
810 | .buswidth = 4 |
811 | }; |
812 | |
813 | static struct qcom_icc_node slv_qhs_cpr_cx = { |
814 | .name = "slv_qhs_cpr_cx" , |
815 | .id = SC8180X_SLAVE_RBCPR_CX_CFG, |
816 | .channels = 1, |
817 | .buswidth = 4 |
818 | }; |
819 | |
820 | static struct qcom_icc_node slv_qhs_cpr_mmcx = { |
821 | .name = "slv_qhs_cpr_mmcx" , |
822 | .id = SC8180X_SLAVE_RBCPR_MMCX_CFG, |
823 | .channels = 1, |
824 | .buswidth = 4 |
825 | }; |
826 | |
827 | static struct qcom_icc_node slv_qhs_cpr_mx = { |
828 | .name = "slv_qhs_cpr_mx" , |
829 | .id = SC8180X_SLAVE_RBCPR_MX_CFG, |
830 | .channels = 1, |
831 | .buswidth = 4 |
832 | }; |
833 | |
834 | static struct qcom_icc_node slv_qhs_crypto0_cfg = { |
835 | .name = "slv_qhs_crypto0_cfg" , |
836 | .id = SC8180X_SLAVE_CRYPTO_0_CFG, |
837 | .channels = 1, |
838 | .buswidth = 4 |
839 | }; |
840 | |
841 | static struct qcom_icc_node = { |
842 | .name = "slv_qhs_ddrss_cfg" , |
843 | .id = SC8180X_SLAVE_CNOC_DDRSS, |
844 | .channels = 1, |
845 | .buswidth = 4, |
846 | .num_links = 1, |
847 | .links = { SC8180X_MASTER_CNOC_DC_NOC } |
848 | }; |
849 | |
850 | static struct qcom_icc_node slv_qhs_display_cfg = { |
851 | .name = "slv_qhs_display_cfg" , |
852 | .id = SC8180X_SLAVE_DISPLAY_CFG, |
853 | .channels = 1, |
854 | .buswidth = 4 |
855 | }; |
856 | |
857 | static struct qcom_icc_node slv_qhs_emac_cfg = { |
858 | .name = "slv_qhs_emac_cfg" , |
859 | .id = SC8180X_SLAVE_EMAC_CFG, |
860 | .channels = 1, |
861 | .buswidth = 4 |
862 | }; |
863 | |
864 | static struct qcom_icc_node slv_qhs_glm = { |
865 | .name = "slv_qhs_glm" , |
866 | .id = SC8180X_SLAVE_GLM, |
867 | .channels = 1, |
868 | .buswidth = 4 |
869 | }; |
870 | |
871 | static struct qcom_icc_node slv_qhs_gpuss_cfg = { |
872 | .name = "slv_qhs_gpuss_cfg" , |
873 | .id = SC8180X_SLAVE_GRAPHICS_3D_CFG, |
874 | .channels = 1, |
875 | .buswidth = 8 |
876 | }; |
877 | |
878 | static struct qcom_icc_node slv_qhs_imem_cfg = { |
879 | .name = "slv_qhs_imem_cfg" , |
880 | .id = SC8180X_SLAVE_IMEM_CFG, |
881 | .channels = 1, |
882 | .buswidth = 4 |
883 | }; |
884 | |
885 | static struct qcom_icc_node slv_qhs_ipa = { |
886 | .name = "slv_qhs_ipa" , |
887 | .id = SC8180X_SLAVE_IPA_CFG, |
888 | .channels = 1, |
889 | .buswidth = 4 |
890 | }; |
891 | |
892 | static struct qcom_icc_node slv_qhs_mnoc_cfg = { |
893 | .name = "slv_qhs_mnoc_cfg" , |
894 | .id = SC8180X_SLAVE_CNOC_MNOC_CFG, |
895 | .channels = 1, |
896 | .buswidth = 4, |
897 | .num_links = 1, |
898 | .links = { SC8180X_MASTER_CNOC_MNOC_CFG } |
899 | }; |
900 | |
901 | static struct qcom_icc_node slv_qhs_npu_cfg = { |
902 | .name = "slv_qhs_npu_cfg" , |
903 | .id = SC8180X_SLAVE_NPU_CFG, |
904 | .channels = 1, |
905 | .buswidth = 4 |
906 | }; |
907 | |
908 | static struct qcom_icc_node slv_qhs_pcie0_cfg = { |
909 | .name = "slv_qhs_pcie0_cfg" , |
910 | .id = SC8180X_SLAVE_PCIE_0_CFG, |
911 | .channels = 1, |
912 | .buswidth = 4 |
913 | }; |
914 | |
915 | static struct qcom_icc_node slv_qhs_pcie1_cfg = { |
916 | .name = "slv_qhs_pcie1_cfg" , |
917 | .id = SC8180X_SLAVE_PCIE_1_CFG, |
918 | .channels = 1, |
919 | .buswidth = 4 |
920 | }; |
921 | |
922 | static struct qcom_icc_node slv_qhs_pcie2_cfg = { |
923 | .name = "slv_qhs_pcie2_cfg" , |
924 | .id = SC8180X_SLAVE_PCIE_2_CFG, |
925 | .channels = 1, |
926 | .buswidth = 4 |
927 | }; |
928 | |
929 | static struct qcom_icc_node slv_qhs_pcie3_cfg = { |
930 | .name = "slv_qhs_pcie3_cfg" , |
931 | .id = SC8180X_SLAVE_PCIE_3_CFG, |
932 | .channels = 1, |
933 | .buswidth = 4 |
934 | }; |
935 | |
936 | static struct qcom_icc_node slv_qhs_pdm = { |
937 | .name = "slv_qhs_pdm" , |
938 | .id = SC8180X_SLAVE_PDM, |
939 | .channels = 1, |
940 | .buswidth = 4 |
941 | }; |
942 | |
943 | static struct qcom_icc_node slv_qhs_pimem_cfg = { |
944 | .name = "slv_qhs_pimem_cfg" , |
945 | .id = SC8180X_SLAVE_PIMEM_CFG, |
946 | .channels = 1, |
947 | .buswidth = 4 |
948 | }; |
949 | |
950 | static struct qcom_icc_node slv_qhs_prng = { |
951 | .name = "slv_qhs_prng" , |
952 | .id = SC8180X_SLAVE_PRNG, |
953 | .channels = 1, |
954 | .buswidth = 4 |
955 | }; |
956 | |
957 | static struct qcom_icc_node slv_qhs_qdss_cfg = { |
958 | .name = "slv_qhs_qdss_cfg" , |
959 | .id = SC8180X_SLAVE_QDSS_CFG, |
960 | .channels = 1, |
961 | .buswidth = 4 |
962 | }; |
963 | |
964 | static struct qcom_icc_node slv_qhs_qspi_0 = { |
965 | .name = "slv_qhs_qspi_0" , |
966 | .id = SC8180X_SLAVE_QSPI_0, |
967 | .channels = 1, |
968 | .buswidth = 4 |
969 | }; |
970 | |
971 | static struct qcom_icc_node slv_qhs_qspi_1 = { |
972 | .name = "slv_qhs_qspi_1" , |
973 | .id = SC8180X_SLAVE_QSPI_1, |
974 | .channels = 1, |
975 | .buswidth = 4 |
976 | }; |
977 | |
978 | static struct qcom_icc_node slv_qhs_qupv3_east0 = { |
979 | .name = "slv_qhs_qupv3_east0" , |
980 | .id = SC8180X_SLAVE_QUP_1, |
981 | .channels = 1, |
982 | .buswidth = 4 |
983 | }; |
984 | |
985 | static struct qcom_icc_node slv_qhs_qupv3_east1 = { |
986 | .name = "slv_qhs_qupv3_east1" , |
987 | .id = SC8180X_SLAVE_QUP_2, |
988 | .channels = 1, |
989 | .buswidth = 4 |
990 | }; |
991 | |
992 | static struct qcom_icc_node slv_qhs_qupv3_west = { |
993 | .name = "slv_qhs_qupv3_west" , |
994 | .id = SC8180X_SLAVE_QUP_0, |
995 | .channels = 1, |
996 | .buswidth = 4 |
997 | }; |
998 | |
999 | static struct qcom_icc_node slv_qhs_sdc2 = { |
1000 | .name = "slv_qhs_sdc2" , |
1001 | .id = SC8180X_SLAVE_SDCC_2, |
1002 | .channels = 1, |
1003 | .buswidth = 4 |
1004 | }; |
1005 | |
1006 | static struct qcom_icc_node slv_qhs_sdc4 = { |
1007 | .name = "slv_qhs_sdc4" , |
1008 | .id = SC8180X_SLAVE_SDCC_4, |
1009 | .channels = 1, |
1010 | .buswidth = 4 |
1011 | }; |
1012 | |
1013 | static struct qcom_icc_node slv_qhs_security = { |
1014 | .name = "slv_qhs_security" , |
1015 | .id = SC8180X_SLAVE_SECURITY, |
1016 | .channels = 1, |
1017 | .buswidth = 4 |
1018 | }; |
1019 | |
1020 | static struct qcom_icc_node slv_qhs_snoc_cfg = { |
1021 | .name = "slv_qhs_snoc_cfg" , |
1022 | .id = SC8180X_SLAVE_SNOC_CFG, |
1023 | .channels = 1, |
1024 | .buswidth = 4, |
1025 | .num_links = 1, |
1026 | .links = { SC8180X_MASTER_SNOC_CFG } |
1027 | }; |
1028 | |
1029 | static struct qcom_icc_node slv_qhs_spss_cfg = { |
1030 | .name = "slv_qhs_spss_cfg" , |
1031 | .id = SC8180X_SLAVE_SPSS_CFG, |
1032 | .channels = 1, |
1033 | .buswidth = 4 |
1034 | }; |
1035 | |
1036 | static struct qcom_icc_node slv_qhs_tcsr = { |
1037 | .name = "slv_qhs_tcsr" , |
1038 | .id = SC8180X_SLAVE_TCSR, |
1039 | .channels = 1, |
1040 | .buswidth = 4 |
1041 | }; |
1042 | |
1043 | static struct qcom_icc_node slv_qhs_tlmm_east = { |
1044 | .name = "slv_qhs_tlmm_east" , |
1045 | .id = SC8180X_SLAVE_TLMM_EAST, |
1046 | .channels = 1, |
1047 | .buswidth = 4 |
1048 | }; |
1049 | |
1050 | static struct qcom_icc_node slv_qhs_tlmm_south = { |
1051 | .name = "slv_qhs_tlmm_south" , |
1052 | .id = SC8180X_SLAVE_TLMM_SOUTH, |
1053 | .channels = 1, |
1054 | .buswidth = 4 |
1055 | }; |
1056 | |
1057 | static struct qcom_icc_node slv_qhs_tlmm_west = { |
1058 | .name = "slv_qhs_tlmm_west" , |
1059 | .id = SC8180X_SLAVE_TLMM_WEST, |
1060 | .channels = 1, |
1061 | .buswidth = 4 |
1062 | }; |
1063 | |
1064 | static struct qcom_icc_node slv_qhs_tsif = { |
1065 | .name = "slv_qhs_tsif" , |
1066 | .id = SC8180X_SLAVE_TSIF, |
1067 | .channels = 1, |
1068 | .buswidth = 4 |
1069 | }; |
1070 | |
1071 | static struct qcom_icc_node slv_qhs_ufs_card_cfg = { |
1072 | .name = "slv_qhs_ufs_card_cfg" , |
1073 | .id = SC8180X_SLAVE_UFS_CARD_CFG, |
1074 | .channels = 1, |
1075 | .buswidth = 4 |
1076 | }; |
1077 | |
1078 | static struct qcom_icc_node slv_qhs_ufs_mem0_cfg = { |
1079 | .name = "slv_qhs_ufs_mem0_cfg" , |
1080 | .id = SC8180X_SLAVE_UFS_MEM_0_CFG, |
1081 | .channels = 1, |
1082 | .buswidth = 4 |
1083 | }; |
1084 | |
1085 | static struct qcom_icc_node slv_qhs_ufs_mem1_cfg = { |
1086 | .name = "slv_qhs_ufs_mem1_cfg" , |
1087 | .id = SC8180X_SLAVE_UFS_MEM_1_CFG, |
1088 | .channels = 1, |
1089 | .buswidth = 4 |
1090 | }; |
1091 | |
1092 | static struct qcom_icc_node slv_qhs_usb3_0 = { |
1093 | .name = "slv_qhs_usb3_0" , |
1094 | .id = SC8180X_SLAVE_USB3, |
1095 | .channels = 1, |
1096 | .buswidth = 4 |
1097 | }; |
1098 | |
1099 | static struct qcom_icc_node slv_qhs_usb3_1 = { |
1100 | .name = "slv_qhs_usb3_1" , |
1101 | .id = SC8180X_SLAVE_USB3_1, |
1102 | .channels = 1, |
1103 | .buswidth = 4 |
1104 | }; |
1105 | |
1106 | static struct qcom_icc_node slv_qhs_usb3_2 = { |
1107 | .name = "slv_qhs_usb3_2" , |
1108 | .id = SC8180X_SLAVE_USB3_2, |
1109 | .channels = 1, |
1110 | .buswidth = 4 |
1111 | }; |
1112 | |
1113 | static struct qcom_icc_node slv_qhs_venus_cfg = { |
1114 | .name = "slv_qhs_venus_cfg" , |
1115 | .id = SC8180X_SLAVE_VENUS_CFG, |
1116 | .channels = 1, |
1117 | .buswidth = 4 |
1118 | }; |
1119 | |
1120 | static struct qcom_icc_node slv_qhs_vsense_ctrl_cfg = { |
1121 | .name = "slv_qhs_vsense_ctrl_cfg" , |
1122 | .id = SC8180X_SLAVE_VSENSE_CTRL_CFG, |
1123 | .channels = 1, |
1124 | .buswidth = 4 |
1125 | }; |
1126 | |
1127 | static struct qcom_icc_node slv_srvc_cnoc = { |
1128 | .name = "slv_srvc_cnoc" , |
1129 | .id = SC8180X_SLAVE_SERVICE_CNOC, |
1130 | .channels = 1, |
1131 | .buswidth = 4 |
1132 | }; |
1133 | |
1134 | static struct qcom_icc_node slv_qhs_gemnoc = { |
1135 | .name = "slv_qhs_gemnoc" , |
1136 | .id = SC8180X_SLAVE_GEM_NOC_CFG, |
1137 | .channels = 1, |
1138 | .buswidth = 4, |
1139 | .num_links = 1, |
1140 | .links = { SC8180X_MASTER_GEM_NOC_CFG } |
1141 | }; |
1142 | |
1143 | static struct qcom_icc_node slv_qhs_llcc = { |
1144 | .name = "slv_qhs_llcc" , |
1145 | .id = SC8180X_SLAVE_LLCC_CFG, |
1146 | .channels = 1, |
1147 | .buswidth = 4 |
1148 | }; |
1149 | |
1150 | static struct qcom_icc_node slv_qhs_mdsp_ms_mpu_cfg = { |
1151 | .name = "slv_qhs_mdsp_ms_mpu_cfg" , |
1152 | .id = SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG, |
1153 | .channels = 1, |
1154 | .buswidth = 4 |
1155 | }; |
1156 | |
1157 | static struct qcom_icc_node slv_qns_ecc = { |
1158 | .name = "slv_qns_ecc" , |
1159 | .id = SC8180X_SLAVE_ECC, |
1160 | .channels = 1, |
1161 | .buswidth = 32 |
1162 | }; |
1163 | |
1164 | static struct qcom_icc_node slv_qns_gem_noc_snoc = { |
1165 | .name = "slv_qns_gem_noc_snoc" , |
1166 | .id = SC8180X_SLAVE_GEM_NOC_SNOC, |
1167 | .channels = 1, |
1168 | .buswidth = 8, |
1169 | .num_links = 1, |
1170 | .links = { SC8180X_MASTER_GEM_NOC_SNOC } |
1171 | }; |
1172 | |
1173 | static struct qcom_icc_node slv_qns_llcc = { |
1174 | .name = "slv_qns_llcc" , |
1175 | .id = SC8180X_SLAVE_LLCC, |
1176 | .channels = 8, |
1177 | .buswidth = 16, |
1178 | .num_links = 1, |
1179 | .links = { SC8180X_MASTER_LLCC } |
1180 | }; |
1181 | |
1182 | static struct qcom_icc_node slv_srvc_gemnoc = { |
1183 | .name = "slv_srvc_gemnoc" , |
1184 | .id = SC8180X_SLAVE_SERVICE_GEM_NOC, |
1185 | .channels = 1, |
1186 | .buswidth = 4 |
1187 | }; |
1188 | |
1189 | static struct qcom_icc_node slv_srvc_gemnoc1 = { |
1190 | .name = "slv_srvc_gemnoc1" , |
1191 | .id = SC8180X_SLAVE_SERVICE_GEM_NOC_1, |
1192 | .channels = 1, |
1193 | .buswidth = 4 |
1194 | }; |
1195 | |
1196 | static struct qcom_icc_node slv_ebi = { |
1197 | .name = "slv_ebi" , |
1198 | .id = SC8180X_SLAVE_EBI_CH0, |
1199 | .channels = 8, |
1200 | .buswidth = 4 |
1201 | }; |
1202 | |
1203 | static struct qcom_icc_node slv_qns2_mem_noc = { |
1204 | .name = "slv_qns2_mem_noc" , |
1205 | .id = SC8180X_SLAVE_MNOC_SF_MEM_NOC, |
1206 | .channels = 1, |
1207 | .buswidth = 32, |
1208 | .num_links = 1, |
1209 | .links = { SC8180X_MASTER_MNOC_SF_MEM_NOC } |
1210 | }; |
1211 | |
1212 | static struct qcom_icc_node slv_qns_mem_noc_hf = { |
1213 | .name = "slv_qns_mem_noc_hf" , |
1214 | .id = SC8180X_SLAVE_MNOC_HF_MEM_NOC, |
1215 | .channels = 2, |
1216 | .buswidth = 32, |
1217 | .num_links = 1, |
1218 | .links = { SC8180X_MASTER_MNOC_HF_MEM_NOC } |
1219 | }; |
1220 | |
1221 | static struct qcom_icc_node slv_srvc_mnoc = { |
1222 | .name = "slv_srvc_mnoc" , |
1223 | .id = SC8180X_SLAVE_SERVICE_MNOC, |
1224 | .channels = 1, |
1225 | .buswidth = 4 |
1226 | }; |
1227 | |
1228 | static struct qcom_icc_node slv_qhs_apss = { |
1229 | .name = "slv_qhs_apss" , |
1230 | .id = SC8180X_SLAVE_APPSS, |
1231 | .channels = 1, |
1232 | .buswidth = 8 |
1233 | }; |
1234 | |
1235 | static struct qcom_icc_node slv_qns_cnoc = { |
1236 | .name = "slv_qns_cnoc" , |
1237 | .id = SC8180X_SNOC_CNOC_SLV, |
1238 | .channels = 1, |
1239 | .buswidth = 8, |
1240 | .num_links = 1, |
1241 | .links = { SC8180X_SNOC_CNOC_MAS } |
1242 | }; |
1243 | |
1244 | static struct qcom_icc_node slv_qns_gemnoc_gc = { |
1245 | .name = "slv_qns_gemnoc_gc" , |
1246 | .id = SC8180X_SLAVE_SNOC_GEM_NOC_GC, |
1247 | .channels = 1, |
1248 | .buswidth = 8, |
1249 | .num_links = 1, |
1250 | .links = { SC8180X_MASTER_SNOC_GC_MEM_NOC } |
1251 | }; |
1252 | |
1253 | static struct qcom_icc_node slv_qns_gemnoc_sf = { |
1254 | .name = "slv_qns_gemnoc_sf" , |
1255 | .id = SC8180X_SLAVE_SNOC_GEM_NOC_SF, |
1256 | .channels = 1, |
1257 | .buswidth = 32, |
1258 | .num_links = 1, |
1259 | .links = { SC8180X_MASTER_SNOC_SF_MEM_NOC } |
1260 | }; |
1261 | |
1262 | static struct qcom_icc_node slv_qxs_imem = { |
1263 | .name = "slv_qxs_imem" , |
1264 | .id = SC8180X_SLAVE_OCIMEM, |
1265 | .channels = 1, |
1266 | .buswidth = 8 |
1267 | }; |
1268 | |
1269 | static struct qcom_icc_node slv_qxs_pimem = { |
1270 | .name = "slv_qxs_pimem" , |
1271 | .id = SC8180X_SLAVE_PIMEM, |
1272 | .channels = 1, |
1273 | .buswidth = 8 |
1274 | }; |
1275 | |
1276 | static struct qcom_icc_node slv_srvc_snoc = { |
1277 | .name = "slv_srvc_snoc" , |
1278 | .id = SC8180X_SLAVE_SERVICE_SNOC, |
1279 | .channels = 1, |
1280 | .buswidth = 4 |
1281 | }; |
1282 | |
1283 | static struct qcom_icc_node slv_xs_pcie_0 = { |
1284 | .name = "slv_xs_pcie_0" , |
1285 | .id = SC8180X_SLAVE_PCIE_0, |
1286 | .channels = 1, |
1287 | .buswidth = 8 |
1288 | }; |
1289 | |
1290 | static struct qcom_icc_node slv_xs_pcie_1 = { |
1291 | .name = "slv_xs_pcie_1" , |
1292 | .id = SC8180X_SLAVE_PCIE_1, |
1293 | .channels = 1, |
1294 | .buswidth = 8 |
1295 | }; |
1296 | |
1297 | static struct qcom_icc_node slv_xs_pcie_2 = { |
1298 | .name = "slv_xs_pcie_2" , |
1299 | .id = SC8180X_SLAVE_PCIE_2, |
1300 | .channels = 1, |
1301 | .buswidth = 8 |
1302 | }; |
1303 | |
1304 | static struct qcom_icc_node slv_xs_pcie_3 = { |
1305 | .name = "slv_xs_pcie_3" , |
1306 | .id = SC8180X_SLAVE_PCIE_3, |
1307 | .channels = 1, |
1308 | .buswidth = 8 |
1309 | }; |
1310 | |
1311 | static struct qcom_icc_node slv_xs_qdss_stm = { |
1312 | .name = "slv_xs_qdss_stm" , |
1313 | .id = SC8180X_SLAVE_QDSS_STM, |
1314 | .channels = 1, |
1315 | .buswidth = 4 |
1316 | }; |
1317 | |
1318 | static struct qcom_icc_node slv_xs_sys_tcu_cfg = { |
1319 | .name = "slv_xs_sys_tcu_cfg" , |
1320 | .id = SC8180X_SLAVE_TCU, |
1321 | .channels = 1, |
1322 | .buswidth = 8 |
1323 | }; |
1324 | |
1325 | static struct qcom_icc_node slv_qup_core_0 = { |
1326 | .name = "slv_qup_core_0" , |
1327 | .id = SC8180X_SLAVE_QUP_CORE_0, |
1328 | .channels = 1, |
1329 | .buswidth = 4 |
1330 | }; |
1331 | |
1332 | static struct qcom_icc_node slv_qup_core_1 = { |
1333 | .name = "slv_qup_core_1" , |
1334 | .id = SC8180X_SLAVE_QUP_CORE_1, |
1335 | .channels = 1, |
1336 | .buswidth = 4 |
1337 | }; |
1338 | |
1339 | static struct qcom_icc_node slv_qup_core_2 = { |
1340 | .name = "slv_qup_core_2" , |
1341 | .id = SC8180X_SLAVE_QUP_CORE_2, |
1342 | .channels = 1, |
1343 | .buswidth = 4 |
1344 | }; |
1345 | |
1346 | static struct qcom_icc_bcm bcm_acv = { |
1347 | .name = "ACV" , |
1348 | .enable_mask = BIT(3), |
1349 | .num_nodes = 1, |
1350 | .nodes = { &slv_ebi } |
1351 | }; |
1352 | |
1353 | static struct qcom_icc_bcm bcm_mc0 = { |
1354 | .name = "MC0" , |
1355 | .keepalive = true, |
1356 | .num_nodes = 1, |
1357 | .nodes = { &slv_ebi } |
1358 | }; |
1359 | |
1360 | static struct qcom_icc_bcm bcm_sh0 = { |
1361 | .name = "SH0" , |
1362 | .keepalive = true, |
1363 | .num_nodes = 1, |
1364 | .nodes = { &slv_qns_llcc } |
1365 | }; |
1366 | |
1367 | static struct qcom_icc_bcm bcm_mm0 = { |
1368 | .name = "MM0" , |
1369 | .num_nodes = 1, |
1370 | .nodes = { &slv_qns_mem_noc_hf } |
1371 | }; |
1372 | |
1373 | static struct qcom_icc_bcm bcm_co0 = { |
1374 | .name = "CO0" , |
1375 | .keepalive = true, |
1376 | .num_nodes = 1, |
1377 | .nodes = { &slv_qns_cdsp_mem_noc } |
1378 | }; |
1379 | |
1380 | static struct qcom_icc_bcm bcm_ce0 = { |
1381 | .name = "CE0" , |
1382 | .num_nodes = 1, |
1383 | .nodes = { &mas_qxm_crypto } |
1384 | }; |
1385 | |
1386 | static struct qcom_icc_bcm bcm_cn0 = { |
1387 | .name = "CN0" , |
1388 | .keepalive = true, |
1389 | .num_nodes = 57, |
1390 | .nodes = { &mas_qnm_snoc, |
1391 | &slv_qhs_a1_noc_cfg, |
1392 | &slv_qhs_a2_noc_cfg, |
1393 | &slv_qhs_ahb2phy_refgen_center, |
1394 | &slv_qhs_ahb2phy_refgen_east, |
1395 | &slv_qhs_ahb2phy_refgen_west, |
1396 | &slv_qhs_ahb2phy_south, |
1397 | &slv_qhs_aop, |
1398 | &slv_qhs_aoss, |
1399 | &slv_qhs_camera_cfg, |
1400 | &slv_qhs_clk_ctl, |
1401 | &slv_qhs_compute_dsp, |
1402 | &slv_qhs_cpr_cx, |
1403 | &slv_qhs_cpr_mmcx, |
1404 | &slv_qhs_cpr_mx, |
1405 | &slv_qhs_crypto0_cfg, |
1406 | &slv_qhs_ddrss_cfg, |
1407 | &slv_qhs_display_cfg, |
1408 | &slv_qhs_emac_cfg, |
1409 | &slv_qhs_glm, |
1410 | &slv_qhs_gpuss_cfg, |
1411 | &slv_qhs_imem_cfg, |
1412 | &slv_qhs_ipa, |
1413 | &slv_qhs_mnoc_cfg, |
1414 | &slv_qhs_npu_cfg, |
1415 | &slv_qhs_pcie0_cfg, |
1416 | &slv_qhs_pcie1_cfg, |
1417 | &slv_qhs_pcie2_cfg, |
1418 | &slv_qhs_pcie3_cfg, |
1419 | &slv_qhs_pdm, |
1420 | &slv_qhs_pimem_cfg, |
1421 | &slv_qhs_prng, |
1422 | &slv_qhs_qdss_cfg, |
1423 | &slv_qhs_qspi_0, |
1424 | &slv_qhs_qspi_1, |
1425 | &slv_qhs_qupv3_east0, |
1426 | &slv_qhs_qupv3_east1, |
1427 | &slv_qhs_qupv3_west, |
1428 | &slv_qhs_sdc2, |
1429 | &slv_qhs_sdc4, |
1430 | &slv_qhs_security, |
1431 | &slv_qhs_snoc_cfg, |
1432 | &slv_qhs_spss_cfg, |
1433 | &slv_qhs_tcsr, |
1434 | &slv_qhs_tlmm_east, |
1435 | &slv_qhs_tlmm_south, |
1436 | &slv_qhs_tlmm_west, |
1437 | &slv_qhs_tsif, |
1438 | &slv_qhs_ufs_card_cfg, |
1439 | &slv_qhs_ufs_mem0_cfg, |
1440 | &slv_qhs_ufs_mem1_cfg, |
1441 | &slv_qhs_usb3_0, |
1442 | &slv_qhs_usb3_1, |
1443 | &slv_qhs_usb3_2, |
1444 | &slv_qhs_venus_cfg, |
1445 | &slv_qhs_vsense_ctrl_cfg, |
1446 | &slv_srvc_cnoc } |
1447 | }; |
1448 | |
1449 | static struct qcom_icc_bcm bcm_mm1 = { |
1450 | .name = "MM1" , |
1451 | .num_nodes = 7, |
1452 | .nodes = { &mas_qxm_camnoc_hf0_uncomp, |
1453 | &mas_qxm_camnoc_hf1_uncomp, |
1454 | &mas_qxm_camnoc_sf_uncomp, |
1455 | &mas_qxm_camnoc_hf0, |
1456 | &mas_qxm_camnoc_hf1, |
1457 | &mas_qxm_mdp0, |
1458 | &mas_qxm_mdp1 } |
1459 | }; |
1460 | |
1461 | static struct qcom_icc_bcm bcm_qup0 = { |
1462 | .name = "QUP0" , |
1463 | .num_nodes = 3, |
1464 | .nodes = { &mas_qup_core_0, |
1465 | &mas_qup_core_1, |
1466 | &mas_qup_core_2 } |
1467 | }; |
1468 | |
1469 | static struct qcom_icc_bcm bcm_sh2 = { |
1470 | .name = "SH2" , |
1471 | .num_nodes = 1, |
1472 | .nodes = { &slv_qns_gem_noc_snoc } |
1473 | }; |
1474 | |
1475 | static struct qcom_icc_bcm bcm_mm2 = { |
1476 | .name = "MM2" , |
1477 | .num_nodes = 6, |
1478 | .nodes = { &mas_qxm_camnoc_sf, |
1479 | &mas_qxm_rot, |
1480 | &mas_qxm_venus0, |
1481 | &mas_qxm_venus1, |
1482 | &mas_qxm_venus_arm9, |
1483 | &slv_qns2_mem_noc } |
1484 | }; |
1485 | |
1486 | static struct qcom_icc_bcm bcm_sh3 = { |
1487 | .name = "SH3" , |
1488 | .keepalive = true, |
1489 | .num_nodes = 1, |
1490 | .nodes = { &mas_acm_apps } |
1491 | }; |
1492 | |
1493 | static struct qcom_icc_bcm bcm_sn0 = { |
1494 | .name = "SN0" , |
1495 | .nodes = { &slv_qns_gemnoc_sf } |
1496 | }; |
1497 | |
1498 | static struct qcom_icc_bcm bcm_sn1 = { |
1499 | .name = "SN1" , |
1500 | .nodes = { &slv_qxs_imem } |
1501 | }; |
1502 | |
1503 | static struct qcom_icc_bcm bcm_sn2 = { |
1504 | .name = "SN2" , |
1505 | .keepalive = true, |
1506 | .nodes = { &slv_qns_gemnoc_gc } |
1507 | }; |
1508 | |
1509 | static struct qcom_icc_bcm bcm_co2 = { |
1510 | .name = "CO2" , |
1511 | .nodes = { &mas_qnm_npu } |
1512 | }; |
1513 | |
1514 | static struct qcom_icc_bcm bcm_sn3 = { |
1515 | .name = "SN3" , |
1516 | .keepalive = true, |
1517 | .nodes = { &slv_srvc_aggre1_noc, |
1518 | &slv_qns_cnoc } |
1519 | }; |
1520 | |
1521 | static struct qcom_icc_bcm bcm_sn4 = { |
1522 | .name = "SN4" , |
1523 | .nodes = { &slv_qxs_pimem } |
1524 | }; |
1525 | |
1526 | static struct qcom_icc_bcm bcm_sn8 = { |
1527 | .name = "SN8" , |
1528 | .num_nodes = 4, |
1529 | .nodes = { &slv_xs_pcie_0, |
1530 | &slv_xs_pcie_1, |
1531 | &slv_xs_pcie_2, |
1532 | &slv_xs_pcie_3 } |
1533 | }; |
1534 | |
1535 | static struct qcom_icc_bcm bcm_sn9 = { |
1536 | .name = "SN9" , |
1537 | .num_nodes = 1, |
1538 | .nodes = { &mas_qnm_aggre1_noc } |
1539 | }; |
1540 | |
1541 | static struct qcom_icc_bcm bcm_sn11 = { |
1542 | .name = "SN11" , |
1543 | .num_nodes = 1, |
1544 | .nodes = { &mas_qnm_aggre2_noc } |
1545 | }; |
1546 | |
1547 | static struct qcom_icc_bcm bcm_sn14 = { |
1548 | .name = "SN14" , |
1549 | .num_nodes = 1, |
1550 | .nodes = { &slv_qns_pcie_mem_noc } |
1551 | }; |
1552 | |
1553 | static struct qcom_icc_bcm bcm_sn15 = { |
1554 | .name = "SN15" , |
1555 | .keepalive = true, |
1556 | .num_nodes = 1, |
1557 | .nodes = { &mas_qnm_gemnoc } |
1558 | }; |
1559 | |
1560 | static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { |
1561 | &bcm_sn3, |
1562 | &bcm_ce0, |
1563 | }; |
1564 | |
1565 | static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { |
1566 | &bcm_sn14, |
1567 | &bcm_ce0, |
1568 | }; |
1569 | |
1570 | static struct qcom_icc_bcm * const camnoc_virt_bcms[] = { |
1571 | &bcm_mm1, |
1572 | }; |
1573 | |
1574 | static struct qcom_icc_bcm * const compute_noc_bcms[] = { |
1575 | &bcm_co0, |
1576 | &bcm_co2, |
1577 | }; |
1578 | |
1579 | static struct qcom_icc_bcm * const config_noc_bcms[] = { |
1580 | &bcm_cn0, |
1581 | }; |
1582 | |
1583 | static struct qcom_icc_bcm * const gem_noc_bcms[] = { |
1584 | &bcm_sh0, |
1585 | &bcm_sh2, |
1586 | &bcm_sh3, |
1587 | }; |
1588 | |
1589 | static struct qcom_icc_bcm * const mc_virt_bcms[] = { |
1590 | &bcm_mc0, |
1591 | &bcm_acv, |
1592 | }; |
1593 | |
1594 | static struct qcom_icc_bcm * const mmss_noc_bcms[] = { |
1595 | &bcm_mm0, |
1596 | &bcm_mm1, |
1597 | &bcm_mm2, |
1598 | }; |
1599 | |
1600 | static struct qcom_icc_bcm * const system_noc_bcms[] = { |
1601 | &bcm_sn0, |
1602 | &bcm_sn1, |
1603 | &bcm_sn2, |
1604 | &bcm_sn3, |
1605 | &bcm_sn4, |
1606 | &bcm_sn8, |
1607 | &bcm_sn9, |
1608 | &bcm_sn11, |
1609 | &bcm_sn15, |
1610 | }; |
1611 | |
1612 | static struct qcom_icc_node * const aggre1_noc_nodes[] = { |
1613 | [MASTER_A1NOC_CFG] = &mas_qhm_a1noc_cfg, |
1614 | [MASTER_UFS_CARD] = &mas_xm_ufs_card, |
1615 | [MASTER_UFS_GEN4] = &mas_xm_ufs_g4, |
1616 | [MASTER_UFS_MEM] = &mas_xm_ufs_mem, |
1617 | [MASTER_USB3] = &mas_xm_usb3_0, |
1618 | [MASTER_USB3_1] = &mas_xm_usb3_1, |
1619 | [MASTER_USB3_2] = &mas_xm_usb3_2, |
1620 | [A1NOC_SNOC_SLV] = &slv_qns_a1noc_snoc, |
1621 | [SLAVE_SERVICE_A1NOC] = &slv_srvc_aggre1_noc, |
1622 | }; |
1623 | |
1624 | static struct qcom_icc_node * const aggre2_noc_nodes[] = { |
1625 | [MASTER_A2NOC_CFG] = &mas_qhm_a2noc_cfg, |
1626 | [MASTER_QDSS_BAM] = &mas_qhm_qdss_bam, |
1627 | [MASTER_QSPI_0] = &mas_qhm_qspi, |
1628 | [MASTER_QSPI_1] = &mas_qhm_qspi1, |
1629 | [MASTER_QUP_0] = &mas_qhm_qup0, |
1630 | [MASTER_QUP_1] = &mas_qhm_qup1, |
1631 | [MASTER_QUP_2] = &mas_qhm_qup2, |
1632 | [MASTER_SENSORS_AHB] = &mas_qhm_sensorss_ahb, |
1633 | [MASTER_CRYPTO_CORE_0] = &mas_qxm_crypto, |
1634 | [MASTER_IPA] = &mas_qxm_ipa, |
1635 | [MASTER_EMAC] = &mas_xm_emac, |
1636 | [MASTER_PCIE] = &mas_xm_pcie3_0, |
1637 | [MASTER_PCIE_1] = &mas_xm_pcie3_1, |
1638 | [MASTER_PCIE_2] = &mas_xm_pcie3_2, |
1639 | [MASTER_PCIE_3] = &mas_xm_pcie3_3, |
1640 | [MASTER_QDSS_ETR] = &mas_xm_qdss_etr, |
1641 | [MASTER_SDCC_2] = &mas_xm_sdc2, |
1642 | [MASTER_SDCC_4] = &mas_xm_sdc4, |
1643 | [A2NOC_SNOC_SLV] = &slv_qns_a2noc_snoc, |
1644 | [SLAVE_ANOC_PCIE_GEM_NOC] = &slv_qns_pcie_mem_noc, |
1645 | [SLAVE_SERVICE_A2NOC] = &slv_srvc_aggre2_noc, |
1646 | }; |
1647 | |
1648 | static struct qcom_icc_node * const camnoc_virt_nodes[] = { |
1649 | [MASTER_CAMNOC_HF0_UNCOMP] = &mas_qxm_camnoc_hf0_uncomp, |
1650 | [MASTER_CAMNOC_HF1_UNCOMP] = &mas_qxm_camnoc_hf1_uncomp, |
1651 | [MASTER_CAMNOC_SF_UNCOMP] = &mas_qxm_camnoc_sf_uncomp, |
1652 | [SLAVE_CAMNOC_UNCOMP] = &slv_qns_camnoc_uncomp, |
1653 | }; |
1654 | |
1655 | static struct qcom_icc_node * const compute_noc_nodes[] = { |
1656 | [MASTER_NPU] = &mas_qnm_npu, |
1657 | [SLAVE_CDSP_MEM_NOC] = &slv_qns_cdsp_mem_noc, |
1658 | }; |
1659 | |
1660 | static struct qcom_icc_node * const config_noc_nodes[] = { |
1661 | [SNOC_CNOC_MAS] = &mas_qnm_snoc, |
1662 | [SLAVE_A1NOC_CFG] = &slv_qhs_a1_noc_cfg, |
1663 | [SLAVE_A2NOC_CFG] = &slv_qhs_a2_noc_cfg, |
1664 | [SLAVE_AHB2PHY_CENTER] = &slv_qhs_ahb2phy_refgen_center, |
1665 | [SLAVE_AHB2PHY_EAST] = &slv_qhs_ahb2phy_refgen_east, |
1666 | [SLAVE_AHB2PHY_WEST] = &slv_qhs_ahb2phy_refgen_west, |
1667 | [SLAVE_AHB2PHY_SOUTH] = &slv_qhs_ahb2phy_south, |
1668 | [SLAVE_AOP] = &slv_qhs_aop, |
1669 | [SLAVE_AOSS] = &slv_qhs_aoss, |
1670 | [SLAVE_CAMERA_CFG] = &slv_qhs_camera_cfg, |
1671 | [SLAVE_CLK_CTL] = &slv_qhs_clk_ctl, |
1672 | [SLAVE_CDSP_CFG] = &slv_qhs_compute_dsp, |
1673 | [SLAVE_RBCPR_CX_CFG] = &slv_qhs_cpr_cx, |
1674 | [SLAVE_RBCPR_MMCX_CFG] = &slv_qhs_cpr_mmcx, |
1675 | [SLAVE_RBCPR_MX_CFG] = &slv_qhs_cpr_mx, |
1676 | [SLAVE_CRYPTO_0_CFG] = &slv_qhs_crypto0_cfg, |
1677 | [SLAVE_CNOC_DDRSS] = &slv_qhs_ddrss_cfg, |
1678 | [SLAVE_DISPLAY_CFG] = &slv_qhs_display_cfg, |
1679 | [SLAVE_EMAC_CFG] = &slv_qhs_emac_cfg, |
1680 | [SLAVE_GLM] = &slv_qhs_glm, |
1681 | [SLAVE_GRAPHICS_3D_CFG] = &slv_qhs_gpuss_cfg, |
1682 | [SLAVE_IMEM_CFG] = &slv_qhs_imem_cfg, |
1683 | [SLAVE_IPA_CFG] = &slv_qhs_ipa, |
1684 | [SLAVE_CNOC_MNOC_CFG] = &slv_qhs_mnoc_cfg, |
1685 | [SLAVE_NPU_CFG] = &slv_qhs_npu_cfg, |
1686 | [SLAVE_PCIE_0_CFG] = &slv_qhs_pcie0_cfg, |
1687 | [SLAVE_PCIE_1_CFG] = &slv_qhs_pcie1_cfg, |
1688 | [SLAVE_PCIE_2_CFG] = &slv_qhs_pcie2_cfg, |
1689 | [SLAVE_PCIE_3_CFG] = &slv_qhs_pcie3_cfg, |
1690 | [SLAVE_PDM] = &slv_qhs_pdm, |
1691 | [SLAVE_PIMEM_CFG] = &slv_qhs_pimem_cfg, |
1692 | [SLAVE_PRNG] = &slv_qhs_prng, |
1693 | [SLAVE_QDSS_CFG] = &slv_qhs_qdss_cfg, |
1694 | [SLAVE_QSPI_0] = &slv_qhs_qspi_0, |
1695 | [SLAVE_QSPI_1] = &slv_qhs_qspi_1, |
1696 | [SLAVE_QUP_1] = &slv_qhs_qupv3_east0, |
1697 | [SLAVE_QUP_2] = &slv_qhs_qupv3_east1, |
1698 | [SLAVE_QUP_0] = &slv_qhs_qupv3_west, |
1699 | [SLAVE_SDCC_2] = &slv_qhs_sdc2, |
1700 | [SLAVE_SDCC_4] = &slv_qhs_sdc4, |
1701 | [SLAVE_SECURITY] = &slv_qhs_security, |
1702 | [SLAVE_SNOC_CFG] = &slv_qhs_snoc_cfg, |
1703 | [SLAVE_SPSS_CFG] = &slv_qhs_spss_cfg, |
1704 | [SLAVE_TCSR] = &slv_qhs_tcsr, |
1705 | [SLAVE_TLMM_EAST] = &slv_qhs_tlmm_east, |
1706 | [SLAVE_TLMM_SOUTH] = &slv_qhs_tlmm_south, |
1707 | [SLAVE_TLMM_WEST] = &slv_qhs_tlmm_west, |
1708 | [SLAVE_TSIF] = &slv_qhs_tsif, |
1709 | [SLAVE_UFS_CARD_CFG] = &slv_qhs_ufs_card_cfg, |
1710 | [SLAVE_UFS_MEM_0_CFG] = &slv_qhs_ufs_mem0_cfg, |
1711 | [SLAVE_UFS_MEM_1_CFG] = &slv_qhs_ufs_mem1_cfg, |
1712 | [SLAVE_USB3] = &slv_qhs_usb3_0, |
1713 | [SLAVE_USB3_1] = &slv_qhs_usb3_1, |
1714 | [SLAVE_USB3_2] = &slv_qhs_usb3_2, |
1715 | [SLAVE_VENUS_CFG] = &slv_qhs_venus_cfg, |
1716 | [SLAVE_VSENSE_CTRL_CFG] = &slv_qhs_vsense_ctrl_cfg, |
1717 | [SLAVE_SERVICE_CNOC] = &slv_srvc_cnoc, |
1718 | }; |
1719 | |
1720 | static struct qcom_icc_node * const dc_noc_nodes[] = { |
1721 | [MASTER_CNOC_DC_NOC] = &mas_qhm_cnoc_dc_noc, |
1722 | [SLAVE_GEM_NOC_CFG] = &slv_qhs_gemnoc, |
1723 | [SLAVE_LLCC_CFG] = &slv_qhs_llcc, |
1724 | }; |
1725 | |
1726 | static struct qcom_icc_node * const gem_noc_nodes[] = { |
1727 | [MASTER_AMPSS_M0] = &mas_acm_apps, |
1728 | [MASTER_GPU_TCU] = &mas_acm_gpu_tcu, |
1729 | [MASTER_SYS_TCU] = &mas_acm_sys_tcu, |
1730 | [MASTER_GEM_NOC_CFG] = &mas_qhm_gemnoc_cfg, |
1731 | [MASTER_COMPUTE_NOC] = &mas_qnm_cmpnoc, |
1732 | [MASTER_GRAPHICS_3D] = &mas_qnm_gpu, |
1733 | [MASTER_MNOC_HF_MEM_NOC] = &mas_qnm_mnoc_hf, |
1734 | [MASTER_MNOC_SF_MEM_NOC] = &mas_qnm_mnoc_sf, |
1735 | [MASTER_GEM_NOC_PCIE_SNOC] = &mas_qnm_pcie, |
1736 | [MASTER_SNOC_GC_MEM_NOC] = &mas_qnm_snoc_gc, |
1737 | [MASTER_SNOC_SF_MEM_NOC] = &mas_qnm_snoc_sf, |
1738 | [MASTER_ECC] = &mas_qxm_ecc, |
1739 | [SLAVE_MSS_PROC_MS_MPU_CFG] = &slv_qhs_mdsp_ms_mpu_cfg, |
1740 | [SLAVE_ECC] = &slv_qns_ecc, |
1741 | [SLAVE_GEM_NOC_SNOC] = &slv_qns_gem_noc_snoc, |
1742 | [SLAVE_LLCC] = &slv_qns_llcc, |
1743 | [SLAVE_SERVICE_GEM_NOC] = &slv_srvc_gemnoc, |
1744 | [SLAVE_SERVICE_GEM_NOC_1] = &slv_srvc_gemnoc1, |
1745 | }; |
1746 | |
1747 | static struct qcom_icc_node * const mc_virt_nodes[] = { |
1748 | [MASTER_LLCC] = &mas_llcc_mc, |
1749 | [SLAVE_EBI_CH0] = &slv_ebi, |
1750 | }; |
1751 | |
1752 | static struct qcom_icc_node * const mmss_noc_nodes[] = { |
1753 | [MASTER_CNOC_MNOC_CFG] = &mas_qhm_mnoc_cfg, |
1754 | [MASTER_CAMNOC_HF0] = &mas_qxm_camnoc_hf0, |
1755 | [MASTER_CAMNOC_HF1] = &mas_qxm_camnoc_hf1, |
1756 | [MASTER_CAMNOC_SF] = &mas_qxm_camnoc_sf, |
1757 | [MASTER_MDP_PORT0] = &mas_qxm_mdp0, |
1758 | [MASTER_MDP_PORT1] = &mas_qxm_mdp1, |
1759 | [MASTER_ROTATOR] = &mas_qxm_rot, |
1760 | [MASTER_VIDEO_P0] = &mas_qxm_venus0, |
1761 | [MASTER_VIDEO_P1] = &mas_qxm_venus1, |
1762 | [MASTER_VIDEO_PROC] = &mas_qxm_venus_arm9, |
1763 | [SLAVE_MNOC_SF_MEM_NOC] = &slv_qns2_mem_noc, |
1764 | [SLAVE_MNOC_HF_MEM_NOC] = &slv_qns_mem_noc_hf, |
1765 | [SLAVE_SERVICE_MNOC] = &slv_srvc_mnoc, |
1766 | }; |
1767 | |
1768 | static struct qcom_icc_node * const system_noc_nodes[] = { |
1769 | [MASTER_SNOC_CFG] = &mas_qhm_snoc_cfg, |
1770 | [A1NOC_SNOC_MAS] = &mas_qnm_aggre1_noc, |
1771 | [A2NOC_SNOC_MAS] = &mas_qnm_aggre2_noc, |
1772 | [MASTER_GEM_NOC_SNOC] = &mas_qnm_gemnoc, |
1773 | [MASTER_PIMEM] = &mas_qxm_pimem, |
1774 | [MASTER_GIC] = &mas_xm_gic, |
1775 | [SLAVE_APPSS] = &slv_qhs_apss, |
1776 | [SNOC_CNOC_SLV] = &slv_qns_cnoc, |
1777 | [SLAVE_SNOC_GEM_NOC_GC] = &slv_qns_gemnoc_gc, |
1778 | [SLAVE_SNOC_GEM_NOC_SF] = &slv_qns_gemnoc_sf, |
1779 | [SLAVE_OCIMEM] = &slv_qxs_imem, |
1780 | [SLAVE_PIMEM] = &slv_qxs_pimem, |
1781 | [SLAVE_SERVICE_SNOC] = &slv_srvc_snoc, |
1782 | [SLAVE_QDSS_STM] = &slv_xs_qdss_stm, |
1783 | [SLAVE_TCU] = &slv_xs_sys_tcu_cfg, |
1784 | }; |
1785 | |
1786 | static const struct qcom_icc_desc sc8180x_aggre1_noc = { |
1787 | .nodes = aggre1_noc_nodes, |
1788 | .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), |
1789 | .bcms = aggre1_noc_bcms, |
1790 | .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), |
1791 | }; |
1792 | |
1793 | static const struct qcom_icc_desc sc8180x_aggre2_noc = { |
1794 | .nodes = aggre2_noc_nodes, |
1795 | .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), |
1796 | .bcms = aggre2_noc_bcms, |
1797 | .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), |
1798 | }; |
1799 | |
1800 | static const struct qcom_icc_desc sc8180x_camnoc_virt = { |
1801 | .nodes = camnoc_virt_nodes, |
1802 | .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), |
1803 | .bcms = camnoc_virt_bcms, |
1804 | .num_bcms = ARRAY_SIZE(camnoc_virt_bcms), |
1805 | }; |
1806 | |
1807 | static const struct qcom_icc_desc sc8180x_compute_noc = { |
1808 | .nodes = compute_noc_nodes, |
1809 | .num_nodes = ARRAY_SIZE(compute_noc_nodes), |
1810 | .bcms = compute_noc_bcms, |
1811 | .num_bcms = ARRAY_SIZE(compute_noc_bcms), |
1812 | }; |
1813 | |
1814 | static const struct qcom_icc_desc sc8180x_config_noc = { |
1815 | .nodes = config_noc_nodes, |
1816 | .num_nodes = ARRAY_SIZE(config_noc_nodes), |
1817 | .bcms = config_noc_bcms, |
1818 | .num_bcms = ARRAY_SIZE(config_noc_bcms), |
1819 | }; |
1820 | |
1821 | static const struct qcom_icc_desc sc8180x_dc_noc = { |
1822 | .nodes = dc_noc_nodes, |
1823 | .num_nodes = ARRAY_SIZE(dc_noc_nodes), |
1824 | }; |
1825 | |
1826 | static const struct qcom_icc_desc sc8180x_gem_noc = { |
1827 | .nodes = gem_noc_nodes, |
1828 | .num_nodes = ARRAY_SIZE(gem_noc_nodes), |
1829 | .bcms = gem_noc_bcms, |
1830 | .num_bcms = ARRAY_SIZE(gem_noc_bcms), |
1831 | }; |
1832 | |
1833 | static const struct qcom_icc_desc sc8180x_mc_virt = { |
1834 | .nodes = mc_virt_nodes, |
1835 | .num_nodes = ARRAY_SIZE(mc_virt_nodes), |
1836 | .bcms = mc_virt_bcms, |
1837 | .num_bcms = ARRAY_SIZE(mc_virt_bcms), |
1838 | }; |
1839 | |
1840 | static const struct qcom_icc_desc sc8180x_mmss_noc = { |
1841 | .nodes = mmss_noc_nodes, |
1842 | .num_nodes = ARRAY_SIZE(mmss_noc_nodes), |
1843 | .bcms = mmss_noc_bcms, |
1844 | .num_bcms = ARRAY_SIZE(mmss_noc_bcms), |
1845 | }; |
1846 | |
1847 | static const struct qcom_icc_desc sc8180x_system_noc = { |
1848 | .nodes = system_noc_nodes, |
1849 | .num_nodes = ARRAY_SIZE(system_noc_nodes), |
1850 | .bcms = system_noc_bcms, |
1851 | .num_bcms = ARRAY_SIZE(system_noc_bcms), |
1852 | }; |
1853 | |
1854 | static struct qcom_icc_bcm * const qup_virt_bcms[] = { |
1855 | &bcm_qup0, |
1856 | }; |
1857 | |
1858 | static struct qcom_icc_node * const qup_virt_nodes[] = { |
1859 | [MASTER_QUP_CORE_0] = &mas_qup_core_0, |
1860 | [MASTER_QUP_CORE_1] = &mas_qup_core_1, |
1861 | [MASTER_QUP_CORE_2] = &mas_qup_core_2, |
1862 | [SLAVE_QUP_CORE_0] = &slv_qup_core_0, |
1863 | [SLAVE_QUP_CORE_1] = &slv_qup_core_1, |
1864 | [SLAVE_QUP_CORE_2] = &slv_qup_core_2, |
1865 | }; |
1866 | |
1867 | static const struct qcom_icc_desc sc8180x_qup_virt = { |
1868 | .nodes = qup_virt_nodes, |
1869 | .num_nodes = ARRAY_SIZE(qup_virt_nodes), |
1870 | .bcms = qup_virt_bcms, |
1871 | .num_bcms = ARRAY_SIZE(qup_virt_bcms), |
1872 | }; |
1873 | |
1874 | static const struct of_device_id qnoc_of_match[] = { |
1875 | { .compatible = "qcom,sc8180x-aggre1-noc" , .data = &sc8180x_aggre1_noc }, |
1876 | { .compatible = "qcom,sc8180x-aggre2-noc" , .data = &sc8180x_aggre2_noc }, |
1877 | { .compatible = "qcom,sc8180x-camnoc-virt" , .data = &sc8180x_camnoc_virt }, |
1878 | { .compatible = "qcom,sc8180x-compute-noc" , .data = &sc8180x_compute_noc, }, |
1879 | { .compatible = "qcom,sc8180x-config-noc" , .data = &sc8180x_config_noc }, |
1880 | { .compatible = "qcom,sc8180x-dc-noc" , .data = &sc8180x_dc_noc }, |
1881 | { .compatible = "qcom,sc8180x-gem-noc" , .data = &sc8180x_gem_noc }, |
1882 | { .compatible = "qcom,sc8180x-mc-virt" , .data = &sc8180x_mc_virt }, |
1883 | { .compatible = "qcom,sc8180x-mmss-noc" , .data = &sc8180x_mmss_noc }, |
1884 | { .compatible = "qcom,sc8180x-qup-virt" , .data = &sc8180x_qup_virt }, |
1885 | { .compatible = "qcom,sc8180x-system-noc" , .data = &sc8180x_system_noc }, |
1886 | { } |
1887 | }; |
1888 | MODULE_DEVICE_TABLE(of, qnoc_of_match); |
1889 | |
1890 | static struct platform_driver qnoc_driver = { |
1891 | .probe = qcom_icc_rpmh_probe, |
1892 | .remove_new = qcom_icc_rpmh_remove, |
1893 | .driver = { |
1894 | .name = "qnoc-sc8180x" , |
1895 | .of_match_table = qnoc_of_match, |
1896 | .sync_state = icc_sync_state, |
1897 | }, |
1898 | }; |
1899 | module_platform_driver(qnoc_driver); |
1900 | |
1901 | MODULE_DESCRIPTION("Qualcomm sc8180x NoC driver" ); |
1902 | MODULE_LICENSE("GPL v2" ); |
1903 | |