1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. |
4 | */ |
5 | |
6 | #include <linux/device.h> |
7 | #include <linux/interconnect.h> |
8 | #include <linux/interconnect-provider.h> |
9 | #include <linux/mod_devicetable.h> |
10 | #include <linux/module.h> |
11 | #include <linux/platform_device.h> |
12 | #include <dt-bindings/interconnect/qcom,sdx65.h> |
13 | |
14 | #include "bcm-voter.h" |
15 | #include "icc-rpmh.h" |
16 | #include "sdx65.h" |
17 | |
18 | static struct qcom_icc_node llcc_mc = { |
19 | .name = "llcc_mc" , |
20 | .id = SDX65_MASTER_LLCC, |
21 | .channels = 1, |
22 | .buswidth = 4, |
23 | .num_links = 1, |
24 | .links = { SDX65_SLAVE_EBI1 }, |
25 | }; |
26 | |
27 | static struct qcom_icc_node acm_tcu = { |
28 | .name = "acm_tcu" , |
29 | .id = SDX65_MASTER_TCU_0, |
30 | .channels = 1, |
31 | .buswidth = 8, |
32 | .num_links = 3, |
33 | .links = { SDX65_SLAVE_LLCC, |
34 | SDX65_SLAVE_MEM_NOC_SNOC, |
35 | SDX65_SLAVE_MEM_NOC_PCIE_SNOC |
36 | }, |
37 | }; |
38 | |
39 | static struct qcom_icc_node qnm_snoc_gc = { |
40 | .name = "qnm_snoc_gc" , |
41 | .id = SDX65_MASTER_SNOC_GC_MEM_NOC, |
42 | .channels = 1, |
43 | .buswidth = 16, |
44 | .num_links = 1, |
45 | .links = { SDX65_SLAVE_LLCC }, |
46 | }; |
47 | |
48 | static struct qcom_icc_node xm_apps_rdwr = { |
49 | .name = "xm_apps_rdwr" , |
50 | .id = SDX65_MASTER_APPSS_PROC, |
51 | .channels = 1, |
52 | .buswidth = 16, |
53 | .num_links = 3, |
54 | .links = { SDX65_SLAVE_LLCC, |
55 | SDX65_SLAVE_MEM_NOC_SNOC, |
56 | SDX65_SLAVE_MEM_NOC_PCIE_SNOC |
57 | }, |
58 | }; |
59 | |
60 | static struct qcom_icc_node qhm_audio = { |
61 | .name = "qhm_audio" , |
62 | .id = SDX65_MASTER_AUDIO, |
63 | .channels = 1, |
64 | .buswidth = 4, |
65 | .num_links = 1, |
66 | .links = { SDX65_SLAVE_ANOC_SNOC }, |
67 | }; |
68 | |
69 | static struct qcom_icc_node qhm_blsp1 = { |
70 | .name = "qhm_blsp1" , |
71 | .id = SDX65_MASTER_BLSP_1, |
72 | .channels = 1, |
73 | .buswidth = 4, |
74 | .num_links = 1, |
75 | .links = { SDX65_SLAVE_ANOC_SNOC }, |
76 | }; |
77 | |
78 | static struct qcom_icc_node qhm_qdss_bam = { |
79 | .name = "qhm_qdss_bam" , |
80 | .id = SDX65_MASTER_QDSS_BAM, |
81 | .channels = 1, |
82 | .buswidth = 4, |
83 | .num_links = 26, |
84 | .links = { SDX65_SLAVE_AOSS, |
85 | SDX65_SLAVE_AUDIO, |
86 | SDX65_SLAVE_BLSP_1, |
87 | SDX65_SLAVE_CLK_CTL, |
88 | SDX65_SLAVE_CRYPTO_0_CFG, |
89 | SDX65_SLAVE_CNOC_DDRSS, |
90 | SDX65_SLAVE_ECC_CFG, |
91 | SDX65_SLAVE_IMEM_CFG, |
92 | SDX65_SLAVE_IPA_CFG, |
93 | SDX65_SLAVE_CNOC_MSS, |
94 | SDX65_SLAVE_PCIE_PARF, |
95 | SDX65_SLAVE_PDM, |
96 | SDX65_SLAVE_PRNG, |
97 | SDX65_SLAVE_QDSS_CFG, |
98 | SDX65_SLAVE_QPIC, |
99 | SDX65_SLAVE_SDCC_1, |
100 | SDX65_SLAVE_SNOC_CFG, |
101 | SDX65_SLAVE_SPMI_FETCHER, |
102 | SDX65_SLAVE_SPMI_VGI_COEX, |
103 | SDX65_SLAVE_TCSR, |
104 | SDX65_SLAVE_TLMM, |
105 | SDX65_SLAVE_USB3, |
106 | SDX65_SLAVE_USB3_PHY_CFG, |
107 | SDX65_SLAVE_SNOC_MEM_NOC_GC, |
108 | SDX65_SLAVE_IMEM, |
109 | SDX65_SLAVE_TCU |
110 | }, |
111 | }; |
112 | |
113 | static struct qcom_icc_node qhm_qpic = { |
114 | .name = "qhm_qpic" , |
115 | .id = SDX65_MASTER_QPIC, |
116 | .channels = 1, |
117 | .buswidth = 4, |
118 | .num_links = 4, |
119 | .links = { SDX65_SLAVE_AOSS, |
120 | SDX65_SLAVE_AUDIO, |
121 | SDX65_SLAVE_IPA_CFG, |
122 | SDX65_SLAVE_ANOC_SNOC |
123 | }, |
124 | }; |
125 | |
126 | static struct qcom_icc_node qhm_snoc_cfg = { |
127 | .name = "qhm_snoc_cfg" , |
128 | .id = SDX65_MASTER_SNOC_CFG, |
129 | .channels = 1, |
130 | .buswidth = 4, |
131 | .num_links = 1, |
132 | .links = { SDX65_SLAVE_SERVICE_SNOC }, |
133 | }; |
134 | |
135 | static struct qcom_icc_node qhm_spmi_fetcher1 = { |
136 | .name = "qhm_spmi_fetcher1" , |
137 | .id = SDX65_MASTER_SPMI_FETCHER, |
138 | .channels = 1, |
139 | .buswidth = 4, |
140 | .num_links = 2, |
141 | .links = { SDX65_SLAVE_AOSS, |
142 | SDX65_SLAVE_ANOC_SNOC |
143 | }, |
144 | }; |
145 | |
146 | static struct qcom_icc_node qnm_aggre_noc = { |
147 | .name = "qnm_aggre_noc" , |
148 | .id = SDX65_MASTER_ANOC_SNOC, |
149 | .channels = 1, |
150 | .buswidth = 8, |
151 | .num_links = 29, |
152 | .links = { SDX65_SLAVE_AOSS, |
153 | SDX65_SLAVE_APPSS, |
154 | SDX65_SLAVE_AUDIO, |
155 | SDX65_SLAVE_BLSP_1, |
156 | SDX65_SLAVE_CLK_CTL, |
157 | SDX65_SLAVE_CRYPTO_0_CFG, |
158 | SDX65_SLAVE_CNOC_DDRSS, |
159 | SDX65_SLAVE_ECC_CFG, |
160 | SDX65_SLAVE_IMEM_CFG, |
161 | SDX65_SLAVE_IPA_CFG, |
162 | SDX65_SLAVE_CNOC_MSS, |
163 | SDX65_SLAVE_PCIE_PARF, |
164 | SDX65_SLAVE_PDM, |
165 | SDX65_SLAVE_PRNG, |
166 | SDX65_SLAVE_QDSS_CFG, |
167 | SDX65_SLAVE_QPIC, |
168 | SDX65_SLAVE_SDCC_1, |
169 | SDX65_SLAVE_SNOC_CFG, |
170 | SDX65_SLAVE_SPMI_FETCHER, |
171 | SDX65_SLAVE_SPMI_VGI_COEX, |
172 | SDX65_SLAVE_TCSR, |
173 | SDX65_SLAVE_TLMM, |
174 | SDX65_SLAVE_USB3, |
175 | SDX65_SLAVE_USB3_PHY_CFG, |
176 | SDX65_SLAVE_SNOC_MEM_NOC_GC, |
177 | SDX65_SLAVE_IMEM, |
178 | SDX65_SLAVE_PCIE_0, |
179 | SDX65_SLAVE_QDSS_STM, |
180 | SDX65_SLAVE_TCU |
181 | }, |
182 | }; |
183 | |
184 | static struct qcom_icc_node qnm_ipa = { |
185 | .name = "qnm_ipa" , |
186 | .id = SDX65_MASTER_IPA, |
187 | .channels = 1, |
188 | .buswidth = 8, |
189 | .num_links = 26, |
190 | .links = { SDX65_SLAVE_AOSS, |
191 | SDX65_SLAVE_AUDIO, |
192 | SDX65_SLAVE_BLSP_1, |
193 | SDX65_SLAVE_CLK_CTL, |
194 | SDX65_SLAVE_CRYPTO_0_CFG, |
195 | SDX65_SLAVE_CNOC_DDRSS, |
196 | SDX65_SLAVE_ECC_CFG, |
197 | SDX65_SLAVE_IMEM_CFG, |
198 | SDX65_SLAVE_IPA_CFG, |
199 | SDX65_SLAVE_CNOC_MSS, |
200 | SDX65_SLAVE_PCIE_PARF, |
201 | SDX65_SLAVE_PDM, |
202 | SDX65_SLAVE_PRNG, |
203 | SDX65_SLAVE_QDSS_CFG, |
204 | SDX65_SLAVE_QPIC, |
205 | SDX65_SLAVE_SDCC_1, |
206 | SDX65_SLAVE_SNOC_CFG, |
207 | SDX65_SLAVE_SPMI_FETCHER, |
208 | SDX65_SLAVE_TCSR, |
209 | SDX65_SLAVE_TLMM, |
210 | SDX65_SLAVE_USB3, |
211 | SDX65_SLAVE_USB3_PHY_CFG, |
212 | SDX65_SLAVE_SNOC_MEM_NOC_GC, |
213 | SDX65_SLAVE_IMEM, |
214 | SDX65_SLAVE_PCIE_0, |
215 | SDX65_SLAVE_QDSS_STM |
216 | }, |
217 | }; |
218 | |
219 | static struct qcom_icc_node qnm_memnoc = { |
220 | .name = "qnm_memnoc" , |
221 | .id = SDX65_MASTER_MEM_NOC_SNOC, |
222 | .channels = 1, |
223 | .buswidth = 8, |
224 | .num_links = 27, |
225 | .links = { SDX65_SLAVE_AOSS, |
226 | SDX65_SLAVE_APPSS, |
227 | SDX65_SLAVE_AUDIO, |
228 | SDX65_SLAVE_BLSP_1, |
229 | SDX65_SLAVE_CLK_CTL, |
230 | SDX65_SLAVE_CRYPTO_0_CFG, |
231 | SDX65_SLAVE_CNOC_DDRSS, |
232 | SDX65_SLAVE_ECC_CFG, |
233 | SDX65_SLAVE_IMEM_CFG, |
234 | SDX65_SLAVE_IPA_CFG, |
235 | SDX65_SLAVE_CNOC_MSS, |
236 | SDX65_SLAVE_PCIE_PARF, |
237 | SDX65_SLAVE_PDM, |
238 | SDX65_SLAVE_PRNG, |
239 | SDX65_SLAVE_QDSS_CFG, |
240 | SDX65_SLAVE_QPIC, |
241 | SDX65_SLAVE_SDCC_1, |
242 | SDX65_SLAVE_SNOC_CFG, |
243 | SDX65_SLAVE_SPMI_FETCHER, |
244 | SDX65_SLAVE_SPMI_VGI_COEX, |
245 | SDX65_SLAVE_TCSR, |
246 | SDX65_SLAVE_TLMM, |
247 | SDX65_SLAVE_USB3, |
248 | SDX65_SLAVE_USB3_PHY_CFG, |
249 | SDX65_SLAVE_IMEM, |
250 | SDX65_SLAVE_QDSS_STM, |
251 | SDX65_SLAVE_TCU |
252 | }, |
253 | }; |
254 | |
255 | static struct qcom_icc_node qnm_memnoc_pcie = { |
256 | .name = "qnm_memnoc_pcie" , |
257 | .id = SDX65_MASTER_MEM_NOC_PCIE_SNOC, |
258 | .channels = 1, |
259 | .buswidth = 8, |
260 | .num_links = 1, |
261 | .links = { SDX65_SLAVE_PCIE_0 }, |
262 | }; |
263 | |
264 | static struct qcom_icc_node qxm_crypto = { |
265 | .name = "qxm_crypto" , |
266 | .id = SDX65_MASTER_CRYPTO, |
267 | .channels = 1, |
268 | .buswidth = 8, |
269 | .num_links = 2, |
270 | .links = { SDX65_SLAVE_AOSS, |
271 | SDX65_SLAVE_ANOC_SNOC |
272 | }, |
273 | }; |
274 | |
275 | static struct qcom_icc_node xm_ipa2pcie_slv = { |
276 | .name = "xm_ipa2pcie_slv" , |
277 | .id = SDX65_MASTER_IPA_PCIE, |
278 | .channels = 1, |
279 | .buswidth = 8, |
280 | .num_links = 1, |
281 | .links = { SDX65_SLAVE_PCIE_0 }, |
282 | }; |
283 | |
284 | static struct qcom_icc_node xm_pcie = { |
285 | .name = "xm_pcie" , |
286 | .id = SDX65_MASTER_PCIE_0, |
287 | .channels = 1, |
288 | .buswidth = 8, |
289 | .num_links = 1, |
290 | .links = { SDX65_SLAVE_ANOC_SNOC }, |
291 | }; |
292 | |
293 | static struct qcom_icc_node xm_qdss_etr = { |
294 | .name = "xm_qdss_etr" , |
295 | .id = SDX65_MASTER_QDSS_ETR, |
296 | .channels = 1, |
297 | .buswidth = 8, |
298 | .num_links = 26, |
299 | .links = { SDX65_SLAVE_AOSS, |
300 | SDX65_SLAVE_AUDIO, |
301 | SDX65_SLAVE_BLSP_1, |
302 | SDX65_SLAVE_CLK_CTL, |
303 | SDX65_SLAVE_CRYPTO_0_CFG, |
304 | SDX65_SLAVE_CNOC_DDRSS, |
305 | SDX65_SLAVE_ECC_CFG, |
306 | SDX65_SLAVE_IMEM_CFG, |
307 | SDX65_SLAVE_IPA_CFG, |
308 | SDX65_SLAVE_CNOC_MSS, |
309 | SDX65_SLAVE_PCIE_PARF, |
310 | SDX65_SLAVE_PDM, |
311 | SDX65_SLAVE_PRNG, |
312 | SDX65_SLAVE_QDSS_CFG, |
313 | SDX65_SLAVE_QPIC, |
314 | SDX65_SLAVE_SDCC_1, |
315 | SDX65_SLAVE_SNOC_CFG, |
316 | SDX65_SLAVE_SPMI_FETCHER, |
317 | SDX65_SLAVE_SPMI_VGI_COEX, |
318 | SDX65_SLAVE_TCSR, |
319 | SDX65_SLAVE_TLMM, |
320 | SDX65_SLAVE_USB3, |
321 | SDX65_SLAVE_USB3_PHY_CFG, |
322 | SDX65_SLAVE_SNOC_MEM_NOC_GC, |
323 | SDX65_SLAVE_IMEM, |
324 | SDX65_SLAVE_TCU |
325 | }, |
326 | }; |
327 | |
328 | static struct qcom_icc_node xm_sdc1 = { |
329 | .name = "xm_sdc1" , |
330 | .id = SDX65_MASTER_SDCC_1, |
331 | .channels = 1, |
332 | .buswidth = 8, |
333 | .num_links = 4, |
334 | .links = { SDX65_SLAVE_AOSS, |
335 | SDX65_SLAVE_AUDIO, |
336 | SDX65_SLAVE_IPA_CFG, |
337 | SDX65_SLAVE_ANOC_SNOC |
338 | }, |
339 | }; |
340 | |
341 | static struct qcom_icc_node xm_usb3 = { |
342 | .name = "xm_usb3" , |
343 | .id = SDX65_MASTER_USB3, |
344 | .channels = 1, |
345 | .buswidth = 8, |
346 | .num_links = 1, |
347 | .links = { SDX65_SLAVE_ANOC_SNOC }, |
348 | }; |
349 | |
350 | static struct qcom_icc_node ebi = { |
351 | .name = "ebi" , |
352 | .id = SDX65_SLAVE_EBI1, |
353 | .channels = 1, |
354 | .buswidth = 4, |
355 | }; |
356 | |
357 | static struct qcom_icc_node qns_llcc = { |
358 | .name = "qns_llcc" , |
359 | .id = SDX65_SLAVE_LLCC, |
360 | .channels = 1, |
361 | .buswidth = 16, |
362 | .num_links = 1, |
363 | .links = { SDX65_MASTER_LLCC }, |
364 | }; |
365 | |
366 | static struct qcom_icc_node qns_memnoc_snoc = { |
367 | .name = "qns_memnoc_snoc" , |
368 | .id = SDX65_SLAVE_MEM_NOC_SNOC, |
369 | .channels = 1, |
370 | .buswidth = 8, |
371 | .num_links = 1, |
372 | .links = { SDX65_MASTER_MEM_NOC_SNOC }, |
373 | }; |
374 | |
375 | static struct qcom_icc_node qns_sys_pcie = { |
376 | .name = "qns_sys_pcie" , |
377 | .id = SDX65_SLAVE_MEM_NOC_PCIE_SNOC, |
378 | .channels = 1, |
379 | .buswidth = 8, |
380 | .num_links = 1, |
381 | .links = { SDX65_MASTER_MEM_NOC_PCIE_SNOC }, |
382 | }; |
383 | |
384 | static struct qcom_icc_node qhs_aoss = { |
385 | .name = "qhs_aoss" , |
386 | .id = SDX65_SLAVE_AOSS, |
387 | .channels = 1, |
388 | .buswidth = 4, |
389 | }; |
390 | |
391 | static struct qcom_icc_node qhs_apss = { |
392 | .name = "qhs_apss" , |
393 | .id = SDX65_SLAVE_APPSS, |
394 | .channels = 1, |
395 | .buswidth = 4, |
396 | }; |
397 | |
398 | static struct qcom_icc_node qhs_audio = { |
399 | .name = "qhs_audio" , |
400 | .id = SDX65_SLAVE_AUDIO, |
401 | .channels = 1, |
402 | .buswidth = 4, |
403 | }; |
404 | |
405 | static struct qcom_icc_node qhs_blsp1 = { |
406 | .name = "qhs_blsp1" , |
407 | .id = SDX65_SLAVE_BLSP_1, |
408 | .channels = 1, |
409 | .buswidth = 4, |
410 | }; |
411 | |
412 | static struct qcom_icc_node qhs_clk_ctl = { |
413 | .name = "qhs_clk_ctl" , |
414 | .id = SDX65_SLAVE_CLK_CTL, |
415 | .channels = 1, |
416 | .buswidth = 4, |
417 | }; |
418 | |
419 | static struct qcom_icc_node qhs_crypto0_cfg = { |
420 | .name = "qhs_crypto0_cfg" , |
421 | .id = SDX65_SLAVE_CRYPTO_0_CFG, |
422 | .channels = 1, |
423 | .buswidth = 4, |
424 | }; |
425 | |
426 | static struct qcom_icc_node = { |
427 | .name = "qhs_ddrss_cfg" , |
428 | .id = SDX65_SLAVE_CNOC_DDRSS, |
429 | .channels = 1, |
430 | .buswidth = 4, |
431 | }; |
432 | |
433 | static struct qcom_icc_node qhs_ecc_cfg = { |
434 | .name = "qhs_ecc_cfg" , |
435 | .id = SDX65_SLAVE_ECC_CFG, |
436 | .channels = 1, |
437 | .buswidth = 4, |
438 | }; |
439 | |
440 | static struct qcom_icc_node qhs_imem_cfg = { |
441 | .name = "qhs_imem_cfg" , |
442 | .id = SDX65_SLAVE_IMEM_CFG, |
443 | .channels = 1, |
444 | .buswidth = 4, |
445 | }; |
446 | |
447 | static struct qcom_icc_node qhs_ipa = { |
448 | .name = "qhs_ipa" , |
449 | .id = SDX65_SLAVE_IPA_CFG, |
450 | .channels = 1, |
451 | .buswidth = 4, |
452 | }; |
453 | |
454 | static struct qcom_icc_node qhs_mss_cfg = { |
455 | .name = "qhs_mss_cfg" , |
456 | .id = SDX65_SLAVE_CNOC_MSS, |
457 | .channels = 1, |
458 | .buswidth = 4, |
459 | }; |
460 | |
461 | static struct qcom_icc_node qhs_pcie_parf = { |
462 | .name = "qhs_pcie_parf" , |
463 | .id = SDX65_SLAVE_PCIE_PARF, |
464 | .channels = 1, |
465 | .buswidth = 4, |
466 | }; |
467 | |
468 | static struct qcom_icc_node qhs_pdm = { |
469 | .name = "qhs_pdm" , |
470 | .id = SDX65_SLAVE_PDM, |
471 | .channels = 1, |
472 | .buswidth = 4, |
473 | }; |
474 | |
475 | static struct qcom_icc_node qhs_prng = { |
476 | .name = "qhs_prng" , |
477 | .id = SDX65_SLAVE_PRNG, |
478 | .channels = 1, |
479 | .buswidth = 4, |
480 | }; |
481 | |
482 | static struct qcom_icc_node qhs_qdss_cfg = { |
483 | .name = "qhs_qdss_cfg" , |
484 | .id = SDX65_SLAVE_QDSS_CFG, |
485 | .channels = 1, |
486 | .buswidth = 4, |
487 | }; |
488 | |
489 | static struct qcom_icc_node qhs_qpic = { |
490 | .name = "qhs_qpic" , |
491 | .id = SDX65_SLAVE_QPIC, |
492 | .channels = 1, |
493 | .buswidth = 4, |
494 | }; |
495 | |
496 | static struct qcom_icc_node qhs_sdc1 = { |
497 | .name = "qhs_sdc1" , |
498 | .id = SDX65_SLAVE_SDCC_1, |
499 | .channels = 1, |
500 | .buswidth = 4, |
501 | }; |
502 | |
503 | static struct qcom_icc_node qhs_snoc_cfg = { |
504 | .name = "qhs_snoc_cfg" , |
505 | .id = SDX65_SLAVE_SNOC_CFG, |
506 | .channels = 1, |
507 | .buswidth = 4, |
508 | .num_links = 1, |
509 | .links = { SDX65_MASTER_SNOC_CFG }, |
510 | }; |
511 | |
512 | static struct qcom_icc_node qhs_spmi_fetcher = { |
513 | .name = "qhs_spmi_fetcher" , |
514 | .id = SDX65_SLAVE_SPMI_FETCHER, |
515 | .channels = 1, |
516 | .buswidth = 4, |
517 | }; |
518 | |
519 | static struct qcom_icc_node qhs_spmi_vgi_coex = { |
520 | .name = "qhs_spmi_vgi_coex" , |
521 | .id = SDX65_SLAVE_SPMI_VGI_COEX, |
522 | .channels = 1, |
523 | .buswidth = 4, |
524 | }; |
525 | |
526 | static struct qcom_icc_node qhs_tcsr = { |
527 | .name = "qhs_tcsr" , |
528 | .id = SDX65_SLAVE_TCSR, |
529 | .channels = 1, |
530 | .buswidth = 4, |
531 | }; |
532 | |
533 | static struct qcom_icc_node qhs_tlmm = { |
534 | .name = "qhs_tlmm" , |
535 | .id = SDX65_SLAVE_TLMM, |
536 | .channels = 1, |
537 | .buswidth = 4, |
538 | }; |
539 | |
540 | static struct qcom_icc_node qhs_usb3 = { |
541 | .name = "qhs_usb3" , |
542 | .id = SDX65_SLAVE_USB3, |
543 | .channels = 1, |
544 | .buswidth = 4, |
545 | }; |
546 | |
547 | static struct qcom_icc_node qhs_usb3_phy = { |
548 | .name = "qhs_usb3_phy" , |
549 | .id = SDX65_SLAVE_USB3_PHY_CFG, |
550 | .channels = 1, |
551 | .buswidth = 4, |
552 | }; |
553 | |
554 | static struct qcom_icc_node qns_aggre_noc = { |
555 | .name = "qns_aggre_noc" , |
556 | .id = SDX65_SLAVE_ANOC_SNOC, |
557 | .channels = 1, |
558 | .buswidth = 8, |
559 | .num_links = 1, |
560 | .links = { SDX65_MASTER_ANOC_SNOC }, |
561 | }; |
562 | |
563 | static struct qcom_icc_node qns_snoc_memnoc = { |
564 | .name = "qns_snoc_memnoc" , |
565 | .id = SDX65_SLAVE_SNOC_MEM_NOC_GC, |
566 | .channels = 1, |
567 | .buswidth = 16, |
568 | .num_links = 1, |
569 | .links = { SDX65_MASTER_SNOC_GC_MEM_NOC }, |
570 | }; |
571 | |
572 | static struct qcom_icc_node qxs_imem = { |
573 | .name = "qxs_imem" , |
574 | .id = SDX65_SLAVE_IMEM, |
575 | .channels = 1, |
576 | .buswidth = 8, |
577 | }; |
578 | |
579 | static struct qcom_icc_node srvc_snoc = { |
580 | .name = "srvc_snoc" , |
581 | .id = SDX65_SLAVE_SERVICE_SNOC, |
582 | .channels = 1, |
583 | .buswidth = 4, |
584 | }; |
585 | |
586 | static struct qcom_icc_node xs_pcie = { |
587 | .name = "xs_pcie" , |
588 | .id = SDX65_SLAVE_PCIE_0, |
589 | .channels = 1, |
590 | .buswidth = 8, |
591 | }; |
592 | |
593 | static struct qcom_icc_node xs_qdss_stm = { |
594 | .name = "xs_qdss_stm" , |
595 | .id = SDX65_SLAVE_QDSS_STM, |
596 | .channels = 1, |
597 | .buswidth = 4, |
598 | }; |
599 | |
600 | static struct qcom_icc_node xs_sys_tcu_cfg = { |
601 | .name = "xs_sys_tcu_cfg" , |
602 | .id = SDX65_SLAVE_TCU, |
603 | .channels = 1, |
604 | .buswidth = 8, |
605 | }; |
606 | |
607 | static struct qcom_icc_bcm bcm_ce0 = { |
608 | .name = "CE0" , |
609 | .keepalive = false, |
610 | .num_nodes = 1, |
611 | .nodes = { &qxm_crypto }, |
612 | }; |
613 | |
614 | static struct qcom_icc_bcm bcm_mc0 = { |
615 | .name = "MC0" , |
616 | .keepalive = true, |
617 | .num_nodes = 1, |
618 | .nodes = { &ebi }, |
619 | }; |
620 | |
621 | static struct qcom_icc_bcm bcm_pn0 = { |
622 | .name = "PN0" , |
623 | .keepalive = true, |
624 | .num_nodes = 26, |
625 | .nodes = { &qhm_snoc_cfg, |
626 | &qhs_aoss, |
627 | &qhs_apss, |
628 | &qhs_audio, |
629 | &qhs_blsp1, |
630 | &qhs_clk_ctl, |
631 | &qhs_crypto0_cfg, |
632 | &qhs_ddrss_cfg, |
633 | &qhs_ecc_cfg, |
634 | &qhs_imem_cfg, |
635 | &qhs_ipa, |
636 | &qhs_mss_cfg, |
637 | &qhs_pcie_parf, |
638 | &qhs_pdm, |
639 | &qhs_prng, |
640 | &qhs_qdss_cfg, |
641 | &qhs_qpic, |
642 | &qhs_sdc1, |
643 | &qhs_snoc_cfg, |
644 | &qhs_spmi_fetcher, |
645 | &qhs_spmi_vgi_coex, |
646 | &qhs_tcsr, |
647 | &qhs_tlmm, |
648 | &qhs_usb3, |
649 | &qhs_usb3_phy, |
650 | &srvc_snoc |
651 | }, |
652 | }; |
653 | |
654 | static struct qcom_icc_bcm bcm_pn1 = { |
655 | .name = "PN1" , |
656 | .keepalive = false, |
657 | .num_nodes = 1, |
658 | .nodes = { &xm_sdc1 }, |
659 | }; |
660 | |
661 | static struct qcom_icc_bcm bcm_pn2 = { |
662 | .name = "PN2" , |
663 | .keepalive = false, |
664 | .num_nodes = 2, |
665 | .nodes = { &qhm_audio, &qhm_spmi_fetcher1 }, |
666 | }; |
667 | |
668 | static struct qcom_icc_bcm bcm_pn3 = { |
669 | .name = "PN3" , |
670 | .keepalive = false, |
671 | .num_nodes = 2, |
672 | .nodes = { &qhm_blsp1, &qhm_qpic }, |
673 | }; |
674 | |
675 | static struct qcom_icc_bcm bcm_pn4 = { |
676 | .name = "PN4" , |
677 | .keepalive = false, |
678 | .num_nodes = 1, |
679 | .nodes = { &qxm_crypto }, |
680 | }; |
681 | |
682 | static struct qcom_icc_bcm bcm_sh0 = { |
683 | .name = "SH0" , |
684 | .keepalive = true, |
685 | .num_nodes = 1, |
686 | .nodes = { &qns_llcc }, |
687 | }; |
688 | |
689 | static struct qcom_icc_bcm bcm_sh1 = { |
690 | .name = "SH1" , |
691 | .keepalive = false, |
692 | .num_nodes = 1, |
693 | .nodes = { &qns_memnoc_snoc }, |
694 | }; |
695 | |
696 | static struct qcom_icc_bcm bcm_sh3 = { |
697 | .name = "SH3" , |
698 | .keepalive = false, |
699 | .num_nodes = 1, |
700 | .nodes = { &xm_apps_rdwr }, |
701 | }; |
702 | |
703 | static struct qcom_icc_bcm bcm_sn0 = { |
704 | .name = "SN0" , |
705 | .keepalive = true, |
706 | .num_nodes = 1, |
707 | .nodes = { &qns_snoc_memnoc }, |
708 | }; |
709 | |
710 | static struct qcom_icc_bcm bcm_sn1 = { |
711 | .name = "SN1" , |
712 | .keepalive = false, |
713 | .num_nodes = 1, |
714 | .nodes = { &qxs_imem }, |
715 | }; |
716 | |
717 | static struct qcom_icc_bcm bcm_sn2 = { |
718 | .name = "SN2" , |
719 | .keepalive = false, |
720 | .num_nodes = 1, |
721 | .nodes = { &xs_qdss_stm }, |
722 | }; |
723 | |
724 | static struct qcom_icc_bcm bcm_sn3 = { |
725 | .name = "SN3" , |
726 | .keepalive = false, |
727 | .num_nodes = 1, |
728 | .nodes = { &xs_sys_tcu_cfg }, |
729 | }; |
730 | |
731 | static struct qcom_icc_bcm bcm_sn5 = { |
732 | .name = "SN5" , |
733 | .keepalive = false, |
734 | .num_nodes = 1, |
735 | .nodes = { &xs_pcie }, |
736 | }; |
737 | |
738 | static struct qcom_icc_bcm bcm_sn6 = { |
739 | .name = "SN6" , |
740 | .keepalive = false, |
741 | .num_nodes = 2, |
742 | .nodes = { &qhm_qdss_bam, &xm_qdss_etr }, |
743 | }; |
744 | |
745 | static struct qcom_icc_bcm bcm_sn7 = { |
746 | .name = "SN7" , |
747 | .keepalive = false, |
748 | .num_nodes = 4, |
749 | .nodes = { &qnm_aggre_noc, &xm_pcie, &xm_usb3, &qns_aggre_noc }, |
750 | }; |
751 | |
752 | static struct qcom_icc_bcm bcm_sn8 = { |
753 | .name = "SN8" , |
754 | .keepalive = false, |
755 | .num_nodes = 1, |
756 | .nodes = { &qnm_memnoc }, |
757 | }; |
758 | |
759 | static struct qcom_icc_bcm bcm_sn9 = { |
760 | .name = "SN9" , |
761 | .keepalive = false, |
762 | .num_nodes = 1, |
763 | .nodes = { &qnm_memnoc_pcie }, |
764 | }; |
765 | |
766 | static struct qcom_icc_bcm bcm_sn10 = { |
767 | .name = "SN10" , |
768 | .keepalive = false, |
769 | .num_nodes = 2, |
770 | .nodes = { &qnm_ipa, &xm_ipa2pcie_slv }, |
771 | }; |
772 | |
773 | static struct qcom_icc_bcm * const mc_virt_bcms[] = { |
774 | &bcm_mc0, |
775 | }; |
776 | |
777 | static struct qcom_icc_node * const mc_virt_nodes[] = { |
778 | [MASTER_LLCC] = &llcc_mc, |
779 | [SLAVE_EBI1] = &ebi, |
780 | }; |
781 | |
782 | static const struct qcom_icc_desc sdx65_mc_virt = { |
783 | .nodes = mc_virt_nodes, |
784 | .num_nodes = ARRAY_SIZE(mc_virt_nodes), |
785 | .bcms = mc_virt_bcms, |
786 | .num_bcms = ARRAY_SIZE(mc_virt_bcms), |
787 | }; |
788 | |
789 | static struct qcom_icc_bcm * const mem_noc_bcms[] = { |
790 | &bcm_sh0, |
791 | &bcm_sh1, |
792 | &bcm_sh3, |
793 | }; |
794 | |
795 | static struct qcom_icc_node * const mem_noc_nodes[] = { |
796 | [MASTER_TCU_0] = &acm_tcu, |
797 | [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, |
798 | [MASTER_APPSS_PROC] = &xm_apps_rdwr, |
799 | [SLAVE_LLCC] = &qns_llcc, |
800 | [SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc, |
801 | [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie, |
802 | }; |
803 | |
804 | static const struct qcom_icc_desc sdx65_mem_noc = { |
805 | .nodes = mem_noc_nodes, |
806 | .num_nodes = ARRAY_SIZE(mem_noc_nodes), |
807 | .bcms = mem_noc_bcms, |
808 | .num_bcms = ARRAY_SIZE(mem_noc_bcms), |
809 | }; |
810 | |
811 | static struct qcom_icc_bcm * const system_noc_bcms[] = { |
812 | &bcm_ce0, |
813 | &bcm_pn0, |
814 | &bcm_pn1, |
815 | &bcm_pn2, |
816 | &bcm_pn3, |
817 | &bcm_pn4, |
818 | &bcm_sn0, |
819 | &bcm_sn1, |
820 | &bcm_sn2, |
821 | &bcm_sn3, |
822 | &bcm_sn5, |
823 | &bcm_sn6, |
824 | &bcm_sn7, |
825 | &bcm_sn8, |
826 | &bcm_sn9, |
827 | &bcm_sn10, |
828 | }; |
829 | |
830 | static struct qcom_icc_node * const system_noc_nodes[] = { |
831 | [MASTER_AUDIO] = &qhm_audio, |
832 | [MASTER_BLSP_1] = &qhm_blsp1, |
833 | [MASTER_QDSS_BAM] = &qhm_qdss_bam, |
834 | [MASTER_QPIC] = &qhm_qpic, |
835 | [MASTER_SNOC_CFG] = &qhm_snoc_cfg, |
836 | [MASTER_SPMI_FETCHER] = &qhm_spmi_fetcher1, |
837 | [MASTER_ANOC_SNOC] = &qnm_aggre_noc, |
838 | [MASTER_IPA] = &qnm_ipa, |
839 | [MASTER_MEM_NOC_SNOC] = &qnm_memnoc, |
840 | [MASTER_MEM_NOC_PCIE_SNOC] = &qnm_memnoc_pcie, |
841 | [MASTER_CRYPTO] = &qxm_crypto, |
842 | [MASTER_IPA_PCIE] = &xm_ipa2pcie_slv, |
843 | [MASTER_PCIE_0] = &xm_pcie, |
844 | [MASTER_QDSS_ETR] = &xm_qdss_etr, |
845 | [MASTER_SDCC_1] = &xm_sdc1, |
846 | [MASTER_USB3] = &xm_usb3, |
847 | [SLAVE_AOSS] = &qhs_aoss, |
848 | [SLAVE_APPSS] = &qhs_apss, |
849 | [SLAVE_AUDIO] = &qhs_audio, |
850 | [SLAVE_BLSP_1] = &qhs_blsp1, |
851 | [SLAVE_CLK_CTL] = &qhs_clk_ctl, |
852 | [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, |
853 | [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, |
854 | [SLAVE_ECC_CFG] = &qhs_ecc_cfg, |
855 | [SLAVE_IMEM_CFG] = &qhs_imem_cfg, |
856 | [SLAVE_IPA_CFG] = &qhs_ipa, |
857 | [SLAVE_CNOC_MSS] = &qhs_mss_cfg, |
858 | [SLAVE_PCIE_PARF] = &qhs_pcie_parf, |
859 | [SLAVE_PDM] = &qhs_pdm, |
860 | [SLAVE_PRNG] = &qhs_prng, |
861 | [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, |
862 | [SLAVE_QPIC] = &qhs_qpic, |
863 | [SLAVE_SDCC_1] = &qhs_sdc1, |
864 | [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, |
865 | [SLAVE_SPMI_FETCHER] = &qhs_spmi_fetcher, |
866 | [SLAVE_SPMI_VGI_COEX] = &qhs_spmi_vgi_coex, |
867 | [SLAVE_TCSR] = &qhs_tcsr, |
868 | [SLAVE_TLMM] = &qhs_tlmm, |
869 | [SLAVE_USB3] = &qhs_usb3, |
870 | [SLAVE_USB3_PHY_CFG] = &qhs_usb3_phy, |
871 | [SLAVE_ANOC_SNOC] = &qns_aggre_noc, |
872 | [SLAVE_SNOC_MEM_NOC_GC] = &qns_snoc_memnoc, |
873 | [SLAVE_IMEM] = &qxs_imem, |
874 | [SLAVE_SERVICE_SNOC] = &srvc_snoc, |
875 | [SLAVE_PCIE_0] = &xs_pcie, |
876 | [SLAVE_QDSS_STM] = &xs_qdss_stm, |
877 | [SLAVE_TCU] = &xs_sys_tcu_cfg, |
878 | }; |
879 | |
880 | static const struct qcom_icc_desc sdx65_system_noc = { |
881 | .nodes = system_noc_nodes, |
882 | .num_nodes = ARRAY_SIZE(system_noc_nodes), |
883 | .bcms = system_noc_bcms, |
884 | .num_bcms = ARRAY_SIZE(system_noc_bcms), |
885 | }; |
886 | |
887 | static const struct of_device_id qnoc_of_match[] = { |
888 | { .compatible = "qcom,sdx65-mc-virt" , |
889 | .data = &sdx65_mc_virt}, |
890 | { .compatible = "qcom,sdx65-mem-noc" , |
891 | .data = &sdx65_mem_noc}, |
892 | { .compatible = "qcom,sdx65-system-noc" , |
893 | .data = &sdx65_system_noc}, |
894 | { } |
895 | }; |
896 | MODULE_DEVICE_TABLE(of, qnoc_of_match); |
897 | |
898 | static struct platform_driver qnoc_driver = { |
899 | .probe = qcom_icc_rpmh_probe, |
900 | .remove_new = qcom_icc_rpmh_remove, |
901 | .driver = { |
902 | .name = "qnoc-sdx65" , |
903 | .of_match_table = qnoc_of_match, |
904 | .sync_state = icc_sync_state, |
905 | }, |
906 | }; |
907 | module_platform_driver(qnoc_driver); |
908 | |
909 | MODULE_DESCRIPTION("Qualcomm SDX65 NoC driver" ); |
910 | MODULE_LICENSE("GPL v2" ); |
911 | |