1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 */
6
7#include <linux/device.h>
8#include <linux/interconnect.h>
9#include <linux/interconnect-provider.h>
10#include <linux/module.h>
11#include <linux/of_platform.h>
12#include <dt-bindings/interconnect/qcom,sdx75.h>
13
14#include "bcm-voter.h"
15#include "icc-common.h"
16#include "icc-rpmh.h"
17#include "sdx75.h"
18
19static struct qcom_icc_node qpic_core_master = {
20 .name = "qpic_core_master",
21 .id = SDX75_MASTER_QPIC_CORE,
22 .channels = 1,
23 .buswidth = 4,
24 .num_links = 1,
25 .links = { SDX75_SLAVE_QPIC_CORE },
26};
27
28static struct qcom_icc_node qup0_core_master = {
29 .name = "qup0_core_master",
30 .id = SDX75_MASTER_QUP_CORE_0,
31 .channels = 1,
32 .buswidth = 4,
33 .num_links = 1,
34 .links = { SDX75_SLAVE_QUP_CORE_0 },
35};
36
37static struct qcom_icc_node qnm_cnoc = {
38 .name = "qnm_cnoc",
39 .id = SDX75_MASTER_CNOC_DC_NOC,
40 .channels = 1,
41 .buswidth = 4,
42 .num_links = 4,
43 .links = { SDX75_SLAVE_LAGG_CFG, SDX75_SLAVE_MCCC_MASTER,
44 SDX75_SLAVE_GEM_NOC_CFG, SDX75_SLAVE_SNOOP_BWMON },
45};
46
47static struct qcom_icc_node alm_sys_tcu = {
48 .name = "alm_sys_tcu",
49 .id = SDX75_MASTER_SYS_TCU,
50 .channels = 1,
51 .buswidth = 8,
52 .num_links = 2,
53 .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC },
54};
55
56static struct qcom_icc_node chm_apps = {
57 .name = "chm_apps",
58 .id = SDX75_MASTER_APPSS_PROC,
59 .channels = 1,
60 .buswidth = 16,
61 .num_links = 3,
62 .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC,
63 SDX75_SLAVE_MEM_NOC_PCIE_SNOC },
64};
65
66static struct qcom_icc_node qnm_gemnoc_cfg = {
67 .name = "qnm_gemnoc_cfg",
68 .id = SDX75_MASTER_GEM_NOC_CFG,
69 .channels = 1,
70 .buswidth = 4,
71 .num_links = 1,
72 .links = { SDX75_SLAVE_SERVICE_GEM_NOC },
73};
74
75static struct qcom_icc_node qnm_mdsp = {
76 .name = "qnm_mdsp",
77 .id = SDX75_MASTER_MSS_PROC,
78 .channels = 1,
79 .buswidth = 16,
80 .num_links = 3,
81 .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC,
82 SDX75_SLAVE_MEM_NOC_PCIE_SNOC },
83};
84
85static struct qcom_icc_node qnm_pcie = {
86 .name = "qnm_pcie",
87 .id = SDX75_MASTER_ANOC_PCIE_GEM_NOC,
88 .channels = 1,
89 .buswidth = 16,
90 .num_links = 2,
91 .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC },
92};
93
94static struct qcom_icc_node qnm_snoc_sf = {
95 .name = "qnm_snoc_sf",
96 .id = SDX75_MASTER_SNOC_SF_MEM_NOC,
97 .channels = 1,
98 .buswidth = 16,
99 .num_links = 3,
100 .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC,
101 SDX75_SLAVE_MEM_NOC_PCIE_SNOC },
102};
103
104static struct qcom_icc_node xm_gic = {
105 .name = "xm_gic",
106 .id = SDX75_MASTER_GIC,
107 .channels = 1,
108 .buswidth = 8,
109 .num_links = 1,
110 .links = { SDX75_SLAVE_LLCC },
111};
112
113static struct qcom_icc_node xm_ipa2pcie = {
114 .name = "xm_ipa2pcie",
115 .id = SDX75_MASTER_IPA_PCIE,
116 .channels = 1,
117 .buswidth = 8,
118 .num_links = 1,
119 .links = { SDX75_SLAVE_MEM_NOC_PCIE_SNOC },
120};
121
122static struct qcom_icc_node llcc_mc = {
123 .name = "llcc_mc",
124 .id = SDX75_MASTER_LLCC,
125 .channels = 1,
126 .buswidth = 4,
127 .num_links = 1,
128 .links = { SDX75_SLAVE_EBI1 },
129};
130
131static struct qcom_icc_node xm_pcie3_0 = {
132 .name = "xm_pcie3_0",
133 .id = SDX75_MASTER_PCIE_0,
134 .channels = 1,
135 .buswidth = 8,
136 .num_links = 1,
137 .links = { SDX75_SLAVE_ANOC_PCIE_GEM_NOC },
138};
139
140static struct qcom_icc_node xm_pcie3_1 = {
141 .name = "xm_pcie3_1",
142 .id = SDX75_MASTER_PCIE_1,
143 .channels = 1,
144 .buswidth = 8,
145 .num_links = 1,
146 .links = { SDX75_SLAVE_ANOC_PCIE_GEM_NOC },
147};
148
149static struct qcom_icc_node xm_pcie3_2 = {
150 .name = "xm_pcie3_2",
151 .id = SDX75_MASTER_PCIE_2,
152 .channels = 1,
153 .buswidth = 8,
154 .num_links = 1,
155 .links = { SDX75_SLAVE_ANOC_PCIE_GEM_NOC },
156};
157
158static struct qcom_icc_node qhm_audio = {
159 .name = "qhm_audio",
160 .id = SDX75_MASTER_AUDIO,
161 .channels = 1,
162 .buswidth = 4,
163 .num_links = 1,
164 .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF },
165};
166
167static struct qcom_icc_node qhm_gic = {
168 .name = "qhm_gic",
169 .id = SDX75_MASTER_GIC_AHB,
170 .channels = 1,
171 .buswidth = 4,
172 .num_links = 1,
173 .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF },
174};
175
176static struct qcom_icc_node qhm_pcie_rscc = {
177 .name = "qhm_pcie_rscc",
178 .id = SDX75_MASTER_PCIE_RSCC,
179 .channels = 1,
180 .buswidth = 4,
181 .num_links = 31,
182 .links = { SDX75_SLAVE_ETH0_CFG, SDX75_SLAVE_ETH1_CFG,
183 SDX75_SLAVE_AUDIO, SDX75_SLAVE_CLK_CTL,
184 SDX75_SLAVE_CRYPTO_0_CFG, SDX75_SLAVE_IMEM_CFG,
185 SDX75_SLAVE_IPA_CFG, SDX75_SLAVE_IPC_ROUTER_CFG,
186 SDX75_SLAVE_CNOC_MSS, SDX75_SLAVE_ICBDI_MVMSS_CFG,
187 SDX75_SLAVE_PCIE_0_CFG, SDX75_SLAVE_PCIE_1_CFG,
188 SDX75_SLAVE_PCIE_2_CFG, SDX75_SLAVE_PDM,
189 SDX75_SLAVE_PRNG, SDX75_SLAVE_QDSS_CFG,
190 SDX75_SLAVE_QPIC, SDX75_SLAVE_QUP_0,
191 SDX75_SLAVE_SDCC_1, SDX75_SLAVE_SDCC_4,
192 SDX75_SLAVE_SPMI_VGI_COEX, SDX75_SLAVE_TCSR,
193 SDX75_SLAVE_TLMM, SDX75_SLAVE_USB3,
194 SDX75_SLAVE_USB3_PHY_CFG, SDX75_SLAVE_DDRSS_CFG,
195 SDX75_SLAVE_SNOC_CFG, SDX75_SLAVE_PCIE_ANOC_CFG,
196 SDX75_SLAVE_IMEM, SDX75_SLAVE_QDSS_STM,
197 SDX75_SLAVE_TCU },
198};
199
200static struct qcom_icc_node qhm_qdss_bam = {
201 .name = "qhm_qdss_bam",
202 .id = SDX75_MASTER_QDSS_BAM,
203 .channels = 1,
204 .buswidth = 4,
205 .num_links = 1,
206 .links = { SDX75_SLAVE_A1NOC_CFG },
207};
208
209static struct qcom_icc_node qhm_qpic = {
210 .name = "qhm_qpic",
211 .id = SDX75_MASTER_QPIC,
212 .channels = 1,
213 .buswidth = 4,
214 .num_links = 1,
215 .links = { SDX75_SLAVE_A1NOC_CFG },
216};
217
218static struct qcom_icc_node qhm_qup0 = {
219 .name = "qhm_qup0",
220 .id = SDX75_MASTER_QUP_0,
221 .channels = 1,
222 .buswidth = 4,
223 .num_links = 1,
224 .links = { SDX75_SLAVE_A1NOC_CFG },
225};
226
227static struct qcom_icc_node qnm_aggre_noc = {
228 .name = "qnm_aggre_noc",
229 .id = SDX75_MASTER_ANOC_SNOC,
230 .channels = 1,
231 .buswidth = 8,
232 .num_links = 1,
233 .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF },
234};
235
236static struct qcom_icc_node qnm_gemnoc_cnoc = {
237 .name = "qnm_gemnoc_cnoc",
238 .id = SDX75_MASTER_GEM_NOC_CNOC,
239 .channels = 1,
240 .buswidth = 8,
241 .num_links = 32,
242 .links = { SDX75_SLAVE_ETH0_CFG, SDX75_SLAVE_ETH1_CFG,
243 SDX75_SLAVE_AUDIO, SDX75_SLAVE_CLK_CTL,
244 SDX75_SLAVE_CRYPTO_0_CFG, SDX75_SLAVE_IMEM_CFG,
245 SDX75_SLAVE_IPA_CFG, SDX75_SLAVE_IPC_ROUTER_CFG,
246 SDX75_SLAVE_CNOC_MSS, SDX75_SLAVE_ICBDI_MVMSS_CFG,
247 SDX75_SLAVE_PCIE_0_CFG, SDX75_SLAVE_PCIE_1_CFG,
248 SDX75_SLAVE_PCIE_2_CFG, SDX75_SLAVE_PCIE_RSC_CFG,
249 SDX75_SLAVE_PDM, SDX75_SLAVE_PRNG,
250 SDX75_SLAVE_QDSS_CFG, SDX75_SLAVE_QPIC,
251 SDX75_SLAVE_QUP_0, SDX75_SLAVE_SDCC_1,
252 SDX75_SLAVE_SDCC_4, SDX75_SLAVE_SPMI_VGI_COEX,
253 SDX75_SLAVE_TCSR, SDX75_SLAVE_TLMM,
254 SDX75_SLAVE_USB3, SDX75_SLAVE_USB3_PHY_CFG,
255 SDX75_SLAVE_DDRSS_CFG, SDX75_SLAVE_SNOC_CFG,
256 SDX75_SLAVE_PCIE_ANOC_CFG, SDX75_SLAVE_IMEM,
257 SDX75_SLAVE_QDSS_STM, SDX75_SLAVE_TCU },
258};
259
260static struct qcom_icc_node qnm_gemnoc_pcie = {
261 .name = "qnm_gemnoc_pcie",
262 .id = SDX75_MASTER_GEM_NOC_PCIE_SNOC,
263 .channels = 1,
264 .buswidth = 16,
265 .num_links = 3,
266 .links = { SDX75_SLAVE_PCIE_0, SDX75_SLAVE_PCIE_1,
267 SDX75_SLAVE_PCIE_2 },
268};
269
270static struct qcom_icc_node qnm_system_noc_cfg = {
271 .name = "qnm_system_noc_cfg",
272 .id = SDX75_MASTER_SNOC_CFG,
273 .channels = 1,
274 .buswidth = 4,
275 .num_links = 1,
276 .links = { SDX75_SLAVE_SERVICE_SNOC },
277};
278
279static struct qcom_icc_node qnm_system_noc_pcie_cfg = {
280 .name = "qnm_system_noc_pcie_cfg",
281 .id = SDX75_MASTER_PCIE_ANOC_CFG,
282 .channels = 1,
283 .buswidth = 4,
284 .num_links = 1,
285 .links = { SDX75_SLAVE_SERVICE_PCIE_ANOC },
286};
287
288static struct qcom_icc_node qxm_crypto = {
289 .name = "qxm_crypto",
290 .id = SDX75_MASTER_CRYPTO,
291 .channels = 1,
292 .buswidth = 8,
293 .num_links = 1,
294 .links = { SDX75_SLAVE_A1NOC_CFG },
295};
296
297static struct qcom_icc_node qxm_ipa = {
298 .name = "qxm_ipa",
299 .id = SDX75_MASTER_IPA,
300 .channels = 1,
301 .buswidth = 8,
302 .num_links = 1,
303 .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF },
304};
305
306static struct qcom_icc_node qxm_mvmss = {
307 .name = "qxm_mvmss",
308 .id = SDX75_MASTER_MVMSS,
309 .channels = 1,
310 .buswidth = 8,
311 .num_links = 1,
312 .links = { SDX75_SLAVE_A1NOC_CFG },
313};
314
315static struct qcom_icc_node xm_emac_0 = {
316 .name = "xm_emac_0",
317 .id = SDX75_MASTER_EMAC_0,
318 .channels = 1,
319 .buswidth = 8,
320 .num_links = 1,
321 .links = { SDX75_SLAVE_A1NOC_CFG },
322};
323
324static struct qcom_icc_node xm_emac_1 = {
325 .name = "xm_emac_1",
326 .id = SDX75_MASTER_EMAC_1,
327 .channels = 1,
328 .buswidth = 8,
329 .num_links = 1,
330 .links = { SDX75_SLAVE_A1NOC_CFG },
331};
332
333static struct qcom_icc_node xm_qdss_etr0 = {
334 .name = "xm_qdss_etr0",
335 .id = SDX75_MASTER_QDSS_ETR,
336 .channels = 1,
337 .buswidth = 8,
338 .num_links = 1,
339 .links = { SDX75_SLAVE_A1NOC_CFG },
340};
341
342static struct qcom_icc_node xm_qdss_etr1 = {
343 .name = "xm_qdss_etr1",
344 .id = SDX75_MASTER_QDSS_ETR_1,
345 .channels = 1,
346 .buswidth = 8,
347 .num_links = 1,
348 .links = { SDX75_SLAVE_A1NOC_CFG },
349};
350
351static struct qcom_icc_node xm_sdc1 = {
352 .name = "xm_sdc1",
353 .id = SDX75_MASTER_SDCC_1,
354 .channels = 1,
355 .buswidth = 8,
356 .num_links = 1,
357 .links = { SDX75_SLAVE_A1NOC_CFG },
358};
359
360static struct qcom_icc_node xm_sdc4 = {
361 .name = "xm_sdc4",
362 .id = SDX75_MASTER_SDCC_4,
363 .channels = 1,
364 .buswidth = 8,
365 .num_links = 1,
366 .links = { SDX75_SLAVE_A1NOC_CFG },
367};
368
369static struct qcom_icc_node xm_usb3 = {
370 .name = "xm_usb3",
371 .id = SDX75_MASTER_USB3_0,
372 .channels = 1,
373 .buswidth = 8,
374 .num_links = 1,
375 .links = { SDX75_SLAVE_A1NOC_CFG },
376};
377
378static struct qcom_icc_node qpic_core_slave = {
379 .name = "qpic_core_slave",
380 .id = SDX75_SLAVE_QPIC_CORE,
381 .channels = 1,
382 .buswidth = 4,
383 .num_links = 0,
384};
385
386static struct qcom_icc_node qup0_core_slave = {
387 .name = "qup0_core_slave",
388 .id = SDX75_SLAVE_QUP_CORE_0,
389 .channels = 1,
390 .buswidth = 4,
391 .num_links = 0,
392};
393
394static struct qcom_icc_node qhs_lagg = {
395 .name = "qhs_lagg",
396 .id = SDX75_SLAVE_LAGG_CFG,
397 .channels = 1,
398 .buswidth = 4,
399 .num_links = 0,
400};
401
402static struct qcom_icc_node qhs_mccc_master = {
403 .name = "qhs_mccc_master",
404 .id = SDX75_SLAVE_MCCC_MASTER,
405 .channels = 1,
406 .buswidth = 4,
407 .num_links = 0,
408};
409
410static struct qcom_icc_node qns_gemnoc = {
411 .name = "qns_gemnoc",
412 .id = SDX75_SLAVE_GEM_NOC_CFG,
413 .channels = 1,
414 .buswidth = 4,
415 .num_links = 0,
416};
417
418static struct qcom_icc_node qss_snoop_bwmon = {
419 .name = "qss_snoop_bwmon",
420 .id = SDX75_SLAVE_SNOOP_BWMON,
421 .channels = 1,
422 .buswidth = 4,
423 .num_links = 0,
424};
425
426static struct qcom_icc_node qns_gemnoc_cnoc = {
427 .name = "qns_gemnoc_cnoc",
428 .id = SDX75_SLAVE_GEM_NOC_CNOC,
429 .channels = 1,
430 .buswidth = 8,
431 .num_links = 1,
432 .links = { SDX75_MASTER_GEM_NOC_CNOC },
433};
434
435static struct qcom_icc_node qns_llcc = {
436 .name = "qns_llcc",
437 .id = SDX75_SLAVE_LLCC,
438 .channels = 1,
439 .buswidth = 16,
440 .num_links = 1,
441 .links = { SDX75_MASTER_LLCC },
442};
443
444static struct qcom_icc_node qns_pcie = {
445 .name = "qns_pcie",
446 .id = SDX75_SLAVE_MEM_NOC_PCIE_SNOC,
447 .channels = 1,
448 .buswidth = 16,
449 .num_links = 1,
450 .links = { SDX75_MASTER_GEM_NOC_PCIE_SNOC },
451};
452
453static struct qcom_icc_node srvc_gemnoc = {
454 .name = "srvc_gemnoc",
455 .id = SDX75_SLAVE_SERVICE_GEM_NOC,
456 .channels = 1,
457 .buswidth = 4,
458 .num_links = 0,
459};
460
461static struct qcom_icc_node ebi = {
462 .name = "ebi",
463 .id = SDX75_SLAVE_EBI1,
464 .channels = 1,
465 .buswidth = 4,
466 .num_links = 0,
467};
468
469static struct qcom_icc_node qns_pcie_gemnoc = {
470 .name = "qns_pcie_gemnoc",
471 .id = SDX75_SLAVE_ANOC_PCIE_GEM_NOC,
472 .channels = 1,
473 .buswidth = 16,
474 .num_links = 1,
475 .links = { SDX75_MASTER_ANOC_PCIE_GEM_NOC },
476};
477
478static struct qcom_icc_node ps_eth0_cfg = {
479 .name = "ps_eth0_cfg",
480 .id = SDX75_SLAVE_ETH0_CFG,
481 .channels = 1,
482 .buswidth = 4,
483 .num_links = 0,
484};
485
486static struct qcom_icc_node ps_eth1_cfg = {
487 .name = "ps_eth1_cfg",
488 .id = SDX75_SLAVE_ETH1_CFG,
489 .channels = 1,
490 .buswidth = 4,
491 .num_links = 0,
492};
493
494static struct qcom_icc_node qhs_audio = {
495 .name = "qhs_audio",
496 .id = SDX75_SLAVE_AUDIO,
497 .channels = 1,
498 .buswidth = 4,
499 .num_links = 0,
500};
501
502static struct qcom_icc_node qhs_clk_ctl = {
503 .name = "qhs_clk_ctl",
504 .id = SDX75_SLAVE_CLK_CTL,
505 .channels = 1,
506 .buswidth = 4,
507 .num_links = 0,
508};
509
510static struct qcom_icc_node qhs_crypto_cfg = {
511 .name = "qhs_crypto_cfg",
512 .id = SDX75_SLAVE_CRYPTO_0_CFG,
513 .channels = 1,
514 .buswidth = 4,
515 .num_links = 0,
516};
517
518static struct qcom_icc_node qhs_imem_cfg = {
519 .name = "qhs_imem_cfg",
520 .id = SDX75_SLAVE_IMEM_CFG,
521 .channels = 1,
522 .buswidth = 4,
523 .num_links = 0,
524};
525
526static struct qcom_icc_node qhs_ipa = {
527 .name = "qhs_ipa",
528 .id = SDX75_SLAVE_IPA_CFG,
529 .channels = 1,
530 .buswidth = 4,
531 .num_links = 0,
532};
533
534static struct qcom_icc_node qhs_ipc_router = {
535 .name = "qhs_ipc_router",
536 .id = SDX75_SLAVE_IPC_ROUTER_CFG,
537 .channels = 1,
538 .buswidth = 4,
539 .num_links = 0,
540};
541
542static struct qcom_icc_node qhs_mss_cfg = {
543 .name = "qhs_mss_cfg",
544 .id = SDX75_SLAVE_CNOC_MSS,
545 .channels = 1,
546 .buswidth = 4,
547 .num_links = 0,
548};
549
550static struct qcom_icc_node qhs_mvmss_cfg = {
551 .name = "qhs_mvmss_cfg",
552 .id = SDX75_SLAVE_ICBDI_MVMSS_CFG,
553 .channels = 1,
554 .buswidth = 4,
555 .num_links = 0,
556};
557
558static struct qcom_icc_node qhs_pcie0_cfg = {
559 .name = "qhs_pcie0_cfg",
560 .id = SDX75_SLAVE_PCIE_0_CFG,
561 .channels = 1,
562 .buswidth = 4,
563 .num_links = 0,
564};
565
566static struct qcom_icc_node qhs_pcie1_cfg = {
567 .name = "qhs_pcie1_cfg",
568 .id = SDX75_SLAVE_PCIE_1_CFG,
569 .channels = 1,
570 .buswidth = 4,
571 .num_links = 0,
572};
573
574static struct qcom_icc_node qhs_pcie2_cfg = {
575 .name = "qhs_pcie2_cfg",
576 .id = SDX75_SLAVE_PCIE_2_CFG,
577 .channels = 1,
578 .buswidth = 4,
579 .num_links = 0,
580};
581
582static struct qcom_icc_node qhs_pcie_rscc = {
583 .name = "qhs_pcie_rscc",
584 .id = SDX75_SLAVE_PCIE_RSC_CFG,
585 .channels = 1,
586 .buswidth = 4,
587 .num_links = 0,
588};
589
590static struct qcom_icc_node qhs_pdm = {
591 .name = "qhs_pdm",
592 .id = SDX75_SLAVE_PDM,
593 .channels = 1,
594 .buswidth = 4,
595 .num_links = 0,
596};
597
598static struct qcom_icc_node qhs_prng = {
599 .name = "qhs_prng",
600 .id = SDX75_SLAVE_PRNG,
601 .channels = 1,
602 .buswidth = 4,
603 .num_links = 0,
604};
605
606static struct qcom_icc_node qhs_qdss_cfg = {
607 .name = "qhs_qdss_cfg",
608 .id = SDX75_SLAVE_QDSS_CFG,
609 .channels = 1,
610 .buswidth = 4,
611 .num_links = 0,
612};
613
614static struct qcom_icc_node qhs_qpic = {
615 .name = "qhs_qpic",
616 .id = SDX75_SLAVE_QPIC,
617 .channels = 1,
618 .buswidth = 4,
619 .num_links = 0,
620};
621
622static struct qcom_icc_node qhs_qup0 = {
623 .name = "qhs_qup0",
624 .id = SDX75_SLAVE_QUP_0,
625 .channels = 1,
626 .buswidth = 4,
627 .num_links = 0,
628};
629
630static struct qcom_icc_node qhs_sdc1 = {
631 .name = "qhs_sdc1",
632 .id = SDX75_SLAVE_SDCC_1,
633 .channels = 1,
634 .buswidth = 4,
635 .num_links = 0,
636};
637
638static struct qcom_icc_node qhs_sdc4 = {
639 .name = "qhs_sdc4",
640 .id = SDX75_SLAVE_SDCC_4,
641 .channels = 1,
642 .buswidth = 4,
643 .num_links = 0,
644};
645
646static struct qcom_icc_node qhs_spmi_vgi_coex = {
647 .name = "qhs_spmi_vgi_coex",
648 .id = SDX75_SLAVE_SPMI_VGI_COEX,
649 .channels = 1,
650 .buswidth = 4,
651 .num_links = 0,
652};
653
654static struct qcom_icc_node qhs_tcsr = {
655 .name = "qhs_tcsr",
656 .id = SDX75_SLAVE_TCSR,
657 .channels = 1,
658 .buswidth = 4,
659 .num_links = 0,
660};
661
662static struct qcom_icc_node qhs_tlmm = {
663 .name = "qhs_tlmm",
664 .id = SDX75_SLAVE_TLMM,
665 .channels = 1,
666 .buswidth = 4,
667 .num_links = 0,
668};
669
670static struct qcom_icc_node qhs_usb3 = {
671 .name = "qhs_usb3",
672 .id = SDX75_SLAVE_USB3,
673 .channels = 1,
674 .buswidth = 4,
675 .num_links = 0,
676};
677
678static struct qcom_icc_node qhs_usb3_phy = {
679 .name = "qhs_usb3_phy",
680 .id = SDX75_SLAVE_USB3_PHY_CFG,
681 .channels = 1,
682 .buswidth = 4,
683 .num_links = 0,
684};
685
686static struct qcom_icc_node qns_a1noc = {
687 .name = "qns_a1noc",
688 .id = SDX75_SLAVE_A1NOC_CFG,
689 .channels = 1,
690 .buswidth = 8,
691 .num_links = 1,
692 .links = { SDX75_MASTER_ANOC_SNOC },
693};
694
695static struct qcom_icc_node qns_ddrss_cfg = {
696 .name = "qns_ddrss_cfg",
697 .id = SDX75_SLAVE_DDRSS_CFG,
698 .channels = 1,
699 .buswidth = 4,
700 .num_links = 1,
701 .links = { SDX75_MASTER_CNOC_DC_NOC },
702};
703
704static struct qcom_icc_node qns_gemnoc_sf = {
705 .name = "qns_gemnoc_sf",
706 .id = SDX75_SLAVE_SNOC_GEM_NOC_SF,
707 .channels = 1,
708 .buswidth = 16,
709 .num_links = 1,
710 .links = { SDX75_MASTER_SNOC_SF_MEM_NOC },
711};
712
713static struct qcom_icc_node qns_system_noc_cfg = {
714 .name = "qns_system_noc_cfg",
715 .id = SDX75_SLAVE_SNOC_CFG,
716 .channels = 1,
717 .buswidth = 4,
718 .num_links = 1,
719 .links = { SDX75_MASTER_SNOC_CFG },
720};
721
722static struct qcom_icc_node qns_system_noc_pcie_cfg = {
723 .name = "qns_system_noc_pcie_cfg",
724 .id = SDX75_SLAVE_PCIE_ANOC_CFG,
725 .channels = 1,
726 .buswidth = 4,
727 .num_links = 1,
728 .links = { SDX75_MASTER_PCIE_ANOC_CFG },
729};
730
731static struct qcom_icc_node qxs_imem = {
732 .name = "qxs_imem",
733 .id = SDX75_SLAVE_IMEM,
734 .channels = 1,
735 .buswidth = 8,
736 .num_links = 0,
737};
738
739static struct qcom_icc_node srvc_pcie_system_noc = {
740 .name = "srvc_pcie_system_noc",
741 .id = SDX75_SLAVE_SERVICE_PCIE_ANOC,
742 .channels = 1,
743 .buswidth = 4,
744 .num_links = 0,
745};
746
747static struct qcom_icc_node srvc_system_noc = {
748 .name = "srvc_system_noc",
749 .id = SDX75_SLAVE_SERVICE_SNOC,
750 .channels = 1,
751 .buswidth = 4,
752 .num_links = 0,
753};
754
755static struct qcom_icc_node xs_pcie_0 = {
756 .name = "xs_pcie_0",
757 .id = SDX75_SLAVE_PCIE_0,
758 .channels = 1,
759 .buswidth = 8,
760 .num_links = 0,
761};
762
763static struct qcom_icc_node xs_pcie_1 = {
764 .name = "xs_pcie_1",
765 .id = SDX75_SLAVE_PCIE_1,
766 .channels = 1,
767 .buswidth = 8,
768 .num_links = 0,
769};
770
771static struct qcom_icc_node xs_pcie_2 = {
772 .name = "xs_pcie_2",
773 .id = SDX75_SLAVE_PCIE_2,
774 .channels = 1,
775 .buswidth = 8,
776 .num_links = 0,
777};
778
779static struct qcom_icc_node xs_qdss_stm = {
780 .name = "xs_qdss_stm",
781 .id = SDX75_SLAVE_QDSS_STM,
782 .channels = 1,
783 .buswidth = 4,
784 .num_links = 0,
785};
786
787static struct qcom_icc_node xs_sys_tcu_cfg = {
788 .name = "xs_sys_tcu_cfg",
789 .id = SDX75_SLAVE_TCU,
790 .channels = 1,
791 .buswidth = 8,
792 .num_links = 0,
793};
794
795static struct qcom_icc_bcm bcm_ce0 = {
796 .name = "CE0",
797 .num_nodes = 1,
798 .nodes = { &qxm_crypto },
799};
800
801static struct qcom_icc_bcm bcm_cn0 = {
802 .name = "CN0",
803 .keepalive = true,
804 .num_nodes = 39,
805 .nodes = { &qhm_pcie_rscc, &qnm_gemnoc_cnoc,
806 &ps_eth0_cfg, &ps_eth1_cfg,
807 &qhs_audio, &qhs_clk_ctl,
808 &qhs_crypto_cfg, &qhs_imem_cfg,
809 &qhs_ipa, &qhs_ipc_router,
810 &qhs_mss_cfg, &qhs_mvmss_cfg,
811 &qhs_pcie0_cfg, &qhs_pcie1_cfg,
812 &qhs_pcie2_cfg, &qhs_pcie_rscc,
813 &qhs_pdm, &qhs_prng,
814 &qhs_qdss_cfg, &qhs_qpic,
815 &qhs_qup0, &qhs_sdc1,
816 &qhs_sdc4, &qhs_spmi_vgi_coex,
817 &qhs_tcsr, &qhs_tlmm,
818 &qhs_usb3, &qhs_usb3_phy,
819 &qns_ddrss_cfg, &qns_system_noc_cfg,
820 &qns_system_noc_pcie_cfg, &qxs_imem,
821 &srvc_pcie_system_noc, &srvc_system_noc,
822 &xs_pcie_0, &xs_pcie_1,
823 &xs_pcie_2, &xs_qdss_stm,
824 &xs_sys_tcu_cfg },
825};
826
827static struct qcom_icc_bcm bcm_mc0 = {
828 .name = "MC0",
829 .keepalive = true,
830 .num_nodes = 1,
831 .nodes = { &ebi },
832};
833
834static struct qcom_icc_bcm bcm_qp0 = {
835 .name = "QP0",
836 .num_nodes = 1,
837 .nodes = { &qpic_core_slave },
838};
839
840static struct qcom_icc_bcm bcm_qup0 = {
841 .name = "QUP0",
842 .keepalive = true,
843 .vote_scale = 1,
844 .num_nodes = 1,
845 .nodes = { &qup0_core_slave },
846};
847
848static struct qcom_icc_bcm bcm_sh0 = {
849 .name = "SH0",
850 .keepalive = true,
851 .num_nodes = 1,
852 .nodes = { &qns_llcc },
853};
854
855static struct qcom_icc_bcm bcm_sh1 = {
856 .name = "SH1",
857 .num_nodes = 10,
858 .nodes = { &alm_sys_tcu, &chm_apps,
859 &qnm_gemnoc_cfg, &qnm_mdsp,
860 &qnm_snoc_sf, &xm_gic,
861 &xm_ipa2pcie, &qns_gemnoc_cnoc,
862 &qns_pcie, &srvc_gemnoc },
863};
864
865static struct qcom_icc_bcm bcm_sn0 = {
866 .name = "SN0",
867 .keepalive = true,
868 .num_nodes = 1,
869 .nodes = { &qns_gemnoc_sf },
870};
871
872static struct qcom_icc_bcm bcm_sn1 = {
873 .name = "SN1",
874 .num_nodes = 21,
875 .nodes = { &xm_pcie3_0, &xm_pcie3_1,
876 &xm_pcie3_2, &qhm_audio,
877 &qhm_gic, &qhm_qdss_bam,
878 &qhm_qpic, &qhm_qup0,
879 &qnm_gemnoc_pcie, &qnm_system_noc_cfg,
880 &qnm_system_noc_pcie_cfg, &qxm_crypto,
881 &qxm_ipa, &qxm_mvmss,
882 &xm_emac_0, &xm_emac_1,
883 &xm_qdss_etr0, &xm_qdss_etr1,
884 &xm_sdc1, &xm_sdc4,
885 &xm_usb3 },
886};
887
888static struct qcom_icc_bcm bcm_sn2 = {
889 .name = "SN2",
890 .num_nodes = 2,
891 .nodes = { &qnm_aggre_noc, &qns_a1noc },
892};
893
894static struct qcom_icc_bcm bcm_sn4 = {
895 .name = "SN4",
896 .num_nodes = 2,
897 .nodes = { &qnm_pcie, &qns_pcie_gemnoc },
898};
899
900static struct qcom_icc_bcm * const clk_virt_bcms[] = {
901 &bcm_qp0,
902 &bcm_qup0,
903};
904
905static struct qcom_icc_node * const clk_virt_nodes[] = {
906 [MASTER_QPIC_CORE] = &qpic_core_master,
907 [MASTER_QUP_CORE_0] = &qup0_core_master,
908 [SLAVE_QPIC_CORE] = &qpic_core_slave,
909 [SLAVE_QUP_CORE_0] = &qup0_core_slave,
910};
911
912static const struct qcom_icc_desc sdx75_clk_virt = {
913 .nodes = clk_virt_nodes,
914 .num_nodes = ARRAY_SIZE(clk_virt_nodes),
915 .bcms = clk_virt_bcms,
916 .num_bcms = ARRAY_SIZE(clk_virt_bcms),
917};
918
919static struct qcom_icc_node * const dc_noc_nodes[] = {
920 [MASTER_CNOC_DC_NOC] = &qnm_cnoc,
921 [SLAVE_LAGG_CFG] = &qhs_lagg,
922 [SLAVE_MCCC_MASTER] = &qhs_mccc_master,
923 [SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
924 [SLAVE_SNOOP_BWMON] = &qss_snoop_bwmon,
925};
926
927static const struct qcom_icc_desc sdx75_dc_noc = {
928 .nodes = dc_noc_nodes,
929 .num_nodes = ARRAY_SIZE(dc_noc_nodes),
930};
931
932static struct qcom_icc_bcm * const gem_noc_bcms[] = {
933 &bcm_sh0,
934 &bcm_sh1,
935 &bcm_sn4,
936};
937
938static struct qcom_icc_node * const gem_noc_nodes[] = {
939 [MASTER_SYS_TCU] = &alm_sys_tcu,
940 [MASTER_APPSS_PROC] = &chm_apps,
941 [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
942 [MASTER_MSS_PROC] = &qnm_mdsp,
943 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
944 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
945 [MASTER_GIC] = &xm_gic,
946 [MASTER_IPA_PCIE] = &xm_ipa2pcie,
947 [SLAVE_GEM_NOC_CNOC] = &qns_gemnoc_cnoc,
948 [SLAVE_LLCC] = &qns_llcc,
949 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
950 [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
951};
952
953static const struct qcom_icc_desc sdx75_gem_noc = {
954 .nodes = gem_noc_nodes,
955 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
956 .bcms = gem_noc_bcms,
957 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
958};
959
960static struct qcom_icc_bcm * const mc_virt_bcms[] = {
961 &bcm_mc0,
962};
963
964static struct qcom_icc_node * const mc_virt_nodes[] = {
965 [MASTER_LLCC] = &llcc_mc,
966 [SLAVE_EBI1] = &ebi,
967};
968
969static const struct qcom_icc_desc sdx75_mc_virt = {
970 .nodes = mc_virt_nodes,
971 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
972 .bcms = mc_virt_bcms,
973 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
974};
975
976static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
977 &bcm_sn1,
978 &bcm_sn4,
979};
980
981static struct qcom_icc_node * const pcie_anoc_nodes[] = {
982 [MASTER_PCIE_0] = &xm_pcie3_0,
983 [MASTER_PCIE_1] = &xm_pcie3_1,
984 [MASTER_PCIE_2] = &xm_pcie3_2,
985 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gemnoc,
986};
987
988static const struct qcom_icc_desc sdx75_pcie_anoc = {
989 .nodes = pcie_anoc_nodes,
990 .num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
991 .bcms = pcie_anoc_bcms,
992 .num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
993};
994
995static struct qcom_icc_bcm * const system_noc_bcms[] = {
996 &bcm_ce0,
997 &bcm_cn0,
998 &bcm_sn0,
999 &bcm_sn1,
1000 &bcm_sn2,
1001};
1002
1003static struct qcom_icc_node * const system_noc_nodes[] = {
1004 [MASTER_AUDIO] = &qhm_audio,
1005 [MASTER_GIC_AHB] = &qhm_gic,
1006 [MASTER_PCIE_RSCC] = &qhm_pcie_rscc,
1007 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
1008 [MASTER_QPIC] = &qhm_qpic,
1009 [MASTER_QUP_0] = &qhm_qup0,
1010 [MASTER_ANOC_SNOC] = &qnm_aggre_noc,
1011 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1012 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1013 [MASTER_SNOC_CFG] = &qnm_system_noc_cfg,
1014 [MASTER_PCIE_ANOC_CFG] = &qnm_system_noc_pcie_cfg,
1015 [MASTER_CRYPTO] = &qxm_crypto,
1016 [MASTER_IPA] = &qxm_ipa,
1017 [MASTER_MVMSS] = &qxm_mvmss,
1018 [MASTER_EMAC_0] = &xm_emac_0,
1019 [MASTER_EMAC_1] = &xm_emac_1,
1020 [MASTER_QDSS_ETR] = &xm_qdss_etr0,
1021 [MASTER_QDSS_ETR_1] = &xm_qdss_etr1,
1022 [MASTER_SDCC_1] = &xm_sdc1,
1023 [MASTER_SDCC_4] = &xm_sdc4,
1024 [MASTER_USB3_0] = &xm_usb3,
1025 [SLAVE_ETH0_CFG] = &ps_eth0_cfg,
1026 [SLAVE_ETH1_CFG] = &ps_eth1_cfg,
1027 [SLAVE_AUDIO] = &qhs_audio,
1028 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1029 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto_cfg,
1030 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1031 [SLAVE_IPA_CFG] = &qhs_ipa,
1032 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1033 [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
1034 [SLAVE_ICBDI_MVMSS_CFG] = &qhs_mvmss_cfg,
1035 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1036 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
1037 [SLAVE_PCIE_2_CFG] = &qhs_pcie2_cfg,
1038 [SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rscc,
1039 [SLAVE_PDM] = &qhs_pdm,
1040 [SLAVE_PRNG] = &qhs_prng,
1041 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1042 [SLAVE_QPIC] = &qhs_qpic,
1043 [SLAVE_QUP_0] = &qhs_qup0,
1044 [SLAVE_SDCC_1] = &qhs_sdc1,
1045 [SLAVE_SDCC_4] = &qhs_sdc4,
1046 [SLAVE_SPMI_VGI_COEX] = &qhs_spmi_vgi_coex,
1047 [SLAVE_TCSR] = &qhs_tcsr,
1048 [SLAVE_TLMM] = &qhs_tlmm,
1049 [SLAVE_USB3] = &qhs_usb3,
1050 [SLAVE_USB3_PHY_CFG] = &qhs_usb3_phy,
1051 [SLAVE_A1NOC_CFG] = &qns_a1noc,
1052 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
1053 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1054 [SLAVE_SNOC_CFG] = &qns_system_noc_cfg,
1055 [SLAVE_PCIE_ANOC_CFG] = &qns_system_noc_pcie_cfg,
1056 [SLAVE_IMEM] = &qxs_imem,
1057 [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_system_noc,
1058 [SLAVE_SERVICE_SNOC] = &srvc_system_noc,
1059 [SLAVE_PCIE_0] = &xs_pcie_0,
1060 [SLAVE_PCIE_1] = &xs_pcie_1,
1061 [SLAVE_PCIE_2] = &xs_pcie_2,
1062 [SLAVE_QDSS_STM] = &xs_qdss_stm,
1063 [SLAVE_TCU] = &xs_sys_tcu_cfg,
1064};
1065
1066static const struct qcom_icc_desc sdx75_system_noc = {
1067 .nodes = system_noc_nodes,
1068 .num_nodes = ARRAY_SIZE(system_noc_nodes),
1069 .bcms = system_noc_bcms,
1070 .num_bcms = ARRAY_SIZE(system_noc_bcms),
1071};
1072
1073static const struct of_device_id qnoc_of_match[] = {
1074 { .compatible = "qcom,sdx75-clk-virt", .data = &sdx75_clk_virt },
1075 { .compatible = "qcom,sdx75-dc-noc", .data = &sdx75_dc_noc },
1076 { .compatible = "qcom,sdx75-gem-noc", .data = &sdx75_gem_noc },
1077 { .compatible = "qcom,sdx75-mc-virt", .data = &sdx75_mc_virt },
1078 { .compatible = "qcom,sdx75-pcie-anoc", .data = &sdx75_pcie_anoc },
1079 { .compatible = "qcom,sdx75-system-noc", .data = &sdx75_system_noc },
1080 { }
1081};
1082MODULE_DEVICE_TABLE(of, qnoc_of_match);
1083
1084static struct platform_driver qnoc_driver = {
1085 .probe = qcom_icc_rpmh_probe,
1086 .remove_new = qcom_icc_rpmh_remove,
1087 .driver = {
1088 .name = "qnoc-sdx75",
1089 .of_match_table = qnoc_of_match,
1090 .sync_state = icc_sync_state,
1091 },
1092};
1093
1094static int __init qnoc_driver_init(void)
1095{
1096 return platform_driver_register(&qnoc_driver);
1097}
1098core_initcall(qnoc_driver_init);
1099
1100static void __exit qnoc_driver_exit(void)
1101{
1102 platform_driver_unregister(&qnoc_driver);
1103}
1104module_exit(qnoc_driver_exit);
1105
1106MODULE_DESCRIPTION("SDX75 NoC driver");
1107MODULE_LICENSE("GPL");
1108

source code of linux/drivers/interconnect/qcom/sdx75.c